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xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd
| 1 | 7,603 |
-- $Id: sys_tst_serloop1_n3.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n3 - syn
-- Description: Tester serial link for nexys3 (serport_1clock case)
--
-- Dependencies: genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serport.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop1_n3;
architecture syn of sys_tst_serloop1_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 8,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
|
gpl-2.0
|
8920eb731e1c604d28681b2f3a102ddf
| 0.491385 | 3.336112 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd
| 1 | 5,349 |
-- $Id: sys_tst_snhumanio_n2.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n2 - syn
-- Description: snhumanio tester design for nexys2
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 410 13.1 O40d xc3s1200e-4 149 207 - 144 t 10.2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.3 update O_FLA_CE_N usage
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n2 is -- top level
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end sys_tst_snhumanio_n2;
architecture syn of sys_tst_snhumanio_n2 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
O_CLKSYS <= CLK;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
gpl-2.0
|
57f567035553d3621bff371d5649cde4
| 0.492802 | 3.439871 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
uniaxial_accelerometer/testbench_02.vhd
| 1 | 11,812 |
--*****************************************************************************
--*****************************************************************************
-- Model: testbench for a uniaxial MEMS accelerometer accelZa_02.vhd in hAMSter
--
--
-- Author: <[email protected]>
-- Date: 30.09.2021
-- Library dependencies:
-- accelZa_02.vhd - VHDL-AMS generated code from ANSYS for hAMSter
--
-- https://github.com/Kolchuzhin/LMGT_MEMS_component_library/tree/master/uniaxial_accelerometer
-------------------------------------------------------------------------------
-- parameters, uMKSV units
--
-- loading cases
-- 0. static mechanical test: az_input
-- 10. static mechanical test, constant modal forces
-- 11. mechanical test: ramp/sweep
-- 12. mechanical test: sin/chirp
-- 13. mechanical test: puls
-- 20. static electrical test: dc
-- 21. electrical test: ramp/sweep, pull-in
-- 22. electrical test: chirp
-- 23. electrical test: puls
--
--
--
-- Damping: modal quality factors qm_i in accelZa_02.vhd
--
-------------------------------------------------------------------------------
-- Euler solver: time=5m; step=200n *** 2021-07-27
-------------------------------------------------------------------------------
-- ID: testbench_02.vhd
-- ver. 0.22 02.08.2021 8 master nodes, az_input
-- ver. 0.30 29.09.2021 GitHuB realize
-- ver. 0.31 30.09.2021 more loading cases
--*****************************************************************************
--*****************************************************************************
use work.electromagnetic_system.all;
use work.all;
library ieee;
use ieee.math_real.all;
entity testbench is
end;
architecture behav of testbench is
terminal struc1_ext,struc2_ext: translational; -- modal dof
terminal lagrange1_ext,lagrange2_ext,lagrange3_ext,lagrange4_ext,lagrange5_ext,lagrange6_ext,lagrange7_ext,lagrange8_ext:translational; --
terminal master1_ext,master2_ext,master3_ext,master4_ext,master5_ext,master6_ext,master7_ext,master8_ext:translational; --
terminal elec1_ext,elec2_ext,elec3_ext: electrical; --
-- Modal displacement
quantity q_ext1 across fm_ext1 through struc1_ext; -- modal amplitude 1 (mode 1)
quantity q_ext2 across fm_ext2 through struc2_ext; -- modal amplitude 2 (mode 5)
-- Lagrangian multipler
quantity p_ext1 across r_ext1 through lagrange1_ext;
quantity p_ext2 across r_ext2 through lagrange2_ext;
quantity p_ext3 across r_ext3 through lagrange3_ext;
quantity p_ext4 across r_ext4 through lagrange4_ext;
quantity p_ext5 across r_ext5 through lagrange5_ext;
quantity p_ext6 across r_ext6 through lagrange6_ext;
quantity p_ext7 across r_ext7 through lagrange7_ext;
quantity p_ext8 across r_ext8 through lagrange8_ext;
-- Nodal displacement
quantity u_ext1 across f_ext1 through master1_ext; -- nodal amplitude 1
quantity u_ext2 across f_ext2 through master2_ext; -- nodal amplitude 2
quantity u_ext3 across f_ext3 through master3_ext; -- nodal amplitude 3
quantity u_ext4 across f_ext4 through master4_ext; -- nodal amplitude 4
quantity u_ext5 across f_ext5 through master5_ext; -- nodal amplitude 5
quantity u_ext6 across f_ext6 through master6_ext; -- nodal amplitude 6
quantity u_ext7 across f_ext7 through master7_ext; -- nodal amplitude 7
quantity u_ext8 across f_ext8 through master8_ext; -- nodal amplitude 8
-- Electrical ports
quantity v_ext1 across i_ext1 through elec1_ext; -- conductor 1
quantity v_ext2 across i_ext2 through elec2_ext; -- conductor 2
quantity v_ext3 across i_ext3 through elec3_ext; -- conductor 3
quantity az_input: real;
constant digital_delay:time:=200.0 ns; -- digital time step size for matrix update == analog time step
-- constant az_input:real:=1.0*10.0;
constant t_end:real:=5.0E-03;
constant dt:real:=2.0E-07; -- time step
constant ac_value:real:= 1.0;
constant dc_value:real:= 1.1; -- V23_pullin=1.085V (ANSYS) / gap=1.8
-- puls
constant t1:real:= 0.3E-03;
constant t2:real:= 1.0E-03; -- 5.0E-06
-- chirp
constant fm_1:real:= 1205.3; -- mode1 frequency
constant fm_2:real:= 15539.0; -- mode5 frequency
constant f_begin:real:= 1205.3*0.1; -- begin of frequency sweep
constant f_end:real:= 1205.3*7.0; -- end of frequency sweep
constant fm1_test:real:= 0.2716; -- f=k*u => u=f/k
constant fm2_test:real:= 76.516;
-- loading cases
-- constant key_load:integer:= 0; -- static mechanical test: az_input
-- constant key_load:integer:=10; -- static mechanical test: constant modal forces
-- constant key_load:integer:=11; -- mechanical test: ramp/sweep
-- constant key_load:integer:=12; -- mechanical test: sin/chirp
-- constant key_load:integer:=13; -- mechanical test: puls
-- constant key_load:integer:=20; -- static electrical test: dc
constant key_load:integer:=21; -- electrical test: ramp/sweep, pull-in
-- constant key_load:integer:=22; -- electrical test: chirp
-- constant key_load:integer:=23; -- electrical test: puls
begin
-- Loads
if key_load = 0 use -- static mechanical test: az_input
az_input == 2.0;
--az_input == 10.0/t_end*now;
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==0.0; -- external modal force 1
fm_ext2==0.0; -- external modal force 2
-- ANSYS: az=2.0*g => Uzmax=0.117083um (mn4) Uzmin=-0.162066um (mn2)
--
-- mn3 o---------------o mn4
-- | |
-- | |
-- | |
-- | movable |
-- | electrode |
-- | |
-- | |
-- | cond3 |
-- mn1 o---------------o mn2
--(mn5) (mn6)
end use;
if key_load = 10 use -- static mechanical test: modal forces
az_input == 0.0;
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==fm1_test; -- external modal force 1: fm_1=km_1 => q_1=1
fm_ext2==fm2_test; -- external modal force 2: fm_2=km_2 => q_2=1
end use;
if key_load = 11 use -- ramp/sweep
az_input == 0.0;
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==fm1_test/t_end/1.0*now;
fm_ext2==fm2_test/t_end/1.0*now;
end use;
if key_load = 12 use -- sin/chirp
az_input == 0.0;
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==0.0 + fm1_test*sin(2.0*3.14*(f_begin + (f_end-f_begin)/t_end*now) * now);
fm_ext2==0.0;
end use;
if key_load = 13 use -- puls
az_input == 0.0;
v_ext1==0.0;
v_ext2==0.0;
fm_ext2==0.0;
if now <= t1-dt use
fm_ext1 == 0.0;
end use;
if now > t1-dt and now <= t1 use
fm_ext1 == 0.0;
end use;
if now > t1 and now <= t2 use
fm_ext1 == fm1_test*0.2;
end use;
if now > t2 and now <= t2+dt use
fm_ext1 == 0.0;
end use;
if now > t2+dt use
fm_ext1 == 0.0;
end use;
end use;
if key_load = 20 use -- static electrical
az_input == 0.0;
v_ext1== 0.5;
v_ext2== 0.0; -- ground electrode
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 21 use -- ramp/sweep
az_input == 0.0;
v_ext2 == dc_value/t_end*now;
i_ext1== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 22 use -- chirp
az_input == 0.0;
v_ext1 == dc_value*0.1 + ac_value*sin(2.0*3.14*(f_begin + (f_end-f_begin)/t_end*now) * now);
v_ext2== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 23 use -- puls
az_input == 0.0;
if now <= t1-dt use
v_ext1 == 0.0;
end use;
if now > t1-dt and now <= t1 use
v_ext1 == 0.0;
end use;
if now > t1 and now <= t2 use
v_ext1 == dc_value*0.1;
end use;
if now > t2 and now <= t2+dt use
v_ext1 == 0.0;
end use;
if now > t2+dt use
v_ext1 == 0.0;
end use;
v_ext2== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
-- BCs:
--i_ext3==0.0; -- floating movable plate
v_ext3==0.0; -- grounded movable plate
--fm_ext1==0.0; -- external modal force 1
--fm_ext2==0.0; -- external modal force 2
-- Lagrangian ports: p/r
r_ext1==0.0; -- must be zero
r_ext2==0.0; -- must be zero
r_ext3==0.0; -- must be zero
r_ext4==0.0; -- must be zero
r_ext5==0.0; -- must be zero
r_ext6==0.0; -- must be zero
r_ext7==0.0; -- must be zero
r_ext8==0.0; -- must be zero
-- nodal ports: u/f
f_ext1==0.0; -- external nodal force on master node 1
f_ext2==0.0; -- external nodal force on master node 2
f_ext3==0.0; -- external nodal force on master node 3
f_ext4==0.0; -- external nodal force on master node 4
f_ext5==0.0; -- external nodal force on master node 5
f_ext6==0.0; -- external nodal force on master node 6
f_ext7==0.0; -- external nodal force on master node 7
f_ext8==0.0; -- external nodal force on master node 8
-------------------------------------------------------------------------------
--
-- Modal ports
--
-- q1 q2
-- o o
-- | |
-- Lagrangian ports o------o---------o------o Nodal ports: 5 master nodes
-- | |
-- r_ext1=0 ->>- p1 o---o o---o u1 -<<- f_ext1=0
-- | element: accelZa_02 |
-- p2 o---o o---o u2 -<<- f_ext2=0
-- | |
-- p3 o---o o---o u3 -<<- f_ext3=0
-- | |
-- p4 o---o o---o u4 -<<- f_ext4=0
-- | |
-- p5 o---o o---o u5 -<<- f_ext5=0
-- | |
-- p6 o---o o---o u6 -<<- f_ext6=0
-- | |
-- p7 o---o o---o u7 -<<- f_ext7=0
-- | |
-- p8 o---o o---o u8 -<<- f_ext8=0
-- | |
-- o------o----o----o------o
-- | | | \
-- o | o \
-- v1_ext | v2_ext=0 o az_input
-- |
-- o v3_ext=0 (plate)
--
-- Electrical ports
--
-- ASCII-Schematic of the ROM component for uniaxial MEMS accelerometer: accelZa_02
-------------------------------------------------------------------------------
ROM_element:
entity accelZa_02(ROM)
generic map (digital_delay)
port map (az_input,
struc1_ext,struc2_ext,
lagrange1_ext,lagrange2_ext,lagrange3_ext,lagrange4_ext,lagrange5_ext,lagrange6_ext,lagrange7_ext,lagrange8_ext,
master1_ext,master2_ext,master3_ext,master4_ext,master5_ext,master6_ext,master7_ext,master8_ext,
elec1_ext,elec2_ext,elec3_ext);
end;
-------------------------------------------------------------------------------
|
mit
|
64188511a75699f7344749169bce9f90
| 0.481036 | 3.19935 | false | true | false | false |
hdlguy/vivado_tcl
|
source/testbench/chirp_gen_tb.vhd
| 1 | 944 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity chirp_gen_tb is
generic(
in_width : natural := 8);
end entity chirp_gen_tb;
architecture rtl of chirp_gen_tb is
--
signal clk : std_logic;
signal reset : std_logic;
signal cos : std_logic_vector(7 downto 0);
signal sin : std_logic_vector(7 downto 0);
--
constant clk_period : time := 10 ns;
--
begin
stim_proc:process
begin
reset <= '1';
wait for clk_period*4;
reset <= '0';
wait;
end process;
uut: entity work.chirp_gen
port map (
clk => clk,
reset => reset,
cos => cos,
sin => sin);
clk_proc:process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
end architecture rtl;
|
gpl-3.0
|
e7a1fb8c2b6d0e0f403bd6f4dba49e65
| 0.505297 | 3.589354 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL source files/Position_INT_to_BCD_decoder.vhd
| 1 | 17,993 |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
--
-- File: Position_INT_to_BCD_decoder.vhd
-- File history:
-- <2.0>: <02/04/2015>: <Updates integer and fractional position automatically. Send codes to pendant>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <receive data in integer form and form BCD code for UART transmitter>
-- BCD data format is commonly used to show data on LCD or 7-segment displays
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--
--------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Position_INT_to_BCD_decoder is
GENERIC(
d_width : INTEGER := 24; -- data width
counter_width : INTEGER := 11 -- position update frequency
);
-- 01bit counter -> 51 us period clock 19,5 kHz
-- 02bit counter -> 102 us period clock 9,75 kHz
-- 03bit counter -> 204 us period clock 4,8 kHz
-- 04bit counter -> 409 us period clock 2,4 kHz
-- 05bit counter -> 820 us period clock 1,2 kHz
-- 06bit counter -> 1.6 ms period clock 610 Hz
-- 07bit counter -> 3.2 ms period clock 305 Hz
-- 08bit counter -> 6.5 ms period clock 152 Hz
-- 09bit counter -> 13 ms period clock 76 Hz
-- 10bit counter -> 26 ms period clock 38 Hz
-- 11bit counter -> 52 ms period clock 19 Hz
-- 12bit counter -> 104 ms period clock 9,5 Hz
-- 13bit counter -> 209 ms period clock 4,75 Hz
-- 14bit counter -> 419 ms period clock 2,35 Hz
-- 15bit counter -> 838 ms period clock 1,2 Hz
-- 16bit counter -> 1,67 s period clock 0,6 Hz
port (
RESET_N : in std_logic; -- RESET. Active low.
SCLK_IN : in std_logic; -- External SCLK 50 Mhz
SCLK_LF_IN : in std_logic; -- External SCLK 10 Mhz
SCLK_KHz_IN : in std_logic; -- External SCLK xx hz
Latch_data_IN : in std_logic; -- latch new position data input
Data_ready_IN : in std_logic; -- from PMAC_block. if '1' - data is ready
Pos_update_request : in std_logic; -- from PMAC_block. if '1' - send new position
Update_freq : in std_logic; -- from PMAC_block.
X_Pos_Int_in : in std_logic_vector(d_width-1 downto 0); -- X position (int)
X_pos_Fract_in : in std_logic_vector(d_width-1 downto 0); -- X position (fract)
Y_Pos_Int_in : in std_logic_vector(d_width-1 downto 0); -- Y position (int)
Y_pos_Fract_in : in std_logic_vector(d_width-1 downto 0); -- Y position (fract)
Z_Pos_Int_in : in std_logic_vector(d_width-1 downto 0); -- Z position (int)
Z_pos_Fract_in : in std_logic_vector(d_width-1 downto 0); -- Z position (fract)
A4_Pos_Int_in : in std_logic_vector(d_width-1 downto 0); -- 4 position (int)
A4_pos_Fract_in : in std_logic_vector(d_width-1 downto 0); -- 4 position (fract)
active_axis : in std_logic_vector(3 downto 0); -- shows active axis
UART_Send_Data : out std_logic; -- if '1' - send position via UART
Data_ready_out : out std_logic; -- decoding finished
Position_Tx_gate : out std_logic; -- gate for UART Tx registers
Position_to_decode : out std_logic_vector(13 downto 0); -- position to be decoded
Pos_Int_dig12_out : out std_logic_vector(7 downto 0); -- position int digits 1 & 2
Pos_Int_dig34_out : out std_logic_vector(7 downto 0); -- position int digits 3 & 4
Pos_Int_dig56_out : out std_logic_vector(7 downto 0); -- position int digits 5 & 6
Pos_Fract_dig12_out : out std_logic_vector(7 downto 0); -- position fract digits 1 & 2
Pos_Fract_dig34_out : out std_logic_vector(7 downto 0) -- position fract digits 3 & 4
);
end Position_INT_to_BCD_decoder;
architecture a_Position of Position_INT_to_BCD_decoder is
-- signal, component etc. declarations
signal Latch_data: std_logic; -- combined inputs to decide when to latch new position data
signal New_data_available : std_logic; -- if '1' - current data /= previous data
signal update_count: std_logic; -- time-based position update (long signal)
signal Latch_data_timer_imp: std_logic; -- time-based position update (impulse)
signal clk_divider : std_logic_vector(counter_width-1 downto 0); -- clock divider
signal Data_ready_out_R: std_logic; -- data is ready
signal Position_Tx_gate_R: std_logic; -- latch BCD position data in UART Tx registers
signal UART_Send_Data_R: std_logic; -- will be used to generate UART write impulse
-- current position
signal Pos_Sign_code_R: std_logic_vector(3 downto 0); -- int position sign
signal Pos_Int_dig12_R : std_logic_vector(7 downto 0); -- int position digits 1&2 (sign)
signal Pos_Int_dig34_R : std_logic_vector(7 downto 0); -- int position digits 3&4
signal Pos_Int_dig5_R : std_logic_vector(3 downto 0); -- int position digits 5
signal Pos_Int_dig6_R : std_logic_vector(3 downto 0); -- int position digits 6
signal Pos_Fract_dig12_R : std_logic_vector(7 downto 0); -- fract position digits 1&2
signal Pos_Fract_dig34_R : std_logic_vector(7 downto 0); -- fract position digits 3&4
--previous position
signal Prev_Pos_Int_dig12_R : std_logic_vector(7 downto 0); -- int position digits 1&2
signal Prev_Pos_Int_dig34_R : std_logic_vector(7 downto 0); -- int position digits 3&4
signal Prev_Pos_Int_dig5_R : std_logic_vector(3 downto 0); -- int position digits 5
signal Prev_Pos_Fract_dig12_R : std_logic_vector(7 downto 0); -- fract position digits 1&2
signal Prev_Pos_Fract_dig34_R : std_logic_vector(7 downto 0); -- fract position digits 3&4
-- comparison results
signal Comp_Pos_Int_dig12 : std_logic; -- int position digits 1
signal Comp_Pos_Int_dig34 : std_logic; -- int position digits 3&4
signal Comp_Pos_Int_dig5 : std_logic; -- int position digits 5
signal Comp_Pos_Fract_dig12 : std_logic; -- fract position digits 1&2
signal Comp_Pos_Fract_dig34 : std_logic; -- fract position digits 3&4
signal X_Pos_Int_R : std_logic_vector(d_width-1 downto 0); -- X position (int)
signal X_pos_Fract_R : std_logic_vector(d_width-1 downto 0); -- X position (fract)
signal Y_Pos_Int_R : std_logic_vector(d_width-1 downto 0); -- Y position (int)
signal Y_pos_Fract_R : std_logic_vector(d_width-1 downto 0); -- Y position (fract)
signal Z_Pos_Int_R : std_logic_vector(d_width-1 downto 0); -- Z position (int)
signal Z_pos_Fract_R : std_logic_vector(d_width-1 downto 0); -- Z position (fract)
signal A4_Pos_Int_R : std_logic_vector(d_width-1 downto 0); -- 4 position (int)
signal A4_pos_Fract_R :std_logic_vector(d_width-1 downto 0); -- 4 position (fract)
signal Position_sign_R : std_logic; -- sign of position ( 0 => "+", 1 => "-")
signal Position_int_R : std_logic_vector(13 downto 0); -- input code for 5 digit BCD decoder (int part of position)
signal Position_fract_R : std_logic_vector(13 downto 0); -- input code for 4 digit BCD decoder (fract part of position)
--signal pos_tenthousands_R : std_logic_vector(3 downto 0); -- BCD code for "thousands" digit (int part)
signal pos_thousands_R : std_logic_vector(3 downto 0); -- BCD code for "thousands" digit (int part)
signal pos_hundreds_R : std_logic_vector(3 downto 0); -- BCD code for "hundreds" digit (int part)
signal pos_tens_R : std_logic_vector(3 downto 0); -- BCD code for "tens" digit (int part)
signal pos_ones_R : std_logic_vector(3 downto 0); -- BCD code for "ones" digit (int part)
signal pos_fr_thousands_R : std_logic_vector(3 downto 0); -- BCD code for "thousands" digit (fract part)
signal pos_fr_hundreds_R : std_logic_vector(3 downto 0); -- BCD code for "hundreds" digit (fract part)
signal pos_fr_tens_R : std_logic_vector(3 downto 0); -- BCD code for "tens" digit (fract part)
signal pos_fr_ones_R : std_logic_vector(3 downto 0); -- BCD code for "ones" digit (fract part)
component impulse_gen_N_2cycle
port (
RESET_N :in std_logic; -- reset
IN_SIGNAL :in std_logic; -- input signal
IN_CLK :in std_logic; -- input clock signal
OUT_SIGNAL_P :out std_logic; -- output impluse Active High
OUT_SIGNAL_N :out std_logic -- output impluse Active Low
);
end component;
component bcd_4dig
Port (
number : in std_logic_vector (13 downto 0);
thousands : out std_logic_vector (3 downto 0);
hundreds : out std_logic_vector (3 downto 0);
tens : out std_logic_vector (3 downto 0);
ones : out std_logic_vector (3 downto 0)
);
end component;
component InEquality_comparator_8bit is
port( DataA : in std_logic_vector(7 downto 0);
DataB : in std_logic_vector(7 downto 0);
ANEB : out std_logic
);
end component;
component InEquality_comparator_4bit is
port( DataA : in std_logic_vector(3 downto 0);
DataB : in std_logic_vector(3 downto 0);
ANEB : out std_logic
);
end component;
begin
-- wiring outputs;
Data_ready_out <= Data_ready_out_R;
Position_Tx_gate <= Position_Tx_gate_R;
UART_Send_Data <= UART_Send_Data_R;
Pos_Int_dig12_out <= Pos_Int_dig12_R;
Pos_Int_dig34_out <= Pos_Int_dig34_R;
Pos_Int_dig56_out(7 downto 4) <= Pos_Int_dig5_R;
Pos_Int_dig56_out(3 downto 0) <= Pos_Int_dig6_R;
Pos_Fract_dig12_out <= Pos_Fract_dig12_R;
Pos_Fract_dig34_out <= Pos_Fract_dig34_R;
Position_to_decode <= Position_int_R;
-- assigning signals
Latch_data <= Latch_data_IN or Latch_data_timer_imp; -- may insert additional signals to start position decoding and transmission
New_data_available <= Comp_Pos_Int_dig12 or Comp_Pos_Int_dig34 or Comp_Pos_Int_dig5 or Comp_Pos_Fract_dig12 or Comp_Pos_Fract_dig34;
\UART_Tx_Gate_impulse_gen1\ : impulse_gen_N_2cycle -- generate signal to latch data in UART Tx registers (2 clk width)
port map(IN_SIGNAL => Data_ready_out_R, IN_CLK => SCLK_LF_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => Position_Tx_gate_R);
\Timer_pos_update_impulse_gen\ : impulse_gen_N_2cycle -- generate signal to update position (2 clk width)
port map(IN_SIGNAL => update_count, IN_CLK => SCLK_Khz_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => Latch_data_timer_imp);
\bcd_decoder_4digit_int\ : bcd_4dig -- 4-digit BCD decoder (integer part of position)
port map(number => Position_int_R(13 downto 0), thousands => pos_thousands_R, hundreds => pos_hundreds_R, tens => pos_tens_R , ones => pos_ones_R);
\bcd_decoder_4digit_fract\ : bcd_4dig -- 4-digit BCD decoder (fractional part of position)
port map(number => Position_fract_R, thousands => pos_fr_thousands_R, hundreds => pos_fr_hundreds_R, tens => pos_fr_tens_R , ones => pos_fr_ones_R);
\comparator1\ : InEquality_comparator_8bit -- compare previous and current position data (int_digits 1&2)
port map(DataA => Pos_Int_dig12_R, DataB => prev_Pos_Int_dig12_R, ANEB => Comp_Pos_Int_dig12);
\comparator2\ : InEquality_comparator_8bit -- compare previous and current position data (int_digits 3&4)
port map(DataA => Pos_Int_dig34_R, DataB => prev_Pos_Int_dig34_R, ANEB => Comp_Pos_Int_dig34);
\comparator3\ : InEquality_comparator_4bit -- compare previous and current position data (int_digits 5&6)
port map(DataA => Pos_Int_dig5_R, DataB => prev_Pos_Int_dig5_R, ANEB => Comp_Pos_Int_dig5);
\comparator4\ : InEquality_comparator_8bit -- compare previous and current position data (fract_digits 1&2)
port map(DataA => Pos_Fract_dig12_R, DataB => prev_Pos_Fract_dig12_R, ANEB => Comp_Pos_Fract_dig12);
\comparator5\ : InEquality_comparator_8bit -- compare previous and current position data (fract_digits 1&2)
port map(DataA => Pos_Fract_dig34_R, DataB => prev_Pos_Fract_dig34_R, ANEB => Comp_Pos_Fract_dig34);
Data_latch: process( RESET_N, SCLK_LF_IN)
begin
if ( RESET_N ='0')then
X_Pos_Int_R <= (OTHERS => '0');
X_pos_Fract_R <= (OTHERS => '0');
Y_Pos_Int_R <= (OTHERS => '0');
Y_pos_Fract_R <= (OTHERS => '0');
Z_Pos_Int_R <= (OTHERS => '0');
Z_pos_Fract_R <= (OTHERS => '0');
A4_Pos_Int_R <= (OTHERS => '0');
A4_pos_Fract_R <= (OTHERS => '0');
Data_ready_out_R <= '1'; -- set flag to prevent false trigger after reset
elsif (falling_edge(SCLK_LF_IN)) then
if (Data_ready_IN = '1' and Latch_data = '1') then -- new axis is selected or update timer expired
X_Pos_Int_R <= X_Pos_Int_in;
X_pos_Fract_R <= X_Pos_fract_in;
Y_Pos_Int_R <= Y_Pos_Int_in;
Y_pos_Fract_R <= Y_Pos_fract_in;
Z_Pos_Int_R <= Z_Pos_Int_in;
Z_pos_Fract_R <= Z_Pos_fract_in;
A4_Pos_Int_R <= A4_Pos_Int_in;
A4_pos_Fract_R <= A4_Pos_fract_in;
Data_ready_out_R <= '0'; -- clear flag
else -- if Latch_data_IN = '0'
Data_ready_out_R <= '1'; --DELAYED FOR 1/2 CLK LF CYCLE
end if;
end if;
end process Data_latch;
DATA_MUX: process( RESET_N, SCLK_IN)
begin
if ( RESET_N ='0')then
Position_sign_R <= '0';
Position_int_R <= (OTHERS => '0');
Position_fract_R <= (OTHERS => '0');
Pos_Int_dig12_R <= x"C0"; -- display: +0
Pos_Int_dig34_R <= (OTHERS => '0');
Pos_Int_dig5_R <= (OTHERS => '0');
Pos_Int_dig6_R <= x"A";
Pos_Fract_dig12_R <= (OTHERS => '0');
Pos_Fract_dig34_R <= (OTHERS => '0');
elsif (rising_edge(SCLK_IN)) then
if (Latch_data = '0' and Data_ready_out_R = '0') then -- duration only 1/2 CLK LF cycle
case (active_axis) is
when "1000" => -- Active axis: X
Position_int_R <= X_Pos_Int_R (13 downto 0);
Position_fract_R <= X_Pos_Fract_R (13 downto 0);
Position_sign_R <= X_Pos_Int_R (16);
when "0100" => -- Active axis: Y
Position_int_R <= Y_Pos_Int_R (13 downto 0);
Position_fract_R <= Y_Pos_Fract_R (13 downto 0);
Position_sign_R <= Y_Pos_Int_R (16);
when "0010" => -- Active axis: Z
Position_int_R <= Z_Pos_Int_R (13 downto 0);
Position_fract_R <= Z_Pos_Fract_R (13 downto 0);
Position_sign_R <= Z_Pos_Int_R (16);
when "0001" => -- Active axis: 4
Position_int_R <= A4_Pos_Int_R (13 downto 0);
Position_fract_R <= A4_Pos_Fract_R (13 downto 0);
Position_sign_R <= A4_Pos_Int_R (16);
when others => Position_int_R <= (OTHERS => '0');
Position_fract_R <= (OTHERS => '0');
Position_sign_R <= '0';
end case;
-- push integer part of position to outputs
Pos_Int_dig12_R <= Pos_Sign_code_R & pos_thousands_R;
Pos_Int_dig34_R <= pos_hundreds_R & pos_tens_R;
Pos_Int_dig5_R <= pos_ones_R;
Pos_Int_dig6_R <= x"A";
-- push fractional part of position to outputs
Pos_Fract_dig12_R <= pos_fr_thousands_R & pos_fr_hundreds_R;
Pos_Fract_dig34_R <= pos_fr_tens_R & pos_fr_ones_R;
else -- latching new data when Latch_data_IN = '1'; transmitting new UART data when Data_ready_out_R = '1'
null;
end if;
end if;
end process DATA_MUX;
Sign_decoder: process( RESET_N, Position_sign_R)
begin
if ( RESET_N ='0')then
Pos_Sign_code_R <= x"C"; -- -> "+"
elsif (Position_sign_R = '0') then -- if '0' -> "+"
Pos_Sign_code_R <= x"C";
else -- if '1' -> "-"
Pos_Sign_code_R <= x"B";
end if;
end process Sign_decoder;
clock_divider: process( RESET_N, SCLK_LF_IN)
begin
if ( RESET_N ='0')then
clk_divider <= (OTHERS => '0');
elsif (rising_edge(SCLK_KHz_IN)) then
clk_divider <= clk_divider + 1;
end if;
end process clock_divider;
update_count <= clk_divider(counter_width-1);
update_timer: process( RESET_N, update_count)
begin
if ( RESET_N ='0')then
UART_Send_Data_R <= '0'; -- active HIGH. "Sent new position data" is inactive
elsif (falling_edge(update_count)) then -- delay between rising and falling edge is used to process new data
if (New_data_available = '1') then -- new data is available
UART_Send_Data_R <= '1'; -- set flag to send data via UART
prev_Pos_Int_dig12_R <= Pos_Int_dig12_R;
prev_Pos_Int_dig34_R <= Pos_Int_dig34_R;
prev_Pos_Int_dig5_R <= Pos_Int_dig5_R;
prev_Pos_Fract_dig12_R <= Pos_Fract_dig12_R;
prev_Pos_Fract_dig34_R <= Pos_Fract_dig34_R;
else
UART_Send_Data_R <= '0'; -- clear flag
end if;
end if;
end process update_timer;
end a_Position;
|
gpl-2.0
|
35c3c3bdb005c2406b7b1cb333ee2d9d
| 0.583227 | 3.135762 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/fdiv/wb_fdiv.vhd
| 1 | 3,450 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- W I S H B O N E V A R I A B L E F R E Q U E N C Y D I V I D E R
-- (wb_fdiv.vhd)
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
entity wb_fdiv is
-------------------------------------------------------------------------------
generic (
USER_CLK : Boolean := false
);
port (
-- wishbone
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- user pins
clk_in : in std_logic := '-'; -- optional alternative clock input
clk_out : out std_logic
);
end wb_fdiv;
-------------------------------------------------------------------------------
architecture mixed of wb_fdiv is
-------------------------------------------------------------------------------
signal divide_s : std_logic_vector(WB_DW-1 downto 0);
signal raw_clk_s : std_logic;
signal div_clk_s : std_logic;
begin
-- select raw clock using USER_CLK generic
raw_clk_s <= clk_in when USER_CLK else wbs_in.clk;
----------------------------------------------------------------------------
WISHBONE_SLAVE : entity work.wbs_single_reg
----------------------------------------------------------------------------
port map (
wbs_in => wbs_in,
wbs_out => wbs_out,
register_out => divide_s
);
----------------------------------------------------------------------------
FDIV : process(divide_s, raw_clk_s)
----------------------------------------------------------------------------
variable cnt : integer range 0 to 255 := 0;
variable cmp : integer range 0 to 255;
begin
cmp := to_integer(unsigned(divide_s));
-- clk_out is deactivated when divider is 0
if (cmp = 0) then
div_clk_s <= '0';
-- decrement cmp since counting from 0
cmp := cmp - 1;
-- toggle clk_out when cnt reaches cmp
elsif (rising_edge(raw_clk_s)) then
if (cnt < cmp) then
cnt := cnt + 1;
else
div_clk_s <= not div_clk_s;
cnt := 0;
end if;
end if;
end process FDIV;
----------------------------------------------------------------------------
CLK_OUT_BUFFER : BUFG
----------------------------------------------------------------------------
port map (
O => clk_out,
I => div_clk_s
);
end mixed;
|
gpl-3.0
|
fb272895cfb8ac00a928e8909c78fcc3
| 0.44058 | 4.700272 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL source files/Input_filter_1channel.vhd
| 1 | 1,366 |
------------------------------------------------------------------------
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
--
-- File: Input_filter_1channel.vhd
--
-- Description:
--
-- General-purpose input filter for FPGA signals (Majority filter)
-- Eliminates line "ringing" and create stable output for high speed logic.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity input_filter_1ch is
port(
reset :in std_logic; -- unfiltered input signal
INPUT_CLK :in std_logic; -- input clock signal
INPUT_SIGNAL_1 :in std_logic; -- unfiltered input signal
FILTERED_SIGNAL_1 :out std_logic -- output filtered signal
);
end input_filter_1ch;
architecture arch of input_filter_1ch is
signal in1 :std_logic_vector (2 downto 0);
begin
FILTERED_SIGNAL_1 <= (in1(0) and in1(1)) or (in1(1) and in1(2)) or (in1(2) and in1(0));
proc1:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in1 <= "000";
elsif rising_edge(input_clk) then
in1(2) <= in1(1);
in1(1) <= in1(0);
in1(0) <= input_signal_1;
end if;
end process proc1;
end arch;
|
gpl-2.0
|
a0da4ce7696605c809b700fa1b7618d9
| 0.538067 | 3.56658 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/wishbone_slave/wbs_single_reg.vhd
| 1 | 3,495 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- S I M P L E W I S H B O N E S L A V E (wbs_single_reg.vhd)
--
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity wbs_single_reg is
generic (
core_address : unsigned(WB_CORE_AW-1 downto 0) := (others => '0')
);
port (
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- permanently outputs the data stored in the register
register_out : out std_logic_vector(WB_DW-1 downto 0)
);
end wbs_single_reg;
architecture two_proc of wbs_single_reg is
type reg_type is record
data : std_logic_vector(WB_DW-1 downto 0);
end record;
signal reg_out, reg_in : reg_type;
signal ff_clk_enable_s : std_logic;
signal addr_match_s : std_logic;
begin
-------------------------------------------------------------------------------
COMBINATIONAL : process(wbs_in, reg_out, addr_match_s)
-------------------------------------------------------------------------------
variable tmp : reg_type;
begin
tmp := reg_out; -- default assignments
-- data input and synchronous reset
if (wbs_in.rst = '1') then
tmp.data := (others => '0');
else
tmp.data := wbs_in.dat;
end if;
-- address comparator
if (unsigned(wbs_in.adr) = core_address) then
addr_match_s <= '1';
else
addr_match_s <= '0';
end if;
-- wishbone data output: on compare match only
if (addr_match_s = '1') then
wbs_out.dat <= reg_out.data;
else
wbs_out.dat <= (others => '0');
end if;
-- register clock enable signal
ff_clk_enable_s <= wbs_in.stb AND wbs_in.we AND addr_match_s;
-- acknowledge output
wbs_out.ack <= wbs_in.stb;
-- data output: always register content
register_out <= reg_out.data;
reg_in <= tmp; -- drive register inputs
end process COMBINATIONAL;
-------------------------------------------------------------------------------
REGISTERS : process(wbs_in.clk, ff_clk_enable_s) -- sequential process
-------------------------------------------------------------------------------
begin
if (rising_edge(wbs_in.clk) AND ff_clk_enable_s = '1') then
reg_out <= reg_in;
end if;
end process REGISTERS;
end two_proc;
|
gpl-3.0
|
4c26d1612ad3042811ba3c51e92c1294
| 0.503004 | 4.267399 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/nexys3/sys_conf.vhd
| 1 | 3,712 |
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432)
-- 2011-11-20 430 1.0 Initial version (derived from _n2 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd):
-- div mul clksys read0 read1 write
-- 2 1 50.0 2 2 3
-- 4 3 75.0 4 4 5 (also 70 MHz)
-- 5 4 80.0 5 5 5
-- 20 17 85.0 5 5 6
-- 10 9 90.0 6 6 6 (also 95 MHz)
-- 1 1 100.0 6 6 7
package sys_conf is
constant sys_conf_clkfx_divide : positive := 5;
constant sys_conf_clkfx_multiply : positive := 4; -- ==> 80 MHz
constant sys_conf_memctl_read0delay : positive := 5;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 5;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
0a62a80393666a9804df8aad31b5e3be
| 0.591864 | 3.541985 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/memlib/fifo_2c_dram.vhd
| 2 | 12,242 |
-- $Id: fifo_2c_dram.vhd 424 2011-11-13 16:38:23Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram - syn
-- Description: FIFO, two clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: ram_1swar_1ar_gen
-- genlib/gray_cnt_n
-- genlib/gray2bin_gen
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.1 use capture+sync flops; reset now glitch free
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-12-28 107 1.0.1 VAL=0 in cycle after RESETR=1
-- 2007-12-28 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2011-11-13 Rev 424: ise 13.1 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m LUT.s Flop Slice CLKW CLKR (xst est.)
-- 4 16 41 32 12 38 54 135MHz 115MHz ( 16 words)
-- 5 16 65 64 14 40 80 113MHz 116MHz ( 32 words)
-- - 2007-12-28 Rev 106: ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m Flop CLKW CLKR (xst est.)
-- 4 16 40 32 42 141MHz 165MHz ( 16 words)
-- 5 16 65 64 52 108MHz 108MHz ( 32 words)
-- 6 16 95 128 61 111MHz 113MHz ( 64 words)
-- 7 16 149 256 74 100MHz 96MHz (128 words)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.memlib.all;
entity fifo_2c_dram is -- fifo, 2 clock, dram based
generic (
AWIDTH : positive := 5; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end fifo_2c_dram;
architecture syn of fifo_2c_dram is
type regw_type is record
raddr_c : slv(AWIDTH-1 downto 0); -- read address (capt from CLKR)
raddr_s : slv(AWIDTH-1 downto 0); -- read address (sync in CLKW)
sizew : slv(AWIDTH-1 downto 0); -- slots to write
busy : slbit; -- busy flag
rstw : slbit; -- resetw active
rstw_sc : slbit; -- resetw (sync-capt from CLKR-CLKW)
rstw_ss : slbit; -- resetw (sync-sync from CLKR-CLKW)
rstr_c : slbit; -- resetr (capt from CLKR)
rstr_s : slbit; -- resetr (sync from CLKR)
end record regw_type;
constant regw_init : regw_type := (
slv(to_unsigned(0,AWIDTH)), -- raddr_c
slv(to_unsigned(0,AWIDTH)), -- raddr_s
slv(to_unsigned(0,AWIDTH)), -- sizew
'0', -- busy
'0','0','0', -- rstw,rstw_sc,rstw_ss
'0','0' -- rstr_c,rstr_s
);
type regr_type is record
waddr_c : slv(AWIDTH-1 downto 0); -- write address (capt from CLKW)
waddr_s : slv(AWIDTH-1 downto 0); -- write address (sync in CLKR)
sizer : slv(AWIDTH-1 downto 0); -- slots to read
val : slbit; -- valid flag
rstr : slbit; -- resetr active
rstr_sc : slbit; -- resetr (sync-capt from CLKW-CLKR)
rstr_ss : slbit; -- resetr (sync-sync from CLKW-CLKR)
rstw_c : slbit; -- resetw (capt from CLKW)
rstw_s : slbit; -- resetw (sync from CLKW)
end record regr_type;
constant regr_init : regr_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr_c
slv(to_unsigned(0,AWIDTH)), -- waddr_s
slv(to_unsigned(0,AWIDTH)), -- sizer
'0', -- val
'0','0','0', -- rstr,rstr_sc,rstr_ss
'0','0' -- rstw_c,rstw_s
);
signal R_REGW : regw_type := regw_init; -- write side state registers
signal N_REGW : regw_type := regw_init; -- next values write side
signal R_REGR : regr_type := regr_init; -- read side state registers
signal N_REGR : regr_type := regr_init; -- next values read side
signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal GCW_RST : slbit := '0';
signal GCW_CE : slbit := '0';
signal GCR_RST : slbit := '0';
signal GCR_CE : slbit := '0';
begin
RAM : ram_1swar_1ar_gen -- dual ported memory
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLKW,
WE => GCW_CE,
ADDRA => WADDR,
ADDRB => RADDR,
DI => DI,
DOA => open,
DOB => DO
);
GCW : gray_cnt_gen -- gray counter for write address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKW,
RESET => GCW_RST,
CE => GCW_CE,
DATA => WADDR
);
GCR : gray_cnt_gen -- gray counter for read address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKR,
RESET => GCR_RST,
CE => GCR_CE,
DATA => RADDR
);
G2B_WW : gray2bin_gen -- gray->bin for waddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => WADDR, DO => WADDR_BIN);
G2B_WR : gray2bin_gen -- gray->bin for waddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGR.waddr_s, DO => WADDR_S_BIN);
G2B_RW : gray2bin_gen -- gray->bin for raddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => RADDR, DO => RADDR_BIN);
G2B_RR : gray2bin_gen -- gray->bin for raddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGW.raddr_s, DO => RADDR_S_BIN);
proc_regw: process (CLKW)
begin
if rising_edge(CLKW) then
R_REGW <= N_REGW;
end if;
end process proc_regw;
proc_nextw: process (R_REGW, RESETW, ENA, R_REGR,
RADDR, RADDR_S_BIN, WADDR_BIN)
variable r : regw_type := regw_init;
variable n : regw_type := regw_init;
variable ibusy : slbit := '0';
variable igcw_ce : slbit := '0';
variable igcw_rst : slbit := '0';
variable isizew : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGW;
n := R_REGW;
isizew := slv(unsigned(RADDR_S_BIN) + unsigned(not WADDR_BIN));
ibusy := '0';
igcw_ce := '0';
igcw_rst := '0';
if unsigned(isizew) = 0 then -- if no free slots
ibusy := '1'; -- next cycle busy=1
end if;
if ENA='1' and r.busy='0' then -- if ena=1 and this cycle busy=0
igcw_ce := '1'; -- write this value
if unsigned(isizew) = 1 then -- if this last free slot
ibusy := '1'; -- next cycle busy=1
end if;
end if;
if RESETW = '1' then -- reset(write side) request
n.rstw := '1'; -- set RSTW flag
elsif r.rstw_ss = '1' then -- request gone and return seen
n.rstw := '0'; -- clear RSTW flag
end if;
if r.rstw='1' and r.rstw_ss='1' then -- RSTW seen on write and read side
igcw_rst := '1'; -- clear write address counter
end if;
if r.rstr_s = '1' then -- RSTR active
igcw_rst := '1'; -- clear write address counter
end if;
if RESETW='1' or r.rstw='1' or r.rstw_ss='1' or r.rstr_s='1'
then -- RESETW or RESETR active
ibusy := '1'; -- signal write side busy
isizew := (others=>'1');
end if;
n.busy := ibusy;
n.sizew := isizew;
n.raddr_c := RADDR; -- data captuture from CLKR
n.raddr_s := r.raddr_c;
n.rstw_sc := R_REGR.rstw_s;
n.rstw_ss := r.rstw_sc;
n.rstr_c := R_REGR.rstr;
n.rstr_s := r.rstr_c;
N_REGW <= n;
GCW_CE <= igcw_ce;
GCW_RST <= igcw_rst;
BUSY <= r.busy;
SIZEW <= r.sizew;
end process proc_nextw;
proc_regr: process (CLKR)
begin
if rising_edge(CLKR) then
R_REGR <= N_REGR;
end if;
end process proc_regr;
proc_nextr: process (R_REGR, RESETR, HOLD, R_REGW,
WADDR, WADDR_S_BIN, RADDR_BIN)
variable r : regr_type := regr_init;
variable n : regr_type := regr_init;
variable ival : slbit := '0';
variable igcr_ce : slbit := '0';
variable igcr_rst : slbit := '0';
variable isizer : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGR;
n := R_REGR;
isizer := slv(unsigned(WADDR_S_BIN) - unsigned(RADDR_BIN));
ival := '1';
igcr_ce := '0';
igcr_rst := '0';
if unsigned(isizer) = 0 then -- if nothing to read
ival := '0'; -- next cycle val=0
end if;
if r.val='1' and HOLD='0' then -- this cycle val=1 and no hold
igcr_ce := '1'; -- retire this value
if unsigned(isizer) = 1 then -- if this is last one
ival := '0'; -- next cycle val=0
end if;
end if;
if RESETR = '1' then -- reset(read side) request
n.rstr := '1'; -- set RSTR flag
elsif r.rstr_ss = '1' then -- request gone and return seen
n.rstr := '0'; -- clear RSTR flag
end if;
if r.rstr='1' and r.rstr_ss='1' then -- RSTR seen on read and write side
igcr_rst := '1'; -- clear read address counter
end if;
if r.rstw_s = '1' then -- RSTW active
igcr_rst := '1'; -- clear read address counter
end if;
if RESETR='1' or r.rstr='1' or r.rstr_ss='1' or r.rstw_s='1'
then -- RESETR or RESETW active
ival := '0'; -- signal read side empty
isizer := (others=>'0');
end if;
n.val := ival;
n.sizer := isizer;
n.waddr_c := WADDR; -- data captuture from CLKW
n.waddr_s := r.waddr_c;
n.rstr_sc := R_REGW.rstr_s;
n.rstr_ss := r.rstr_sc;
n.rstw_c := R_REGW.rstw;
n.rstw_s := r.rstw_c;
N_REGR <= n;
GCR_CE <= igcr_ce;
GCR_RST <= igcr_rst;
VAL <= r.val;
SIZER <= r.sizer;
end process proc_nextr;
end syn;
|
gpl-2.0
|
1cbbdc4db8df999d7035894697ef35f0
| 0.505881 | 3.521864 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/tb_noekeon.vhd
| 1 | 5,032 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon IS
END tb_noekeon;
ARCHITECTURE behavior OF tb_noekeon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
wait for clk_period*64;-- + clk_period/2;
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
-- wait for clk_period + clk_period/2;
-- rst <= '1';
-- enc <= '1';
--
-- a_0_in <= X"e2f687e0";
-- a_1_in <= X"7b75660f";
-- a_2_in <= X"fc372233";
-- a_3_in <= X"bc47532c";
--
-- k_0_in <= X"b1656851";
-- k_1_in <= X"699e29fa";
-- k_2_in <= X"24b70148";
-- k_3_in <= X"503d2dfc";
--
-- wait for clk_period;
-- rst <= '0';
--
-- wait for clk_period*15 + clk_period/2;
--
-- assert a_0_out = X"2a78421b"
-- report "DECRYPT ERROR (a_0)" severity FAILURE;
--
-- assert a_1_out = X"87c7d092"
-- report "DECRYPT ERROR (a_1)" severity FAILURE;
--
-- assert a_2_out = X"4f26113f"
-- report "DECRYPT ERROR (a_2)" severity FAILURE;
--
-- assert a_3_out = X"1d1349b2"
-- report "DECRYPT ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
|
gpl-3.0
|
b068209150abd75cf34613665c22fc70
| 0.553657 | 2.849377 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/avmb/sys_conf.vhd
| 1 | 1,673 |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_mb (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.4; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(40000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-2.0
|
39aa6ccb972fa42015a0587d136dfe1f
| 0.637776 | 3.945755 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/tb/tbd_serport_autobaud.vhd
| 1 | 4,932 |
-- $Id: tbd_serport_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_autobaud - syn
-- Description: Wrapper for serport_uart_autobaud and serport_uart_rxtx to
-- avoid records. It has a port interface which will not be
-- modified by xst synthesis (no records, no generic port).
--
-- Dependencies: clkdivce
-- serport_uart_autobaud
-- serport_uart_rxtx
-- serport_uart_rx
--
-- To test: serport_uart_autobaud
-- serport_uart_rxtx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 151 291 0 - t 9.23
-- 2007-10-27 92 9.1 J30 xc3s1000-4 151 291 0 - t 9.23
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 338 0 178 s 9.45
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 152 293 0 - s 9.40
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-01-20 112 1.0.1 rename clkgen->clkdivce
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serport.all;
entity tbd_serport_autobaud is -- serial port autobaud [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CE_USEC : out slbit; -- usec pulse (here every 4 clocks)
CE_MSEC : out slbit; -- msec pulse (here every 20 clocks)
CLKDIV : out slv13; -- clock divider setting
ABACT : out slbit; -- autobaud active
ABDONE : out slbit; -- autobaud done
RXDATA : out slv8; -- receiver data out (1st rx)
RXVAL : out slbit; -- receiver data valid (1st rx)
RXERR : out slbit; -- receiver data error (1st rx)
RXACT : out slbit; -- receiver active (1st rx)
TXSD2 : out slbit; -- transmit serial data (2nd tx)
RXDATA3 : out slv8; -- receiver data out (3rd rx)
RXVAL3 : out slbit; -- receiver data valid (3rd rx)
RXERR3 : out slbit; -- receiver data error (3rd rx)
RXACT3 : out slbit -- receiver active (3rd rx)
);
end tbd_serport_autobaud;
architecture syn of tbd_serport_autobaud is
constant cdwidth : positive := 13;
signal LCE_MSEC : slbit := '0';
signal LCLKDIV : slv13 := (others=>'0');
signal LRXDATA : slv8 := (others=>'0');
signal LRXVAL : slbit := '0';
signal LTXSD2 : slbit := '0';
signal LABACT : slbit := '0';
begin
CKLDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => LCE_MSEC
);
AUTOBAUD : serport_uart_autobaud
generic map (
CDWIDTH => cdwidth,
CDINIT => 15)
port map (
CLK => CLK,
CE_MSEC => LCE_MSEC,
RESET => RESET,
RXSD => RXSD,
CLKDIV => LCLKDIV,
ACT => LABACT,
DONE => ABDONE
);
UART1 : serport_uart_rxtx
generic map (
CDWIDTH => cdwidth)
port map (
CLK => CLK,
RESET => LABACT,
CLKDIV => LCLKDIV,
RXSD => RXSD,
RXDATA => LRXDATA,
RXVAL => LRXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => LTXSD2,
TXDATA => LRXDATA,
TXENA => LRXVAL,
TXBUSY => open
);
UART2 : serport_uart_rx
generic map (
CDWIDTH => cdwidth)
port map (
CLK => CLK,
RESET => LABACT,
CLKDIV => LCLKDIV,
RXSD => LTXSD2,
RXDATA => RXDATA3,
RXVAL => RXVAL3,
RXERR => RXERR3,
RXACT => RXACT3
);
CE_MSEC <= LCE_MSEC;
CLKDIV <= LCLKDIV;
ABACT <= LABACT;
RXDATA <= LRXDATA;
RXVAL <= LRXVAL;
TXSD2 <= LTXSD2;
end syn;
|
gpl-2.0
|
2d002e1e89af8ba05ac784494c50d92e
| 0.533658 | 3.805556 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/algorithms/sourdis_bispo_nfa/vhdl/state_pcre_exact.vhd
| 1 | 2,970 |
-- ----------------------------------------------------------------------------
-- Entity for implementation of exactly N
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity STATE_PCRE_EXACT is
generic(
M : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
INPUT : in std_logic;
SYMBOL : in std_logic;
WE : in std_logic;
-- output data interface
OUTPUT : out std_logic
);
end entity STATE_PCRE_EXACT;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of STATE_PCRE_EXACT is
signal local_reset : std_logic;
signal local_reset_out: std_logic;
signal cnt_reset: std_logic;
signal sh_out : std_logic;
signal sh_in : std_logic;
signal value : std_logic_vector(11 downto 0);
begin
local_reset <= RESET or not SYMBOL;
local_reset_out <= RESET or cnt_reset;
input_reg: process(CLK, RESET)
begin
if (clk'event and CLK='1') then
if (local_reset = '1') then
sh_in <= '0';
else
sh_in <= INPUT;
end if;
end if;
end process;
gen_shift: if M > 2 generate
shift_reg: entity work.sh_reg
generic map(
NUM_BITS => M - 2
)
port map(
CLK => CLK,
DIN => sh_in,
CE => WE,
DOUT => sh_out
);
end generate;
gen_2: if M = 2 generate
sh_out <= sh_in;
end generate;
gen_1: if M = 1 generate
sh_out <= INPUT;
end generate;
output_reg: process(CLK, RESET)
begin
if (clk'event and CLK='1') then
if (local_reset_out = '1') then
OUTPUT <= '0';
else
OUTPUT <= sh_out;
end if;
end if;
end process;
cnt_reset_u: process(CLK, RESET)
begin
if (CLK'event and CLK = '1') then
if (local_reset = '1') then
value <= (others => '0');
else
if (we = '1') then
if ((cnt_reset = '1')) then
value <= value + 1;
end if;
end if;
end if;
end if;
end process;
cnt_reset <= '1' when (value > 0 and value <= M) else '0';
end architecture full;
|
gpl-2.0
|
2115882df798c58d3daca007971778d3
| 0.393603 | 4.555215 | false | false | false | false |
armandas/FPGalaxy
|
player.vhd
| 1 | 4,536 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity player is
port(
clk, not_reset: in std_logic;
shooting_sound, explosion_sound: in std_logic;
buzzer: out std_logic
);
end player;
architecture behaviour of player is
signal pitch: std_logic_vector(18 downto 0);
signal duration: std_logic_vector(25 downto 0);
signal volume: std_logic_vector(2 downto 0);
signal enable: std_logic;
signal d_counter, d_counter_next: std_logic_vector(25 downto 0);
signal note, note_next: std_logic_vector(8 downto 0);
signal note_addr, note_addr_next: std_logic_vector(4 downto 0);
signal change_note: std_logic;
-- data source for tunes
signal source, source_next: std_logic;
-- container for current data selected by multiplexer
signal data: std_logic_vector(8 downto 0);
-- data containers for use with ROMs. Add more as needed.
signal data_1, data_2: std_logic_vector(8 downto 0);
type state_type is (off, playing);
signal state, state_next: state_type;
signal start: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
state <= off;
source <= '0';
note_addr <= (others => '0');
note <= (others => '0');
d_counter <= (others => '0');
elsif clk'event and clk = '1' then
state <= state_next;
source <= source_next;
note_addr <= note_addr_next;
note <= note_next;
d_counter <= d_counter_next;
end if;
end process;
process(state, start, enable, duration, d_counter, note_addr, change_note)
begin
state_next <= state;
note_addr_next <= note_addr;
case state is
when off =>
note_addr_next <= (others => '0');
if start = '1' then
state_next <= playing;
end if;
when playing =>
if duration = 0 then
state_next <= off;
elsif change_note = '1' then
note_addr_next <= note_addr + 1;
end if;
end case;
end process;
enable <= '1' when state = playing else '0';
change_note <= '1' when d_counter = duration else '0';
d_counter_next <= d_counter + 1 when (enable = '1' and
d_counter < duration) else
(others => '0');
with note(8 downto 6) select
pitch <= "1101110111110010001" when "001", -- 110 Hz
"0110111011111001000" when "010", -- 220 Hz
"0011011101111100100" when "011", -- 440 Hz
"0001101110111110010" when "100", -- 880 Hz
"0000110111011111001" when "101", -- 1760 Hz
"0000011011101111100" when "110", -- 3520 Hz
"0000001101110111110" when "111", -- 7040 Hz
"0000000000000000000" when others;
with note(5 downto 3) select
duration <= "00000010111110101111000010" when "001", -- 1/64
"00000101111101011110000100" when "010", -- 1/32
"00001011111010111100001000" when "011", -- 1/16
"00010111110101111000010000" when "100", -- 1/8
"00101111101011110000100000" when "101", -- 1/4
"01011111010111100001000000" when "110", -- 1/2
"10111110101111000010000000" when "111", -- 1/1
"00000000000000000000000000" when others;
volume <= note(2 downto 0);
start <= '1' when (shooting_sound = '1' or explosion_sound = '1') else '0';
-- data source
source_next <= '0' when shooting_sound = '1' else
'1' when explosion_sound = '1' else
source;
data <= data_1 when source = '0' else data_2;
note_next <= data;
shooting:
entity work.shooting_sound(content)
port map(
addr => note_addr,
data => data_1
);
explosion:
entity work.explosion_sound(content)
port map(
addr => note_addr,
data => data_2
);
sounds:
entity work.sounds(generator)
port map(
clk => clk, not_reset => not_reset,
enable => enable,
period => pitch,
volume => volume,
buzzer => buzzer
);
end behaviour;
|
bsd-2-clause
|
90f8799c3ab038af1feed3f1ec451f6b
| 0.531966 | 4.112421 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/memlib/fifo_1c_dram_raw.vhd
| 2 | 4,593 |
-- $Id: fifo_1c_dram_raw.vhd 421 2011-11-07 21:23:50Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fifo_1c_dram_raw - syn
-- Description: FIFO, single clock domain, distributed RAM based, 'raw'
-- interface exposing dram signals.
--
-- Dependencies: ram_1swar_1ar_gen
--
-- Test bench: tb/tb_fifo_1c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-03 47 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
WE : in slbit; -- write enable
RE : in slbit; -- read enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
EMPTY : out slbit; -- empty flag
FULL : out slbit -- full flag
);
end fifo_1c_dram_raw;
architecture syn of fifo_1c_dram_raw is
type regs_type is record
waddr : slv(AWIDTH-1 downto 0); -- write address
raddr : slv(AWIDTH-1 downto 0); -- read address
empty : slbit; -- empty flag
full : slbit; -- full flag
end record regs_type;
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RAM_WE : slbit := '0';
begin
RAM : ram_1swar_1ar_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
WE => RAM_WE,
ADDRA => R_REGS.waddr,
ADDRB => R_REGS.raddr,
DI => DI,
DOA => open,
DOB => DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, WE, RE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
variable we_val : slbit := '0';
variable re_val : slbit := '0';
variable iram_we : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
re_val := RE and not r.empty;
we_val := WE and ((not r.full) or RE);
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
iram_we := '0';
if RESET = '1' then
n := regs_init;
else
if we_val = '1' then
n.waddr := slv(unsigned(r.waddr) + 1);
iram_we := '1';
if re_val = '0' then
n.empty := '0';
if unsigned(isize) = memsize-1 then
n.full := '1';
end if;
end if;
end if;
if re_val = '1' then
n.raddr := slv(unsigned(r.raddr) + 1);
if we_val = '0' then
n.full := '0';
if unsigned(isize) = 1 then
n.empty := '1';
end if;
end if;
end if;
end if;
N_REGS <= n;
RAM_WE <= iram_we;
SIZE <= isize;
EMPTY <= r.empty;
FULL <= r.full;
end process proc_next;
end syn;
|
gpl-2.0
|
7ee8d02ca45741e1ce54ffd2d6596425
| 0.531025 | 3.57154 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/Instruction_Memory.vhd
| 1 | 3,417 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity IM is
port (
rst : in std_logic;
addr : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
);
end IM;
architecture behavioral of IM is
type memoria_rom is array (0 to 63) of std_logic_vector (31 downto 0);
signal ROM : memoria_rom := (
"10000010000100000010000000000101", --mov 5, %g1
"10100000000100000011111111111000", --mov -8, %l0
"10100010000100000010000000000100", --mov 4, %l1
"10110001001010000110000000000010", --sll %g1, 2, %i0
"10110011001101000110000000000001", --srl %l1, 1, %i1
"10000001111010000010000000000000",--restore %g0,0,%g0
"10100000000000000110000000000011", --add %g1,3,%l0
"10000001111000000010000000000000",--save %g0,0,%g0
"10000000101000000010000000000100", -- subcc %g0,4,%g0
"00000000000000000000000000000000",
"10000100010000000000000000000001", -- addx %g0,%g1, %g2
"10010000000100000000000000010000", -- mov %l0, %o0
"00000001000000000000000000000000", --nop
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
--"00000000000000000000000000000000",
--"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000" -- Fila con datos 56 a 63
);
begin
process(rst, addr)
begin
if (rst = '1') then
data <= "00000000000000000000000000000000";
else
data <= ROM(conv_integer(addr));
end if;
end process;
end behavioral;
--from random import randint
--n = 64
--for i in xrange(n):
-- x = randint(0, 1<<32)
--num = str(bin(x))[2:]
--num = (32 - len(num)) * '0' + num
--print "\"" + num + "\","
|
mit
|
d682435bc6a121f0c3b6a9101e78251b
| 0.784021 | 5.161631 | false | false | false | false |
rogerioag/gcg
|
tutorial/ula/src/somador.vhd
| 1 | 1,155 |
-- Projeto gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Descrição da Entidade: somador.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity somador is
port(a, b, cin, opSomador:in std_logic; s, cout: out std_logic);
end somador;
architecture estrutural of somador is
component and2
port(a, b: in std_logic; y: out std_logic);
end component;
component xor2
port(a, b: in std_logic; y: out std_logic);
end component;
component and3
port(a, b, c: in std_logic; y: out std_logic);
end component;
component or3
port(a, b, c: in std_logic; y: out std_logic);
end component;
signal s_X1_X2, s_X2_A1, s_A1_O1, s_A2_O1, s_A3_O1, s_A4_O1: std_logic;
begin
X1: xor2 port map(a=>a, b=>b, y=>s_X1_X2);
X2: xor2 port map(a=>s_X1_X2, b=>cin, y=>s_X2_A1);
A1: and2 port map(a=>s_X2_A1, b=>opSomador, y=>s);
A2: and3 port map(a=>a, b=>b, c=>opSomador, y=>s_A2_O1);
A3: and3 port map(a=>a, b=>cin, c=>opSomador, y=>s_A3_O1);
A4: and3 port map(a=>b, b=>cin, c=>opSomador, y=>s_A4_O1);
O1: or3 port map(a=>s_A2_O1, b=>s_A3_O1, c=>s_A4_O1, y=>cout);
end estrutural;
|
gpl-3.0
|
441a223c7e6efbc91c9ff78bf68e58ee
| 0.648742 | 2.19619 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/round_f.vhd
| 1 | 7,285 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end round_f;
architecture Behavioral of round_f is
signal a_0_in_s : std_logic_vector(31 downto 0);
signal theta_0_s : std_logic_vector(31 downto 0);
signal theta_1_s : std_logic_vector(31 downto 0);
signal theta_2_s : std_logic_vector(31 downto 0);
signal theta_3_s : std_logic_vector(31 downto 0);
signal pi_1_1_s : std_logic_vector(31 downto 0);
signal pi_1_2_s : std_logic_vector(31 downto 0);
signal pi_1_3_s : std_logic_vector(31 downto 0);
signal gamma_0_s : std_logic_vector(31 downto 0);
signal gamma_1_s : std_logic_vector(31 downto 0);
signal gamma_2_s : std_logic_vector(31 downto 0);
signal gamma_3_s : std_logic_vector(31 downto 0);
signal pi_2_1_s : std_logic_vector(31 downto 0);
signal pi_2_2_s : std_logic_vector(31 downto 0);
signal pi_2_3_s : std_logic_vector(31 downto 0);
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component pi_1 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component gamma is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component pi_2 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component reg_128 is
port(clk : in std_logic;
rst : in std_logic;
data_in_0 : in std_logic_vector(31 downto 0);
data_in_1 : in std_logic_vector(31 downto 0);
data_in_2 : in std_logic_vector(31 downto 0);
data_in_3 : in std_logic_vector(31 downto 0);
data_out_0 : out std_logic_vector(31 downto 0);
data_out_1 : out std_logic_vector(31 downto 0);
data_out_2 : out std_logic_vector(31 downto 0);
data_out_3 : out std_logic_vector(31 downto 0));
end component;
signal a_0_aux_s : std_logic_vector(31 downto 0);
signal stage_0_out_0_s : std_logic_vector(31 downto 0);
signal stage_0_out_1_s : std_logic_vector(31 downto 0);
signal stage_0_out_2_s : std_logic_vector(31 downto 0);
signal stage_0_out_3_s : std_logic_vector(31 downto 0);
signal stage_1_out_0_s : std_logic_vector(31 downto 0);
signal stage_1_out_1_s : std_logic_vector(31 downto 0);
signal stage_1_out_2_s : std_logic_vector(31 downto 0);
signal stage_1_out_3_s : std_logic_vector(31 downto 0);
signal stage_2_out_0_s : std_logic_vector(31 downto 0);
signal stage_2_out_1_s : std_logic_vector(31 downto 0);
signal stage_2_out_2_s : std_logic_vector(31 downto 0);
signal stage_2_out_3_s : std_logic_vector(31 downto 0);
signal rc_delay_s : std_logic_vector(31 downto 0);
begin
rc_delay_s <= rc_in;
a_0_in_s <= (a_0_in xor rc_delay_s) when enc = '0' else a_0_in;
THETA_0 : theta port map (a_0_in_s,
a_1_in,
a_2_in,
a_3_in,
k_0_in,
k_1_in,
k_2_in,
k_3_in,
theta_0_s,
theta_1_s,
theta_2_s,
theta_3_s);
REG_STAGE_0: reg_128 port map (clk,
rst,
theta_0_s,
theta_1_s,
theta_2_s,
theta_3_s,
stage_0_out_0_s,
stage_0_out_1_s,
stage_0_out_2_s,
stage_0_out_3_s);
PI_1_0 : pi_1 port map (stage_0_out_1_s,
stage_0_out_2_s,
stage_0_out_3_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s);
a_0_aux_s <= (stage_0_out_0_s xor rc_delay_s) when enc = '1' else stage_0_out_0_s;
REG_STAGE_1: reg_128 port map (clk,
rst,
a_0_aux_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s,
stage_1_out_0_s,
stage_1_out_1_s,
stage_1_out_2_s,
stage_1_out_3_s);
GAMMA_0 : gamma port map (stage_1_out_0_s,
stage_1_out_1_s,
stage_1_out_2_s,
stage_1_out_3_s,
gamma_0_s,
gamma_1_s,
gamma_2_s,
gamma_3_s);
REG_STAGE_2: reg_128 port map (clk,
rst,
gamma_0_s,
gamma_1_s,
gamma_2_s,
gamma_3_s,
stage_2_out_0_s,
stage_2_out_1_s,
stage_2_out_2_s,
stage_2_out_3_s);
PI_2_0 : pi_2 port map (stage_2_out_1_s,
stage_2_out_2_s,
stage_2_out_3_s,
pi_2_1_s,
pi_2_2_s,
pi_2_3_s);
a_0_out <= stage_2_out_0_s;
a_1_out <= pi_2_1_s;
a_2_out <= pi_2_2_s;
a_3_out <= pi_2_3_s;
end Behavioral;
|
gpl-3.0
|
136b78149d6270de7a5a0a1c9445786f
| 0.585175 | 2.704157 | false | false | false | false |
rogerioag/gcg
|
tutorial/ula/testbench/and3_tb.vhd
| 1 | 2,050 |
-- Testebench gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Teste da entidade and3.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and3_tb is
end and3_tb;
architecture logica of and3_tb is
-- Declaração do componente.
component and3
port (a,b,c: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for and3_0: and3 use entity work.and3;
signal s_t_a, s_t_b, s_t_c, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
and3_0: and3 port map (a=>s_t_a,b=>s_t_b,c=>s_t_c,y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a, vi_b, vi_c: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(
('0', '0', '0', '0'),
('0', '0', '1', '0'),
('0', '1', '0', '0'),
('0', '1', '1', '0'),
('1', '0', '0', '0'),
('1', '0', '1', '0'),
('1', '1', '0', '0'),
('1', '1', '1', '1')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
s_t_c <= patterns(i).vi_c;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
|
gpl-3.0
|
4df9d9aa5cecf388e32c5164687d3073
| 0.565175 | 2.896011 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd
| 2 | 10,103 |
-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_xfirst_gen_unisim - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end ram_1swsr_xfirst_gen_unisim;
architecture syn of ram_1swsr_xfirst_gen_unisim is
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36
generic map (
INIT => O"000000000000",
SRVAL => O"000000000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(36*i+31 downto 36*i),
DOP => L_DO(36*i+35 downto 36*i+32),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(36*i+31 downto 36*i),
DIP => L_DI(36*i+35 downto 36*i+32),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_09_S36;
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36
generic map (
INIT => X"00000000",
SRVAL => X"00000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(32*i+31 downto 32*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(32*i+31 downto 32*i),
DIP => "0000",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_09_S32;
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18
generic map (
INIT => O"000000",
SRVAL => O"000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(18*i+15 downto 18*i),
DOP => L_DO(18*i+17 downto 18*i+16),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(18*i+15 downto 18*i),
DIP => L_DI(18*i+17 downto 18*i+16),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_10_S18;
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18
generic map (
INIT => X"0000",
SRVAL => X"0000",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(16*i+15 downto 16*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(16*i+15 downto 16*i),
DIP => "00",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_10_S16;
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9
generic map (
INIT => O"000",
SRVAL => O"000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(9*i+7 downto 9*i),
DOP => L_DO(9*i+8 downto 9*i+8),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(9*i+7 downto 9*i),
DIP => L_DI(9*i+8 downto 9*i+8),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_11_S9;
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9
generic map (
INIT => X"00",
SRVAL => X"00",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(8*i+7 downto 8*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(8*i+7 downto 8*i),
DIP => "0",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_11_S8;
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4
generic map (
INIT => X"0",
SRVAL => X"0",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(4*i+3 downto 4*i),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(4*i+3 downto 4*i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_12_S4;
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2
generic map (
INIT => "00",
SRVAL => "00",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(2*i+1 downto 2*i),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(2*i+1 downto 2*i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_13_S2;
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1
generic map (
INIT => "0",
SRVAL => "0",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(i downto i),
ADDR => ADDR,
CLK => CLK,
DI => DI(i downto i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_14_S1;
end syn;
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
|
gpl-2.0
|
65b852056b0084f1d0e4bc2783617685
| 0.475205 | 3.403976 | false | false | false | false |
os-cillation/easyfpga-soc
|
templates/fsm.vhd
| 1 | 2,389 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.constants.all;
--------------------------------------------------------------------------------
ENTITY <entity_name> is
--------------------------------------------------------------------------------
port (
clk_i : in std_logic;
rst_i : in std_logic;
);
end <entity_name>;
--------------------------------------------------------------------------------
ARCHITECTURE fsm of <entity_name> is
--------------------------------------------------------------------------------
----------------------------------------------
-- States and state signals
----------------------------------------------
type state_type is (
idle,
2nd_state,
...
);
signal current_state, nextstate : state_type;
begin
----------------------------------------------
MOORE_OUTPUT_LOGIC :
----------------------------------------------
process (current_state)
begin
case current_state is
when idle =>
end case;
end process MOORE_OUTPUT_LOGIC;
----------------------------------------------
NEXT_STATE_LOGIC :
----------------------------------------------
process (current_state)
begin
case current_state is
when idle =>
end case;
end process NEXT_STATE_LOGIC;
----------------------------------------------
STATE_REGISTER :
----------------------------------------------
process (clk_i, rst_i)
begin
if (rst_i = '1') then
current_state <= idle;
elsif rising_edge(clk_i) then
current_state <= next_state;
end if;
end process STATE_REGISTER;
end fsm;
|
gpl-3.0
|
c48600e219226196ee6466478c052c50
| 0.459607 | 5.104701 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_2/noekeon.vhd
| 1 | 8,076 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is an iterative implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
architecture Behavioral of noekeon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(407 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal rc_in_s : std_logic_vector(407 downto 0);
begin
-- rc_in_s <= X"80 1b 36 6c d8 ab 4d 9a 2f 5e bc 63 c6 97 35 6a d4";
-- rc_in_s <= X"80801b1b36366c6cd8d8abab4d4d9a9a2f2f5e5ebcbc6363c6c6979735356a6ad4d4";
rc_in_s <= X"8080801b1b1b3636366c6c6cd8d8d8ababab4d4d4d9a9a9a2f2f2f5e5e5ebcbcbc636363c6c6c69797973535356a6a6ad4d4d4";
--00000000000000000000000000000000000000000000";
--RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
RC_SHR_0: rc_shr port map (clk, rst, rc_in_s, rc_s);
rc_ext_s <= X"000000" & rc_s;
ROUND_F_0 : round_f port map (clk,
rst,
enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
|
gpl-3.0
|
52e7e677a4a6696b3d2715ee965d67ad
| 0.591134 | 2.541221 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/psr.vhd
| 1 | 512 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
Rst : in STD_LOGIC;
clk : in STD_LOGIC;
Ncwp : in STD_LOGIC;
Carry : out STD_LOGIC;
Cwp : out STD_LOGIC
);
end PSR;
architecture Behavioral of PSR is
begin
process(clk,Rst,NZVC)
begin
if (rising_edge(clk)) then
if (Rst = '1') then
Carry <= '0';
Cwp <= '0';
else
Cwp <= Ncwp;
Carry <=NZVC(0);
end if;
end if;
end process;
end Behavioral;
|
mit
|
bb2d7533d0a940f668729fb508f47d82
| 0.587891 | 2.860335 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/avmb/tb/tb_avmb_fusp.vhd
| 1 | 5,853 |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_avmb_fusp - sim
-- Description: Test bench for avmb (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- vlib/xlib/dcm_sfs
-- tb_avmb_core
-- vlib/serport/serport_uart_rxtx
-- avmb_fusp_aif [UUT]
--
-- To test: generic, any avmb_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.4; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.xlib.all;
use work.avmblib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_avmb_fusp is
end tb_avmb_fusp;
architecture sim of tb_avmb_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv4 := (others=>'0');
signal I_BTN : slv1 := (others=>'0');
signal O_LED : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 10 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
begin
TBCORE : tbcore_rlink_dcm
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
DCM_SYS : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKSYS,
LOCKED => open
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
MBCORE : entity work.tb_avmb_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : avmb_fusp_aif
port map (
I_CLK40 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod 2 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-2.0
|
3b28f6ce0975963ccccd569842e02dab
| 0.539552 | 3.440917 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL source files/bcd_5digit.vhd
| 1 | 3,062 |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
--
-- File: BCD_DECODER.vhd
-- File history:
-- <1.2>: <02/04/2015>: <added thousands and tens-thousands digits. MAX 65536 decimal>
-- <1.3>: <02/04/2015>: <MAX 131071 decimal>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Decode 16 bit input integer (max 99.999) into 5 digits in BCD code
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--------------------------------------------------------------------------------
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bcd_5dig is
Port (
number : in std_logic_vector (16 downto 0);
tensthousands : out std_logic_vector (3 downto 0);
thousands : out std_logic_vector (3 downto 0);
hundreds : out std_logic_vector (3 downto 0);
tens : out std_logic_vector (3 downto 0);
ones : out std_logic_vector (3 downto 0)
);
end bcd_5dig;
architecture Behavioral of bcd_5dig is
begin
bin_to_bcd : process (number)
-- Internal variable for storing bits
variable shift : unsigned(36 downto 0);
-- Alias for parts of shift register
alias num is shift(16 downto 0);
alias one is shift(20 downto 17);
alias ten is shift(24 downto 21);
alias hun is shift(28 downto 25);
alias thous is shift(32 downto 29);
alias tensthous is shift(36 downto 33);
--alias num is shift(7 downto 0);
--alias one is shift(11 downto 8);
--alias ten is shift(15 downto 12);
--alias hun is shift(19 downto 16);
--alias thous is shift(19 downto 16);
--alias tensthous is shift(19 downto 16);
begin
-- Clear previous number and store new number in shift register
num := unsigned(number);
one := X"0";
ten := X"0";
hun := X"0";
thous := X"0";
tensthous := X"0";
-- Loop eight times
for i in 1 to num'Length loop
-- Check if any digit is greater than or equal to 5
if one >= 5 then
one := one + 3;
end if;
if ten >= 5 then
ten := ten + 3;
end if;
if hun >= 5 then
hun := hun + 3;
end if;
if thous >= 5 then
thous := thous + 3;
end if;
if tensthous >= 5 then
tensthous := tensthous + 3;
end if;
-- Shift entire register left once
shift := shift_left(shift, 1);
end loop;
-- Push decimal numbers to output
tensthousands <= std_logic_vector(tensthous);
thousands <= std_logic_vector(thous);
hundreds <= std_logic_vector(hun);
tens <= std_logic_vector(ten);
ones <= std_logic_vector(one);
end process;
end Behavioral;
|
gpl-2.0
|
c339cd60240357a9645fb0946725d213
| 0.527106 | 3.905612 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/frame_ctrl.vhd
| 1 | 62,070 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- F R A M E C O N T R O L L E R (frame_ctrl.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity frame_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
d : in frame_ctrl_in_type;
q : out frame_ctrl_out_type;
wbi : in wbm_in_type;
wbo : out wbm_out_type
);
end frame_ctrl;
architecture two_proc of frame_ctrl is
type state_type is (
idle, -- initial/reset state
opcode_check, -- check opcode, store frame id and check parity
-- parity check fails or opcode unknown
nack0, -- initiate transmission of NACK
nack1, -- wait until transmission done
-- acknowledge
ack0, -- initiate transmission of an ACK frame
ack1, -- wait until transmission done
-- MCU_SEL
mcu_select0, -- send reply
mcu_select1, -- wait until transmitted
mcu_select2, -- assert mcu select flag (enable_ctrl)
-- DETECT
detect0, -- send reply
detect1, -- wait until transmitted
-- REGISTER_WR
wr_init, -- send register write command and wait until acknowledged
wr_finish, -- finally clear receive buffer
-- For both MWR and AWR
multi_init, -- store total length, store full register address
-- REGISTER_MWR (writing multiple values in a row into one register)
mwr_process, -- 1st wishbone cycle step, central state
mwr_write1, -- 2nd wishbone cycle step, write data
mwr_write2, -- 3rd wishbone cycle step, de-assert control signals and return to reg_mwr_init
mwr_flush, -- flush rx buffer
mwr_wait, -- wait until receive buffer has further data
-- REGISTER_AWR (auto-address increment, writing multiple values in multiple adjacent registers)
awr_process, -- 1st wishbone cycle step, central state
awr_write1, -- 2nd wishbone cycle step, write data
awr_write2, -- 3rd wishbone cycle step, de-assert control signals and return to reg_mwr_init
awr_flush, -- flush rx buffer
awr_wait, -- wait until receive buffer has further data
-- REGISTER_RD
rd_init,
rd_buffer,
rdre_init,
rdre_finish,
-- REGISTER_MRD (multi-read: read a single register multiple times)
mrd_init1, -- send opcode and id, store address and length
mrd_init2, -- wait until tx buffer is done with opcode and id, clear rx buffer
mrd_process, -- 1st wishbone cycle step, central state
mrd_read1, -- 2nd wishbone read cycle step, read data
mrd_read2, -- 3rd wishbone read cycle step, reset control signals and increment counters
mrdre_forward, -- send data that were buffered in mrd_process
mrdre_wait, -- wait until tx buffer is done
mrd_finish1, -- init sending parity
mrd_finish2, -- wait until parity sent
-- REGISTER_ARD (auto-address-increment, reading multiple adjacent registers)
ard_init1, -- send opcode and id, store start address and length
ard_init2, -- wait until tx buffer is done with opcode and id, clear rx buffer
ard_process, -- 1st wishbone cycle step, central state
ard_read1, -- 2nd wishbone read cycle step. Read data
ard_read2, -- 3rd wishbone read cycle step. Reset control signals and increment counters
ardre_forward, -- send data that were buffered in ard_process
ardre_wait, -- wait until tx buffer is done
ard_finish1, -- init sending parity
ard_finish2, -- wait until parity sent
-- interrupts
int_init,
int_finish,
int_en
);
type reg_type is record
state : state_type;
rdre_buffer : std_logic_vector(WB_DW-1 downto 0);
ardre_buffer : std_logic_vector((FIFO_WIDTH*PROTO_WC_TX_MAX)-1 downto 0); -- used to buffer auto-address-increment
-- read data before forwarding to tx buffer
interrupt_en : std_logic;
timeout_cnt : integer range 0 to WB_TIMEOUT_CYCLES-1;
frame_id : std_logic_vector(FIFO_WIDTH-1 downto 0);
error_code : std_logic_vector(FIFO_WIDTH-1 downto 0);
start_address : std_logic_vector(WB_AW-1 downto 0); -- start address (mwr, awr and ard)
length : integer range 0 to REGISTER_DAT_MAX + REGISTER_MWR_LEN; -- total length of mwr/awr frames
-- data-only length of ard frames
process_cnt : integer range 0 to REGISTER_DAT_MAX; -- number of bytes already written (mwr/awr) or
-- number of reads (ard)
receive_cnt : integer range 1 to ((REGISTER_DAT_MAX + REGISTER_MWR_LEN) / 16) + 1; -- how many times the rx-buffer has asserted complete
next_byte_pos : integer range 0 to PROTO_WC_RX_MAX; -- position of the next byte to write
parity : std_logic_vector(FIFO_WIDTH-1 downto 0); -- stores a parity that is calculated in more than one state
end record;
signal reg_out, reg_in : reg_type;
begin
--===========================================================================--
COMBINATIONAL : process(d, reg_out, wbi)
--===========================================================================--
variable tmp : reg_type;
begin
tmp := reg_out; -- default assignments
case tmp.state is
--IDLE-------------------------------------------------------------------
when idle =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- reset register values
tmp.timeout_cnt := 0;
tmp.frame_id := x"00";
tmp.next_byte_pos := 0;
tmp.length := 0;
tmp.process_cnt := 0;
tmp.parity := (others => '0');
tmp.receive_cnt := 1;
tmp.ardre_buffer := (others => '-');
-- set error code to unknown
tmp.error_code := ERROR_UNKNOWN;
-- next state
if (wbi.girq = '1' AND tmp.interrupt_en = '1') then -- irq
tmp.state := int_init;
elsif (d.recbuf_complete = '1') then -- frame received
tmp.state := opcode_check;
else
tmp.state := idle;
end if;
--INT_INIT---------------------------------------------------------------
when int_init =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_valid <= '1';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- compose frame
q.trabuf_frame(q.trabuf_frame'length-1 downto 24) <= (others => '-');
q.trabuf_frame(23 downto 0) <=
wbi.int_adr & -- parity (= core address)
wbi.int_adr & -- core address (8 bit)
SOC_INT_OPC;
-- next state
if (d.trabuf_busy = '1') then
tmp.state := int_finish;
else
tmp.state := int_init;
end if;
--INT_FINISH-------------------------------------------------------------
when int_finish =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- disable interrupts (to avoid sending infinite interrupts)
tmp.interrupt_en := '0';
-- next state
if d.trabuf_busy = '1' then
tmp.state := int_finish;
else
tmp.state := idle;
end if;
--OPCODE_CHECK-----------------------------------------------------------
when opcode_check =>
-- outputs (the same as in idle)
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- store frame id
tmp.frame_id := d.recbuf_frame(15 downto 8);
-- mcu_select
if (d.recbuf_frame(7 downto 0) = MCU_SEL_OPC) then
-- parity check
if (( MCU_SEL_OPC xor
d.recbuf_frame(15 downto 8)) =
d.recbuf_frame(23 downto 16)) then
tmp.state := mcu_select0;
else
tmp.error_code := ERROR_PARITY;
tmp.state := nack0;
end if;
-- detect
elsif (d.recbuf_frame(7 downto 0) = DETECT_OPC) then
tmp.state := detect0;
-- soc_int_en
elsif (d.recbuf_frame(7 downto 0) = SOC_INT_EN_OPC) then
--assert false report "received SOC_INT_EN" severity note;
-- parity check
if (( SOC_INT_EN_OPC xor
d.recbuf_frame(15 downto 8)) =
d.recbuf_frame(23 downto 16)) then
tmp.state := int_en;
else
tmp.error_code := ERROR_PARITY;
tmp.state := nack0;
end if;
-- register_wr
elsif (d.recbuf_frame(7 downto 0) = REGISTER_WR_OPC) then
--assert false report "received REGISTER_WR" severity note;
-- parity check
if (( REGISTER_WR_OPC xor
d.recbuf_frame(15 downto 8) xor
d.recbuf_frame(23 downto 16) xor
d.recbuf_frame(31 downto 24) xor
d.recbuf_frame(39 downto 32)) =
d.recbuf_frame(47 downto 40)) then
tmp.state := wr_init;
else
tmp.error_code := ERROR_PARITY;
tmp.state := nack0;
end if;
-- register_mwr
elsif (d.recbuf_frame(7 downto 0) = REGISTER_MWR_OPC) then
--assert false report "received REGISTER_MWR" severity note;
tmp.state := multi_init;
-- register_awr
elsif (d.recbuf_frame(7 downto 0) = REGISTER_AWR_OPC) then
--assert false report "received REGISTER_AWR" severity note;
tmp.state := multi_init;
-- register_rd
elsif (d.recbuf_frame(7 downto 0) = REGISTER_RD_OPC) then
--assert false report "received REGISTER_RD" severity note;
-- parity check
if (( REGISTER_RD_OPC xor
d.recbuf_frame(15 downto 8) xor
d.recbuf_frame(23 downto 16) xor
d.recbuf_frame(31 downto 24)) =
d.recbuf_frame(39 downto 32)) then
tmp.state := rd_init;
else
tmp.error_code := ERROR_PARITY;
tmp.state := nack0;
end if;
-- register_mrd
elsif (d.recbuf_frame(7 downto 0) = REGISTER_MRD_OPC) then
--assert false report "received REGISTER_MRD" severity note;
-- parity check
if (( REGISTER_MRD_OPC xor
d.recbuf_frame(15 downto 8) xor
d.recbuf_frame(23 downto 16) xor
d.recbuf_frame(31 downto 24) xor
d.recbuf_frame(39 downto 32)) =
d.recbuf_frame(47 downto 40)) then
tmp.state := mrd_init1;
else
tmp.error_code := ERROR_PARITY;
tmp.state := nack0;
end if;
-- register_ard
elsif (d.recbuf_frame(7 downto 0) = REGISTER_ARD_OPC) then
--assert false report "received REGISTER_ARD" severity note;
-- parity check
if (( REGISTER_ARD_OPC xor
d.recbuf_frame(15 downto 8) xor
d.recbuf_frame(23 downto 16) xor
d.recbuf_frame(31 downto 24) xor
d.recbuf_frame(39 downto 32)) =
d.recbuf_frame(47 downto 40)) then
tmp.state := ard_init1;
else
tmp.error_code := ERROR_PARITY;
tmp.state := nack0;
end if;
-- unknown opcode: send nack after a timeout
else
-- stay in this state until timeout (use process_cnt for counting)
if (tmp.process_cnt < OPCODE_UNKNOWN_TIMEOUT) then
tmp.state := opcode_check;
tmp.process_cnt := tmp.process_cnt + 1;
else
assert false report "received unknown opcode, will now reply nack" severity warning;
-- send nack (assume correct ID reception)
tmp.error_code := ERROR_OPC_UNKNOWN;
tmp.state := nack0;
tmp.frame_id := d.recbuf_frame(15 downto 8);
end if;
end if;
--WR_INIT----------------------------------------------------------------
when wr_init =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= d.recbuf_frame(39 downto 32);
-- |--- core address ---| |--- register address ---|
wbo.adr <= d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24);
wbo.stb <= '1';
wbo.we <= '1';
wbo.cyc <= '1';
-- increment timeout counter
tmp.timeout_cnt := tmp.timeout_cnt + 1;
-- next state
if (wbi.ack = '1') then
tmp.state := wr_finish;
elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then
tmp.state := wr_init;
else -- timout
tmp.error_code := ERROR_WB_TIMEOUT;
tmp.state := nack0;
end if;
--WR_FINISH--------------------------------------------------------------
when wr_finish =>
-- outputs
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
tmp.state := ack0;
--MULTI_INIT-------------------------------------------------------------
when multi_init =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- store address
tmp.start_address := d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24);
-- store length
if (d.recbuf_frame(7 downto 0) = REGISTER_MWR_OPC) then
tmp.length := to_integer(unsigned(d.recbuf_frame(39 downto 32))) + REGISTER_MWR_LEN;
elsif (d.recbuf_frame(7 downto 0) = REGISTER_AWR_OPC) then
tmp.length := to_integer(unsigned(d.recbuf_frame(39 downto 32))) + REGISTER_AWR_LEN;
end if;
-- reset process counter (which is used as write-counter)
tmp.process_cnt := 0;
-- set initial byte position
tmp.next_byte_pos := 5;
-- one rx-buffer is already received, "reset" to one has been done in idle state
-- tmp.receive_cnt := 1;
-- calculate parity over opcode, id, both address bytes and length
tmp.parity := d.recbuf_frame(7 downto 0) xor
d.recbuf_frame(15 downto 8) xor
d.recbuf_frame(23 downto 16) xor
d.recbuf_frame(31 downto 24) xor
d.recbuf_frame(39 downto 32);
-- next state, proceed after 6 bytes received
if (d.recbuf_frame(7 downto 0) = REGISTER_MWR_OPC) then
tmp.state := mwr_process;
elsif (d.recbuf_frame(7 downto 0) = REGISTER_AWR_OPC) then
tmp.state := awr_process;
end if;
--MWR_PROCESS------------------------------------------------------------
when mwr_process =>
--outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
-- everything has been written, don't write the parity byte
if (tmp.length = REGISTER_MWR_LEN + tmp.process_cnt) then
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state will be flush, don't write
elsif (tmp.next_byte_pos = PROTO_WC_RX_MAX) then
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- init wishbone cycle
else
wbo.dat <= d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8);
wbo.adr <= tmp.start_address;
wbo.stb <= '1';
wbo.we <= '1';
wbo.cyc <= '1';
-- increment timeout counter
tmp.timeout_cnt := tmp.timeout_cnt + 1;
end if;
-- next state
-- if complete, enter wr_finish
if ((tmp.length = REGISTER_MWR_LEN + tmp.process_cnt) and -- length = overhead + write count --> all writes done
(tmp.receive_cnt * 16 >= tmp.length)) then -- potentially received bytes >= length --> all bytes (parity incl.) received
-- parity check
if (tmp.parity = d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8)) then
tmp.state := wr_finish;
else
tmp.error_code := ERROR_PARITY;
tmp.state := nack0;
end if;
-- enter flush when buffer processed but bytes left (byte position overruns buffer width)
elsif (tmp.next_byte_pos = PROTO_WC_RX_MAX) then
tmp.state := mwr_flush;
-- enter next_byte after core acknowledges, until then stay in this state unless timeout
elsif (wbi.ack = '1') then
-- xor data byte to parity
tmp.parity := tmp.parity xor d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8);
tmp.state := mwr_write1;
elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then
tmp.state := mwr_process;
else -- timeout
tmp.error_code := ERROR_WB_TIMEOUT;
tmp.state := nack0;
end if;
--MWR_WRITE1-------------------------------------------------------------
when mwr_write1 =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
-- 2nd wishbone cycle
wbo.dat <= d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8);
wbo.adr <= tmp.start_address;
wbo.stb <= '1';
wbo.we <= '1';
wbo.cyc <= '1';
-- next state
tmp.state := mwr_write2;
--MWR_WRITE2-------------------------------------------------------------
when mwr_write2 =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
-- 3rd wishbone cycle
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- increment write counter and byte position
tmp.process_cnt := tmp.process_cnt + 1;
tmp.next_byte_pos := tmp.next_byte_pos + 1;
-- reset timeout counter
tmp.timeout_cnt := 0;
-- next state
tmp.state := mwr_process;
--MWR_FLUSH--------------------------------------------------------------
when mwr_flush =>
-- outputs
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- start at the beginning after flush
tmp.next_byte_pos := 0;
-- next state
tmp.state := mwr_wait;
--MWR_WAIT---------------------------------------------------------------
when mwr_wait =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
if (d.recbuf_complete = '1') then
tmp.state := mwr_process;
-- after this state one more buffer is completely received
tmp.receive_cnt := tmp.receive_cnt + 1;
else
tmp.state := mwr_wait;
end if;
--AWR_PROCESS------------------------------------------------------------
when awr_process =>
--outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
-- everything has been written, don't write the parity byte
if (tmp.length = REGISTER_MWR_LEN + tmp.process_cnt) then
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state will be flush, don't write
elsif (tmp.next_byte_pos = PROTO_WC_RX_MAX) then
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- 1st wishbone cycle
else
wbo.dat <= d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8);
wbo.stb <= '1';
wbo.we <= '1';
wbo.cyc <= '1';
-- core address-part gets incremented by process_cnt (write counter)
wbo.adr <= tmp.start_address(WB_AW - 1 downto WB_AW - WB_REG_AW) &
std_logic_vector(to_unsigned(
to_integer(unsigned(tmp.start_address(WB_REG_AW - 1 downto 0))) + tmp.process_cnt
, WB_CORE_AW));
-- increment timeout counter
tmp.timeout_cnt := tmp.timeout_cnt + 1;
end if;
-- next state
-- if complete, enter wr_finish
if ((tmp.length = REGISTER_MWR_LEN + tmp.process_cnt) and -- length = overhead + write count AND --> all writes done
(tmp.receive_cnt * 16 >= tmp.length)) then -- potentially received bytes >= length --> all bytes (parity incl.) received
-- parity check
if (tmp.parity = d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8)) then
tmp.state := wr_finish;
else
tmp.error_code := ERROR_PARITY;
tmp.state := nack0;
end if;
-- enter flush when buffer processed but bytes left (byte position overruns buffer width)
elsif (tmp.next_byte_pos = PROTO_WC_RX_MAX) then
tmp.state := awr_flush;
-- enter next_byte after core acknowledges, until then stay in this state unless timeout
elsif (wbi.ack = '1') then
-- xor data byte to parity
tmp.parity := tmp.parity xor d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8);
tmp.state := awr_write1;
elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then
tmp.state := awr_process;
else -- timeout
tmp.error_code := ERROR_WB_TIMEOUT;
tmp.state := nack0;
end if;
--AWR_WRITE1-------------------------------------------------------------
when awr_write1 =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
-- 2nd wishbone cycle
wbo.dat <= d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8);
wbo.stb <= '1';
wbo.we <= '1';
wbo.cyc <= '1';
-- core address-part gets incremented by process_cnt (write counter)
wbo.adr <= tmp.start_address(WB_AW - 1 downto WB_AW - WB_REG_AW) &
std_logic_vector(to_unsigned(
to_integer(unsigned(tmp.start_address(WB_REG_AW - 1 downto 0))) + tmp.process_cnt
, WB_CORE_AW));
-- next state
tmp.state := awr_write2;
--AWR_WRITE2-------------------------------------------------------------
when awr_write2 =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
-- 3rd wishbone cycle
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- increment write counter and byte position
tmp.process_cnt := tmp.process_cnt + 1;
tmp.next_byte_pos := tmp.next_byte_pos + 1;
-- reset timeout counter
tmp.timeout_cnt := 0;
-- next state
tmp.state := awr_process;
--AWR_FLUSH--------------------------------------------------------------
when awr_flush =>
-- outputs
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- start at the beginning after flush
tmp.next_byte_pos := 0;
-- next state
tmp.state := awr_wait;
--AWR_WAIT---------------------------------------------------------------
when awr_wait =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
if (d.recbuf_complete = '1') then
tmp.state := awr_process;
-- after this state one more buffer is completely received
tmp.receive_cnt := tmp.receive_cnt + 1;
else
tmp.state := awr_wait;
end if;
--RD_INIT----------------------------------------------------------------
when rd_init =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
-- |--- core address ---| |--- register address ---|
wbo.adr <= d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24);
wbo.stb <= '1';
wbo.we <= '0';
wbo.cyc <= '1';
-- increment timeout counter
tmp.timeout_cnt := tmp.timeout_cnt + 1;
-- next state: wait until slave acknowledges
if (wbi.ack = '1') then
tmp.state := rd_buffer;
elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then
tmp.state := rd_init;
else -- timeout
tmp.error_code := ERROR_WB_TIMEOUT;
tmp.state := nack0;
end if;
--RD_BUFFER--------------------------------------------------------------
when rd_buffer =>
-- outputs: clear recbuf, store reply in buffer
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
-- |--- core address ---| |--- register address ---|
wbo.adr <= d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24);
wbo.stb <= '1';
wbo.we <= '0';
wbo.cyc <= '1';
-- store reply in buffer
tmp.rdre_buffer := wbi.dat;
-- next state
tmp.state := rdre_init;
--RDRE_INIT--------------------------------------------------------------
when rdre_init =>
-- outputs: send REGISTER_RDRE to trabuf, close wb cycle
-- compose frame
q.trabuf_frame(7 downto 0) <= REGISTER_RDRE_OPC; -- opcode
q.trabuf_frame(15 downto 8) <= tmp.frame_id; -- frame id
q.trabuf_frame(23 downto 16) <= tmp.rdre_buffer(7 downto 0); -- data
q.trabuf_frame(31 downto 24) <= REGISTER_RDRE_OPC XOR -- parity
tmp.frame_id XOR
tmp.rdre_buffer(7 downto 0);
q.trabuf_frame(q.trabuf_frame'length-1 downto 32) <= (others => '-');
q.trabuf_valid <= '1';
q.trabuf_length <= 0;
q.recbuf_clear <= '1';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: Wait until trabuf is busy
if (d.trabuf_busy = '1') then
tmp.state := rdre_finish;
else
tmp.state := rdre_init;
end if;
--RDRE_FINISH------------------------------------------------------------
when rdre_finish =>
-- outputs
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: Wait until trabuf is done
if (d.trabuf_busy = '1') then
tmp.state := rdre_finish;
else
tmp.state := idle;
end if;
--MRD_INIT1--------------------------------------------------------------
when mrd_init1 =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
-- already transmit opcode and id
q.trabuf_valid <= '1';
q.trabuf_length <= 2;
q.trabuf_frame(q.trabuf_frame'length-1 downto 16) <= (others => '-');
q.trabuf_frame(15 downto 0) <=
d.recbuf_frame(15 downto 8) & -- id
REGISTER_MRDRE_OPC;
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- init parity
tmp.parity := REGISTER_MRDRE_OPC xor d.recbuf_frame(15 downto 8); -- opc xor id
-- store address
tmp.start_address := d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24);
-- store length
tmp.length := to_integer(unsigned(d.recbuf_frame(39 downto 32)));
-- reset process (read) counter and next byte position
tmp.process_cnt := 0;
tmp.next_byte_pos := 0;
-- next state: proceed when trabuf is busy
if (d.trabuf_busy = '1') then
tmp.state := mrd_init2;
else
tmp.state := mrd_init1;
end if;
--MRD_INIT2--------------------------------------------------------------
when mrd_init2 =>
-- outputs
q.recbuf_clear <= '1';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '0';
q.trabuf_length <= 2;
q.trabuf_frame <= (others => '-');
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: proceed when trabuf done
if (d.trabuf_busy = '0') then
tmp.state := mrd_process;
else
tmp.state := mrd_init2;
end if;
--MRD_PROCESS------------------------------------------------------------
when mrd_process =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '0';
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.trabuf_frame <= (others => '-');
-- if mrdre buffer is full
if (tmp.next_byte_pos = PROTO_WC_TX_MAX) then
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- if there is data left to read
elsif (tmp.process_cnt < tmp.length) then
-- 1st wishbone read cycle
wbo.adr <= tmp.start_address;
wbo.dat <= (others => '-');
wbo.stb <= '1';
wbo.we <= '0';
wbo.cyc <= '1';
-- buffer is not full, but there is no data to read
else
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
end if;
-- increment wishbone timeout counter
tmp.timeout_cnt := tmp.timeout_cnt + 1;
-- next state
if (not (tmp.length = 0)) then
-- forward if mrdre buffer is full ...
if (tmp.next_byte_pos = PROTO_WC_TX_MAX) then
-- wait here when tx buffer is busy
if (d.trabuf_busy = '0') then
tmp.state := mrdre_forward;
else
tmp.state := mrd_process;
end if;
-- ... or if processing has finish (all data read)
elsif (tmp.process_cnt = tmp.length) then
tmp.state := mrdre_forward;
elsif (wbi.ack = '1') then
tmp.state := mrd_read1;
elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then
tmp.state := mrd_process;
else -- timeout
tmp.error_code := ERROR_WB_TIMEOUT;
tmp.state := nack0;
end if;
-- if length = 0
else
tmp.state := mrd_finish1;
end if;
--MRD_READ1--------------------------------------------------------------
when mrd_read1 =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '0';
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.trabuf_frame <= (others => '-');
-- 2nd wishbone read cycle
wbo.adr <= tmp.start_address;
wbo.dat <= (others => '-');
wbo.stb <= '1';
wbo.we <= '0';
wbo.cyc <= '1';
-- buffer register content
tmp.ardre_buffer(((tmp.next_byte_pos*FIFO_WIDTH) + 7) downto (tmp.next_byte_pos*FIFO_WIDTH)) := wbi.dat;
-- update parity
tmp.parity := tmp.parity xor wbi.dat;
-- next state
tmp.state := mrd_read2;
--MRD_READ2--------------------------------------------------------------
when mrd_read2 =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '0';
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.trabuf_frame <= (others => '-');
-- 3rd wishbone read cycle
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- increment process (read) counter and next byte position
tmp.process_cnt := tmp.process_cnt + 1;
tmp.next_byte_pos := tmp.next_byte_pos + 1;
-- reset wishbone timeout counter
tmp.timeout_cnt := 0;
-- next state
tmp.state := mrd_process;
--MRDRE_WAIT-------------------------------------------------------------
when mrdre_wait =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '0';
q.trabuf_length <= tmp.next_byte_pos;
q.trabuf_frame <= tmp.ardre_buffer;
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state, proceed when transmit buffer is done
if (d.trabuf_busy = '0') then
-- if there is data left to read
if (tmp.process_cnt < tmp.length) then
tmp.next_byte_pos := 0;
tmp.state := mrd_process;
else
tmp.state := mrd_finish1;
end if;
else
tmp.state := mrdre_wait;
end if;
--MRD_FINISH1------------------------------------------------------------
when mrd_finish1 =>
-- outputs
q.recbuf_clear <= '1';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '1';
q.trabuf_length <= 1;
q.trabuf_frame(q.trabuf_frame'length-1 downto 8) <= (others => '-');
q.trabuf_frame(7 downto 0) <= tmp.parity;
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
if (d.trabuf_busy = '1') then
tmp.state := mrd_finish2;
else
tmp.state := mrd_finish1;
end if;
--MRD_FINISH2------------------------------------------------------------
when mrd_finish2 =>
-- outputs
q.recbuf_clear <= '1';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '0';
q.trabuf_length <= 1;
q.trabuf_frame(q.trabuf_frame'length-1 downto 8) <= (others => '-');
q.trabuf_frame(7 downto 0) <= tmp.parity;
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
if (d.trabuf_busy = '1') then
tmp.state := mrd_finish2;
else
tmp.state := idle;
end if;
--MRDRE_FORWARD----------------------------------------------------------
when mrdre_forward =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '1';
q.trabuf_length <= tmp.next_byte_pos;
q.trabuf_frame <= tmp.ardre_buffer;
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
tmp.state := mrdre_wait;
--ARD_INIT1--------------------------------------------------------------
when ard_init1 =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
-- already transmit opcode and id
q.trabuf_valid <= '1';
q.trabuf_length <= 2;
q.trabuf_frame(q.trabuf_frame'length-1 downto 16) <= (others => '-');
q.trabuf_frame(15 downto 0) <=
d.recbuf_frame(15 downto 8) & -- id
REGISTER_ARDRE_OPC;
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- init parity
tmp.parity := REGISTER_ARDRE_OPC xor d.recbuf_frame(15 downto 8);
-- store start address
tmp.start_address := d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24);
-- store length
tmp.length := to_integer(unsigned(d.recbuf_frame(39 downto 32)));
-- reset process (read) counter and next byte position
tmp.process_cnt := 0;
tmp.next_byte_pos := 0;
-- next state: proceed when trabuf is busy
if (d.trabuf_busy = '1') then
tmp.state := ard_init2;
else
tmp.state := ard_init1;
end if;
--ARD_INIT2--------------------------------------------------------------
when ard_init2 =>
-- outputs
q.recbuf_clear <= '1';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '0';
q.trabuf_length <= 2;
q.trabuf_frame <= (others => '-');
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: proceed when trabuf done
if (d.trabuf_busy = '0') then
tmp.state := ard_process;
else
tmp.state := ard_init2;
end if;
--ARD_PROCESS------------------------------------------------------------
when ard_process =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '0';
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.trabuf_frame <= (others => '-');
-- if ardre buffer is full
if (tmp.next_byte_pos = PROTO_WC_TX_MAX) then
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- if there is data left to read
elsif (tmp.process_cnt < tmp.length) then
-- 1st wishbone read cycle
wbo.adr <=
tmp.start_address(WB_AW-1 downto WB_CORE_AW) &
std_logic_vector(to_unsigned((to_integer(unsigned(tmp.start_address(WB_CORE_AW-1 downto 0))) + tmp.process_cnt), WB_CORE_AW));
wbo.dat <= (others => '-');
wbo.stb <= '1';
wbo.we <= '0';
wbo.cyc <= '1';
-- buffer is not full, but there is no data to read
else
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
end if;
-- increment wishbone timeout counter
tmp.timeout_cnt := tmp.timeout_cnt + 1;
-- next state
if (not (tmp.length = 0)) then
-- forward if ardre buffer is full ...
if (tmp.next_byte_pos = PROTO_WC_TX_MAX) then
-- wait here when tx buffer is busy
if (d.trabuf_busy = '0') then
tmp.state := ardre_forward;
else
tmp.state := ard_process;
end if;
-- ... or if processing has finish (all data read)
elsif (tmp.process_cnt = tmp.length) then
tmp.state := ardre_forward;
elsif (wbi.ack = '1') then
tmp.state := ard_read1;
elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then
tmp.state := ard_process;
else -- timeout
tmp.error_code := ERROR_WB_TIMEOUT;
tmp.state := nack0;
end if;
-- if length = 0
else
tmp.state := ard_finish1;
end if;
--ARD_READ1--------------------------------------------------------------
when ard_read1 =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '0';
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.trabuf_frame <= (others => '-');
-- 2nd wishbone read cycle
wbo.adr <=
tmp.start_address(WB_AW-1 downto WB_CORE_AW) &
std_logic_vector(to_unsigned((to_integer(unsigned(tmp.start_address(WB_CORE_AW-1 downto 0))) + tmp.process_cnt), WB_CORE_AW));
wbo.dat <= (others => '-');
wbo.stb <= '1';
wbo.we <= '0';
wbo.cyc <= '1';
-- buffer register content
tmp.ardre_buffer(((tmp.next_byte_pos*FIFO_WIDTH) + 7) downto (tmp.next_byte_pos*FIFO_WIDTH)) := wbi.dat;
-- update parity
tmp.parity := tmp.parity xor wbi.dat;
-- next state
tmp.state := ard_read2;
--ARD_READ2--------------------------------------------------------------
when ard_read2 =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '0';
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.trabuf_frame <= (others => '-');
-- 3rd wishbone read cycle
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- increment process (read) counter and next byte position
tmp.process_cnt := tmp.process_cnt + 1;
tmp.next_byte_pos := tmp.next_byte_pos + 1;
-- reset wishbone timeout counter
tmp.timeout_cnt := 0;
-- next state
tmp.state := ard_process;
--ARDRE_FORWARD----------------------------------------------------------
when ardre_forward =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '1';
q.trabuf_length <= tmp.next_byte_pos;
q.trabuf_frame <= tmp.ardre_buffer;
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
tmp.state := ardre_wait;
--ARDRE_WAIT-------------------------------------------------------------
when ardre_wait =>
-- outputs
q.recbuf_clear <= '0';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '0';
q.trabuf_length <= tmp.next_byte_pos;
q.trabuf_frame <= tmp.ardre_buffer;
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state, proceed when transmit buffer is done
if (d.trabuf_busy = '0') then
-- if there is data left to read
if (tmp.process_cnt < tmp.length) then
tmp.next_byte_pos := 0;
tmp.state := ard_process;
else
tmp.state := ard_finish1;
end if;
else
tmp.state := ardre_wait;
end if;
--ARD_FINISH1------------------------------------------------------------
when ard_finish1 =>
-- outputs
q.recbuf_clear <= '1';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '1';
q.trabuf_length <= 1;
q.trabuf_frame(q.trabuf_frame'length-1 downto 8) <= (others => '-');
q.trabuf_frame(7 downto 0) <= tmp.parity;
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
if (d.trabuf_busy = '1') then
tmp.state := ard_finish2;
else
tmp.state := ard_finish1;
end if;
--ARD_FINISH2------------------------------------------------------------
when ard_finish2 =>
-- outputs
q.recbuf_clear <= '1';
q.mcu_select <= '0';
q.transmitter_mode <= '1';
q.trabuf_valid <= '0';
q.trabuf_length <= 1;
q.trabuf_frame(q.trabuf_frame'length-1 downto 8) <= (others => '-');
q.trabuf_frame(7 downto 0) <= tmp.parity;
wbo.adr <= (others => '-');
wbo.dat <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
if (d.trabuf_busy = '1') then
tmp.state := ard_finish2;
else
tmp.state := idle;
end if;
--NACK0------------------------------------------------------------------
when nack0 =>
-- outputs
-- compose frame
q.trabuf_frame(7 downto 0) <= NACK_OPC; -- opcode
q.trabuf_frame(15 downto 8) <= tmp.frame_id; -- frame id
q.trabuf_frame(23 downto 16) <= tmp.error_code; -- error code
q.trabuf_frame(31 downto 24) <= NACK_OPC XOR -- parity
tmp.frame_id XOR
tmp.error_code;
q.trabuf_frame(q.trabuf_frame'length-1 downto 32) <= (others => '-');
q.recbuf_clear <= '1';
q.trabuf_valid <= '1';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: wait until transmission buffer is busy
if (d.trabuf_busy = '1') then
tmp.state := nack1;
else
tmp.state := nack0;
end if;
--NACK1------------------------------------------------------------------
when nack1 =>
-- outputs
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: wait until transmission buffer is done
if (d.trabuf_busy = '1') then
tmp.state := nack1;
else
tmp.state := idle;
end if;
--ACK0-------------------------------------------------------------------
when ack0 =>
-- outputs
-- compose frame
q.trabuf_frame(7 downto 0) <= ACK_OPC; -- opcode
q.trabuf_frame(15 downto 8) <= tmp.frame_id; -- frame id
q.trabuf_frame(23 downto 16) <= ACK_OPC XOR tmp.frame_id; -- parity
q.trabuf_frame(q.trabuf_frame'length-1 downto 24) <= (others => '-');
q.recbuf_clear <= '1';
q.trabuf_valid <= '1';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: wait until transmission buffer is busy
if (d.trabuf_busy = '1') then
tmp.state := ack1;
else
tmp.state := ack0;
end if;
--ACK1-------------------------------------------------------------------
when ack1 =>
-- outputs
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: wait until transmission buffer is done
if (d.trabuf_busy = '1') then
tmp.state := ack1;
else
tmp.state := idle;
end if;
--MCU_SELECT0 : Send reply-----------------------------------------------
when mcu_select0 =>
-- outputs
-- compose frame
q.trabuf_frame(7 downto 0) <= ACK_OPC; -- opcode
q.trabuf_frame(15 downto 8) <= tmp.frame_id; -- frame id
q.trabuf_frame(23 downto 16) <= ACK_OPC XOR tmp.frame_id; -- parity
q.trabuf_frame(q.trabuf_frame'length-1 downto 24) <= (others => '-');
q.recbuf_clear <= '1';
q.trabuf_valid <= '1';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: wait until transmission buffer is busy
if (d.trabuf_busy = '1') then
tmp.state := mcu_select1;
else
tmp.state := mcu_select0;
end if;
--MCU_SELECT1 : Wait until transmitted-----------------------------------
when mcu_select1 =>
-- outputs
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: wait until transmission buffer is done
if (d.trabuf_busy = '1') then
tmp.state := mcu_select1;
else
tmp.state := mcu_select2;
end if;
--MCU_SELECT2 : Switch to MCU--------------------------------------------
when mcu_select2 =>
-- outputs (mcu_select and recbuf_clear asserted)
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '1';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state
tmp.state := idle;
--DETECT0 : Transmit reply-----------------------------------------------
when detect0 =>
-- reply frame
q.trabuf_frame(7 downto 0) <= DETECT_REPLY_OPC; -- opcode
q.trabuf_frame(15 downto 8) <= DETECT_REPLY_FPGA; -- fpga identifier
q.trabuf_frame(23 downto 16) <= DETECT_REPLY_OPC XOR DETECT_REPLY_FPGA;
q.trabuf_frame(q.trabuf_frame'length-1 downto 24) <= (others => '-');
-- outputs
q.recbuf_clear <= '1';
q.trabuf_valid <= '1';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: wait until transmission buffer is busy
if (d.trabuf_busy = '1') then
tmp.state := detect1;
else
tmp.state := detect0;
end if;
--DETECT1 : Wait until transmitted---------------------------------------
when detect1 =>
-- outputs
q.recbuf_clear <= '1';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '1';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- next state: wait until transmission buffer is done
if (d.trabuf_busy = '1') then
tmp.state := detect1;
else
tmp.state := idle;
end if;
--SOC_INT_EN-------------------------------------------------------------
when int_en =>
-- outputs
q.recbuf_clear <= '0';
q.trabuf_frame <= (others => '-');
q.trabuf_valid <= '0';
q.trabuf_length <= 0;
q.mcu_select <= '0';
q.transmitter_mode <= '0';
wbo.dat <= (others => '-');
wbo.adr <= (others => '-');
wbo.stb <= '0';
wbo.we <= '0';
wbo.cyc <= '0';
-- store frame id
tmp.frame_id := d.recbuf_frame(15 downto 8);
-- enable interrupts
tmp.interrupt_en := '1';
-- next state
tmp.state := ack0;
end case;
-------------------------------------------------------------------------
reg_in <= tmp; -- drive register inputs
end process COMBINATIONAL;
--===========================================================================--
REGISTERS : process(clk,rst)
--===========================================================================--
begin
if rising_edge(clk) then
if (rst = '1') then
reg_out.state <= idle;
else
reg_out <= reg_in;
end if;
end if;
end process REGISTERS;
end two_proc;
|
gpl-3.0
|
10fd406de30e3805e27790e2519d1c1b
| 0.429451 | 4.076044 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/tb/tb_serport_uart_rx.vhd
| 1 | 9,874 |
-- $Id: tb_serport_uart_rx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_uart_rx - sim
-- Description: Test bench for serport_uart_rx
--
-- Dependencies: simlib/simclk
-- tbd_serport_uart_rx [UUT]
--
-- To test: serport_uart_rx
--
-- Target Devices: generic
--
-- Verified (with tb_serport_uart_rx_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (63488 cl 15.21s)
-- 2007-10-21 91 - 0.26 - - c:ok (63488 cl 7.12s)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0.3 now numeric_std clean
-- 2010-04-24 281 1.0.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serport.all;
entity tb_serport_uart_rx is
end tb_serport_uart_rx;
architecture sim of tb_serport_uart_rx is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv5 := slv(to_unsigned(15, 5));
signal RXSD : slbit := '1';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal N_MON_VAL : slbit := '0';
signal N_MON_ERR : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_ERR_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_ERR_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
UUT : entity work.tbd_serport_uart_rx
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_uart_rx_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable irxerr : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable irate : integer := 16;
type bit_10_array_type is array (0 to 9) of slbit;
type int_10_array_type is array (0 to 9) of integer;
variable valpuls : bit_10_array_type := (others=>'0');
variable delpuls : int_10_array_type := (others=>0);
variable npuls : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
idelta := 0;
while RXACT='1' loop -- ensure that uart isn't active
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
read_ea(iline, irate);
wait for 2*clock_period;
CLKDIV <= slv(to_unsigned(irate-1, CLKDIV'length));
wait for 2*clock_period;
when ".xrate" => -- .xrate
read_ea(iline, irate);
when "puls " => -- puls
writetimestamp(oline, CLK_CYCLE, ": puls ");
read_ea(iline, irxval);
read_ea(iline, irxerr);
read_ea(iline, irxdata);
npuls := 0;
for i in valpuls'range loop
testempty(iline, ok);
if ok then
exit;
end if;
read_ea(iline, valpuls(i));
read_ea(iline, delpuls(i));
assert delpuls(i)>0
report "assert puls length > 0" severity failure;
npuls := npuls + 1;
write(oline, valpuls(i), right, 3);
write(oline, delpuls(i), right, 3);
end loop; -- i
writeline(output, oline);
if npuls > 0 then
N_MON_VAL <= irxval;
N_MON_ERR <= irxerr;
N_MON_DAT <= irxdata;
for i in 0 to npuls-1 loop
RXSD <= valpuls(i);
wait for clock_period;
N_MON_VAL <= '0';
wait for (delpuls(i)-1)*clock_period;
end loop; -- i
end if;
when "send " => -- send
read_ea(iline, idelta);
read_ea(iline, itxdata);
RXSD <= '1';
wait for idelta*clock_period;
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
N_MON_VAL <= '1';
N_MON_ERR <= '0';
N_MON_DAT <= itxdata;
RXSD <= '0'; -- start bit
wait for clock_period;
N_MON_VAL <= '0';
wait for (irate-1)*clock_period;
RXSD <= '1';
for i in itxdata'reverse_range loop -- transmit lsb first
RXSD <= itxdata(i); -- data bit
wait for irate*clock_period;
end loop;
RXSD <= '1'; -- stop bit
wait for irate*clock_period;
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
idelta := 0;
while RXACT='1' loop
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 12*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING ERR="));
write(oline, R_MON_ERR_2);
write(oline, string'(" DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_ERR_2 <= R_MON_ERR_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_ERR_1 <= N_MON_ERR;
R_MON_DAT_1 <= N_MON_DAT;
if RXVAL='1' or RXERR='1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_ERR_2 = '0' then
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
else
if RXERR = '1' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, RXERR=1 expected"));
end if;
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
1af2c20d95539224171f66037412854a
| 0.499494 | 3.828616 | false | false | false | false |
willprice/build-a-comp-vhdl-modules
|
base/tests/RightShiftTests.vhd
| 1 | 1,314 |
library ieee, base;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use base.base.all;
entity RightShiftTests is
end entity RightShiftTests;
architecture TB of RightShiftTests is
component RightShift
port(c_in : in unsigned(3 downto 0) := "0001";
c_out : out unsigned(3 downto 0);
data_in : in unsigned(3 downto 0);
data_out : out unsigned(3 downto 0));
end component RightShift;
for uut : RightShift use entity work.RightShift(Behavioural);
signal c_in : unsigned(3 downto 0) := "0000";
signal c_out : unsigned(3 downto 0) := "0000";
signal data_in : unsigned(3 downto 0) := "0000";
signal data_out : unsigned(3 downto 0) := "0000";
begin
-- Unit under test
uut : RightShift
port map(c_in => c_in,
c_out => c_out,
data_in => data_in,
data_out => data_out);
test : process
begin
wait_for_sim_setup;
c_in <= "0011";
wait for 10 ns;
assert_equal(c_out, "0011");
c_in <= "0001";
data_in <= "0001";
wait for 10 ns;
assert_equal(data_out, "0000");
c_in <= "0001";
data_in <= "0010";
wait for 10 ns;
assert_equal(data_out, "0001");
c_in <= "0100";
data_in <= "0010";
wait for 10 ns;
assert_equal(data_out, "0010");
report "Test complete";
wait;
end process;
end architecture TB;
|
mit
|
a9933812dfb56c7df3d6a6335ed87db0
| 0.618721 | 2.894273 | false | true | false | false |
os-cillation/easyfpga-soc
|
easy_cores/gpio/gpio8.vhd
| 1 | 5,557 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- 8 - B I T G P I O E A S Y C O R E
-- (gpio8.vhd)
--
-- Structural
--
-- Adapts the verilog gpio module to vhdl and the wbs/wbm types
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
ENTITY gpio8 is
-------------------------------------------------------------------------------
port (
-- WISHBONE interface (with clock input)
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- GPIO pins
gpio0 : inout std_logic;
gpio1 : inout std_logic;
gpio2 : inout std_logic;
gpio3 : inout std_logic;
gpio4 : inout std_logic;
gpio5 : inout std_logic;
gpio6 : inout std_logic;
gpio7 : inout std_logic
);
end gpio8;
-------------------------------------------------------------------------------
ARCHITECTURE structural of gpio8 is
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
COMPONENT gpio_top is
-- this component is the link to the verilog module.
-- here, the signal names from simple_spi_top.v are used
-------------------------------------------------------------------------------
port (
-- WISHBONE interface
wb_clk_i : in std_logic; -- clock
wb_rst_i : in std_logic; -- reset (asynchronous active low)
wb_cyc_i : in std_logic; -- cycle
wb_stb_i : in std_logic; -- strobe
wb_adr_i : in std_logic_vector(7 downto 0); -- address
wb_we_i : in std_logic; -- write enable
wb_dat_i : in std_logic_vector(31 downto 0);-- data input
wb_dat_o : out std_logic_vector(31 downto 0);-- data output
wb_ack_o : out std_logic; -- bus termination
wb_inta_o : out std_logic; -- interrupt output
wb_sel_i : in std_logic_vector(3 downto 0); -- byte select (constant "0001")
-- GPIO interface
ext_pad_o : out std_logic_vector(7 downto 0); -- GPIO outputs
ext_pad_i : in std_logic_vector(7 downto 0); -- GPIO inputs
ext_padoe_o : out std_logic_vector(7 downto 0) -- output driver enables
);
END COMPONENT;
signal ext_pad_i_s : std_logic_vector(7 downto 0);
signal ext_pad_o_s : std_logic_vector(7 downto 0);
signal ext_padoe_o_s : std_logic_vector(7 downto 0);
signal dat_i_tmp_s : std_logic_vector(31 downto 0);
signal dat_o_tmp_s : std_logic_vector(31 downto 0);
signal wb_sel_s : std_logic_vector(3 downto 0);
--------------------------------------------------------------------------------
begin -- architecture structural
-------------------------------------------------------------------------------
-- data width adaption
dat_i_tmp_s <= x"000000" & wbs_in.dat;
wbs_out.dat <= dat_o_tmp_s(7 downto 0);
-- constant byte selection lines
wb_sel_s <= "0001";
-- tristate-able drivers
ext_pad_i_s(0) <= gpio0;
gpio0 <= 'Z' when ext_padoe_o_s(0) = '0' else ext_pad_o_s(0);
ext_pad_i_s(1) <= gpio1;
gpio1 <= 'Z' when ext_padoe_o_s(1) = '0' else ext_pad_o_s(1);
ext_pad_i_s(2) <= gpio2;
gpio2 <= 'Z' when ext_padoe_o_s(2) = '0' else ext_pad_o_s(2);
ext_pad_i_s(3) <= gpio3;
gpio3 <= 'Z' when ext_padoe_o_s(3) = '0' else ext_pad_o_s(3);
ext_pad_i_s(4) <= gpio4;
gpio4 <= 'Z' when ext_padoe_o_s(4) = '0' else ext_pad_o_s(4);
ext_pad_i_s(5) <= gpio5;
gpio5 <= 'Z' when ext_padoe_o_s(5) = '0' else ext_pad_o_s(5);
ext_pad_i_s(6) <= gpio6;
gpio6 <= 'Z' when ext_padoe_o_s(6) = '0' else ext_pad_o_s(6);
ext_pad_i_s(7) <= gpio7;
gpio7 <= 'Z' when ext_padoe_o_s(7) = '0' else ext_pad_o_s(7);
-------------------------------------------------------------------------------
GPIO_CORE : gpio_top
-------------------------------------------------------------------------------
port map (
-- WISHBONE interface
wb_clk_i => wbs_in.clk,
wb_rst_i => wbs_in.rst,
wb_cyc_i => wbs_in.cyc,
wb_stb_i => wbs_in.stb,
wb_adr_i => wbs_in.adr(7 downto 0),
wb_we_i => wbs_in.we,
wb_dat_i => dat_i_tmp_s,
wb_dat_o => dat_o_tmp_s,
wb_ack_o => wbs_out.ack,
wb_inta_o => wbs_out.irq,
wb_sel_i => wb_sel_s,
-- GPIO interface
ext_pad_o => ext_pad_o_s,
ext_pad_i => ext_pad_i_s,
ext_padoe_o => ext_padoe_o_s
);
end structural;
|
gpl-3.0
|
a222916e033cf812c52c8a0efead53a1
| 0.482455 | 3.451553 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd
| 1 | 9,364 |
-- $Id: sys_tst_rlink_n3.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n3 - syn
-- Description: rlink tester design for nexys3
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-18 440 13.1 O40d xc6slx16-2 752 1258 48 439 t 7.9
-- 2011-11-26 433 13.1 O40d xc6slx16-2 722 1199 36 423 t 9.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-18 440 1.1.1 use [rt]xok for DSP_DP
-- 2011-12-11 438 1.1 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_n3;
architecture syn of sys_tst_rlink_n3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
gpl-2.0
|
6204a32a074f5d139e8ec4b3d72054b7
| 0.496476 | 3.189373 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/pdp11_ounit.vhd
| 2 | 3,982 |
-- $Id: pdp11_ounit.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ounit - syn
-- Description: pdp11: arithmetic unit for addresses (ounit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end pdp11_ounit;
architecture syn of pdp11_ounit is
-- --------------------------------------
begin
process (DSRC, DDST, DTMP, PC, ASEL, AZERO,
IREG8, VMDOUT, CONST, BSEL, OPSUB)
variable ma : slv16 := (others=>'0'); -- effective port a data
variable mb : slv16 := (others=>'0'); -- effective port b data
variable sum : slv16 := (others=>'0'); -- sum
variable nzo : slbit := '0';
begin
if AZERO = '0' then
case ASEL is
when c_ounit_asel_dsrc => ma := DSRC;
when c_ounit_asel_ddst => ma := DDST;
when c_ounit_asel_dtmp => ma := DTMP;
when c_ounit_asel_pc => ma := PC;
when others => null;
end case;
else
ma := (others=>'0');
end if;
case BSEL is
when c_ounit_bsel_ireg6 => mb := "000000000" & IREG8(5 downto 0) & "0";
when c_ounit_bsel_ireg8 => mb := IREG8(7) & IREG8(7) & IREG8(7) &
IREG8(7) & IREG8(7) & IREG8(7) &
IREG8(7) & IREG8 & "0";
when c_ounit_bsel_vmdout => mb := VMDOUT;
when c_ounit_bsel_const => mb := "0000000" & CONST;
when others => null;
end case;
if OPSUB = '0' then
sum := slv(unsigned(ma) + unsigned(mb));
else
sum := slv(unsigned(ma) - unsigned(mb));
end if;
nzo := '0';
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
DOUT <= sum;
NZOUT(1) <= sum(15);
NZOUT(0) <= nzo;
end process;
end syn;
|
gpl-2.0
|
ad449c02150b1e06ee9e6e3b005a2adb
| 0.507032 | 3.785171 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL source files/PENDANT_DECODER.vhd
| 1 | 30,991 |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
--
-- File: PENDANT_DECODER.vhd
-- File history:
-- <1.0>: <24/03/2015>: <Only Mode and Axis>
-- <2.0>: <25/03/2015>: <Buttons F1-F3, +,- , ampersand>
-- <3.0>: <03/04/2015>: <Improvements and corrections made. Release version>
--
-- Description:
--
-- <Module decodes pendant signals and set flags to External data controller>
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--
--------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity PENDANT_DECODER is
GENERIC(
COUNTER_WIDTH : INTEGER := 11 -- UART write mode duration
);
-- 01bit counter -> 51 us period clock 19,5 kHz
-- 02bit counter -> 102 us period clock 9,75 kHz
-- 03bit counter -> 204 us period clock 4,8 kHz
-- 04bit counter -> 409 us period clock 2,4 kHz
-- 05bit counter -> 820 us period clock 1,2 kHz
-- 06bit counter -> 1.6 ms period clock 610 Hz
-- 07bit counter -> 3.2 ms period clock 305 Hz
-- 08bit counter -> 6.5 ms period clock 152 Hz
-- 09bit counter -> 13 ms period clock 76 Hz
-- 10bit counter -> 26 ms period clock 38 Hz
-- 11bit counter -> 52 ms period clock 19 Hz
-- 12bit counter -> 104 ms period clock 9,5 Hz
-- 13bit counter -> 209 ms period clock 4,75 Hz
-- 14bit counter -> 419 ms period clock 2,35 Hz
-- 15bit counter -> 838 ms period clock 1,2 Hz
port (
RESET_N : in std_logic; -- RESET. Active low.
SCLK_IN : in std_logic; -- External SCLK 50 Mhz
SCLK_LF_IN : in std_logic; -- External SCLK 10 Mhz
SCLK_Khz_IN : in std_logic; -- External SCLK xx Khz
UART_DATA1_IN : in std_logic_vector(7 downto 0); -- Data FROM pendant
UART_DATA2_IN : in std_logic_vector(7 downto 0); -- Data FROM pendant
Disp_axis_reg : in std_logic_vector(23 downto 0); -- Data FROM PMAC (confirmation of axis and mode selection)
LED_reg : in std_logic_vector(23 downto 0); -- Data FROM PMAC (indicators on programmable LEDs)
sw1 : in std_logic; --switch 1
sw2 : in std_logic; --switch 2
Current_axis_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
Speed_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
Button_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
UART_DATA_OUT : out std_logic_vector(7 downto 0); -- Data TO pendant (Axis and mode)
UART_Tx_Gate : out std_logic; -- latch UART data in external Tx registers (buttons confirmation)
UART_Write_mode : out std_logic; -- enter UART transmit mode
UART_DATA_OUT2 : out std_logic_vector(23 downto 0); -- Data TO pendant (LED control, 3x 8 bit)
UART_Tx_Gate2 : out std_logic; -- latch UART data in external Tx registers (LED control)
UART_DATA_OUT3 : out std_logic_vector(7 downto 0); -- Data TO pendant (Speed register)
UART_Tx_Gate3 : out std_logic; -- latch UART data in external Tx registers (Speed register)
MODE_out : out std_logic_vector (2 downto 0); -- Selected MODE (simulation of handwheel)
Mode_Ready_out : out std_logic; -- mode may be switched
AXIS_out : out std_logic_vector (3 downto 0); -- Selected AXIS (simulation of handwheel)
Axis_Ready_out : out std_logic; -- axis may be switched
ACLR_UART_Rx_Out_N : out std_logic; -- clear UART Rx reg (active low)
flag1 : out std_logic --temp out 1
);
end PENDANT_DECODER;
architecture behavioral of PENDANT_DECODER is
-- signal, component etc. declarations
type axis_values is (X,Y,Z,A4);
type mode_values is (MANU, INC, HPG);
type discret_values is (JOG_MINUS,JOG_PLUS);
signal current_axis : axis_values;
signal next_axis : axis_values;
signal current_mode : mode_values;
signal next_mode : mode_values;
signal Mode_feedback : std_logic_vector (2 downto 0); -- active mode in CNC
signal Axis_feedback : std_logic_vector (3 downto 0); -- active axis in CNC
signal Led_feedback : std_logic_vector (2 downto 0); -- status of LEDs on F1-F3 buttons
signal Previous_Led : std_logic_vector (2 downto 0); -- previous status of LEDs on F1-F3 buttons
signal Axis_reg_block_pmac : std_logic;
signal Axis_reg_block_uart : std_logic;
signal Mode_reg_block_pmac : std_logic;
signal Mode_reg_block_uart : std_logic;
signal speed_reg_block : std_logic;
signal reset_speed_reg_flag : std_logic;
signal reset_speed_reg_R : std_logic;
signal mode_out_b : std_logic_vector(2 downto 0) ; -- internal register (updated after button is released)
signal axis_out_b : std_logic_vector(3 downto 0) ; -- internal register (updated after button is released)
signal mode_out_r : std_logic_vector(2 downto 0) ; -- buffered output (updated only after PMAC confirmation)
signal axis_out_r : std_logic_vector(3 downto 0) ; -- buffered output (updated only after PMAC confirmation)
signal buttons_out_r : std_logic_vector(5 downto 0) ;
signal speed_out_r : std_logic_vector(3 downto 0) ;
signal Current_axis_reg_R : std_logic_vector(23 downto 0) ;
signal Speed_reg_R : std_logic_vector(23 downto 0) ;
signal Button_reg_R : std_logic_vector(23 downto 0) ;
signal UART_DATA_OUT_R : std_logic_vector(7 downto 0) ;
signal UART_DATA_OUT_LED_R : std_logic_vector(23 downto 0) ;
signal UART_DATA_OUT_SPEED_R : std_logic_vector(7 downto 0) ;
signal UART_DATA_AXIS : std_logic_vector(7 downto 0) ;
signal UART_Tx_Gate_R1 : std_logic;
signal UART_Tx_Gate_flag1 : std_logic;
signal UART_Tx_Start_R1 : std_logic;
signal Axis_Ready_out_R : std_logic;
signal UART_DATA_MODE : std_logic_vector(7 downto 0) ;
signal UART_Tx_Gate_R2 : std_logic;
signal UART_Tx_Gate_flag2 : std_logic;
signal UART_Tx_Start_R2 : std_logic;
signal UART_DATA_LED : std_logic_vector(23 downto 0) ;
signal UART_Tx_Gate_R3 : std_logic;
signal UART_Tx_Gate_flag3 : std_logic;
signal UART_DATA_SPEED : std_logic_vector(7 downto 0) ;
signal UART_Tx_Gate_R4 : std_logic;
signal UART_Tx_Gate_flag4 : std_logic;
signal UART_Tx_flags : std_logic;
signal UART_Tx_Gate_R : std_logic;
signal counter : std_logic_vector (COUNTER_WIDTH-1 downto 0);
signal UART_Write_mode_R : std_logic;
signal stop_counter : std_logic;
signal start_counter : std_logic;
signal Reset_Write_mode : std_logic;
component impulse_gen_N_2cycle
port (
RESET_N :in std_logic; -- reset
IN_SIGNAL :in std_logic; -- input signal
IN_CLK :in std_logic; -- input clock signal
OUT_SIGNAL_P :out std_logic; -- output impluse Active High
OUT_SIGNAL_N :out std_logic -- output impluse Active Low
);
end component;
component Latch_trigger is
port( Data : in std_logic;
Enable : in std_logic;
Aclr : in std_logic;
Aset : in std_logic;
Clock : in std_logic;
Q : out std_logic
);
end component;
begin
-- writing outputs from buffers
MODE_out <= mode_out_r;
Axis_out <= axis_out_r;
Current_axis_reg <= Current_axis_reg_R;
Speed_reg <= Speed_reg_R;
Button_reg <= Button_reg_R;
UART_DATA_OUT <= UART_DATA_OUT_R; -- load buttons confirmation to UART
UART_Tx_Gate <= UART_Tx_Gate_R;
UART_DATA_OUT2 <= UART_DATA_OUT_LED_R; -- load LED control commands to UART
UART_Tx_Gate2 <= UART_Tx_Gate_R3; -- latch LED control commands to UART
UART_DATA_OUT3 <= UART_DATA_OUT_SPEED_R; -- load speed commands to UART
UART_Tx_Gate3 <= UART_Tx_Gate_R4; -- latch speed commands to UART
UART_Write_mode <= UART_Write_mode_R; -- enter UART transmit mode after new Tx data was latched
Axis_Ready_out <= Axis_Ready_out_R;
Mode_Ready_out <= not(Mode_reg_block_pmac);
ACLR_UART_Rx_Out_N <= '1'; -- ACLR not active
flag1 <= '0';
-- wiring inputs
Mode_feedback <= Disp_axis_reg (2 downto 0); -- extract Active mode code from CNC feedback
Axis_feedback <= Disp_axis_reg (23 downto 20); -- extract Active axis code from CNC feedback
Led_feedback <= LED_reg (2 downto 0); -- extract LED1 - LED3 status from CNC feedback
-- wiring registers and internal signals
Current_axis_reg_R(23 downto 20) <= axis_out_b; -- write selected axis code to Current_Axis_reg (bits 23-20)
Current_axis_reg_R(19 downto 17) <= "000"; -- reserved for more axes (7 axis max)
Current_axis_reg_R(16 downto 13) <= Axis_feedback; -- show active axis selected on CNC
Current_axis_reg_R(12) <= not(Axis_reg_block_pmac); -- 1 when ready to select new axis
Current_axis_reg_R(11) <= not(Mode_reg_block_pmac); -- 1 when ready to select new mode
Current_axis_reg_R(10 downto 8) <= Mode_feedback; -- show active mode selected on CNC
-- Current_axis_reg_R(7 downto 3) <= "00000"; -- reserved for more modes
Current_axis_reg_R(7) <= UART_Tx_Gate_flag2; --
Current_axis_reg_R(6 downto 3) <= "0000"; -- reserved for more modes
Current_axis_reg_R(2 downto 0) <= mode_out_b; -- write selected mode code to Current_Axis_reg (bits 2-0)
Speed_reg_R (3 downto 0) <= speed_out_r;
Speed_reg_R (23 downto 4) <= (OTHERS => '0');
Button_reg_R(23 downto 6) <= (OTHERS => '0');
Button_reg_R(5 downto 0) <= Buttons_out_r; -- show status of all buttons real-time
UART_Tx_Gate_R <= UART_Tx_Gate_R1 or UART_Tx_Gate_R2; -- latch AXIS(1), MODE(2) codes to UART in position #1
UART_Tx_flags <= UART_Tx_Start_R1 or UART_Tx_Start_R2 or UART_Tx_Gate_flag4 or UART_Tx_Gate_flag3; -- New data is available (2 SCLK_Khz width = 50us)
Reset_Write_mode <= RESET_N and not(stop_counter);
\UART_Tx_Gate_impulse_gen1\ : impulse_gen_N_2cycle -- generate signal to latch data in UART Tx registers (2 clk width) (from AXIS process)
port map(IN_SIGNAL => UART_Tx_Gate_flag1, IN_CLK => SCLK_LF_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => UART_Tx_Gate_R1);
\UART_Tx_Gate_impulse_gen2\ : impulse_gen_N_2cycle -- generate signal to latch data in UART Tx registers (2 clk width) (from MODE process)
port map(IN_SIGNAL => UART_Tx_Gate_flag2, IN_CLK => SCLK_LF_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => UART_Tx_Gate_R2);
\UART_Tx_Gate_impulse_gen3\ : impulse_gen_N_2cycle -- generate signal to latch data in UART Tx registers (2 clk width) (from LED process)
port map(IN_SIGNAL => UART_Tx_Gate_flag3, IN_CLK => SCLK_LF_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => UART_Tx_Gate_R3);
\UART_Tx_Gate_impulse_gen4\ : impulse_gen_N_2cycle -- generate signal to latch data in UART Tx registers (2 clk width) (from SPEED process)
port map(IN_SIGNAL => UART_Tx_Gate_flag4, IN_CLK => SCLK_LF_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => UART_Tx_Gate_R4);
\UART_Tx_start_impulse_gen1\ : impulse_gen_N_2cycle -- generate signal to transmit UART data (2 clk width) (from AXIS process)
port map(IN_SIGNAL => UART_Tx_Gate_flag1, IN_CLK => SCLK_Khz_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => UART_Tx_Start_R1);
\UART_Tx_start_impulse_gen2\ : impulse_gen_N_2cycle -- generate signal to transmit UART data (2 clk width) (from MODE process)
port map(IN_SIGNAL => UART_Tx_Gate_flag2, IN_CLK => SCLK_Khz_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => UART_Tx_Start_R2);
\speed_reg_reset_impulse_gen2\ : impulse_gen_N_2cycle -- generate signal to reset speed reg in new mode (2 clk width) (from MODE process)
port map(IN_SIGNAL => reset_speed_reg_flag, IN_CLK => SCLK_Khz_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => reset_speed_reg_R);
\Axis_ready_impulse_gen1\ : impulse_gen_N_2cycle -- generate signal to latch axis data (2 clk width) (from AXIS process)
port map(IN_SIGNAL => UART_Tx_Gate_flag1, IN_CLK => SCLK_Khz_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => Axis_Ready_out_R);
\UART_write_trigger\ : Latch_trigger -- generate '1' once Tx_flags = 1 and hold it until being reset
port map(Data => '0', Enable => '0', Aclr => Reset_Write_mode, Aset => UART_Tx_flags , Clock => SCLK_LF_IN, Q => start_counter);
Axis_select: process( RESET_N, SCLK_IN)
begin
if ( RESET_N ='0')then
axis_out_b <= "1000"; -- Axis: X
axis_out_r <= "1000"; -- Axis: X
Axis_reg_block_pmac <= '0';
Axis_reg_block_uart <= '0';
current_axis <= X;
next_axis <= X;
UART_Tx_Gate_flag1 <= '0'; -- clear flag.
UART_DATA_AXIS <= (OTHERS => '0');
elsif (rising_edge(SCLK_IN)) then
if (Axis_reg_block_pmac = '0') then -- if axis select is allowed
if (Axis_reg_block_uart = '0')then -- if no other button is pressed
case (UART_DATA1_IN) is
when x"55" => Axis_reg_block_uart <= '1'; -- Axis: X
when x"56" => Axis_reg_block_uart <= '1'; -- Axis: Y
when x"57" => Axis_reg_block_uart <= '1'; -- Axis: Z
when x"58" => Axis_reg_block_uart <= '1'; -- Axis: 4
when others => null;
end case;
elsif (Axis_reg_block_uart = '1') then -- button is pressed, uart block is set until button is released
case (UART_DATA1_IN) is
when x"15" => axis_out_b <= "1000"; next_axis <= X; Axis_reg_block_uart <= '0'; Axis_reg_block_pmac <= '1'; UART_DATA_AXIS <= x"C5"; -- Axis: X
when x"16" => axis_out_b <= "0100"; next_axis <= Y; Axis_reg_block_uart <= '0'; Axis_reg_block_pmac <= '1'; UART_DATA_AXIS <= x"C6"; -- Axis: Y
when x"17" => axis_out_b <= "0010"; next_axis <= Z; Axis_reg_block_uart <= '0'; Axis_reg_block_pmac <= '1'; UART_DATA_AXIS <= x"C7"; -- Axis: Z
when x"18" => axis_out_b <= "0001"; next_axis <= A4; Axis_reg_block_uart <= '0'; Axis_reg_block_pmac <= '1'; UART_DATA_AXIS <= x"C8"; -- Axis: 4
when others => null;
end case;
else null;
end if;
elsif (Axis_feedback = axis_out_b) then -- Axis_reg_block_pmac = 1, got axis confirmation from PMAC
current_axis <= next_axis;
axis_out_r <= axis_out_b; -- output new axis value (to update position)
Axis_reg_block_pmac <= '0'; -- clear register block
UART_Tx_Gate_flag1 <= '1'; -- set flag to form short Gate impulse to latch Data into UART Tx registers
else -- Axis_reg_block_pmac = 1, waiting for axis confirmation from PMAC
UART_Tx_Gate_flag1 <= '0'; -- clear flag
end if;
end if;
end process axis_select;
Mode_select: process( RESET_N, SCLK_IN)
begin
if ( RESET_N ='0')then
mode_out_b <= "001"; -- Mode: MANU
mode_out_r <= "001"; -- Mode: MANU
Mode_reg_block_uart <= '0';
Mode_reg_block_pmac <= '0';
current_mode <= MANU;
next_mode <= MANU;
UART_Tx_Gate_flag2 <= '0'; -- clear flag.
UART_DATA_MODE <= (OTHERS => '0');
reset_speed_reg_flag <= '0'; -- clear flag.
elsif (rising_edge(SCLK_IN)) then
if (Mode_reg_block_pmac = '0') then -- if mode select is allowed
if (Mode_reg_block_uart = '0')then -- if no other button is pressed
UART_Tx_Gate_flag2 <= '0'; -- clear flag
case (UART_DATA1_IN) is
when x"52" => Mode_reg_block_uart <= '1'; -- Mode: MANU
when x"53" => Mode_reg_block_uart <= '1'; -- Mode: INC
when x"54" => Mode_reg_block_uart <= '1'; -- Mode: HPG
when others => null;
end case;
elsif (Mode_reg_block_uart = '1') then -- button is pressed, uart block is set until button is released
UART_Tx_Gate_flag2 <= '0'; -- clear flag
case (UART_DATA1_IN) is
when x"12" => Mode_out_b <= "001"; next_mode <= MANU; Mode_reg_block_uart <= '0'; Mode_reg_block_pmac <= '1'; UART_DATA_MODE <= x"C2"; -- Mode: MANU
when x"13" => Mode_out_b <= "010"; next_mode <= INC; Mode_reg_block_uart <= '0'; Mode_reg_block_pmac <= '1'; UART_DATA_MODE <= x"C3"; -- Mode: INC
when x"14" => Mode_out_b <= "100"; next_mode <= HPG; Mode_reg_block_uart <= '0'; Mode_reg_block_pmac <= '1'; UART_DATA_MODE <= x"C4"; -- Mode: HPG
when others => null;
end case;
else null;
end if;
elsif (Mode_feedback = mode_out_b) then -- Axis_reg_block_pmac = 1, got mode confirmation from PMAC
current_mode <= next_mode;
Mode_out_r <= Mode_out_b; -- output new mode value
Mode_reg_block_pmac <= '0'; -- clear register block
UART_Tx_Gate_flag2 <= '1'; -- set flag to form short Gate impulse to latch Data into UART Tx registers
reset_speed_reg_flag <= '1'; -- set flag to form short Gate impulse to reset speed register
else -- Axis_reg_block_pmac = 1, waiting for axis confirmation from PMAC
UART_Tx_Gate_flag2 <= '0'; -- clear flag
reset_speed_reg_flag <= '0'; -- clear flag
end if;
end if;
end process mode_select;
buttons_reg: process( RESET_N, SCLK_IN)
begin
if ( RESET_N ='0')then
Buttons_out_r <= (OTHERS => '0');
elsif (rising_edge(SCLK_IN)) then
case (UART_DATA1_IN) is
when x"41" => Buttons_out_r(0) <= '1'; -- Button: F1 is pressed
when x"01" => Buttons_out_r(0) <= '0'; -- Button: F1 is released
when x"42" => Buttons_out_r(1) <= '1'; -- Button: F2 is pressed
when x"02" => Buttons_out_r(1) <= '0'; -- Button: F2 is released
when x"43" => Buttons_out_r(2) <= '1'; -- Button: F3 is pressed
when x"03" => Buttons_out_r(2) <= '0'; -- Button: F1 is released
when x"5A" => Buttons_out_r(3) <= '1'; -- Button: minus is pressed
when x"1A" => Buttons_out_r(3) <= '0'; -- Button: minus is released
when x"5B" => Buttons_out_r(4) <= '1'; -- Button: ampersand is pressed
when x"1B" => Buttons_out_r(4) <= '0'; -- Button: ampersand is released
when x"59" => Buttons_out_r(5) <= '1'; -- Button: plus is pressed
when x"19" => Buttons_out_r(5) <= '0'; -- Button: plus is released
when others => null;
end case;
end if;
end process buttons_reg;
speed_reg_proc: process( RESET_N, SCLK_Khz_IN)
begin
if ( RESET_N ='0')then
speed_out_r <= "0001";
speed_reg_block <= '0'; -- clear block, speed change is allowed on next J+/J- press
UART_DATA_SPEED <= x"00"; -- jog speed: 0
UART_Tx_Gate_flag4 <= '0'; -- clear flag.
elsif (rising_edge(SCLK_Khz_IN)) then -- !!!!!!!!!!!!!!!!!!!!! WAS SCLK_IN !!!!!!!!!!!!!!!!!!!!!
if (reset_speed_reg_R = '1') then -- occurs when entering new mode (2 clk_lf impulse)
speed_out_r <= "0001";
if (CURRENT_MODE = INC) then
UART_DATA_SPEED <= x"91"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x1
elsif (CURRENT_MODE = MANU) then
UART_DATA_SPEED <= x"88"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 5
elsif (CURRENT_MODE = HPG) then
UART_DATA_SPEED <= x"A1"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x1
else
UART_DATA_SPEED <= x"00"; UART_Tx_Gate_flag4 <= '1'; -- send null
end if;
elsif (UART_DATA1_IN = x"5D" and speed_reg_block = '0') then -- J+ pressed, speed change allowed
if (CURRENT_MODE = INC) then
case (speed_out_r) is
when "0000" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"91"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x1
when "0001" => speed_out_r <= "0010"; UART_DATA_SPEED <= x"92"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x10
when "0010" => speed_out_r <= "0100"; UART_DATA_SPEED <= x"93"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x100
when "0100" => speed_out_r <= "0100"; UART_DATA_SPEED <= x"93"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x100
when others => speed_out_r <= "0001"; UART_DATA_SPEED <= x"91"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x1
end case;
elsif (CURRENT_MODE = MANU) then
case (speed_out_r) is
when "0000" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"88"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 5
when "0001" => speed_out_r <= "0010"; UART_DATA_SPEED <= x"89"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 20
when "0010" => speed_out_r <= "0100"; UART_DATA_SPEED <= x"8A"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 50
when "0100" => speed_out_r <= "1000"; UART_DATA_SPEED <= x"8B"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 100
when "1000" => speed_out_r <= "1000"; UART_DATA_SPEED <= x"8B"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 100
when others => speed_out_r <= "0001"; UART_DATA_SPEED <= x"88"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 5
end case;
elsif (CURRENT_MODE = HPG) then
case (speed_out_r) is
when "0000" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"A1"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x1
when "0001" => speed_out_r <= "0010"; UART_DATA_SPEED <= x"A2"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x10
when "0010" => speed_out_r <= "0100"; UART_DATA_SPEED <= x"A3"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x100
when "0100" => speed_out_r <= "0100"; UART_DATA_SPEED <= x"A3"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x100
when others => speed_out_r <= "0001"; UART_DATA_SPEED <= x"A1"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x1
end case;
else
speed_out_r <= "0001"; UART_DATA_SPEED <= x"00"; UART_Tx_Gate_flag4 <= '0';
end if;
speed_reg_block <= '1'; -- set block to change speed only 1 time
elsif (UART_DATA1_IN = x"5C" and speed_reg_block = '0') then -- J- pressed, speed change allowed
if (CURRENT_MODE = INC) then
case (speed_out_r) is
when "0000" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"91"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x1
when "0001" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"91"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x1
when "0010" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"91"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x1
when "0100" => speed_out_r <= "0010"; UART_DATA_SPEED <= x"92"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x10
when "1000" => speed_out_r <= "0100"; UART_DATA_SPEED <= x"93"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x100
when others => speed_out_r <= "0001"; UART_DATA_SPEED <= x"91"; UART_Tx_Gate_flag4 <= '1'; -- INC PLSR: x1
end case;
elsif (CURRENT_MODE = MANU) then
case (speed_out_r) is
when "0000" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"88"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 5
when "0001" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"88"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 5
when "0010" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"88"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 5
when "0100" => speed_out_r <= "0010"; UART_DATA_SPEED <= x"89"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 20
when "1000" => speed_out_r <= "0100"; UART_DATA_SPEED <= x"8A"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 50
when others => speed_out_r <= "0001"; UART_DATA_SPEED <= x"88"; UART_Tx_Gate_flag4 <= '1'; -- jog speed: 5
end case;
elsif (CURRENT_MODE = HPG) then
case (speed_out_r) is
when "0000" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"A1"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x1
when "0001" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"A1"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x1
when "0010" => speed_out_r <= "0001"; UART_DATA_SPEED <= x"A1"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x1
when "0100" => speed_out_r <= "0010"; UART_DATA_SPEED <= x"A2"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x10
when "1000" => speed_out_r <= "0100"; UART_DATA_SPEED <= x"A3"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x100
when others => speed_out_r <= "0001"; UART_DATA_SPEED <= x"A1"; UART_Tx_Gate_flag4 <= '1'; -- INC RAPD: x1
end case;
else
speed_out_r <= "0001"; UART_DATA_SPEED <= x"00"; UART_Tx_Gate_flag4 <= '0';
end if;
speed_reg_block <= '1'; -- set block to change speed only 1 time
elsif (UART_DATA1_IN = x"1D") then -- J+ released
speed_reg_block <= '0'; -- clear block, speed change is allowed on next J+/J- press
UART_Tx_Gate_flag4 <= '0'; -- clear flag.
elsif (UART_DATA1_IN = x"1C") then -- J- released
speed_reg_block <= '0'; -- clear block, speed change is allowed on next J+/J- press
UART_Tx_Gate_flag4 <= '0'; -- clear flag.
else
UART_Tx_Gate_flag4 <= '0'; -- clear flag;
end if;
end if;
end process speed_reg_proc;
Led_control: process( RESET_N, SCLK_Khz_IN)
-- Alias for parts of LED register
alias LED1 is UART_DATA_LED(7 downto 0);
alias LED2 is UART_DATA_LED(15 downto 8);
alias LED3 is UART_DATA_LED(23 downto 16);
begin
if ( RESET_N ='0')then
UART_Tx_Gate_flag3 <= '0'; -- clear flag.
UART_DATA_LED <= (OTHERS => '0');
Previous_LED <= (OTHERS => '0');
elsif (rising_edge(SCLK_Khz_IN)) then -- intentionally use low frequency clock to make longer gate signal
if (LED_feedback /= Previous_Led) then
case (LED_feedback) is
when "000" => LED3 <= x"03"; LED2 <= x"02"; LED1 <= x"01"; -- L3:OFF, L2:OFF, L1:OFF
when "001" => LED3 <= x"03"; LED2 <= x"02"; LED1 <= x"41";
when "010" => LED3 <= x"03"; LED2 <= x"42"; LED1 <= x"01";
when "011" => LED3 <= x"03"; LED2 <= x"42"; LED1 <= x"41";
when "100" => LED3 <= x"43"; LED2 <= x"02"; LED1 <= x"01";
when "101" => LED3 <= x"43"; LED2 <= x"02"; LED1 <= x"41";
when "110" => LED3 <= x"43"; LED2 <= x"42"; LED1 <= x"01";
when "111" => LED3 <= x"43"; LED2 <= x"42"; LED1 <= x"41"; -- L3:ON, L2:ON, L1:ON
end case;
Previous_Led <= LED_feedback;
UART_Tx_Gate_flag3 <= '1'; -- used to form short Gate impulse to latch Data into UART Tx registers
else -- LED status has NO change
UART_Tx_Gate_flag3 <= '0'; -- clear flag3
end if;
end if;
end process Led_control;
UART_DATA: process( RESET_N, SCLK_IN)
begin
if ( RESET_N ='0')then
UART_DATA_OUT_R <= (OTHERS => '0');
elsif (rising_edge(SCLK_IN)) then
if (UART_Tx_Gate_R1 = '1') then -- AXIS confirmation code need to be transmitted
UART_DATA_OUT_R <= UART_DATA_AXIS;
elsif (UART_Tx_Gate_R2 = '1') then -- MODE confirmation code need to be transmitted
UART_DATA_OUT_R <= UART_DATA_MODE;
else
UART_DATA_OUT_R <= (OTHERS => '0');
end if;
end if;
end process UART_DATA;
UART_SPEED_DATA: process( RESET_N, SCLK_IN)
begin
if ( RESET_N ='0')then
UART_DATA_OUT_SPEED_R <= (OTHERS => '0');
elsif (rising_edge(SCLK_IN)) then
if (UART_Tx_Gate_R4 = '1') then -- Speed code need to be transmitted
UART_DATA_OUT_SPEED_R <= UART_DATA_SPEED;
else
UART_DATA_OUT_SPEED_R <= (OTHERS => '0');
end if;
end if;
end process UART_SPEED_DATA;
UART_LED_DATA: process( RESET_N, SCLK_IN)
begin
if ( RESET_N ='0')then
UART_DATA_OUT_LED_R <= (OTHERS => '0');
elsif (rising_edge(SCLK_IN)) then
if (UART_Tx_Gate_R3 = '1') then -- LED control code need to be transmitted
UART_DATA_OUT_LED_R <= UART_DATA_LED;
else
UART_DATA_OUT_LED_R <= (OTHERS => '0');
end if;
end if;
end process UART_LED_DATA;
timer: -- generate impulse to initiate UART transmission
process(RESET_N,SCLK_Khz_IN)
begin
if (RESET_N = '0') then
counter <= (others => '0');
stop_counter <= '0';
UART_Write_mode_R <= '0';
elsif (rising_edge(SCLK_Khz_IN)) then
if (start_counter = '1' and UART_Tx_Gate_R = '0') then -- UART data was latched (Tx gate->0), but one of Tx flags is still '1';
if (counter <= 2**(COUNTER_WIDTH-1) and stop_counter = '0') then
counter <= counter + 1;
UART_Write_mode_R <= '1'; -- enter UART transmit mode
else
counter <= (others => '0');
stop_counter <= '1';
UART_Write_mode_R <= '0'; -- exit UART transmit mode
end if;
else
counter <= (others => '0');
stop_counter <= '0';
UART_Write_mode_R <= '0';
end if;
end if;
end process timer;
end behavioral;
|
gpl-2.0
|
531aaa205b1ca0697bc3f8a148f4908b
| 0.545933 | 3.218172 | false | false | false | false |
AdanDuM/INE5406-SD
|
washing_machine.vhd
| 1 | 6,908 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Alunos: Adan Pereira Gomes e Wesley Mayk Gama Luz
entity washing_machine is
generic (
sr_width : positive := 2 -- state register width (motor_state)
-- address_width : positive := 2
);
port (
clock, reset: in std_logic;
-- interface externa
on_button, sensor_cover, -- sensor signals
zero_minute, zero_seconds, -- timer flags
empty, full : in std_logic; -- filled flags
motor_state_in : in std_logic_vector(sr_width-1 downto 0); -- motor state register input
motor_state_out: out std_logic_vector(sr_width-1 downto 0); -- motor state register output
motor_state_en, -- motor state register enable
water_pump_in, water_pump_out, -- pump control signals
rotate_motor_l, rotate_motor_r, -- motor control signals
led_waiting, led_soak, led_wash, led_spin, led_ready, -- led info
timer_reset: out std_logic
-- interface com barramento
--writeE, readE: in std_logic;
--address : in std_logic_vector(address_width-1 downto 0);
--writeData: in std_logic_vector(7 downto 0);
--readData: out std_logic_vector(7 downto 0)
);
end entity;
architecture BC of washing_machine is
type State is (waiting, wash, soak, spin, drain, fill, paused, rotate_l, rotate_r, ready);
signal actualState, nextState: State;
begin
-- next-state logic
LPE: process(actualState, motor_state_in, on_button, sensor_cover, zero_minute, zero_seconds, empty, full) is
begin
nextState <= actualState;
case actualState is
when waiting =>
if on_button = '1' then
nextState <= wash;
end if;
when wash =>
if full = '0' then
nextState <= fill;
else
nextState <= paused;
end if;
when soak =>
if zero_minute = '1' then
nextState <= spin;
end if;
when spin =>
if empty = '0' then
nextState <= drain;
end if;
when drain =>
if empty = '1' then
nextState <= spin;
end if;
when fill =>
if full = '1' then
nextState <= wash;
end if;
when paused =>
if motor_state_in = "01" and zero_minute = '0' and zero_seconds = '1' then
nextState <= rotate_r;
elsif motor_state_in = "10" and zero_minute = '0' and zero_seconds = '1' then
nextState <= rotate_l;
elsif zero_minute = '1' then
nextState <= wash;
end if;
when rotate_l =>
if zero_seconds = '1' then
nextState <= paused;
end if;
when rotate_r =>
if zero_seconds = '1' then
nextState <= paused;
end if;
when ready =>
if on_button = '1' or sensor_cover = '0' then
nextState <= waiting;
end if;
end case;
end process;
-- state element (memory)
ME: process(clock, reset) is
begin
if reset = '1' then
actualState <= waiting;
elsif rising_edge(clock) then
actualState <= nextState;
end if;
end process;
-- output-logic
OL: process(actualState) is
begin
case actualState is
when waiting =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '0';
motor_state_out <= (others => '0');
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '0';
rotate_motor_l <= '0';
rotate_motor_r <= '0';
-- led info
led_waiting <= '1';
led_soak <= '0';
led_wash <= '0';
led_spin <= '0';
led_ready <= '0';
when wash =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '0';
motor_state_out <= (others => '0');
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '0';
rotate_motor_l <= '0';
rotate_motor_r <= '0';
-- led info
led_waiting <= '0';
led_soak <= '0';
led_wash <= '1';
led_spin <= '0';
led_ready <= '0';
when soak =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '0';
motor_state_out <= (others => '0');
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '0';
rotate_motor_l <= '0';
rotate_motor_r <= '0';
-- led info
led_waiting <= '0';
led_soak <= '1';
led_wash <= '0';
led_spin <= '0';
led_ready <= '0';
when spin =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '0';
motor_state_out <= (others => '0');
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '0';
rotate_motor_l <= '0';
rotate_motor_r <= '1';
-- led info
led_waiting <= '0';
led_soak <= '0';
led_wash <= '0';
led_spin <= '1';
led_ready <= '0';
when drain =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '0';
motor_state_out <= (others => '0');
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '1';
rotate_motor_l <= '0';
rotate_motor_r <= '0';
-- led info
led_waiting <= '0';
led_soak <= '0';
led_wash <= '0';
led_spin <= '1';
led_ready <= '0';
when fill =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '0';
motor_state_out <= (others => '0');
-- motor and pump
water_pump_in <= '1';
water_pump_out <= '0';
rotate_motor_l <= '0';
rotate_motor_r <= '0';
-- led info
led_waiting <= '0';
led_soak <= '0';
led_wash <= '1';
led_spin <= '0';
led_ready <= '0';
when paused =>
timer_reset <= '1';
-- motor state register
motor_state_en <= '0';
motor_state_out <= (others => '0');
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '0';
rotate_motor_l <= '0';
rotate_motor_r <= '0';
-- led info
led_waiting <= '0';
led_soak <= '0';
led_wash <= '1';
led_spin <= '0';
led_ready <= '0';
when rotate_l =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '1';
motor_state_out <= "10";
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '0';
rotate_motor_l <= '1';
rotate_motor_r <= '0';
-- led info
led_waiting <= '0';
led_soak <= '0';
led_wash <= '1';
led_spin <= '0';
led_ready <= '0';
when rotate_r =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '1';
motor_state_out <= "01";
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '0';
rotate_motor_l <= '0';
rotate_motor_r <= '1';
-- led info
led_waiting <= '0';
led_soak <= '0';
led_wash <= '1';
led_spin <= '0';
led_ready <= '0';
when ready =>
timer_reset <= '0';
-- motor state register
motor_state_en <= '0';
motor_state_out <= (others => '0');
-- motor and pump
water_pump_in <= '0';
water_pump_out <= '0';
rotate_motor_l <= '0';
rotate_motor_r <= '0';
-- led info
led_waiting <= '0';
led_soak <= '0';
led_wash <= '0';
led_spin <= '0';
led_ready <= '1';
end case;
end process;
end architecture;
|
gpl-2.0
|
4a389b108025907941419e706976e4d8
| 0.542994 | 2.742358 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/pwm/wb_pwm8.vhd
| 1 | 2,844 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- W I S H B O N E C O M P L I A N T P W M 8
-- (wb_pwm8.vhd)
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.pwm8_comp.all;
-------------------------------------------------------------------------------
entity wb_pwm8 is
-------------------------------------------------------------------------------
generic (
USER_CLK : Boolean := false
);
port (
-- wishbone
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- user pins
clk_in : in std_logic := '-'; -- optional alternative clock input
pwm_out : out std_logic
);
end wb_pwm8;
-------------------------------------------------------------------------------
architecture structural of wb_pwm8 is
-------------------------------------------------------------------------------
signal pwm_in_s : pwm8_in_type;
signal wbs_register_s : std_logic_vector(WB_DW-1 downto 0);
signal pwm_clk_s : std_logic;
begin
-- select pwm clock using USER_CLK generic
pwm_clk_s <= clk_in when USER_CLK else wbs_in.clk;
----------------------------------------------------------------------------
WISHBONE_SLAVE : entity work.wbs_single_reg
----------------------------------------------------------------------------
port map (
wbs_in => wbs_in,
wbs_out => wbs_out,
register_out => wbs_register_s -- duty cycle only
);
----------------------------------------------------------------------------
PWM_8 : entity work.pwm8
----------------------------------------------------------------------------
port map (
clk => pwm_clk_s,
rst => wbs_in.rst,
d => pwm_in_s,
pwm => pwm_out
);
-- connect wbs_register to pwm entity
pwm_in_s.duty_cycle <= wbs_register_s(7 downto 0);
end structural;
|
gpl-3.0
|
c1569cadbf62c0ddfa752cf84a869df1
| 0.45218 | 4.565008 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega1/RF.vhd
| 1 | 1,074 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RF is
Port ( Rs1 : in STD_LOGIC_VECTOR (4 downto 0);
Rs2 : in STD_LOGIC_VECTOR (4 downto 0);
Rd : in STD_LOGIC_VECTOR (4 downto 0);
rst : in STD_LOGIC;
Dwr : in STD_LOGIC_VECTOR (31 downto 0);
ORs1 : out STD_LOGIC_VECTOR (31 downto 0);
ORs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (0 to 39) of std_logic_vector (31 downto 0);
signal registers : ram_type :=(others => x"00000000");
begin
process(rs1,rs2,rd,dwr, rst)
begin
registers(0) <= x"00000000";
if rst = '0' then
if(rd/="00000")then
registers(conv_integer(rd)) <= Dwr;
end if;
ORs1 <= registers(conv_integer(Rs1));
ORs2 <= registers(conv_integer(Rs2));
else
ORs1 <= (others => '0');
ORs2 <= (others => '0');
--registers(16) <= x"00000011";
--registers(17) <= x"FFFFFFF7";
--registers(18) <= x"0000000E";
end if;
end process;
end Behavioral;
|
mit
|
7173606aa3614d47537001350ed4bd35
| 0.598696 | 2.983333 | false | false | false | false |
xylnao/w11a-extra
|
rtl/ibus/ib_sres_or_mon.vhd
| 2 | 3,467 |
-- $Id: ib_sres_or_mon.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_mon - sim
-- Description: ibus result or monitor
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end ib_sres_or_mon;
architecture sim of ib_sres_or_mon is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
constant dzero : slv16 := (others=>'0');
variable oline : line;
variable nack : integer := 0;
variable nbusy : integer := 0;
variable ndout : integer := 0;
begin
nack := 0;
nbusy := 0;
ndout := 0;
if IB_SRES_1.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_2.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_3.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_4.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
if now > 0 ns and (nack>1 or nbusy>1 or ndout>1) then
write(oline, now, right, 12);
if nack > 1 then
write(oline, string'(" #ack="));
write(oline, nack);
end if;
if nbusy > 1 then
write(oline, string'(" #busy="));
write(oline, nbusy);
end if;
if ndout > 1 then
write(oline, string'(" #dout="));
write(oline, ndout);
end if;
write(oline, string'(" FAIL in "));
write(oline, ib_sres_or_mon'path_name);
writeline(output, oline);
end if;
end process proc_comb;
end sim;
|
gpl-2.0
|
b35a4bc65c2b888606e4635b7cff8a24
| 0.555235 | 3.330451 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/avmb/sys_tst_rlink_mb.vhd
| 1 | 6,836 |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_mb - syn
-- Description: rlink tester design for avmb
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
--
-- Test bench: tb/tb_tst_rlink_mb
--
-- Target Devices: generic
-- Tool versions: xst 13.4; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Avnet Spartan-6 MicroBoard Switches, Buttons, LEDs:
--
-- SWI(3:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod 2/top RS232 port /
--
-- LED(3:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_mb is -- top level
-- implements avmb_fusp_aif
port (
I_CLK40 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- mb switches
I_BTN : in slv1; -- mb button
O_LED : out slv4; -- mb leds
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_mb;
architecture syn of sys_tst_rlink_mb is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv4 := (others=>'0');
signal BTN : slv1 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK40,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
SWIDTH => 4,
BWIDTH => 1,
LWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => (others=>'0'),
DSP_DP => (others=>'0'),
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
LED(3 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
gpl-2.0
|
a5f8c60e65d3e9fabd6c8bc5a99b7b20
| 0.490053 | 3.384158 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL source files/bcd_4digit.vhd
| 1 | 2,456 |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
-- File: BCD_DECODER.vhd
-- File history:
-- <1.3>: <02/04/2015>: <added thousands digit. Max 16383>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Decode 13 bit input integer (max 9.999) into 4 digits in BCD code
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--------------------------------------------------------------------------------
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bcd_4dig is
Port (
number : in std_logic_vector (13 downto 0);
thousands : out std_logic_vector (3 downto 0);
hundreds : out std_logic_vector (3 downto 0);
tens : out std_logic_vector (3 downto 0);
ones : out std_logic_vector (3 downto 0)
);
end bcd_4dig;
architecture Behavioral of bcd_4dig is
begin
bin_to_bcd : process (number)
-- Internal variable for storing bits
variable shift : unsigned(29 downto 0);
-- Alias for parts of shift register
alias num is shift(13 downto 0);
alias one is shift(17 downto 14);
alias ten is shift(21 downto 18);
alias hun is shift(25 downto 22);
alias thous is shift(29 downto 26);
begin
-- Clear previous number and store new number in shift register
num := unsigned(number);
one := X"0";
ten := X"0";
hun := X"0";
thous := X"0";
-- Loop eight times
for i in 1 to num'Length loop
-- Check if any digit is greater than or equal to 5
if one >= 5 then
one := one + 3;
end if;
if ten >= 5 then
ten := ten + 3;
end if;
if hun >= 5 then
hun := hun + 3;
end if;
if thous >= 5 then
thous := thous + 3;
end if;
-- Shift entire register left once
shift := shift_left(shift, 1);
end loop;
-- Push decimal numbers to output
thousands <= std_logic_vector(thous);
hundreds <= std_logic_vector(hun);
tens <= std_logic_vector(ten);
ones <= std_logic_vector(one);
end process;
end Behavioral;
|
gpl-2.0
|
f21a312d6e5977b3b7518be09d5ecbed
| 0.520358 | 3.96129 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/MUX_DM.vhd
| 1 | 705 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_DM is
Port ( PC : in STD_LOGIC_VECTOR (4 downto 0);
RFsource : in std_logic_vector (1 downto 0);
DataToMem : in STD_LOGIC_VECTOR (31 downto 0);
ALUResult : in STD_LOGIC_VECTOR (31 downto 0);
DataToReg : out STD_LOGIC_VECTOR (31 downto 0)
);
end MUX_DM;
architecture Behavioral of MUX_DM is
begin
process(PC, RFsource, DataToMem, ALUResult) begin
if(RFsource = "00") then
DataToReg <= DataToMem;
elsif(RFsource = "01") then
DataToReg <= ALUResult;
else
DataToReg(4 downto 0) <= PC;
DataToReg(31 downto 5) <= (others => '0');
end if;
end process;
end Behavioral;
|
mit
|
06b8c19b1fa513b3aeb3929dd5577e7a
| 0.62695 | 3.309859 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw 5/SeqSideEightBitAdder.vhd
| 1 | 1,573 |
library ieee;
use ieee.std_logic_1164.all;
entity SeqSideEightBitAdder is
port(
SW: IN std_logic_vector(17 downto 0); --sw17 save?, sw16 add?
KEY0: IN std_logic;
LEDR: out std_logic_vector(8 downto 0);
HEX0, HEX1: OUT std_logic_vector(6 downto 0)
);
end SeqSideEightBitAdder;
architecture impl of SeqSideEightBitAdder is
component OneBitAdder is
port(
A, B, CIN: IN std_logic;
S, COUT: OUT std_logic
);
end component;
component HexDisplay is
port(
input: in std_logic_vector(3 downto 0);
display: out std_logic_vector(6 downto 0)
);
end component;
signal c: std_logic_vector(8 downto 0);
signal reg: std_logic_vector(7 downto 0) := SW(15 downto 8);
signal bBuffor: std_logic_vector(7 downto 0) := SW(7 downto 0);
signal output: std_logic_vector(7 downto 0) := "00000000";
begin
H0: HexDisplay port map(output(3 downto 0), Hex0(6 downto 0));
H1: HexDisplay port map(output(7 downto 4), Hex1(6 downto 0));
SUM: for i in 7 downto 0 generate
ad : OneBitAdder port map(
reg(i), bBuffor(i), c(i), output(i), c(i + 1)
);
end generate;
c(0) <= not(SW(16));
process (KEY0)
begin
if rising_edge(KEY0) then
if SW(16) = '0' then --add or sub
for i in 7 downto 0 loop
bBuffor(i) <= not(SW(i));
end loop;
else
for i in 7 downto 0 loop
bBuffor(i) <= SW(i);
end loop;
end if;
if SW(17) = '1' then --if save last solution
reg(7 downto 0) <= output(7 downto 0);
else
reg(7 downto 0) <= SW(15 downto 8);
end if;
end if;
LEDR(7 downto 0) <= output(7 downto 0);
LEDR(8) <= c(8);
end process;
end;
|
mit
|
284789aa4ab354e9bb6042340767d3d1
| 0.6548 | 2.75 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/algorithms/sindhu_prasana_nfa/vhdl/sindhu_prasana_nfa.vhd
| 1 | 2,982 |
-- ----------------------------------------------------------------------------
-- Entity for implementation of SINDHU PRASANA NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity SINDHU_PRASANA_NFA is
generic(
DATA_WIDTH : integer := %$%;
RULES : integer := %$%
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
DATA : in std_logic_vector(DATA_WIDTH - 1 downto 0);
SOF : in std_logic;
EOF : in std_logic;
SRC_RDY : in std_logic;
DST_RDY : out std_logic;
-- output data interface
BITMAP : out std_logic_vector(RULES - 1 downto 0);
VLD : out std_logic;
ACK : in std_logic
);
end entity SINDHU_PRASANA_NFA;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of SINDHU_PRASANA_NFA is
signal local_reset : std_logic;
signal local_reset_fsm : std_logic;
signal we : std_logic;
-- signal rdy : std_logic;
-- signal vld_internal : std_logic;
-- signal set : std_logic;
%$%
begin
-- local_reset <= RESET or ACK;
-- we <= SRC_RDY and rdy;
-- DST_RDY <= rdy;
-- VLD <= vld_internal;
-- set <= SRC_RDY and EOF and rdy;
-- rdy <= not vld_internal;
--
-- end_reg: process(CLK)
-- begin
-- if (CLK'event and CLK = '1') then
-- if (local_reset = '1') then
-- vld_internal <= '0';
-- else
-- if set = '1' then
-- vld_internal <= '1';
-- end if;
-- end if;
-- end if;
-- end process end_reg;
local_reset <= RESET or local_reset_fsm;
ctrl_fsm: entity work.CONTROL_FSM
port map(
CLK => CLK,
RESET => RESET,
-- input interface
EOF => EOF,
SRC_RDY => SRC_RDY,
DST_RDY => DST_RDY,
-- output interface
WE => we,
LOCAL_RESET => local_reset_fsm,
-- inner interface
VLD => VLD,
ACK => ACK
);
%$%
final_bitmap_u: entity work.FINAL_BITMAP
generic map(
DATA_WIDTH => RULES
)
port map(
CLK => CLK,
RESET => local_reset,
-- input data interface
SET => bitmap_in,
-- output data interface
BITMAP => BITMAP
);
end architecture full;
|
gpl-2.0
|
a7ef070d549116f458b6e0ba06358e15
| 0.407109 | 4.272206 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/xlib/xlib.vhd
| 1 | 7,213 |
-- $Id: xlib.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: xlib
-- Description: Xilinx specific components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
-- 2008-05-23 149 1.0.4 add iob_io(_gen)
-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);
-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)
-- 2007-12-16 101 1.0.1 add INIT generic ports
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package xlib is
component iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end component;
component iob_reg_i_gen is -- registered IOB, input, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slv(DWIDTH-1 downto 0); -- input data
PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_reg_o is -- registered IOB, output
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end component;
component iob_reg_o_gen is -- registered IOB, output, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slv(DWIDTH-1 downto 0); -- output data
PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_reg_io is -- registered IOB, in/output
generic (
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slbit; -- input data (read from pad)
DO : in slbit; -- output data (write to pad)
PAD : inout slbit -- i/o pad
);
end component;
component iob_reg_io_gen is -- registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_io is -- un-registered IOB, in/output
generic (
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
OE : in slbit; -- output enable
DI : out slbit; -- input data (read from pad)
DO : in slbit; -- output data (write to pad)
PAD : inout slbit -- i/o pad
);
end component;
component iob_oddr2_simple is -- DDR2 output I/O pad
generic (
ALIGN : string := "NONE"; -- ddr_alignment
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO0 : in slbit; -- output data
DO1 : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end component;
component iob_io_gen is -- un-registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_keeper is -- keeper for IOB
port (
PAD : inout slbit -- i/o pad
);
end component;
component iob_keeper_gen is -- keeper for IOB, vector
generic (
DWIDTH : positive := 16); -- data port width
port (
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 2; -- FX clock divide (2-32)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end component;
end package xlib;
|
gpl-2.0
|
919b437c376fb90efef535e8cc607e0d
| 0.499792 | 3.832625 | false | false | false | false |
armandas/FPGalaxy
|
explosion.vhd
| 2 | 3,788 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity explosion is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
destruction: in std_logic;
origin_x, origin_y: std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(2 downto 0)
);
end explosion;
architecture behaviour of explosion is
-- frame size (32x32 px)
constant SIZE: integer := 32;
-- colour masks
constant RED: std_logic_vector := "100";
constant YELLOW: std_logic_vector := "110";
-- for delay of 100ms
constant DELAY: integer := 2000000;
signal counter, counter_next: std_logic_vector(20 downto 0);
type states is (idle, state1, state2, state3);
signal state, state_next: states;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal explosion_rgb, explosion_mask: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
state <= idle;
counter <= (others => '0');
elsif falling_edge(clk) then
state <= state_next;
counter <= counter_next;
end if;
end process;
animation: process(state, counter, destruction)
begin
state_next <= state;
counter_next <= counter;
case state is
when idle =>
counter_next <= (others => '0');
if destruction = '1' then
state_next <= state1;
end if;
when state1 =>
if counter = DELAY - 1 then
counter_next <= (others => '0');
state_next <= state2;
else
counter_next <= counter + 1;
end if;
when state2 =>
if counter = DELAY - 1 then
counter_next <= (others => '0');
state_next <= state3;
else
counter_next <= counter + 1;
end if;
when state3 =>
if counter = DELAY - 1 then
counter_next <= (others => '0');
state_next <= idle;
else
counter_next <= counter + 1;
end if;
end case;
end process;
output_enable <= '1' when (state /= idle and
px_x >= origin_x and
px_x < origin_x + SIZE and
px_y >= origin_y and
px_y < origin_y + SIZE) else
'0';
explosion_mask <= explosion_rgb when state = state1 and
-- only allow reg through
explosion_rgb(1) = '0' else
explosion_rgb when state = state2 and
-- allow red and yellow through
explosion_rgb(0) = '0' else
-- allow all colours through
explosion_rgb when state = state3 else
(others => '0');
rgb_pixel <= explosion_mask when output_enable = '1' else (others => '0');
row_address <= px_y(4 downto 0) - origin_y(4 downto 0);
col_address <= px_x(4 downto 0) - origin_x(4 downto 0);
addr <= row_address & col_address;
explosion:
entity work.explosion_rom(content)
port map(addr => addr, data => explosion_rgb);
end behaviour;
|
bsd-2-clause
|
bc665ab4c7cded70b687be66e49843e2
| 0.486272 | 4.435597 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
| 1 | 7,314 |
-- $Id: tb_nexys2_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- tb_nexys2_core
-- vlib/serport/serport_uart_rxtx
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_nexys2_fusp is
end tb_nexys2_fusp;
architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 20 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
begin
TBCORE : tbcore_rlink_dcm
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_fusp_aif
port map (
I_CLK50 => CLKOSC,
O_CLKSYS => CLKSYS,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-2.0
|
cbf4d88d95ea173aead7f594dd4db485
| 0.535822 | 3.065381 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/i2c_master/i2c_master.vhd
| 1 | 3,475 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- I 2 C M A S T E R E A S Y C O R E
-- (i2c_master.vhd)
--
-- Structural
--
-- Adapts the i2c_master_top module to easyFPGA
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
ENTITY i2c_master is
-------------------------------------------------------------------------------
port (
-- WISHBONE interface (with clock input)
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- I2C master interface
i2c_sda_io : inout std_logic;
i2c_scl_io : inout std_logic
);
end i2c_master;
-------------------------------------------------------------------------------
ARCHITECTURE structural of i2c_master is
-------------------------------------------------------------------------------
signal scl_pad_i_s : std_logic; -- i2c clock line input
signal scl_pad_o_s : std_logic; -- i2c clock line output
signal scl_padoen_o_s : std_logic; -- i2c clock line output enable, active low
signal sda_pad_i_s : std_logic; -- i2c data line input
signal sda_pad_o_s : std_logic; -- i2c data line output
signal sda_padoen_o_s : std_logic; -- i2c data line output enable, active low
-------------------------------------------------------------------------------
begin -- architecture structural
-------------------------------------------------------------------------------
-- tristate drivers
sda_pad_i_s <= i2c_sda_io;
i2c_sda_io <= 'Z' when sda_padoen_o_s = '1' else sda_pad_o_s;
scl_pad_i_s <= i2c_scl_io;
i2c_scl_io <= 'Z' when scl_padoen_o_s = '1' else scl_pad_o_s;
-------------------------------------------------------------------------------
I2C_MASTER_CORE : entity work.i2c_master_top -- vhdl'93-style direct instance
-------------------------------------------------------------------------------
port map (
-- WISHBONE interface
wb_clk_i => wbs_in.clk,
wb_rst_i => wbs_in.rst,
wb_cyc_i => wbs_in.cyc,
wb_stb_i => wbs_in.stb,
wb_adr_i => wbs_in.adr(2 downto 0),
wb_we_i => wbs_in.we,
wb_dat_i => wbs_in.dat,
wb_dat_o => wbs_out.dat,
wb_ack_o => wbs_out.ack,
wb_inta_o => wbs_out.irq,
-- Unidirectional I2C lines
scl_pad_i => scl_pad_i_s,
scl_pad_o => scl_pad_o_s,
scl_padoen_o => scl_padoen_o_s,
sda_pad_i => sda_pad_i_s,
sda_pad_o => sda_pad_o_s,
sda_padoen_o => sda_padoen_o_s
);
end structural;
|
gpl-3.0
|
4c7cccce01c38a9d6e6e6f91130908f4
| 0.489784 | 3.69288 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd
| 1 | 18,382 |
-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_xfirst_gen_unisim - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_xfirst_gen_unisim;
architecture syn of ram_2swsr_xfirst_gen_unisim is
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
begin
assert AWIDTH>=9 and AWIDTH<=15
report "assert(AWIDTH>=9 and AWIDTH<=15): unsupported BRAM from factor"
severity failure;
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => O"000000000000",
INIT_B => O"000000000000",
SRVAL_A => O"000000000000",
SRVAL_B => O"000000000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(36*i+31 downto 36*i),
DOB => L_DOB(36*i+31 downto 36*i),
DOPA => L_DOA(36*i+35 downto 36*i+32),
DOPB => L_DOB(36*i+35 downto 36*i+32),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(36*i+31 downto 36*i),
DIB => L_DIB(36*i+31 downto 36*i),
DIPA => L_DIA(36*i+35 downto 36*i+32),
DIPB => L_DIB(36*i+35 downto 36*i+32),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_09_S36;
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => X"00000000",
INIT_B => X"00000000",
SRVAL_A => X"00000000",
SRVAL_B => X"00000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(32*i+31 downto 32*i),
DOB => DOB(32*i+31 downto 32*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(32*i+31 downto 32*i),
DIB => DIB(32*i+31 downto 32*i),
DIPA => "0000",
DIPB => "0000",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_09_S32;
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => O"000000",
INIT_B => O"000000",
SRVAL_A => O"000000",
SRVAL_B => O"000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(18*i+15 downto 18*i),
DOB => L_DOB(18*i+15 downto 18*i),
DOPA => L_DOA(18*i+17 downto 18*i+16),
DOPB => L_DOB(18*i+17 downto 18*i+16),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(18*i+15 downto 18*i),
DIB => L_DIB(18*i+15 downto 18*i),
DIPA => L_DIA(18*i+17 downto 18*i+16),
DIPB => L_DIB(18*i+17 downto 18*i+16),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_10_S18;
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => X"0000",
INIT_B => X"0000",
SRVAL_A => X"0000",
SRVAL_B => X"0000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(16*i+15 downto 16*i),
DOB => DOB(16*i+15 downto 16*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(16*i+15 downto 16*i),
DIB => DIB(16*i+15 downto 16*i),
DIPA => "00",
DIPB => "00",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_10_S16;
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => O"000",
INIT_B => O"000",
SRVAL_A => O"000",
SRVAL_B => O"000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(9*i+7 downto 9*i),
DOB => L_DOB(9*i+7 downto 9*i),
DOPA => L_DOA(9*i+8 downto 9*i+8),
DOPB => L_DOB(9*i+8 downto 9*i+8),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(9*i+7 downto 9*i),
DIB => L_DIB(9*i+7 downto 9*i),
DIPA => L_DIA(9*i+8 downto 9*i+8),
DIPB => L_DIB(9*i+8 downto 9*i+8),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_11_S9;
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => X"00",
INIT_B => X"00",
SRVAL_A => X"00",
SRVAL_B => X"00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(8*i+7 downto 8*i),
DOB => DOB(8*i+7 downto 8*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(8*i+7 downto 8*i),
DIB => DIB(8*i+7 downto 8*i),
DIPA => "0",
DIPB => "0",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_11_S8;
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4_S4
generic map (
INIT_A => X"0",
INIT_B => X"0",
SRVAL_A => X"0",
SRVAL_B => X"0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(4*i+3 downto 4*i),
DOB => L_DOB(4*i+3 downto 4*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(4*i+3 downto 4*i),
DIB => L_DIB(4*i+3 downto 4*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_12_S4;
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2_S2
generic map (
INIT_A => "00",
INIT_B => "00",
SRVAL_A => "00",
SRVAL_B => "00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(2*i+1 downto 2*i),
DOB => L_DOB(2*i+1 downto 2*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(2*i+1 downto 2*i),
DIB => L_DIB(2*i+1 downto 2*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_13_S2;
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1_S1
generic map (
INIT_A => "0",
INIT_B => "0",
SRVAL_A => "0",
SRVAL_B => "0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(i downto i),
DOB => DOB(i downto i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(i downto i),
DIB => DIB(i downto i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_14_S1;
AW_15_S1: if AWIDTH = 15 generate
signal DOA0: slv(DWIDTH-1 downto 0) := (others=> '0');
signal DOA1: slv(DWIDTH-1 downto 0) := (others=> '0');
signal DOB0: slv(DWIDTH-1 downto 0) := (others=> '0');
signal DOB1: slv(DWIDTH-1 downto 0) := (others=> '0');
signal OSELA: slbit := '0';
signal OSELB: slbit := '0';
signal ENA0: slbit := '0';
signal ENB0: slbit := '0';
signal ENA1: slbit := '0';
signal ENB1: slbit := '0';
signal WEA0: slbit := '0';
signal WEB0: slbit := '0';
signal WEA1: slbit := '0';
signal WEB1: slbit := '0';
varible isela: slbit := '0';
varible iselb: slbit := '0';
begin
GL: for i in DWIDTH-1 downto 0 generate
MEM0 : RAMB16_S1_S1
generic map (
INIT_A => "0",
INIT_B => "0",
SRVAL_A => "0",
SRVAL_B => "0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA0(i downto i),
DOB => DOB0(i downto i),
ADDRA => ADDRA(AWIDTH - 2 downto 0),
ADDRB => ADDRB(AWIDTH - 2 downto 0),
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(i downto i),
DIB => DIB(i downto i),
ENA => ENA0,
ENB => ENB0,
SSRA => '0',
SSRB => '0',
WEA => WEA0,
WEB => WEB0
);
MEM1 : RAMB16_S1_S1
generic map (
INIT_A => "0",
INIT_B => "0",
SRVAL_A => "0",
SRVAL_B => "0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA1(i downto i),
DOB => DOB1(i downto i),
ADDRA => ADDRA(AWIDTH - 2 downto 0),
ADDRB => ADDRB(AWIDTH - 2 downto 0),
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(i downto i),
DIB => DIB(i downto i),
ENA => ENA1,
ENB => ENB1,
SSRA => '0',
SSRB => '0',
WEA => WEA1,
WEB => WEB1
);
end generate GL;
process
begin
wait until rising_edge(CLKA);
if ENA = '1' then
OSELA <= ADDRA(AWIDTH - 1);
end if;
end process;
process
begin
wait until rising_edge(CLKB);
if ENB = '1' then
OSELB <= ADDRB(AWIDTH - 1);
end if;
end process;
DOA <= DOA0 when OSELA = '0' else DOA1;
DOB <= DOB0 when OSELB = '0' else DOB1;
isela := ADDRA(AWIDTH - 1);
iselb := ADDRB(AWIDTH - 1);
ENA0 <= ENA and not isela;
ENB0 <= ENB and not iselb;
ENA1 <= ENA and isela;
ENB1 <= ENB and iselb;
WEA0 <= WEA and not isela;
WEB0 <= WEB and not iselb;
WEA1 <= WEA and isela;
WEB1 <= WEB and iselb;
end generate AW_15_S1;
end syn;
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
|
gpl-2.0
|
a8f379d5fafb1d7f5972480a36371888
| 0.455826 | 3.370988 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/windows_manager_arch_tb.vhd
| 1 | 3,408 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:07:59 10/22/2017
-- Design Name:
-- Module Name: C:/Users/DELL/Desktop/Processor3/Processor/windows_manager_arch_tb.vhd
-- Project Name: Processor
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: windows_manager_arch
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY windows_manager_arch_tb IS
END windows_manager_arch_tb;
ARCHITECTURE behavior OF windows_manager_arch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT windows_manager_arch
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic;
nrs1 : OUT std_logic_vector(5 downto 0);
nrs2 : OUT std_logic_vector(5 downto 0);
nrd : OUT std_logic_vector(5 downto 0);
nCWP : OUT std_logic;
no7 : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal rd : std_logic_vector(4 downto 0) := (others => '0');
signal op : std_logic_vector(1 downto 0) := (others => '0');
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
signal CWP : std_logic := '0';
--Outputs
signal nrs1 : std_logic_vector(5 downto 0);
signal nrs2 : std_logic_vector(5 downto 0);
signal nrd : std_logic_vector(5 downto 0);
signal nCWP : std_logic;
signal no7 : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: windows_manager_arch PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
op => op,
op3 => op3,
CWP => CWP,
nrs1 => nrs1,
nrs2 => nrs2,
nrd => nrd,
nCWP => nCWP,
no7 => no7
);
-- Stimulus process
stim_proc: process
begin
rs1 <= "10000";
rs2 <= "10001";
rd <= "10010";
cwp <= '0';
op <= "10";
op3 <="000000";
wait for 20 ns;
cwp <= '1';
wait for 20 ns;
rs1 <= "11000";
rs2 <= "11001";
rd <= "11010";
wait for 20 ns;
op <= "10";
op3 <= "111101";
wait for 20 ns;
rs1 <= "00000";
rs2 <= "00001";
rd <= "00010";
wait for 20 ns;
cwp <= '1';
wait;
end process;
END;
|
mit
|
6d052049a430e17357ad4d627a114c53
| 0.564847 | 3.517028 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/MUX_COR.vhd
| 1 | 833 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_COR is
Port ( ALUaddress : in STD_LOGIC_VECTOR (31 downto 0);
PC_dis30 : in STD_LOGIC_VECTOR (31 downto 0);
PC_seu : in STD_LOGIC_VECTOR (31 downto 0);
PC_4 : in STD_LOGIC_VECTOR (4 downto 0);
PCsource : in STD_LOGIC_VECTOR (1 downto 0);
MUXout : out STD_LOGIC_VECTOR (4 downto 0)
);
end MUX_COR;
architecture Behavioral of MUX_COR is
begin
process(ALUaddress, PC_dis30, PC_seu, PC_4, PCsource) begin
case PCsource is
when "00" =>
MUXout <= ALUaddress(4 downto 0);
when "01" =>
MUXout <= PC_dis30(4 downto 0);
when "10" =>
MUXout <= PC_seu(4 downto 0);
when "11" =>
MUXout <= PC_4;
when others =>
MUXout <= PC_4;
end case;
end process;
end Behavioral;
|
mit
|
1e6c4c0c362100369b0056c2a9c6610e
| 0.587035 | 3.029091 | false | false | false | false |
willprice/build-a-comp-vhdl-modules
|
base/LU.vhd
| 1 | 735 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LU is
port(
a_in : in unsigned(3 downto 0);
b_in : in unsigned(3 downto 0);
control_in : in unsigned(3 downto 0);
control_out : out unsigned(3 downto 0);
data_out : out unsigned(3 downto 0)
);
end entity LU;
architecture Behavioural of LU is
begin
control_out <= control_in;
process(a_in, b_in, control_in) is
begin
case (control_in(1 downto 0)) is
when "00" => data_out <= not a_in;
when "01" => data_out <= a_in and b_in;
when "10" => data_out <= a_in or b_in;
when "11" => data_out <= a_in xor b_in;
when others => data_out <= "0000";
end case;
end process;
end architecture Behavioural;
|
mit
|
2215bde600cf9f8ce6cd46722d516cc0
| 0.619048 | 2.672727 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/CU_tb.vhd
| 3 | 1,182 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CU_TB IS
END CU_TB;
ARCHITECTURE behavior OF CU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CU
PORT(
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
aluop : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal op : std_logic_vector(1 downto 0) := (others => '0');
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal aluop : std_logic_vector(5 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CU PORT MAP (
op => op,
op3 => op3,
aluop => aluop
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns
-- insert stimulus here
op <= "10";
op3 <= "000000";
wait for 20 ns;
op3 <= "000001";
wait for 20 ns;
op3 <= "000100";
wait for 20 ns;
op3 <= "000010";
wait;
end process;
END;
|
mit
|
d07f1664439fabe0d95f43e1f08cc32a
| 0.588832 | 3.517857 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd
| 1 | 4,000 |
-- $Id: nexys2_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys2_fusp_dummy;
architecture syn of nexys2_fusp_dummy is
begin
O_CLKSYS <= I_CLK50; -- use 50 MHz clock
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
gpl-2.0
|
236e534e50f8294d889e4aeef4775acd
| 0.52875 | 3.352892 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/DataPath.vhd
| 3 | 2,067 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity DataPath is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Data_Out : out STD_LOGIC_VECTOR(31 downto 0)
);
end DataPath;
architecture Behavioral of DataPath is
component PC is
port (
DAT_in : in std_logic_vector (31 downto 0);
rst : in std_logic;
clk : in std_logic;
DAT_out : out std_logic_vector (31 downto 0)
);
end component PC;
component Sumador is
port (
Operador1 : in std_logic_vector (31 downto 0);
Operador2 : in std_logic_vector (31 downto 0);
Resultado : out std_logic_vector (31 downto 0)
);
end component Sumador;
component IM is
port (
rst : in std_logic;
addr : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
);
end component IM;
signal addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal mid_addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal new_addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal aumento: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal instruction: std_logic_vector(31 downto 0);
begin
-- Instantiate nPC
nPC : PC
port map (
rst => rst,
clk => clk,
DAT_in => new_addr,
DAT_out => mid_addr
);
-- Instantiate PC
ProgC : PC
port map (
rst => rst,
clk => clk,
DAT_in => mid_addr,
DAT_out => addr
);
-- Instantiate Sumador
Adder : Sumador
port map (
Operador1 => addr,
Operador2 => aumento,
Resultado => new_addr
);
-- Instantiate IM
Instruction_mem : IM
port map (
rst => rst,
addr => addr,
data => Data_out
);
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
aumento <= "00000000000000000000000000000000";
else
aumento <= "00000000000000000000000000000001";
end if;
end if;
end process;
end Behavioral;
|
mit
|
9718347fc1086a7dc514d84f4851292e
| 0.623609 | 3.433555 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/soc_bridge_tb.vhd
| 1 | 78,856 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- S O C B R I D G E T E S T B E N C H (soc_bridge_tb.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
-------------------------------------------------------------------------------
ENTITY soc_bridge_tb is
-------------------------------------------------------------------------------
begin
end soc_bridge_tb;
-------------------------------------------------------------------------------
ARCHITECTURE simulation of soc_bridge_tb is
-------------------------------------------------------------------------------
-- constants
constant CLK_PERIOD : time := 25 ns;
constant DATA_OUT_MAX : integer := 300;
constant WBS1_ADR : std_logic_vector(WB_CORE_AW-1 downto 0) := x"01";
constant WBS2_ADR : std_logic_vector(WB_CORE_AW-1 downto 0) := x"02";
constant WBS3_ADR : std_logic_vector(WB_CORE_AW-1 downto 0) := x"03";
constant WBS8_ADR : std_logic_vector(WB_CORE_AW-1 downto 0) := x"08"; -- alias for WBS3
-- signals
signal fpga_active_i : std_logic;
signal mcu_active_o : std_logic;
signal fifo_data_io : std_logic_vector(7 downto 0);
signal fifo_rxf_n_i : std_logic;
signal fifo_txe_n_i : std_logic;
signal fifo_rd_n_o : std_logic;
signal fifo_wr_o : std_logic;
signal clk_s : std_logic;
signal wbm_out_s : wbm_out_type;
signal wbm_in_s : wbm_in_type;
-- wishbone slaves
signal wbs1_in_s : wbs_in_type;
signal wbs1_out_s : wbs_out_type;
signal wbs1_reg1_out_s: std_logic_vector(7 downto 0);
signal wbs1_reg2_out_s: std_logic_vector(7 downto 0);
signal wbs2_in_s : wbs_in_type;
signal wbs2_out_s : wbs_out_type;
signal wbs2_reg1_out_s: std_logic_vector(7 downto 0);
signal wbs2_reg2_out_s: std_logic_vector(7 downto 0);
signal wbs3_in_s : wbs_in_type;
signal wbs3_out_s : wbs_out_type;
-- intercon signals
signal core_adr_s : std_logic_vector(WB_CORE_AW-1 downto 0);
signal reg_adr_s : std_logic_vector(WB_REG_AW-1 downto 0);
signal adr_match_1_s : std_logic;
signal adr_match_2_s : std_logic;
signal adr_match_3_s : std_logic;
signal wishbone_rst_s : std_logic;
-- data output array (stores all bytes sent back by the soc bridge)
type data_out_t is array (0 to DATA_OUT_MAX) of std_logic_vector(7 downto 0);
signal data_out_s : data_out_t;
signal data_out_cnt_s : integer range 0 to DATA_OUT_MAX;
-------------------------------------------------
procedure send_to_fifo (
-------------------------------------------------
constant data : in unsigned;
signal data_io : out std_logic_vector(7 downto 0);
signal rxf_n_i : out std_logic;
signal rd_n_o : in std_logic
) is
begin
-- assert rxf and wait until rd was asserted
rxf_n_i <= '0';
wait until rd_n_o = '0';
wait for 50 ns; -- T3: 20..50 ns
-- apply data
data_io <= std_logic_vector(data);
-- wait until dut closes transfer
wait until rd_n_o = '1';
wait for 25 ns; -- T5: 0..25 ns
rxf_n_i <= '1';
-- hiZ data lines
data_io <= (others => 'Z');
wait for 80 ns; -- T6: >80 ns
end procedure send_to_fifo;
begin -- architecture simulation
------------------------------------------------------
DATA_OUT : process(clk_s, fifo_wr_o, fifo_data_io)
------------------------------------------------------
variable data_out_cnt : integer range 0 to DATA_OUT_MAX := 0;
begin
if (falling_edge(fifo_wr_o)) then
data_out_s(data_out_cnt) <= fifo_data_io;
data_out_cnt := data_out_cnt + 1;
data_out_cnt_s <= data_out_cnt;
end if;
end process DATA_OUT;
-------------------------------------------------
STIMULI_PROC :
-------------------------------------------------
process begin
------------------------------------
-- init
------------------------------------
wishbone_rst_s <= '1';
fpga_active_i <= '0';
fifo_rxf_n_i <= '1';
fifo_txe_n_i <= '0';
fifo_data_io <= (others => '-');
wait for 100 ns;
wishbone_rst_s <= '0';
wait for CLK_PERIOD*10;
------------------------------------
-- test fpga activation
------------------------------------
assert false
report "Will now activate fpga"
severity note;
fpga_active_i <= '1';
wait for CLK_PERIOD*2;
assert (mcu_active_o = '0')
report "enable_ctrl error"
severity error;
--------------------------------------------------------
-- test reaction on status read (actually for the MCU)
--------------------------------------------------------
assert false
report "Will now test reaction on status read"
severity note;
send_to_fifo(x"c3",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o);
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- nack
data_out_s(data_out_cnt_s - 3) = x"00" and -- id
data_out_s(data_out_cnt_s - 2) = x"11" and -- error code
data_out_s(data_out_cnt_s - 1) = x"00") -- parity
report "Invalid answer to status read"
severity error;
--------------------------------------------------------
-- test detect function
--------------------------------------------------------
assert false
report "Will now send DETECT"
severity note;
send_to_fifo(x"EE",fifo_data_io,fifo_rxf_n_i, fifo_rd_n_o);
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"FF" and -- detect reply opcode
data_out_s(data_out_cnt_s - 2) = x"EF" and -- fpga identifier
data_out_s(data_out_cnt_s - 1) = x"10") -- parity
report "Wrong reply to detect frame"
severity error;
------------------------------------
-- send register wr command
------------------------------------
assert false
report "Will now send REGISTER_WR"
severity note;
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"1D",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"53",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data
send_to_fifo(x"29",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"53")
report "REGISTER_WR failed!"
severity error;
--------------------------------------------------
-- send register wr command to non-existent core
--------------------------------------------------
assert false
report "Will now send REGISTER_WR to non-existent core"
severity note;
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"1F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"1F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- nack
data_out_s(data_out_cnt_s - 3) = x"1F" and -- id
data_out_s(data_out_cnt_s - 2) = x"33" and -- error code
data_out_s(data_out_cnt_s - 1) = x"3D") -- parity
report "Read back value differs from last write"
severity error;
------------------------------------
-- send register wr command (wrong parity)
------------------------------------
assert false
report "Will now send REGISTER_WR with wrong parity"
severity note;
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"1E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"53" and -- last write
data_out_s(data_out_cnt_s - 1) = x"FB") -- parity
report "Register WR with wrong parity changed register"
severity error;
------------------------------------
-- send register rd command (wrong parity)
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity (wrong)
wait for 10 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"21" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"12") -- parity
report "Unexpected reply to register RD with wrong parity"
severity error;
------------------------------------
-- send register mwr command
------------------------------------
assert false
report "Will now send REGISTER_MWR"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"1F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"BA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"BA" and -- last write
data_out_s(data_out_cnt_s - 1) = x"12") -- parity
report "Read back value differs from last write"
severity error;
-------------------------------------------------------------
-- send register mwr command that requires partial reception
-------------------------------------------------------------
assert false
report "Will now send a long REGISTER_MWR (14 data bytes)"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"0E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data5
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data6
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data7
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data8
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data9
send_to_fifo(x"AA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data10
send_to_fifo(x"BB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data11
send_to_fifo(x"CC",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data12
send_to_fifo(x"DD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data13
send_to_fifo(x"7b",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"DD" and -- last write
data_out_s(data_out_cnt_s - 1) = x"75") -- parity
report "Read back value differs from last write"
severity error;
-------------------------------------------------------------
-- send register mwr command that failed on harware
-------------------------------------------------------------
assert false
report "Will now send a long REGISTER_MWR (11 data bytes)"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"0E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"0B",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"30",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data5
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data6
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data7
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data8
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data9
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data10
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"41" and -- last write
data_out_s(data_out_cnt_s - 1) = x"E9") -- parity
report "Read back value differs from last write"
severity error;
--------------------------------------------------------------------
-- send register mwr command that requires more partial receptions
--------------------------------------------------------------------
assert false
report "Will now send a 64 byte long REGISTER_MWR"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"0e",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"40",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0 - sequence begin 0
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data5
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data6
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data7
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data8
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data9
send_to_fifo(x"42",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data10
send_to_fifo(x"43",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data11
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data12
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data13
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data14
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data15 - sequence begin 1
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data16
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data17
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data18
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data19
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data20
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data21
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data22
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data23
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data24
send_to_fifo(x"42",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data25
send_to_fifo(x"43",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data26
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data27
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data28
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data29
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data30 - sequence begin 2
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data31
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data32
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data33
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data34
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data35
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data36
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data37
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data38
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data39
send_to_fifo(x"42",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data40
send_to_fifo(x"43",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data41
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data42
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data43
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data44
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data45 - sequence begin 3
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data46
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data47
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data48
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data49
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data50
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data51
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data52
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data53
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data54
send_to_fifo(x"42",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data55
send_to_fifo(x"43",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data56
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data57
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data58
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data59 - sequence begin 4
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data60
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data61
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data62
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data63
send_to_fifo(x"2E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"34")
report "REGISTER_MWR failed!"
severity error;
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"34" and -- last write
data_out_s(data_out_cnt_s - 1) = x"9C") -- parity
report "Read back value differs from last write"
severity error;
--------------------------------------------------------------------
-- send very short register mwr command
--------------------------------------------------------------------
assert false
report "Will now send a very short REGISTER_MWR"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"23",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"46",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"23")
report "REGISTER_MWR failed!"
severity error;
-------------------------------------
-- send register mwr with length 0
-------------------------------------
assert false
report "Will now send REGISTER_MWR with length 0"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"23")
report "REGISTER_MWR with length 0 changed register content"
severity error;
--------------------------------------------------------------------
-- send very short register mwr command with wrong parity
--------------------------------------------------------------------
assert false
report "Will now send a very short REGISTER_MWR with wrong parity"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"19",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"FC",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"19" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"2A") -- parity
report "Did not reply NACK after REGISTER_MWR with wrong parity"
severity error;
-- this warning will be thrown since not all request data is known while
-- already writing to registers. Parity check is performed afterwards.
assert (wbs1_reg1_out_s = x"23")
report "REGISTER_MWR with wrong parity affected register"
severity warning;
-----------------------------------------------------------
-- send register mwr to non-existent core
-----------------------------------------------------------
assert false
report "Will now send REGISTER_MWR to non-existent core"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"09",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"90",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"05",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"AF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"56" and -- id
data_out_s(data_out_cnt_s - 2) = x"33" and -- error code
data_out_s(data_out_cnt_s - 1) = x"74") -- parity
report "Did not reply NACK after trying to access non-existent core"
severity error;
------------------------------------
-- send register awr command
------------------------------------
assert false
report "Will now send REGISTER_AWR"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"CD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"C3",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert ((wbs1_reg1_out_s = x"AB") and (wbs1_reg2_out_s = x"CD"))
report "Register AWR failed"
severity error;
------------------------------------------------
-- send register awr command with wrong parity
------------------------------------------------
assert false
report "Will now send REGISTER_AWR with wrong parity"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"CD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"22" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"11") -- parity
report "Did not reply NACK after REGISTER_AWR with wrong parity"
severity error;
------------------------------------------------------
-- send register awr that failed in integration test
------------------------------------------------------
assert false
report "Will now send REGISTER_AWR with length 4"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"08",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"14",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"04",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"87",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"E6",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"00" and -- ACK opcode
data_out_s(data_out_cnt_s - 2) = x"EF" and -- id
data_out_s(data_out_cnt_s - 1) = x"EF") -- parity
report "Did not reply ACK after REGISTER_AWR with length 4"
severity error;
-------------------------------------
-- send register awr with length 0
-------------------------------------
assert false
report "Will now send REGISTER_AWR with length 0"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"49",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert ((wbs1_reg1_out_s = x"AB") and (wbs1_reg2_out_s = x"CD"))
report "Register AWR with length 0 changed register content"
severity error;
-----------------------------------------------------------
-- send register awr that exceeds register address range
-----------------------------------------------------------
assert false
report "Will now send REGISTER_AWR that exceeds register address range - test wrap-around"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"FE",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"CD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"3F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"EF")
report "Register AWR wrap-around failed"
severity error;
-----------------------------------------------------------
-- send register awr to non-existent core
-----------------------------------------------------------
assert false
report "Will now send REGISTER_AWR to non-existent core"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"F0",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"F0",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"CD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"C1",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"22" and -- id
data_out_s(data_out_cnt_s - 2) = x"33" and -- error code
data_out_s(data_out_cnt_s - 1) = x"00") -- parity
report "Did not reply NACK after trying to access non-existent core"
severity error;
-----------------------------------------------------------
-- load 256-register core with data using awr
-----------------------------------------------------------
assert false
report "Will now load data to 256 register core"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data5
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data6
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data7
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data8
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data9
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data10
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data11
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data12
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data13
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data14
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data15
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data16
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data17
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data18
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data19
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data20
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data21
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data22
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data23
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data24
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data25
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data26
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data27
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data28
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data29
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data30
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data31
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data32
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data33
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data34
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data35
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data36
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data37
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data38
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data39
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data40
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data41
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data42
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data43
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data44
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data45
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data46
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data47
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data48
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data49
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data50
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data51
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data52
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data53
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data54
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data55
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data56
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data57
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data58
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data59
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data60
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data61
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data62
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data63
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data64
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data65
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data66
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data67
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data68
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data69
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data70
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data71
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data72
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data73
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data74
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data75
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data76
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data77
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data78
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data79
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data80
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data81
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data82
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data83
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data84
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data85
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data86
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data87
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data88
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data89
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data90
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data91
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data92
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data93
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data94
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data95
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data96
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data97
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data98
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data99
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data100
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data101
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data102
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data103
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data104
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data105
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data106
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data107
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data108
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data109
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data110
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data111
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data112
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data113
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data114
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data115
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data116
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data117
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data118
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data119
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data120
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data121
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data122
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data123
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data124
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data125
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data126
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data127
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data128
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data129
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data130
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data131
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data132
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data133
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data134
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data135
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data136
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data137
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data138
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data139
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data140
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data141
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data142
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data143
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data144
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data145
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data146
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data147
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data148
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data149
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data150
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data151
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data152
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data153
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data154
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data155
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data156
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data157
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data158
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data159
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data160
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data161
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data162
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data163
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data164
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data165
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data166
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data167
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data168
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data169
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data170
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data171
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data172
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data173
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data174
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data175
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data176
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data177
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data178
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data179
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data180
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data181
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data182
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data183
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data184
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data185
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data186
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data187
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data188
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data189
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data190
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data191
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data192
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data193
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data194
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data195
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data196
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data197
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data198
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data199
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data200
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data201
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data202
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data203
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data204
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data205
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data206
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data207
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data208
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data209
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data210
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data211
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data212
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data213
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data214
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data215
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data216
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data217
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data218
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data219
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data220
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data221
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data222
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data223
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data224
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data225
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data226
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data227
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data228
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data229
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data230
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data231
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data232
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data233
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data234
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data235
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data236
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data237
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data238
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data239
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data240
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data241
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data242
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data243
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data244
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data245
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data246
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data247
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data248
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data249
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data250
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data251
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data252
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data253
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data254
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"00" and -- ACK opcode
data_out_s(data_out_cnt_s - 2) = x"69" and -- id
data_out_s(data_out_cnt_s - 1) = x"69") -- parity
report "Did not reply ACK after 256-byte AWR"
severity error;
-----------------------------------------------------------
-- send register ard to read two bytes
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD with length 2"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"23",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"02",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"59",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 10 us;
assert( data_out_s(data_out_cnt_s - 5) = x"90" and -- ARDRE opcode
data_out_s(data_out_cnt_s - 4) = x"23" and -- id
data_out_s(data_out_cnt_s - 3) = x"EF" and -- data0
data_out_s(data_out_cnt_s - 2) = x"CD" and -- data1
data_out_s(data_out_cnt_s - 1) = x"91") -- parity
report "Reading 2 bytes using ARD failed"
severity error;
-----------------------------------------------------------
-- send register ard to non-existent core
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD to non-existent core"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"24",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"02",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"24" and -- id
data_out_s(data_out_cnt_s - 2) = x"33" and -- error code
data_out_s(data_out_cnt_s - 1) = x"06") -- parity
report "Did not reply NACK after trying to access (ARD) non-existent core"
severity error;
-----------------------------------------------------------
-- send register ard to with wrong parity
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD with wrong parity"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"25",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"12",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"12",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"25" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"16") -- parity
report "Did not reply NACK after REGISTER_ARD with wrong parity"
severity error;
-----------------------------------------------------------
-- send register ard with length 0
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD with length 0"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"4D",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"90" and -- ARDRE opcode
data_out_s(data_out_cnt_s - 2) = x"35" and -- id
data_out_s(data_out_cnt_s - 1) = x"A5") -- parity
report "Unexpected answer to ARD with length 0"
severity error;
-----------------------------------------------------------
-- send register ard to read 100 bytes
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD with length 100"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"25",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"64",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length = 100
send_to_fifo(x"3b",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 50 us;
assert( data_out_s(data_out_cnt_s - 103) = x"90" and -- ARDRE opcode
data_out_s(data_out_cnt_s - 102) = x"25" and -- id
data_out_s(data_out_cnt_s - 101) = x"FF" and -- data0
data_out_s(data_out_cnt_s - 100) = x"03" and -- data1
data_out_s(data_out_cnt_s - 99) = x"11" and -- data2
data_out_s(data_out_cnt_s - 98) = x"11" and -- data3
data_out_s(data_out_cnt_s - 97) = x"22" and -- data4
data_out_s(data_out_cnt_s - 96) = x"22" and -- data5
data_out_s(data_out_cnt_s - 95) = x"33" and -- data6
data_out_s(data_out_cnt_s - 94) = x"33" and -- data7
data_out_s(data_out_cnt_s - 93) = x"44" and -- data8
data_out_s(data_out_cnt_s - 92) = x"44" and -- data9
data_out_s(data_out_cnt_s - 91) = x"55" and -- data10
data_out_s(data_out_cnt_s - 90) = x"55" and -- data11
data_out_s(data_out_cnt_s - 89) = x"66" and -- data12
data_out_s(data_out_cnt_s - 88) = x"66" and -- data13
data_out_s(data_out_cnt_s - 87) = x"77" and -- data14
data_out_s(data_out_cnt_s - 86) = x"77" and -- data15
data_out_s(data_out_cnt_s - 85) = x"88" and -- data16
data_out_s(data_out_cnt_s - 84) = x"88" and -- data17
data_out_s(data_out_cnt_s - 83) = x"99" and -- data18
data_out_s(data_out_cnt_s - 82) = x"99" and -- data19
data_out_s(data_out_cnt_s - 81) = x"55" and -- data20
data_out_s(data_out_cnt_s - 80) = x"55" and -- data21
data_out_s(data_out_cnt_s - 79) = x"66" and -- data22
data_out_s(data_out_cnt_s - 78) = x"66" and -- data23
data_out_s(data_out_cnt_s - 77) = x"77" and -- data24
data_out_s(data_out_cnt_s - 76) = x"77" and -- data25
data_out_s(data_out_cnt_s - 75) = x"88" and -- data26
data_out_s(data_out_cnt_s - 74) = x"88" and -- data27
data_out_s(data_out_cnt_s - 73) = x"99" and -- data28
data_out_s(data_out_cnt_s - 72) = x"99" and -- data29
data_out_s(data_out_cnt_s - 71) = x"55" and -- data30
data_out_s(data_out_cnt_s - 70) = x"55" and -- data31
data_out_s(data_out_cnt_s - 69) = x"66" and -- data32
data_out_s(data_out_cnt_s - 68) = x"66" and -- data33
data_out_s(data_out_cnt_s - 67) = x"77" and -- data34
data_out_s(data_out_cnt_s - 66) = x"77" and -- data35
data_out_s(data_out_cnt_s - 65) = x"88" and -- data36
data_out_s(data_out_cnt_s - 64) = x"88" and -- data37
data_out_s(data_out_cnt_s - 63) = x"99" and -- data38
data_out_s(data_out_cnt_s - 62) = x"99" and -- data39
data_out_s(data_out_cnt_s - 61) = x"55" and -- data40
data_out_s(data_out_cnt_s - 60) = x"55" and -- data41
data_out_s(data_out_cnt_s - 59) = x"66" and -- data42
data_out_s(data_out_cnt_s - 58) = x"66" and -- data43
data_out_s(data_out_cnt_s - 57) = x"77" and -- data44
data_out_s(data_out_cnt_s - 56) = x"77" and -- data45
data_out_s(data_out_cnt_s - 55) = x"88" and -- data46
data_out_s(data_out_cnt_s - 54) = x"88" and -- data47
data_out_s(data_out_cnt_s - 53) = x"99" and -- data48
data_out_s(data_out_cnt_s - 52) = x"99" and -- data49
data_out_s(data_out_cnt_s - 51) = x"55" and -- data50
data_out_s(data_out_cnt_s - 50) = x"55" and -- data51
data_out_s(data_out_cnt_s - 49) = x"66" and -- data52
data_out_s(data_out_cnt_s - 48) = x"66" and -- data53
data_out_s(data_out_cnt_s - 47) = x"77" and -- data54
data_out_s(data_out_cnt_s - 46) = x"77" and -- data55
data_out_s(data_out_cnt_s - 45) = x"88" and -- data56
data_out_s(data_out_cnt_s - 44) = x"88" and -- data57
data_out_s(data_out_cnt_s - 43) = x"99" and -- data58
data_out_s(data_out_cnt_s - 42) = x"99" and -- data59
data_out_s(data_out_cnt_s - 41) = x"55" and -- data60
data_out_s(data_out_cnt_s - 40) = x"55" and -- data61
data_out_s(data_out_cnt_s - 39) = x"66" and -- data62
data_out_s(data_out_cnt_s - 38) = x"66" and -- data63
data_out_s(data_out_cnt_s - 37) = x"77" and -- data64
data_out_s(data_out_cnt_s - 36) = x"77" and -- data65
data_out_s(data_out_cnt_s - 35) = x"88" and -- data66
data_out_s(data_out_cnt_s - 34) = x"88" and -- data67
data_out_s(data_out_cnt_s - 33) = x"99" and -- data68
data_out_s(data_out_cnt_s - 32) = x"99" and -- data69
data_out_s(data_out_cnt_s - 31) = x"55" and -- data70
data_out_s(data_out_cnt_s - 30) = x"55" and -- data71
data_out_s(data_out_cnt_s - 29) = x"66" and -- data72
data_out_s(data_out_cnt_s - 28) = x"66" and -- data73
data_out_s(data_out_cnt_s - 27) = x"77" and -- data74
data_out_s(data_out_cnt_s - 26) = x"77" and -- data75
data_out_s(data_out_cnt_s - 25) = x"88" and -- data76
data_out_s(data_out_cnt_s - 24) = x"88" and -- data77
data_out_s(data_out_cnt_s - 23) = x"99" and -- data78
data_out_s(data_out_cnt_s - 22) = x"99" and -- data79
data_out_s(data_out_cnt_s - 21) = x"55" and -- data80
data_out_s(data_out_cnt_s - 20) = x"55" and -- data81
data_out_s(data_out_cnt_s - 19) = x"66" and -- data82
data_out_s(data_out_cnt_s - 18) = x"66" and -- data83
data_out_s(data_out_cnt_s - 17) = x"77" and -- data84
data_out_s(data_out_cnt_s - 16) = x"77" and -- data85
data_out_s(data_out_cnt_s - 15) = x"88" and -- data86
data_out_s(data_out_cnt_s - 14) = x"88" and -- data87
data_out_s(data_out_cnt_s - 13) = x"99" and -- data88
data_out_s(data_out_cnt_s - 12) = x"99" and -- data89
data_out_s(data_out_cnt_s - 11) = x"55" and -- data90
data_out_s(data_out_cnt_s - 10) = x"55" and -- data91
data_out_s(data_out_cnt_s - 9) = x"66" and -- data92
data_out_s(data_out_cnt_s - 8) = x"66" and -- data93
data_out_s(data_out_cnt_s - 7) = x"77" and -- data94
data_out_s(data_out_cnt_s - 6) = x"77" and -- data95
data_out_s(data_out_cnt_s - 5) = x"88" and -- data96
data_out_s(data_out_cnt_s - 4) = x"88" and -- data97
data_out_s(data_out_cnt_s - 3) = x"99" and -- data98
data_out_s(data_out_cnt_s - 2) = x"99" and -- data99
data_out_s(data_out_cnt_s - 1) = x"49" ) -- parity
report "Reading 100 bytes using ARD failed"
severity error;
-----------------------------------------------------------
-- send register mrd to read 3 bytes
-----------------------------------------------------------
assert false
report "Will now send REGISTER_MRD with length 3"
severity note;
send_to_fifo(x"73",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"26",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length = 3
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 6) = x"93" and -- MRDRE opcode
data_out_s(data_out_cnt_s - 5) = x"26" and -- id
data_out_s(data_out_cnt_s - 4) = x"FF" and -- data0
data_out_s(data_out_cnt_s - 3) = x"FF" and -- data1
data_out_s(data_out_cnt_s - 2) = x"FF" and -- data2
data_out_s(data_out_cnt_s - 1) = x"4A") -- parity
report "Unexpected answer to MRD with length 3"
severity error;
-----------------------------------------------------------
-- send register mrd to read 30 bytes
-----------------------------------------------------------
assert false
report "Will now send REGISTER_MRD with length 30"
severity note;
send_to_fifo(x"73",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"26",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"1E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length = 30
send_to_fifo(x"4B",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 20 us;
assert( data_out_s(data_out_cnt_s - 33) = x"93" and -- MRDRE opcode
data_out_s(data_out_cnt_s - 32) = x"26" and -- id
data_out_s(data_out_cnt_s - 31) = x"11" and -- data0
data_out_s(data_out_cnt_s - 30) = x"11" and -- data1
data_out_s(data_out_cnt_s - 29) = x"11" and -- data2
data_out_s(data_out_cnt_s - 28) = x"11" and -- data3
data_out_s(data_out_cnt_s - 27) = x"11" and -- data4
data_out_s(data_out_cnt_s - 26) = x"11" and -- data5
data_out_s(data_out_cnt_s - 25) = x"11" and -- data6
data_out_s(data_out_cnt_s - 24) = x"11" and -- data7
data_out_s(data_out_cnt_s - 23) = x"11" and -- data8
data_out_s(data_out_cnt_s - 22) = x"11" and -- data9
data_out_s(data_out_cnt_s - 21) = x"11" and -- data10
data_out_s(data_out_cnt_s - 20) = x"11" and -- data11
data_out_s(data_out_cnt_s - 19) = x"11" and -- data12
data_out_s(data_out_cnt_s - 18) = x"11" and -- data12
data_out_s(data_out_cnt_s - 17) = x"11" and -- data13
data_out_s(data_out_cnt_s - 16) = x"11" and -- data15
data_out_s(data_out_cnt_s - 15) = x"11" and -- data16
data_out_s(data_out_cnt_s - 14) = x"11" and -- data17
data_out_s(data_out_cnt_s - 13) = x"11" and -- data18
data_out_s(data_out_cnt_s - 12) = x"11" and -- data19
data_out_s(data_out_cnt_s - 11) = x"11" and -- data20
data_out_s(data_out_cnt_s - 10) = x"11" and -- data21
data_out_s(data_out_cnt_s - 9) = x"11" and -- data22
data_out_s(data_out_cnt_s - 8) = x"11" and -- data23
data_out_s(data_out_cnt_s - 7) = x"11" and -- data24
data_out_s(data_out_cnt_s - 6) = x"11" and -- data25
data_out_s(data_out_cnt_s - 5) = x"11" and -- data26
data_out_s(data_out_cnt_s - 4) = x"11" and -- data27
data_out_s(data_out_cnt_s - 3) = x"11" and -- data28
data_out_s(data_out_cnt_s - 2) = x"11" and -- data29
data_out_s(data_out_cnt_s - 1) = x"B5") -- parity
report "Unexpected answer to MRD with length 30"
severity error;
-----------------------------------------------------------
-- send register mrd with wrong parity
-----------------------------------------------------------
assert false
report "Will now send REGISTER_MRD with wrong parity"
severity note;
send_to_fifo(x"73",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"1E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length = 30
send_to_fifo(x"4B",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"99" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"AA") -- parity
report "Did not reply NACK after REGISTER_MRD with wrong parity"
severity error;
------------------------------------
-- enable interrupts (wrong parity)
------------------------------------
assert false
report "Will now send INT_EN (wrong parity)"
severity note;
send_to_fifo(x"AA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"27",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"AA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- wrong parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"27" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"14") -- parity
report "Did not reply NACK after INT_EN with wrong parity"
severity error;
------------------------------------
-- enable interrupts
------------------------------------
assert false
report "Will now send INT_EN"
severity note;
send_to_fifo(x"AA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"28",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"82",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"00" and -- NACK opcode
data_out_s(data_out_cnt_s - 2) = x"28" and -- id
data_out_s(data_out_cnt_s - 1) = x"28") -- parity
report "Did not reply ACK after INT_EN"
severity error;
------------------------------------
-- send MCU_SEL (wrong parity)
------------------------------------
assert false
report "Will now send MCU_SEL with wrong parity"
severity note;
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"29",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- wrong parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"29" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"1A") -- parity
report "Did not reply NACK after MCU_SEL with wrong parity"
severity error;
assert (mcu_active_o = '0')
report "Wrong parity MCU_SEL caused switching to MCU"
severity error;
------------------------------------
-- test switching back to mcu
------------------------------------
assert false
report "Will now send MCU_SEL"
severity note;
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"30",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (mcu_active_o = '1')
report "Switching back to MCU failed!"
severity error;
if (mcu_active_o = '1') then
fpga_active_i <= '0';
end if;
-- terminate simulation the hard way
assert false report "SIMULATION FINISHED" severity failure;
end process STIMULI_PROC;
-------------------------------------------------
-- UUT instantiation
-------------------------------------------------
UUT : entity work.soc_bridge
port map (
fpga_active_i => fpga_active_i,
mcu_active_o => mcu_active_o,
fifo_data_io => fifo_data_io,
fifo_rxf_n_i => fifo_rxf_n_i,
fifo_txe_n_i => fifo_txe_n_i,
fifo_rd_n_o => fifo_rd_n_o,
fifo_wr_o => fifo_wr_o,
wbm_i => wbm_in_s,
wbm_o => wbm_out_s
);
-- two pwm16 cores as slaves
WBS1 : entity work.wbs_dual_out
port map (
wbs_in => wbs1_in_s,
wbs_out => wbs1_out_s,
reg1_out => wbs1_reg1_out_s,
reg2_out => wbs1_reg2_out_s
);
WBS2 : entity work.wbs_dual_out
port map (
wbs_in => wbs2_in_s,
wbs_out => wbs2_out_s,
reg1_out => wbs2_reg1_out_s,
reg2_out => wbs2_reg2_out_s
);
WBS3 : entity work.wbs256
port map (
wbs_in => wbs3_in_s,
wbs_out => wbs3_out_s
);
---------------
-- Intercon
---------------
-- split address
reg_adr_s <= wbm_out_s.adr(WB_REG_AW-1 downto 0);
core_adr_s <= wbm_out_s.adr(WB_AW-1 downto WB_REG_AW);
-- connect common signals
wbs1_in_s.dat <= wbm_out_s.dat;
wbs2_in_s.dat <= wbm_out_s.dat;
wbs3_in_s.dat <= wbm_out_s.dat;
wbs1_in_s.adr <= reg_adr_s;
wbs2_in_s.adr <= reg_adr_s;
wbs3_in_s.adr <= reg_adr_s;
wbs1_in_s.we <= wbm_out_s.we;
wbs2_in_s.we <= wbm_out_s.we;
wbs3_in_s.we <= wbm_out_s.we;
wbs1_in_s.cyc <= wbs1_in_s.cyc;
wbs2_in_s.cyc <= wbs2_in_s.cyc;
wbs3_in_s.cyc <= wbs3_in_s.cyc;
wbm_in_s.clk <= clk_s;
wbs1_in_s.clk <= clk_s;
wbs2_in_s.clk <= clk_s;
wbs3_in_s.clk <= clk_s;
wbs1_in_s.rst <= wishbone_rst_s;
wbs2_in_s.rst <= wishbone_rst_s;
wbs3_in_s.rst <= wishbone_rst_s;
-- slave data out mux
with core_adr_s select wbm_in_s.dat <=
wbs1_out_s.dat when WBS1_ADR,
wbs2_out_s.dat when WBS2_ADR,
wbs3_out_s.dat when WBS3_ADR,
wbs3_out_s.dat when WBS8_ADR,
(others => '-') when others;
-- address comparator
adr_match_1_s <= '1' when core_adr_s = WBS1_ADR else '0';
adr_match_2_s <= '1' when core_adr_s = WBS2_ADR else '0';
adr_match_3_s <= '1' when (core_adr_s = WBS3_ADR OR core_adr_s = WBS8_ADR) else '0';
-- ack or gate
wbm_in_s.ack <= wbs1_out_s.ack or
wbs2_out_s.ack or
wbs3_out_s.ack;
-- stb and gates
wbs1_in_s.stb <= wbm_out_s.cyc and wbm_out_s.stb and adr_match_1_s;
wbs2_in_s.stb <= wbm_out_s.cyc and wbm_out_s.stb and adr_match_2_s;
wbs3_in_s.stb <= wbm_out_s.cyc and wbm_out_s.stb and adr_match_3_s;
-------------------------------------------------
CLK_GENERATOR :
-------------------------------------------------
process begin
clk_s <= '0';
wait for CLK_PERIOD/2;
clk_s <= '1';
wait for CLK_PERIOD/2;
end process CLK_GENERATOR;
end simulation;
|
gpl-3.0
|
2d7e6d97e06ef46ed39caed9e88a6e17
| 0.567794 | 2.491107 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
| 1 | 7,323 |
-- $Id: tb_nexys3_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- vlib/xlib/dcm_sfs
-- tb_nexys3_core
-- vlib/serport/serport_uart_rxtx
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp is
end tb_nexys3_fusp;
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 10 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
begin
TBCORE : tbcore_rlink_dcm
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
DCM_SYS : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKSYS,
LOCKED => open
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-2.0
|
cea2796fb3423a6ab4c327fddc94313d
| 0.532296 | 3.120153 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/vhdl/final_bitmap.vhd
| 1 | 1,533 |
-- ----------------------------------------------------------------------------
-- Entity for final bitmap representation
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity FINAL_BITMAP is
generic(
DATA_WIDTH : integer := 8
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
SET : in std_logic_vector(DATA_WIDTH - 1 downto 0);
-- output data interface
BITMAP : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity FINAL_BITMAP;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of FINAL_BITMAP is
begin
gen_reg: for i in 0 to DATA_WIDTH - 1 generate
reg: process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
BITMAP(i) <= '0';
else
if SET(i) = '1' then
BITMAP(i) <= '1';
end if;
end if;
end if;
end process reg;
end generate gen_reg;
end architecture full;
|
gpl-2.0
|
12349517faa858405df351fe9c165494
| 0.373125 | 5.161616 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd
| 1 | 3,977 |
-- $Id: tb_tst_serloop1_n2.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n2 - sim
-- Description: Test bench for sys_tst_serloop1_n2
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop2_n2 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n2
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop1_n2 is
end tb_tst_serloop1_n2;
architecture sim of tb_tst_serloop1_n2 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
UUT : entity work.sys_tst_serloop1_n2
port map (
I_CLK50 => CLK50,
O_CLKSYS => open,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FLA_CE_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK50,
CLKH => CLK50,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-2.0
|
2efa8ce313cedd3b7a41d75a19f1364a
| 0.530048 | 3.111894 | false | false | false | false |
AdanDuM/INE5406-SD
|
dec7seg.vhd
| 1 | 799 |
library IEEE;
use IEEE.std_logic_1164.all;
-- Alunos: Adan Pereira Gomes e Wesley Mayk Gama Luz
entity dec7seg is
port (
bcd_in: in std_logic_vector(3 downto 0);
dec_out: out std_logic_vector(6 downto 0)
);
end entity;
architecture structural of dec7seg is
begin
dec_out <= "1000000" when bcd_in = "0000" else -- 0
"1111001" when bcd_in = "0001" else -- 1
"0100100" when bcd_in = "0010" else -- 2
"0110000" when bcd_in = "0011" else -- 3
"0011001" when bcd_in = "0100" else -- 4
"0010010" when bcd_in = "0101" else -- 5
"0000010" when bcd_in = "0110" else -- 6
"1111000" when bcd_in = "0111" else -- 7
"0000000" when bcd_in = "1000" else -- 8
"0010000" when bcd_in = "1001" else -- 9
"0000110"; -- E - Error
end architecture;
|
gpl-2.0
|
0dcd9eff577b6e2637074fd0aeb2eec8
| 0.604506 | 2.843416 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/rlinklib.vhd
| 1 | 11,792 |
-- $Id: rlinklib.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rlinklib
-- Description: Definitions for rlink interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-21 442 3.2.1 retire old, deprecated interfaces
-- 2011-12-09 437 3.2 add rlink_core8
-- 2011-11-18 427 3.1.3 now numeric_std clean
-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
-- new rlink_serport interface;
-- rename rlink_core_serport->rlink_base_serport
-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.1 rename: [cd]crc->[cd]err, ioto->rbnak, ioerr->rberr
-- 2010-12-04 343 3.0 move rbus components to rbus/rblib; renames
-- rri_ -> rlink and c_rri -> c_rlink;
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport
-- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- 2010-05-01 285 2.1.3 remove rri_rb_rpcompat, now obsolete
-- 2010-04-18 279 2.1.2 rri_core_serport: drop RTSFBUF generic
-- 2010-04-10 275 2.1.1 add rri_core_serport
-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core, rri_serport;
-- CE_USEC, RTSFLUSH, CTS_N, RTS_N for rri_serport
-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
-- 2008-08-22 161 1.3 renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp
-- 2008-02-16 116 1.2.1 added rri_wreg(rw|w|r)_3
-- 2008-01-20 113 1.2 added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat
-- 2007-11-24 98 1.1 added RP_IINT for rri_core.
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.serport.all;
package rlinklib is
constant c_rlink_cpref : slv4 := "1000"; -- default comma prefix
constant c_rlink_ncomm : positive := 4; -- number commas (sop,eop,nak,attn)
constant c_rlink_dat_idle : slv9 := "100000000";
constant c_rlink_dat_sop : slv9 := "100000001";
constant c_rlink_dat_eop : slv9 := "100000010";
constant c_rlink_dat_nak : slv9 := "100000011";
constant c_rlink_dat_attn : slv9 := "100000100";
constant c_rlink_cmd_rreg : slv3 := "000";
constant c_rlink_cmd_rblk : slv3 := "001";
constant c_rlink_cmd_wreg : slv3 := "010";
constant c_rlink_cmd_wblk : slv3 := "011";
constant c_rlink_cmd_stat : slv3 := "100";
constant c_rlink_cmd_attn : slv3 := "101";
constant c_rlink_cmd_init : slv3 := "110";
constant c_rlink_iint_rbf_anena: integer := 15; -- anena flag
constant c_rlink_iint_rbf_itoena: integer := 14; -- itoena flag
subtype c_rlink_iint_rbf_itoval is integer range 7 downto 0; -- command code
subtype c_rlink_cmd_rbf_seq is integer range 7 downto 3; -- sequence number
subtype c_rlink_cmd_rbf_code is integer range 2 downto 0; -- command code
subtype c_rlink_stat_rbf_stat is integer range 7 downto 5; -- ext status bits
constant c_rlink_stat_rbf_attn: integer := 4; -- attention flags set
constant c_rlink_stat_rbf_cerr: integer := 3; -- command error
constant c_rlink_stat_rbf_derr: integer := 2; -- data error
constant c_rlink_stat_rbf_rbnak: integer := 1; -- rbus no ack or timeout
constant c_rlink_stat_rbf_rberr: integer := 0; -- rbus err bit set
type rl_moni_type is record -- rlink_core monitor port
eop : slbit; -- eop send in last cycle
attn : slbit; -- attn send in last cycle
lamp : slbit; -- attn (lam) pending
end record rl_moni_type;
constant rl_moni_init : rl_moni_type :=
('0','0','0'); -- eop,attn,lamp
-- ise 13.1 xst can bug check if generic defaults in a package are defined via
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
-- As workaround the ibus default addresses are defined here as constant.
constant rbaddr_rlink_serport : slv8 := slv(to_unsigned(2#11111110#,8));
-- this definition logically belongs into the 'for test benches' section'
-- must be here because it is needed as generic default in rlink_core8
-- simbus sb_cntl field usage for rlink
constant sbcntl_sbf_rlmon : integer := 15;
component rlink_core is -- rlink core with 9bit iface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6); -- idle timeout counter width
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit; -- rlink 9b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
component rlink_aif is -- rlink, abstract interface
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
RESET : in slbit :='0'; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit := '0' -- rlink 9b: data hold
);
end component;
component rlink_core8 is -- rlink core with 8bit iface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
RESET : in slbit; -- reset
RLB_DI : in slv8; -- rlink 8b: data in
RLB_ENA : in slbit; -- rlink 8b: data enable
RLB_BUSY : out slbit; -- rlink 8b: data busy
RLB_DO : out slv8; -- rlink 8b: data out
RLB_VAL : out slbit; -- rlink 8b: data valid
RLB_HOLD : in slbit; -- rlink 8b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
--
-- core + concrete_interface combo's
--
component rlink_sp1c is -- rlink_core8+serport_1clock combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
SER_MONI : out serport_moni_type -- serport: monitor port
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component rlink_mon is -- rlink monitor
generic (
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end component;
component rlink_mon_sb is -- simbus wrap for rlink monitor
generic (
DWIDTH : positive := 9; -- data port width (8 or 9)
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end component;
end package rlinklib;
|
gpl-2.0
|
b08c9c41cf238417d325c24caf417588
| 0.559023 | 3.608323 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega1/Instruction_Memory.vhd
| 1 | 3,482 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity IM is
port (
rst : in std_logic;
addr : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
);
end IM;
architecture behavioral of IM is
type memoria_rom is array (0 to 63) of std_logic_vector (31 downto 0);
signal ROM : memoria_rom := (
"10000010000100000010000000001000", --0: 82 10 20 08 mov 8, %g1
"10000100000100000011111111111001", --4: 84 10 3f f9 mov -7, %g2
"10010000000000000100000000000010", --8: 90 00 40 02 add %g1, %g2, %o0
--"10000010000110000100000000000010", --c: 82 18 40 02 xor %g1, %g2, %g1 ojo con este registro !!!
"10010100001010000100000000000010", --10: 94 28 40 02 andn %g1, %g2, %o2
"10010110001110000100000000000010", --14: 96 38 40 02 xnor %g1, %g2, %o3
"10011000001000000100000000000010", --18: 98 20 40 02 sub %g1, %g2, %o4
"00000001000000000000000000000000", --nop
"00000001000000000000000000000000", --nop
"00000001000000000000000000000000", --nop
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000" -- Fila con datos 56 a 63
);
begin
process(rst, addr)
begin
if (rst = '1') then
data <= "00000000000000000000000000000000";
else
data <= ROM(conv_integer(addr));
end if;
end process;
end behavioral;
--from random import randint
--n = 64
--for i in xrange(n):
-- x = randint(0, 1<<32)
--num = str(bin(x))[2:]
--num = (32 - len(num)) * '0' + num
--print "\"" + num + "\","
|
mit
|
9b5d76b3fcd1022109a659f8d61afdb2
| 0.77714 | 4.911142 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/xlib/iob_keeper_gen.vhd
| 2 | 2,074 |
-- $Id: iob_keeper_gen.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_keeper_gen - sim
-- Description: keeper for IOB, vector
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-06-03 299 1.1 add explicit R_KEEP and driver
-- 2008-05-22 148 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_keeper_gen is -- keeper for IOB, vector
generic (
DWIDTH : positive := 16); -- data port width
port (
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_keeper_gen;
-- Is't possible to directly use 'PAD<='H' in proc_pad. Introduced R_KEEP and
-- the explicit driver 'PAD<=R_KEEP' to state the keeper function more clearly.
architecture sim of iob_keeper_gen is
signal R_KEEP : slv(DWIDTH-1 downto 0) := (others=>'W');
begin
proc_keep: process (PAD)
begin
for i in PAD'range loop
if PAD(i) = '1' then
R_KEEP(i) <= 'H';
elsif PAD(i) = '0' then
R_KEEP(i) <= 'L';
elsif PAD(i)='X' or PAD(i)='U' then
R_KEEP(i) <= 'W';
end if;
end loop;
PAD <= R_KEEP;
end process proc_keep;
end sim;
|
gpl-2.0
|
f33ffee7a45dc3a711d082b233f3842e
| 0.592093 | 3.545299 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd
| 1 | 9,746 |
-- $Id: sys_tst_rlink_n2.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n2 - syn
-- Description: rlink tester design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n2
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8
-- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2
-- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8
-- 2010-12-29 351 12.1 M53d xc3s1200e-4 604 1298 68 851 t 14.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-18 440 1.1.6 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.1.5 use nx_cram_dummy now
-- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage
-- 2011-11-17 426 1.1.3 use dcm_sfs now
-- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.1.1 use now sn_humanio
-- 2011-06-26 385 1.1 move s3_humanio_rbus from tst_rlink to top level
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_n2;
architecture syn of sys_tst_rlink_n2 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
O_CLKSYS <= CLK;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
gpl-2.0
|
1a8275e3ea2dcdeb5204a68fe5dc5528
| 0.503386 | 3.13477 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/nexys2/sys_conf.vhd
| 1 | 3,626 |
-- $Id: sys_conf.vhd 428 2011-11-20 12:19:31Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 428 1.1.1 use clksys=56 (58 no closure after numeric_std...)
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-05 295 1.0 Initial version (derived from _s3 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
-- valid system clock / delay combinations:
-- div mul clksys read0 read1 write
-- 1 1 50.0 2 2 3
-- 25 27 54.0 3 3 3
-- 25 29 58.0 3 3 4
package sys_conf is
constant sys_conf_clkfx_divide : positive := 25;
constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 4;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
06e74151b9094015f83f80019a39ff28
| 0.605626 | 3.597222 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd
| 1 | 2,813 |
-- $Id: tbd_serport_uart_rx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_uart_rx - syn
-- Description: Wrapper for serport_uart_rx to avoid records. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: serport_uart_rx
--
-- To test: serport_uart_rx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 26 67 0 - t 8.17
-- 2007-10-27 92 9.1 J30 xc3s1000-4 26 67 0 - t 8.25
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 29 90 0 47 s 8.45
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 31 92 0 - s 8.25
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity tbd_serport_uart_rx is -- serial port uart rx [tb design]
-- generic: CDWIDTH=5
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv5; -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end tbd_serport_uart_rx;
architecture syn of tbd_serport_uart_rx is
begin
UART : serport_uart_rx
generic map (
CDWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
end syn;
|
gpl-2.0
|
ee0ed6018f60d9bd4309f322fa69dbc9
| 0.546392 | 3.720899 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd
| 1 | 3,729 |
-- $Id: nexys3_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1 use nxcramlib
-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys3_fusp_dummy;
architecture syn of nexys3_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
|
gpl-2.0
|
92cd18bdab83bab806fd86b2a731b13a
| 0.520515 | 3.411711 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/serport_xontx.vhd
| 1 | 4,805 |
-- $Id: serport_xontx.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx - syn
-- Description: serial port: xon/xoff logic tx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-10-22 417 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx;
architecture syn of serport_xontx is
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
end syn;
|
gpl-2.0
|
45e1a0e6d4ae53d57f520141cead44fc
| 0.48845 | 3.941756 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_2/round_f.vhd
| 1 | 6,751 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end round_f;
architecture Behavioral of round_f is
signal a_0_in_s : std_logic_vector(31 downto 0);
signal theta_0_s : std_logic_vector(31 downto 0);
signal theta_1_s : std_logic_vector(31 downto 0);
signal theta_2_s : std_logic_vector(31 downto 0);
signal theta_3_s : std_logic_vector(31 downto 0);
signal pi_1_1_s : std_logic_vector(31 downto 0);
signal pi_1_2_s : std_logic_vector(31 downto 0);
signal pi_1_3_s : std_logic_vector(31 downto 0);
signal gamma_0_s : std_logic_vector(31 downto 0);
signal gamma_1_s : std_logic_vector(31 downto 0);
signal gamma_2_s : std_logic_vector(31 downto 0);
signal gamma_3_s : std_logic_vector(31 downto 0);
signal pi_2_1_s : std_logic_vector(31 downto 0);
signal pi_2_2_s : std_logic_vector(31 downto 0);
signal pi_2_3_s : std_logic_vector(31 downto 0);
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component pi_1 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component gamma is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component pi_2 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component reg_128 is
port(clk : in std_logic;
rst : in std_logic;
data_in_0 : in std_logic_vector(31 downto 0);
data_in_1 : in std_logic_vector(31 downto 0);
data_in_2 : in std_logic_vector(31 downto 0);
data_in_3 : in std_logic_vector(31 downto 0);
data_out_0 : out std_logic_vector(31 downto 0);
data_out_1 : out std_logic_vector(31 downto 0);
data_out_2 : out std_logic_vector(31 downto 0);
data_out_3 : out std_logic_vector(31 downto 0));
end component;
signal a_0_aux_s : std_logic_vector(31 downto 0);
signal stage_0_out_0_s : std_logic_vector(31 downto 0);
signal stage_0_out_1_s : std_logic_vector(31 downto 0);
signal stage_0_out_2_s : std_logic_vector(31 downto 0);
signal stage_0_out_3_s : std_logic_vector(31 downto 0);
signal stage_1_out_0_s : std_logic_vector(31 downto 0);
signal stage_1_out_1_s : std_logic_vector(31 downto 0);
signal stage_1_out_2_s : std_logic_vector(31 downto 0);
signal stage_1_out_3_s : std_logic_vector(31 downto 0);
signal rc_delay_s : std_logic_vector(31 downto 0);
begin
rc_delay_s <= rc_in;
a_0_in_s <= (a_0_in xor rc_delay_s) when enc = '0' else a_0_in;
THETA_0 : theta port map (a_0_in_s,
a_1_in,
a_2_in,
a_3_in,
k_0_in,
k_1_in,
k_2_in,
k_3_in,
theta_0_s,
theta_1_s,
theta_2_s,
theta_3_s);
REG_STAGE_0: reg_128 port map (clk,
rst,
theta_0_s,
theta_1_s,
theta_2_s,
theta_3_s,
stage_0_out_0_s,
stage_0_out_1_s,
stage_0_out_2_s,
stage_0_out_3_s);
PI_1_0 : pi_1 port map (stage_0_out_1_s,
stage_0_out_2_s,
stage_0_out_3_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s);
a_0_aux_s <= (stage_0_out_0_s xor rc_delay_s) when enc = '1' else stage_0_out_0_s;
REG_STAGE_1: reg_128 port map (clk,
rst,
a_0_aux_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s,
stage_1_out_0_s,
stage_1_out_1_s,
stage_1_out_2_s,
stage_1_out_3_s);
GAMMA_0 : gamma port map (stage_1_out_0_s,
stage_1_out_1_s,
stage_1_out_2_s,
stage_1_out_3_s,
gamma_0_s,
gamma_1_s,
gamma_2_s,
gamma_3_s);
PI_2_0 : pi_2 port map (gamma_1_s,
gamma_2_s,
gamma_3_s,
pi_2_1_s,
pi_2_2_s,
pi_2_3_s);
a_0_out <= gamma_0_s;
a_1_out <= pi_2_1_s;
a_2_out <= pi_2_2_s;
a_3_out <= pi_2_3_s;
end Behavioral;
|
gpl-3.0
|
fa6ae2c3cd4f0dbd720fb9da1985adc8
| 0.590579 | 2.705812 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/simlib/simclk.vhd
| 1 | 2,775 |
-- $Id: simclk.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simclk - sim
-- Description: Clock generator for test benches
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-10 72 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_CYCLE : out slv31; -- clock cycle number
CLK_STOP : in slbit -- clock stop trigger
);
end entity simclk;
architecture sim of simclk is
begin
proc_clk: process
constant clock_halfperiod : time := PERIOD/2;
variable icycle : slv31 := (others=>'0');
begin
CLK <= '0';
CLK_CYCLE <= (others=>'0');
wait for OFFSET;
clk_loop: loop
CLK <= '1';
wait for 0 ns; -- make a delta cycle so that clock
icycle := slv(unsigned(icycle) + 1); -- cycle number is updated after the
CLK_CYCLE <= icycle; -- clock transition. all edge triggered
-- proc's will thus read old value.
wait for clock_halfperiod;
CLK <= '0';
wait for clock_halfperiod;
exit clk_loop when CLK_STOP = '1';
end loop;
CLK <= '1'; -- final clock cycle for clk_sim
wait for clock_halfperiod;
CLK <= '0';
wait for clock_halfperiod;
wait; -- endless wait, simulator will stop
end process proc_clk;
end sim;
|
gpl-2.0
|
39749f20b2166f0feac957cea48f8406
| 0.566126 | 4.03343 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw4/cw4.vhd
| 1 | 3,845 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CW4 IS
port(
SW: IN std_logic_vector(17 downto 0);
HEX0: OUT std_logic_vector(0 to 6);
HEX1: OUT std_logic_vector(0 to 6);
HEX2: OUT std_logic_vector(0 to 6);
HEX3: OUT std_logic_vector(0 to 6);
HEX4: OUT std_logic_vector(0 to 6);
HEX5: OUT std_logic_vector(0 to 6);
HEX6: OUT std_logic_vector(0 to 6);
HEX7: OUT std_logic_vector(0 to 6)
);
END CW4;
ARCHITECTURE strukturalna OF CW4 IS
CONSTANT space : std_logic_vector(2 downto 0) := "111";
COMPONENT mux3bit8to1
port(
S, U0, U1, U2, U3, U4, U5, U6, U7:
IN std_logic_vector(2 downto 0);
M0: OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
COMPONENT char7seg
port(
C : IN std_logic_vector(2 downto 0);
DISPLAY : OUT std_logic_vector(0 to 6)
);
END COMPONENT;
SIGNAL M0: std_logic_vector(2 downto 0);
SIGNAL M1: std_logic_vector(2 downto 0);
SIGNAL M2: std_logic_vector(2 downto 0);
SIGNAL M3: std_logic_vector(2 downto 0);
SIGNAL M4: std_logic_vector(2 downto 0);
SIGNAL M5: std_logic_vector(2 downto 0);
SIGNAL M6: std_logic_vector(2 downto 0);
SIGNAL M7: std_logic_vector(2 downto 0);
BEGIN
MUX0: mux3bit8to1 port map(
SW(17 downto 15), SW(14 downto 12), SW(11 downto 9), SW(8 downto 6), SW(5 downto 3), SW(2 downto 0), space, space, space, M0
);
MUX1: mux3bit8to1 port map(
SW(17 downto 15), SW(11 downto 9), SW(8 downto 6), SW(5 downto 3), SW(2 downto 0), space, space, space, SW(14 downto 12), M1
);
MUX2: mux3bit8to1 port map(
SW(17 downto 15), SW(8 downto 6), SW(5 downto 3), SW(2 downto 0), space, space, space, SW(14 downto 12), SW(11 downto 9), M2
);
MUX3: mux3bit8to1 port map(
SW(17 downto 15), SW(5 downto 3), SW(2 downto 0), space, space, space, SW(14 downto 12), SW(11 downto 9),SW(8 downto 6), M3
);
MUX4: mux3bit8to1 port map(
SW(17 downto 15),SW(2 downto 0), space, space, space, SW(14 downto 12), SW(11 downto 9), SW(8 downto 6), SW(5 downto 3), M4
);
MUX5: mux3bit8to1 port map(
SW(17 downto 15), space, space, space, SW(14 downto 12), SW(11 downto 9), SW(8 downto 6), SW(5 downto 3), SW(2 downto 0), M5
);
MUX6: mux3bit8to1 port map(
SW(17 downto 15), space, space, SW(14 downto 12), SW(11 downto 9), SW(8 downto 6), SW(5 downto 3), SW(2 downto 0),space, M6
);
MUX7: mux3bit8to1 port map(
SW(17 downto 15), space, SW(14 downto 12), SW(11 downto 9), SW(8 downto 6), SW(5 downto 3), SW(2 downto 0),space, space, M7
);
H0: char7seg port map(M0, HEX0);
H1: char7seg port map(M1, HEX1);
H2: char7seg port map(M2, HEX2);
H3: char7seg port map(M3, HEX3);
H4: char7seg port map(M4, HEX4);
H5: char7seg port map(M5, HEX5);
H6: char7seg port map(M6, HEX6);
H7: char7seg port map(M7, HEX7);
END strukturalna;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux3bit8to1 IS
port(
S, U0, U1, U2, U3, U4, U5, U6, U7:
IN std_logic_vector(2 downto 0);
M0: OUT std_logic_vector(2 downto 0) --było M
);
END mux3bit8to1;
ARCHITECTURE strukturalna OF mux3bit8to1 IS
signal output : std_logic_vector(2 downto 0);
begin
with s select
output <= U0 when "000",
U1 when "001",
U2 when "010",
U3 when "011",
U4 when "100",
U5 when "101",
U6 when "110",
U7 when "111",
"---" when others;
M0 <= output;
END strukturalna;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY char7seg IS
port(
C : IN std_logic_vector(2 downto 0);
DISPLAY : OUT std_logic_vector(0 to 6)
);
END char7seg;
ARCHITECTURE strukturalna of char7seg IS
signal output : std_logic_vector(0 to 6);
begin
with c select
output <= "1001111" when "000",
"1000011" when "001",
"1110001" when "010",
"0000001" when "011",
"0011000" when "100",
"1111111" when others;
display <= output;
END strukturalna;
|
mit
|
a97b1c566362cf04c5891c36fad30eb5
| 0.644901 | 2.549072 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
| 1 | 20,479 |
-- $Id: sys_w11a_n2.vhd 440 2011-12-18 20:08:09Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n2 - syn
-- Description: w11a test design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_bram
-- vlib/nxcramlib/nx_cram_dummy
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- bplib/nxcramlib/nx_cram_memctl_as
-- ibus/ib_sres_or_2
-- ibus/ibdr_minisys
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_sys_w11a_n2
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II
-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II
-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II
-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II
-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II
-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II
-- " 306 10.1.02 K39 xc3s1200e-4 1309 4311 242 2665 ok: LP+PC+DL+II
-- " 306 9.2.02 J40 xc3s1200e-4 1316 4259 242 2656 ok: LP+PC+DL+II
-- " 306 9.1 J30 xc3s1200e-4 1311 4260 242 2643 ok: LP+PC+DL+II
-- " 306 8.2.03 I34 xc3s1200e-4 1371 4394 242 2765 ok: LP+PC+DL+II
-- 2010-06-13 305 11.4 L68 xc3s1200e-4 1318 4360 242 2629 ok: LP+PC+DL+II
-- 2010-06-12 304 11.4 L68 xc3s1200e-4 1323 4201 242 2574 ok: LP+PC+DL+II
-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II
-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-18 440 1.2.7 use rlink_sp1c
-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage
-- 2011-11-19 427 1.2.4 now numeric_std clean
-- 2011-11-17 426 1.2.3 use dcm_sfs now
-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.2.1 use now sn_humanio
-- 2010-12-30 351 1.2 ported to rbv3
-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
-- BUGFIX: resolve rbus address clash hio<->ibr
-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn;
-- rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-13 305 1.1.2 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-12 304 1.1.1 re-do LED driver logic (show cpu modes or cpurust)
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03 300 1.0.2 use default FAWIDTH for rri_core_serport
-- use s3_humanio_rri
-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7
-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)
------------------------------------------------------------------------------
--
-- w11a test design for nexys2
-- w11a + rlink + serport
--
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0): if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_w11a_n2;
architecture syn of sys_w11a_n2 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CPU_RESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal CACHE_CHIT : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
signal DISPREG : slv16 := (others=>'0');
constant rbaddr_core0 : slv8 := "00000000";
constant rbaddr_ibus : slv8 := "10000000";
constant rbaddr_hio : slv8 := "11000000";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
O_CLKSYS <= CLK;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6, -- 64 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RB_SRES_OR : rb_sres_or_3
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_3 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
CORE : pdp11_core
port map (
CLK => CLK,
RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM_BRAM: if sys_conf_bram > 0 generate
signal HM_VAL_BRAM : slbit := '0';
begin
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => EM_MREQ.req,
HM_VAL => HM_VAL_BRAM,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end generate MEM_BRAM;
MEM_SRAM: if sys_conf_bram = 0 generate
CACHE: pdp11_cache
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
FMISS => CACHE_FMISS,
CHIT => CACHE_CHIT,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => HM_ENA,
HM_VAL => CACHE_CHIT,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
SRAM_CTL: nx_cram_memctl_as
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => CPU_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end generate MEM_SRAM;
IB_SRES_OR : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES_IBDR,
IB_SRES_OR => IB_SRES
);
IBD_MINI : if false generate
begin
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MINI;
IBD_MAXI : if true generate
begin
IBDR_SYS : ibdr_maxisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MAXI;
DSP_DAT(15 downto 0) <= DISPREG;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
LED <= iled;
end process;
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= CACHE_CHIT;
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
6e5245d0154ecc2e5ae2c715c90bff4f
| 0.504859 | 3.012061 | false | false | false | false |
rogerioag/gcg
|
tutorial/ula/testbench/nor2_tb.vhd
| 1 | 1,798 |
-- Testebench gerado via script.
-- Data: Sáb,31/12/2011-01:19:07
-- Autor: rogerio
-- Comentario: Teste da entidade nor2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nor2_tb is
end nor2_tb;
architecture logica of nor2_tb is
-- Declaração do componente.
component nor2
port (a, b: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for nor2_0: nor2 use entity work.nor2;
signal s_t_a, s_t_b, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
nor2_0: nor2 port map ( a=>s_t_a, b=>s_t_b, y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a, vi_b: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada que são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
-- Casos de teste.
constant patterns : pattern_array :=
(
('0', '0', '1'),
('0', '1', '0'),
('1', '0', '0'),
('1', '1', '0')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
|
gpl-3.0
|
0e8af97c6a886a22df74056423a200c8
| 0.62809 | 2.937294 | false | true | false | false |
xylnao/w11a-extra
|
rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd
| 1 | 6,264 |
-- $Id: bp_rs232_2l4l_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2l4l_iob - syn
-- Description: iob's for internal + external rs232, with select
--
-- Dependencies: bp_rs232_2line_iob
-- bp_rs232_4line_iob
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.2.2 fix mistake in tx and rts relay
-- 2011-08-07 404 1.2.1 add RELAY generic and a relay stage towards IOB's
-- 2011-08-06 403 1.2 add pipeline flops; add RESET signal
-- 2011-07-09 391 1.1 moved and renamed to bpgen
-- 2011-07-02 387 1.0.1 use bp_rs232_[24]line_iob now
-- 2010-04-17 278 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end bp_rs232_2l4l_iob;
architecture syn of bp_rs232_2l4l_iob is
signal RXD0 : slbit := '0';
signal RXD1 : slbit := '0';
signal CTS1_N : slbit := '0';
signal R_RXD : slbit := '1';
signal R_CTS_N : slbit := '0';
signal R_TXD0 : slbit := '1';
signal R_TXD1 : slbit := '1';
signal R_RTS1_N : slbit := '0';
signal RR_RXD0 : slbit := '1';
signal RR_TXD0 : slbit := '1';
signal RR_RXD1 : slbit := '1';
signal RR_TXD1 : slbit := '1';
signal RR_CTS1_N : slbit := '0';
signal RR_RTS1_N : slbit := '0';
begin
-- On Digilent Atlys bords the IOBs for P0 and P1 are on diagonally opposide
-- corners of the die, which causes very long (7-8ns) routing delays to a LUT
-- in the middle. The RELAY generic allows to add 'relay flops' between IOB
-- flops and the mux implented in proc_regs_mux.
--
-- The data flow is
-- iob-flop relay-flop if-flop port
-- RXD0 -> RR_RXD0 -> R_RXD -> RXD
-- TXD0 <- RR_TXD0 <- R_TXD0 <- TXD
-- RXD1 -> RR_RXD1 -> R_RXD -> RXD
-- TXD1 <- RR_TXD1 <- R_TXD1 <- TXD
-- CTS1_N -> RR_CTS1_N -> R_CTS_N -> CTS
-- RTS1_N <- RR_RTS1_N <- R_RTS1_N <- RTS
P0 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD0,
TXD => RR_TXD0,
I_RXD => I_RXD0,
O_TXD => O_TXD0
);
P1 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD1,
TXD => RR_TXD1,
CTS_N => CTS1_N,
RTS_N => RR_RTS1_N,
I_RXD => I_RXD1,
O_TXD => O_TXD1,
I_CTS_N => I_CTS1_N,
O_RTS_N => O_RTS1_N
);
DORELAY : if RELAY generate
proc_regs_pipe: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
RR_RXD0 <= '1';
RR_TXD0 <= '1';
RR_RXD1 <= '1';
RR_TXD1 <= '1';
RR_CTS1_N <= '0';
RR_RTS1_N <= '0';
else
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end if;
end if;
end process proc_regs_pipe;
end generate DORELAY;
NORELAY : if not RELAY generate
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end generate NORELAY;
proc_regs_mux: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_RXD <= '1';
R_CTS_N <= '0';
R_TXD0 <= '1';
R_TXD1 <= '1';
R_RTS1_N <= '0';
else
if SEL = '0' then -- use 2-line rs232, no flow cntl
R_RXD <= RR_RXD0; -- get port 0 inputs
R_CTS_N <= '0';
R_TXD0 <= TXD; -- set port 0 output
R_TXD1 <= '1'; -- port 1 outputs to idle state
R_RTS1_N <= '0';
else -- otherwise use 4-line rs232
R_RXD <= RR_RXD1; -- get port 1 inputs
R_CTS_N <= RR_CTS1_N;
R_TXD0 <= '1'; -- port 0 output to idle state
R_TXD1 <= TXD; -- set port 1 outputs
R_RTS1_N <= RTS_N;
end if;
end if;
end if;
end process proc_regs_mux;
RXD <= R_RXD;
CTS_N <= R_CTS_N;
end syn;
|
gpl-2.0
|
7e81145f5a527634f9e83b306187f491
| 0.489943 | 3.168437 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/fifo_adapter.vhd
| 1 | 2,448 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- F I F O A D A P T E R
-- Asynchronous entity to tristate external pins if disabled
-- and invert control signals to be high active
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity fifo_adapter is
port (
-- external fifo pins
data_pins : inout std_logic_vector(7 downto 0);
rxf_pin : in std_logic;
txd_pin : in std_logic;
wr_pin : out std_logic;
rd_pin : out std_logic;
-- internal fifo signals
enable_i : in std_logic; -- async enable
direction_i : in std_logic; -- data direction (0:receive, 1:send)
data_transmit_i : in std_logic_vector(7 downto 0);
data_receive_o : out std_logic_vector(7 downto 0);
rxf_o : out std_logic;
txd_o : out std_logic;
wr_i : in std_logic;
rd_i : in std_logic
);
end fifo_adapter;
architecture async of fifo_adapter is
begin
-- receive data (dir=0)
data_receive_o <= data_pins when (enable_i='1' and direction_i='0')
else (others => '0');
-- send data (dir=1)
data_pins <= data_transmit_i when (enable_i='1' and direction_i='1')
else (others => 'Z');
-- control pins: connect when enabled
rxf_o <= not rxf_pin when enable_i = '1' else '0';
txd_o <= not txd_pin when enable_i = '1' else '0';
wr_pin <= wr_i when enable_i = '1' else 'Z';
rd_pin <= not rd_i when enable_i = '1' else 'Z';
end async;
|
gpl-3.0
|
f0c68ccca5a7f3257e6951a8b4a1037a
| 0.581699 | 3.777778 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/avmb/tb/sys_conf_sim.vhd
| 1 | 1,513 |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_mb (for simulation)
--
-- Dependencies: -
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(40000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
gpl-2.0
|
5b850ffaca6715d8bb51800c5730b9e6
| 0.63384 | 4.034667 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd
| 1 | 4,605 |
-- $Id: tb_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n2 - sim
-- Description: Test bench for sys_tst_serloop2_n2
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop2_n2 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n2
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop2_n2 is
end tb_tst_serloop2_n2;
architecture sim of tb_tst_serloop2_n2 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
DCM_H : dcm_sfs
generic map (
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKH,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n2
port map (
I_CLK50 => CLK50,
O_CLKSYS => open,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FLA_CE_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-2.0
|
2935b25a7bb9ca220945df8ed9f48ea7
| 0.521607 | 3.124152 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/pdp11_mmu_ssr12.vhd
| 2 | 6,050 |
-- $Id: pdp11_mmu_ssr12.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu_ssr12 - syn
-- Description: pdp11: mmu register ssr1 and ssr2
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_mmu_ssr12;
architecture syn of pdp11_mmu_ssr12 is
constant ibaddr_ssr1 : slv16 := slv(to_unsigned(8#177574#,16));
constant ibaddr_ssr2 : slv16 := slv(to_unsigned(8#177576#,16));
subtype ssr1_ibf_rb_delta is integer range 15 downto 11;
subtype ssr1_ibf_rb_num is integer range 10 downto 8;
subtype ssr1_ibf_ra_delta is integer range 7 downto 3;
subtype ssr1_ibf_ra_num is integer range 2 downto 0;
signal IBSEL_SSR1 : slbit := '0';
signal IBSEL_SSR2 : slbit := '0';
signal R_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
signal R_SSR2 : slv16 := (others=>'0');
signal N_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
signal N_SSR2 : slv16 := (others=>'0');
begin
SEL_SSR1 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr1)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR1
);
SEL_SSR2 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr2)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR2
);
proc_ibres : process (IBSEL_SSR1, IBSEL_SSR2, IB_MREQ, R_SSR1, R_SSR2)
variable ssr1out : slv16 := (others=>'0');
variable ssr2out : slv16 := (others=>'0');
begin
ssr1out := (others=>'0');
if IBSEL_SSR1 = '1' then
ssr1out(ssr1_ibf_rb_delta) := R_SSR1.rb_delta;
ssr1out(ssr1_ibf_rb_num) := R_SSR1.rb_num;
ssr1out(ssr1_ibf_ra_delta) := R_SSR1.ra_delta;
ssr1out(ssr1_ibf_ra_num) := R_SSR1.ra_num;
end if;
ssr2out := (others=>'0');
if IBSEL_SSR2 = '1' then
ssr2out := R_SSR2;
end if;
IB_SRES.dout <= ssr1out or ssr2out;
IB_SRES.ack <= (IBSEL_SSR1 or IBSEL_SSR2) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_regs : process (CLK)
begin
if rising_edge(CLK) then
R_SSR1 <= N_SSR1;
R_SSR2 <= N_SSR2;
end if;
end process proc_regs;
proc_comb : process (CRESET, IBSEL_SSR1, IB_MREQ,
R_SSR1, R_SSR2, TRACE, MONI)
variable nssr1 : mmu_ssr1_type := mmu_ssr1_init;
variable nssr2 : slv16 := (others=>'0');
variable delta : slv5 := (others=>'0');
variable use_rb : slbit := '0';
begin
nssr1 := R_SSR1;
nssr2 := R_SSR2;
delta := "0" & MONI.delta;
use_rb := '0';
if MONI.regnum/=nssr1.ra_num and unsigned(nssr1.ra_delta)/=0 then
use_rb := '1';
end if;
if CRESET = '1' then
nssr1 := mmu_ssr1_init;
nssr2 := (others=>'0');
elsif IBSEL_SSR1='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
nssr1.rb_delta := IB_MREQ.din(ssr1_ibf_rb_delta);
nssr1.rb_num := IB_MREQ.din(ssr1_ibf_rb_num);
end if;
if IB_MREQ.be0 = '1' then
nssr1.ra_delta := IB_MREQ.din(ssr1_ibf_ra_delta);
nssr1.ra_num := IB_MREQ.din(ssr1_ibf_ra_num);
end if;
elsif TRACE = '1' then
if MONI.istart = '1' then
nssr1 := mmu_ssr1_init;
nssr2 := MONI.pc;
elsif MONI.regmod = '1' then
if use_rb = '0' then
nssr1.ra_num := MONI.regnum;
if MONI.isdec = '0' then
nssr1.ra_delta := slv(signed(nssr1.ra_delta) + signed(delta));
else
nssr1.ra_delta := slv(signed(nssr1.ra_delta) - signed(delta));
end if;
else
nssr1.rb_num := MONI.regnum;
if MONI.isdec = '0' then
nssr1.rb_delta := slv(signed(nssr1.rb_delta) + signed(delta));
else
nssr1.rb_delta := slv(signed(nssr1.rb_delta) - signed(delta));
end if;
end if;
end if;
end if;
N_SSR1 <= nssr1;
N_SSR2 <= nssr2;
end process proc_comb;
end syn;
|
gpl-2.0
|
2a0b962748378a6d7d26cc02b7e2e1ed
| 0.559008 | 3.126615 | false | false | false | false |
xylnao/w11a-extra
|
rtl/ibus/ibdr_pc11.vhd
| 1 | 12,707 |
-- $Id: ibdr_pc11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_pc11 - syn
-- Description: ibus dev(rem): PC11
--
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
-- causes interrupt, if enabled; validated with zpcae0
-- 2009-06-01 221 0.9 Initial version (untested)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end ibdr_pc11;
architecture syn of ibdr_pc11 is
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
constant rcsr_ibf_rerr : integer := 15;
constant rcsr_ibf_rbusy : integer := 11;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_renb : integer := 0;
constant pcsr_ibf_perr : integer := 15;
constant pcsr_ibf_prdy : integer := 7;
constant pcsr_ibf_pie : integer := 6;
constant pbuf_ibf_pval : integer := 8;
constant pbuf_ibf_rbusy : integer := 9;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rerr : slbit; -- rcsr: reader error
rbusy : slbit; -- rcsr: reader busy
rdone : slbit; -- rcsr: reader done
rie : slbit; -- rcsr: reader interrupt enable
rbuf : slv8; -- rbuf:
rintreq : slbit; -- ptr interrupt request
perr : slbit; -- pcsr: punch error
prdy : slbit; -- pcsr: punch ready
pie : slbit; -- pcsr: punch interrupt enable
pbuf : slv8; -- pbuf:
pintreq : slbit; -- ptp interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- rerr (init=1!)
'0','0','0', -- rbusy,rdone,rie
(others=>'0'), -- rbuf
'0', -- rintreq
'1', -- perr (init=1!)
'1', -- prdy (init=1!)
'0', -- pie
(others=>'0'), -- pbuf
'0' -- pintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- reader control status -----
idout(rcsr_ibf_rerr) := r.rerr;
idout(rcsr_ibf_rbusy) := r.rbusy;
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rie = '0' and -- IE 0->1 transition
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
(r.rerr='1' or r.rdone='1') then -- but err or done set
n.rintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupts
end if;
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
if r.rerr = '0' then -- if not in error state
n.rbusy := '1'; -- set busy
n.rdone := '0'; -- clear done
n.rbuf := (others=>'0'); -- clear buffer
n.rintreq := '0'; -- cancel interrupt
ilam := '1'; -- rri lam
else -- if in error state
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
else -- rri ---------------------
if ibw1 = '1' then
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
and r.rerr='0' then
n.rbusy := '0'; -- clear busy
n.rdone := '0'; -- clear done
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- reader data buffer --------
idout(r.rbuf'range) := r.rbuf;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if true then -- !! PC11 is unusual !!
n.rdone := '0'; -- any read or write will clear done
n.rbuf := (others=>'0'); -- and the reader buffer
n.rintreq := '0'; -- also interrupt is canceled
end if;
else -- rri ---------------------
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rbusy := '0';
n.rdone := '1';
if r.rie = '1' then
n.rintreq := '1';
end if;
end if;
end if;
when ibaddr_pcsr => -- PCSR -- punch control status ------
idout(pcsr_ibf_perr) := r.perr;
idout(pcsr_ibf_prdy) := r.prdy;
idout(pcsr_ibf_pie) := r.pie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.pie := IB_MREQ.din(pcsr_ibf_pie);
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
if r.pie='0' and -- IE 0->1 transition
(r.perr='1' or r.prdy='1') then -- but err or done set
n.pintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.pintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
if ibw1 = '1' then
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
and r.perr='0' then
n.prdy := '1'; -- set ready
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.perr = '0' then -- if not in error state
n.pbuf := IB_MREQ.din(n.pbuf'range);
n.prdy := '0'; -- clear ready
n.pintreq := '0'; -- cancel interrupts
ilam := '1'; -- rri lam
else -- if in error state
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri ---------------------
idout(r.pbuf'range) := r.pbuf;
idout(pbuf_ibf_pval) := not r.prdy;
idout(pbuf_ibf_rbusy) := r.rbusy;
if ibrd = '1' then
n.prdy := '1';
if r.pie = '1' then
n.pintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK_PTR = '1' then
n.rintreq := '0';
end if;
if EI_ACK_PTP = '1' then
n.pintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_PTR <= r.rintreq;
EI_REQ_PTP <= r.pintreq;
end process proc_next;
end syn;
|
gpl-2.0
|
b0f7c00ad556b2323f47e15f3223cb8f
| 0.42811 | 4.06234 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/CU.vhd
| 1 | 2,043 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CU is
Port ( op : in STD_LOGIC_VECTOR(1 DOWNTO 0);
op3 : in STD_LOGIC_VECTOR(5 DOWNTO 0);
aluop : out STD_LOGIC_VECTOR(5 DOWNTO 0));
end CU;
architecture Behavioral of CU is
begin
process(op, op3)
begin
if(op = "10") then --formato3
case op3 is
when "000000" => --Add
aluop <= "000000";
when "000100" => --Sub
aluop <= "000001";
when "000001" => -- And
aluop <= "000010";
when "000101" => --Andn
aluop <= "000011";
when "000010" => --or
aluop <= "000100";
when "000110" => --orn
aluop <= "000101";
when "000011" => --xor
aluop <= "000110";
when "000111" => --xnor
aluop <= "000111";
when "010100" => --SUBcc
aluop <= "001000";
when "001100" => --SUBx
aluop <= "001001";
when "011100" => --SUBxcc
aluop <= "001010";
when "010001" => --ANDcc
aluop <= "001011";
when "010101" => --ANDNcc
aluop <= "001100";
when "010010" => --ORcc
aluop <= "001101";
when "010110" => --ORNcc
aluop <= "001110";
when "010011" => --XORcc
aluop <= "001111";
when "010111" => --XNORcc
aluop <= "010000";
when "001000" => --ADDx
aluop <= "010001";
when "011000" => --ADDxcc
aluop <= "010010";
when "010000" => --ADDcc
aluop <= "010011";
when "100101" =>AluOp <= "100101";--SLL Shift Left Logical
when "100110" =>AluOp <= "100110";--SRL Shift Right Logical
when "111100" =>AluOp <= "111100";--Save
when "111101" =>AluOp <= "111101";--RESTORE
when others =>
aluop <= (others=>'1'); --error
end case;
else
aluop <= (others=>'1'); --No existe
end if;
end process;
end Behavioral;
|
mit
|
f7ecf9e4a68a457fbb2ebd65a5522802
| 0.468918 | 3.399334 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/tb/rlinktblib.vhd
| 1 | 8,525 |
-- $Id: rlinktblib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rlinktblib
-- Description: rlink test environment components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 3.0.1 add rbtba_aif;
-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*;
-- many rri->rlink renames; drop rbus parts;
-- 2010-11-13 338 2.5.2 add rritb_core_dcm
-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-05 301 2.1.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.1.1 rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
-- drop RP_IINT signal from interfaces
-- add sbcntl_sbf_(cp|rp)mon defs
-- 2010-04-24 282 2.1 add rritb_core
-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.5 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.1.4 add AP_LAM for rritb_rpmon(_sb)
-- 2007-11-24 98 1.1.3 add RP_IINT for rritb_rpmon(_sb)
-- 2007-09-01 78 1.1.2 add rricp_rp
-- 2007-08-25 75 1.1.1 add rritb_cpmon_sb, rritb_rpmon_sb
-- 2007-08-16 74 1.1 remove rritb_tt* component; some interface changes
-- 2007-08-03 71 1.0.2 use rrirp_acif; change generics for rritb_[cr]pmon
-- 2007-07-22 68 1.0.1 add rritb_cpmon rritb_rpmon monitors
-- 2007-07-15 66 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rlinklib.all;
package rlinktblib is
type rlink_tba_cntl_type is record -- rlink_tba control
cmd : slv3; -- command code
ena : slbit; -- command enable
addr : slv8; -- address
cnt : slv8; -- block size
eop : slbit; -- end packet after current command
end record rlink_tba_cntl_type;
constant rlink_tba_cntl_init : rlink_tba_cntl_type := (
(others=>'0'), -- cmd
'0', -- ena
(others=>'0'), -- addr
(others=>'0'), -- cnt
'0'); -- eop
type rlink_tba_stat_type is record -- rlink_tba status
busy : slbit; -- command busy
ack : slbit; -- command acknowledge
err : slbit; -- command error flag
stat : slv8; -- status flags
braddr : slv8; -- block read address (for wblk)
bre : slbit; -- block read enable (for wblk)
bwaddr : slv8; -- block write address (for rblk)
bwe : slbit; -- block write enable (for rblk)
attnpend : slbit; -- attn pending
attnint : slbit; -- attn interrupt
end record rlink_tba_stat_type;
constant rlink_tba_stat_init : rlink_tba_stat_type := (
'0','0','0', -- busy, ack, err
(others=>'0'), -- stat
(others=>'0'), -- braddr
'0', -- bre
(others=>'0'), -- bwaddr
'0', -- bwe
'0','0'); -- attnpend, attnint
component rlink_tba is -- rlink test bench adapter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CNTL : in rlink_tba_cntl_type; -- control port
DI : in slv16; -- input data
STAT : out rlink_tba_stat_type; -- status port
DO : out slv16; -- output data
RL_DI : out slv9; -- rlink: data in
RL_ENA : out slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv9; -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : out slbit -- rlink: data hold
);
end component;
component rbtba_aif is -- rbus tba, abstract interface
-- no generics, no records
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ_aval : in slbit; -- rbus: request - aval
RB_MREQ_re : in slbit; -- rbus: request - re
RB_MREQ_we : in slbit; -- rbus: request - we
RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : in slv8; -- rbus: request - addr
RB_MREQ_din : in slv16; -- rbus: request - din
RB_SRES_ack : out slbit; -- rbus: response - ack
RB_SRES_busy : out slbit; -- rbus: response - busy
RB_SRES_err : out slbit; -- rbus: response - err
RB_SRES_dout : out slv16; -- rbus: response - dout
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end component;
component tbcore_rlink is -- core of vhpi_cext based test bench
generic (
CLK_PERIOD : time := 20 ns; -- clock period
CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLK : out slbit; -- main clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end component;
component tbcore_rlink_dcm is -- dcm aware core of vhpi_cext based tb
generic (
CLKOSC_PERIOD : time := 20 ns; -- clock osc period
CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLKOSC : out slbit; -- clock osc
CLKSYS : in slbit; -- DCM derived system clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end component;
-- FIXME after this point !!
component rricp_rp is -- rri comm->reg port aif forwarder
-- implements rricp_aif, uses rrirp_aif
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit :='0'; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit := '0' -- rlink: data hold
);
end component;
end package rlinktblib;
|
gpl-2.0
|
a1a69b7aa1607481101a2ad6fa7a5199
| 0.488446 | 3.924954 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/vhdl/value_decoder.vhd
| 1 | 1,292 |
-- ----------------------------------------------------------------------------
-- Entity for value decoding (N->1)
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity VALUE_DECODER is
generic(
DATA_WIDTH : integer := 8;
VALUE : integer := 0
);
port(
-- input data interface
INPUT : in std_logic_vector(DATA_WIDTH - 1 downto 0);
-- output data interface
OUTPUT : out std_logic
);
end entity VALUE_DECODER;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of VALUE_DECODER is
begin
dec: process(INPUT)
begin
if (INPUT = conv_std_logic_vector(VALUE, DATA_WIDTH)) then
OUTPUT <= '1';
else
OUTPUT <= '0';
end if;
end process dec;
end architecture full;
|
gpl-2.0
|
3feff70e5aed547fd5f366d7a2ec371d
| 0.362229 | 5.716814 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
electrostatically_actuated_membrane/testbench.vhd
| 1 | 6,330 |
-- =============================================================================
-- Model: testbench for an electrostatically actuated silicon membrane
--
-- Author: Vladimir Kolchuzhin, Chemnitz
-- <[email protected]>
-- Date: 21.10.2015
--
-- =============================================================================
-- VHDL-AMS generated code from ANSYS ROM Tool for hAMSter:
--
-- initial_160.vhd
-- s_ams_160.vhd
-- ca12_ams_160.vhd
-- ememb_160.vhd
--
-- units: uMKSV
---------------
--
-- Geometrical parameters of membrane:
--------------------------------------
-- memb_a=4000.0 ! length
-- memb_b=4000.0 ! width
-- memb_h= 5.0 ! thickness
-- fafl_l= 300.0 ! fringing field distance in plane direction
-- fafl_h= 200.0 ! fringing field distance above membrane
-- el_gap= 30.0 ! electrode gap
--
--
-- Solver parameters:
---------------------
-- Euler solver: time= 5ms; step=5.0 us
--
--
-- Load options:
----------------
-- use_pass=0 => external modal forces, uN; fm1_ext=km_1*q1_ext, => q1_ext=1.0 (mechanical test)
-- use_pass=1 => calculation of voltage displacement functions up to pull-in: voltage sweep
-- use_pass=4 => harmonic analysis -> chirp for harmonic response; + DFT (postprocessing)
--------------------------------------------------------------------------------
-- use_pass=1:
-- membrane is driven by a voltage: electrical excitation - > mechanical response
-- electrostatic softening vs stress stiffening:
--
-- The computed pull-in voltage is 90.0 volts in LIN case w/o stress stiffening;
-- The computed pull-in voltage is 258.0 volts in NL case.
--
--------------------------------------------------------------------------------
-- ID: testbench.vhd
--
-- Rev. 1.00 22.10.2015
--
-- =============================================================================
library ieee;
use work.electromagnetic_system.all;
use work.all;
use ieee.math_real.all;
entity testbench is
end;
architecture behav of testbench is
terminal struc1_ext,struc2_ext: translational; --
terminal lagrange1_ext,lagrange2_ext:translational; --
terminal master1_ext,master2_ext:translational; --
terminal elec1_ext,elec2_ext: electrical; --
-- Modal displacement
quantity q1_ext across fm1_ext through struc1_ext; -- modal amplitude 1
quantity q2_ext across fm2_ext through struc2_ext; -- modal amplitude 2
-- Lagrangian multipler
quantity p1_ext across r1_ext through lagrange1_ext;
quantity p2_ext across r2_ext through lagrange2_ext;
-- Nodal displacement
quantity u1_ext across f1_ext through master1_ext;
quantity u2_ext across f2_ext through master2_ext;
-- Electrical ports
quantity v1_ext across i1_ext through elec1_ext; -- conductor 1
quantity v2_ext across i2_ext through elec2_ext; -- conductor 2
constant f_1:real:=421.761e+03;
constant T_1:real:=1.0/f_1;
constant t_end:real:=5.0e-03;
constant dt:real:=5.0e-06;
-- convert real -> time
constant digital_delay:time:=5.0 us; -- time step size for matrix update: digital_delay=dt!
constant Vmax_value:real:= 258.0; -- Vmax for voltage ramp:
-- 1) LIN: 90.0 V
-- 2) NL: 258.0 V
-- sweep/chirp parameters
constant f_begin:real:=0.1e+03;
constant f_end:real:= 40.0e+03;
constant Vdc_value:real:= 70.0; -- Vdc
constant Vac_value:real:= 2.0; -- Vac
constant use_pass:integer:=1; -- *** 0/1/4 ***
-- use_pass=0 => external modal forces, uN; fmi_ext=km_i*qi_ext, => qi_ext=1.0 (mechanical test)
-- use_pass=1 => calculation of voltage displacement functions up to pull-in: voltage sweep
-- use_pass=4 => harmonic analysis -> chirp for harmonic response; + DFT (postprocessing)
begin
-- Loads:
if DOMAIN = quiescent_domain use
v1_ext == 0.0;
v2_ext == 0.0;
fm1_ext == 0.0; -- external modal force 1
fm2_ext == 0.0; -- external modal force 2
else
if use_pass = 0 use -- step 0->1 at t=0.0
v1_ext == 0.0;
v2_ext == 0.0;
fm1_ext == 23.6778051194; -- external modal force 1
fm2_ext == 212.6896178680; -- external modal force 2
end use;
if use_pass = 1 use -- ramp/sweep
v1_ext == Vmax_value/t_end*now;
v2_ext == 0.0;
fm1_ext == 0.0; -- external modal force 1
fm2_ext == 0.0; -- external modal force 2
end use;
if use_pass = 4 use -- chirp
v1_ext == Vdc_value + Vac_value*sin(2.0*3.14*(f_begin + (f_end-f_begin)/t_end*now) * now);
v2_ext == 0.0;
fm1_ext == 0.0; -- external modal force 1
fm2_ext == 0.0; -- external modal force 2
end use;
end use;
----------------------------------
r1_ext==0.0; -- must be zero
r2_ext==0.0; -- must be zero
f1_ext==0.0; -- external nodal force on master node 1
f2_ext==0.0; -- external nodal force on master node 2
-------------------------------------------------------------------------------
--
-- Lagrangian ports
--
-- p1 p2
-- r_ext1=0 ->>- o o -<<- r_ext2=0
-- | |
-- modal ports o-------o---------o-------o nodal ports
-- | |
-- fm_ext1=0 ->>- q1 o---o o---o u1 -<<- f_ext1=0
-- | |
-- fm_ext2=0 ->>- q2 o---o component_1: ememb_160 o---o u2 -<<- f_ext2=0
-- | |
-- | |
-- | |
-- o-------o---------o-------o
-- | |
-- v1_ext o o v2_ext=0
-- input ground
--
-- electrical ports
--
-- ASCII-Schematic of the elsta-membrane-component
component_1: entity ememb_160(behav)
generic map (digital_delay)
port map (struc1_ext,struc2_ext,
lagrange1_ext,lagrange2_ext,
master1_ext,master2_ext,
elec1_ext,elec2_ext);
end;
-- =============================================================================
|
mit
|
84f4a88c7fd9b56dbd2141a9e0d4a02f
| 0.495893 | 3.497238 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/RF.vhd
| 1 | 1,337 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RF is
Port ( Rs1 : in STD_LOGIC_VECTOR (5 downto 0);
Rs2 : in STD_LOGIC_VECTOR (5 downto 0);
Rd : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Dwr : in STD_LOGIC;
DATATOREG : in STD_LOGIC_VECTOR (31 downto 0);
ORs1 : out STD_LOGIC_VECTOR (31 downto 0);
ORs2 : out STD_LOGIC_VECTOR (31 downto 0);
cRD : out STD_LOGIC_VECTOR (31 downto 0)
);
end RF;
architecture Behavioral of RF is
type ram_type is array (0 to 39) of std_logic_vector (31 downto 0);
signal registers : ram_type := (others => x"00000000");
begin
process(rs1, rs2, rd, dwr, rst, DATATOREG, registers)
begin
registers(0) <= x"00000000";
if (rst = '0') then
if (Dwr = '1' and Rd /= "00000") then
registers(conv_integer(Rd)) <= DATATOREG;
end if;
ORs1 <= registers(conv_integer(Rs1));
ORs2 <= registers(conv_integer(Rs2));
cRD <= registers(conv_integer(Rd));
else
ORs1 <= (others => '0');
ORs2 <= (others => '0');
cRD <= (others => '0');
--registers(16) <= x"00000011";
--registers(17) <= x"FFFFFFF7";
--registers(18) <= x"0000000E";
end if;
end process;
end Behavioral;
|
mit
|
573ff918294eb9851a74afa92b8b32b9
| 0.566193 | 3.317618 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/tb/tb_rlink.vhd
| 1 | 23,682 |
-- $Id: tb_rlink.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink - sim
-- Description: Test bench for rlink_core
--
-- Dependencies: simlib/simclk
-- genlib/clkdivce
-- rbus/tbd_tester
-- rbus/rb_mon
-- rlink/rlink_mon
-- tbd_rlink_gen [UUT]
--
-- To test: rlink_core (via tbd_rlink_direct)
-- rlink_base (via tbd_rlink_serport)
-- rlink_serport (via tbd_rlink_serport)
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.7 fix crc8_update_tbl usage; now numeric_std clean
-- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx)
-- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport)
-- 2010-12-23 347 3.0.4 use rb_mon, rlink_mon directly; rename CP_*->RL_*
-- 2010-12-22 346 3.0.3 add .rlmon and .rbmon commands
-- 2010-12-21 345 3.0.2 rename commands .[rt]x... to [rt]x...;
-- add .[rt]x(idle|attn) cmds; remove 'bbbbbbbb' cmd
-- 2010-12-12 344 3.0.1 add .attn again; add .txbad, .txoof; ren oob->oof
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- use rbd_tester instead of sim target;
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.2.2 new init encoding (WE=0/1 int/ext);use sv_ prefix
-- for shared variables
-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.2 add CE_USEC in tbd_rri_gen interface
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.2 CLK_CYCLE now 31 bits
-- 2008-01-20 112 1.1.1 rename clkgen->clkdivce
-- 2007-11-24 98 1.1 add RP_IINT support, add checkmiss_tx to test
-- for missing responses
-- 2007-10-26 92 1.0.2 add DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
-- command set:
-- .reset assert RESET for 1 clk
-- .rlmon ien enable rlink monitor
-- .rbmon ien enable rbus monitor
-- .wait n wait n clks
-- .iowt n wait n clks for rlink i/o; auto-extend
-- .attn dat(16) pulse attn lines with dat
-- txsop send <sop>
-- txeop send <eop>
-- txnak send <nak>
-- txidle send <idle>
-- txattn send <attn>
-- tx8 dat(8) send 8 bit value
-- tx16 dat(16) send 16 bit value
-- txcrc send crc
-- txbad send bad (inverted) crc
-- txc cmd(8) send cmd - crc
-- txca cmd(8) addr(8) send cmd - addr - crc
-- txcad cmd(8) addr(8) dat(16) send cmd - addr - dl dh - crc
-- txcac cmd(8) addr(8) cnt(8) send cmd - addr - cnt - crc
-- txoof dat(9) send out-of-frame symbol
-- rxsop reset rx list; expect sop
-- rxeop expect <eop>
-- rxnak expect <nak>
-- rxidle expect <idle>
-- rxattn expect <attn>
-- rx8 dat(8) expect 8 bit value
-- rx16 dat(16) expect 16 bit value
-- rxcrc expect crc
-- rxcs cmd(8) stat(8) expect cmd - stat - crc
-- rxcds cmd(8) dat(16) stat(8) expect cmd - dl dh - stat - crc
-- rxccd cmd(8) ccmd(8) dat(16) stat(8) expect cmd - ccmd - dl dh - stat - crc
-- rxoof dat(9) expect out-of-frame symbol
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.genlib.all;
use work.comlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_rlink is
end tb_rlink;
architecture sim of tb_rlink is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RESET : slbit := '0';
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RB_MREQ_aval : slbit := '0';
signal RB_MREQ_re : slbit := '0';
signal RB_MREQ_we : slbit := '0';
signal RB_MREQ_initt: slbit := '0';
signal RB_MREQ_addr : slv8 := (others=>'0');
signal RB_MREQ_din : slv16 := (others=>'0');
signal RB_SRES_ack : slbit := '0';
signal RB_SRES_busy : slbit := '0';
signal RB_SRES_err : slbit := '0';
signal RB_SRES_dout : slv16 := (others=>'0');
signal RB_LAM_TBENCH : slv16 := (others=>'0');
signal RB_LAM_TESTER : slv16 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal TXRXACT : slbit := '0';
signal RLMON_EN : slbit := '0';
signal RBMON_EN : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal CLK_STOP : slbit := '0';
constant slv9_zero : slv9 := (others=>'0');
constant slv16_zero : slv16 := (others=>'0');
type slv9_array_type is array (0 to 255) of slv9;
type slv16_array_type is array (0 to 255) of slv16;
shared variable sv_rxlist : slv9_array_type := (others=>slv9_zero);
shared variable sv_nrxlist : natural := 0;
shared variable sv_rxind : natural := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
component tbd_rlink_gen is -- rlink, generic tb design interface
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end component;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_STOP => CLK_STOP
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5
)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
RB_MREQ.aval <= RB_MREQ_aval;
RB_MREQ.re <= RB_MREQ_re;
RB_MREQ.we <= RB_MREQ_we;
RB_MREQ.init <= RB_MREQ_initt;
RB_MREQ.addr <= RB_MREQ_addr;
RB_MREQ.din <= RB_MREQ_din;
RB_SRES_ack <= RB_SRES.ack;
RB_SRES_busy <= RB_SRES.busy;
RB_SRES_err <= RB_SRES.err;
RB_SRES_dout <= RB_SRES.dout;
RBTEST : rbd_tester
generic map (
RB_ADDR => slv(to_unsigned(2#11110000#,8)))
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM_TESTER,
RB_STAT => RB_STAT
);
RB_LAM <= RB_LAM_TESTER or RB_LAM_TBENCH;
RLMON : rlink_mon
generic map (
DWIDTH => RL_DI'length)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => RLMON_EN,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
RBMON : rb_mon
generic map (
DBASE => 2)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => RBMON_EN,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
UUT : tbd_rlink_gen
port map (
CLK => CLK,
CE_INT => CE_MSEC,
CE_USEC => CE_USEC,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
TXRXACT => TXRXACT
);
proc_stim: process
file fstim : text open read_mode is "tb_rlink_stim";
variable iline : line;
variable oline : line;
variable ien : slbit := '0';
variable icmd : slv8 := (others=>'0');
variable iaddr : slv8 := (others=>'0');
variable icnt : slv8 := (others=>'0');
variable istat : slv3 := (others=>'0');
variable iattn : slv16 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ioof : slv9 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iowait : integer := 0;
variable txcrc,rxcrc : slv8 := (others=>'0');
variable txlist : slv9_array_type := (others=>slv9_zero);
variable ntxlist : natural := 0;
procedure do_tx8 (data : inout slv8) is
begin
txlist(ntxlist) := '0' & data;
ntxlist := ntxlist + 1;
txcrc := crc8_update_tbl(txcrc, data);
end procedure do_tx8;
procedure do_tx16 (data : inout slv16) is
begin
do_tx8(data( 7 downto 0));
do_tx8(data(15 downto 8));
end procedure do_tx16;
procedure do_rx8 (data : inout slv8) is
begin
sv_rxlist(sv_nrxlist) := '0' & data;
sv_nrxlist := sv_nrxlist + 1;
rxcrc := crc8_update_tbl(rxcrc, data);
end procedure do_rx8;
procedure do_rx16 (data : inout slv16) is
begin
do_rx8(data( 7 downto 0));
do_rx8(data(15 downto 8));
end procedure do_rx16;
procedure checkmiss_rx is
begin
if sv_rxind < sv_nrxlist then
for i in sv_rxind to sv_nrxlist-1 loop
writetimestamp(oline, SB_CLKCYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, sv_rxlist(i)(8));
write(oline, string'(" "));
write(oline, sv_rxlist(i)(7 downto 0));
writeline(output, oline);
end loop;
end if;
end procedure checkmiss_rx;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
RLMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
RBMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".iowt " => -- .iowt
read_ea(iline, iowait);
idelta := iowait;
while idelta > 0 loop -- until time has expired
if TXRXACT = '1' then -- if any io activity
idelta := iowait; -- restart timer
else
idelta := idelta - 1; -- otherwise count down time
end if;
wait for clock_period;
end loop;
when ".attn " => -- .attn
read_ea(iline, iattn);
RB_LAM_TBENCH <= iattn; -- pulse attn lines
wait for clock_period; -- for 1 clock
RB_LAM_TBENCH <= (others=>'0');
when "txsop " => -- txsop send sop
txlist(0) := c_rlink_dat_sop;
ntxlist := 1;
txcrc := (others=>'0');
when "txeop " => -- txeop send eop
txlist(0) := c_rlink_dat_eop;
ntxlist := 1;
txcrc := (others=>'0');
when "txnak " => -- txnak send nak
txlist(0) := c_rlink_dat_nak;
ntxlist := 1;
txcrc := (others=>'0');
when "txidle" => -- txidle send idle
txlist(0) := c_rlink_dat_idle;
ntxlist := 1;
when "txattn" => -- txattn send attn
txlist(0) := c_rlink_dat_attn;
ntxlist := 1;
when "tx8 " => -- tx8 send 8 bit value
read_ea(iline, iaddr);
ntxlist := 0;
do_tx8(iaddr);
when "tx16 " => -- tx16 send 16 bit value
read_ea(iline, idata);
ntxlist := 0;
do_tx16(idata);
when "txcrc " => -- txcrc send crc
txlist(0) := '0' & txcrc;
ntxlist := 1;
when "txbad " => -- txbad send bad crc
txlist(0) := '0' & (not txcrc);
ntxlist := 1;
when "txc " => -- txc send: cmd crc
read_ea(iline, icmd);
ntxlist := 0;
do_tx8(icmd);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txca " => -- txc send: cmd addr crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txcad " => -- txc send: cmd addr data crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
read_ea(iline, idata);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
do_tx16(idata);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txcac " => -- txc send: cmd addr cnt crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
read_ea(iline, icnt);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
do_tx8(icnt);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txoof " => -- txoof send out-of-frame symbol
read_ea(iline, txlist(0));
ntxlist := 1;
when "rxsop " => -- rxsop expect sop
checkmiss_rx;
sv_rxlist(0) := c_rlink_dat_sop;
sv_nrxlist := 1;
sv_rxind := 0;
rxcrc := (others=>'0');
when "rxeop " => -- rxeop expect eop
sv_rxlist(sv_nrxlist) := c_rlink_dat_eop;
sv_nrxlist := sv_nrxlist + 1;
when "rxnak " => -- rxnak expect nak
sv_rxlist(sv_nrxlist) := c_rlink_dat_nak;
sv_nrxlist := sv_nrxlist + 1;
when "rxidle" => -- rxidle expect idle
sv_rxlist(sv_nrxlist) := c_rlink_dat_idle;
sv_nrxlist := sv_nrxlist + 1;
when "rxattn" => -- rxattn expect attn
sv_rxlist(sv_nrxlist) := c_rlink_dat_attn;
sv_nrxlist := sv_nrxlist + 1;
when "rx8 " => -- rx8 expect 8 bit value
read_ea(iline, iaddr);
do_rx8(iaddr);
when "rx16 " => -- rx16 expect 16 bit value
read_ea(iline, idata);
do_rx16(idata);
when "rxcrc " => -- rxcrc expect crc
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist+1;
when "rxcs " => -- rxcs expect: cmd stat crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxcds " => -- rxcsd expect: cmd data stat crc
read_ea(iline, icmd);
read_ea(iline, idata);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx16(idata);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxccd " => -- rxccd expect: cmd ccmd dat stat crc
read_ea(iline, icmd);
read_ea(iline, icnt);
read_ea(iline, idata);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx8(icnt);
do_rx16(idata);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxoof " => -- rxoof expect: out-of-frame symbol
read_ea(iline, ioof);
sv_rxlist(sv_nrxlist) := ioof;
sv_nrxlist := sv_nrxlist + 1;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
next file_loop when ntxlist=0;
for i in 0 to ntxlist-1 loop
RL_DI <= txlist(i);
RL_ENA <= '1';
writetimestamp(oline, SB_CLKCYCLE, ": stim");
write(oline, txlist(i)(8), right, 3);
write(oline, txlist(i)(7 downto 0), right, 9);
if txlist(i)(8) = '1' then
case txlist(i) is
when c_rlink_dat_idle =>
write(oline, string'(" (idle)"));
when c_rlink_dat_sop =>
write(oline, string'(" (sop) "));
when c_rlink_dat_eop =>
write(oline, string'(" (eop) "));
when c_rlink_dat_nak =>
write(oline, string'(" (nak) "));
when c_rlink_dat_attn =>
write(oline, string'(" (attn)"));
when others =>
write(oline, string'(" (????)"));
end case;
end if;
writeline(output, oline);
wait for clock_period;
while RL_BUSY = '1' loop
wait for clock_period;
end loop;
RL_ENA <= '0';
end loop; -- i
ntxlist := 0;
end loop; -- file fstim
wait for 50*clock_period;
checkmiss_rx;
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
if RL_VAL = '1' then
writetimestamp(oline, SB_CLKCYCLE, ": moni");
write(oline, RL_DO(8), right, 3);
write(oline, RL_DO(7 downto 0), right, 9);
if RL_DO(8) = '1' then
case RL_DO is
when c_rlink_dat_idle =>
write(oline, string'(" (idle)"));
when c_rlink_dat_sop =>
write(oline, string'(" (sop) "));
when c_rlink_dat_eop =>
write(oline, string'(" (eop) "));
when c_rlink_dat_nak =>
write(oline, string'(" (nak) "));
when c_rlink_dat_attn =>
write(oline, string'(" (attn)"));
when others =>
write(oline, string'(" (????)"));
end case;
end if;
if sv_nrxlist > 0 then
write(oline, string'(" CHECK"));
if sv_rxind < sv_nrxlist then
if RL_DO = sv_rxlist(sv_rxind) then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, sv_rxlist(sv_rxind)(8), right, 2);
write(oline, sv_rxlist(sv_rxind)(7 downto 0), right, 9);
end if;
sv_rxind := sv_rxind + 1;
else
write(oline, string'(" FAIL, UNEXPECTED"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
87e63b3cf5d90cd03c75de9c221ded5e
| 0.476902 | 3.714241 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/algorithms/sourdis_bispo_nfa/vhdl/sourdis_bispo_nfa.vhd
| 1 | 2,986 |
-- ----------------------------------------------------------------------------
-- Entity for implementation of Sourdis_Bispo NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity SOURDIS_BISPO_NFA is
generic(
DATA_WIDTH : integer := %$%;
RULES : integer := %$%
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
DATA : in std_logic_vector(DATA_WIDTH - 1 downto 0);
SOF : in std_logic;
EOF : in std_logic;
SRC_RDY : in std_logic;
DST_RDY : out std_logic;
-- output data interface
BITMAP : out std_logic_vector(RULES - 1 downto 0);
VLD : out std_logic;
ACK : in std_logic
);
end entity SOURDIS_BISPO_NFA;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of SOURDIS_BISPO_NFA is
signal local_reset : std_logic;
signal local_reset_fsm : std_logic;
signal we : std_logic;
-- signal rdy : std_logic;
-- signal vld_internal : std_logic;
-- signal set : std_logic;
%$%
begin
local_reset <= RESET or local_reset_fsm;
ctrl_fsm: entity work.CONTROL_FSM
port map(
CLK => CLK,
RESET => RESET,
-- input interface
EOF => EOF,
SRC_RDY => SRC_RDY,
DST_RDY => DST_RDY,
-- output interface
WE => we,
LOCAL_RESET => local_reset_fsm,
-- inner interface
VLD => VLD,
ACK => ACK
);
-- local_reset <= RESET or ACK;
-- we <= SRC_RDY and rdy;
-- DST_RDY <= rdy;
-- VLD <= vld_internal;
-- set <= SRC_RDY and EOF and rdy;
-- rdy <= not vld_internal;
--
-- end_reg: process(CLK)
-- begin
-- if (CLK'event and CLK = '1') then
-- if (local_reset = '1') then
-- vld_internal <= '0';
-- else
-- if set = '1' then
-- vld_internal <= '1';
-- end if;
-- end if;
-- end if;
-- end process end_reg;
%$%
final_bitmap_u: entity work.FINAL_BITMAP
generic map(
DATA_WIDTH => RULES
)
port map(
CLK => CLK,
RESET => local_reset,
-- input data interface
SET => bitmap_in,
-- output data interface
BITMAP => BITMAP
);
end architecture full;
|
gpl-2.0
|
daa0f31ee14fc85094939ff2856c7b3b
| 0.405224 | 4.284075 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/algorithms/sourdis_bispo_nfa/vhdl/state_pcre_at_most.vhd
| 1 | 2,499 |
-- ----------------------------------------------------------------------------
-- Entity for implementation of exactly N
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity STATE_PCRE_AT_MOST is
generic(
M : integer;
N : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
INPUT : in std_logic;
SYMBOL : in std_logic;
WE : in std_logic;
-- output data interface
OUTPUT : out std_logic
);
end entity STATE_PCRE_AT_MOST;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of STATE_PCRE_AT_MOST is
signal local_reset : std_logic;
signal value : std_logic_vector(11 downto 0);
signal at_most_in : std_logic;
begin
local_reset <= RESET or not SYMBOL;
gen_exact_part_y: if (M > 0) generate
exact_u: entity work.STATE_PCRE_EXACT
generic map(
M => M
)
port map(
CLK => CLK,
RESET => RESET,
-- input data interface
INPUT => INPUT,
SYMBOL => SYMBOL,
WE => WE,
-- output data interface
OUTPUT => at_most_in
);
end generate;
gen_exact_part_n: if (M = 0) generate
at_most_in <= INPUT;
end generate;
cnt_symbols: process(RESET, CLK)
begin
if (CLK'event and CLK = '1') then
if (local_reset = '1') then
value <= (others => '0');
else
if (we = '1') then
if ((value > 0) or (at_most_in = '1')) then
value <= value + 1;
end if;
end if;
end if;
end if;
end process;
OUTPUT <= '1' when (value > 0 and value <= (N-M)) else '0';
end architecture full;
|
gpl-2.0
|
b13bac2f0d5db2421c81c35a5ddbdda2
| 0.371349 | 4.909627 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/serport_xonrx.vhd
| 1 | 4,229 |
-- $Id: serport_xonrx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xonrx - syn
-- Description: serial port: xon/xoff logic rx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end serport_xonrx;
architecture syn of serport_xonrx is
type regs_type is record
txok : slbit; -- tx channel ok state
escseen : slbit; -- escape seen
rxdata : slv8; -- user rxdata
rxval : slbit; -- user rxval
rxovr : slbit; -- user rxovr
end record regs_type;
constant regs_init : regs_type := (
'1', -- txok (startup default is ok !!)
'0', -- escseen
(others=>'0'), -- rxdata
'0','0' -- rxval,rxovr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if ENAXON = '0' then
n.txok := '1';
end if;
if ENAESC = '0' then
n.escseen := '0';
end if;
n.rxovr := '0'; -- ensure single clock pulse
if UART_RXVAL = '1' then
if ENAXON='1' and UART_RXDATA=c_serport_xon then
n.txok := '1';
elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
n.txok := '0';
elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
n.escseen := '1';
else
if r.escseen = '1' then
n.escseen := '0';
end if;
if r.rxval = '0' then
n.rxval := '1';
if r.escseen = '1' then
n.rxdata := not UART_RXDATA;
else
n.rxdata := UART_RXDATA;
end if;
else
n.rxovr := '1';
end if;
end if;
end if;
if r.rxval='1' and RXHOLD='0' then
n.rxval := '0';
end if;
N_REGS <= n;
RXDATA <= r.rxdata;
RXVAL <= r.rxval;
RXOVR <= r.rxovr;
TXOK <= r.txok;
end process proc_next;
end syn;
|
gpl-2.0
|
967ca7a797e077028da9968d9672b416
| 0.508867 | 3.985862 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/s3board/tb/tb_s3board_core.vhd
| 1 | 3,256 |
-- $Id: tb_s3board_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board_core - sim
-- Description: Test bench for s3board - core device handling
--
-- Dependencies: vlib/parts/issi/is61lv25616al
--
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_s3board_core is
port (
I_SWI : out slv8; -- s3 switches
I_BTN : out slv4; -- s3 buttons
O_MEM_CE_N : in slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : in slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- sram: write enable (act.low)
O_MEM_OE_N : in slbit; -- sram: output enable (act.low)
O_MEM_ADDR : in slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end tb_s3board_core;
architecture sim of tb_s3board_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(1),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(3),
LB_N => O_MEM_BE_N(2),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(31 downto 16)
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
gpl-2.0
|
3af95b625337d556eb0e4508ddc5b432
| 0.569103 | 3.074599 | false | false | false | false |
hdlguy/vivado_tcl
|
source/chirp_gen.vhd
| 1 | 1,567 |
-- This block makes double accumulator linear FM chirp generator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity chirp_gen is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
cos : out std_logic_vector(7 downto 0);
sin : out std_logic_vector(7 downto 0));
end chirp_gen;
architecture rtl of chirp_gen is
constant chirp_rate : unsigned(31 downto 0) := B"00000000_00010000_00000000_00000000";
signal phase, freq : unsigned(31 downto 0);
signal s_axis_phase_tdata : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal m_axis_data_tdata : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
-- The double accumulator phase generator.
regs_proc:process
begin
wait until rising_edge(clk);
if reset = '1' then
freq <= (others=>'0');
phase <= (others=>'0');
else
freq <= freq + chirp_rate;
phase <= phase + freq;
end if;
end process;
-- Pack the 12 phase bits into the silly axis bus.
s_axis_phase_tdata(11 downto 0) <= std_logic_vector(phase(phase'left downto phase'left-11));
-- The sine rom IP core.
sine_rom_inst : entity work.sine_rom
PORT MAP (
aclk => clk,
s_axis_phase_tvalid => '1',
s_axis_phase_tdata => s_axis_phase_tdata,
m_axis_data_tvalid => open,
m_axis_data_tdata => m_axis_data_tdata);
-- Rip the sine and cosine out of the silly axis bus.
sin <= m_axis_data_tdata(15 downto 8);
cos <= m_axis_data_tdata( 7 downto 0);
end rtl;
|
gpl-3.0
|
de21af9a5ad729ee727b936e068c9e94
| 0.608807 | 3.474501 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL source files/Input_filter_4channel.vhd
| 1 | 3,125 |
------------------------------------------------------------------------
-- Author: Aleksandr Gudilko
-- Email: [email protected]
--
-- File:Input_filter_4channel.vhd
--
-- Description:
--
-- General-purpose input filter for FPGA signals (Majority filter)
-- Eliminates line "ringing" and create stable output for high speed logic.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity input_filter_4ch is
port(
reset :in std_logic; -- unfiltered input signal
INPUT_CLK :in std_logic; -- input clock signal
INPUT_SIGNAL_1 :in std_logic; -- unfiltered input signal
INPUT_SIGNAL_2 :in std_logic; -- unfiltered input signal
INPUT_SIGNAL_3 :in std_logic; -- unfiltered input signal
INPUT_SIGNAL_4 :in std_logic; -- unfiltered input signal
FILTERED_SIGNAL_1 :out std_logic; -- output filtered signal
FILTERED_SIGNAL_2 :out std_logic; -- output filtered signal
FILTERED_SIGNAL_3 :out std_logic; -- output filtered signal
FILTERED_SIGNAL_4 :out std_logic -- output filtered signal
);
end input_filter_4ch;
architecture arch of input_filter_4ch is
signal in1 :std_logic_vector (2 downto 0);
signal in2 :std_logic_vector (2 downto 0);
signal in3 :std_logic_vector (2 downto 0);
signal in4 :std_logic_vector (2 downto 0);
begin
FILTERED_SIGNAL_1 <= (in1(0) and in1(1)) or (in1(1) and in1(2)) or (in1(2) and in1(0));
FILTERED_SIGNAL_2 <= (in2(0) and in2(1)) or (in2(1) and in2(2)) or (in2(2) and in2(0));
FILTERED_SIGNAL_3 <= (in3(0) and in3(1)) or (in3(1) and in3(2)) or (in3(2) and in3(0));
FILTERED_SIGNAL_4 <= (in4(0) and in4(1)) or (in4(1) and in4(2)) or (in4(2) and in4(0));
proc1:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in1 <= "000";
elsif rising_edge(input_clk) then
in1(2) <= in1(1);
in1(1) <= in1(0);
in1(0) <= input_signal_1;
end if;
end process proc1;
proc2:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in2 <= "000";
elsif rising_edge(input_clk) then
in2(2) <= in2(1);
in2(1) <= in2(0);
in2(0) <= input_signal_2;
end if;
end process proc2;
proc3:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in3 <= "000";
elsif rising_edge(input_clk) then
in3(2) <= in3(1);
in3(1) <= in3(0);
in3(0) <= input_signal_3;
end if;
end process proc3;
proc4:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in4 <= "000";
elsif rising_edge(input_clk) then
in4(2) <= in4(1);
in4(1) <= in4(0);
in4(0) <= input_signal_4;
end if;
end process proc4;
end arch;
|
gpl-2.0
|
149b20594ad2673548b8494f7a81c854
| 0.52224 | 3.310381 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/wishbone_slave/wbs_dual_out.vhd
| 1 | 4,931 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- W I S H B O N E S L A V E (wbs_dual_out.vhd)
-- with two output registers
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
--===========================================================================--
-- Type and component definition package
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
package wbs_defs is
type wbs_reg_type is record
reg1 : std_logic_vector(WB_DW-1 downto 0);
reg2 : std_logic_vector(WB_DW-1 downto 0);
end record;
component wbs_dual_out
port (
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- register outputs
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0)
);
end component;
end package;
--===========================================================================--
-- Entity
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.wbs_defs.all;
-------------------------------------------------------------------------------
entity wbs_dual_out is
-------------------------------------------------------------------------------
port (
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- register outputs
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0)
);
end wbs_dual_out;
-------------------------------------------------------------------------------
architecture behavioral of wbs_dual_out is
-------------------------------------------------------------------------------
----------------------------------------------
-- register addresses
----------------------------------------------
constant REG1_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"00";
constant REG2_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"01";
----------------------------------------------
-- signals
----------------------------------------------
signal reg_out_s, reg_in_s : wbs_reg_type;
signal reg1_adr_match_s, reg2_adr_match_s : std_logic;
signal reg1_ce_s, reg2_ce_s : std_logic;
begin
-------------------------------------------------------------------------------
-- Concurrent
-------------------------------------------------------------------------------
-- register address decoder/comparator
reg1_adr_match_s <= '1' when wbs_in.adr = REG1_ADR else '0';
reg2_adr_match_s <= '1' when wbs_in.adr = REG2_ADR else '0';
-- register CE
reg1_ce_s <= wbs_in.stb AND wbs_in.we AND reg1_adr_match_s;
reg2_ce_s <= wbs_in.stb AND wbs_in.we AND reg2_adr_match_s;
-- acknowledge output
wbs_out.ack <= wbs_in.stb;
-- register inputs always get data from wbs_in
reg_in_s.reg1 <= wbs_in.dat;
reg_in_s.reg2 <= wbs_in.dat;
-- register output -> wbs_out via demultiplexer
with wbs_in.adr select
wbs_out.dat <= reg_out_s.reg1 when REG1_ADR,
reg_out_s.reg2 when REG2_ADR,
(others => '-') when others;
-- register outputs -> non-wishbone outputs
reg1_out <= reg_out_s.reg1;
reg2_out <= reg_out_s.reg2;
-------------------------------------------------------------------------------
REGISTERS : process(wbs_in.clk)
-------------------------------------------------------------------------------
begin
-- everything sync to clk
if (rising_edge(wbs_in.clk)) then
-- store reg1
if (reg1_ce_s = '1') then
reg_out_s.reg1 <= reg_in_s.reg1;
-- store reg2
elsif (reg2_ce_s = '1') then
reg_out_s.reg2 <= reg_in_s.reg2;
-- hold
else
reg_out_s <= reg_out_s;
end if;
end if;
end process REGISTERS;
end behavioral;
|
gpl-3.0
|
6cecd9aad8875418f6bb92c1e9a65a25
| 0.46522 | 4.116027 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/transmit_frame_buffer.vhd
| 1 | 9,398 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- T R A N S M I T F R A M E B U F F E R (transmit_frame_buffer.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
-------------------------------------------------------------------------------
-- Type and component definition package
-------------------------------------------------------------------------------
package transmit_frame_buffer_comp is
type transmit_frame_buffer_in_type is record
frame : std_logic_vector((FIFO_WIDTH*PROTO_WC_TX_MAX)-1 downto 0);
frame_valid : std_logic;
fifo_busy : std_logic; -- fifo_ctrl direction output
fifo_wr : std_logic;
transmit_mode : std_logic;
length : integer range 0 to PROTO_WC_TX_MAX; -- if 0, the buffer determines the
-- length using the opcode.
-- For ardre frames the length is
-- > 0 indicating how many bytes
-- should be transmitted.
end record;
type transmit_frame_buffer_out_type is record
word : std_logic_vector(FIFO_WIDTH-1 downto 0);
send : std_logic;
trabuf_busy : std_logic;
end record;
component transmit_frame_buffer
port (
clk : in std_logic;
rst : in std_logic;
d : in transmit_frame_buffer_in_type;
q : out transmit_frame_buffer_out_type
);
end component;
end package;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.transmit_frame_buffer_comp.all;
use work.constants.all;
-------------------------------------------------------------------------------
entity transmit_frame_buffer is
-------------------------------------------------------------------------------
port (
clk : in std_logic;
rst : in std_logic;
d : in transmit_frame_buffer_in_type;
q : out transmit_frame_buffer_out_type
);
end transmit_frame_buffer;
-------------------------------------------------------------------------------
architecture two_proc of transmit_frame_buffer is
-------------------------------------------------------------------------------
type frame_type is array (0 to PROTO_WC_TX_MAX-1)
of std_logic_vector(FIFO_WIDTH-1 downto 0);
type state_type is (
idle,
buffer_frame,
set_length,
apply_word,
wait_for_wr_high,
wait_for_wr_low,
wait_for_fifo,
check_index
);
type reg_type is record
frame : frame_type;
state : state_type;
byte_count : integer range 0 to PROTO_WC_TX_MAX;
byte_index : integer range 0 to PROTO_WC_TX_MAX;
end record;
signal reg_out, reg_in : reg_type;
begin
-------------------------------------------------------------------------------
COMBINATIONAL : process(d, reg_out)
-------------------------------------------------------------------------------
variable tmp : reg_type;
begin
-- read register to tmp variable
tmp := reg_out;
case tmp.state is
--IDLE-------------------------------------------------------------------
when idle =>
-- outputs
q.word <= (others => '-');
q.trabuf_busy <= '0';
q.send <= '0';
-- reset register variables
tmp.byte_index := 0;
tmp.byte_count := 0;
-- next state
if (d.frame_valid = '1') then
tmp.state := buffer_frame;
else
tmp.state := idle;
end if;
--BUFFER_FRAME-----------------------------------------------------------
when buffer_frame =>
-- outputs
q.word <= (others => '-');
q.trabuf_busy <= '1';
q.send <= '0';
-- buffer frame
for index in 0 to PROTO_WC_TX_MAX-1 loop
tmp.frame(index) :=
d.frame((index*FIFO_WIDTH)+(FIFO_WIDTH-1) downto index*FIFO_WIDTH);
end loop;
-- next state
tmp.state := set_length;
--SET_LENGTH-------------------------------------------------------------
when set_length =>
-- outputs
q.word <= (others => '-');
q.trabuf_busy <= '1';
q.send <= '0';
if (d.length = 0) then
-- set byte_count by means of the opcode
case tmp.frame(0) is
when ACK_OPC => tmp.byte_count := ACK_LEN;
when NACK_OPC => tmp.byte_count := NACK_LEN;
when DETECT_REPLY_OPC => tmp.byte_count := DETECT_REPLY_LEN;
when REGISTER_RDRE_OPC => tmp.byte_count := REGISTER_RDRE_LEN;
when SOC_INT_OPC => tmp.byte_count := SOC_INT_LEN;
when others => tmp.byte_count := 0;
end case;
-- if the length is given by frame_ctrl
else
tmp.byte_count := d.length;
end if;
-- next state
if (d.transmit_mode = '1') then
tmp.state := apply_word;
else
tmp.state := set_length;
end if;
--APPLY_WORD-------------------------------------------------------------
when apply_word =>
-- outputs
q.word <= tmp.frame(tmp.byte_index);
q.trabuf_busy <= '1';
q.send <= '1';
-- next state: wait until fifo is busy
if (d.fifo_busy = '1') then
tmp.state := wait_for_wr_high;
else
tmp.state := apply_word;
end if;
--WAIT_FOR_WR_HIGH-------------------------------------------------------
when wait_for_wr_high =>
-- outputs
q.word <= tmp.frame(tmp.byte_index);
q.trabuf_busy <= '1';
q.send <= '1';
-- next state: wait until wr has been asserted ...
if (d.fifo_wr = '1') then
tmp.state := wait_for_wr_low;
else
tmp.state := wait_for_wr_high;
end if;
--WAIT_FOR_WR_LOW--------------------------------------------------------
when wait_for_wr_low =>
-- outputs
q.word <= tmp.frame(tmp.byte_index);
q.trabuf_busy <= '1';
q.send <= '1';
-- next state: wait until wr is zero again
if (d.fifo_wr = '0') then
tmp.state := wait_for_fifo;
else
tmp.state := wait_for_wr_low;
end if;
--WAIT_FOR_FIFO----------------------------------------------------------
when wait_for_fifo =>
-- outputs (the same as in apply_word)
q.word <= tmp.frame(tmp.byte_index);
q.trabuf_busy <= '1';
q.send <= '0';
-- next state: wait until fifo is done
if (d.fifo_busy = '1') then
tmp.state := wait_for_fifo;
else
-- increment index when leaving state
tmp.byte_index := tmp.byte_index + 1;
tmp.state := check_index;
end if;
--CHECK_INDEX------------------------------------------------------------
when check_index =>
-- outputs
q.word <= (others => '-');
q.trabuf_busy <= '1';
q.send <= '0';
-- next state
if (tmp.byte_index = tmp.byte_count) then
tmp.state := idle;
else
tmp.state := apply_word;
end if;
end case;
-- write back to register
reg_in <= tmp;
end process COMBINATIONAL;
-------------------------------------------------------------------------------
REGISTERS : process(clk,rst)
-------------------------------------------------------------------------------
begin
if (rising_edge(clk)) then
if (rst = '1') then
reg_out.frame <= (others => (others => '0'));
reg_out.state <= idle;
reg_out.byte_count <= 0;
reg_out.byte_index <= 0;
else
reg_out <= reg_in;
end if;
end if;
end process REGISTERS;
end two_proc;
|
gpl-3.0
|
bf36ecb9540469352201e972b8aa3ec9
| 0.419451 | 4.620452 | false | false | false | false |
os-cillation/easyfpga-soc
|
templates/standalone_application/hello_world.vhd
| 1 | 2,373 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- H E L L O W O R L D S T A N D A L O N E A P P L I C A T I O N
-- (hello_world.vhd)
--
-- Simple 1 Hz LED blinker
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--------------------------------------------------------------------------------
ENTITY hello_world is
--------------------------------------------------------------------------------
port (
-- 8 MHz clock input
clk_i : in std_logic;
-- LED output
gpio_b0_00 : out std_logic
);
end hello_world;
--------------------------------------------------------------------------------
ARCHITECTURE behavioral of hello_world is
--------------------------------------------------------------------------------
constant counter_max : natural := 8000000;
-------------------------------------------------------------------------------
begin -- architecture behavioral
-------------------------------------------------------------------------------
counter : process(clk_i)
variable count : natural range 0 to counter_max := 0;
begin
if (rising_edge(clk_i)) then
-- LED on
if (count < counter_max/2) then
gpio_b0_00 <= '1';
count := count + 1;
-- LED off
elsif (count < counter_max) then
gpio_b0_00 <= '0';
count := count + 1;
-- counter reset
else
count := 0;
end if;
end if;
end process counter;
end behavioral;
|
gpl-3.0
|
e5deec7637f4ae1666ed2df9a23049be
| 0.453434 | 4.985294 | false | false | false | false |
xylnao/w11a-extra
|
rtl/ibus/ibdr_minisys.vhd
| 2 | 7,065 |
-- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_minisys - syn
-- Description: ibus(rem) devices for minimal system:SDR+KW+DL+RK
--
-- Dependencies: ibdr_sdreg
-- ibd_kw11l
-- ibdr_dl11
-- ibdr_rk11
-- ib_sres_or_4
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 128 469 16 265 s 7.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 122 472 16 269 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
-- to _dl11
-- 2009-05-31 221 1.0.6 add RESET to kw11l;
-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC
-- 2008-08-22 161 1.0.4 use iblib, ibdlib
-- 2008-05-09 144 1.0.3 use EI_ACK with _kw11l, _dl11
-- 2008-04-18 136 1.0.2 add RESET port, use for ibdr_sdreg
-- 2008-01-20 113 1.0.1 RRI_LAM now vector
-- 2008-01-20 112 1.0 Initial version
------------------------------------------------------------------------------
--
-- mini system setup
--
-- ibbase vec pri slot attn device name
--
-- 177546 100 6 4 - KW11-L
-- 177400 220 5 3 4 RK11
-- 177560 060 4 2 1 DL11-RX 1st
-- 064 4 1 ^ DL11-TX 1st
-- 177570 - - - - sdreg
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end ibdr_minisys;
architecture syn of ibdr_minisys is
constant conf_intmap : intmap_array_type :=
(intmap_init, -- line 15
intmap_init, -- line 14
intmap_init, -- line 13
intmap_init, -- line 12
intmap_init, -- line 11
intmap_init, -- line 10
intmap_init, -- line 9
intmap_init, -- line 8
intmap_init, -- line 7
intmap_init, -- line 6
intmap_init, -- line 5
(8#100#,6), -- line 4 KW11-L
(8#220#,5), -- line 3 RK11
(8#060#,4), -- line 2 DL11-RX
(8#064#,4), -- line 1 DL11-TX
intmap_init -- line 0
);
signal RB_LAM_DL11 : slbit := '0';
signal RB_LAM_RK11 : slbit := '0';
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
signal IB_SRES_DL11 : ib_sres_type := ib_sres_init;
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
signal EI_REQ : slv16_1 := (others=>'0');
signal EI_ACK : slv16_1 := (others=>'0');
signal EI_REQ_KW11L : slbit := '0';
signal EI_REQ_DL11RX : slbit := '0';
signal EI_REQ_DL11TX : slbit := '0';
signal EI_REQ_RK11 : slbit := '0';
signal EI_ACK_KW11L : slbit := '0';
signal EI_ACK_DL11RX : slbit := '0';
signal EI_ACK_DL11TX : slbit := '0';
signal EI_ACK_RK11 : slbit := '0';
begin
SDREG : ibdr_sdreg
port map (
CLK => CLK,
RESET => RESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SDREG,
DISPREG => DISPREG
);
KW11L : ibd_kw11l
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
BRESET => BRESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_KW11L,
EI_REQ => EI_REQ_KW11L,
EI_ACK => EI_ACK_KW11L
);
DL11 : ibdr_dl11
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_DL11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11,
EI_REQ_RX => EI_REQ_DL11RX,
EI_REQ_TX => EI_REQ_DL11TX,
EI_ACK_RX => EI_ACK_DL11RX,
EI_ACK_TX => EI_ACK_DL11TX
);
RK11 : ibdr_rk11
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RB_LAM => RB_LAM_RK11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RK11,
EI_REQ => EI_REQ_RK11,
EI_ACK => EI_ACK_RK11
);
SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_SDREG,
IB_SRES_2 => IB_SRES_KW11L,
IB_SRES_3 => IB_SRES_DL11,
IB_SRES_4 => IB_SRES_RK11,
IB_SRES_OR => IB_SRES
);
INTMAP : ib_intmap
generic map (
INTMAP => conf_intmap)
port map (
EI_REQ => EI_REQ,
EI_ACKM => EI_ACKM,
EI_ACK => EI_ACK,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT
);
EI_REQ(4) <= EI_REQ_KW11L;
EI_REQ(3) <= EI_REQ_RK11;
EI_REQ(2) <= EI_REQ_DL11RX;
EI_REQ(1) <= EI_REQ_DL11TX;
EI_ACK_KW11L <= EI_ACK(4);
EI_ACK_RK11 <= EI_ACK(3);
EI_ACK_DL11RX <= EI_ACK(2);
EI_ACK_DL11TX <= EI_ACK(1);
RB_LAM(1) <= RB_LAM_DL11;
RB_LAM(2) <= '0'; -- for 2nd DL11
RB_LAM(3) <= '0'; -- for DZ11
RB_LAM(4) <= RB_LAM_RK11;
RB_LAM(15 downto 5) <= (others=>'0');
end syn;
|
gpl-2.0
|
e0d09a244773aa857421e9a2c84a6403
| 0.492994 | 3.144192 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
quartz/quartz.vhd
| 1 | 3,033 |
--=============================================================================
-- Model: macromodel of the quartz based on an equivalent RLC circuit
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
-- Date: 30.11.2011
-------------------------------------------------------------------------------
-- Library: kvl in hAMSter
--
-- ID: quartz.vhd
--
-- Rev. 1.00 24.08.2015 GitHub
-------------------------------------------------------------------------------
-- [Hrsg. Wolfgang Hilberg, Funkuhrtechnik, München 1988]
-- für einen Quarz mit f = 77.5 kHz gelten etwa folgende Werte:
-- Lm = 3127.11 H
-- Rm = 17 kOhm
-- Cm = 1.35 fF
-- C = 1.25 pF
-------------------------------------------------------------------------------
--
-- Lm Rm Cm
-- e1 i1 ____ i2 || e2
-- <--o---^^^^--o--|____|--o--||---o-->
-- | || |
-- | || Cp |
-- o-------------||-------------o
-- ||
--
-- ASCII-Schematic of the quartz
--=============================================================================
use work.electromagnetic_system.all;
use work.all;
library ieee;
-------------------------------------------------------------------------------
entity quartz is
generic (
Rm_val:real; -- resistance value
Lm_val:real; -- inductance value
Cm_val:real; -- capacitance value
Cp_val:real); -- capacitance value
port (terminal e1,e2:electrical); -- interface terminals
end entity quartz;
-------------------------------------------------------------------------------
architecture behav_subcircuit of quartz is -- subcircuit
terminal i1,i2: electrical; -- internal terminals
begin
Lm:
entity inductor(basic)
generic map(Lm_val)
port map(e1,i1);
Rm:
entity resistor(basic)
generic map(Rm_val)
port map(i1,i2);
Cm:
entity capacitor(basic)
generic map(Cm_val)
port map(i2,e2);
Cp:
entity capacitor(basic)
generic map(Cp_val)
port map(e1,e2);
end architecture behav_subcircuit;
-------------------------------------------------------------------------------
architecture behav_ode of quartz is -- series RLC by 2nd ODE
quantity v across i through e1 to e2;
begin
v == i'dot'dot + Rm_val/Lm_val*i'dot + 1.0/Lm_val/Cm_val*i;
end architecture behav_ode;
-------------------------------------------------------------------------------
architecture behav_Hs of quartz is -- series RLC by H(s)
quantity v across i through e1 to e2;
constant numerator: real_vector(1 to 3):=(0.0, 1.0, 0.0); -- a0 a1 a2
constant denomerator: real_vector(1 to 3):=(1.0/Cm_val,Rm_val,Lm_val); -- b0 b1 b2
begin
i == v'LTF(numerator,denomerator);
end architecture behav_Hs;
--=============================================================================
--=============================================================================
|
mit
|
054890b7fec161e2bddc313894116d02
| 0.415045 | 4.009259 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/bpgen/sn_humanio.vhd
| 1 | 4,353 |
-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio - syn
-- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3
--
-- Dependencies: xlib/iob_reg_o_gen
-- bpgen/bp_swibtnled
-- bpgen/sn_4x7segctl
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
-- 2011-07-02 387 1.1.2 use bp_swibtnled
-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
-- 2010-04-10 275 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end sn_humanio;
architecture syn of sn_humanio is
signal N_ANO_N : slv4 := (others=>'0');
signal N_SEG_N : slv8 := (others=>'0');
begin
IOB_ANO_N : iob_reg_o_gen
generic map (DWIDTH => 4)
port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
IOB_SEG_N : iob_reg_o_gen
generic map (DWIDTH => 8)
port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
HIO : bp_swibtnled
generic map (
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,
LWIDTH => LWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
DRV : sn_4x7segctl
generic map (
CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
port map (
CLK => CLK,
DIN => DSP_DAT,
DP => DSP_DP,
ANO_N => N_ANO_N,
SEG_N => N_SEG_N
);
end syn;
|
gpl-2.0
|
388aaf41ab871b48261b738efc4db9f5
| 0.519412 | 3.443829 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw 5/FourBitMultiplier.vhd
| 1 | 2,656 |
library ieee;
use ieee.std_logic_1164.all;
entity FourBitMultiplier is
port(
SW : IN std_logic_vector(7 downto 0);
KEY0: IN std_logic;
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5: OUT std_logic_vector (6 downto 0);
LEDR: out std_logic_vector(7 downto 0)
);
end FourBitMultiplier;
architecture impl of FourBitMultiplier is
component OneBitAdder is
port(
A, B, CIN: IN std_logic;
S, COUT: OUT std_logic
);
end component;
component HexDisplay is
port(
input: in std_logic_vector(3 downto 0);
display: out std_logic_vector(6 downto 0)
);
end component;
signal c0: std_logic_vector(4 downto 0) := "00000";
signal c1: std_logic_vector(4 downto 0) := "00000";
signal c2: std_logic_vector(4 downto 0) := "00000";
signal line2: std_logic_vector(2 downto 0) := "000";
signal line3: std_logic_vector(2 downto 0) := "000";
signal buf: std_logic_vector(7 downto 0) := "00000000";
signal ledrOut: std_logic_vector(7 downto 0) := "00000000";
begin
H0: HexDisplay port map(
ledrOut(3 downto 0), HEX0(6 downto 0)
);
H1: HexDisplay port map(
ledrOut(7 downto 4), HEX1(6 downto 0)
);
HEX2 <= "1101110"; -- = sign
H3: HexDisplay port map(
SW(3 downto 0), HEX3(6 downto 0)
);
HEX4 <= "0010010"; -- multiplication sign
H5: HexDisplay port map(
SW(7 downto 4), HEX5(6 downto 0)
);
--1st line of adders
add01: OneBitAdder port map(
SW(5) and SW(0), SW(4) and SW(1), c0(0), buf(1), C0(1)
);
add11: OneBitAdder port map(
SW(6) and SW(0), SW(5) and SW(1), c0(1), line2(0), C0(2)
);
add21: OneBitAdder port map(
SW(7) and SW(0), SW(6) and SW(1), c0(2), line2(1), C0(3)
);
add31: OneBitAdder port map(
'0', SW(7) and SW(1), c0(0), line2(2), C0(4)
);
--2nd line of adders
add02: OneBitAdder port map(
line2(0), SW(4) and SW(2), c1(0), buf(2), C1(1)
);
add12: OneBitAdder port map(
line2(1), SW(5) and SW(2), c1(1), line3(0), C1(2)
);
add22: OneBitAdder port map(
line2(2), SW(6) and SW(2), c1(2), line3(1), C1(3)
);
add32: OneBitAdder port map(
C0(4), SW(7) and SW(2), c1(3), line3(2), C1(4)
);
--3th line of adders
add03: OneBitAdder port map(
line3(0), SW(4) and SW(3), c2(0), buf(3), C2(1)
);
add13: OneBitAdder port map(
line3(1), SW(5) and SW(3), c2(1), buf(4), C2(2)
);
add23: OneBitAdder port map(
line3(2), SW(6) and SW(3), c2(2), buf(5), C2(3)
);
add33: OneBitAdder port map(
C1(4), SW(7) and SW(3), c2(3), buf(6), buf(7)
);
--others
process (KEY0)
begin
if rising_edge(KEY0) then
ledrOut(0) <= SW(4) and SW(0);
ledrOut(7 downto 1) <= buf(7 downto 1);
LEDR(0) <= SW(4) and SW(0);
LEDR(7 downto 1) <= buf(7 downto 1);
end if;
end process;
end;
|
mit
|
b87c441655a84982eab42bfb3dc780e5
| 0.624247 | 2.379928 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd
| 1 | 2,918 |
-- $Id: dcm_sfs_unisim_s3e.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: dcm_sfs - syn
-- Description: DCM for simple frequency synthesis; SPARTAN-3E version
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.0.3 rename dcm_sp_sfs -> dcm_sfs, SPARTAN-3E version
-- 2011-11-10 423 1.0.2 add FAMILY generic, SPARTAN-3 support
-- 2010-11-12 338 1.0.1 drop SB_CLK generic; allow DIV=1,MUL=1 without DCM
-- 2010-11-07 337 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
architecture syn of dcm_sfs is
begin
assert (CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1) or CLKFX_MULTIPLY>=2
report "assert((FX_DIV=1 and FX_MULT)=1 or FX_MULT>=2"
severity failure;
DCM0: if CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate DCM0;
DCM1: if CLKFX_MULTIPLY>=2 generate
DCM : dcm_sp
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => CLKFX_DIVIDE,
CLKFX_MULTIPLY => CLKFX_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE")
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end generate DCM1;
end syn;
|
gpl-2.0
|
30b108a2400728b9993df0c05a087514
| 0.585332 | 3.804433 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/constants.vhd
| 1 | 4,681 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package constants is
---------------------------------
-- protcol opcodes and lengthes
---------------------------------
constant ACK_OPC : std_logic_vector(7 downto 0) := x"00";
constant ACK_LEN : integer := 3;
constant NACK_OPC : std_logic_vector(7 downto 0) := x"11";
constant NACK_LEN : integer := 4;
constant MCU_SEL_OPC : std_logic_vector(7 downto 0) := x"55";
constant MCU_SEL_LEN : integer := 3;
-- detect (who is communicating)
constant DETECT_OPC : std_logic_vector(7 downto 0) := x"EE";
constant DETECT_LEN : integer := 1;
constant DETECT_REPLY_OPC : std_logic_vector(7 downto 0) := x"FF";
constant DETECT_REPLY_LEN : integer := 3;
constant DETECT_REPLY_FPGA : std_logic_vector(7 downto 0) := x"EF";
-- write operations
constant REGISTER_WR_OPC : std_logic_vector(7 downto 0) := x"66";
constant REGISTER_WR_LEN : integer := 6;
constant REGISTER_MWR_OPC : std_logic_vector(7 downto 0) := x"65";
constant REGISTER_MWR_LEN : integer := 6; -- minimal length (no data)
constant REGISTER_AWR_OPC : std_logic_vector(7 downto 0) := x"69";
constant REGISTER_AWR_LEN : integer := 6; -- minimal length (no data)
-- read operations and replies
constant REGISTER_RD_OPC : std_logic_vector(7 downto 0) := x"77";
constant REGISTER_RD_LEN : integer := 5;
constant REGISTER_RDRE_OPC : std_logic_vector(7 downto 0) := x"88";
constant REGISTER_RDRE_LEN : integer := 4;
constant REGISTER_MRD_OPC : std_logic_vector(7 downto 0) := x"73";
constant REGISTER_MRD_LEN : integer := 6;
constant REGISTER_MRDRE_OPC : std_logic_vector(7 downto 0) := x"93";
constant REGISTER_MRDRE_LEN : integer := 3; -- minimal length (no data)
constant REGISTER_ARD_OPC : std_logic_vector(7 downto 0) := x"79";
constant REGISTER_ARD_LEN : integer := 6;
constant REGISTER_ARDRE_OPC : std_logic_vector(7 downto 0) := x"90";
constant REGISTER_ARDRE_LEN : integer := 3; -- minimal length (no data)
-- interrupts
constant SOC_INT_OPC : std_logic_vector(7 downto 0) := x"99";
constant SOC_INT_LEN : integer := 3;
constant SOC_INT_EN_OPC : std_logic_vector(7 downto 0) := x"AA";
constant SOC_INT_EN_LEN : integer := 3;
---------------------------------
-- global protocol parameters
---------------------------------
constant REGISTER_DAT_MAX : integer := 255; -- maximum mwr/awr data length
constant PROTO_WC_RX_MAX : integer := 16; -- number of bytes that fit into rx buffer
constant PROTO_WC_TX_MAX : integer := 16; -- number of bytes that fit into tx buffer
constant PROTO_WC_MAX : integer := REGISTER_MWR_LEN + REGISTER_DAT_MAX; -- longest frame possible
constant FIFO_WIDTH : integer := 8;
constant OPCODE_UNKNOWN_TIMEOUT : integer := 20;
---------------------------------
-- error codes
---------------------------------
constant ERROR_UNKNOWN : std_logic_vector(7 downto 0) := x"00";
constant ERROR_OPC_UNKNOWN : std_logic_vector(7 downto 0) := x"11";
constant ERROR_PARITY : std_logic_vector(7 downto 0) := x"22";
constant ERROR_WB_TIMEOUT : std_logic_vector(7 downto 0) := x"33";
---------------------------------
-- wishbone
---------------------------------
constant WB_DW : integer := 8; -- data width
constant WB_AW : integer := 16; -- address width
constant WB_CORE_AW : integer := 8; -- core base-address bits
-- (encoded by intercon)
constant WB_REG_AW : integer := 8; -- register address bits
-- (encoded by core)
constant WB_TIMEOUT_CYCLES : integer := 16; -- clock cycles until
-- timeout detection
end constants;
|
gpl-3.0
|
83a5526ee926c31e4ea463019849580f
| 0.59154 | 3.920436 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/algorithms/sourdis_bispo_nfa/vhdl/state_pcre_at_least.vhd
| 1 | 1,814 |
-- ----------------------------------------------------------------------------
-- Entity for implementation of exactly N
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity STATE_PCRE_AT_LEAST is
generic(
M : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
INPUT : in std_logic;
SYMBOL : in std_logic;
WE : in std_logic;
-- output data interface
OUTPUT : out std_logic
);
end entity STATE_PCRE_AT_LEAST;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of STATE_PCRE_AT_LEAST is
signal value : std_logic_vector(11 downto 0);
signal local_reset : std_logic;
begin
local_reset <= RESET or not SYMBOL;
cnt_symbols: process(RESET, CLK)
begin
if (CLK'event and CLK = '1') then
if (local_reset = '1') then
value <= (others => '0');
else
if (we = '1') then
if ((value > 0) or (INPUT = '1')) then
value <= value + 1;
end if;
end if;
end if;
end if;
end process;
OUTPUT <= '1' when (value >= M) else '0';
end architecture full;
|
gpl-2.0
|
997a22bc352065e373f0bac1dac68827
| 0.364388 | 5.109859 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL stimulus files/Pendant_decoder_testbench.vhd
| 1 | 14,627 |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
--
-- File: Pendant_decoder_testbench.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- Testbench for UART pendant decoder
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Pendant_decoder_testbench is
end Pendant_decoder_testbench;
architecture behavioral of Pendant_decoder_testbench is
constant SYSCLK_PERIOD : time := 20 ns; -- 50MHZ
constant SYSCLK_LF_PERIOD : time := 100 ns; -- 10MHZ
constant SYSCLK_Khz_PERIOD : time := 0.256 us; -- 3900 Khz. REAL FREQ is 39 Khz (T=25.6 us)
signal SYSCLK : std_logic := '0';
signal SYSCLK_LF : std_logic := '0';
signal SYSCLK_Khz : std_logic := '0';
signal NSYSRESET : std_logic := '0';
signal s_UART_DATA1_IN : std_logic_vector (7 downto 0);
signal s_UART_DATA2_IN : std_logic_vector (7 downto 0);
signal s_UART_DATA_OUT : std_logic_vector (7 downto 0);
signal s_UART_Tx_Gate : std_logic;
signal s_UART_Write_mode : std_logic;
signal s_UART_DATA_OUT2 : std_logic_vector (7 downto 0);
signal s_UART_Tx_Gate2 : std_logic;
signal s_ACLR_UART_Rx_Out_N : std_logic;
signal s_Disp_axis_reg : std_logic_vector (23 downto 0);
signal s_Current_axis_reg : std_logic_vector (23 downto 0);
signal s_MODE_out : std_logic_vector (2 downto 0);
signal s_Mode_Ready_out : std_logic;
signal s_AXIS_out : std_logic_vector (3 downto 0);
signal s_Axis_Ready_out : std_logic;
signal s_LED_reg : std_logic_vector (23 downto 0);
signal s_Button_reg : std_logic_vector (23 downto 0);
signal s_Speed_reg : std_logic_vector (23 downto 0);
component PENDANT_DECODER
-- ports
port(
-- Inputs
RESET_N : in std_logic;
SCLK_IN : in std_logic;
SCLK_Khz_IN : in std_logic; -- External SCLK xx Khz
SCLK_LF_IN : in std_logic; -- External SCLK 10 Mhz
UART_DATA1_IN : in std_logic_vector(7 downto 0);
UART_DATA2_IN : in std_logic_vector(7 downto 0);
Disp_axis_reg : in std_logic_vector(23 downto 0); -- Data FROM PMAC (confirmation of axis and mode selection)
LED_reg : in std_logic_vector(23 downto 0); -- Data FROM PMAC (indicators on programmable LEDs)
sw1 : in std_logic;
sw2 : in std_logic;
-- Outputs
Current_axis_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
Speed_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
Button_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
UART_DATA_OUT : out std_logic_vector(7 downto 0);
UART_Tx_Gate : out std_logic; -- latch UART data in external Tx registers
UART_Write_mode : out std_logic;
UART_DATA_OUT2 : out std_logic_vector(7 downto 0); -- Data TO pendant (LED control)
UART_Tx_Gate2 : out std_logic; -- latch UART data in external Tx registers (LED control)
MODE_out : out std_logic_vector(2 downto 0);
Mode_Ready_out : out std_logic;
AXIS_out : out std_logic_vector(3 downto 0);
Axis_Ready_out : out std_logic;
ACLR_UART_Rx_Out_N : out std_logic; -- clear UART Rx reg (active low)
flag1 : out std_logic
-- Inouts
);
end component;
begin
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 10 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
SYSCLK_LF <= not SYSCLK_LF after (SYSCLK_LF_PERIOD / 2.0 );
SYSCLK_Khz <= not SYSCLK_Khz after (SYSCLK_Khz_PERIOD / 2.0 );
-- Instantiate Unit Under Test: PENDANT_DECODER
PENDANT_DECODER_0 : PENDANT_DECODER
-- port map
port map(
-- Inputs
RESET_N => NSYSRESET,
SCLK_IN => SYSCLK,
SCLK_LF_IN => SYSCLK_LF,
SCLK_Khz_IN => SYSCLK_Khz,
UART_DATA1_IN => s_UART_DATA1_IN,
UART_DATA2_IN => s_UART_DATA2_IN,
Disp_axis_reg => s_Disp_axis_reg,
LED_reg => s_LED_reg,
sw1 => '0',
sw2 => '0',
-- Outputs
Current_axis_reg => s_Current_axis_reg,
Speed_reg => s_Speed_reg,
Button_reg => s_Button_reg,
UART_DATA_OUT => s_UART_DATA_OUT,
UART_Tx_Gate => s_UART_Tx_Gate,
UART_Write_mode => s_UART_Write_mode,
UART_DATA_OUT2 => s_UART_DATA_OUT2,
UART_Tx_Gate2 => s_UART_Tx_Gate2,
MODE_out => s_MODE_out,
Mode_Ready_out => s_Mode_Ready_out,
AXIS_out => s_Axis_out,
Axis_Ready_out => s_Axis_Ready_out,
ACLR_UART_Rx_Out_N => s_ACLR_UART_Rx_Out_N,
flag1 => open
-- Inouts
);
process
begin
-----------------
--Initialization
--Reset for 10 clk cycles
-----------------
s_UART_DATA1_IN <= (others => '0');
s_UART_DATA2_IN <= (others => '0');
s_Disp_axis_reg <= (others => '0');
s_LED_reg <= (others => '0');
--AXIS CHANGE
--------------------------------------
--send axis X code
wait for ( SYSCLK_PERIOD * 20 );
s_UART_DATA1_IN <= x"55"; -- axis X (1st part)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"16"; -- axis Y (2nd part) - wrong!
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"400000"; -- Y confirmation, FALSE
wait for ( SYSCLK_PERIOD * 3 );
s_Disp_axis_reg <= x"880000"; -- false confirmation, FALSE
wait for ( SYSCLK_PERIOD * 3 );
s_Disp_axis_reg <= x"800000"; -- X confirmation, TRUE
--------------------------------------
--send axis Y code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"56"; -- axis Y
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"16"; -- axis Y
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"400000"; -- Y confirmation, TRUE
-------------------------------------
--send axis X code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"55"; -- axis X
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"800000"; -- X confirmation, TRUE
-------------------------------------
--send axis Y code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"56"; -- axis Y
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"16"; -- axis Y
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"400000"; -- Y confirmation, TRUE
-------------------------------------
--send axis Z code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"57"; -- axis Z
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"17"; -- axis Z
--emulate Axis change before confirmation
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"55"; -- axis X
wait for ( SYSCLK_PERIOD * 2 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"200000"; -- Z confirmation, TRUE
-------------------------------------
--send axis A4 code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"58"; -- axis 4
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"18"; -- axis 4
--emulate Axis change before confirmation
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"55"; -- axis X
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"800000"; -- X confirmation, FALSE
wait for ( SYSCLK_PERIOD * 4 );
s_Disp_axis_reg <= x"100000"; -- A4 confirmation, TRUE
-------------------------------------
--MODE CHANGE
--------------------------------------
--send mode MANU code
wait for ( SYSCLK_PERIOD * 15 );
s_UART_DATA1_IN <= x"52"; -- MANU
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"12"; -- MANU
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000002"; -- INC confirmation, FALSE
wait for ( SYSCLK_PERIOD * 4 );
s_Disp_axis_reg <= x"000001"; -- MANU confirmation, TRUE
--------------------------------------
--send mode INC code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"53"; -- INC
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"13"; -- INC
--emulate Axis change before confirmation
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"55"; -- axis X
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000002"; -- INC confirmation, TRUE
--send mode HPG code
wait for ( SYSCLK_PERIOD * 7 );
s_UART_DATA1_IN <= x"54"; -- HPG
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"14"; -- HPG
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000004"; -- HPG confirmation, TRUE
--send mode MANU code
wait for ( SYSCLK_PERIOD * 7 );
s_UART_DATA1_IN <= x"52"; -- MANU
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"12"; -- MANU
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000001"; -- MANU confirmation, TRUE
--send mode INC code
wait for ( SYSCLK_PERIOD * 7 );
s_UART_DATA1_IN <= x"53"; -- INC
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"13"; -- INC
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000002"; -- INC confirmation, TRUE
--------------------------------------
wait for ( SYSCLK_PERIOD * 30 );
-------------------------------------
--BUTTONS press
--------------------------------------
--press F1
wait for ( SYSCLK_PERIOD * 50 );
s_UART_DATA1_IN <= x"41"; -- F1 press
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"01"; -- F1 release (will not be processed)
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"01"; -- F1 release
-- emulate LED control
wait for ( SYSCLK_PERIOD * 8 );
s_LED_reg <= x"000001"; -- LED1 ON
--press F2
wait for ( SYSCLK_PERIOD * 110 );
s_UART_DATA1_IN <= x"42"; -- F2 press
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"02"; -- F2 release (will not be processed)
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"02"; -- F2 release
-- emulate LED control
wait for ( SYSCLK_PERIOD * 8 );
s_LED_reg <= x"000003"; -- LED1 and LED2 ON
--press F3
wait for ( SYSCLK_PERIOD * 110 );
s_UART_DATA1_IN <= x"43"; -- F3 press
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"03"; -- F3 release (will not be processed)
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"03"; -- F3 release
-- emulate LED control
wait for ( SYSCLK_PERIOD * 8 );
s_LED_reg <= x"000004"; -- LED3 ON
wait for ( SYSCLK_PERIOD * 110 );
s_LED_reg <= x"000000"; -- LED1-3 OFF
----------------------
-- TEST J+ and J-
----------------------
wait for ( SYSCLK_PERIOD * 110 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (1st)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (2nd)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
--s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (3rd)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (4th)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (5th)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 10 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (1st)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (2nd)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (3rd)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (4th)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (5th)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 800 );
end process;
end behavioral;
|
gpl-2.0
|
3d269271c3b5171047b5156e0e7b238e
| 0.563684 | 3.040324 | false | false | false | false |
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