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rogerioag/gcg
|
tutorial/ula/testbench/somador_tb.vhd
| 1 | 2,382 |
-- Testebench gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Descrição da Entidade: somador.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity somador_tb is
end somador_tb;
architecture estrutural of somador_tb is
-- Declaração do componente.
component somador
port(a, b, cin, opSomador:in std_logic; s, cout: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for somador_0: somador use entity work.somador;
signal t_a, t_b, t_cin, t_opSomador, t_s, t_cout: std_logic;
begin
-- Instanciação do Componente.
somador_0: somador port map (a=>t_a, b=>t_b, cin=>t_cin, opSomador=>t_opSomador, s=>t_s, cout=>t_cout);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
type pattern_type is record
-- entradas.
vi_a, vi_b, vi_cin, vi_opSomador: std_logic;
-- saídas.
vo_s, vo_cout : std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0', '0', '1', '0', '0'),
('0', '0', '1', '1', '1', '0'),
('0', '1', '0', '1', '1', '0'),
('0', '1', '1', '1', '0', '1'),
('1', '0', '0', '1', '1', '0'),
('1', '0', '1', '1', '0', '1'),
('1', '1', '0', '1', '0', '1'),
('1', '1', '1', '1', '1', '1'),
('1', '1', '1', '0', '0', '0')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
t_a <= patterns(i).vi_a;
t_b <= patterns(i).vi_b;
t_cin <= patterns(i).vi_cin;
t_opSomador <= patterns(i).vi_opSomador;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert t_s = patterns(i).vo_s
report "Valor de t_s não confere com o resultado esperado." severity error;
assert t_cout = patterns(i).vo_cout
report "Valor de t_cout não confere com o resultado esperado."severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end estrutural;
|
gpl-3.0
|
344e9877eadb738c00c1703cbfab1776
| 0.576207 | 3.079531 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd
| 1 | 3,297 |
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (cloned from _n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim...
-- constant sys_conf_clkfx_divide : positive := 5;
-- constant sys_conf_clkfx_multiply : positive := 4; -- ==> 80 MHz
constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 7;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
9ac77adbff7ae72db9d8ccc2258adef1
| 0.605702 | 3.692049 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
| 1 | 20,935 |
-- $Id: sys_w11a_s3.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_s3 - syn
-- Description: w11a test design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_sp1c
-- vlib/rbus/rb_sres_or_2
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_bram
-- vlib/s3board/s3_sram_dummy
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- bplib/s3board/s3_sram_memctl
-- ibus/ib_sres_or_2
-- ibus/ibdr_minisys
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_sys_w11a_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-21 442 13.1 O40d xc3s1000-4 1301 4307 270 2613 OK: LP+PC+DL+II
-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II
-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II
-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II
-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II
-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK
-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK
-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK
-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK
-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK
-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK
-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK
-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK
-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16
-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK
-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK
-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL
-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK
-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-21 442 1.4.4 use rlink_sp1c; hio led usage now a for n2/n3
-- 2011-11-19 427 1.4.3 now numeric_std clean
-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.4.1 use now sn_humanio
-- 2010-12-30 351 1.4 ported to rbv3
-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...)
-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport
-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3
-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl
-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce
-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- add pm1 rs232 (usp) support
-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport
-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy
-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3)
-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini|maxi)sys interface changes
-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys
-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu
-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames
-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust
-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg)
-- 2008-04-19 137 1.3.4 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys
-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs
-- 2008-02-23 118 1.3.1 add _mem70
-- 2008-02-17 117 1.3 use ext. memory interface of _core;
-- use _cache + memctl or _bram (configurable)
-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05)
-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET
-- add _ib_mux2
-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack
-- instanciate all parts directly
-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb
-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO
-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them
-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
--
-- w11a test design for s3board
-- w11a + rlink + serport
--
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0): if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_s3 is -- top level
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_w11a_s3;
architecture syn of sys_w11a_s3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CPU_RESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal CACHE_CHIT : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
signal DISPREG : slv16 := (others=>'0');
constant rbaddr_core0 : slv8 := "00000000";
constant rbaddr_ibus : slv8 := "10000000";
constant rbaddr_hio : slv8 := "11000000";
begin
CLK <= I_CLK50; -- use 50MHz as system clock
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6, -- 64 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_OR => RB_SRES
);
RP2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
CORE : pdp11_core
port map (
CLK => CLK,
RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM_BRAM: if sys_conf_bram > 0 generate
signal HM_VAL_BRAM : slbit := '0';
begin
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => EM_MREQ.req,
HM_VAL => HM_VAL_BRAM,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end generate MEM_BRAM;
MEM_SRAM: if sys_conf_bram = 0 generate
CACHE: pdp11_cache
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
FMISS => CACHE_FMISS,
CHIT => CACHE_CHIT,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => HM_ENA,
HM_VAL => CACHE_CHIT,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
SRAM_CTL: s3_sram_memctl
port map (
CLK => CLK,
RESET => CPU_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR(17 downto 0),
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end generate MEM_SRAM;
IB_SRES_OR : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES_IBDR,
IB_SRES_OR => IB_SRES);
IBD_MINI : if false generate
begin
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG);
end generate IBD_MINI;
IBD_MAXI : if true generate
begin
IBDR_SYS : ibdr_maxisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG);
end generate IBD_MAXI;
DSP_DAT(15 downto 0) <= DISPREG;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
LED <= iled;
end process;
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= CACHE_CHIT;
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
b63ed2b0b44024fa14e5c2c0096042b7
| 0.517602 | 2.909659 | false | false | false | false |
sigasi/SigasiProjectCreator
|
tests/test-files/tutorial/testbench.vhd
| 2 | 832 |
library IEEE;
use IEEE.std_logic_1164.all;
-- Test bench for Sigasi Tutorial Project.
entity testbench is
end entity testbench;
architecture STR of testbench is
signal data_out : std_logic_vector(7 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal valid : std_logic;
signal start : std_logic;
signal clk : std_logic;
signal rst : std_logic;
constant PERIOD : time := 50 ns; -- Half the clock period. The frequency will be 1/PERIOD = 20 MHz
begin
clock_generator_instance : entity work.clock_generator(BEH)
generic map(
PERIOD => PERIOD
)
port map(
clk => clk
);
dut_instance : entity work.dut(RTL)
port map(
data_out => data_out,
data_in => data_in,
valid => valid,
start => start,
clk => clk,
rst => rst
);
end architecture STR;
|
bsd-3-clause
|
4139413cf4e5219c30d1c1bd65913535
| 0.647837 | 3.116105 | false | true | false | false |
os-cillation/easyfpga-soc
|
easy_cores/i2c_master/i2c_master_top.vhd
| 1 | 15,007 |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
--
-- $Date: 2009-01-20 10:38:45 $
-- $Revision: 1.8 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_master_top is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_top;
architecture structural of i2c_master_top is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal, active low
signal rst_n : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
begin
-- generate internal reset signal (active low)
rst_n <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_we_i and iack_o;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_n, wb_clk_i)
begin
if (rst_n = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_n, wb_clk_i)
begin
if (rst_n = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = "100") ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl
port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_n,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_n)
begin
if (rst_n = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_n)
begin
if (rst_n = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
|
gpl-3.0
|
e868c7c4fb16491ea802dcf1c9f6663b
| 0.448791 | 4.201288 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/tb/tbcore_rlink.vhd
| 1 | 8,507 |
-- $Id: tbcore_rlink.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbcore_rlink - sim
-- Description: Core for a rlink_cext based test bench
--
-- Dependencies: simlib/simclk
--
-- To test: generic, any rlink_cext based target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.rlink_cext_vhpi.all;
entity tbcore_rlink is -- core of rlink_cext based test bench
generic (
CLK_PERIOD : time := 20 ns; -- clock period
CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLK : out slbit; -- main clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end tbcore_rlink;
architecture sim of tbcore_rlink is
signal CLK_L : slbit := '0';
signal CLK_STOP : slbit := '0';
begin
SYSCLK : simclk
generic map (
PERIOD => CLK_PERIOD,
OFFSET => CLK_OFFSET)
port map (
CLK => CLK_L,
CLK_CYCLE => SB_CLKCYCLE,
CLK_STOP => CLK_STOP
);
CLK <= CLK_L;
proc_conf: process
file fconf : text open read_mode is "rlink_cext_conf";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable ien : slbit := '0';
variable ibit : integer := 0;
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
SB_CNTL <= (others=>'L');
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
file_loop: while not endfile(fconf) loop
readline (fconf, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
end if;
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rbmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rbmon) <= 'L';
end if;
when ".sinit" => -- .sinit
readgen_ea(iline, iaddr, 8);
readgen_ea(iline, idata, 8);
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= 'H';
wait for 0 ns;
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
wait for 0 ns;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
wait; -- halt process here
end process proc_conf;
proc_stim: process
variable icycle : integer := 0;
variable irxint : integer := 0;
variable irxslv : slv24 := (others=>'0');
variable ibit : integer := 0;
variable oline : line;
variable r_sb_cntl : slv16 := (others=>'Z');
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
wait for CLK_OFFSET;
wait for 10*CLK_PERIOD;
stim_loop: loop
wait until rising_edge(CLK_L);
wait for CLK_PERIOD-SETUP_TIME;
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
icycle := to_integer(unsigned(SB_CLKCYCLE));
RX_VAL <= '0';
if RX_HOLD = '0' then
irxint := rlink_cext_getbyte(icycle);
if irxint >= 0 then
if irxint <= 16#ff# then -- normal data byte
RX_DATA <= slv(to_unsigned(irxint, 8));
RX_VAL <= '1';
elsif irxint >= 16#1000000# then -- out-of-band message
irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24));
iaddr := irxslv(23 downto 16);
idata := irxslv(15 downto 0);
writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG");
write(oline, irxslv(23 downto 16), right, 9);
write(oline, irxslv(15 downto 8), right, 9);
write(oline, irxslv( 7 downto 0), right, 9);
write(oline, string'(" : "));
writeoct(oline, iaddr, right, 3);
writeoct(oline, idata, right, 7);
writeline(output, oline);
if unsigned(iaddr) = 0 then
ibit := to_integer(unsigned(idata(15 downto 8)));
r_sb_cntl(ibit) := idata(0);
else
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= '1';
wait for 0 ns;
SB_VAL <= 'Z';
wait for 0 ns;
end if;
end if;
elsif irxint = -1 then -- end-of-file seen
exit stim_loop;
else
report "rlink_cext_getbyte error: " & integer'image(-irxint)
severity failure;
end if;
end if;
SB_CNTL <= r_sb_cntl;
end loop;
wait for 50*CLK_PERIOD;
CLK_STOP <= '1';
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable itxdata : integer := 0;
variable itxrc : integer := 0;
variable oline : line;
begin
loop
wait until rising_edge(CLK_L);
wait for C2OUT_TIME;
if TX_ENA = '1' then
itxdata := to_integer(unsigned(TX_DATA));
itxrc := rlink_cext_putbyte(itxdata);
assert itxrc=0
report "rlink_cext_putbyte error: " & integer'image(itxrc)
severity failure;
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
ec189c956f7f06d9e84042018bd8df83
| 0.517809 | 3.870337 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd
| 1 | 18,709 |
-- $Id: tb_tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop - sim
-- Description: Generic test bench for sys_tst_serloop_xx
--
-- Dependencies: vlib/serport/serport_uart_rxtx
-- vlib/serport/serport_xontx
--
-- To test: sys_tst_serloop_xx
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-11-06 420 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serport.all;
entity tb_tst_serloop is
port (
CLKS : in slbit; -- clock for serport
CLKH : in slbit; -- clock for humanio
CLK_STOP : out slbit; -- clock stop
P0_RXD : out slbit; -- port 0 receive data (board view)
P0_TXD : in slbit; -- port 0 transmit data (board view)
P0_RTS_N : in slbit; -- port 0 rts_n
P0_CTS_N : out slbit; -- port 0 cts_n
P1_RXD : out slbit; -- port 1 receive data (board view)
P1_TXD : in slbit; -- port 1 transmit data (board view)
P1_RTS_N : in slbit; -- port 1 rts_n
P1_CTS_N : out slbit; -- port 1 cts_n
SWI : out slv8; -- hio switches
BTN : out slv4 -- hio buttons
);
end tb_tst_serloop;
architecture sim of tb_tst_serloop is
signal CLK_STOP_L : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal CLKDIV : slv13 := (others=>'0');
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal ACTPORT : slbit := '0';
signal BREAK : slbit := '0';
signal CTS_CYCLE : integer := 0;
signal CTS_FRACT : integer := 0;
signal XON_CYCLE : integer := 0;
signal XON_FRACT : integer := 0;
signal S2M_ACTIVE : slbit := '0';
signal S2M_SIZE : integer := 0;
signal S2M_ENAESC : slbit := '0';
signal S2M_ENAXON : slbit := '0';
signal M2S_XONSEEN : slbit := '0';
signal M2S_XOFFSEEN : slbit := '0';
signal R_XONRXOK : slbit := '1';
signal R_XONTXOK : slbit := '1';
begin
proc_cycle: process (CLKS)
begin
if rising_edge(CLKS) then
CLK_CYCLE <= slv(unsigned(CLK_CYCLE) + 1);
end if;
end process proc_cycle;
UART : serport_uart_rxtx
generic map (
CDWIDTH => 13)
port map (
CLK => CLKS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
XONTX : serport_xontx
port map (
CLK => CLKS,
RESET => UART_RESET,
ENAXON => S2M_ENAXON,
ENAESC => S2M_ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => UART_TXENA,
UART_TXBUSY => UART_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => R_XONRXOK,
TXOK => R_XONTXOK
);
proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N,
P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N)
variable eff_txd : slbit := '0';
begin
if BREAK = '0' then -- if no break active
eff_txd := UART_TXD; -- send uart
else -- otherwise
eff_txd := '0'; -- force '0'
end if;
if ACTPORT = '0' then -- use port 0
P0_RXD <= eff_txd; -- write port 0 inputs
P0_CTS_N <= CTS_N;
UART_RXD <= P0_TXD; -- get port 0 outputs
RTS_N <= P0_RTS_N;
P1_RXD <= '1'; -- port 1 inputs to idle state
P1_CTS_N <= '0';
else -- use port 1
P1_RXD <= eff_txd; -- write port 1 inputs
P1_CTS_N <= CTS_N;
UART_RXD <= P1_TXD; -- get port 1 outputs
RTS_N <= P1_RTS_N;
P0_RXD <= '1'; -- port 0 inputs to idle state
P0_CTS_N <= '0';
end if;
end process proc_port_mux;
proc_cts: process(CLKS)
variable cts_timer : integer := 0;
begin
if rising_edge(CLKS) then
if CTS_CYCLE = 0 then -- if cts throttle off
CTS_N <= '0'; -- cts permanently asserted
else -- otherwise determine throttling
if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends
cts_timer := cts_timer - 1; -- decrement
else
cts_timer := CTS_CYCLE-1; -- otherwise reload
end if;
if cts_timer < cts_fract then -- if in lower 'fract' counts
CTS_N <= '1'; -- throttle: deassert CTS
else -- otherwise
CTS_N <= '0'; -- let go: assert CTS
end if;
end if;
end if;
end process proc_cts;
proc_xonrxok: process(CLKS)
variable xon_timer : integer := 0;
begin
if rising_edge(CLKS) then
if XON_CYCLE = 0 then -- if xon throttle off
R_XONRXOK <= '1'; -- xonrxok permanently asserted
else -- otherwise determine throttling
if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends
xon_timer := xon_timer - 1; -- decrement
else
xon_timer := XON_CYCLE-1; -- otherwise reload
end if;
if xon_timer < xon_fract then -- if in lower 'fract' counts
R_XONRXOK <= '0'; -- throttle: deassert xonrxok
else -- otherwise
R_XONRXOK <= '1'; -- let go: assert xonrxok
end if;
end if;
end if;
end process proc_xonrxok;
proc_xontxok: process(CLKS)
begin
if rising_edge(CLKS) then
if M2S_XONSEEN = '1' then
R_XONTXOK <= '1';
elsif M2S_XOFFSEEN = '1' then
R_XONTXOK <= '0';
end if;
end if;
end process proc_xontxok;
proc_stim: process
file fstim : text open read_mode is "tb_tst_serloop_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable iactport : slbit := '0';
variable iswi : slv8 := (others=>'0');
variable btn_num : integer := 0;
variable i_cycle : integer := 0;
variable i_fract : integer := 0;
variable nbyte : integer := 0;
variable enaesc : slbit := '0';
variable enaxon : slbit := '0';
variable bcnt : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
procedure waitclk(ncyc : in integer) is
begin
for i in 1 to ncyc loop
wait until rising_edge(CLKS);
end loop; -- i
end procedure waitclk;
begin
-- initialize some top level out signals
SWI <= (others=>'0');
BTN <= (others=>'0');
wait until rising_edge(CLKS);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wait " => -- wait
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": wait ");
write(oline, idelta, right, 5);
writeline(output, oline);
waitclk(idelta);
when "port " => -- switch rs232 port
read_ea(iline, iactport);
ACTPORT <= iactport;
writetimestamp(oline, CLK_CYCLE, ": port ");
write(oline, iactport, right, 5);
writeline(output, oline);
when "cts " => -- setup cts throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
CTS_CYCLE <= i_cycle;
CTS_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "xon " => -- setup xon throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
XON_CYCLE <= i_cycle;
XON_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "swi " => -- new SWI settings
read_ea(iline, iswi);
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": swi ");
write(oline, iswi, right, 10);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
SWI <= iswi;
wait until rising_edge(CLKS);
waitclk(idelta);
when "btn " => -- BTN push (3 cyc down + 3 cyc wait)
read_ea(iline, btn_num);
read_ea(iline, idelta);
if btn_num>=0 and btn_num<=3 then
writetimestamp(oline, CLK_CYCLE, ": btn ");
write(oline, btn_num, right, 5);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
BTN(btn_num) <= '1'; -- 3 cycle BTN pulse
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
BTN(btn_num) <= '0';
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKS);
waitclk(idelta);
else
write(oline, string'("!! btn: btn number out of range"));
writeline(output, oline);
end if;
when "expect" => -- expect n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": expect");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
if nbyte > 0 then
S2M_ACTIVE <= '1';
S2M_SIZE <= nbyte;
else
S2M_ACTIVE <= '0';
end if;
S2M_ENAESC <= enaesc;
S2M_ENAXON <= enaxon;
wait until rising_edge(CLKS);
when "send " => -- send n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
bcnt := 0;
itxdata := (others=>'0');
wait until falling_edge(CLKS);
while bcnt < nbyte loop
while TXBUSY='1' or RTS_N='1' loop
wait until falling_edge(CLKS);
end loop;
TXDATA <= itxdata;
itxdata := slv(unsigned(itxdata) + 1);
bcnt := bcnt + 1;
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until falling_edge(CLKS);
end loop;
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send...
wait until falling_edge(CLKS);
end loop;
wait until rising_edge(CLKS);
when "break " => -- send a break for n cycles
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": break ");
write(oline, idelta, right, 5);
writeline(output, oline);
-- send break for n cycles
BREAK <= '1';
waitclk(idelta);
BREAK <= '0';
-- wait for 3 bit cell width
waitclk(3*to_integer(unsigned(CLKDIV)+1));
-- send 'sync' character
wait until falling_edge(CLKS);
TXDATA <= "10000000";
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until rising_edge(CLKS);
when "clkdiv" => -- set new clock divider
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": clkdiv");
write(oline, idelta, right, 5);
writeline(output, oline);
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length));
UART_RESET <= '1';
wait until rising_edge(CLKS);
UART_RESET <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
-- extra wait for at least two character times (20 bit times)
-- to allow tx and rx of the last character
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
CLK_STOP_L <= '1';
wait for 500 ns; -- allows dcm's to stop
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
CLK_STOP <= CLK_STOP_L;
proc_moni: process
variable oline : line;
variable dclk : integer := 0;
variable active_1 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable irxeff : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable doesc : slbit := '0';
variable bcnt : integer := 0;
variable xseen : slbit := '0';
begin
loop
wait until falling_edge(CLKS);
M2S_XONSEEN <= '0';
M2S_XOFFSEEN <= '0';
if S2M_ACTIVE='1' and active_1='0' then -- start expect message
irxdata := (others=>'0');
bcnt := 0;
end if;
if S2M_ACTIVE='0' and active_1='1' then -- end expect message
if bcnt = S2M_SIZE then
writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
else
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
write(oline, bcnt, right, 5);
write(oline, string'(" expect="));
write(oline, S2M_SIZE, right, 5);
end if;
writeline(output, oline);
end if;
active_1 := S2M_ACTIVE;
if RXVAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": char: ");
write(oline, RXDATA, right, 10);
write(oline, string'(" ("));
writeoct(oline, RXDATA, right, 3);
write(oline, string'(") dt="));
write(oline, dclk, right, 4);
irxeff := RXDATA;
irxval := '1';
if doesc = '1' then
irxeff := not RXDATA;
irxval := '1';
doesc := '0';
write(oline, string'(" eff="));
write(oline, irxeff, right, 10);
write(oline, string'(" ("));
writeoct(oline, irxeff, right, 3);
write(oline, string'(")"));
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then
doesc := '1';
irxval := '0';
write(oline, string'(" XESC seen"));
end if;
xseen := '0';
if S2M_ENAXON = '1' then
if RXDATA = c_serport_xon then
write(oline, string'(" XON seen"));
M2S_XONSEEN <= '1';
xseen := '1';
elsif RXDATA = c_serport_xoff then
write(oline, string'(" XOFF seen"));
M2S_XOFFSEEN <= '1';
xseen := '1';
end if;
end if;
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
if irxeff = irxdata then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL: expect="));
write(oline, irxdata, right, 10);
end if;
irxdata := slv(unsigned(irxdata) + 1);
bcnt := bcnt + 1;
end if;
writeline(output, oline);
dclk := 0;
end if;
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
writeline(output, oline);
end if;
dclk := dclk + 1;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
de32e22e00c156f4d211d346174570ca
| 0.487306 | 4.117298 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
clamped_beam/hAMSter_model/cbeam.vhd
| 1 | 12,612 |
--*****************************************************************************
--*****************************************************************************
-- Model: clamped /one side fixed/ beam
--
-- Author: <[email protected]>
-- Date: 19.10.2011
--
-- VHDL-AMS generated code from ANSYS for hAMSter, uMKSV units
-------------------------------------------------------------------------------
--
-- Lagrangian ports
--
-- p1 p2
-- r_ext1 ->>- o o -<<- r_ext2
-- | |
-- modal ports o-------o---------o-------o nodal ports
-- | |
-- | o------------------o |
-- fm_ext1 ->>- q1 o---o /| cbeam | o---o u1 -<<- f_ext1
-- | /o------------------o |
-- fm_ext2 ->>- q2 o---o o---o u2 -<<- f_ext2
-- | o------------------o |
-- | //////////////////// |
-- o-------o---------o-------o
-- | |
-- o o
-- input: v1_ext v2_ext=0 (ground)
--
-- electrical ports
--
-- ASCII-Schematic of the MEMS-component: cbeam
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Reference: Release 11.0 Documentation for ANSYS
-- 8.5. Sample Miniature Clamped-Clamped Beam Analysis => Clamped Beam
--
-- Beam parameters
-- B_L=100 Beam length
-- B_W=20 Beam width
-- B_T=2 Beam thickness
-- E_G=4 Electrode gap
--
-- Material properties <110> Si
-- EX=169e3 MPa, Young's modulus
-- NUXY=0.066, Poisson's ratio
-- DENS=2.329e-15 kg/um/um/um, density
-- ALPX=1e-6
-- number of basis functions = 2; 2 modes: i=1 (Dominant mode), j=0(Dominant mode), k=2(Relevant mode)
-- 2 conductors => 1 capacitance C12
-- 2 master nodes
--
-- Damping: modal quality factors, see below
--
-- Calculation of voltage displacement functions up to pull-in:
-- Linear analysis: 157 volts (stress stiffening is OFF)
-- Nonlinear analysis: 160 volts (stress stiffening is ON)
--
--
-- There are two element loads: acceleration and a uniform pressure load:
-- acel,,,9.81e12 ! acceleration in Z-direction 9.81e6 m/s**2
-- sf,all,pres,0.1 ! uniform 100 kPa pressure load
--
--
-- Modal analysis data and mode specifications:
-- # FREQUENCY RELEVANCY BOUND DISPL. SCALE CONTRIBUTION,%
-- 1 0.27544E+06 Dominant 3.3517 0.29836 95.271
-- 2 0.17337E+07 Relevant 0.84607E-01 11.819 2.4049
-- 3 0.26843E+07
-- 4 0.30116E+07 Unused
-- 5 0.48994E+07
-- 6 0.92066E+07
-- 7 0.97424E+07
-- 8 0.14856E+08
-- 9 0.15914E+08
-------------------------------------------------------------------------------
-- Euler solver:
-- time=50u; step=10n
-------------------------------------------------------------------------------
-- ID: cbeam.vhd
-- ver. 1.00 29.04.2019 cbeam.vhd
--*****************************************************************************
--*****************************************************************************
package Electromagnetic_system IS
nature electrical is real across real through electrical_ground reference;
nature translational is real across real through mechanical_ground reference;
end package Electromagnetic_system;
library ieee;
use ieee.math_real.all;
use work.electromagnetic_system.all;
entity cbeam is
generic (delay:time; el_load1, el_load2:real);
port (terminal struc1,struc2:translational;
terminal lagrange1,lagrange2:translational;
terminal master1,master2:translational;
terminal elec1,elec2:electrical);
end;
architecture behav of cbeam is
type ret_type is array(1 to 4) of real;
quantity q1 across fm1 through struc1;
quantity q2 across fm2 through struc2;
quantity p1 across r1 through lagrange1;
quantity p2 across r2 through lagrange2;
quantity u1 across f1 through master1;
quantity u2 across f2 through master2;
quantity v1 across i1 through elec1;
quantity v2 across i2 through elec2;
-------------------------------------------------------------------------------
-- model parameters from FE-simulations
constant mm_1:real:= 0.232818464746E-11; -- modal mass for mode 1 []--o
constant mm_2:real:= 0.231854244007E-11; -- modal mass for mode 2 []--o
constant f_1:real:= 0.27544E+06 ; -- frequency mode 1 ***
constant f_2:real:= 0.17337E+07 ; -- frequency mode 2 ***
-- eigenvector at master node 1
constant fi1_1:real:= 0.999999988058 ; -- eigenvector mode 1 at master node 1
constant fi1_2:real:= 0.999999776074 ; -- eigenvector mode 2 at master node 1
-- eigenvector at master node 2
constant fi2_1:real:= 0.339254165955 ; -- eigenvector mode 2 at master node 1
constant fi2_2:real:= -0.712900181001 ; -- eigenvector mode 2 at master node 2
-- acceleration in z-direction 9.8e6 m/s**2
constant el1_1:real:= -35.7003234220 ; -- element load 1 mode 1
constant el1_2:real:= 19.8834674929 ; -- element load 1 mode 2
-- uniform 1 MPa pressure load
constant el2_1:real:= 77.7939081502 ; -- element load 2 mode 1
constant el2_2:real:= -45.6034402711 ; -- element load 2 mode 2
-------
constant Qm_1:real:= 10.0; -- quality factor for mode 1, user defined
constant Qm_2:real:= 10.0; -- quality factor for mode 2, user defined
constant km_1:real:= mm_1*(2.0*3.14*f_1)**2; -- modal stiffness mode 1 o--^^^--o
constant km_2:real:= mm_2*(2.0*3.14*f_2)**2; -- modal stiffness mode 2 o--^^^--o
constant dm_1:real:=SQRT(mm_1*km_1)/Qm_1*1.0; -- modal damping constant for mode 1 o--[|--o
constant dm_2:real:=SQRT(mm_2*km_2)/Qm_2*1.0; -- modal damping constant for mode 2 o--[|--o
-------------------------------------------------------------------------------
-- the strain energy function
constant s_type102:integer:=1; -- type of fit function: Lagrange polynomial
constant s_inve102:integer:=1; -- not inverted
signal s_ord102:real_vector(1 to 3):=(4.0, 4.0, 0.0); -- order of polynomial
signal s_fak102:real_vector(1 to 4):=(0.298355752783,11.819,0.0,40.19036861); -- scaling factors
constant s_anz102:integer:= 25; -- total number of coefficients
signal s_data102:real_vector(1 to 25):= -- polynomial coefficients
(
0.226452885625E-07, -- const
0.502194834436E-14, -- Mode1
0.974597248387 , -- Mode1^2
-0.584354937591E-14, -- Mode1^3
0.674835073746E-03, -- Mode1^4
0.112014816202E-14, -- Mode2
-0.132493195796E-06, -- Mode1 *Mode2
-0.101086003850E-13, -- Mode1^2 *Mode2
0.172646020973E-03, -- Mode1^3 *Mode2
0.986580043093E-14, -- Mode1^4 *Mode2
0.245012468704E-01, -- Mode2^2
-0.381910747387E-13, -- Mode1 *Mode2^2
0.530076496003E-04, -- Mode1^2 *Mode2^2
0.437150863736E-13, -- Mode1^3 *Mode2^2
0.118922308547E-06, -- Mode1^4 *Mode2^2
-0.122397026431E-14, -- Mode2^3
0.235696025724E-05, -- Mode1 *Mode2^3
0.109962124175E-13, -- Mode1^2 *Mode2^3
0.307100846248E-08, -- Mode1^3 *Mode2^3
-0.106950600932E-13, -- Mode1^4 *Mode2^3
0.842283549353E-07, -- Mode2^4
0.339296643681E-13, -- Mode1 *Mode2^4
0.196771612043E-08, -- Mode1^2 *Mode2^4
-0.388931868309E-13, -- Mode1^3 *Mode2^4
0.956200475259E-08 -- Mode1^4 *Mode2^4
);
-------------------------------------------------------------------------------
-- the capacitance between conductor 1 and 2
constant ca12_type102:integer:=1;
constant ca12_inve102:integer:=2; -- inverted
signal ca12_ord102:real_vector(1 to 3):=(4.0, 4.0, 0.0);
signal ca12_fak102:real_vector(1 to 4):=(0.298355752783,11.819,0.0,221.195116364);
constant ca12_anz102:integer:= 25;
signal ca12_data102:real_vector(1 to 25):=
(
0.786977915624 ,
0.237757590542 ,
-0.420162902857E-01,
0.404716034822E-01,
-0.284440944423E-01,
-0.333290459426E-02,
-0.102992669984E-02,
-0.944894840532E-04,
-0.458951893598E-02,
0.460316501145E-02,
-0.413549361113E-04,
-0.167284022813E-05,
-0.253538631204E-03,
0.473015846241E-03,
-0.158699467701E-03,
-0.213429653791E-04,
-0.203875298546E-03,
0.391792780289E-03,
0.575196252076E-03,
-0.781830603931E-03,
-0.291343226820E-04,
-0.363789188765E-04,
0.319432802011E-03,
-0.110700000779E-03,
-0.185819256550E-03
);
-------------------------------------------------------------------------------
function spoly_calc(qx, qy, qz : in real:=0.0; s_type,s_inve : integer :=0;
s_ord, s_fak, s_data:real_vector) return ret_type is
constant Sx:integer:=integer(s_ord(1))+1;
constant Sy:integer:=integer(s_ord(2))+1;
constant Sz:integer:=integer(s_ord(3))+1;
variable fwx:real_vector(1 to Sx):=(others=>0.0);
variable fwy:real_vector(1 to Sy):=(others=>0.0);
variable fwz:real_vector(1 to 1):=(others=>0.0);
variable dfwx:real_vector(1 to Sx):=(others=>0.0);
variable dfwy:real_vector(1 to Sy):=(others=>0.0);
variable dfwz:real_vector(1 to 1):=(others=>0.0);
variable res_val:ret_type:=(others=>0.0);
variable fwv,dfwvx,dfwvy,dfwvz,fak2:real:=0.0;
variable Px_s,Py_s,Px,Py,Lx,Ly,Lz,ii:integer:=0;
begin
Lx:=integer(s_ord(1));
Ly:=integer(s_ord(2));
Lz:=integer(s_ord(3));
for i in 1 to Lx+1 loop
fwx(i):=qx**(i-1)*s_fak(1)**(i-1);
if i=2 then
dfwx(i):=s_fak(1)**(i-1);
end if;
if i>2 then
dfwx(i):=real(i-1)*qx**(i-2)*s_fak(1)**(i-1);
end if;
end loop;
for i in 1 to Ly+1 loop
fwy(i):=qy**(i-1)*s_fak(2)**(i-1);
if i=2 then
dfwy(i):=s_fak(2)**(i-1);
end if;
if i>2 then
dfwy(i):=real(i-1)*qy**(i-2)*s_fak(2)**(i-1);
end if;
end loop;
for i in 1 to Lz+1 loop
fwz(i):=qz**(i-1)*s_fak(3)**(i-1);
if i=2 then
dfwz(i):=s_fak(3)**(i-1);
end if;
if i>2 then
dfwz(i):=real(i-1)*qz**(i-2)*s_fak(3)**(i-1);
end if;
end loop;
if s_type=1 then -- type Lagrange polynomial
ii:=1;
for zi in 0 to Lz loop
for yi in 0 to Ly loop
for xi in 0 to Lx loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
end loop;
end loop;
end if;
if s_inve=1 then
fwv:=fwv*s_fak(4);
dfwvx:=dfwvx*s_fak(4);
dfwvy:=dfwvy*s_fak(4);
dfwvz:=dfwvz*s_fak(4);
else
fak2:=1.0/s_fak(4);
dfwvx:=-dfwvx/(fwv**2);
dfwvy:=-dfwvy/(fwv**2);
dfwvz:=-dfwvz/(fwv**2);
fwv:=1.0/fwv;
fwv:=fwv*fak2;
dfwvx:=dfwvx*fak2;
dfwvy:=dfwvy*fak2;
dfwvz:=dfwvz*fak2;
end if;
res_val:=(fwv, dfwvx, dfwvy, dfwvz);
return res_val;
end spoly_calc;
-------------------------------------------------------------------------------
signal sene_102:ret_type;
signal ca12_102:ret_type;
begin
p1:process
begin
sene_102<= spoly_calc(q1,q2,0.0,s_type102,s_inve102,s_ord102,s_fak102,s_data102);
ca12_102<= spoly_calc(q1,q2,0.0,ca12_type102,ca12_inve102,ca12_ord102,ca12_fak102,ca12_data102);
wait for delay;
end process;
break on sene_102(2),sene_102(3),sene_102(4),ca12_102(2),ca12_102(3),ca12_102(4);
-- linear mechanical model: km_i=const
--fm1==mm_1*q1'dot'dot + dm_1*q1'dot + km_1*q1 -ca12_102(2)*(v1-v2)**2/2.0 +fi1_1*p1 +fi2_1*p2 -el1_1*el_load1 -el2_1*el_load2;
--fm2==mm_2*q2'dot'dot + dm_2*q2'dot + km_2*q2 -ca12_102(3)*(v1-v2)**2/2.0 +fi1_2*p1 +fi2_2*p2 -el1_2*el_load1 -el2_2*el_load2;
-- non-linear mechanical model:
fm1==mm_1*q1'dot'dot + dm_1*q1'dot + sene_102(2) -ca12_102(2)*(v1-v2)**2/2.0 +fi1_1*p1 +fi2_1*p2 -el1_1*el_load1 -el2_1*el_load2;
fm2==mm_2*q2'dot'dot + dm_2*q2'dot + sene_102(3) -ca12_102(3)*(v1-v2)**2/2.0 +fi1_2*p1 +fi2_2*p2 -el1_2*el_load1 -el2_2*el_load2;
r1==fi1_1*q1+fi1_2*q2-u1;
r2==fi2_1*q1+fi2_2*q2-u2;
f1==-p1;
f2==-p2;
i1==+((v1-v2)*(ca12_102(2)*q1'dot+ca12_102(3)*q2'dot)+(v1'dot-v2'dot)*ca12_102(1));
i2==-((v1-v2)*(ca12_102(2)*q1'dot+ca12_102(3)*q2'dot)+(v1'dot-v2'dot)*ca12_102(1));
end;
-------------------------------------------------------------------------------
|
mit
|
8cbe1da6a4f6ab11fd1102bee4f9c5cf
| 0.536711 | 2.877481 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw13/secondb.vhd
| 1 | 974 |
Library ieee;
use ieee.std_logic_1164.all;
entity secondb is
port(
A, B, C: buffer std_logic;
CLK: in std_logic
);
end secondb;
architecture solution of secondb is
component jk
port(
J,K, CLK : IN std_logic;
Q: OUT std_logic
);
end component;
begin
jk2: jk port map(
'1', C or B, CLK, A
);
jk1: jk port map(
A and not(C), C, CLK, B
);
jk0: jk port map(
not(A) and B, A and not(B), CLK, C
);
end solution;
Library ieee;
use ieee.std_logic_1164.all;
entity jk is
port(
J,K, CLK : IN std_logic;
Q: OUT std_logic
);
end jk;
architecture impl of jk is
signal temp: std_logic;
begin
process(CLK)
begin
if rising_edge(CLK) then
if (J = '0' and K = '0') then
temp <= temp;
elsif (J = '0' and K = '1') then
temp <= '0';
elsif (J = '1' and K = '0') then
temp <= '1';
elsif (J = '1' and K = '1') then
temp <= not(temp);
end if;
end if;
end process;
Q <= temp;
end impl;
|
mit
|
28c221c07e936bd35c46730eac8e3ab3
| 0.565708 | 2.465823 | false | false | false | false |
ambikeshwar1991/nghdl
|
src/ghdlserver/Utility_Package.vhdl
| 2 | 7,046 |
-- author: Madhav P. Desai
library ieee;
use ieee.std_logic_1164.all;
package Utility_Package is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant c_word_length : integer := 32;
constant c_vhpi_max_string_length : integer := 1024;
-----------------------------------------------------------------------------
-- types
-----------------------------------------------------------------------------
subtype VhpiString is string(1 to c_vhpi_max_string_length);
-----------------------------------------------------------------------------
-- utility functions
-----------------------------------------------------------------------------
function Minimum(x,y: integer) return integer; -- returns minimum
function Pack_String_To_Vhpi_String(x: string) return VhpiString; -- converts x to null terminated string
function Pack_SLV_To_Vhpi_String(x: std_logic_vector) return VhpiString; -- converts slv x to null terminated string
function Unpack_String(x: VhpiString; lgth: integer) return std_logic_vector; -- convert null term string to slv
function To_Std_Logic(x: VhpiString) return std_logic; -- string to sl
function To_String(x: std_logic) return VhpiString; -- string to sl
function Convert_To_String(val : natural) return STRING; -- convert val to string.
function Convert_SLV_To_String(val : std_logic_vector) return STRING; -- convert val to string.
function To_Hex_Char (constant val: std_logic_vector) return character;
function Convert_SLV_To_Hex_String(val : std_logic_vector) return STRING; -- convert val to string.
end package Utility_Package;
package body Utility_Package is
-----------------------------------------------------------------------------
-- utility functions
-----------------------------------------------------------------------------
function Minimum(x,y: integer) return integer is
begin
if( x < y) then return x; else return y; end if;
end Minimum;
function Ceiling(x,y: integer) return integer is
variable ret_var : integer;
begin
assert x /= 0 report "divide by zero in ceiling function" severity failure;
ret_var := x/y;
if(ret_var*y < x) then ret_var := ret_var + 1; end if;
return(ret_var);
end Ceiling;
function Pack_String_To_Vhpi_String(x: string) return VhpiString is
alias lx: string(1 to x'length) is x;
variable strlen: integer;
variable ret_var : VhpiString;
begin
strlen := Minimum(c_vhpi_max_string_length-1,x'length);
for I in 1 to strlen loop
ret_var(I) := lx(I);
end loop;
ret_var(strlen+1) := nul;
return(ret_var);
end Pack_String_To_Vhpi_String;
function Pack_SLV_To_Vhpi_String(x: std_logic_vector) return VhpiString is
alias lx : std_logic_vector(1 to x'length) is x;
variable strlen: integer;
variable ret_var : VhpiString;
begin
strlen := Minimum(c_vhpi_max_string_length-1,x'length);
for I in 1 to strlen loop
if(lx(I) = '1') then
ret_var(I) := '1';
else
ret_var(I) := '0';
end if;
end loop;
ret_var(strlen+1) := nul;
return(ret_var);
end Pack_SLV_To_Vhpi_String;
function Unpack_String(x: VhpiString; lgth: integer) return std_logic_vector is
variable ret_var : std_logic_vector(1 to lgth);
variable strlen: integer;
begin
strlen := Minimum(c_vhpi_max_string_length-1,lgth);
for I in 1 to strlen loop
if(x(I) = '1') then
ret_var(I) := '1';
else
ret_var(I) := '0';
end if;
end loop;
return(ret_var);
end Unpack_String;
function To_Std_Logic(x: VhpiString) return std_logic is
variable s: std_logic_vector(0 downto 0);
begin
s := Unpack_String(x,1);
return(s(0));
end To_Std_Logic;
function To_String(x: std_logic) return VhpiString is
variable s: std_logic_vector(0 downto 0);
begin
s(0) := x;
return(Pack_SLV_To_Vhpi_String(s));
end To_String;
-- Thanks to: D. Calvet [email protected]
function Convert_To_String(val : NATURAL) return STRING is
variable result : STRING(10 downto 1) := (others => '0'); -- smallest natural, longest string
variable pos : NATURAL := 1;
variable tmp, digit : NATURAL;
begin
tmp := val;
loop
digit := abs(tmp MOD 10);
tmp := tmp / 10;
result(pos) := character'val(character'pos('0') + digit);
pos := pos + 1;
exit when tmp = 0;
end loop;
return result((pos-1) downto 1);
end Convert_To_String;
function Convert_SLV_To_String(val : std_logic_vector) return STRING is
alias lval: std_logic_vector(1 to val'length) is val;
variable ret_var: string( 1 to lval'length);
begin
for I in lval'range loop
if(lval(I) = '1') then
ret_var(I) := '1';
elsif (lval(I) = '0') then
ret_var(I) := '0';
else
ret_var(I) := 'X';
end if;
end loop;
return(ret_var);
end Convert_SLV_To_String;
function To_Hex_Char (constant val: std_logic_vector) return character is
alias lval: std_logic_vector(1 to val'length) is val;
variable tvar : std_logic_vector(1 to 4);
variable ret_val : character;
begin
if(lval'length >= 4) then
tvar := lval(1 to 4);
else
tvar := (others => '0');
tvar(1 to lval'length) := lval;
end if;
case tvar is
when "0000" => ret_val := '0';
when "0001" => ret_val := '1';
when "0010" => ret_val := '2';
when "0011" => ret_val := '3';
when "0100" => ret_val := '4';
when "0101" => ret_val := '5';
when "0110" => ret_val := '6';
when "0111" => ret_val := '7';
when "1000" => ret_val := '8';
when "1001" => ret_val := '9';
when "1010" => ret_val := 'a';
when "1011" => ret_val := 'b';
when "1100" => ret_val := 'c';
when "1101" => ret_val := 'd';
when "1110" => ret_val := 'e';
when "1111" => ret_val := 'f';
when others => ret_val := 'f';
end case;
return(ret_val);
end To_Hex_Char;
function Convert_SLV_To_Hex_String(val : std_logic_vector) return STRING is
alias lval: std_logic_vector(val'length downto 1) is val;
variable ret_var: string( 1 to Ceiling(lval'length,4));
variable hstr : std_logic_vector(4 downto 1);
variable I : integer;
begin
I := 0;
while I < (lval'length/4) loop
hstr := lval(4*(I+1) downto (4*I)+1);
ret_var(ret_var'length - I) := To_Hex_Char(hstr);
I := (I + 1);
end loop; -- I
hstr := (others => '0');
if(ret_var'length > (lval'length/4)) then
hstr((lval'length-((lval'length/4)*4)) downto 1) := lval(lval'length downto (4*(lval'length/4))+1);
ret_var(1) := To_Hex_Char(hstr);
end if;
return(ret_var);
end Convert_SLV_To_Hex_String;
end Utility_Package;
|
bsd-2-clause
|
c6ca306fb00d0024fb9ed2bf6cbe0ffc
| 0.549106 | 3.537149 | false | false | false | false |
os-cillation/easyfpga-soc
|
templates/two_process_entity.vhd
| 1 | 3,281 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- <NAME> (<NAME>.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Type and component definition package
-------------------------------------------------------------------------------
package <NAME>_comp is
type <NAME>_in_type is record
end record;
type <NAME>_out_type is record
end record;
component <NAME>
port (
clk : in std_logic;
rst : in std_logic;
d : in <NAME>_in_type;
q : out <NAME>_out_type
);
end component;
end package;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.<NAME>_comp.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity <NAME> is
port (
clk : in std_logic;
rst : in std_logic;
d : in <NAME>_in_type;
q : out <NAME>_out_type
);
end <NAME>;
architecture two_proc of <NAME> is
type reg_type is record
end record;
signal reg_out, reg_in : reg_type;
begin
-------------------------------------------------------------------------------
COMBINATIONAL : process(d, reg_out) -- combinational process
-------------------------------------------------------------------------------
variable tmp : reg_type;
begin
tmp := reg_out; -- default assignments
---algorithm-------------------------------------------------------------
-------------------------------------------------------------------------
reg_in <= tmp; -- drive register inputs
end process COMBINATIONAL;
-------------------------------------------------------------------------------
REGISTERS : process(clk,rst) -- sequential process
-------------------------------------------------------------------------------
begin
if (rst = '1') then
-- TODO: reg_out.* <= '0'
elsif rising_edge(clk) then
reg_out <= reg_in;
end if;
end process REGISTERS;
end two_proc;
|
gpl-3.0
|
f75e2be200fae3d6269fa99f9fc6be6f
| 0.405059 | 5.432119 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/LUT/simulation/LUT_tb_pkg.vhd
| 6 | 5,828 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE LUT_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END LUT_TB_PKG;
PACKAGE BODY LUT_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END LUT_TB_PKG;
|
gpl-2.0
|
fea15fc685b7731adeb9de3b76f43d9e
| 0.594887 | 4.486528 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/avmb/sys_conf.vhd
| 1 | 3,195 |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_mb (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.4; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2; -- ==> 80 MHz
-- constant sys_conf_memctl_read0delay : positive := 5;
-- constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
-- constant sys_conf_memctl_writedelay : positive := 5;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- constant sys_conf_bram : integer := 0; -- no bram, use cache
-- constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
-- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
constant sys_conf_bram : integer := 1; -- bram only
constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(40000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
902bd200fa253e00845ad1b06c776e5f
| 0.605634 | 3.732477 | false | false | false | false |
armandas/FPGalaxy
|
alien_generator.vhd
| 2 | 5,161 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien;
architecture generator of alien is
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 64;
constant FRAME_DELAY: integer := 50000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_y: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(24 downto 0);
signal alien_rgb, alien11_rgb, alien12_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, alive, position_in_frame,
restart)
begin
destruction <= '0';
alive_next <= alive;
if restart = '1' then
alive_next <= (others => '1');
elsif missile_arrived = '1' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien11_rgb when frame = '0' else
alien12_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_11:
entity work.alien11_rom(content)
port map(addr => addr, data => alien11_rgb);
alien_12:
entity work.alien12_rom(content)
port map(addr => addr, data => alien12_rgb);
end generator;
|
bsd-2-clause
|
48a3264044a0831e5e197069787a0bed
| 0.57547 | 3.715623 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/pdp11_decode.vhd
| 2 | 20,093 |
-- $Id: pdp11_decode.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_decode - syn
-- Description: pdp11: instruction decoder
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.6 now numeric_std clean
-- 2010-09-18 300 1.0.5 rename (adlm)box->(oalm)unit
-- 2008-11-30 174 1.0.4 BUGFIX: add updt_dstadsrc; set for MFP(I/D)
-- 2008-05-03 143 1.0.3 get fork_srcr,fork_dstr,fork_dsta assign out of if
-- 2008-04-27 139 1.0.2 BUGFIX: mtp now via do_fork_op; is_dsta logic mods
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end pdp11_decode;
architecture syn of pdp11_decode is
begin
proc_idecode: process (IREG)
alias OPCODE : slv4 is IREG(15 downto 12); -- basic opcode (upper 4 bits)
alias OPPRIM : slv3 is IREG(14 downto 12); -- basic opcode without B bit
alias OPBYTE : slbit is IREG(15); -- byte flag of basic opcode
alias OPEXT1 : slv3 is IREG(11 downto 9); -- extended opcode, part 1
alias OPEXT2 : slv3 is IREG(8 downto 6); -- extended opcode, part 2
alias OPEXT3 : slv3 is IREG(5 downto 3); -- extended opcode, part 3
alias OPEXT4 : slv3 is IREG(2 downto 0); -- extended opcode, part 4
alias SRCMODF : slv3 is IREG(11 downto 9); -- src register full mode
alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
alias SRCDEF : slbit is IREG(9); -- src register mode defered
alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
alias DSTDEF : slbit is IREG(3); -- dst register mode defered
alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
variable nstat : decode_stat_type;
variable is_srcr : slbit := '0'; -- source is read
variable is_dstr : slbit := '0'; -- destination is read
variable is_dstm : slbit := '0'; -- destination is modified
variable is_dstw : slbit := '0'; -- destination is written
variable is_srcmode0 : slbit := '0'; -- source is register mode
variable is_dstmode0notpc : slbit := '0'; -- dest. is register mode, not PC
begin
is_srcr := '0';
is_dstr := '0';
is_dstm := '0';
is_dstw := '0';
is_srcmode0 := '0';
is_dstmode0notpc := '0';
nstat.is_dstmode0 := '0';
nstat.is_srcpc := '0';
nstat.is_srcpcmode1 := '0';
nstat.is_dstpc := '0';
nstat.is_dstw_reg := '0';
nstat.is_dstw_pc := '0';
nstat.is_rmwop := '0';
nstat.is_bytop := '0';
nstat.is_res := '1';
nstat.op_rtt := '0';
nstat.op_mov := '0';
nstat.trap_vec := "000";
nstat.force_srcsp := '0';
nstat.updt_dstadsrc := '0';
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_pass;
nstat.aunit_cc1op := '0';
nstat.aunit_ccmode := IREG(8 downto 6); -- STATIC
nstat.lunit_func := (others=>'0');
nstat.munit_func := (others=>'0');
nstat.res_sel := c_dpath_res_ounit;
nstat.fork_op := (others=>'0');
nstat.fork_srcr := (others=>'0');
nstat.fork_dstr := (others=>'0');
nstat.fork_dsta := (others=>'0');
nstat.fork_opg := (others=>'0');
nstat.fork_opa := (others=>'0');
nstat.do_fork_op := '0';
nstat.do_fork_srcr := '0';
nstat.do_fork_dstr := '0';
nstat.do_fork_dsta := '0';
nstat.do_fork_opg := '0';
nstat.do_pref_dec := '0';
if SRCMODF = "000" then
is_srcmode0 := '1';
end if;
if DSTMODF = "000" then
nstat.is_dstmode0 := '1';
if DSTREG /= c_gpr_pc then
is_dstmode0notpc := '1';
end if;
end if;
if SRCREG = c_gpr_pc then
nstat.is_srcpc := '1';
if SRCMODF = "001" then
nstat.is_srcpcmode1 := '1';
end if;
end if;
if DSTREG = c_gpr_pc then
nstat.is_dstpc := '1';
end if;
if OPPRIM = "000" then
if OPBYTE='0' and OPEXT1="000" then
if OPEXT2="000" and OPEXT3="000" then -- HALT,...,RTT
nstat.is_res := '0';
case OPEXT4 is
when "000" => -- HALT
nstat.fork_op := c_fork_op_halt;
nstat.do_fork_op := '1';
when "001" => -- WAIT
nstat.fork_op := c_fork_op_wait;
nstat.do_fork_op := '1';
when "010" => -- RTI
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rtti;
nstat.do_fork_op := '1';
when "011" => -- BPT (trap to 14)
nstat.trap_vec := "011";
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
when "100" => -- IOT (trap to 20)
nstat.trap_vec := "100";
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
when "101" => -- RESET
nstat.fork_op := c_fork_op_reset;
nstat.do_fork_op := '1';
when "110" => -- RTT
nstat.op_rtt := '1';
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rtti;
nstat.do_fork_op := '1';
when others =>
nstat.is_res := '1';
end case;
end if;
if OPEXT2 = "001" then -- JMP
nstat.is_res := '0';
nstat.fork_opa := c_fork_opa_jmp;
nstat.do_fork_dsta := '1';
end if;
if OPEXT2 = "010" then
if OPEXT3 = "000" then -- RTS
nstat.is_res := '0';
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rts;
nstat.do_fork_op := '1';
end if;
if OPEXT3 = "011" then -- SPL
nstat.is_res := '0';
nstat.fork_op := c_fork_op_spl;
nstat.do_fork_op := '1';
end if;
end if;
if OPEXT2 = "010" then
if OPEXT3(2) = '1' then -- SEx/CLx
nstat.is_res := '0';
nstat.fork_op := c_fork_op_mcc;
nstat.do_fork_op := '1';
--!!!nstat.do_pref_dec := '1'; --??? ensure ireg_we ....
end if;
end if;
if OPEXT2 = "011" then -- SWAP
nstat.is_res := '0';
is_dstm := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
nstat.lunit_func := c_lunit_func_swap;
nstat.res_sel := c_dpath_res_lunit;
end if;
end if; -- OPBYTE='0' and OPEXT1="000"
if OPEXT1(2)='0' and -- BR class instructions
((OPBYTE='0' and OPEXT2(2)='1') or -- BR
(OPBYTE='0' and (OPEXT1(0)='1' or OPEXT1(1)='1')) or -- BNE,..,BLE
OPBYTE='1') then -- BPL,..,BCS
nstat.is_res := '0';
nstat.fork_op := c_fork_op_br;
nstat.do_fork_op := '1';
end if;
if OPBYTE='0' and OPEXT1="100" then -- JSR
nstat.is_res := '0';
nstat.fork_opa := c_fork_opa_jsr;
nstat.do_fork_dsta := '1';
end if;
if OPBYTE='1' and OPEXT1="100" then -- EMT, TRAP
nstat.is_res := '0';
if OPEXT2(2) = '0' then -- EMT (trap tp 30)
nstat.trap_vec := "110";
else -- TRAP (trap to 34)
nstat.trap_vec := "111";
end if;
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
end if;
if OPEXT1 = "101" then -- CLR(B),...,TST(B)
nstat.is_res := '0';
nstat.res_sel := c_dpath_res_aunit;
if OPBYTE = '1' then
nstat.is_bytop := '1';
end if;
nstat.aunit_cc1op := '1';
case OPEXT2 is
when "000" => -- CLR: 0 + 0 + 0 (0)
is_dstw := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_zero;
nstat.aunit_cimod := c_aunit_mod_zero;
when "001" => -- COM: 0 + ~DST + 0 (~dst)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_zero;
when "010" => -- INC: 0 + DST + 1 (dst+1)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_one;
when "011" => -- DEC: ~0 + DST + 0 (dst-1)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_one;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
when "100" => -- NEG: 0 + ~DST + 1 (-dst)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_one;
when "101" => -- ADC: 0 + DST + CI (dst+ci)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_pass;
when "110" => -- SBC: ~0 + DST + ~CI (dst-ci)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_one;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_inv;
when "111" => -- TST: 0 + DST + 0 (dst)
is_dstr := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
when others => null;
end case;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
end if;
if OPEXT1 = "110" then
if OPEXT2(2) = '0' then -- ROR(B),...,ASL(B)
nstat.is_res := '0';
is_dstm := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
if OPBYTE = '1' then
nstat.is_bytop := '1';
end if;
nstat.res_sel := c_dpath_res_lunit;
case OPEXT2(1 downto 0) is
when "00" => -- ROR
nstat.lunit_func := c_lunit_func_ror;
when "01" => -- ROL
nstat.lunit_func := c_lunit_func_rol;
when "10" => -- ASR
nstat.lunit_func := c_lunit_func_asr;
when "11" => -- ASL
nstat.lunit_func := c_lunit_func_asl;
when others => null;
end case;
end if;
if OPBYTE='0' and OPEXT2="100" then -- MARK
nstat.is_res := '0';
nstat.fork_op := c_fork_op_mark;
nstat.do_fork_op := '1';
end if;
if OPEXT2 = "101" then -- MFP(I/D)
nstat.is_res := '0';
nstat.force_srcsp := '1';
if DSTREG = c_gpr_sp then -- is dst reg == sp ?
nstat.updt_dstadsrc := '1'; -- ensure DSRC update in dsta flow
end if;
nstat.res_sel := c_dpath_res_ounit;
if nstat.is_dstmode0 = '1' then
nstat.fork_opa := c_fork_opa_mfp_reg;
else
nstat.fork_opa := c_fork_opa_mfp_mem;
end if;
nstat.do_fork_dsta := '1';
end if;
if OPEXT2 = "110" then -- MTP(I/D)
nstat.is_res := '0';
nstat.force_srcsp := '1';
nstat.res_sel := c_dpath_res_ounit;
nstat.fork_opa := c_fork_opa_mtp;
nstat.fork_op := c_fork_op_mtp;
nstat.do_fork_op := '1';
end if;
if OPBYTE='0' and OPEXT2="111" then -- SXT
nstat.is_res := '0';
is_dstw := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
nstat.lunit_func := c_lunit_func_sxt;
nstat.res_sel := c_dpath_res_lunit;
end if;
end if;
end if; -- OPPRIM="000"
if OPPRIM/="000" and OPPRIM/="111" then
nstat.is_res := '0';
case OPPRIM is
when "001" => -- MOV
is_srcr := '1';
is_dstw := '1';
nstat.op_mov := '1';
nstat.lunit_func := c_lunit_func_mov;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "010" => -- CMP
is_srcr := '1';
is_dstr := '1';
nstat.res_sel := c_dpath_res_aunit;
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_one;
nstat.is_bytop := OPBYTE;
when "011" => -- BIT
is_srcr := '1';
is_dstr := '1';
nstat.lunit_func := c_lunit_func_bit;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "100" => -- BIC
is_srcr := '1';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_bic;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "101" => -- BIS
is_srcr := '1';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_bis;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "110" =>
is_srcr := '1';
is_dstm := '1';
nstat.res_sel := c_dpath_res_aunit;
if OPBYTE = '0' then -- ADD
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
else -- SUB
nstat.aunit_srcmod := c_aunit_mod_inv;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_one;
end if;
when others => null;
end case;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_srcmode0 and is_dstmode0notpc;
end if;
if OPBYTE='0' and OPPRIM="111" then
case OPEXT1 is
when "000" => -- MUL
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_mul;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_mul;
nstat.do_fork_opg := '1';
when "001" => -- DIV
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_div;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_div;
nstat.do_fork_opg := '1';
when "010" => -- ASH
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_ash;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_ash;
nstat.do_fork_opg := '1';
when "011" => -- ASHC
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_ashc;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_ashc;
nstat.do_fork_opg := '1';
when "100" => -- XOR
nstat.is_res := '0';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_xor;
nstat.res_sel := c_dpath_res_lunit;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
when "111" => -- SOB: SRC + ~0 + 0 (src-1)
nstat.is_res := '0';
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_one;
nstat.aunit_cimod := c_aunit_mod_zero;
nstat.res_sel := c_dpath_res_aunit;
nstat.fork_op := c_fork_op_sob;
nstat.do_fork_op := '1';
when others => null;
end case;
end if;
if OPBYTE='1' and OPPRIM="111" then -- FPU
nstat.is_res := '1'; -- ??? FPU not yet handled
end if;
case SRCMOD is
when "00" => nstat.fork_srcr := c_fork_srcr_def;
when "01" => nstat.fork_srcr := c_fork_srcr_inc;
when "10" => nstat.fork_srcr := c_fork_srcr_dec;
when "11" => nstat.fork_srcr := c_fork_srcr_ind;
when others => null;
end case;
if is_srcr='1' and SRCMODF /="000" then
nstat.do_fork_srcr := '1';
end if;
case DSTMOD is
when "00" => nstat.fork_dstr := c_fork_dstr_def;
when "01" => nstat.fork_dstr := c_fork_dstr_inc;
when "10" => nstat.fork_dstr := c_fork_dstr_dec;
when "11" => nstat.fork_dstr := c_fork_dstr_ind;
when others => null;
end case;
if (is_dstr or is_dstm)='1' and nstat.is_dstmode0='0' then
nstat.do_fork_dstr := '1';
end if;
if is_dstw='1' and nstat.is_dstmode0='0' then
case DSTMOD is
when "00" => nstat.fork_opg := c_fork_opg_wdef;
when "01" => nstat.fork_opg := c_fork_opg_winc;
when "10" => nstat.fork_opg := c_fork_opg_wdec;
when "11" => nstat.fork_opg := c_fork_opg_wind;
when others => null;
end case;
end if;
if is_dstm='1' and nstat.is_dstmode0='0' then
nstat.is_rmwop := '1';
end if;
case DSTMOD is
when "00" => nstat.fork_dsta := c_fork_dsta_def;
when "01" => nstat.fork_dsta := c_fork_dsta_inc;
when "10" => nstat.fork_dsta := c_fork_dsta_dec;
when "11" => nstat.fork_dsta := c_fork_dsta_ind;
when others => null;
end case;
if (is_dstw or is_dstm)='1' and nstat.is_dstmode0='1' then
nstat.is_dstw_reg := '1';
if DSTREG = c_gpr_pc then
nstat.is_dstw_pc := '1'; --??? hack rename -> is_dstw_pc
end if;
end if;
STAT <= nstat;
end process proc_idecode;
end syn;
|
gpl-2.0
|
070d4f6a241dd4b3b9c06ae9b07ed9a2
| 0.473598 | 3.410796 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/tst_serloop.vhd
| 1 | 7,737 |
-- $Id: tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop - syn
-- Description: simple stand-alone tester for serport components
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-11-06 420 1.0 Initial version
-- 2011-10-14 416 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end tst_serloop;
architecture syn of tst_serloop is
type regs_type is record
rxdata : slv8; -- next rx char
txdata : slv8; -- next tx char
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
rxok_1 : slbit; -- rxok last cycle
txok_1 : slbit; -- txok last cycle
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0'), -- txokcnt
'0','0', -- rxok_1,txok_1
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI,
RXDATA, RXVAL, TXBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxhold : slbit := '1';
variable itxena : slbit := '0';
variable itxdata : slv8 := (others=>'0');
variable skipxon : slbit := '0';
function nextchar(skipxon: in slbit; data: in slv8) return slv8 is
variable inc : slv8 := (others=>'0');
begin
inc := "00000001";
if skipxon='1' and (data=c_serport_xon or data=c_serport_xoff) then
inc := "00000010";
end if;
return slv(unsigned(data)+unsigned(inc));
end function nextchar;
begin
r := R_REGS;
n := R_REGS;
irxhold := '1';
itxena := '0';
itxdata := RXDATA;
if HIO_CNTL.mode = c_mode_txblast then
itxdata := r.txdata;
end if;
skipxon := '0';
if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then
skipxon := '1';
end if;
if HIO_CNTL.enathrottle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXVAL='1' and r.rxthrottle='0' then
irxhold := '0';
if RXDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := nextchar(skipxon, RXDATA);
end if;
when c_mode_txblast =>
if TXBUSY = '0' then
itxena := '1';
n.txdata := nextchar(skipxon, r.txdata);
end if;
irxhold := '0';
if RXVAL = '1' then
n.rxuicnt := slv(unsigned(r.rxuicnt) + 1);
n.rxuidat := RXDATA;
end if;
when c_mode_loop =>
if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then
irxhold := '0';
itxena := '1';
end if;
when others => null;
end case;
if SER_MONI.abact = '1' then -- if auto bauder active
n.rxfecnt := (others=>'0'); -- reset frame error counter
else -- otherwise
if SER_MONI.rxerr = '1' then -- count rx frame errors
n.rxfecnt := slv(unsigned(r.rxfecnt) + 1);
end if;
end if;
if SER_MONI.rxovr = '1' then
n.rxoecnt := slv(unsigned(r.rxoecnt) + 1);
end if;
if RXVAL='1' and irxhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
n.rxok_1 := SER_MONI.rxok;
n.txok_1 := SER_MONI.txok;
if SER_MONI.rxok='0' and r.rxok_1='1' then
n.rxokcnt := slv(unsigned(r.rxokcnt) + 1);
end if;
if SER_MONI.txok='0' and r.txok_1='1' then
n.txokcnt := slv(unsigned(r.txokcnt) + 1);
end if;
N_REGS <= n;
RXHOLD <= irxhold;
TXENA <= itxena;
TXDATA <= itxdata;
HIO_STAT.rxfecnt <= r.rxfecnt;
HIO_STAT.rxoecnt <= r.rxoecnt;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.rxuicnt <= r.rxuicnt;
HIO_STAT.rxuidat <= r.rxuidat;
HIO_STAT.rxokcnt <= r.rxokcnt;
HIO_STAT.txokcnt <= r.txokcnt;
end process proc_next;
end syn;
|
gpl-2.0
|
21e5994329aba8eceafec6fb7cda4b1e
| 0.503425 | 3.963627 | false | false | false | false |
willprice/build-a-comp-vhdl-modules
|
base/Register.vhd
| 1 | 686 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Reg is
port(
-- Control in "DCBA":
-- A: Clock
-- B: Reset
-- C: Enable
control_in : in unsigned(3 downto 0) := "0101";
control_out : out unsigned(3 downto 0);
data_in : in unsigned(3 downto 0) := "0000";
data_out : out unsigned(3 downto 0)
);
end entity Reg;
architecture Behavioural of Reg is
signal clock, enable : std_logic;
begin
control_out <= control_in;
clock <= control_in(0);
enable <= control_in(2);
process(clock, enable, data_in) is
begin
if (clock = '1' and enable = '1') then
data_out <= data_in;
end if;
end process;
end architecture Behavioural;
|
mit
|
649afd852a01e67747c43a6b74c0a3e5
| 0.645773 | 2.823045 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd
| 1 | 11,877 |
-- $Id: tb_nx_cram_memctl.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nx_cram_memctl - sim
-- Description: Test bench for nx_cram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- bplib/micron/mt45w8mw16b
-- tbd_nx_cram_memctl [UUT, abstact]
--
-- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as)
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl
-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl
-- 2010-05-23 293 1.0 Initial version (derived from tb_s3_sram_memctl)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_nx_cram_memctl is
end tb_nx_cram_memctl;
architecture sim of tb_nx_cram_memctl is
component tbd_nx_cram_memctl is -- CRAM driver (abstract) [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv22 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slbit := '0';
signal O_MEM_BE_N : slv2 := (others=>'0');
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADV_N : slbit := '0';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'0');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv22 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv22 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv22 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 7.5 ns; -- compatible ucf for
constant c2out_time : time := 12.0 ns; -- tbd_nx_cram_memctl_as
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
UUT : tbd_nx_cram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_nx_cram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv22 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 7, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
wait for clock_period;
REQ <= '0';
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 7, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
wait for clock_period;
REQ <= '0';
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" be="));
write(oline, not O_MEM_BE_N, right, 4);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 6, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 4, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
|
gpl-2.0
|
e56b3c6638542973b25b0d3a1e868b2e
| 0.496422 | 3.53377 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/algorithms/clark_nfa/vhdl/clark_nfa.vhd
| 1 | 2,919 |
-- ----------------------------------------------------------------------------
-- Entity for implementation of Clark NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity CLARK_NFA is
generic(
DATA_WIDTH : integer := %$%;
RULES : integer := %$%
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
DATA : in std_logic_vector(DATA_WIDTH - 1 downto 0);
SOF : in std_logic;
EOF : in std_logic;
SRC_RDY : in std_logic;
DST_RDY : out std_logic;
-- output data interface
BITMAP : out std_logic_vector(RULES - 1 downto 0);
VLD : out std_logic;
ACK : in std_logic
);
end entity CLARK_NFA;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of CLARK_NFA is
signal local_reset : std_logic;
signal local_reset_fsm : std_logic;
signal we : std_logic;
-- signal rdy : std_logic;
-- signal vld_internal : std_logic;
-- signal set : std_logic;
%$%
begin
local_reset <= RESET or local_reset_fsm;
ctrl_fsm: entity work.CONTROL_FSM
port map(
CLK => CLK,
RESET => RESET,
-- input interface
EOF => EOF,
SRC_RDY => SRC_RDY,
DST_RDY => DST_RDY,
-- output interface
WE => we,
LOCAL_RESET => local_reset_fsm,
-- inner interface
VLD => VLD,
ACK => ACK
);
-- we <= SRC_RDY and rdy;
-- DST_RDY <= rdy;
-- VLD <= vld_internal;
-- set <= SRC_RDY and EOF and rdy;
-- rdy <= not vld_internal;
--
-- end_reg: process(CLK)
-- begin
-- if (CLK'event and CLK = '1') then
-- if (local_reset = '1') then
-- vld_internal <= '0';
-- else
-- if set = '1' then
-- vld_internal <= '1';
-- end if;
-- end if;
-- end if;
-- end process end_reg;
%$%
final_bitmap_u: entity work.FINAL_BITMAP
generic map(
DATA_WIDTH => RULES
)
port map(
CLK => CLK,
RESET => local_reset,
-- input data interface
SET => bitmap_in,
-- output data interface
BITMAP => BITMAP
);
end architecture full;
|
gpl-2.0
|
326dd2fee2f4cc9191d94927648b5498
| 0.398082 | 4.376312 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/xlib/dcm_sfs_unisim_s3.vhd
| 2 | 2,911 |
-- $Id: dcm_sfs_unisim_s3.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: dcm_sfs - syn
-- Description: DCM for simple frequency synthesis; SPARTAN-3 version
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.0.3 rename dcm_sp_sfs -> dcm_sfs, SPARTAN-3 version
-- 2011-11-10 423 1.0.2 add FAMILY generic, SPARTAN-3 support
-- 2010-11-12 338 1.0.1 drop SB_CLK generic; allow DIV=1,MUL=1 without DCM
-- 2010-11-07 337 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
architecture syn of dcm_sfs is
begin
assert (CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1) or CLKFX_MULTIPLY>=2
report "assert((FX_DIV=1 and FX_MULT)=1 or FX_MULT>=2"
severity failure;
DCM0: if CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate DCM0;
DCM1: if CLKFX_MULTIPLY>=2 generate
DCM : dcm
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => CLKFX_DIVIDE,
CLKFX_MULTIPLY => CLKFX_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE")
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end generate DCM1;
end syn;
|
gpl-2.0
|
9516057808343c19d6bba97f4e30c532
| 0.585022 | 3.82021 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/memlib/fifo_1c_dram.vhd
| 2 | 3,081 |
-- $Id: fifo_1c_dram.vhd 421 2011-11-07 21:23:50Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fifo_1c_dram - syn
-- Description: FIFO, single clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: fifo_1c_dram_raw
--
-- Test bench: tb/tb_fifo_1c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-06-06 49 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m Flop clock(xst est.)
-- 4 16 31 32 22 153MHz ( 16 words)
-- 5 16 49 64 23 120MHz ( 32 words)
-- 6 16 70 128 23 120MHz ( 64 words)
-- 7 16 111 256 30 120MHz (128 words)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_1c_dram is -- fifo, 1 clock, dram based
generic (
AWIDTH : positive := 7; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZE : out slv(AWIDTH downto 0) -- number of used slots
);
end fifo_1c_dram;
architecture syn of fifo_1c_dram is
signal WE : slbit := '0';
signal RE : slbit := '0';
signal SIZE_L : slv(AWIDTH-1 downto 0) := (others=>'0');
signal EMPTY : slbit := '0';
signal FULL : slbit := '0';
begin
FIFO : fifo_1c_dram_raw
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
RESET => RESET,
WE => WE,
RE => RE,
DI => DI,
DO => DO,
SIZE => SIZE_L,
EMPTY => EMPTY,
FULL => FULL
);
WE <= ENA and (not FULL);
RE <= (not EMPTY) and (not HOLD);
BUSY <= FULL;
VAL <= not EMPTY;
SIZE <= FULL & SIZE_L;
end syn;
|
gpl-2.0
|
19fc6f2d4b1fe51d42f802676c3cecce
| 0.534242 | 3.654804 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/MUX_tb.vhd
| 1 | 2,288 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:18:38 09/28/2017
-- Design Name:
-- Module Name: C:/Users/utp/Desktop/TEMPORAL/ALU/MUX_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MUX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MUX_tb IS
END MUX_tb;
ARCHITECTURE behavior OF MUX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm13 : IN std_logic_vector(31 downto 0);
i : IN std_logic;
Oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal SEUimm13 : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
--Outputs
signal Oper2 : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX PORT MAP (
Crs2 => Crs2,
SEUimm13 => SEUimm13,
i => i,
Oper2 => Oper2
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Crs2 <= "00000000000000001110000000000111";
SEUimm13 <= "00000000000000000000111010000111";
i <= '1';
-- insert stimulus here
wait;
end process;
END;
|
mit
|
6a64fed084c84dffbbd3f4d9f4c3b2ff
| 0.591783 | 3.986063 | false | true | false | false |
gtarciso/INE5406
|
dist_gray.vhd
| 1 | 1,096 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity graycode_dist is
generic(width: integer);
port(
inpt0: in std_logic_vector(width-1 downto 0);
inpt1: in std_logic_vector(width-1 downto 0);
outp: out std_logic_vector(width-1 downto 0)
);
end entity;
architecture dist of graycode_dist is
signal aux0: std_logic_vector(width-1 downto 0);
signal aux1: std_logic_vector(width-1 downto 0);
signal zero: std_logic_vector(width-1 downto 0);
signal max: std_logic_vector(width-1 downto 0);
begin
zero <= (others => '0');
max <= (others => '1');
aux0(width-1) <= inpt0(width-1);
gtb0: for i in width-2 downto 0 generate
aux0(i) <= inpt0(i) xor aux0(i+1);
end generate;
aux1(width-1) <= inpt1(width-1);
gbt1: for i in width-2 downto 0 generate
aux1(i) <= inpt1(i) xor aux1(i+1);
end generate;
outp <= std_logic_vector(unsigned(aux0) - unsigned(aux1)) when aux0 > aux1 else
std_logic_vector(unsigned(aux1) - unsigned(aux0)) when aux0 < aux1 else
zero;
end architecture;
|
cc0-1.0
|
e4b3018ff3185152d55899fd7d869eab
| 0.646898 | 3.019284 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/serport_1clock.vhd
| 1 | 7,756 |
-- $Id: serport_1clock.vhd 438 2011-12-11 23:40:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_1clock - syn
-- Description: serial port: serial port module, 1 clock domain
--
-- Dependencies: serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_1c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-23 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
use work.memlib.all;
entity serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end serport_1clock;
architecture syn of serport_1clock is
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV
);
RESET_INT <= RESET or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXFIFO_SIZE
);
TXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => open
);
-- receive back preasure
-- on if fifo more than 3/4 full
-- off if fifo less than 1/2 full
proc_rxok: process (CLK)
constant rxsize_rxok_off : slv3 := "011";
constant rxsize_rxok_on : slv3 := "010";
variable rxsize_msb : slv3 := "000";
begin
if rising_edge(CLK) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2);
if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
MONI.rxerr <= RXERR;
MONI.rxovr <= RXOVR;
MONI.rxact <= RXACT;
MONI.txact <= UART_TXBUSY;
MONI.abact <= ABACT;
MONI.abdone <= ABDONE;
MONI.rxok <= RXOK;
MONI.txok <= TXOK;
proc_abclkdiv: process (ABCLKDIV)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV;
end process proc_abclkdiv;
end syn;
|
gpl-2.0
|
1e46fc03aa28ba0e0fde90ba694b4584
| 0.542677 | 3.78157 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_1/tb_noekeon.vhd
| 1 | 5,032 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon IS
END tb_noekeon;
ARCHITECTURE behavior OF tb_noekeon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
wait for clk_period*32;-- + clk_period/2;
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
-- wait for clk_period + clk_period/2;
-- rst <= '1';
-- enc <= '1';
--
-- a_0_in <= X"e2f687e0";
-- a_1_in <= X"7b75660f";
-- a_2_in <= X"fc372233";
-- a_3_in <= X"bc47532c";
--
-- k_0_in <= X"b1656851";
-- k_1_in <= X"699e29fa";
-- k_2_in <= X"24b70148";
-- k_3_in <= X"503d2dfc";
--
-- wait for clk_period;
-- rst <= '0';
--
-- wait for clk_period*15 + clk_period/2;
--
-- assert a_0_out = X"2a78421b"
-- report "DECRYPT ERROR (a_0)" severity FAILURE;
--
-- assert a_1_out = X"87c7d092"
-- report "DECRYPT ERROR (a_1)" severity FAILURE;
--
-- assert a_2_out = X"4f26113f"
-- report "DECRYPT ERROR (a_2)" severity FAILURE;
--
-- assert a_3_out = X"1d1349b2"
-- report "DECRYPT ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
|
gpl-3.0
|
8f9b9ca824f39e5c318922cd3781388d
| 0.553657 | 2.849377 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/can_wrapper/can.vhd
| 1 | 5,000 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- C A N E A S Y C O R E
-- (can.vhd)
--
-- Structural
--
-- Adapts the verilog can module to vhdl and the wbs/wbm types
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
ENTITY can is
-------------------------------------------------------------------------------
port (
-- WISHBONE interface (with clock input)
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- CAN bus interface
can_tx_out : out std_logic;
can_rx_in : in std_logic
);
end can;
-------------------------------------------------------------------------------
ARCHITECTURE mixed of can is
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
COMPONENT can_top is
-- this component is the link to the verilog module.
-- here, the signal names from can_top.v are used
-------------------------------------------------------------------------------
port (
-- WISHBONE interface
wb_clk_i : in std_logic; -- wishbone clock
wb_rst_i : in std_logic; -- reset (asynchronous active high)
wb_cyc_i : in std_logic; -- cycle
wb_stb_i : in std_logic; -- strobe
wb_adr_i : in std_logic_vector(7 downto 0); -- address
wb_we_i : in std_logic; -- write enable
wb_dat_i : in std_logic_vector(7 downto 0); -- data input
wb_dat_o : out std_logic_vector(7 downto 0); -- data output
wb_ack_o : out std_logic; -- bus termination
-- Signals that will also be connected to wishbone
irq_on : out std_logic; -- interrupt output
clk_i : in std_logic; -- "normal" clock input
-- CAN bus interface
bus_off_on : out std_logic; -- direction output. '0' when receiving
rx_i : in std_logic; -- receive input
tx_o : out std_logic -- transmit output
);
END COMPONENT;
signal reset_s : std_logic;
signal initial_reset_s : std_logic; -- '1' at the beginning, '0'
-- after 15 clock cycles
signal irq_n_s : std_logic; -- inverted irq signal
-------------------------------------------------------------------------------
begin -- architecture mixed
-------------------------------------------------------------------------------
-- both wishbone and initial reset signals will work
reset_s <= wbs_in.rst OR initial_reset_s;
-- make irq signal active-high
wbs_out.irq <= not irq_n_s;
-------------------------------------------------------------------------------
CAN_CORE : can_top
-------------------------------------------------------------------------------
port map (
-- "normal" clock is also wishbone clock
clk_i => wbs_in.clk,
-- WISHBONE interface
wb_clk_i => wbs_in.clk,
wb_rst_i => reset_s,
wb_cyc_i => wbs_in.cyc,
wb_stb_i => wbs_in.stb,
wb_adr_i => wbs_in.adr,
wb_we_i => wbs_in.we,
wb_dat_i => wbs_in.dat,
wb_dat_o => wbs_out.dat,
wb_ack_o => wbs_out.ack,
irq_on => irq_n_s,
-- CAN bus interface
rx_i => can_rx_in,
tx_o => can_tx_out
);
-------------------------------------------------------------------------------
INITIAL_RESET : process (wbs_in.clk)
-------------------------------------------------------------------------------
variable cnt : integer range 0 to 15 := 0;
begin
if (rising_edge(wbs_in.clk)) then
if (cnt < 15) then
cnt := cnt + 1;
initial_reset_s <= '1';
else
initial_reset_s <= '0';
end if;
end if;
end process INITIAL_RESET;
end mixed;
|
gpl-3.0
|
5f816c3ba771416d90bcc5db2a3b77a5
| 0.437 | 4.464286 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/gamma.vhd
| 5 | 2,501 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gamma is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end gamma;
architecture Behavioral of gamma is
signal a_0_tmp_s : std_logic_vector(31 downto 0);
signal a_1_tmp_s : std_logic_vector(31 downto 0);
signal a_2_tmp_s : std_logic_vector(31 downto 0);
signal a_3_tmp_s : std_logic_vector(31 downto 0);
signal a_1_1_tmp_s : std_logic_vector(31 downto 0);
signal a_0_1_tmp_s : std_logic_vector(31 downto 0);
signal a_0_2_tmp_s : std_logic_vector(31 downto 0);
begin
--Gamma(a){
-- a[1] ^= ~a[3]&~a[2];
-- a[0] ^= a[2]& a[1];
-- tmp = a[3];
-- a[3] = a[0];
-- a[0] = tmp;
-- a[2] ^= a[0]^a[1]^a[3];
-- a[1] ^= ~a[3]&~a[2];
-- a[0] ^= a[2]& a[1];
--}
a_1_tmp_s <= a_1_in xor (not(a_3_in) and not(a_2_in)); -- a[1] ^= ~a[3]&~a[2];
a_0_tmp_s <= a_0_in xor (a_2_in and a_1_tmp_s); -- a[2]& a[1];
a_0_1_tmp_s <= a_3_in; -- a[0] = a[3];
a_3_tmp_s <= a_0_tmp_s; -- a[3] = a[0];
a_2_tmp_s <= a_0_1_tmp_s xor a_1_tmp_s xor a_2_in xor a_3_tmp_s; -- a[2] ^= a[0]^a[1]^a[3];
a_1_1_tmp_s <= a_1_tmp_s xor (not(a_3_tmp_s) and not(a_2_tmp_s)); -- a[1] ^= ~a[3]&~a[2];
a_0_2_tmp_s <= a_0_1_tmp_s xor (a_2_tmp_s and a_1_1_tmp_s); -- a[0] ^= a[2]& a[1];
a_3_out <= a_3_tmp_s;
a_2_out <= a_2_tmp_s;
a_1_out <= a_1_1_tmp_s;
a_0_out <= a_0_2_tmp_s;
end Behavioral;
|
gpl-3.0
|
6f6cd57764eb2e9beb352526c480e0db
| 0.57377 | 2.350564 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/vhdl/control_fsm.vhd
| 1 | 3,160 |
-- ----------------------------------------------------------------------------
-- Pattern match control FSM
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity CONTROL_FSM is
port(
CLK : in std_logic;
RESET : in std_logic;
-- input interface
EOF : in std_logic;
SRC_RDY : in std_logic;
DST_RDY : out std_logic;
-- output interface
WE : out std_logic;
LOCAL_RESET : out std_logic;
-- inner interface
VLD : out std_logic;
ACK : in std_logic
);
end entity CONTROL_FSM;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture CONTROL_FSM_ARCH of CONTROL_FSM is
type tstates is (READY, FINISH, VALID, PREPARE);
signal current_state : tstates;
signal next_state : tstates;
begin
-- FSM state register
state_register: process (RESET, CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '1' then
current_state <= READY;
else
current_state <= next_state;
end if;
end if;
end process state_register;
-- transitions in FSM
transitions_FSM: process (current_state, EOF, SRC_RDY, ACK)
begin
next_state <= current_state;
case current_state is
when READY =>
if (EOF = '1' and SRC_RDY = '1') then
next_state <= FINISH;
end if;
when FINISH =>
next_state <= VALID;
when VALID =>
if (ACK = '1') then
next_state <= PREPARE;
end if;
when PREPARE =>
next_state <= READY;
when others =>
end case;
end process;
-- outputs of FSM
outputs_FSM: process (current_state, EOF, SRC_RDY, ACK)
begin
case current_state is
when READY =>
DST_RDY <= '1';
VLD <= '0';
LOCAL_RESET <= '0';
WE <= SRC_RDY;
when FINISH =>
DST_RDY <= '0';
VLD <= '0';
LOCAL_RESET <= '0';
WE <= '0';
when VALID =>
DST_RDY <= '0';
VLD <= '1';
LOCAL_RESET <= '0';
WE <= '0';
when PREPARE =>
DST_RDY <= '0';
VLD <= '0';
LOCAL_RESET <= '1';
WE <= '0';
when others =>
end case;
end process;
end architecture CONTROL_FSM_ARCH;
|
gpl-2.0
|
8c9622c2766ab1f5442ac5398a973419
| 0.383544 | 4.945227 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/psr_mod.vhd
| 1 | 1,486 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR_Modifier is
Port ( AluResult : in STD_LOGIC_VECTOR (31 downto 0);
OP1 : in STD_LOGIC;
OP2 : in STD_LOGIC;
AluOp : in STD_LOGIC_VECTOR (5 downto 0);
NZVC : out STD_LOGIC_VECTOR (3 downto 0));
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(AluResult,OP1,OP2,AluOp)
begin
if(aluOp = "000001" or AluOp = "000011")then--ADDCC ADDXCC
NZVC(3) <= AluResult(31);
if(AluResult = X"00000000")then
NZVC(2) <= '1';
else
NZVC(2) <= '0';
end if;
NZVC(1) <= (OP1 and OP2 and (not AluResult(31))) or ((OP1) and (not OP2) and AluResult(31));
NZVC(0) <= (OP1 and OP2) or ((not AluResult(31)) and (OP1 or OP2));
else
if(AluOp = "000101")then--SUBCC
NZVC(3) <= AluResult(31);
if(AluResult = X"00000000")then
NZVC(2) <= '1';
else
NZVC(2) <= '0';
end if;
NZVC(1) <= ((OP1 and (not OP2) and (not AluResult(31))) or ((not OP1) and OP2 and AluResult(31)));
NZVC(0) <= ((not OP1) and OP2) or (AluResult(31) and ((not OP1) or OP2));
else
if(AluOp = "000101" or AluOp = "000111" or AluOp = "001001" or AluOp = "001011" or AluOp = "001101" or AluOp = "001111")then
NZVC(3) <= AluResult(31);
if(AluResult = X"00000000")then
NZVC(2) <= '1';
else
NZVC(2) <= '0';
end if;
NZVC(1) <= '0';
NZVC(0) <= '0';
else
nzvc <= "1000";
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
f4ce85aa5cc218f8a8730700b8a5c63d
| 0.582773 | 2.746765 | false | false | false | false |
AdanDuM/INE5406-SD
|
regNbits.vhd
| 1 | 554 |
library IEEE;
use IEEE.std_logic_1164.all;
-- Alunos: Adan Pereira Gomes e Wesley Mayk Gama Luz
entity regNbits is
generic (N: positive := 5);
port (
clock, reset, enable: in std_logic;
data: in std_logic_vector((N - 1) downto 0);
Q: out std_logic_vector((N - 1) downto 0)
);
end entity;
architecture circuito of regNbits is
begin
REG : process (clock, reset)
begin
if reset = '0' then
Q <= (others => '0');
elsif rising_edge(clock) then
if enable = '1' then
Q <= data;
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
48ae576d983974dec8e80b2374d69521
| 0.649819 | 2.77 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/receive_frame_buffer_tb.vhd
| 1 | 4,757 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity receive_frame_buffer_tb is
end receive_frame_buffer_tb;
architecture write_sequence of receive_frame_buffer_tb is
constant CLK_PERIOD : time := 10 ns;
constant UUT_WORD_COUNT_MAX : natural := 11;
constant UUT_WIDTH : natural := 8;
signal clk, clr, store : std_logic;
signal complete, full : std_logic;
signal word : std_logic_vector(UUT_WIDTH -1 downto 0);
signal frame : std_logic_vector(UUT_WORD_COUNT_MAX*UUT_WIDTH -1 downto 0);
procedure clear (signal clr : out std_logic;
signal store : out std_logic
) is
begin
clr <= '1';
store <= '1';
wait for CLK_PERIOD;
end clear;
procedure send_word (constant word_arg : in std_logic_vector(UUT_WIDTH -1 downto 0);
signal word : out std_logic_vector(UUT_WIDTH -1 downto 0);
signal clr : out std_logic;
signal store : out std_logic
) is
begin
clr <= '0';
store <= '1';
word <= word_arg;
wait for CLK_PERIOD;
end send_word;
begin
--**************************************
-- instantiation of unit under test
--**************************************
UUT : entity work.receive_frame_buffer
generic map (
WIDTH => UUT_WIDTH ,
WORD_COUNT_MAX => UUT_WORD_COUNT_MAX
) port map (
clk_i => clk,
clear_i => clr,
store_i => store,
frame_complete_o => complete,
full_o => full,
word_i => word,
frame_o => frame
);
--*****************************
-- clock generator process
--*****************************
CLOCK_GEN_PROC : process is
begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process CLOCK_GEN_PROC;
--*******************************
-- stimuli generator process
--*******************************
STIMULI_GEN_PROC : process is
begin
-- hold in reset for 100 ns
clr <= '1';
store <= '0';
word <= x"00";
wait for 100 ns;
--******************
-- send MCU_SEL
--******************
assert false report "will now send MCU_SEL" severity note;
send_word(word_arg => x"8A", word => word, clr => clr, store => store);
send_word(word_arg => x"55", word => word, clr => clr, store => store);
clear(clr => clr, store => store);
--**********************
-- send REGISTER_WR
--**********************
assert false report "will now send REGISTER_WR" severity note;
send_word(word_arg => x"8A", word => word, clr => clr, store => store);
send_word(word_arg => x"66", word => word, clr => clr, store => store);
-- data
send_word(word_arg => x"00", word => word, clr => clr, store => store);
send_word(word_arg => x"11", word => word, clr => clr, store => store);
send_word(word_arg => x"22", word => word, clr => clr, store => store);
send_word(word_arg => x"33", word => word, clr => clr, store => store);
-- address
send_word(word_arg => x"44", word => word, clr => clr, store => store);
send_word(word_arg => x"AA", word => word, clr => clr, store => store);
send_word(word_arg => x"BB", word => word, clr => clr, store => store);
send_word(word_arg => x"CC", word => word, clr => clr, store => store);
-- parity (correct)
send_word(word_arg => x"99", word => word, clr => clr, store => store);
-- clear
clear(clr => clr, store => store);
wait; -- forever
end process STIMULI_GEN_PROC;
end write_sequence;
|
gpl-3.0
|
83fcc9d088bd6ed6df16dec7f5cc1000
| 0.502838 | 4.07976 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
miscellaneous/f_pulse.vhd
| 2 | 1,423 |
-------------------------------------------------------------------------------
-- Model: pulse force source
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
-- Date: 06.01.2012
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: f_pulse.vhd
-- ver. 1.0
-- status: 1T triangular pulse OK
-------------------------------------------------------------------------------
-- pulse parameters:
-- VL low
-- VH high
-- TD delay time
-- TR rise time
-- TF fall time
-- TW pulse width
-- PER period
--
-------------------------------------------------------------------------------
library ieee;
use work.electromagnetic_system.all;
use work.all;
use ieee.math_real.all;
entity f_pulse is
generic (dc_value,ac_value,period:real); -- generic parameters
port (terminal p,n:translational); -- interface ports
end entity f_pulse;
architecture basic of f_pulse is
quantity u across f through p to n;
begin
if now <= period/2.0 use
f == dc_value - ac_value + ( (ac_value*2.0)/(period/2.0) ) * now;
end use;
if now > period/2.0 and now <= period use
f == dc_value + ac_value*1.0 - ( (ac_value*2.0)/(period/2.0) ) * (now - period/2.0);
end use;
if now > period use
f == 0.0;
end use;
end architecture basic;
-------------------------------------------------------------------------------
|
mit
|
6df8d217c56ff822e4b9e9ab95fc387d
| 0.470134 | 3.941828 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/s3board/s3_sram_dummy.vhd
| 2 | 2,046 |
-- $Id: s3_sram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s3_sram_dummy - syn
-- Description: s3board: SRAM protection dummy
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-04-17 278 1.0.2 renamed from sram_dummy
-- 2007-12-09 101 1.0.1 use _N for active low
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity s3_sram_dummy is -- SRAM protection dummy
port (
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end s3_sram_dummy;
architecture syn of s3_sram_dummy is
begin
O_MEM_CE_N <= "11"; -- disable sram chips
O_MEM_BE_N <= "1111";
O_MEM_WE_N <= '1';
O_MEM_OE_N <= '1';
O_MEM_ADDR <= (others=>'0');
IO_MEM_DATA <= (others=>'0');
end syn;
|
gpl-2.0
|
4d8dbcfbddd0eafa56f64e78cb7a4fef
| 0.569892 | 3.381818 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/RF_tb.vhd
| 3 | 1,328 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
COMPONENT RF
PORT(
Rs1 : IN std_logic_vector(4 downto 0);
Rs2 : IN std_logic_vector(4 downto 0);
Rd : IN std_logic_vector(4 downto 0);
Rst : IN std_logic;
Dwr : IN std_logic_vector(31 downto 0);
ORs1 : OUT std_logic_vector(31 downto 0);
ORs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal Rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal Rd : std_logic_vector(4 downto 0) := (others => '0');
signal Rst : std_logic := '0';
signal Dwr : std_logic_vector(31 downto 0) := (others => '0');
signal ORs1 : std_logic_vector(31 downto 0);
signal ORs2 : std_logic_vector(31 downto 0);
BEGIN
uut: RF PORT MAP (
Rs1 => Rs1,
Rs2 => Rs2,
Rd => Rd,
Rst => Rst,
Dwr => Dwr,
ORs1 => ORs1,
ORs2 => ORs2
);
stim_proc: process
begin
Dwr <= "00000000000000000000000000001000";
Rd <= "00011";
rs1 <= "00011";
rs2 <= "00010";
wait for 30 ns;
rs1 <= "10000";
rs2 <= "10001";
wait for 30 ns;
end process;
END;
|
mit
|
97b431aa028c25b91890e856ad86368b
| 0.542169 | 3.223301 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_1/noekeon.vhd
| 1 | 7,924 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is an iterative implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
architecture Behavioral of noekeon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(271 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal rc_in_s : std_logic_vector(271 downto 0);
begin
-- rc_in_s <= X"80 1b 36 6c d8 ab 4d 9a 2f 5e bc 63 c6 97 35 6a d4";
rc_in_s <= X"80801b1b36366c6cd8d8abab4d4d9a9a2f2f5e5ebcbc6363c6c6979735356a6ad4d4";
-- 000000000000000000";
--RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
RC_SHR_0: rc_shr port map (clk, rst, rc_in_s, rc_s);
rc_ext_s <= X"000000" & rc_s;
ROUND_F_0 : round_f port map (clk,
rst,
enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
|
gpl-3.0
|
8e1b689da26bc6591672985af184dd8a
| 0.585563 | 2.557779 | false | false | false | false |
gtarciso/INE5406
|
decodificador2x4.vhd
| 1 | 635 |
library ieee;
use ieee.std_logic_1164.all;
entity decodificador2x4 is
port(
inpt: in std_logic_vector(1 downto 0);
enable: in std_logic;
outp: out std_logic_vector(3 downto 0)
);
end decodificador2x4;
architecture decoder of decodificador2x4 is
begin
process(inpt, enable)
begin
if enable='1' then
case inpt is
when "00" =>
outp <= "0001";
when "01" =>
outp <= "0010";
when "10" =>
outp <= "0100";
when others =>
outp <= "1000";
end case;
else
outp <= "0000";
end if;
end process;
end decoder;
|
cc0-1.0
|
a0ba1f68932272f841279d0f79f37ca0
| 0.544882 | 3.413978 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/tst_serlooplib.vhd
| 1 | 4,993 |
-- $Id: tst_serlooplib.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: tst_serlooplib
-- Description: Definitions for tst_serloop records and helpers
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-10-14 416 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.serport.all;
package tst_serlooplib is
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
type hio_cntl_type is record -- humanio controls
mode : slv2; -- mode (idle,(tx|tx)blast,loop)
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
end record hio_cntl_type;
constant hio_cntl_init : hio_cntl_type := (
c_mode_idle, -- mode
'0','0','0','0' -- enaxon,enaesc,enathrottle,enaftdi
);
type hio_stat_type is record -- humanio status
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
end record hio_stat_type;
constant hio_stat_init : hio_stat_type := (
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0') -- txokcnt
);
-- -------------------------------------
component tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end component;
component tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to display by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end component;
end package tst_serlooplib;
|
gpl-2.0
|
c1b0615959431fee668d34bde40545be
| 0.512918 | 4.406884 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/delayLineBRAM/example_design/delayLineBRAM_prod.vhd
| 2 | 10,119 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 17
-- C_READ_WIDTH_A : 17
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 17
-- C_READ_WIDTH_B : 17
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY delayLineBRAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END delayLineBRAM_prod;
ARCHITECTURE xilinx OF delayLineBRAM_prod IS
COMPONENT delayLineBRAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : delayLineBRAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-2.0
|
ce89a3926d62a835d323be15e2ced9af
| 0.495306 | 3.857796 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/tb_round_f.vhd
| 3 | 4,349 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enc : std_logic := '0';
signal rst : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
clk => clk,
rst => rst,
enc => enc,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period + clk_period/2;
rst <= '1';
wait for clk_period;
rst <= '0';
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
wait for clk_period;
-- assert a_0_out = X"febb00d0"
-- report "ROUND ERROR (a_0)" severity FAILURE;
--
-- assert a_1_out = X"074ee42e"
-- report "ROUND ERROR (a_1)" severity FAILURE;
--
-- assert a_2_out = X"dde647ab"
-- report "ROUND ERROR (a_2)" severity FAILURE;
--
-- assert a_3_out = X"3207ef78"
-- report "ROUND ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
|
gpl-3.0
|
5aa193a9bf159b35852eb46a65d79185
| 0.561278 | 2.926649 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/CU.vhd
| 1 | 5,639 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CU is
Port ( OP : in STD_LOGIC_VECTOR (1 downto 0);
OP3 : in STD_LOGIC_VECTOR (5 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
Cond : in STD_LOGIC_VECTOR (3 downto 0);
wren : out STD_LOGIC;
PCsource : out STD_LOGIC_VECTOR (1 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0);
RdEnMem : out STD_LOGIC;
WrEnMem : out STD_LOGIC;
RFsource : out STD_LOGIC_VECTOR (1 downto 0);
RFdest : out STD_LOGIC
);
end CU;
architecture Behavioral of CU is
signal calcicc : std_logic := '0';
begin
process(op, op3, icc, cond)
begin
--valores for defecto
PCsource <= "11";
RFsource <= "01";
wren <= '0';
RdEnMem <= '0';
WrEnMem <= '0';
RFdest <= '0';
if(op = "10") then --formato3
wren <= '1';
case op3 is
when "000000" => --Add
aluop <= "000000"; --0
when "000100" => --Sub
aluop <= "000001"; --1
when "000001" => -- And
aluop <= "000010"; --2
when "000101" => --Andn
aluop <= "000011"; --3
when "000010" => --or
aluop <= "000100"; --4
when "000110" => --orn
aluop <= "000101"; --5
when "000011" => --xor
aluop <= "000110"; --6
when "000111" => --xnor
aluop <= "000111"; --7
when "010100" => --SUBcc
aluop <= "001000"; --8
when "001100" => --SUBx
aluop <= "001001"; --9
when "011100" => --SUBxcc
aluop <= "001010"; --10
when "010001" => --ANDcc
aluop <= "001011"; --11
when "010101" => --ANDNcc
aluop <= "001100"; --12
when "010010" => --ORcc
aluop <= "001101"; --13
when "010110" => --ORNcc
aluop <= "001110"; --14
when "010011" => --XORcc
aluop <= "001111"; --15
when "010111" => --XNORcc
aluop <= "010000"; --16
when "001000" => --ADDx
aluop <= "010001"; --17
when "011000" => --ADDxcc
aluop <= "010010"; --18
when "010000" => --ADDcc
aluop <= "010011"; --19
when "100101" =>
AluOp <= "100101";--SLL Shift Left Logical 37
when "100110" =>
AluOp <= "100110";--SRL Shift Right Logical 38
when "111100" =>
AluOp <= "111100";--Save 60
when "111101" =>
AluOp <= "111101";--RESTORE 61
when "111000" =>
ALUOP <= "010100";
RFsource <= "10";--selecciona PC como datatoreg
PCsource <= "00";--operacion de la alu
RFdest <= '0';--seleccion nRD
when others =>
aluop <= (others=>'1'); --error
end case;
elsif (op = "11") then
case OP3 is
when "000000" =>--load word
ALUOP <= "010101"; --21
RdEnMem <= '1';--activa lectura en memoria
WrEnMem <= '0';
RFsource <= "00";--selecciona dato de memoria como datatoreg
wren <= '1';
when "000100" =>--store word
ALUOP <= "010110"; --22
WrEnMem <= '1';--activa escritura en memoria
RdEnMem <= '0';
when others =>
ALUOP <= "000000";
end case;
elsif(OP = "01") then
ALUOP <= "000000";
wren <='0';
RFsource <= "10";--selecciona PC como datatoreg
RFdest <= '1';--selecciona no7 como registro de destino
PCsource <= "01";--selecciona disp30 como source del PC
WrEnMem <= '0';
RdEnMem <= '1';
elsif(OP = "00") then
--NZCV
wren <= '0';
ALUOP <= "000000";
case cond is
when "1000" =>
PCsource <= "10";--BA escoge disp22 como source
when "1001" =>--BNE
calcicc <= not icc(2);
if(calcicc = '1') then
PCsource <= "10";
end if;
when "0001" =>--BE
calcicc <= icc(2);
if(calcicc='1') then
PCsource <= "10";
end if;
when "1010" =>--BG
calcicc <= not (icc(2) or (icc(3) xor icc(0)));
if(calcicc = '1') then
PCsource <= "10";
end if;
when "0010" =>--BLE
calcicc <= icc(2) or (icc(3) xor icc(0));
if(calcicc='1') then
PCsource <= "10";
end if;
when "1011" =>--BGE
calcicc <= not(icc(3) xor icc(0));
if(calcicc='1') then
PCsource <= "10";
end if;
when "0011" =>--BL
calcicc <= (icc(3) xor icc(0));
if(calcicc='1') then
PCsource <= "10";
end if;
when "1100" =>--BGU
calcicc <= not(icc(1) or icc(2));
if(calcicc='1') then
PCsource <= "10";
end if;
when "0100" =>--BLEU
calcicc <= (icc(1) or icc(2));
if(calcicc='1') then
PCsource <= "10";
end if;
when "1101" =>--BCC
calcicc <= not icc(1);
if(calcicc='1') then
PCsource <= "10";
end if;
when "0101" =>--BCS
calcicc <= icc(1);
if(calcicc='1') then
PCsource <= "10";
end if;
when "1110" =>--BPOS
calcicc <= not icc(3);
if(calcicc='1') then
PCsource <= "10";
end if;
when "0110" =>--BNEG
calcicc <= icc(3);
if(calcicc='1') then
PCsource <= "10";
end if;
when "1111" =>--BVC
calcicc <= not icc(0);
if(calcicc='1') then
PCsource <= "10";
end if;
when "0111" =>--BVS
calcicc <= icc(0);
if(calcicc='1') then
PCsource <= "10";
end if;
when others =>
PCsource <="00";
end case;
end if;
end process;
end Behavioral;
|
mit
|
6559eff1a607e9156d091ce53f098203
| 0.472424 | 3.649838 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/windows_manager_arch.vhd
| 1 | 3,017 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Notas:
-- La idea de este modulo es expandir la cantidad de registros disponibles
-- con 5 bits yo solo tengo 2**5 -1 registros. Las ventanas nos dejar ir moviendonos
-- para tener mas ventanas, en nuestra arquitectura de 40 a 520.
-- Los registros globales siempre van a estar en la misma posicion, los unicos que se mueven son los locales,outs, inputs.
--Basado en https://www.educreations.com/lesson/view/procesador-sparc-v8-soportando-windowing/13230159/
-- analizar el estado del psr en los primeros 5 bits que son cwp
--save: cwp<=cwp-1 >> cwp<='0'
--restore: cwp<=cwp+1 >> cwp<='1'
entity windows_manager_arch is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
CWP : in STD_LOGIC;
nrs1 : out STD_LOGIC_VECTOR (5 downto 0);
nrs2 : out STD_LOGIC_VECTOR (5 downto 0);
nrd : out STD_LOGIC_VECTOR (5 downto 0);
nCWP : out STD_LOGIC);
end windows_manager_arch;
architecture Behavioral of windows_manager_arch is
begin
process(rs1,rs2,rd,cwp)
begin
--si es locales y salida, usa la logica del video:
-- 10 y 23
if (rs1>="01000" and rs1<="10111") then
nrs1<=conv_std_logic_vector(conv_integer(rs1)+(conv_integer(cwp)*16),6);
end if;
if (rs2>="01000" and rs2<="10111") then
nrs2<=conv_std_logic_vector(conv_integer(rs2)+(conv_integer(cwp)*16),6);
end if;
if (rd>="01000" and rd<="10111") then
nrd<=conv_std_logic_vector(conv_integer(rd)+(conv_integer(cwp)*16),6);
end if;
--si es entrada
if (rs1>="11000" and rs1<="11111") then
nrs1<=conv_std_logic_vector(conv_integer(rs1)-(conv_integer(cwp)*16),6);
end if;
if (rs2>="11000" and rs2<="11111") then
nrs2<=conv_std_logic_vector(conv_integer(rs2)-(conv_integer(cwp)*16),6);
end if;
if (rd>="11000" and rd<="11111") then
nrd<=conv_std_logic_vector(conv_integer(rd)-(conv_integer(cwp)*16),6);
end if;
--si son globales esas siempre van a quedar en la misma parte
if (rs1>="00000" and rs1<="00111") then
nrs1<='0'&rs1;
end if;
if (rs2>="00000" and rs2<="00111") then
nrs2<='0'&rs2;
end if;
if (rd>="00000" and rd<="00111") then
nrd<='0'&rd;
end if;
end process;
process(op,op3,cwp)
begin
if (op="10") and (cwp = '1') then
-- para save
if (op3="111100")then -- save
ncwp<='0';
end if;
if (op3="111101")then --restore
ncwp<='1';
end if;
end if;
if (op="10") and (cwp = '0') then
--restore
if (op3="111101")then --restore
ncwp<='1';
end if;
if (op3="111100")then --save
ncwp<='0';
end if;
end if;
if(op="10")then
if ((op3/="111100") and (op3/="111101"))then
ncwp <= cwp;
end if;
end if;
end process;
end Behavioral;
|
mit
|
0ff8b5f80c579da94d9961fbe7ed5a04
| 0.630096 | 2.798701 | false | false | false | false |
rogerioag/gcg
|
tutorial/ula/testbench/and2_tb.vhd
| 1 | 1,834 |
-- Testebench gerado via script.
-- Data: Qua,20/07/2011-14:18:43
-- Autor: rogerio
-- Comentario: Teste da entidade and2.
library ieee;
use ieee.std_logic_1164.all;
entity and2_tb is
end and2_tb;
architecture logica of and2_tb is
-- Declaração do componente.
component and2
port (a,b: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for and2_0: and2 use entity work.and2;
signal s_t_a, s_t_b, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
and2_0: and2 port map (a=>s_t_a,b=>s_t_b,y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a,vi_b: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(
('0', '0', '0'),
('0', '1', '0'),
('1', '0', '0'),
('1', '1', '1')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
|
gpl-3.0
|
ceb1050a9260314a15d523b9c8bcc9a8
| 0.592735 | 3.100683 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/noekeon_pipe/reg_128.vhd
| 3 | 2,131 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:28 03/02/2015
-- Design Name:
-- Module Name: reg_128 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg_128 is
port(clk : in std_logic;
rst : in std_logic;
data_in_0 : in std_logic_vector(31 downto 0);
data_in_1 : in std_logic_vector(31 downto 0);
data_in_2 : in std_logic_vector(31 downto 0);
data_in_3 : in std_logic_vector(31 downto 0);
data_out_0 : out std_logic_vector(31 downto 0);
data_out_1 : out std_logic_vector(31 downto 0);
data_out_2 : out std_logic_vector(31 downto 0);
data_out_3 : out std_logic_vector(31 downto 0));
end reg_128;
architecture Behavioral of reg_128 is
signal reg_32_0_s : std_logic_vector(31 downto 0);
signal reg_32_1_s : std_logic_vector(31 downto 0);
signal reg_32_2_s : std_logic_vector(31 downto 0);
signal reg_32_3_s : std_logic_vector(31 downto 0);
begin
pr_reg: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_32_0_s <= (others => '0');
reg_32_1_s <= (others => '0');
reg_32_2_s <= (others => '0');
reg_32_3_s <= (others => '0');
else
reg_32_0_s <= data_in_0;
reg_32_1_s <= data_in_1;
reg_32_2_s <= data_in_2;
reg_32_3_s <= data_in_3;
end if;
end if;
end process;
data_out_0 <= reg_32_0_s;
data_out_1 <= reg_32_1_s;
data_out_2 <= reg_32_2_s;
data_out_3 <= reg_32_3_s;
end Behavioral;
|
gpl-3.0
|
ce66819268869dc02319d1b12fa985f3
| 0.563585 | 2.972106 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/RF.vhd
| 1 | 1,074 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RF is
Port ( Rs1 : in STD_LOGIC_VECTOR (5 downto 0);
Rs2 : in STD_LOGIC_VECTOR (5 downto 0);
Rd : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Dwr : in STD_LOGIC_VECTOR (31 downto 0);
ORs1 : out STD_LOGIC_VECTOR (31 downto 0);
ORs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (0 to 39) of std_logic_vector (31 downto 0);
signal registers : ram_type :=(others => x"00000000");
begin
process(rs1,rs2,rd,dwr, rst)
begin
registers(0) <= x"00000000";
if rst = '0' then
if(rd/="00000")then
registers(conv_integer(rd)) <= Dwr;
end if;
ORs1 <= registers(conv_integer(Rs1));
ORs2 <= registers(conv_integer(Rs2));
else
ORs1 <= (others => '0');
ORs2 <= (others => '0');
--registers(16) <= x"00000011";
--registers(17) <= x"FFFFFFF7";
--registers(18) <= x"0000000E";
end if;
end process;
end Behavioral;
|
mit
|
20428a4f0257b8255a54fd5af7137cac
| 0.598696 | 2.983333 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
cylindrical_conductor_with_skin_effect/cyl_cond.vhd
| 1 | 3,953 |
-------------------------------------------------------------------------------
-- Model: SOLID CYLINDER for TIME-DOMAIN ANALYSIS
--
-- Author: Vladimir Kolchuzhin, MMT, TU Chemnitz
-- <[email protected]>
-- Date: 01.12.2014
-- Library:
-- kvl in hAMSter
-------------------------------------------------------------------------------
-- IEEE TRANSACTIONS ON MAGNETICS, VOL. 32, NO. I , JANUARY 1996
-- Lawrence J. Giacoletto
-- FREQUENCY AND TIME-DOMAIN ANALYSIS OF SKIN EFFECTS
-- for the cylinder conductor as a series element
-- for the cylinder conductor as a shunt element
-------------------------------------------------------------------------------
-- ID: cyl_cond.vhd
-- Rev. 1.0
-------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY user;
USE ieee.math_real.all;
USE ieee.electrical_systems.ALL;
entity wire is
generic (dc_value,ac_value,freq,phase:real); -- parameters:
port (terminal p,n:electrical); -- pins
end entity wire;
-------------------------------------------------------------------------------
-- for the cylinder conductor as a series element
architecture series_element of cyl_cond is
quantity v across i through p to n;
-- material properties
constant sigma:real:=37.0e-06; -- conductivity CuZr, S/m
constant mu:real:=1.0e-07*4.0*3.14; -- permeability: 4*pi*1e-7 H/m
-- geometry
constant R2:real:=10.0e-03; -- outside radius R2
constant L:real:=1.0; -- length of conductor, m
constant Rdc:real:=L/sigma/(3.14*R2*R2); -- dc resistance of conductor
constant omega_c:real:= 1.0/(sigma*mu*R2*R2); -- characteristic radian frequency
constant c0:real:= 1.0;
constant c1:real:= 0.125/omega_c;
constant c2:real:=-5.208333e-03/(omega_c**2);
constant c3:real:= 3.255208e-04/(omega_c**3);
constant c4:real:=-2.170139e-05/(omega_c**4);
constant c5:real:= 1.469365e-06/(omega_c**5);
constant c6:real:=-9.990874e-08/(omega_c**6);
constant c7:real:= 6.801447e-09/(omega_c**7);
constant c8:real:=-4.631829e-10/(omega_c**8);
constant c9:real:= 3.154634e-11/(omega_c**9);
begin
v == Rdc*(c0*i + c1*i'dot + c2*i'dot'dot + c3*i'dot'dot'dot + c4*i'dot'dot'dot'dot + c5*i'dot'dot'dot'dot'dot +
c6*i'dot'dot'dot'dot'dot'dot + c7*i'dot'dot'dot'dot'dot'dot'dot + c8*i'dot'dot'dot'dot'dot'dot'dot'dot +
c9*i'dot'dot'dot'dot'dot'dot'dot'dot'dot);
end architecture series_element;
-------------------------------------------------------------------------------
-- for the cylinder conductor as a shunt element
architecture shunt_element of cyl_cond is
quantity v across i through p to n;
-- material properties
constant sigma:real:=37.0e-06; -- conductivity CuZr, S/m
constant mu:real:=1.0e-07*4.0*3.14; -- permeability: 4*pi*1e-7 H/m
-- geometry
constant R2:real:=10.0e-03; -- outside radius R2
constant L:real:=1.0; -- length of conductor, m
constant Rdc:real:=L/sigma/(3.14*R2*R2); -- dc resistance of conductor
constant omega_c:real:= 1.0/(sigma*mu*R2*R2); -- characteristic radian frequency
constant d0:real:= 1.0;
constant d1:real:=-0.125/omega_c;
constant d2:real:= 2.083333e-02/(omega_c**2);
constant d3:real:=-3.580734e-03/(omega_c**3);
constant d4:real:= 6.184882e-04/(omega_c**4);
constant d5:real:=-1.069248e-04/(omega_c**5);
constant d6:real:= 1.848816e-05/(omega_c**6);
constant d7:real:=-3.196859e-06/(omega_c**7);
constant d8:real:= 5.527843e-07/(omega_c**8);
constant d9:real:=-9.558471e-08/(omega_c**9);
begin
i == (d0*v + d1*v'dot + d2*v'dot'dot + d3*v'dot'dot'dot + d4*v'dot'dot'dot'dot + d5*v'dot'dot'dot'dot'dot +
d6*v'dot'dot'dot'dot'dot'dot + d7*v'dot'dot'dot'dot'dot'dot'dot + d8*v'dot'dot'dot'dot'dot'dot'dot'dot +
d9*v'dot'dot'dot'dot'dot'dot'dot'dot'dot)/Rdc;
end architecture shunt_element;
-------------------------------------------------------------------------------
|
mit
|
0688da1f530206b68e52ea20b2dec6cc
| 0.573741 | 2.94122 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/pdp11_aunit.vhd
| 2 | 8,217 |
-- $Id: pdp11_aunit.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_aunit - syn
-- Description: pdp11: arithmetic unit for data (aunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
-- arithmetic unit for data, usage:
-- ADD: SRC + DST + 0 (dst+src)
-- SUB: ~SRC + DST + 1 (dst-src)
-- ADC: 0 + DST + CI (dst+ci)
-- SBC: ~0 + DST + ~CI (dst-ci)
-- CMP: SRC + ~DST + 1 (src-dst)
-- COM: 0 + ~DST + 0 (~dst)
-- NEG: 0 + ~DST + 1 (-dst)
-- INC: 0 + DST + 1 (dst+1)
-- DEC: ~0 + DST + 0 (dst-1)
-- CLR: 0 + 0 + 0 (0)
-- SOB: SRC + ~0 + 0 (src-1)
entity pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_aunit;
architecture syn of pdp11_aunit is
-- --------------------------------------
begin
process (DSRC, DDST, CI, CIMOD, CC1OP, CCMODE, SRCMOD, DSTMOD, BYTOP)
variable msrc : slv16 := (others=>'0'); -- effective src data
variable mdst : slv16 := (others=>'0'); -- effective dst data
variable mci : slbit := '0'; -- effective ci
variable sum : slv16 := (others=>'0'); -- sum
variable co8 : slbit := '0'; -- co 8 bit
variable co16 : slbit := '0'; -- co 16 bit
variable nno : slbit := '0'; -- local no
variable nzo : slbit := '0'; -- local zo
variable nvo : slbit := '0'; -- local vo
variable nco : slbit := '0'; -- local co
variable src_msb : slbit := '0'; -- msb from src (bit 15 or 7)
variable dst_msb : slbit := '0'; -- msb from dst (bit 15 or 7)
variable sum_msb : slbit := '0'; -- msb from sum (bit 15 or 7)
alias NO : slbit is CCOUT(3);
alias ZO : slbit is CCOUT(2);
alias VO : slbit is CCOUT(1);
alias CO : slbit is CCOUT(0);
-- procedure do_add8_ci_co: 8 bit adder with carry in and carry out
-- implemented following the recommended pattern for XST ISE V8.1
procedure do_add8_ci_co (
variable a : in slv8; -- input a
variable b : in slv8; -- input b
variable ci : in slbit; -- carry in
variable sum : out slv8; -- sum out
variable co : out slbit -- carry out
) is
variable tmp: slv9;
begin
tmp := conv_std_logic_vector((conv_integer(a) + conv_integer(b) +
conv_integer(ci)),9);
sum := tmp(7 downto 0);
co := tmp(8);
end procedure do_add8_ci_co;
begin
case SRCMOD is
when c_aunit_mod_pass => msrc := DSRC;
when c_aunit_mod_inv => msrc := not DSRC;
when c_aunit_mod_zero => msrc := (others=>'0');
when c_aunit_mod_one => msrc := (others=>'1');
when others => null;
end case;
case DSTMOD is
when c_aunit_mod_pass => mdst := DDST;
when c_aunit_mod_inv => mdst := not DDST;
when c_aunit_mod_zero => mdst := (others=>'0');
when c_aunit_mod_one => mdst := (others=>'1');
when others => null;
end case;
case CIMOD is
when c_aunit_mod_pass => mci := CI;
when c_aunit_mod_inv => mci := not CI;
when c_aunit_mod_zero => mci := '0';
when c_aunit_mod_one => mci := '1';
when others => null;
end case;
do_add8_ci_co(msrc(7 downto 0), mdst(7 downto 0), mci,
sum(7 downto 0), co8);
do_add8_ci_co(msrc(15 downto 8), mdst(15 downto 8), co8,
sum(15 downto 8), co16);
DOUT <= sum;
-- V ('overflow) bit set if
-- ADD : both operants of same sign but has result opposite sign
-- SUB : both operants of opposide sign and sign source equals sign result
-- CMP : both operants of opposide sign and sign dest. equals sign result
nno := '0';
nzo := '0';
nvo := '0';
nco := '0';
if BYTOP = '1' then
nno := sum(7);
if unsigned(sum(7 downto 0)) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co8;
src_msb := DSRC(7);
dst_msb := DDST(7);
sum_msb := sum(7);
else
nno := sum(15);
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co16;
src_msb := DSRC(15);
dst_msb := DDST(15);
sum_msb := sum(15);
end if;
-- the logic for 2 operand V+C is ugly. It is reverse engineered from
-- the MOD's the operation type.
if CC1OP = '0' then -- 2 operand cases
if unsigned(CIMOD) = unsigned(c_aunit_mod_zero) then -- case ADD
nvo := not(src_msb xor dst_msb) and (src_msb xor sum_msb);
else
if unsigned(SRCMOD) = unsigned(c_aunit_mod_inv) then -- case SUB
nvo := (src_msb xor dst_msb) and not (src_msb xor sum_msb);
else -- case CMP
nvo := (src_msb xor dst_msb) and not (dst_msb xor sum_msb);
end if;
nco := not nco; -- invert C for SUB and CMP
end if;
else -- 1 operand cases
case CCMODE is
when c_aunit_ccmode_clr|c_aunit_ccmode_tst =>
nvo := '0'; -- force v=0 for tst and clr
nco := '0'; -- force c=0 for tst and clr
when c_aunit_ccmode_com =>
nvo := '0'; -- force v=0 for com
nco := '1'; -- force c=1 for com
when c_aunit_ccmode_inc =>
nvo := sum_msb and not dst_msb;
nco := CI; -- C not affected for INC
when c_aunit_ccmode_dec =>
nvo := not sum_msb and dst_msb;
nco := CI; -- C not affected for DEC
when c_aunit_ccmode_neg =>
nvo := sum_msb and dst_msb;
nco := not nzo;
when c_aunit_ccmode_adc =>
nvo := sum_msb and not dst_msb;
when c_aunit_ccmode_sbc =>
nvo := not sum_msb and dst_msb;
nco := not nco;
when others => null;
end case;
end if;
NO <= nno;
ZO <= nzo;
VO <= nvo;
CO <= nco;
end process;
end syn;
|
gpl-2.0
|
1e718865d8f1b7ba446dc2483b290292
| 0.490082 | 3.648757 | false | false | false | false |
sigasi/SigasiProjectCreator
|
tests/test-files/tutorial/dut.vhd
| 2 | 940 |
library IEEE;
use IEEE.std_logic_1164.all;
entity dut is
port(
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
valid : out std_logic;
start : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity dut;
architecture RTL of dut is
constant MIN_COUNT : integer := 0;
constant MAX_COUNT : integer := 5;
signal count : integer range 0 to MAX_COUNT;
begin
OUTPUT_GENERATOR : process(count, data_in) is
begin
if count = MAX_COUNT then
valid <= '1';
data_out <= data_in;
else
valid <= '0';
data_out <=(others => '0');
end if;
end process OUTPUT_GENERATOR;
COUNTER : process(clk, rst) is
begin
if rst = '1' then
count <= 0;
elsif rising_edge(clk) then
if start = '1' then
count <= 0;
elsif count < MAX_COUNT then
count <= count + 1;
end if;
end if;
end process COUNTER;
end architecture RTL;
|
bsd-3-clause
|
d7c261dd006b849d672f1d1b1767dc18
| 0.618085 | 2.848485 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw13/UpDownMod55.vhd
| 1 | 914 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UpDownMod55 is
port(
clk, up: in std_logic;
q : out integer range 0 to 63
);
end entity;
architecture impl of UpDownMod55 is
component UpDownMod16 is
port(
clk, load, enable, up : in std_logic;
toLoad: in integer range 0 to 15;
q : out integer range 0 to 15;
carry : out std_logic
);
end component;
signal carry, load : std_logic;
signal enable : std_logic := '1';
signal a,b, al, bl : integer range 0 to 15;
begin
counter1 : UpDownMod16 port map(
clk, load, enable, up, al, a, carry
);
counter2 : UpDownMod16 port map(
carry, load, enable, up, bl, b
);
process(a, b)
begin
if (a = 7 and b = 3 and up = '1') then
load <= '1'; al <= 0; bl <= 0;
elsif (a = 15 and b = 15 and up = '0') then
load <= '1'; al <= 6; bl <= 3;
else
load <= '0';
end if;
end process;
q <= b * 16 + a;
end impl;
|
mit
|
b9c289ca9e9958ddca1de923e63ba52a
| 0.618162 | 2.618911 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/fifo_controller.vhd
| 1 | 8,500 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--===========================================================================--
-- F I F O C O N T R O L L E R
--
-- purpose: abstraction of an ftdi ft245 style fifo interface
-- type: mealy state machine
--===========================================================================--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.constants.all;
--===========================================================================--
entity fifo_controller is
--===========================================================================--
generic(
FIFO_WIDTH : natural := 8
);
port(
-- fifo adapter interface
data_transmit_o : out std_logic_vector(FIFO_WIDTH -1 downto 0);
txe_i : in std_logic;
wr_o : out std_logic;
data_receive_i : in std_logic_vector(FIFO_WIDTH -1 downto 0);
rxf_i : in std_logic;
rd_o : out std_logic;
direction_o : out std_logic; -- 0:receiver, 1:transmitter
-- receive buffer interface
word_recbuf_o : out std_logic_vector(FIFO_WIDTH -1 downto 0);
store_recbuf_o : out std_logic;
busy_recbuf_i : in std_logic;
-- transmit buffer interface
word_trabuf_i : in std_logic_vector(FIFO_WIDTH -1 downto 0);
send_trabuf_i : in std_logic;
-- misc
transmitter_mode_i: in std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end fifo_controller;
--===========================================================================--
architecture two_proc of fifo_controller is
--===========================================================================--
type state_type is (
idle,
rd_request,
rd_wait0,
rd_wait1,
rd_wait2,
rd_store,
rd_end,
wr0,
wr1,
wr2,
wr3,
wr4
);
type reg_type is record
state : state_type;
counter : integer range 0 to 15;
end record;
signal reg_out, reg_in : reg_type;
begin
--===========================================================================--
COMBINATIONAL : process (reg_out, rxf_i, txe_i, word_trabuf_i, send_trabuf_i,
data_receive_i, transmitter_mode_i, busy_recbuf_i) is
--===========================================================================--
variable tmp : reg_type;
begin
-- default assignment
tmp := reg_out;
case tmp.state is
when idle =>
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '0'; -- receiver mode
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- reset counter
tmp.counter := 0;
-- next state logic
if (rxf_i = '1' and busy_recbuf_i = '0') then
tmp.state := rd_request;
rd_o <= '1';
elsif (send_trabuf_i = '1' and transmitter_mode_i = '1') then
tmp.state := wr0;
else
tmp.state := idle;
end if;
-- read request: assert rd to read fifo receive buffer
-- read wait: wait three cycles for data to become valid
-- Total duration: 50 ns @ 80 MHz
when rd_request | rd_wait0 | rd_wait1 | rd_wait2 =>
-- outputs
wr_o <= '0';
rd_o <= '1';
direction_o <= '0';
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- next state logic:
case tmp.state is
when rd_request =>
tmp.state := rd_wait0;
when rd_wait0 =>
tmp.state := rd_wait1;
when rd_wait1 =>
tmp.state := rd_wait2;
when others => -- rd_wait2
tmp.state := rd_store;
end case;
-- read store: assumes data is valid and stores
when rd_store =>
-- outputs
wr_o <= '0';
rd_o <= '1';
direction_o <= '0';
store_recbuf_o <= '1';
data_transmit_o <= (others=>'-');
word_recbuf_o <= data_receive_i;
-- next state logic
tmp.state := rd_end;
-- read end: wait until rxf is reset
when rd_end =>
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '0';
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- next state logic
if (rxf_i = '0') then
tmp.state := idle;
else
tmp.state := rd_end;
end if;
when wr0 => -- wait for txe
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '0';
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- next state logic
if (txe_i = '1') then
tmp.state := wr1;
else
tmp.state := wr0;
end if;
when wr1 => -- set direction
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '1';
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- next state logic
tmp.state := wr2;
when wr2 => -- drive out data
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '1';
store_recbuf_o <= '0';
data_transmit_o <= word_trabuf_i;
word_recbuf_o <= (others=>'-');
-- next state logic
tmp.state := wr3;
when wr3 => -- assert wr (minimum 50 ns)
-- outputs
wr_o <= '1';
rd_o <= '0';
direction_o <= '1';
store_recbuf_o <= '0';
data_transmit_o <= word_trabuf_i;
word_recbuf_o <= (others=>'-');
-- count
tmp.counter := tmp.counter + 1;
-- next state logic
if (tmp.counter < 4) then -- 50 ns * 80 MHz = 4
tmp.state := wr3;
else
tmp.state := wr4;
end if;
when wr4 => -- deassert wr
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '1';
store_recbuf_o <= '0';
data_transmit_o <= word_trabuf_i;
word_recbuf_o <= (others=>'-');
-- next state logic
tmp.state := idle;
end case;
-- drive register inputs
reg_in <= tmp;
end process COMBINATIONAL;
--===========================================================================--
REGISTERS : process (clk_i, rst_i) is
--===========================================================================--
begin
if (rising_edge(clk_i)) then
if (rst_i = '1') then
reg_out.state <= idle;
else
reg_out <= reg_in;
end if;
end if;
end process REGISTERS;
end two_proc;
|
gpl-3.0
|
0e916261aa606f47cfdcfdfa25563c65
| 0.401882 | 4.39731 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/wb_slave_single_reg_tb.vhd
| 1 | 3,828 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- WB SLAVE SINGLE REGISTER TESTBENCH (wb_slave_single_reg_tb.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wb_slave_single_reg_comp.all;
-------------------------------------------------------------------------------
ENTITY wb_slave_single_reg_tb is
-------------------------------------------------------------------------------
begin
end wb_slave_single_reg_tb;
-------------------------------------------------------------------------------
ARCHITECTURE simulation of wb_slave_single_reg_tb is
-------------------------------------------------------------------------------
-- constants
constant CLK_PERIOD : time := 10 ns;
-- signals
signal clk : std_logic;
signal rst : std_logic;
signal uut_in : wb_slave_in_type;
signal uut_out : wb_slave_out_type;
begin
-------------------------------------------------
STIMULI_PROC :
-------------------------------------------------
process begin
-- hold reset for 100 ns and 10 clock cycles
rst <= '1';
uut_in.dat_i <= (others => '0');
uut_in.adr_i <= (others => '0');
uut_in.stb_i <= '0';
uut_in.we_i <= '0';
wait for 100 ns;
rst <= '0';
wait for CLK_PERIOD*10;
-- single write
assert false report "Perform single write" severity note;
uut_in.dat_i <= x"FFFFFFFF";
uut_in.adr_i <= std_logic_vector(to_unsigned(15,32));
uut_in.stb_i <= '1';
uut_in.we_i <= '1';
wait for CLK_PERIOD;
if (uut_out.ack_o = '0') then wait until uut_out.ack_o = '1'; end if;
uut_in.stb_i <= '0';
wait for CLK_PERIOD;
-- single write (wrong address)
assert false report "Perform single write with wrong address" severity note;
uut_in.dat_i <= x"00000000";
uut_in.adr_i <= std_logic_vector(to_unsigned(10,32));
uut_in.stb_i <= '1';
uut_in.we_i <= '1';
wait for CLK_PERIOD;
if (uut_out.ack_o = '0') then wait until uut_out.ack_o = '1'; end if;
uut_in.stb_i <= '0';
wait for CLK_PERIOD;
-- single read
assert false report "Perform single read" severity note;
uut_in.adr_i <= std_logic_vector(to_unsigned(15,32));
uut_in.stb_i <= '1';
uut_in.we_i <= '0';
wait for CLK_PERIOD;
if (uut_out.ack_o = '0') then wait until uut_out.ack_o = '1'; end if;
uut_in.stb_i <= '0';
wait for CLK_PERIOD;
wait; -- forever
end process STIMULI_PROC;
-------------------------------------------------
-- UUT instantiation
-------------------------------------------------
UUT : entity work.wb_slave_single_reg
generic map (
register_address => to_unsigned(15,32)
)
port map (
clk_i => clk,
rst_i => rst,
wb_in => uut_in,
wb_out=> uut_out
);
-------------------------------------------------
CLK_GENERATOR :
-------------------------------------------------
process begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process CLK_GENERATOR;
end simulation;
|
gpl-3.0
|
998886491f71c4b2670b87742241e1a2
| 0.509927 | 3.828 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/DataMemory.vhd
| 1 | 981 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DataMemory is
Port ( WrEnMem : in STD_LOGIC;
RdEnMem : in STD_LOGIC;
reset : in std_logic;
crd : in STD_LOGIC_VECTOR (31 downto 0);
ALUResult : in STD_LOGIC_VECTOR (31 downto 0);
DataToMem : out STD_LOGIC_VECTOR (31 downto 0)
);
end DataMemory;
architecture Behavioral of DataMemory is
type ram_type is array (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
signal memory : ram_type := (others => x"00000000");
begin
process (WrEnMem,RdEnMem, reset, crd, ALUResult)
begin
if(reset = '1' or (WrEnMem='0' and RdEnMem='0')) then
DataToMem <= (others => '0');
elsif(WrEnMem = '1' and RdEnMem = '0') then
memory(conv_integer(ALUResult)) <= crd;
elsif(RdEnMem = '1' and WrEnMem = '0') then
DataToMem <= memory(conv_integer(ALUResult));
end if;
end process;
end Behavioral;
|
mit
|
6c8898d5b180eb562eff5f4c4db7a94a
| 0.614679 | 3.466431 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/Processor.vhd
| 1 | 9,935 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Processor is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end Processor;
architecture Behavioral of Processor is
COMPONENT Sumador
PORT(
Operador1 : IN std_logic_vector(31 downto 0);
Resultado : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT adder_SEU22
PORT(
OP1 : IN std_logic_vector(31 downto 0);
OP2 : IN std_logic_vector(31 downto 0);
AddOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT adder_COR
PORT(
OP1 : IN std_logic_vector(29 downto 0);
OP2 : IN std_logic_vector(31 downto 0);
Addout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
Carry : IN std_logic;
OPer1 : IN std_logic_vector(31 downto 0);
OPer2 : IN std_logic_vector(31 downto 0);
Salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
icc : IN std_logic_vector(3 downto 0);
Cond : IN std_logic_vector(3 downto 0);
wren : OUT std_logic;
PCsource : OUT std_logic_vector(1 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0);
RdEnMem : OUT std_logic;
WrEnMem : OUT std_logic;
RFsource : OUT std_logic_vector(1 downto 0);
RFdest : OUT std_logic
);
END COMPONENT;
COMPONENT DataMemory
PORT(
WrEnMem : IN std_logic;
RdEnMem : IN std_logic;
reset : IN std_logic;
crd : IN std_logic_vector(31 downto 0);
ALUResult : IN std_logic_vector(31 downto 0);
DataToMem : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
--clkFPGA: in std_logic;
rst : IN std_logic;
addr : IN std_logic_vector(31 downto 0);
data : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT MUX_wm
PORT(
RDin : IN std_logic_vector(5 downto 0);
o15 : IN std_logic_vector(5 downto 0);
RFDest : IN std_logic;
nRD : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT MUX_rf
PORT(
CRS2 : IN std_logic_vector(31 downto 0);
SEUimm13 : IN std_logic_vector(31 downto 0);
i : IN std_logic;
OPer2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT MUX_COR
PORT(
ALUaddress : IN std_logic_vector(31 downto 0);
PC_dis30 : IN std_logic_vector(31 downto 0);
PC_seu : IN std_logic_vector(31 downto 0);
PC_4 : IN std_logic_vector(4 downto 0);
PCsource : IN std_logic_vector(1 downto 0);
MUXout : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
COMPONENT MUX_DM
PORT(
PC : IN std_logic_vector(4 downto 0);
RFsource : IN std_logic_vector(1 downto 0);
DataToMem : IN std_logic_vector(31 downto 0);
ALUResult : IN std_logic_vector(31 downto 0);
DataToReg : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT PC
PORT(
DAT_in : IN std_logic_vector(4 downto 0);
rst : IN std_logic;
clk : IN std_logic;
DAT_out : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
COMPONENT PSR_Modifier
PORT(
rst : IN std_logic;
OP1 : IN std_logic_vector(31 downto 0);
OP2 : IN std_logic_vector(31 downto 0);
AluOp : IN std_logic_vector(7 downto 0);
AluResult : IN std_logic_vector(31 downto 0);
NZVC : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT PSR
PORT(
clk : IN std_logic;
Rst : IN std_logic;
NZVC : IN std_logic_vector(3 downto 0);
Ncwp : IN std_logic_vector(4 downto 0);
Cwp : OUT std_logic_vector(4 downto 0);
Carry : OUT std_logic;
icc : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rst : IN std_logic;
RS1 : IN std_logic_vector(5 downto 0);
RS2 : IN std_logic_vector(5 downto 0);
RD : IN std_logic_vector(5 downto 0);
DATATOREG : IN std_logic_vector(31 downto 0);
dwr : IN std_logic;
ORS1 : OUT std_logic_vector(31 downto 0);
ORS2 : OUT std_logic_vector(31 downto 0);
CRD : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Mod5Seu
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm32 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT windows_manager_arch is
Port (
rst : in std_logic;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
CWP : in STD_LOGIC_VECTOR (4 downto 0);
nrs1 : out STD_LOGIC_VECTOR (5 downto 0);
nrs2 : out STD_LOGIC_VECTOR (5 downto 0);
nrd : out STD_LOGIC_VECTOR (5 downto 0);
nCWP : out STD_LOGIC_VECTOR (4 downto 0);
no7 : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT SEU22
PORT(
disp22 : IN std_logic_vector(21 downto 0);
seuOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal nPCtoPC : std_logic_vector (31 downto 0) := (others => '0');
signal PCtoOthers : std_logic_vector(31 downto 0):= (others => '0');
signal IMout : std_logic_vector(31 downto 0):= (others => '0');
signal nrdWM : std_logic_vector (5 downto 0):= (others => '0');
signal o7WM : std_logic_vector (5 downto 0):= (others => '0');
signal pc_4 : std_logic_vector (31 downto 0):= (others => '0');
signal disp22e : std_logic_vector (31 downto 0):= (others => '0');
signal disp22_PC : std_logic_vector (31 downto 0):= (others => '0');
signal disp30_PC : std_logic_vector (31 downto 0):= (others => '0');
signal cualuop : std_logic_vector (5 downto 0):= (others => '0');
signal carry_p : std_logic:='0';
signal crs1_p : std_logic_vector (31 downto 0):= (others => '0');
signal crs2_p : std_logic_vector (31 downto 0):= (others => '0');
signal seusimm13 : std_logic_vector (31 downto 0):= (others => '0');
signal frs2 : std_logic_vector (31 downto 0):= (others => '0');
signal ALUout : std_logic_vector (31 downto 0):= (others => '0');
signal icc_p : std_logic_vector (3 downto 0):= (others => '0');
signal wren_p : std_logic:='0';
signal rfdest_p : std_logic:='0';
signal rfsource_p : std_logic_vector (1 downto 0):= (others => '0');
signal pcsource_p : std_logic_vector (1 downto 0):= (others => '0');
signal rdenmem_p : std_logic:='0';
signal wrenmem_p : std_logic:='0';
signal crd_p : std_logic_vector (31 downto 0);
signal datatoreg_p : std_logic_vector (31 downto 0):= (others => '0');
signal datatomux : std_logic_vector (31 downto 0):= (others => '0');
signal mux1torf : std_logic_vector (5 downto 0):= (others => '0');
signal nrs1_p : std_logic_vector (5 downto 0):= (others => '0');
signal nrs2_p : std_logic_vector (5 downto 0):= (others => '0');
signal cwp_p : std_logic_vector (4 downto 0):= (others => '0');
signal ncwp_p : std_logic_vector (4 downto 0):= (others => '0');
signal nzvc_p : std_logic_vector (3 downto 0):= (others => '0');
signal mux3tonpc : std_logic_vector (4 downto 0):= (others => '0');
begin
Inst_SEU22: SEU22 PORT MAP(
disp22 => IMout(21 downto 0),
seuOut => disp22e
);
Inst_Sumador_module: Sumador PORT MAP(
Operador1 => PCtoOthers,
Resultado => pc_4
);
Inst_adder_SEU22: adder_SEU22 PORT MAP(
OP1 => PCtoOthers,
OP2 => disp22e,
AddOut => disp22_PC
);
Inst_adder_COR: adder_COR PORT MAP(
OP1 => IMout(29 downto 0),
OP2 => PCtoOthers,
Addout => disp30_PC
);
Inst_ALU: ALU PORT MAP(
ALUOP => cualuop,
Carry => carry_p,
OPer1 => crs1_p,
OPer2 => frs2,
Salida => ALUout
);
Inst_CU: CU PORT MAP(
OP => IMout (31 downto 30),
OP3 => IMout (24 downto 19),
icc => icc_p,
Cond => IMout (28 downto 25),
wren => wren_p,
PCsource => pcsource_p,
ALUOP => cualuop,
RdEnMem => rdenmem_p,
WrEnMem => wrenmem_p,
RFsource => rfsource_p,
RFdest => rfdest_p
);
Inst_DataMemory: DataMemory PORT MAP(
WrEnMem => wrenmem_p,
RdEnMem => rdenmem_p,
reset => reset,
crd => crd_p,
ALUResult => ALUout,
DataToMem => datatomux
);
Inst_IM: IM PORT MAP(
--clkFPGA=>clk,
rst => reset,
addr => PCtoOthers,
data => IMout
);
Inst_MUX_wm: MUX_wm PORT MAP(
RDin => nrdWM,
o15 => o7WM,
RFDest => rfdest_p,
nRD => mux1torf
);
Inst_MUX_rf: MUX_rf PORT MAP(
CRS2 => crs2_p,
SEUimm13 => seusimm13,
i => IMout (13),
OPer2 => frs2
);
Inst_MUX_COR: MUX_COR PORT MAP(
ALUaddress => ALUout,
PC_dis30 => disp30_PC,
PC_seu => disp22_PC,
PC_4 => pc_4,
PCsource => pcsource_p,
MUXout => mux3tonpc
);
Inst_MUX_DM: MUX_DM PORT MAP(
PC => PCtoOthers,
RFsource => rfsource_p,
DataToMem => datatomux ,
ALUResult => ALUout,
DataToReg => datatoreg_p
);
Inst_PC: PC PORT MAP(
DAT_in => nPCtoPC,
rst => reset,
clk => clk,
DAT_out => PCtoOthers
);
Inst_nPC: PC PORT MAP(
DAT_in => mux3tonpc,
rst => reset,
clk => clk,
DAT_out => nPCtoPC
);
Inst_PSR_Modifier: PSR_Modifier PORT MAP(
rst => reset,
OP1 => crs1_p ,
OP2 => crs2_p,
AluOp => cualuop,
AluResult => ALUout,
NZVC => nzvc_p
);
Inst_PSR: PSR PORT MAP(
clk => clk,
Rst => reset ,
NZVC => nzvc_p,
Ncwp => ncwp_p,
Cwp => cwp_p,
Carry => carry_p,
icc => icc_p
);
Inst_RF: RF PORT MAP(
rst => reset,
RS1 => nrs1_p,
RS2 => nrs2_p,
RD => mux1torf,
DATATOREG => datatoreg_p ,
Dwr => wren_p,
ORS1 => crs1_p,
ORS2 => crs2_p,
CRD => crd_p
);
Inst_Mod5Seu: Mod5Seu PORT MAP(
imm13 => IMout (12 downto 0),
SEUimm32 => seusimm13
);
Inst_windows_manager_arch: windows_manager_arch PORT MAP(
rst => reset,
cwp => cwp_p,
rs1 => IMout (18 downto 14),
rs2 => IMout (4 downto 0) ,
rd => IMout (29 downto 25),
op => IMout (31 downto 30),
op3 => IMout (24 downto 19),
ncwp => ncwp_p,
nrs1 => nrs1_p,
nrs2 => nrs2_p,
nrd => nrdWM,
no7 => o7WM
);
DataOut<=datatoreg_p;
end Behavioral;
|
mit
|
a495debe246f592556173f902332e0fc
| 0.622043 | 2.814448 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
electrostatically_actuated_membrane/ca12_ams_160.vhd
| 1 | 892 |
package ca12_dat_160 is
constant ca12_type160:integer:=1;
constant ca12_inve160:integer:=2;
signal ca12_ord160:real_vector(1 to 3):=( 4.0, 4.0, 0.0 );
signal ca12_fak160:real_vector(1 to 4):=( 0.114386722375, 0.795085352965, 0.0, 0.225083783539 );
constant ca12_anz160:integer:= 25;
signal ca12_data160:real_vector(1 to 25):=
(
0.924864850772 ,
0.750140219005E-01,
-0.661841035530E-02,
0.109715066982E-02,
-0.215094781164E-03,
-0.533643405991E-02,
-0.864001014363E-03,
0.315112801689E-03,
-0.103808114827E-03,
0.301052576502E-04,
-0.142570841390E-03,
0.546854159479E-04,
-0.209086737993E-04,
0.897245384403E-05,
-0.318291521927E-05,
0.160290107930E-05,
-0.173411215981E-05,
0.101851559925E-05,
-0.625232626794E-06,
0.277844130785E-06,
-0.774100642402E-07,
0.824389854108E-07,
-0.539399052887E-07,
0.362089073215E-07,
-0.191260647195E-07
);
end;
|
mit
|
a18f01552b20e6ff6f37470370f4e5db
| 0.716368 | 2.103774 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/pdp11_lunit.vhd
| 2 | 6,761 |
-- $Id: pdp11_lunit.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_lunit - syn
-- Description: pdp11: logic unit for data (lunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from lbox
-- 2008-03-30 131 1.0.2 BUGFIX: SXT clears V condition code
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_lunit;
architecture syn of pdp11_lunit is
-- --------------------------------------
begin
process (DSRC, DDST, CCIN, FUNC, BYTOP)
variable iout : slv16 := (others=>'0');
variable inzstd : slbit := '0';
variable ino : slbit := '0';
variable izo : slbit := '0';
variable ivo : slbit := '0';
variable ico : slbit := '0';
alias DSRC_L : slv8 is DSRC(7 downto 0);
alias DSRC_H : slv8 is DSRC(15 downto 8);
alias DDST_L : slv8 is DDST(7 downto 0);
alias DDST_H : slv8 is DDST(15 downto 8);
alias NI : slbit is CCIN(3);
alias ZI : slbit is CCIN(2);
alias VI : slbit is CCIN(1);
alias CI : slbit is CCIN(0);
alias iout_l : slv8 is iout(7 downto 0);
alias iout_h : slv8 is iout(15 downto 8);
begin
iout := (others=>'0');
inzstd := '1'; -- use standard logic by default
ino := '0';
izo := '0';
ivo := '0';
ico := '0';
--
-- the decoding of FUNC is done "manually" to get a structure based on
-- a 8->1 pattern. This matches the opcode structure and seems most
-- efficient.
--
if FUNC(3) = '0' then
if BYTOP = '0' then
case FUNC(2 downto 0) is
when "000" => -- ASR
iout := DDST(15) & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
when "001" => -- ASL
iout := DDST(14 downto 0) & '0';
ico := DDST(15);
ivo := iout(15) xor ico;
when "010" => -- ROR
iout := CI & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
when "011" => -- ROL
iout := DDST(14 downto 0) & CI;
ico := DDST(15);
ivo := iout(15) xor ico;
when "100" => -- BIS
iout := DDST or DSRC;
ico := CI;
when "101" => -- BIC
iout := DDST and not DSRC;
ico := CI;
when "110" => -- BIT
iout := DDST and DSRC;
ico := CI;
when "111" => -- MOV
iout := DSRC;
ico := CI;
when others => null;
end case;
else
case FUNC(2 downto 0) is
when "000" => -- ASRB
iout_l := DDST_L(7) & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
when "001" => -- ASLB
iout_l := DDST(6 downto 0) & '0';
ico := DDST(7);
ivo := iout_l(7) xor ico;
when "010" => -- RORB
iout_l := CI & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
when "011" => -- ROLB
iout_l := DDST_L(6 downto 0) & CI;
ico := DDST_L(7);
ivo := iout_l(7) xor ico;
when "100" => -- BISB
iout_l := DDST_L or DSRC_L;
ico := CI;
when "101" => -- BICB
iout_l := DDST_L and not DSRC_L;
ico := CI;
when "110" => -- BITB
iout_l := DDST_L and DSRC_L;
ico := CI;
when "111" => -- MOVB
iout_l := DSRC_L;
iout_h := (others=>DSRC_L(7));
ico := CI;
when others => null;
end case;
end if;
else
case FUNC(2 downto 0) is
when "000" => -- SXT
iout := (others=>NI);
inzstd := '0';
ino := NI;
izo := not NI;
ivo := '0';
ico := CI;
when "001" => -- SWAP
iout := DDST_L & DDST_H;
inzstd := '0';
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
when "010" => -- XOR
iout := DDST xor DSRC;
ico := CI;
when others => null;
end case;
end if;
DOUT <= iout;
if inzstd = '1' then
if BYTOP = '1' then
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
else
ino := iout(15);
if unsigned(iout) = 0 then
izo := '1';
else
izo := '0';
end if;
end if;
end if;
CCOUT(3) <= ino;
CCOUT(2) <= izo;
CCOUT(1) <= ivo;
CCOUT(0) <= ico;
end process;
end syn;
|
gpl-2.0
|
9cd58ccdd742c0ccbd0db701e30d3638
| 0.43322 | 3.863429 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/tb/tb_pdp11core.vhd
| 1 | 23,753 |
-- $Id: tb_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_pdp11core - sim
-- Description: Test bench for pdp11_core
--
-- Dependencies: simlib/simclk
-- tbd_pdp11core [UUT]
-- pdp11_intmap
--
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.29; ISim 11.3
--
-- Verified (with tb_pdp11core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2010-12-30 351 - 0.29 - - u:ok
-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
-- 2010-06-20 308 - 0.29 - - u:ok
-- 2009-11-22 252 - 0.26 - - u:ok
-- 2007-12-30 107 - 0.25 - - u:ok
-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok
-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
-- 2007-10-07 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.3.2 now numeric_std clean
-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
-- 'sta' behaviour with new 'stapc' command; rename
-- lal,lah -> wal,wah and implement locally; new
-- output format with cpfunc name
-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon
-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_
-- 2009-11-28 253 1.1.12 add hack for ISim 11.3
-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits)
-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail
-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now
-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for
-- command completion, wtgo waits for CPU to halt.
-- added .cerr,.merr directive, check cmd(m)err state
-- added .sdef as ignored directive
-- 2008-02-24 119 1.1.4 added lah,rps,wps command
-- 2008-01-26 114 1.1.3 add handling of d=val,msk
-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-02 79 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11_sim.all;
use work.pdp11.all;
entity tb_pdp11core is
end tb_pdp11core;
architecture sim of tb_pdp11core is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
signal CP_CNTL_req : slbit := '0';
signal CP_CNTL_func : slv5 := (others=>'0');
signal CP_CNTL_rnum : slv3 := (others=>'0');
signal CP_ADDR_addr : slv22_1 := (others=>'0');
signal CP_ADDR_racc : slbit := '0';
signal CP_ADDR_be : slv2 := "11";
signal CP_ADDR_ena_22bit : slbit := '0';
signal CP_ADDR_ena_ubmap : slbit := '0';
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT_cmdbusy : slbit := '0';
signal CP_STAT_cmdack : slbit := '0';
signal CP_STAT_cmderr : slbit := '0';
signal CP_STAT_cmdmerr : slbit := '0';
signal CP_STAT_cpugo : slbit := '0';
signal CP_STAT_cpustep : slbit := '0';
signal CP_STAT_cpuhalt : slbit := '0';
signal CP_STAT_cpurust : slv4 := (others=>'0');
signal CP_DOUT : slv16 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal R_CHKDAT : slv16 := (others=>'0');
signal R_CHKMSK : slv16 := (others=>'0');
signal R_CHKREQ : slbit := '0';
signal R_WAITCMD : slbit := '0';
signal R_WAITSTEP : slbit := '0';
signal R_WAITGO : slbit := '0';
signal R_WAITOK : slbit := '0';
signal R_CP_STAT : cp_stat_type := cp_stat_init;
signal R_CP_DOUT : slv16 := (others=>'0');
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_STOP => CLK_STOP
);
UUT: entity work.tbd_pdp11core
port map (
CLK => CLK,
RESET => RESET,
CP_CNTL_req => CP_CNTL_req,
CP_CNTL_func => CP_CNTL_func,
CP_CNTL_rnum => CP_CNTL_rnum,
CP_ADDR_addr => CP_ADDR_addr,
CP_ADDR_racc => CP_ADDR_racc,
CP_ADDR_be => CP_ADDR_be,
CP_ADDR_ena_22bit => CP_ADDR_ena_22bit,
CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap,
CP_DIN => CP_DIN,
CP_STAT_cmdbusy => CP_STAT_cmdbusy,
CP_STAT_cmdack => CP_STAT_cmdack,
CP_STAT_cmderr => CP_STAT_cmderr,
CP_STAT_cmdmerr => CP_STAT_cmdmerr,
CP_STAT_cpugo => CP_STAT_cpugo,
CP_STAT_cpustep => CP_STAT_cpustep,
CP_STAT_cpuhalt => CP_STAT_cpuhalt,
CP_STAT_cpurust => CP_STAT_cpurust,
CP_DOUT => CP_DOUT
);
proc_stim: process
file ifile : text open read_mode is "tb_pdp11core_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable idummy : integer := 0;
variable dcycle : integer := 0;
variable irqline : integer := 0;
variable ireq : boolean := false;
variable ifunc : slv5 := (others=>'0');
variable irnum : slv3 := (others=>'0');
variable idin : slv16 := (others=>'0');
variable imsk : slv16 := (others=>'1');
variable ichk : boolean := false;
variable idosta: slbit := '0';
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable rind : integer := 0;
variable nblk : integer := 0;
variable xmicmd : string(1 to 3) := (others=>' ');
variable iwtstp : boolean := false;
variable iwtgo : boolean := false;
variable icerr : integer := 0;
variable imerr : integer := 0;
variable to_cmd : integer := 50;
variable to_stp : integer := 100;
variable to_go : integer := 5000;
variable ien : slbit := '0';
variable ibit : integer := 0;
variable imemi : boolean := false;
variable ioff : slv6 := (others=>'0');
variable idoibr : boolean := false;
variable r_addr : slv22_1 := (others=>'0');
variable r_ena_22bit : slbit := '0';
variable r_ena_ubmap : slbit := '0';
variable r_ibrbase : slv(c_ibrb_ibf_base) := (others=>'0');
variable r_ibrbe : slv2 := (others=>'0');
begin
SB_CNTL <= (others=>'L');
wait for clock_offset - setup_time;
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
file_loop: while not endfile(ifile) loop
-- this logic is a quick hack to implement the 'stapc' command
if idosta = '0' then
readline (ifile, iline);
iwtstp := false;
iwtgo := false;
if nblk>0 and -- outstanding [rw]mi lines ?
iline'length>=3 and -- and 3 leading blanks
iline(iline'left to iline'left+2)=" " then
nblk := nblk - 1; -- than fill [rw]mi command in again
iline(iline'left to iline'left+2) := xmicmd;
end if;
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
else
idosta := '0';
dname := "sta ";
ok := true;
end if;
if ok then
case dname is
when "rsp " => dname := "rr6 "; -- rsp -> rr6
when "rpc " => dname := "rr7 "; -- rpc -> rr7
when "wsp " => dname := "wr6 "; -- wsp -> wr6
when "wpc " => dname := "wr7 "; -- wpc -> wr7
when others => null;
end case;
rind := character'pos(dname(3)) - character'pos('0');
if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7]
dname(2)='r' and
(rind>=0 and rind<=7) then
dname(3) := '|'; -- replace with [rw]r|
end if;
if dname(1) = '.' then
case dname is
when ".mode " => -- .mode
readword_ea(iline, dname);
assert dname="pdpcp "
report "assert .mode == pdpcp" severity failure;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".tocmd" => -- .tocmd
read_ea(iline, idelta);
to_cmd := idelta;
when ".tostp" => -- .tostp
read_ea(iline, idelta);
to_stp := idelta;
when ".togo " => -- .togo
read_ea(iline, idelta);
to_go := idelta;
when ".sdef " => -- .sdef (ignore it)
readempty(iline);
when ".cerr " => -- .cerr
read_ea(iline, icerr);
when ".merr " => -- .merr
read_ea(iline, imerr);
when ".anena" => -- .anena (ignore it)
readempty(iline);
when ".rlmon" => -- .rlmon (ignore it)
readempty(iline);
when ".rbmon" => -- .rbmon (ignore it)
readempty(iline);
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
testempty_ea(iline);
next file_loop;
else
ireq := true;
ifunc := c_cpfunc_noop;
irnum := "000";
ichk := false;
idin := (others=>'0');
imsk := (others=>'1');
imemi := false;
idoibr := false;
case dname is
when "brm " => -- brm
read_ea(iline, nblk);
xmicmd := "rmi";
next file_loop;
when "bwm " => -- bwm
read_ea(iline, nblk);
xmicmd := "wmi";
next file_loop;
when "rr| " => -- rr[0-7]
ifunc := c_cpfunc_rreg;
irnum := slv(to_unsigned(rind, 3));
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wr| " => -- wr[0-7]
ifunc := c_cpfunc_wreg;
irnum := slv(to_unsigned(rind, 3));
readoct_ea(iline, idin);
-- Note: there are no field definitions for wal, wah, wibrb because
-- there is no corresponding cp command. Therefore the
-- rbus field definitions are used here
when "wal " => -- wal
readoct_ea(iline, idin);
r_addr := (others=>'0'); -- write to al clears ah !!
r_ena_22bit := '0';
r_ena_ubmap := '0';
r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr);
testempty_ea(iline);
next file_loop;
when "wah " => -- wah
readoct_ea(iline, idin);
r_addr(21 downto 16) := idin(c_ah_rbf_addr);
r_ena_22bit := idin(c_ah_rbf_ena_22bit);
r_ena_ubmap := idin(c_ah_rbf_ena_ubmap);
testempty_ea(iline);
next file_loop;
when "wibrb " => -- wibrb
readoct_ea(iline, idin);
r_ibrbase := idin(c_ibrb_ibf_base);
if idin(c_ibrb_ibf_be) /= "00" then
r_ibrbe := idin(c_ibrb_ibf_be);
else
r_ibrbe := "11";
end if;
testempty_ea(iline);
next file_loop;
when "rm " => -- rm
ifunc := c_cpfunc_rmem;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "rmi " => -- rmi
ifunc := c_cpfunc_rmem;
imemi := true;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wm " => -- wm
ifunc := c_cpfunc_wmem;
readoct_ea(iline, idin);
when "wmi " => -- wmi
ifunc := c_cpfunc_wmem;
imemi := true;
readoct_ea(iline, idin);
when "ribr " => -- ribr
ifunc := c_cpfunc_rmem;
idoibr := true;
readoct_ea(iline, ioff);
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wibr " => -- wibr
ifunc := c_cpfunc_wmem;
idoibr := true;
readoct_ea(iline, ioff);
readoct_ea(iline, idin);
when "rps " => -- rps
ifunc := c_cpfunc_rpsw;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wps " => -- wps
ifunc := c_cpfunc_wpsw;
readoct_ea(iline, idin);
-- Note: in old version 'sta addr' was an atomic operation, loading
-- the pc and starting the cpu. Now this is action is two step
-- first a wpc followed by a 'sta'.
when "stapc " => -- stapc
ifunc := c_cpfunc_wreg;
irnum := c_gpr_pc;
readoct_ea(iline, idin);
idosta := '1'; -- request 'sta' to be done next
when "sta " => -- sta
ifunc := c_cpfunc_sta;
when "sto " => -- sto
ifunc := c_cpfunc_sto;
when "cont " => -- cont
ifunc := c_cpfunc_cont;
when "step " => -- step
ifunc := c_cpfunc_step;
iwtstp := true;
when "rst " => -- rst
ifunc := c_cpfunc_rst;
when "wtgo " => -- wtgo
iwtgo := true;
ireq := false; -- no cp request !
when "wtlam " => -- wtlam (ignore it)
readempty(iline);
next file_loop;
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
end if;
testempty_ea(iline);
end if;
if idoibr then
CP_ADDR_addr(15 downto 13) <= "111";
CP_ADDR_addr(c_ibrb_ibf_base) <= r_ibrbase;
CP_ADDR_addr(5 downto 1) <= ioff(5 downto 1);
CP_ADDR_racc <= '1';
CP_ADDR_be <= r_ibrbe;
CP_ADDR_ena_22bit <= '0';
CP_ADDR_ena_ubmap <= '0';
else
CP_ADDR_addr <= r_addr;
CP_ADDR_racc <= '0';
CP_ADDR_be <= "11";
CP_ADDR_ena_22bit <= r_ena_22bit;
CP_ADDR_ena_ubmap <= r_ena_ubmap;
end if;
if ireq then
CP_CNTL_req <= '1';
CP_CNTL_func <= ifunc;
CP_CNTL_rnum <= irnum;
end if;
if ichk then
CP_DIN <= (others=>'0');
R_CHKDAT <= idin;
R_CHKMSK <= imsk;
R_CHKREQ <= '1';
else
CP_DIN <= idin;
R_CHKREQ <= '0';
end if;
R_WAITCMD <= '0';
R_WAITSTEP <= '0';
R_WAITGO <= '0';
if iwtgo then
idelta := to_go;
R_WAITGO <= '1';
elsif iwtstp then
idelta := to_stp;
R_WAITSTEP <= '1';
else
idelta := to_cmd;
R_WAITCMD <= '1';
end if;
wait for clock_period;
CP_CNTL_req <= '0';
dcycle := 1;
while idelta>0 and R_WAITOK='0' loop
wait for clock_period;
dcycle := dcycle + 1;
idelta := idelta - 1;
end loop;
if imemi then -- rmi or wmi seen ? then inc ar
r_addr := slv(unsigned(r_addr) + 1);
end if;
write(oline, dcycle, right, 4);
write(oline, string'(" "));
if ireq then
case ifunc is
when c_cpfunc_rreg => write(oline, string'("rreg"));
when c_cpfunc_wreg => write(oline, string'("wreg"));
when c_cpfunc_rpsw => write(oline, string'("rpsw"));
when c_cpfunc_wpsw => write(oline, string'("wpsw"));
when c_cpfunc_rmem =>
if idoibr then
write(oline, string'("ribr"));
else
write(oline, string'("rmem"));
end if;
when c_cpfunc_wmem =>
if idoibr then
write(oline, string'("wibr"));
else
write(oline, string'("wmem"));
end if;
when c_cpfunc_sta => write(oline, string'("sta "));
when c_cpfunc_sto => write(oline, string'("sto "));
when c_cpfunc_cont => write(oline, string'("cont"));
when c_cpfunc_step => write(oline, string'("step"));
when c_cpfunc_rst => write(oline, string'("rst "));
when others =>
write(oline, string'("?"));
writeoct(oline, ifunc, right, 2);
write(oline, string'("?"));
end case;
writeoct(oline, irnum, right, 2);
writeoct(oline, idin, right, 8);
else
write(oline, string'("---- - ------"));
end if;
write(oline, R_CP_STAT.cmdbusy, right, 3);
write(oline, R_CP_STAT.cmdack, right, 2);
write(oline, R_CP_STAT.cmderr, right, 2);
write(oline, R_CP_STAT.cmdmerr, right, 2);
writeoct(oline, R_CP_DOUT, right, 8);
write(oline, R_CP_STAT.cpugo, right, 3);
write(oline, R_CP_STAT.cpustep, right, 2);
write(oline, R_CP_STAT.cpuhalt, right, 2);
writeoct(oline, R_CP_STAT.cpurust, right, 3);
if R_WAITOK = '1' then
if R_CP_STAT.cmderr='1' or icerr=1 then
if R_CP_STAT.cmderr='1' and icerr=0 then
write(oline, string'(" FAIL CMDERR"));
elsif R_CP_STAT.cmderr='1' and icerr=1 then
write(oline, string'(" CHECK CMDERR SEEN"));
elsif R_CP_STAT.cmderr='0' and icerr=1 then
write(oline, string'(" FAIL CMDERR EXPECTED,MISSED"));
end if;
elsif R_CP_STAT.cmdmerr='1' or imerr=1 then
if R_CP_STAT.cmdmerr='1' and imerr=0 then
write(oline, string'(" FAIL CMDMERR"));
elsif R_CP_STAT.cmdmerr='1' and imerr=1 then
write(oline, string'(" CHECK CMDMERR SEEN"));
elsif R_CP_STAT.cmdmerr='0' and imerr=1 then
write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED"));
end if;
elsif R_CHKREQ='1' then
if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then
write(oline, string'(" CHECK OK"));
else
write(oline, string'(" CHECK FAILED, d="));
writeoct(oline, R_CHKDAT, right, 7);
if unsigned(R_CHKMSK)/=0 then
write(oline, string'(","));
writeoct(oline, R_CHKMSK, right, 7);
end if;
end if;
end if;
if iwtgo then
write(oline, string'(" WAIT GO OK "));
elsif iwtstp then
write(oline, string'(" WAIT STEP OK"));
end if;
else
write(oline, string'(" WAIT FAILED (will reset)"));
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
end if;
writeline(output, oline);
end loop;
wait for 4*clock_period;
CLK_STOP <= '1';
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
R_WAITOK <= '0';
if R_WAITCMD = '1' then
if CP_STAT_cmdack = '1' then
R_WAITOK <= '1';
end if;
elsif R_WAITGO = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then
R_WAITOK <= '1';
end if;
elsif R_WAITSTEP = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then
R_WAITOK <= '1';
end if;
end if;
R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy;
R_CP_STAT.cmdack <= CP_STAT_cmdack;
R_CP_STAT.cmderr <= CP_STAT_cmderr;
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr;
R_CP_STAT.cpugo <= CP_STAT_cpugo;
R_CP_STAT.cpustep <= CP_STAT_cpustep;
R_CP_STAT.cpuhalt <= CP_STAT_cpuhalt;
R_CP_STAT.cpurust <= CP_STAT_cpurust;
R_CP_DOUT <= CP_DOUT;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
f5b00d7ab67370257f2ed5e4da968675
| 0.483981 | 3.617025 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/pdp11_tmu.vhd
| 1 | 8,622 |
-- $Id: pdp11_tmu.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_tmu - sim
-- Description: pdp11: trace and monitor unit
--
-- Dependencies: -
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.7 now numeric_std clean
-- 2010-10-17 333 1.0.6 use ibus V2 interface
-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
-- 2008-04-19 137 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end pdp11_tmu;
architecture sim of pdp11_tmu is
signal R_FIRST : slbit := '1';
begin
proc_tm: process (CLK)
variable oline : line;
variable ipsw : slv16 := (others=>'0');
variable ibaddr : slv16 := (others=>'0');
variable emaddr : slv22 := (others=>'0');
variable dp_ireg_we_last : slbit := '0';
variable vm_ibsres_busy_last : slbit := '0';
variable vm_ibsres_ack_last : slbit := '0';
variable wcycle : boolean := false;
file ofile : text open write_mode is "tmu_ofile";
begin
if rising_edge(CLK) then
if R_FIRST = '1' then
R_FIRST <= '0';
write(oline, string'("#"));
write(oline, string'(" clkcycle:d"));
write(oline, string'(" cpu:o"));
write(oline, string'(" dp.pc:o"));
write(oline, string'(" dp.psw:o"));
write(oline, string'(" dp.ireg:o"));
write(oline, string'(" dp.ireg_we:b"));
write(oline, string'(" dp.ireg_we_last:b")); -- is ireg_we last cycle
write(oline, string'(" dp.dsrc:o"));
write(oline, string'(" dp.ddst:o"));
write(oline, string'(" dp.dtmp:o"));
write(oline, string'(" dp.dres:o"));
write(oline, string'(" dp.gpr_adst:o"));
write(oline, string'(" dp.gpr_mode:o"));
write(oline, string'(" dp.gpr_bytop:b"));
write(oline, string'(" dp.gpr_we:b"));
write(oline, string'(" vm.ibmreq.aval:b"));
write(oline, string'(" vm.ibmreq.re:b"));
write(oline, string'(" vm.ibmreq.we:b"));
write(oline, string'(" vm.ibmreq.rmw:b"));
write(oline, string'(" vm.ibmreq.be0:b"));
write(oline, string'(" vm.ibmreq.be1:b"));
write(oline, string'(" vm.ibmreq.cacc:b"));
write(oline, string'(" vm.ibmreq.racc:b"));
write(oline, string'(" vm.ibmreq.addr:o"));
write(oline, string'(" vm.ibmreq.din:o"));
write(oline, string'(" vm.ibsres.ack:b"));
write(oline, string'(" vm.ibsres.busy:b"));
write(oline, string'(" vm.ibsres.dout:o"));
write(oline, string'(" co.cpugo:b"));
write(oline, string'(" co.cpuhalt:b"));
write(oline, string'(" sy.emmreq.req:b"));
write(oline, string'(" sy.emmreq.we:b"));
write(oline, string'(" sy.emmreq.be:b"));
write(oline, string'(" sy.emmreq.cancel:b"));
write(oline, string'(" sy.emmreq.addr:o"));
write(oline, string'(" sy.emmreq.din:o"));
write(oline, string'(" sy.emsres.ack_r:b"));
write(oline, string'(" sy.emsres.ack_w:b"));
write(oline, string'(" sy.emsres.dout:o"));
write(oline, string'(" sy.chit:b"));
writeline(ofile, oline);
end if;
ipsw := (others=>'0');
ipsw(psw_ibf_cmode) := DM_STAT_DP.psw.cmode;
ipsw(psw_ibf_pmode) := DM_STAT_DP.psw.pmode;
ipsw(psw_ibf_rset) := DM_STAT_DP.psw.rset;
ipsw(psw_ibf_pri) := DM_STAT_DP.psw.pri;
ipsw(psw_ibf_tflag) := DM_STAT_DP.psw.tflag;
ipsw(psw_ibf_cc) := DM_STAT_DP.psw.cc;
ibaddr := "1110000000000000";
ibaddr(DM_STAT_VM.ibmreq.addr'range) := DM_STAT_VM.ibmreq.addr;
emaddr := (others=>'0');
emaddr(DM_STAT_SY.emmreq.addr'range) := DM_STAT_SY.emmreq.addr;
wcycle := false;
if dp_ireg_we_last='1' or
DM_STAT_DP.gpr_we='1' or
DM_STAT_SY.emmreq.req='1' or
DM_STAT_SY.emsres.ack_r='1' or
DM_STAT_SY.emsres.ack_w='1' or
DM_STAT_SY.emmreq.cancel='1' or
DM_STAT_VM.ibmreq.re='1' or
DM_STAT_VM.ibmreq.we='1' or
DM_STAT_VM.ibsres.ack='1'
then
wcycle := true;
end if;
if DM_STAT_VM.ibsres.busy='0' and
(vm_ibsres_busy_last='1' and vm_ibsres_ack_last='0')
then
wcycle := true;
end if;
if ENA = '0' then -- if not enabled
wcycle := false; -- force to not logged...
end if;
if wcycle then
write(oline, to_integer(unsigned(SB_CLKCYCLE)), right, 9);
write(oline, string'(" 0"));
writeoct(oline, DM_STAT_DP.pc, right, 7);
writeoct(oline, ipsw, right, 7);
writeoct(oline, DM_STAT_DP.ireg, right, 7);
write(oline, DM_STAT_DP.ireg_we, right, 2);
write(oline, dp_ireg_we_last, right, 2);
writeoct(oline, DM_STAT_DP.dsrc, right, 7);
writeoct(oline, DM_STAT_DP.ddst, right, 7);
writeoct(oline, DM_STAT_DP.dtmp, right, 7);
writeoct(oline, DM_STAT_DP.dres, right, 7);
writeoct(oline, DM_STAT_DP.gpr_adst, right, 2);
writeoct(oline, DM_STAT_DP.gpr_mode, right, 2);
write(oline, DM_STAT_DP.gpr_bytop, right, 2);
write(oline, DM_STAT_DP.gpr_we, right, 2);
write(oline, DM_STAT_VM.ibmreq.aval, right, 2);
write(oline, DM_STAT_VM.ibmreq.re, right, 2);
write(oline, DM_STAT_VM.ibmreq.we, right, 2);
write(oline, DM_STAT_VM.ibmreq.rmw, right, 2);
write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
writeoct(oline, ibaddr, right, 7);
writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
write(oline, DM_STAT_VM.ibsres.ack, right, 2);
write(oline, DM_STAT_VM.ibsres.busy, right, 2);
writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7);
write(oline, DM_STAT_CO.cpugo, right, 2);
write(oline, DM_STAT_CO.cpuhalt, right, 2);
write(oline, DM_STAT_SY.emmreq.req, right, 2);
write(oline, DM_STAT_SY.emmreq.we, right, 2);
write(oline, DM_STAT_SY.emmreq.be, right, 3);
write(oline, DM_STAT_SY.emmreq.cancel, right, 2);
writeoct(oline, emaddr, right, 9);
writeoct(oline, DM_STAT_SY.emmreq.din, right, 7);
write(oline, DM_STAT_SY.emsres.ack_r, right, 2);
write(oline, DM_STAT_SY.emsres.ack_w, right, 2);
writeoct(oline, DM_STAT_SY.emsres.dout, right, 7);
write(oline, DM_STAT_SY.chit, right, 2);
writeline(ofile, oline);
end if;
dp_ireg_we_last := DM_STAT_DP.ireg_we;
vm_ibsres_busy_last := DM_STAT_VM.ibsres.busy;
vm_ibsres_ack_last := DM_STAT_VM.ibsres.ack;
end if;
end process proc_tm;
end sim;
|
gpl-2.0
|
eb2047c0e33a667a28d4ba0e71ae96b7
| 0.560891 | 3.22077 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/pwm/pwm16.vhd
| 1 | 3,873 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- 16-bit PWM using two-process design pattern
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Type and component definition package
-------------------------------------------------------------------------------
package pwm16_comp is
type pwm16_in_type is record
duty_cycle : std_logic_vector(15 downto 0);
end record;
component pwm16
port (
clk : in std_logic;
rst : in std_logic;
d : in pwm16_in_type;
pwm : out std_logic
);
end component;
end package;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pwm16_comp.all;
-------------------------------------------------------------------------------
ENTITY pwm16 is
-------------------------------------------------------------------------------
port (
clk : in std_logic;
rst : in std_logic;
d : in pwm16_in_type;
pwm : out std_logic
);
end pwm16;
-------------------------------------------------------------------------------
ARCHITECTURE two_proc of pwm16 is
-------------------------------------------------------------------------------
type reg_type is record
pwm_cnt : unsigned(15 downto 0); -- pwm counter
end record;
signal reg_out, reg_in : reg_type;
begin
-------------------------------------------------------------------------------
COMBINATIONAL : process(d, reg_out)
-------------------------------------------------------------------------------
variable tmp_var : reg_type;
begin
tmp_var := reg_out; -- default assignments
---algorithm-------------------------------------------------------------
-- PWM: reset on overflow, increment otherwise
if (tmp_var.pwm_cnt = 2**16-1) then
tmp_var.pwm_cnt := (others => '0');
else
tmp_var.pwm_cnt := reg_out.pwm_cnt + 1;
end if;
-- compare and drive output
if (tmp_var.pwm_cnt >= unsigned(d.duty_cycle)) then
pwm <= '0';
else
pwm <= '1';
end if;
-------------------------------------------------------------------------
reg_in <= tmp_var; -- drive register inputs
end process COMBINATIONAL;
-------------------------------------------------------------------------------
REGISTERS : process(clk,rst)
-------------------------------------------------------------------------------
begin
if rising_edge(clk) then
if (rst = '1') then
reg_out.pwm_cnt <= (others => '0');
else
reg_out <= reg_in;
end if;
end if;
end process REGISTERS;
end two_proc;
|
gpl-3.0
|
831bcea7b65027d6e97613221c38dc77
| 0.40692 | 5.198658 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/LUT/example_design/LUT_prod_exdes.vhd
| 6 | 5,285 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
|
gpl-2.0
|
1979a3e63aee53b16008bd06233f3e9b
| 0.500473 | 4.693606 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd
| 1 | 1,605 |
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
gpl-2.0
|
9cb730f89d64f603661d533ed7a52ba1
| 0.639252 | 3.895631 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/xlib/iob_reg_i.vhd
| 2 | 1,852 |
-- $Id: iob_reg_i.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, input only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end iob_reg_i;
architecture syn of iob_reg_i is
begin
IOB : iob_reg_i_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DI(0) => DI,
PAD(0) => PAD
);
end syn;
|
gpl-2.0
|
befd304b3f2504c85947e7b698b76fc4
| 0.542657 | 3.748988 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/SEU22.vhd
| 1 | 470 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEU22 is
Port ( disp22 : in STD_LOGIC_VECTOR (21 downto 0);
seuOut : out STD_LOGIC_VECTOR (31 downto 0)
);
end SEU22;
architecture Behavioral of SEU22 is
begin
seuOut(21 downto 0) <= disp22;
process(disp22) begin
if(disp22(21) = '0') then
seuOut(31 downto 22) <= (others => '0');
else
seuOut(31 downto 22) <= (others=>'1');
end if;
end process;
end Behavioral;
|
mit
|
175481349d1c6759c62a5210befe74c0
| 0.614894 | 3.154362 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd
| 2 | 2,738 |
-- $Id: sys_conf_sim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_s3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce
-- 2008-02-23 118 1.1 add memory config
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
25dd5de7a9fd778ae0963a385ba79ba2
| 0.586925 | 3.62649 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Talleres/TallerVhdl/registro.vhd
| 1 | 554 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity registro is
Port ( reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (31 downto 0);
clk : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (31 downto 0));
end registro;
architecture Behavioral of registro is
signal init: std_logic_vector(31 downto 0):=(others=>'0');
begin
process(reset, clk, data_in)
begin
if reset = '1' then
data_out <= init;
else
if rising_edge(clk) then
data_out <= data_in;
end if;
end if;
end process;
end Behavioral;
|
mit
|
9070ac58454453ec301d91452444a91c
| 0.637184 | 3.043956 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
miscellaneous/Hall_sensor.vhd
| 1 | 1,916 |
------------------------------------------------------------------------------------------------------------------------
-- Model Title: Hall sensor
-- Entity Name: hall_sensor
-- Author: <[email protected]>
-- Created:
-- Last update: 2020/07/08 Schaeftlarn
--
------------------------------------------------------------------------------------------------------------------------
-- Description: small signal model of Hall sensor: Vh == Binput*Rh*Ic/d
-- simulated with systemvision.com
--
-- SMD HS-420 Datasheet:
-- Magnetic sensitivity: VH=100…330 mV/kG at Ic=5mA => -(2...6.6) mV/T/mA
-- input resistance: Rin=240...550 Ohm
-- output resistance: Rout=240...550 Ohm
-- control current: Ic max=20 mA / Ic nom=5 mA
-- operating temperature range: -40...110 degC
-- meaning of temperature coefficient of resistance (0...40 degC): -1.8
-- meaning of temperature coefficient of VH (0...40 degC): -1.8
--
-- Indium Antimonide:
-- Rh= -7.2e-4 m3/C; d=0.4 mm => Magnetic sensitivity: VH=Rh*Ic/d= -1.8 mV/T/mA
--
------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.electrical_systems.all;
use IEEE.energy_systems.all;
entity hall_sensor is
generic (key : real := 1.0); -- key [no units]
port (quantity Binput: in real;
terminal e_ic1, e_ic2: electrical;
terminal e_vh1, e_vh2: electrical);
end entity hall_sensor;
architecture basic of hall_sensor is
quantity vc across ic through e_ic1 to e_ic2;
quantity vh across ih through e_vh1 to e_vh2;
-------
-- model parameters
constant Rin:real:= 400.0; -- input resistance: Rin, Ohm
constant Rh:real:= -7.2e-4; -- Indium Antimonide Rh
constant d:real:= 0.4e-3; -- thickness, d
begin
vc == Rin*ic;
vh == Binput*Rh*ic/d;
--- for information only
--VH == Rh*ic/d; -- magnetic sensitivity
end architecture basic;
|
mit
|
a1e766b90bcd9ccdb3fba60465dde305
| 0.54232 | 3.531365 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd
| 1 | 9,196 |
-- $Id: tbcore_rlink_dcm.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbcore_rlink_dcm - sim
-- Description: DCM aware core for a rlink_cext based test bench
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
--
-- To test: generic, any rlink_cext based target
--
-- Target Devices: generic
-- Tool versions: 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 rename rritb_core_dcm->tbcore_rlink_dcm; rbv3 names
-- 2010-11-13 338 1.1 First DCM aware version, cloned from rritb_core
-- 2010-06-05 301 1.1.2 renamed .rpmon -> .rbmon
-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.rlink_cext_vhpi.all;
entity tbcore_rlink_dcm is -- dcm aware core of rlink_cext based tb
generic (
CLKOSC_PERIOD : time := 20 ns; -- clock osc period
CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLKOSC : out slbit; -- clock osc
CLKSYS : in slbit; -- DCM derived system clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end tbcore_rlink_dcm;
architecture sim of tbcore_rlink_dcm is
signal CLK_STOP : slbit := '0';
begin
CLKGEN : simclk
generic map (
PERIOD => CLKOSC_PERIOD,
OFFSET => CLKOSC_OFFSET)
port map (
CLK => CLKOSC,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt
port map (
CLK => CLKSYS,
CLK_CYCLE => SB_CLKCYCLE
);
proc_conf: process
file fconf : text open read_mode is "rlink_cext_conf";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable ien : slbit := '0';
variable ibit : integer := 0;
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
SB_CNTL <= (others=>'L');
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
file_loop: while not endfile(fconf) loop
readline (fconf, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
end if;
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rbmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rbmon) <= 'L';
end if;
when ".sinit" => -- .sinit
readgen_ea(iline, iaddr, 8);
readgen_ea(iline, idata, 8);
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= 'H';
wait for 0 ns;
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
wait for 0 ns;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
wait; -- halt process here
end process proc_conf;
proc_stim: process
variable t_lastclksys : time := 0 ns;
variable clksys_period : time := 0 ns;
variable icycle : integer := 0;
variable irxint : integer := 0;
variable irxslv : slv24 := (others=>'0');
variable ibit : integer := 0;
variable oline : line;
variable r_sb_cntl : slv16 := (others=>'Z');
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
-- just wait for 10 CLKSYS cycles
for i in 1 to 10 loop
wait until rising_edge(CLKSYS);
clksys_period := now - t_lastclksys;
t_lastclksys := now;
end loop; -- i
stim_loop: loop
wait until rising_edge(CLKSYS);
clksys_period := now - t_lastclksys;
t_lastclksys := now;
wait for clksys_period-SETUP_TIME;
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
icycle := to_integer(unsigned(SB_CLKCYCLE));
RX_VAL <= '0';
if RX_HOLD = '0' then
irxint := rlink_cext_getbyte(icycle);
if irxint >= 0 then
if irxint <= 16#ff# then -- normal data byte
RX_DATA <= slv(to_unsigned(irxint, 8));
RX_VAL <= '1';
elsif irxint >= 16#1000000# then -- out-of-band message
irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24));
iaddr := irxslv(23 downto 16);
idata := irxslv(15 downto 0);
writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG");
write(oline, irxslv(23 downto 16), right, 9);
write(oline, irxslv(15 downto 8), right, 9);
write(oline, irxslv( 7 downto 0), right, 9);
write(oline, string'(" : "));
writeoct(oline, iaddr, right, 3);
writeoct(oline, idata, right, 7);
writeline(output, oline);
if unsigned(iaddr) = 0 then
ibit := to_integer(unsigned(idata(15 downto 8)));
r_sb_cntl(ibit) := idata(0);
else
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= '1';
wait for 0 ns;
SB_VAL <= 'Z';
wait for 0 ns;
end if;
end if;
elsif irxint = -1 then -- end-of-file seen
exit stim_loop;
else
report "rlink_cext_getbyte error: " & integer'image(-irxint)
severity failure;
end if;
end if;
SB_CNTL <= r_sb_cntl;
end loop;
-- just wait for 50 CLKSYS cycles
for i in 1 to 50 loop
wait until rising_edge(CLKSYS);
end loop; -- i
CLK_STOP <= '1';
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable itxdata : integer := 0;
variable itxrc : integer := 0;
variable oline : line;
begin
loop
wait until rising_edge(CLKSYS);
wait for C2OUT_TIME;
if TX_ENA = '1' then
itxdata := to_integer(unsigned(TX_DATA));
itxrc := rlink_cext_putbyte(itxdata);
assert itxrc=0
report "rlink_cext_putbyte error: " & integer'image(itxrc)
severity failure;
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
bbc3dff702565587fac1bf4cb98ae328
| 0.522727 | 3.888372 | false | false | false | false |
armandas/FPGalaxy
|
bin2bcd.vhd
| 2 | 3,219 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bin2bcd is
generic(N_BIN: positive := 16);
port(
clk, not_reset: in std_logic;
binary_in: in std_logic_vector(N_BIN - 1 downto 0);
bcd0, bcd1, bcd2, bcd3, bcd4: out std_logic_vector(3 downto 0)
);
end bin2bcd;
architecture behaviour of bin2bcd is
type states is (start, shift, done);
signal state, state_next: states;
signal binary, binary_next: std_logic_vector(N_BIN - 1 downto 0);
signal bcds, bcds_reg, bcds_next: std_logic_vector(19 downto 0);
-- output register keep output constant during conversion
signal bcds_out_reg, bcds_out_reg_next: std_logic_vector(19 downto 0);
-- need to keep track of shifts
signal shift_counter, shift_counter_next: natural range 0 to N_BIN;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
binary <= (others => '0');
bcds <= (others => '0');
state <= start;
bcds_out_reg <= (others => '0');
shift_counter <= 0;
elsif falling_edge(clk) then
binary <= binary_next;
bcds <= bcds_next;
state <= state_next;
bcds_out_reg <= bcds_out_reg_next;
shift_counter <= shift_counter_next;
end if;
end process;
convert:
process(state, binary, binary_in, bcds, bcds_reg, shift_counter)
begin
state_next <= state;
bcds_next <= bcds;
binary_next <= binary;
shift_counter_next <= shift_counter;
case state is
when start =>
state_next <= shift;
binary_next <= binary_in;
bcds_next <= (others => '0');
shift_counter_next <= 0;
when shift =>
if shift_counter = N_BIN then
state_next <= done;
else
binary_next <= binary(N_BIN - 2 downto 0) & 'L';
bcds_next <= bcds_reg(18 downto 0) & binary(N_BIN - 1);
shift_counter_next <= shift_counter + 1;
end if;
when done =>
state_next <= start;
end case;
end process;
bcds_reg(19 downto 16) <= bcds(19 downto 16) + 3 when bcds(19 downto 16) > 4 else
bcds(19 downto 16);
bcds_reg(15 downto 12) <= bcds(15 downto 12) + 3 when bcds(15 downto 12) > 4 else
bcds(15 downto 12);
bcds_reg(11 downto 8) <= bcds(11 downto 8) + 3 when bcds(11 downto 8) > 4 else
bcds(11 downto 8);
bcds_reg(7 downto 4) <= bcds(7 downto 4) + 3 when bcds(7 downto 4) > 4 else
bcds(7 downto 4);
bcds_reg(3 downto 0) <= bcds(3 downto 0) + 3 when bcds(3 downto 0) > 4 else
bcds(3 downto 0);
bcds_out_reg_next <= bcds when state = done else
bcds_out_reg;
bcd4 <= bcds_out_reg(19 downto 16);
bcd3 <= bcds_out_reg(15 downto 12);
bcd2 <= bcds_out_reg(11 downto 8);
bcd1 <= bcds_out_reg(7 downto 4);
bcd0 <= bcds_out_reg(3 downto 0);
end behaviour;
|
bsd-2-clause
|
0e59bd7fa185c8630b81734a546d3952
| 0.529357 | 3.760514 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/spi/spi.vhd
| 1 | 4,058 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- S P I E A S Y C O R E
-- (spi.vhd)
--
-- Structural
--
-- Adapts the verilog spi module to vhdl and the wbs/wbm types
--
-- The reset input is inverted to be active-high
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
ENTITY spi is
-------------------------------------------------------------------------------
port (
-- WISHBONE interface (with clock input)
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- SPI master interface
sck_out : out std_logic;
mosi_out : out std_logic;
miso_in : in std_logic
);
end spi;
-------------------------------------------------------------------------------
ARCHITECTURE structural of spi is
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
COMPONENT simple_spi_top is
-- this component is the link to the verilog module.
-- here, the signal names from simple_spi_top.v are used
-------------------------------------------------------------------------------
port (
-- WISHBONE interface
clk_i : in std_logic; -- clock
rst_i : in std_logic; -- reset (asynchronous active low)
cyc_i : in std_logic; -- cycle
stb_i : in std_logic; -- strobe
adr_i : in std_logic_vector(1 downto 0); -- address
we_i : in std_logic; -- write enable
dat_i : in std_logic_vector(7 downto 0); -- data input
dat_o : out std_logic_vector(7 downto 0); -- data output
ack_o : out std_logic; -- bus termination
inta_o : out std_logic; -- interrupt output
-- SPI port
sck_o : out std_logic; -- serial clock output
mosi_o : out std_logic; -- MasterOut SlaveIN
miso_i : in std_logic -- MasterIn SlaveOut
);
END COMPONENT;
signal rst_active_low : std_logic;
--------------------------------------------------------------------------------
begin -- architecture structural
-------------------------------------------------------------------------------
-- invert reset signal
rst_active_low <= not wbs_in.rst;
-------------------------------------------------------------------------------
SPI_CORE : simple_spi_top
-------------------------------------------------------------------------------
port map (
clk_i => wbs_in.clk,
-- WISHBONE interface
rst_i => rst_active_low,
cyc_i => wbs_in.cyc,
stb_i => wbs_in.stb,
adr_i => wbs_in.adr(1 downto 0),
we_i => wbs_in.we,
dat_i => wbs_in.dat,
dat_o => wbs_out.dat,
ack_o => wbs_out.ack,
inta_o => wbs_out.irq,
-- SPI port
sck_o => sck_out,
mosi_o => mosi_out,
miso_i => miso_in
);
end structural;
|
gpl-3.0
|
73966e3ad11dfdd7b6b4f22523e058ac
| 0.442336 | 4.523969 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/i2c_master/i2c_master_byte_ctrl.vhd
| 1 | 12,626 |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $
--
-- $Date: 2004-02-18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
|
gpl-3.0
|
94c85e0daa96b8b087e794f847fded9d
| 0.460082 | 3.869445 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega1/Procesador_0.vhd
| 1 | 3,730 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Processor is
Port ( rst : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (31 downto 0);
clk : in STD_LOGIC);
end Processor;
architecture Behavioral of Processor is
signal out_nPC: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal data_in: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal pc_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal im_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal seu_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal imm13_aux: STD_LOGIC_VECTOR(12 downto 0):=(others=>'0');--en formato3
--el inmmediato va del bit 0 al 12
signal crs1_aux: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal crs2_aux: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal mux_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal cpu_out: STD_LOGIC_VECTOR(5 downto 0):=(others=>'0');
signal alu_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
COMPONENT PC
PORT(
rst : IN std_logic;
clk : IN std_logic;
DAT_in : IN std_logic_vector(31 downto 0);
DAT_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Sumador
PORT(
operador1 : IN std_logic_vector(31 downto 0);
operador2 : IN std_logic_vector(31 downto 0);
resultado : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
rst : in STD_LOGIC;
addr : IN std_logic_vector(31 downto 0);
data : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Mod5Seu
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm32 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT MUX
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm13 : IN std_logic_vector(31 downto 0);
i : IN std_logic;
Oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rst : in STD_LOGIC;
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
dwr : IN std_logic_vector(31 downto 0);
ORs1 : OUT std_logic_vector(31 downto 0);
ORs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
Salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
aluop : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
begin
Inst_PC: PC PORT MAP(
rst => rst,
clk => clk,
DAT_in => out_nPC,
DAT_out => pc_out
);
Inst_nPC: PC PORT MAP(
rst => rst,
clk => clk,
DAT_in => data_in,
DAT_out => out_nPC
);
Inst_Sumador: Sumador PORT MAP(
operador1 => "00000000000000000000000000000001",
operador2 => pc_out,
resultado => data_in
);
Inst_IM: IM PORT MAP(
rst => rst,
addr => pc_out,
data => im_out
);
Inst_SEU: Mod5Seu PORT MAP(
imm13 => im_out(12 downto 0),
SEUimm32 => seu_out
);
Inst_MUX: MUX PORT MAP(
Crs2 => crs2_aux,
SEUimm13 => seu_out,
i => im_out(13),
Oper2 => mux_out
);
Inst_RF: RF PORT MAP(
rst => rst,
rs1 => im_out(18 downto 14),
rs2 => im_out(4 downto 0),
rd => im_out(29 downto 25),
dwr => alu_out,
ORs1 => crs1_aux,
ORs2 => crs2_aux
);
Inst_ALU: ALU PORT MAP(
Oper1 => crs1_aux,
Oper2 => mux_out,
ALUOP => cpu_out,
Salida => alu_out
);
Inst_CU: CU PORT MAP(
op => im_out(31 downto 30),
op3 => im_out(24 downto 19),
aluop => cpu_out
);
data_out <= alu_out;
end Behavioral;
|
mit
|
38640e03607d6be1797d7bb4a4e9bf8a
| 0.619035 | 2.815094 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/enable_controller.vhd
| 1 | 3,065 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- E N A B L E C O N T R O L L E R
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity enable_controller is
port (
-- mcu interface
fpga_active_i : in std_logic;
mcu_active_o : out std_logic;
-- soc interface
mcu_select_i : in std_logic;
fifo_enable_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end enable_controller;
architecture fsm of enable_controller is
type state_type is (mcu_active, fpga_active, switch_to_mcu);
signal current_state, next_state : state_type;
begin
-------------------------------------------------
-- Combinational next state and output logic
-------------------------------------------------
STATEMACHINE : process (current_state, fpga_active_i, mcu_select_i) is
begin
case current_state is
when mcu_active =>
fifo_enable_o <= '0';
mcu_active_o <= '1';
if rising_edge(fpga_active_i) then
next_state <= fpga_active;
else
next_state <= mcu_active;
end if;
when fpga_active =>
fifo_enable_o <= '1';
mcu_active_o <= '0';
if mcu_select_i = '1' then
next_state <= switch_to_mcu;
else
next_state <= fpga_active;
end if;
when switch_to_mcu =>
fifo_enable_o <= '1';
mcu_active_o <= '1';
if fpga_active_i = '1' then
next_state <= switch_to_mcu;
else
next_state <= mcu_active;
end if;
end case;
end process STATEMACHINE;
-------------------------------------------------------------------
-- State register with sync reset. Resets to mcu_active state
-------------------------------------------------------------------
STATE_REGISTER : process (clk_i, rst_i) is
begin
if (rising_edge(clk_i)) then
if (rst_i = '1') then
current_state <= mcu_active;
else
current_state <= next_state;
end if;
end if;
end process STATE_REGISTER;
end fsm;
|
gpl-3.0
|
fa3947839655e785834aa24ee5a03212
| 0.502773 | 4.304775 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL source files/Decoder_1hot_3-to-8.vhd
| 1 | 1,624 |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
--
-- File: Decoder_1hot_3-to-8.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- 1-hot decoder: decodes input number and makes only 1 output active (high),
-- while other outputs remain disabled (low)
-- Decoder operation is clocked to avoid output jittering.
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity decoder is
port (
reset_n: in std_logic;
input: in std_logic;
clk: in std_logic;
output: out std_logic_vector (7 downto 0)
);
end decoder;
architecture archi of decoder is
begin
state_control: process (RESET_N, CLK)
begin
if (RESET_N = '0') then
output <= "00000000";
elsif (rising_edge(clk)) then
case input is
when '0' => output <= "00000001";
when '1' => output <= "00000010";
when '2' => output <= "00000100";
when '3' => output <= "00001000";
when '4' => output <= "00010000";
when '5' => output <= "00100000";
when '6' => output <= "01000000";
when '7' => output <= "10000000";
when others => output <= "00000000";
end case;
end if;
end process;
end archi;
|
gpl-2.0
|
ef8b3601d9d7941f3ca1222942c7853c
| 0.521552 | 3.538126 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL stimulus files/BCD_decoder_testbench.vhd
| 1 | 7,986 |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
--
-- File: BCD_decoder_testbench.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- Testbench for 4/5 digits Integer-to-BCD decoder
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BCD_decoder_testbench is
GENERIC(
d_width : INTEGER := 24 -- data width
);
end BCD_decoder_testbench;
architecture behavioral of BCD_decoder_testbench is
constant SYSCLK_PERIOD : time := 20 ns; -- 50MHZ
constant SYSCLK_LF_PERIOD : time := 100 ns; -- 10MHZ
constant SYSCLK_Khz_PERIOD : time := 0.256 us; -- 3900 Khz. REAL FREQ is 39 Khz (T=25.6 us)
signal SYSCLK : std_logic := '0';
signal SYSCLK_LF : std_logic := '0';
signal SYSCLK_Khz : std_logic := '0';
signal NSYSRESET : std_logic := '0';
signal s_Latch_data_IN: std_logic;
signal s_X_Pos_Int_in: std_logic_vector(d_width-1 downto 0);
signal s_X_pos_Fract_in: std_logic_vector(d_width-1 downto 0);
signal s_Y_Pos_Int_in: std_logic_vector(d_width-1 downto 0);
signal s_Y_pos_Fract_in: std_logic_vector(d_width-1 downto 0);
signal s_Z_Pos_Int_in: std_logic_vector(d_width-1 downto 0);
signal s_Z_pos_Fract_in: std_logic_vector(d_width-1 downto 0);
signal s_A4_Pos_Int_in: std_logic_vector(d_width-1 downto 0);
signal s_A4_pos_Fract_in: std_logic_vector(d_width-1 downto 0);
signal s_active_axis: std_logic_vector (3 downto 0);
signal s_Position_to_decode: std_logic_vector(7 downto 0);
signal s_Data_ready_out: std_logic;
signal s_Position_Tx_gate: std_logic;
signal s_Pos_Int_dig12_out: std_logic_vector(7 downto 0);
signal s_Pos_Int_dig34_out: std_logic_vector(7 downto 0);
signal s_Pos_Int_dig56_out: std_logic_vector(7 downto 0);
signal s_Pos_Fract_dig12_out: std_logic_vector(7 downto 0);
signal s_Pos_Fract_dig34_out: std_logic_vector(7 downto 0);
component Position_INT_to_BCD_decoder
-- ports
port(
-- Inputs
RESET_N : in std_logic;
SCLK_IN : in std_logic;
SCLK_LF_IN : in std_logic;
SCLK_Hz_IN : in std_logic;
Latch_data_IN : in std_logic;
Data_ready_IN : in std_logic;
Pos_update_request : in std_logic;
Update_freq : in std_logic;
X_Pos_Int_in : in std_logic_vector(23 downto 0);
X_pos_Fract_in : in std_logic_vector(23 downto 0);
Y_Pos_Int_in : in std_logic_vector(23 downto 0);
Y_pos_Fract_in : in std_logic_vector(23 downto 0);
Z_Pos_Int_in : in std_logic_vector(23 downto 0);
Z_pos_Fract_in : in std_logic_vector(23 downto 0);
A4_Pos_Int_in : in std_logic_vector(23 downto 0);
A4_pos_Fract_in : in std_logic_vector(23 downto 0);
active_axis : in std_logic_vector(3 downto 0);
-- Outputs
Position_to_decode : out std_logic_vector(7 downto 0);
Data_ready_out : out std_logic;
Position_Tx_gate : out std_logic;
Pos_Int_dig12_out : out std_logic_vector(7 downto 0);
Pos_Int_dig34_out : out std_logic_vector(7 downto 0);
Pos_Int_dig56_out : out std_logic_vector(7 downto 0);
Pos_Fract_dig12_out : out std_logic_vector(7 downto 0);
Pos_Fract_dig34_out : out std_logic_vector(7 downto 0)
-- Inouts
);
end component;
begin
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 10 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
SYSCLK_LF <= not SYSCLK_LF after (SYSCLK_LF_PERIOD / 2.0 );
SYSCLK_Khz <= not SYSCLK_Khz after (SYSCLK_Khz_PERIOD / 2.0 );
-- Instantiate Unit Under Test: Position_INT_to_BCD_decoder
Position_INT_to_BCD_decoder_0 : Position_INT_to_BCD_decoder
-- port map
port map(
-- Inputs
RESET_N => NSYSRESET,
SCLK_IN => SYSCLK,
SCLK_LF_IN => SYSCLK_LF,
SCLK_Hz_IN => SYSCLK_Khz,
Latch_data_IN => s_Latch_data_IN,
Data_ready_IN => '1',
Pos_update_request => '0',
Update_freq => '0',
X_Pos_Int_in => s_X_Pos_Int_in,
X_pos_Fract_in => s_X_pos_Fract_in,
Y_Pos_Int_in => s_Y_Pos_Int_in,
Y_pos_Fract_in => s_Y_pos_Fract_in,
Z_Pos_Int_in => s_Z_Pos_Int_in,
Z_pos_Fract_in => s_Z_pos_Fract_in,
A4_Pos_Int_in => s_A4_Pos_Int_in,
A4_pos_Fract_in => s_A4_pos_Fract_in,
active_axis => s_active_axis,
-- Outputs
Position_to_decode => s_Position_to_decode,
Data_ready_out => s_Data_ready_out,
Position_Tx_gate => s_Position_Tx_gate,
Pos_Int_dig12_out => s_Pos_Int_dig12_out,
Pos_Int_dig34_out => s_Pos_Int_dig34_out,
Pos_Int_dig56_out => s_Pos_Int_dig56_out,
Pos_Fract_dig12_out => s_Pos_Fract_dig12_out,
Pos_Fract_dig34_out => s_Pos_Fract_dig34_out
-- Inouts
);
process
begin
-----------------
--Initialization
--Reset for 10 clk cycles
-----------------
s_X_Pos_Int_in <= (others => '0');
s_X_pos_Fract_in <= (others => '0');
s_Y_Pos_Int_in <= (others => '0');
s_Y_pos_Fract_in <= (others => '0');
s_Z_Pos_Int_in <= (others => '0');
s_Z_pos_Fract_in <= (others => '0');
s_A4_Pos_Int_in <= (others => '0');
s_A4_pos_Fract_in <= (others => '0');
s_Latch_data_IN <= '0';
s_active_axis <= (others => '0');
-----------------
--set IN data
-----------------
wait for ( SYSCLK_PERIOD * 30 );
s_X_Pos_Int_in <= x"1A1B4A";
s_X_pos_Fract_in <= x"1D1E1F";
s_Y_Pos_Int_in <= x"2A2B5D";
s_Y_pos_Fract_in <= x"2D2E25";
s_Z_Pos_Int_in <= x"3A3B7F";
s_Z_pos_Fract_in <= x"3D3E3F";
s_A4_Pos_Int_in <= x"4A4B91";
s_A4_pos_Fract_in <= x"4D4E4F";
-----------------
--Emulate LATCH DATA IN signal
-----------------
wait for ( SYSCLK_LF_PERIOD * 5 );
s_active_axis <= "1000"; --X
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '1';
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '0';
wait for ( SYSCLK_LF_PERIOD * 3 );
s_active_axis <= "0100"; --Y
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '1';
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '0';
wait for ( SYSCLK_LF_PERIOD * 3 );
s_active_axis <= "0010"; --Z
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '1';
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '0';
wait for ( SYSCLK_LF_PERIOD * 3 );
s_active_axis <= "0001"; --A4
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '1';
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '0';
wait for ( SYSCLK_LF_PERIOD * 3 );
s_active_axis <= "0000"; --false
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '1';
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '0';
wait for ( SYSCLK_LF_PERIOD * 3 );
s_active_axis <= "0101"; --false
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '1';
wait for ( SYSCLK_LF_PERIOD * 2 );
s_Latch_data_IN <= '0';
wait for ( SYSCLK_LF_PERIOD * 40 );
end process;
end behavioral;
|
gpl-2.0
|
7b1208a4523fe596782bc734f54e2d52
| 0.548585 | 2.972088 | false | false | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_2/tb_noekeon.vhd
| 1 | 5,032 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon IS
END tb_noekeon;
ARCHITECTURE behavior OF tb_noekeon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
wait for clk_period*48;-- + clk_period/2;
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
-- wait for clk_period + clk_period/2;
-- rst <= '1';
-- enc <= '1';
--
-- a_0_in <= X"e2f687e0";
-- a_1_in <= X"7b75660f";
-- a_2_in <= X"fc372233";
-- a_3_in <= X"bc47532c";
--
-- k_0_in <= X"b1656851";
-- k_1_in <= X"699e29fa";
-- k_2_in <= X"24b70148";
-- k_3_in <= X"503d2dfc";
--
-- wait for clk_period;
-- rst <= '0';
--
-- wait for clk_period*15 + clk_period/2;
--
-- assert a_0_out = X"2a78421b"
-- report "DECRYPT ERROR (a_0)" severity FAILURE;
--
-- assert a_1_out = X"87c7d092"
-- report "DECRYPT ERROR (a_1)" severity FAILURE;
--
-- assert a_2_out = X"4f26113f"
-- report "DECRYPT ERROR (a_2)" severity FAILURE;
--
-- assert a_3_out = X"1d1349b2"
-- report "DECRYPT ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
|
gpl-3.0
|
763cc0fbc66c6321c726d3ad49919287
| 0.553657 | 2.849377 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd
| 1 | 3,975 |
-- $Id: tb_tst_serloop1_n3.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n3 - sim
-- Description: Test bench for sys_tst_serloop1_n3
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop1_n3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_tst_serloop1_n3 is
end tb_tst_serloop1_n3;
architecture sim of tb_tst_serloop1_n3 is
signal CLK100 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
UUT : entity work.sys_tst_serloop1_n3
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_PPCM_CE_N => open,
O_PPCM_RST_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK100,
CLKH => CLK100,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-2.0
|
e9becdb99c05721bf99992e2c14e16c8
| 0.531069 | 3.110329 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega1/ALU.vhd
| 1 | 1,026 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
Salida : out STD_LOGIC_VECTOR (31 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(ALUOP, Oper1, Oper2)
begin
case ALUOP is
when "000000" =>
Salida <= Oper1 + Oper2;
when "000001" =>
Salida <= Oper1 - Oper2;
when "000010" =>
Salida <= Oper1 and Oper2;
when "000011" =>
Salida <= Oper1 and not Oper2;
when "000100" =>
Salida <= Oper1 or Oper2;
when "000101" =>
Salida <= Oper1 or not Oper2;
when "000110" =>
Salida <= Oper1 xor Oper2;
when "000111" =>
Salida <= Oper1 xnor Oper2;
when others =>
Salida <= (others=>'1');
end case;
end process;
end Behavioral;
|
mit
|
1098245bcbf01714cc4e906d1aa4d8a2
| 0.562378 | 3.128049 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
electrostatically_actuated_membrane/initial_160.vhd
| 1 | 516 |
package initial_160 is
constant mm_1:real:= 0.306735124580E-07;
constant km_1:real:= 23.67780511942; -- ddE/dq1/dq1 at q1=0.0
constant dm_1:real:= 2.840743666170e-05; -- Q=30
constant mm_2:real:= 0.201756803926E-07;
constant km_2:real:= 212.6896178680; -- ddE/dq2/dq2 at q2=0.0
constant dm_2:real:= 6.905036631344e-05; -- Q=30
constant fi1_1:real:= 1.00000000000 ;
constant fi1_2:real:= 1.00000000000 ;
constant fi2_1:real:= 0.999999560836 ;
constant fi2_2:real:= 0.999998225220 ;
end;
|
mit
|
0e142bcdb92488e4c1473c163f5fb827
| 0.682171 | 2.214592 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw13/secondc.vhd
| 1 | 1,051 |
Library ieee;
use ieee.std_logic_1164.all;
--modulo 12 przerzutniki D
entity secondc is
port(
A ,B ,C ,D: buffer std_logic;
CLK: in std_logic
);
end secondc;
architecture mod12 of secondc is
component dflipflop
port (
D, CLK, RES: IN std_logic;
Q: OUT std_logic
);
end component;
signal reset: std_logic;
begin
CLR: dflipflop port map(
(A and (B) and not(C) and (D)), not(CLK), '0', reset
);
d3: dflipflop port map(
not(A), not(B), reset , A
);
d2: dflipflop port map(
not(B), not(C), reset, B
);
d1: dflipflop port map(
not(C), not(D), reset, C
);
d0: dflipflop port map(
not(D), CLK, reset, D
);
end mod12;
Library ieee;
use ieee.std_logic_1164.all;
entity dflipflop is
port (
D, CLK, RES: IN std_logic;
Q: OUT std_logic
);
end dflipflop;
architecture impl of dflipflop is
begin
process(CLK, RES)
begin
if (RES = '1') then Q <= '0';
elsif rising_edge(CLK) then
if (D = '0') then
Q <= '0';
elsif D = '1' then
Q <= '1';
end if;
end if;
end process;
end impl;
|
mit
|
bc75212f9d283f4e3f71174a49560701
| 0.610847 | 2.526442 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/LUT/example_design/LUT_exdes.vhd
| 6 | 4,054 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
CLK : IN STD_LOGIC := '0';
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT MAP(
i => CLK,
o => CLK_i
);
end xilinx;
|
gpl-2.0
|
06fd422905d70f447463415dcce41c85
| 0.566354 | 4.769412 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/serport_uart_rxtx.vhd
| 1 | 2,838 |
-- $Id: serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rxtx - syn
-- Description: serial port UART - transmitter + receiver
--
-- Dependencies: serport_uart_rx
-- serport_uart_tx
-- Test bench: tb/tb_serport_uart_rxtx
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity serport_uart_rxtx is -- serial port uart: rx+tx combo
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end serport_uart_rxtx;
architecture syn of serport_uart_rxtx is
begin
RX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
TX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
|
gpl-2.0
|
f72f6e610cf5f810f62c1d664d937c7a
| 0.550388 | 4.185841 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/MUX_wm_tb.vhd
| 1 | 2,232 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:31:23 10/22/2017
-- Design Name:
-- Module Name: C:/Users/DELL/Desktop/Processor3/Processor/MUX_wm_tb.vhd
-- Project Name: Processor
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MUX_wm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MUX_wm_tb IS
END MUX_wm_tb;
ARCHITECTURE behavior OF MUX_wm_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX_wm
PORT(
RDin : IN std_logic_vector(5 downto 0);
o15 : IN std_logic_vector(5 downto 0);
RFDest : IN std_logic;
nRD : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal RDin : std_logic_vector(5 downto 0) := (others => '0');
signal o15 : std_logic_vector(5 downto 0) := (others => '0');
signal RFDest : std_logic := '0';
--Outputs
signal nRD : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX_wm PORT MAP (
RDin => RDin,
o15 => o15,
RFDest => RFDest,
nRD => nRD
);
-- Stimulus process
stim_proc: process
begin
RFDest <= '1';
RDin <= "010000";
o15 <= "010001";
wait for 20 ns;
RFDest <= '0';
RDin <= "010010";
o15 <= "010011";
wait;
end process;
END;
|
mit
|
eaf6307e7908e2a68b436caf9167483d
| 0.583333 | 3.738693 | false | true | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/DataPath_tb.vhd
| 3 | 1,123 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY DataPath_tb IS
END DataPath_tb;
ARCHITECTURE behavior OF DataPath_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DataPath
PORT(
clk : IN std_logic;
rst : IN std_logic;
Data_Out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal Data_Out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DataPath PORT MAP (
clk => clk,
rst => rst,
Data_Out => Data_Out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
-- insert stimulus here
wait;
end process;
END;
|
mit
|
b6abcd8887965221b22fab1d9ea4f4b0
| 0.582369 | 3.587859 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/pwm/wb_pwm16.vhd
| 1 | 2,950 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- W I S H B O N E C O M P L I A N T P W M 16
-- (wb_pwm16.vhd)
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.pwm16_comp.all;
--use work.wbs_defs.all;
-------------------------------------------------------------------------------
entity wb_pwm16 is
-------------------------------------------------------------------------------
generic (
USER_CLK : Boolean := false
);
port (
-- wishbone
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- user pins
clk_in : in std_logic := '-'; -- optinal alternative clock input
pwm_out : out std_logic
);
end wb_pwm16;
-------------------------------------------------------------------------------
architecture structural of wb_pwm16 is
-------------------------------------------------------------------------------
signal pwm_in_s : pwm16_in_type;
signal reg1_s : std_logic_vector(WB_DW-1 downto 0);
signal reg2_s : std_logic_vector(WB_DW-1 downto 0);
signal pwm_clk_s : std_logic;
begin
-- select pwm clock using USER_CLK generic
pwm_clk_s <= clk_in when USER_CLK else wbs_in.clk;
----------------------------------------------------------------------------
WISHBONE_SLAVE : entity work.wbs_dual_out
----------------------------------------------------------------------------
port map (
wbs_in => wbs_in,
wbs_out => wbs_out,
reg1_out => reg1_s,
reg2_out => reg2_s
);
----------------------------------------------------------------------------
PWM_16 : entity work.pwm16
----------------------------------------------------------------------------
port map (
clk => pwm_clk_s,
rst => wbs_in.rst,
d => pwm_in_s,
pwm => pwm_out
);
-- connect boths wbs registers to pwm entity, reg2 contains the high-byte
pwm_in_s.duty_cycle <= reg2_s & reg1_s;
end structural;
|
gpl-3.0
|
7b6c947590069529d2b35f86abcc9f38
| 0.456271 | 4.389881 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/simlib/simbus.vhd
| 1 | 1,967 |
-- $Id: simbus.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: simbus
-- Description: Global signals for support control in test benches
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package simbus is
signal SB_CLKSTOP : slbit := '0'; -- global clock stop
signal SB_CLKCYCLE : slv31 := (others=>'0'); -- global clock cycle
signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
signal SB_VAL : slbit := '0'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'0'); -- init bcast address
signal SB_DATA : slv16 := (others=>'0'); -- init bcast data
-- Note: SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak ('L','H') and
-- strong ('0','1') drivers. Therefore always remove strenght before
-- using, e.g. with to_x01()
end package simbus;
|
gpl-2.0
|
264cb3f8418085a74b0576496536e211
| 0.592781 | 3.711321 | false | false | false | false |
gtarciso/INE5406
|
cont_zeros_esq.vhd
| 1 | 606 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cont_zeros_esq is
port(
inpt: in std_logic_vector(3 downto 0);
outp: out std_logic_vector(2 downto 0)
);
end entity;
architecture arch of cont_zeros_esq is
signal aux: std_logic_vector(3 downto 0);
signal cont: std_logic_vector(2 downto 0);
begin
outp <= "100" when inpt = "0000" else
"011" when inpt = "0001" else
"010" when inpt = "0010" or inpt = "0011" else
"001" when inpt = "0100" or inpt = "0101" or inpt = "0110" or inpt = "0111" else
"000";
end architecture;
|
cc0-1.0
|
3ffee573906ab808a129a89c4ab2e58b
| 0.628713 | 3.172775 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
uniaxial_accelerometer/accelZa_02.vhd
| 1 | 13,567 |
--*****************************************************************************
--*****************************************************************************
-- Model: accelZa_02
-- uniaxial polysilicon MEMS accelerometer
--
-- VHDL-AMS generated code from ANSYS MAPDL ROM TOOL for hAMSter:
-- rompass1_accelZa.mac
-- rompass2_accelZ.mac
--
-- uMKSV units
--
-- Author: <[email protected]>
-- Date: 02.08.2021
-------------------------------------------------------------------------------
-- model geometric parameters, um
-- gc=15.8 ! the gap between plate corners and cap surface
-- heght=15 ! the thickness of the moving plate (baseline: 15um)
-- gd=1.8 ! the gap between plate corners and die surface
--
-- Reference:
-- http://dx.doi.org/10.3390/s121013985
-------------------------------------------------------------------------------
-- modes: 2 dominant (1 and 5)
-- electrodes: 3 (2 capacitances: C13 and C23)
-- element load: the linear acceleration of the structure az=1g x az_input
-- master nodes: 8
--
--
--
--
-- Modal ports
--
-- q1 q2
-- o o
-- | |
-- Lagrangian ports o------o---------o------o Nodal ports:
-- | |
-- p1 o---o o---o u1
-- | ROM element: accelZa |
-- p2 o---o o---o u2
-- | |
-- p3 o---o o---o u3
-- | |
-- p4 o---o o---o u4
-- | |
-- p5 o---o o---o u5
-- | |
-- p6 o---o o---o u6
-- | |
-- p7 o---o o---o u7
-- | |
-- p8 o---o o---o u8
-- | |
-- o------o----o----o------o
-- | | | \
-- o | o \
-- v1_ext | v2_ext=0 o az_input
-- |
-- o v3_ext=0 (plate)
--
-- Electrical ports
--
-- ASCII-Schematic of the ROM component for uniaxial MEMS accelerometer: accelZa
-------------------------------------------------------------------------------
-- Euler solver: time=5m; step=500n ***
-------------------------------------------------------------------------------
-- ID: accelZa_02.vhd
--
-- ver. 1.02 05.08.2021 GitHuB realize:
-- https://github.com/Kolchuzhin/LMGT_MEMS_component_library/tree/master/uniaxial_accelerometer
--
--*****************************************************************************
--*****************************************************************************
--===========================================================================--
--===========================================================================--
package Electromagnetic_system IS
nature electrical is real across real through electrical_ground reference;
nature translational is real across real through mechanical_ground reference;
end package Electromagnetic_system;
-------------------------------------------------------------------------------
use work.electromagnetic_system.all;
library ieee;
use ieee.math_real.all;
--===========================================================================--
--===========================================================================--
entity accelZa_02 is
generic (delay:time);
port (quantity az_input: in real;
terminal struc1,struc2:translational;
terminal lagrange1,lagrange2,lagrange3,lagrange4,lagrange5,lagrange6,lagrange7,lagrange8:translational;
terminal master1,master2,master3,master4,master5,master6,master7,master8:translational;
terminal elec1,elec2,elec3:electrical);
end;
architecture ROM of accelZa_02 is
type ret_type is array(1 to 4) of real;
quantity q1 across fm1 through struc1;
quantity q2 across fm2 through struc2;
quantity p1 across r1 through lagrange1;
quantity p2 across r2 through lagrange2;
quantity p3 across r3 through lagrange3;
quantity p4 across r4 through lagrange4;
quantity p5 across r5 through lagrange5;
quantity p6 across r6 through lagrange6;
quantity p7 across r7 through lagrange7;
quantity p8 across r8 through lagrange8;
quantity u1 across f1 through master1;
quantity u2 across f2 through master2;
quantity u3 across f3 through master3;
quantity u4 across f4 through master4;
quantity u5 across f5 through master5;
quantity u6 across f6 through master6;
quantity u7 across f7 through master7;
quantity u8 across f8 through master8;
quantity v1 across i1 through elec1;
quantity v2 across i2 through elec2;
quantity v3 across i3 through elec3;
--===========================================================================--
constant mm_1:real:= 0.473364651010E-08; -- mode1 modal mass
constant mm_2:real:= 0.803474901717E-08; -- mode5 modal mass
constant fm_1:real:= 1205.3; -- mode1 frequency
constant fm_2:real:= 15539.0; -- mode5 frequency
constant km_1:real:= 0.2716; -- k1=mass*((2*PI*f1)**2)
constant km_2:real:= 76.516; -- k2=mass*((2*PI*f2)**2)
constant qm_1:real:= 1.0; -- mode1 quality factor
constant qm_2:real:= 1.0; -- mode5 quality factor
constant dm_1:real:= SQRT(mm_1*km_1)/qm_1; -- damping ratio SQRT(m*k)/q
constant dm_2:real:= SQRT(mm_2*km_2)/qm_2; -- damping ratio SQRT(m*k)/q
constant fi1_1:real:= 0.999835485909; -- master node 1
constant fi1_2:real:= 0.403769743614;
constant fi2_1:real:= 0.999835586749;
constant fi2_2:real:= 0.403769489490;
constant fi3_1:real:= -0.745314753376;
constant fi3_2:real:= 0.999974954447;
constant fi4_1:real:= -0.745314653634;
constant fi4_2:real:= 0.999974699952;
constant fi5_1:real:= 0.999835485910;
constant fi5_2:real:= 0.403769744306;
constant fi6_1:real:= 0.999835586751;
constant fi6_2:real:= 0.403769490182;
constant fi7_1:real:= -0.745314753375;
constant fi7_2:real:= 0.999974955317;
constant fi8_1:real:= -0.745314653633;
constant fi8_2:real:= 0.999974700821; -- master node 8
constant el1_1:real:= -0.218433078934E-01;
constant el1_2:real:= -0.109604826007 ;
constant el2_1:real:= -0.436866157865E-01;
constant el2_2:real:= -0.219209652036 ;
--===========================================================================--
constant s_type150:integer:=1;
constant s_inve150:integer:=1;
signal s_ord150:real_vector(1 to 3):=(4.0, 2.0, 0.0);
signal s_fak150:real_vector(1 to 4):=(1.02, 51.0, 0.0, 0.1452005335);
constant s_anz150:integer:=15;
signal s_data150:real_vector(1 to 15):=(
0.153046214864E-10,
-0.115346424932E-10,
0.898594050430 ,
0.131856183100E-10,
0.451168146307E-09,
-0.192639596352E-11,
-0.180817757915E-06,
-0.100841662878E-12,
0.819408921286E-10,
0.250892538141E-11,
0.101405768487 ,
0.961373531525E-11,
0.295710869676E-09,
-0.109899447351E-10,
-0.478033992492E-09);
--===========================================================================--
constant ca13_type150:integer:=1;
constant ca13_inve150:integer:=2;
signal ca13_ord150:real_vector(1 to 3):=(4.0, 2.0, 0.0);
signal ca13_fak150:real_vector(1 to 4):=(1.02, 51.0, 0.00, 1.24878218153);
constant ca13_anz150:integer:=15;
signal ca13_data150:real_vector(1 to 15):=(
0.821596533919 ,
-0.180241554630 ,
-0.127562294156E-01,
0.818686861972E-03,
0.432945579544E-02,
0.759644315386E-02,
0.534049229957E-03,
0.997510446329E-03,
-0.908056944362E-03,
-0.143119042257E-02,
0.250236472124E-05,
-0.180877516419E-04,
-0.633278731250E-04,
0.297334467098E-04,
0.728567968866E-04);
--===========================================================================--
constant ca23_type150:integer:=1;
constant ca23_inve150:integer:=2;
signal ca23_ord150:real_vector(1 to 3):=(4.0, 2.0, 0.0);
signal ca23_fak150:real_vector(1 to 4):=(1.02, 51.0, 0.0, 0.958512583853);
constant ca23_anz150:integer:= 15;
signal ca23_data150:real_vector(1 to 15):=(
0.783998489543 ,
0.232937982634 ,
-0.305701885773E-01,
-0.170807820768E-01,
0.268079240498E-01,
0.461037567958E-02,
-0.188754982379E-04,
0.360563171587E-04,
0.963438020727E-03,
-0.790519579176E-03,
-0.272090902872E-04,
-0.572697741434E-04,
0.311851954139E-03,
-0.304790455820E-04,
-0.216006518183E-03);
--===========================================================================--
function spoly_calc(qx, qy, qz : in real:=0.0; s_type,s_inve : integer :=0;
s_ord, s_fak, s_data:real_vector) return ret_type is
constant Sx:integer:=integer(s_ord(1))+1;
constant Sy:integer:=integer(s_ord(2))+1;
constant Sz:integer:=integer(s_ord(3))+1;
variable fwx:real_vector(1 to Sx):=(others=>0.0);
variable fwy:real_vector(1 to Sy):=(others=>0.0);
variable fwz:real_vector(1 to 1):=(others=>0.0);
variable dfwx:real_vector(1 to Sx):=(others=>0.0);
variable dfwy:real_vector(1 to Sy):=(others=>0.0);
variable dfwz:real_vector(1 to 1):=(others=>0.0);
variable res_val:ret_type:=(others=>0.0);
variable fwv,dfwvx,dfwvy,dfwvz,fak2:real:=0.0;
variable Px_s,Py_s,Px,Py,Lx,Ly,Lz,ii:integer:=0;
begin
Lx:=integer(s_ord(1));
Ly:=integer(s_ord(2));
Lz:=integer(s_ord(3));
for i in 1 to Lx+1 loop
fwx(i):=qx**(i-1)*s_fak(1)**(i-1);
if i=2 then
dfwx(i):=s_fak(1)**(i-1);
end if;
if i>2 then
dfwx(i):=real(i-1)*qx**(i-2)*s_fak(1)**(i-1);
end if;
end loop;
for i in 1 to Ly+1 loop
fwy(i):=qy**(i-1)*s_fak(2)**(i-1);
if i=2 then
dfwy(i):=s_fak(2)**(i-1);
end if;
if i>2 then
dfwy(i):=real(i-1)*qy**(i-2)*s_fak(2)**(i-1);
end if;
end loop;
for i in 1 to Lz+1 loop
fwz(i):=qz**(i-1)*s_fak(3)**(i-1);
if i=2 then
dfwz(i):=s_fak(3)**(i-1);
end if;
if i>2 then
dfwz(i):=real(i-1)*qz**(i-2)*s_fak(3)**(i-1);
end if;
end loop;
if s_type=1 then
ii:=1;
for zi in 0 to Lz loop
for yi in 0 to Ly loop
for xi in 0 to Lx loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
end loop;
end loop;
end if;
if s_inve=1 then
fwv:=fwv*s_fak(4);
dfwvx:=dfwvx*s_fak(4);
dfwvy:=dfwvy*s_fak(4);
dfwvz:=dfwvz*s_fak(4);
else
fak2:=1.0/s_fak(4);
dfwvx:=-dfwvx/(fwv**2);
dfwvy:=-dfwvy/(fwv**2);
dfwvz:=-dfwvz/(fwv**2);
fwv:=1.0/fwv;
fwv:=fwv*fak2;
dfwvx:=dfwvx*fak2;
dfwvy:=dfwvy*fak2;
dfwvz:=dfwvz*fak2;
end if;
res_val:=(fwv, dfwvx, dfwvy, dfwvz);
return res_val;
end spoly_calc;
--===========================================================================--
signal sene_150:ret_type;
signal ca13_150:ret_type;
signal ca23_150:ret_type;
begin
p1:process
begin
sene_150<= spoly_calc(q1,q2,0.0,s_type150,s_inve150,s_ord150,s_fak150,s_data150);
ca13_150<= spoly_calc(q1,q2,0.0,ca13_type150,ca13_inve150,ca13_ord150,ca13_fak150,ca13_data150);
ca23_150<= spoly_calc(q1,q2,0.0,ca23_type150,ca23_inve150,ca23_ord150,ca23_fak150,ca23_data150);
wait for delay;
end process;
break on sene_150(2),sene_150(3),sene_150(4),ca13_150(2),ca13_150(3),ca13_150(4),ca23_150(2),ca23_150(3),ca23_150(4);
fm1==mm_1*q1'dot'dot + dm_1*q1'dot +sene_150(2) -ca13_150(2)*(v1-v3)**2/2.0 -ca23_150(2)*(v2-v3)**2/2.0 +fi1_1*p1 +fi2_1*p2 +fi3_1*p3 +fi4_1*p4 +fi5_1*p5 +fi6_1*p6 +fi7_1*p7 +fi8_1*p8 -el1_1*az_input;
fm2==mm_2*q2'dot'dot + dm_2*q2'dot +sene_150(3) -ca13_150(3)*(v1-v3)**2/2.0 -ca23_150(3)*(v2-v3)**2/2.0 +fi1_2*p1 +fi2_2*p2 +fi3_2*p3 +fi4_2*p4 +fi5_2*p5 +fi6_2*p6 +fi7_2*p7 +fi8_2*p8 -el1_2*az_input;
--
r1==fi1_1*q1+fi1_2*q2-u1;
r2==fi2_1*q1+fi2_2*q2-u2;
r3==fi3_1*q1+fi3_2*q2-u3;
r4==fi4_1*q1+fi4_2*q2-u4;
r5==fi5_1*q1+fi5_2*q2-u5;
r6==fi6_1*q1+fi6_2*q2-u6;
r7==fi7_1*q1+fi7_2*q2-u7;
r8==fi8_1*q1+fi8_2*q2-u8;
--
f1==-p1;
f2==-p2;
f3==-p3;
f4==-p4;
f5==-p5;
f6==-p6;
f7==-p7;
f8==-p8;
i1==+((v1-v3)*(ca13_150(2)*q1'dot+ca13_150(3)*q2'dot)+(v1'dot-v3'dot)*ca13_150(1));
i2==+((v2-v3)*(ca23_150(2)*q1'dot+ca23_150(3)*q2'dot)+(v2'dot-v3'dot)*ca23_150(1));
i3==-((v1-v3)*(ca13_150(2)*q1'dot+ca13_150(3)*q2'dot)+(v1'dot-v3'dot)*ca13_150(1))-((v2-v3)*(ca23_150(2)*q1'dot+ca23_150(3)*q2'dot)+(v2'dot-v3'dot)*ca23_150(1));
end;
--===========================================================================--
--===========================================================================--
|
mit
|
267833d2746e1b8cc3d15f8e71ae26d5
| 0.496941 | 2.893367 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
| 1 | 3,377 |
-- $Id: tb_nexys2_core.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_core - sim
-- Description: Test bench for nexys2 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 1.1 update O_FLA_CE_N usage
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_nexys2_core is
port (
I_SWI : out slv8; -- n2 switches
I_BTN : out slv4; -- n2 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys2_core;
architecture sim of tb_nexys2_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
gpl-2.0
|
2e0a88ff7f1dbb6c82f4113dd2ab3073
| 0.564406 | 3.147251 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/adqsin.vhd
| 6 | 1,455 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsin is
port(
dqs_pad : in std_logic; -- DQS pad
dqsn_pad : in std_logic; -- DQSN pad
dqs : out std_logic
);
end;
architecture rtl of adqsin is
component stratixiii_io_ibuf IS
generic (
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "z";
lpm_type : string := "stratixiii_io_ibuf"
);
port (
i : in std_logic := '0';
ibar : in std_logic := '0';
o : out std_logic
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_buf : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- In buffer (DQS, DQSN) ------------------------------------------------------------
dqs_buf0 : stratixiii_io_ibuf
generic map(
differential_mode => "true",
bus_hold => "false",
simulate_z_as => "z",
lpm_type => "stratixiii_io_ibuf"
)
port map(
i => dqs_pad,
ibar => dqsn_pad,
o => dqs_buf
);
dqs <= dqs_buf;
end;
|
gpl-2.0
|
a3643499c7cf942efdf88433e49337f4
| 0.45567 | 3.808901 | false | false | false | false |
skrasser/papilio_synth
|
hdl/envelope.vhd
| 1 | 3,383 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity envelope is
port (data_in : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0);
attack : in STD_LOGIC_VECTOR(3 downto 0); -- attack rate
delay : in STD_LOGIC_VECTOR(3 downto 0); -- delay rate
sustain : in STD_LOGIC_VECTOR(3 downto 0); -- sustain level
release : in STD_LOGIC_VECTOR(3 downto 0); -- release rate
gate : in STD_LOGIC;
clk : in STD_LOGIC
);
end envelope;
architecture behavioral of envelope is
begin
process(clk)
constant state_idle : std_logic_vector(2 downto 0) := "000";
constant state_attack : std_logic_vector(2 downto 0) := "001";
constant state_delay : std_logic_vector(2 downto 0) := "010";
constant state_sustain : std_logic_vector(2 downto 0) := "011";
constant state_release : std_logic_vector(2 downto 0) := "100";
variable state : std_logic_vector(2 downto 0) := state_idle;
variable sum : unsigned(22 downto 0) := (others => '0');
variable rate : unsigned(3 downto 0);
variable vol : unsigned(7 downto 0) := (others => '0');
variable datamod : unsigned(15 downto 0);
function trigger(asum : unsigned(22 downto 0);
arate : unsigned(3 downto 0)
) return boolean is
begin
-- bit 7 is set after 1.024 msec
if asum(to_integer(arate) + 7) = '1' then
return true;
else
return false;
end if;
end trigger;
begin
if rising_edge(clk) then
case state is
when state_idle =>
vol := (others => '0');
sum := (others => '0');
if gate = '1' then
state := state_attack;
end if;
when state_attack =>
sum := sum + 1;
if trigger(sum, unsigned(attack)) then
sum := (others => '0');
vol := vol + 1;
-- if up to maximum volume, then switch to delay state
if vol = 255 then
state := state_delay;
end if;
end if;
when state_delay =>
sum := sum + 1;
if trigger(sum, unsigned(delay)) then
sum := (others => '0');
vol := vol - 1;
if vol = unsigned(sustain & "0000") then
state := state_sustain;
end if;
end if;
when state_sustain =>
-- stay in this state as long as the gate is active
if gate = '0' then
state := state_release;
-- need to reset sum since this did not occur on trigger
sum := (others => '0');
end if;
when state_release =>
sum := sum + 1;
if gate = '1' then
-- new note played, go through idle state for setup
state := state_idle;
elsif trigger(sum, unsigned(release)) then
sum := (others => '0');
vol := vol - 1;
if vol = 0 then
state := state_idle;
end if;
end if;
when others =>
state := state_idle;
end case;
-- apply volume to incoming data
datamod := unsigned(data_in) * vol;
data_out <= std_logic_vector(datamod(15 downto 8));
end if;
end process;
end behavioral;
|
mit
|
d262285d76fd4fe6b0d9e361e5c28262
| 0.522613 | 3.9383 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-cpci-xc2v6000/leon3mp.vhd
| 1 | 30,061 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to 1);
can_rxd : in std_logic_vector(0 to 1);
can_stb : out std_logic_vector(0 to 1);
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_SDCTRL+CFG_CAN;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ, CFG_SPW_EN)
port map (lclk, pci_lclk, clkm, open, spw_lclk, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg1 : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0,
ramws => CFG_SRCTRL_RAMWS, romws => CFG_SRCTRL_PROMWS,
ramaddr => 16#400#, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sd1 : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data(63 downto 32), sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm(7 downto 0));
end generate;
-- sdsn : if (CFG_SDEN = 0) or (CFG_MEMC = 2) generate ahbso(3) <= ahbs_none; end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, sden => CFG_MCTRL_SDEN,
invclk => CFG_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mg0 : if (CFG_SRCTRL + CFG_MCTRL_LEON2) = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
mgpads : if (CFG_SRCTRL + CFG_MCTRL_LEON2) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
j2u : if CFG_AHB_UART = 0 generate
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, u1i.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, u1o.txd);
end generate;
j1u : if CFG_AHB_UART = 1 generate
rxd_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
txd_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
-- pp : if CFG_PCI /= 0 generate
--
-- pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
-- pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
-- apb_en => CFG_PCI_ARBAPB)
-- port map ( clk => pciclk, rst_n => pcii.rst,
-- req_n => pci_arb_req_n, frame_n => pcii.frame,
-- gnt_n => pci_arb_gnt_n, pclk => clkm,
-- prst_n => rstn, apbi => apbi, apbo => apbo(10)
-- );
-- pgnt_pad : outpadv generic map (tech => padtech, width => 4)
-- port map (pci_arb_gnt, pci_arb_gnt_n);
-- preq_pad : inpadv generic map (tech => padtech, width => 4)
-- port map (pci_arb_req, pci_arb_req_n);
-- end generate;
--
-- pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
-- port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
-- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
-- pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
--
-- end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
-- ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb(0) <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(0), can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(0), can_lrx);
end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => fabtech,
hindex => maxahbmsp+i, pindex => 10+i, paddr => 10+i, pirq => 10+i,
sysfreq => cpu_freq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT,
netlist => CFG_SPW_NETLIST, ports => 1, dmachan => CFG_SPW_DMACHAN,
memtech => memtech, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ*2/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-CPCI-XC2V6000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
287fdd0853ce04178249a45a7468a711
| 0.557666 | 3.430055 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbdpram.vhd
| 1 | 5,303 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahdpbram
-- File: ahbdpram.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: AHB DP ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbdpram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end;
architecture rtl of ahbdpram is
--constant abits : integer := log2(kbytes) + 8;
constant kbytes : integer := 2**(abits - 8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBDPRAM, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal bwrite : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
signal hwdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
if (r.hwrite or not r.hready) = '1' then haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
end if;
if r.hwrite = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then v.hwrite := '0'; v.hready := '1'; end if;
bwrite <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ahbdrivedata(ramdata);
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
hwdata <= ahbreadword(ahbsi.hwdata, r.addr(4 downto 2));
bw : if bytewrite = 1 generate
ra : for i in 0 to 3 generate
aram : syncram_dp generic map (tech, abits, 8) port map (
clk, ramaddr, hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, bwrite(3-i),
clkdp, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable, write(3-i)
);
end generate;
end generate;
nobw : if bytewrite = 0 generate
aram : syncram_dp generic map (tech, abits, 32) port map (
clk, ramaddr, hwdata(31 downto 0), ramdata, ramsel, r.hwrite,
clkdp, address, datain, dataout, enable, write(0)
);
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbdpram" & tost(hindex) &
": AHB DP SRAM Module, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
|
gpl-2.0
|
e231e0e1b027815693348b837eed8d91
| 0.606449 | 3.37341 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/adapters/elastic_buffer.vhd
| 1 | 5,491 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: elastic_buffer
-- File: elastic_buffer.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII's elastic buffer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity elastic_buffer is
generic (
tech : integer := 0;
abits : integer := 7
);
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
wr_data : in std_logic_vector(9 downto 0);
rd_clk : in std_logic;
rd_rst : in std_logic;
rd_data : out std_logic_vector(9 downto 0)
) ;
end entity ;
architecture arch of elastic_buffer is
type rd_reg_type is record
fifo_out_d0 : std_logic_vector(9 downto 0);
fifo_out_d1 : std_logic_vector(9 downto 0);
insert_d0 : std_logic;
insert_d1 : std_logic;
start_reading : std_logic;
end record;
type wr_reg_type is record
fifo_in_d0 : std_logic_vector(9 downto 0);
fifo_in_d1 : std_logic_vector(9 downto 0);
delete_d0 : std_logic;
delete_d1 : std_logic;
end record;
constant rd_reg_none : rd_reg_type := (
fifo_out_d0 => (others => '0'),
fifo_out_d1 => (others => '0'),
insert_d0 => '0',
insert_d1 => '0',
start_reading => '0'
);
constant wr_reg_none : wr_reg_type := (
fifo_in_d0 => (others => '0'),
fifo_in_d1 => (others => '0'),
delete_d0 => '0',
delete_d1 => '0'
);
-- 8/10b encoding sequences
constant COMMAP : std_logic_vector(6 downto 0) := "0011111";
constant COMMAN : std_logic_vector(6 downto 0) := "1100000";
constant D16_2P : std_logic_vector(9 downto 0) := "0110110101";
constant D16_2N : std_logic_vector(9 downto 0) := "1001000101";
signal rd_r, rd_rin : rd_reg_type;
signal wr_r, wr_rin : wr_reg_type;
signal rd_en, wr_en : std_logic;
signal wrusedw_int, rdusedw_int : std_logic_vector(abits-1 downto 0);
signal fifo_out : std_logic_vector(9 downto 0);
signal rd_rstn, wr_rstn : std_logic;
begin
comb : process(rd_r, wr_r, fifo_out, wr_data, rdusedw_int, wrusedw_int, rd_rin, wr_rin, rd_rst, wr_rst)
variable rd_v : rd_reg_type;
variable wr_v : wr_reg_type;
variable insert : std_logic;
begin
rd_v := rd_rin;
wr_v := wr_rin;
rd_v.fifo_out_d0 := fifo_out;
rd_v.fifo_out_d1 := rd_r.fifo_out_d0;
rd_v.insert_d0 := '0';
rd_v.insert_d1 := rd_r.insert_d0;
rd_v.start_reading := rd_r.start_reading or rdusedw_int(rdusedw_int'left);
wr_v.fifo_in_d0 := wr_data;
wr_v.fifo_in_d1 := wr_r.fifo_in_d0;
wr_v.delete_d0 := '0';
wr_v.delete_d1 := wr_r.delete_d0;
if rdusedw_int(abits-1 downto abits-6) < "011111" and
((rd_r.fifo_out_d1(9 downto 3) = COMMAP and rd_r.fifo_out_d0 = D16_2N ) or (rd_r.fifo_out_d1(9 downto 3) = COMMAN and rd_r.fifo_out_d0 = D16_2P)) then
rd_v.insert_d0 := '1';
end if;
if wrusedw_int(abits-1 downto abits-6) > "100000" and
((wr_r.fifo_in_d1(9 downto 3) = COMMAP and wr_r.fifo_in_d0 = D16_2N ) or (wr_r.fifo_in_d1(9 downto 3) = COMMAN and wr_r.fifo_in_d0 = D16_2P)) then
wr_v.delete_d0 := '1';
end if;
-- inserting /I2/ when needed
if (rd_r.insert_d0 or rd_r.insert_d1) = '1' then
rd_v.fifo_out_d0 := rd_r.fifo_out_d1;
end if;
rd_en <= rd_r.start_reading and (not rd_rst) and not (rd_r.insert_d0 or rd_v.insert_d0);
-- deleting /I2/ when needed
wr_en <= (not wr_rst) and not (wr_r.delete_d0 or wr_v.delete_d0);
rd_data <= rd_r.fifo_out_d1;
rd_rin <= rd_v;
wr_rin <= wr_v;
end process;
rd_seq : process(rd_clk, rd_rst)
begin
if rd_rst = '1' then
rd_r <= rd_reg_none;
elsif rising_edge(rd_clk) then
rd_r <= rd_rin;
end if;
end process;
wr_seq : process(wr_clk, wr_rst)
begin
if wr_rst = '1' then
wr_r <= wr_reg_none;
elsif rising_edge(wr_clk) then
wr_r <= wr_rin;
end if;
end process;
-- Active low sync resets for the fifo
rd_rstn <= not(rd_rst);
wr_rstn <= not(wr_rst);
fifo0: syncfifo_2p
generic map(
tech => tech,
abits => abits,
dbits => 10
)
port map(
rclk => rd_clk,
rrstn => rd_rstn,
wrstn => wr_rstn,
renable => rd_en,
rfull => open,
rempty => open,
aempty => open,
rusedw => rdusedw_int,
dataout => fifo_out,
wclk => wr_clk,
write => wr_en,
wfull => open,
afull => open,
wempty => open,
wusedw => wrusedw_int,
datain => wr_r.fifo_in_d1
);
end architecture ;
|
gpl-2.0
|
ec9e24f46530d062381fe98f6107b42b
| 0.607175 | 2.629789 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spi2ahbx.vhd
| 1 | 17,422 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahbx
-- File: spi2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with spi2ahb or spi2ahb_apb.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a SPI memory device. To write to the core, issue the
-- following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Write instruction
-- 2. Send 32-bit address
-- 3. Send data to be written
-- 4. Deassert chip select
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. If less than HSIZE bytes are transferred the core will drop the data.
-- After HSIZE bytes has been transferred the core will perform the write to
-- memory. If another byte is received before the core has written its data
-- then the core will discard the current and any following bytes. This
-- condition can be detected by checking the MALFUNCTION bit in the core's
-- status register.
--
-- To read to the core, issue the following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Send read instruction
-- 2. Send 32-bit address to be used
-- 3. Send dummy byte (depending on read instruction used)
-- 4. Read bytes
-- 5. Deassert chip select
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). If the buffer is empty when the core should return the first
-- byte then the core will return invalid data. This condition can be later
-- detected by checking the MALFUNCTION bit in the core's status register.
-- When the core initiates additional data fetches can be configured via the
-- RAHEAD bit in the control/status register.
--
-- The cores control/status register is read via the RDSR instruction and
-- written via the WRSR instruction.
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7 | Reserved, always zero (RO) |
-- | 6 | RAHEAD: Read ahead. When this bit is set the core will make a |
-- | | new access to fetch data as soon as the last current data bit |
-- | | has been moved. Otherwise the core will not attempt the new |
-- | | access until the 'change' transition on SCK. See GRIP doc. for |
-- | | details. Default value is '1'. (RW) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | MALFUNCTION: Set to 1 if DMA is not finished when new byte |
-- | | starts getting shifted |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filter used on SCK
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity spi2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end entity spi2ahbx;
architecture rtl of spi2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OE : std_ulogic := conv_std_logic(oepol = 1);
constant HIZ : std_ulogic := not OE;
-----------------------------------------------------------------------------
-- Instructions
-----------------------------------------------------------------------------
constant RDSR_INST : std_logic_vector(7 downto 0) := X"05";
constant WRSR_INST : std_logic_vector(7 downto 0) := X"01";
constant READ_INST : std_logic_vector(7 downto 0) := X"03";
constant READD_INST : std_logic_vector(7 downto 0) := X"0B"; -- with dummy
constant WRITE_INST : std_logic_vector(7 downto 0) := X"02";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type state_type is (decode, rdsr, wrsr, addr, dummy, rd, wr, idle, malfunction);
type spi2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
--
rahead : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
prot : std_ulogic;
malf : std_ulogic;
--
brec : std_ulogic;
rec : std_ulogic;
dummy : std_ulogic;
cnt : std_logic_vector(2 downto 0);
bcnt : std_logic_vector(1 downto 0);
sreg : std_logic_vector(7 downto 0);
miso : std_ulogic;
rdop : std_logic_vector(1 downto 0);
--
misooen : std_ulogic;
sel : std_logic_vector(1 downto 0);
psck : std_ulogic;
sck : std_logic_vector(filter downto 0);
mosi : std_logic_vector(1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : spi2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_SPI2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, spii, amo, spi2ahbi)
variable v : spi2ahb_reg_type;
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable lb : std_ulogic;
variable sample : std_ulogic;
variable change : std_ulogic;
begin
v := r; ahbreq := '0'; lb := '0'; hrdata := (others => '0');
sample := '0'; change := '0'; v.brec := '0';
---------------------------------------------------------------------------
-- Sync input signals
---------------------------------------------------------------------------
v.sel := r.sel(0) & spii.spisel;
v.sck := r.sck(filter-1 downto 0) & spii.sck;
v.mosi := r.mosi(0) & spii.mosi;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
if andv(r.sck(filter downto 1)) = '1' then v.psck := '1'; end if;
if orv(r.sck(filter downto 1)) = '0' then v.psck := '0'; end if;
if (r.psck xor v.psck) = '1' then
if r.psck = conv_std_logic(cpol = 1) then
sample := not conv_std_logic(cpha = 1);
change := conv_std_logic(cpha = 1);
else
sample := conv_std_logic(cpha = 1);
change := not conv_std_logic(cpha = 1);
end if;
end if;
if sample = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "111" then
v.cnt := (others => '0');
v.brec := '1';
end if;
if r.state /= dummy then
v.sreg := r.sreg(6 downto 0) & r.mosi(1);
end if;
end if;
if change = '1' then
v.miso := r.sreg(7);
end if;
---------------------------------------------------------------------------
-- SPI slave control FSM
---------------------------------------------------------------------------
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
case r.state is
when decode =>
if r.brec = '1' then
case r.sreg is
when RDSR_INST =>
v.state := rdsr;
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
when WRSR_INST => v.state := wrsr;
when READ_INST | READD_INST=>
v.state := addr; v.rec := '0';
v.dummy := r.sreg(3);
when WRITE_INST => v.state := addr; v.rec := '1';
when others => null;
end case;
end if;
when rdsr =>
if r.brec = '1' then
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
end if;
when wrsr =>
if r.brec = '1' then
v.rahead := r.sreg(6);
v.hsize := r.sreg(1 downto 0);
end if;
when addr =>
-- First we need a 4 byte address, then we handle data.
if r.brec = '1' then
if r.dodma = '1' then
v.state := malfunction;
else
v.haddr := r.haddr(23 downto 0) & r.sreg;
end if;
v.bcnt := r.bcnt + 1;
if r.bcnt = "11" then
if r.rec = '1' then
v.state := wr;
else
if r.dummy = '1' then
v.state := dummy;
else
v.state := rd;
end if;
v.malf := '0';
v.dodma := '1';
v.hwrite := '0';
end if;
end if;
end if;
when dummy =>
if r.brec = '1' then
v.state := rd;
end if;
when rd =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
if (lb and r.rahead) = '1' then
v.dodma := '1';
v.bcnt := "00";
end if;
v.rdop(0) := lb and not r.rahead;
end if;
if (change and v.dodma) = '1' then
v.state := malfunction;
end if;
-- Without readahead
if orv(r.rdop) = '1' then
if (sample and v.dodma) = '1' then
-- Case is a little tricky. Master may have sampled bad
-- data but we detect the DMA operation as completed.
v.state := malfunction;
end if;
if (r.rdop(0) and change) = '1' then
v.dodma := '1';
v.rdop := "10";
end if;
if (r.dodma and not v.dodma) = '1' then
v.miso := hrdata(31);
v.rdop := (others => '0');
end if;
end if;
when wr =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
if v.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.hwrite := '1'; v.malf := '0'; end if;
else
v.state := malfunction;
end if;
end if;
when idle =>
if r.sel(1) = '0' then
v.state := decode;
v.misooen := OE;
v.cnt := (others => '0');
v.bcnt := (others => '0');
end if;
when malfunction =>
v.malf := '1';
end case;
if r.state /= rd then v.rdop := (others => '0'); end if;
if spi2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((spi2ahbi.haddr xor r.haddr) and spi2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if spi2ahbi.en = '1' then
if r.sel(1) = '1' then
v.state := idle;
v.misooen := HIZ;
end if;
else
v.state := idle;
v.misooen := HIZ;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.haddr := (others => '0');
v.hdata := (others => '0');
v.hsize := HSIZE_WORD(1 downto 0);
v.rahead := '1';
v.mexc := '0';
v.dodma := '0';
v.prot := '0';
v.malf := '0';
v.psck := conv_std_logic(cpol = 1);
v.miso := '1';
v.misooen := HIZ;
end if;
if spi2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
spi2ahbo.dma <= r.dodma;
spi2ahbo.wr <= r.hwrite;
spi2ahbo.prot <= r.prot;
-- Several unused here..
spio.miso <= r.miso;
spio.misooen <= r.misooen;
spio.mosi <= '0';
spio.mosioen <= HIZ;
spio.sck <= '0';
spio.sckoen <= HIZ;
spio.ssn <= (others => '0');
spio.enable <= spi2ahbi.en;
spio.astart <= '0';
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("spi2ahb" & tost(hindex) & ": SPI to AHB bridge");
-- pragma translate_on
end architecture rtl;
|
gpl-2.0
|
2370de25d068a3ef59b7843eeff94eba
| 0.465618 | 3.952359 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx25/testbench.vhd
| 1 | 9,557 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
-- support the use of an external AHB slave and different HPE board versions
------------------------------------------------------------------------------
-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 1000 ns;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
-- u1 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
-- phy0 : if CFG_GRETH > 0 generate
-- p0 : phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
-- end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
gpl-2.0
|
6ffb51824841c37222163f4452230411
| 0.527467 | 3.522669 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ahb2avl_async_be.vhd
| 1 | 10,973 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async_be
-- File: ahb2avl_async_be.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Avalon clock domain part of ahb2avl_async
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
ahbbits : integer := ahbdw;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end;
architecture rtl of ahb2avl_async_be is
constant avlbl: integer := (burstlen*32) / avldbits;
constant onev: std_logic_vector(15 downto 0) := (others => '1');
type be_state is (idle,acc1,acc2,rdwait);
type be_regs is record
req1,req2 : ddr_request_type;
start1,start2: std_ulogic;
resp: ddr_response_type;
s: be_state;
ramaddr: std_logic_vector(log2(avlbl)-1 downto 0);
beginburst: std_ulogic;
wr: std_ulogic;
rd: std_ulogic;
reading: std_ulogic;
rdata_valid_prev: std_ulogic;
wmaskmode: std_ulogic;
rstarted: std_ulogic;
end record;
signal r,nr: be_regs;
begin
comb: process(r,rst,request,start_tog,avlso,wbrdata)
variable v: be_regs;
variable vstart: std_logic;
variable vreq: ddr_request_type;
variable startmask,endmask,mask,mask16,mask8: std_logic_vector(avldbits/8-1 downto 0);
variable ad32: std_logic_vector(3 downto 2);
variable nwmaskmode: std_ulogic;
variable rbw: std_ulogic;
variable slvi: ddravl_slv_in_type;
variable rddone: std_ulogic;
variable inc_ramaddr: std_ulogic;
variable aendaddr: std_logic_vector(9 downto 0);
begin
v := r;
slvi := ddravl_slv_in_none;
slvi.burstbegin := r.beginburst;
slvi.addr(avlabits-1 downto log2(avlbl)) :=
vreq.startaddr(avlabits-1-log2(avlbl)+log2(burstlen*4) downto log2(burstlen*4));
slvi.addr(log2(avlbl)-1 downto 0) := r.ramaddr;
slvi.wdata(avldbits-1 downto 0) := wbrdata;
slvi.write_req := r.wr;
slvi.size := std_logic_vector(to_unsigned(avlbl, slvi.size'length));
-- fix for accesses wider than 32-b word
aendaddr := request.endaddr; --(log2(4*burstlen)-1 downto 2);
if request.hsize(1 downto 0)="11" and request.hio='0' then
aendaddr(2):='1';
end if;
if ahbbits > 64 and request.hsize(2)='1' then
aendaddr(3 downto 2) := "11";
if ahbbits > 128 and request.hsize(0)='1' then
aendaddr(4) := '1';
end if;
end if;
v.req1 := request;
v.req1.endaddr := aendaddr;
v.req2 := r.req1;
v.start1 := start_tog;
v.start2 := r.start1;
vstart:=r.start2; vreq:=r.req2;
if nosync /= 0 then vstart:=start_tog; vreq:=r.req1; end if;
startmask := (others => '1'); endmask := (others => '1');
mask16 := (others => '1'); mask8 := (others => '1');
case avldbits is
when 32 =>
if vreq.startaddr(1)='0' then mask16:="1100"; else mask16:="0011"; end if;
if vreq.startaddr(0)='0' then mask8:="1010"; else mask8:="0101"; end if;
when 64 =>
if vreq.startaddr(2)='0' then startmask:="11111111";
else startmask:="00001111";
end if;
if vreq.endaddr(2)='0' then endmask:="11110000";
else endmask:="11111111";
end if;
if vreq.startaddr(1)='0' then mask16:="11001100"; else mask16:="00110011"; end if;
if vreq.startaddr(0)='0' then mask8:="10101010"; else mask8:="01010101"; end if;
when 128 =>
ad32 := vreq.startaddr(3 downto 2);
case ad32 is
when "00" => startmask:="1111111111111111";
when "01" => startmask:="0000111111111111";
when "10" => startmask:="0000000011111111";
when others => startmask:="0000000000001111";
end case;
ad32 := vreq.endaddr(3 downto 2);
case ad32 is
when "00" => endmask:="1111000000000000";
when "01" => endmask:="1111111100000000";
when "10" => endmask:="1111111111110000";
when others => endmask:="1111111111111111";
end case;
if vreq.startaddr(1)='0' then mask16:="1100110011001100"; else mask16:="0011001100110011"; end if;
if vreq.startaddr(0)='0' then mask8:="1010101010101010"; else mask8:="0101010101010101"; end if;
when 256 =>
case vreq.startaddr(4 downto 2) is
when "000" => startmask:="11111111111111111111111111111111";
when "001" => startmask:="00001111111111111111111111111111";
when "010" => startmask:="00000000111111111111111111111111";
when "011" => startmask:="00000000000011111111111111111111";
when "100" => startmask:="00000000000000001111111111111111";
when "101" => startmask:="00000000000000000000111111111111";
when "110" => startmask:="00000000000000000000000011111111";
when others => startmask:="00000000000000000000000000001111";
end case;
case vreq.endaddr(4 downto 2) is
when "000" => endmask:="11110000000000000000000000000000";
when "001" => endmask:="11111111000000000000000000000000";
when "010" => endmask:="11111111111100000000000000000000";
when "011" => endmask:="11111111111111110000000000000000";
when "100" => endmask:="11111111111111111111000000000000";
when "101" => endmask:="11111111111111111111111100000000";
when "110" => endmask:="11111111111111111111111111110000";
when others => endmask:="11111111111111111111111111111111";
end case;
if vreq.startaddr(1)='0' then mask16:="11001100110011001100110011001100"; else mask16:="00110011001100110011001100110011"; end if;
if vreq.startaddr(0)='0' then mask8:="10101010101010101010101010101010"; else mask8:="01010101010101010101010101010101"; end if;
when others =>
--pragma translate_off
assert false report "Unsupported data bus width" severity failure;
--pragma translate_on
end case;
mask := (others => r.wmaskmode);
nwmaskmode := r.wmaskmode;
if r.wmaskmode='0' then
if r.ramaddr=vreq.startaddr(log2(burstlen*4)-1 downto log2(avldbits/8)) then
mask := startmask;
nwmaskmode:='1';
if r.reading='1' then v.rstarted := '1'; end if;
end if;
end if;
if r.ramaddr=vreq.endaddr(log2(burstlen*4)-1 downto log2(avldbits/8)) then
mask := mask and endmask;
nwmaskmode:='0';
end if;
if vreq.hsize(2 downto 1)="00" then
mask := mask and mask16;
if vreq.hsize(0)='0' then
mask := mask and mask8;
end if;
end if;
rddone := '0';
inc_ramaddr := '0';
rbw := '0';
if r.reading /= '0' then
if avlso.rdata_valid='1' then
rbw := '1';
inc_ramaddr := '1';
if v.rstarted='1' then
v.resp.rctr_gray(log2(avlbl)-1 downto 0) := nextgray(r.resp.rctr_gray(log2(avlbl)-1 downto 0));
end if;
if r.ramaddr=(r.ramaddr'range => '1') then
rddone:='1';
end if;
end if;
else
v.resp.rctr_gray := (others => '0');
end if;
v.beginburst := '0';
case r.s is
when idle =>
if vstart /= r.resp.done_tog then
v.s := acc1;
v.beginburst := '1';
end if;
v.reading := '0';
v.rstarted := '0';
v.wmaskmode := '0';
v.rd := '0';
v.wr := '0';
when acc1 =>
v.wr := vreq.hwrite;
v.rd := not vreq.hwrite;
v.reading := not vreq.hwrite;
if vreq.hwrite='1' then
slvi.write_req := '1';
end if;
if vreq.hwrite/='0' then
v.s := acc2;
end if;
if vreq.hwrite='0' and avlso.ready='1' then
v.s := rdwait;
end if;
if vreq.hwrite = '0' then
mask := (others => '1');
end if;
if avlso.ready='1' and vreq.hwrite/='0' then
inc_ramaddr := '1';
end if;
when acc2 =>
if avlso.ready='1' then
inc_ramaddr := '1';
if r.ramaddr=onev(r.ramaddr'length-1 downto 0) then
v.wr := '0';
v.resp.done_tog := not r.resp.done_tog;
v.s := idle;
end if;
end if;
when rdwait =>
v.rd := '0';
if rddone='1' then
v.resp.done_tog := not r.resp.done_tog;
v.s := idle;
end if;
end case;
if inc_ramaddr/='0' then
v.ramaddr := std_logic_vector(unsigned(r.ramaddr)+1);
v.wmaskmode := nwmaskmode;
end if;
if v.s=idle then
v.ramaddr := (others => '0');
end if;
slvi.read_req := v.rd;
slvi.be(avldbits/8-1 downto 0) := mask;
if rst='0' then
v.s := idle;
v.resp := ddr_response_none;
end if;
nr <= v;
response <= r.resp;
wbraddr <= r.resp.done_tog & v.ramaddr;
rbwaddr <= r.ramaddr;
rbwdata <= avlso.rdata(avldbits-1 downto 0);
rbwrite <= rbw;
avlsi <= slvi;
end process;
regs: process(clk)
begin
if rising_edge(clk) then
r <= nr;
end if;
end process;
end;
|
gpl-2.0
|
c124aad3ee5629881bd31e66272880ef
| 0.583523 | 3.747609 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/techmult.vhd
| 1 | 7,825 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: techmult
-- File: techmult.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multiplier with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.multlib.all;
library techmap;
use techmap.allmul.all;
use techmap.gencomp.all;
entity techmult is
generic (
tech : integer := 0;
arch : integer := 0;
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : natural := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of techmult is
signal gnd, vcc : std_ulogic;
-- pragma translate_off
signal pres : std_ulogic := '0';
signal sonly : std_ulogic := '0';
-- pragma translate_on
begin
gnd <= '0'; vcc <= '1';
np : if num_stages = 1 generate
arch0 : if (arch = 0) generate --inferred
product <= mixed_mul(a, b, sign);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
arch1 : if (arch = 1) generate -- modgen
m1717 : if (a_width = 17) and (b_width = 17) generate
m17 : mul_17_17 generic map (mulpipe => 0)
port map (clk, vcc, a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
m3317 : if (a_width = 33) and (b_width = 17) generate
m33 : mul_33_17 port map (a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
m339 : if (a_width = 33) and (b_width = 9) generate
m33 : mul_33_9 port map (a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
m3333 : if (a_width = 33) and (b_width = 33) generate
m33 : mul_33_33 generic map (mulpipe => 0)
port map (clk, vcc, a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
mgen : if not(((a_width = 17) and (b_width = 17)) or
((a_width = 33) and (b_width = 33)) or
((a_width = 33) and (b_width = 17)) or
((a_width = 33) and (b_width = 9)))
generate
product <= mixed_mul(a, b, sign);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
end generate;
arch2 : if (arch = 2) generate --techspec
axd : if (tech = axdsp) and (a_width = 33) and (b_width = 33) generate
m33 : axcel_mul_33x33_signed generic map (pipe => 0)
port map (a, b, vcc, clk, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
end generate;
arch3 : if (arch = 3) generate -- designware
dwm : mul_dw
generic map (a_width => a_width, b_width => b_width,
num_stages => 1, stall_mode => 0)
port map (a => a, b => b, clk => clk, en => en, sign => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
end generate;
pipe2 : if num_stages = 2 generate
arch0 : if (arch = 0) generate -- inferred
dwm : gen_mult_pipe
generic map (a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode)
port map (a => a, b => b, clk => clk, en => en, tc => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
arch1 : if (arch = 1) generate -- modgen
m1717 : if (a_width = 17) and (b_width = 17) generate
m17 : mul_17_17 generic map (mulpipe => 1)
port map (clk, en, a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
m3333 : if (a_width = 33) and (b_width = 33) generate
m33 : mul_33_33 generic map (mulpipe => 1)
port map (clk, en, a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
end generate;
arch2 : if (arch = 2) generate --techspec
axd : if (tech = axdsp) and (a_width = 33) and (b_width = 33) generate
m33 : axcel_mul_33x33_signed generic map (pipe => 1)
port map (a, b, en, clk, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
end generate;
arch3 : if (arch = 3) generate -- designware
dwm : mul_dw
generic map (a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode)
port map (a => a, b => b, clk => clk, en => en, sign => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
end generate;
pipe3 : if num_stages > 2 generate
arch0 : if (arch = 0) generate -- inferred
dwm : gen_mult_pipe
generic map (a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode)
port map (a => a, b => b, clk => clk, en => en, tc => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
arch3 : if (arch = 3) generate -- designware
dwm : mul_dw
generic map (a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode)
port map (a => a, b => b, clk => clk, en => en, sign => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
end generate;
-- pragma translate_off
process begin
wait for 5 ns;
assert pres = '1' report "techmult: configuration not supported. (width " &
tost(a_width) & "x" & tost(b_width) & ", tech " & tost(tech) & ", arch " &
tost(arch) & ")"
severity failure;
wait;
end process;
process begin
wait for 5 ns;
assert not ((sonly = '1') and (sign = '0')) report "techmult: unsinged multiplication for this configuration not supported"
severity failure;
if sonly = '1' then wait on sign; else wait; end if;
end process;
-- pragma translate_on
end;
|
gpl-2.0
|
94b21df5e09f9494a1b12ed4b11876f5
| 0.561278 | 3.539123 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/topadder00.vhd
| 1 | 1,415 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity topadder00 is
port(
clkadd: in std_logic ;
codopadd: in std_logic_vector ( 3 downto 0 );
inFlagadd: in std_logic ;
portAaddin: in std_logic_vector ( 7 downto 0 );
portBaddin: in std_logic_vector ( 7 downto 0 );
SLaddin: in std_logic ;
LEDaddin: in std_logic ;
portAaddout: out std_logic_vector ( 7 downto 0 );
portBaddout: out std_logic_vector ( 7 downto 0 );
SLaddout: out std_logic ;
LEDaddout: out std_logic ;
outFlagadd: out std_logic;
Soaddin: in std_logic_vector ( 7 downto 0 );
Soaddout: out std_logic_vector ( 7 downto 0 ) );
end;
architecture topadder0 of topadder00 is
begin
padd: process(clkadd, inFlagadd)
begin
if (clkadd'event and clkadd = '1') then
if ((codopadd = "0101") or (codopadd = "0110")) then
portAaddout <= portAaddin;
portBaddout <= portBaddin;
SLaddout <= SLaddin;
if (inFlagadd = '1') then
Soaddout <= Soaddin;
LEDaddout <= LEDaddin;
outFlagadd <= '1';
else
outFlagadd <= '0';
end if;
else
Soaddout <= (others => 'Z');
outFlagadd <= 'Z';
LEDaddout <= 'Z';
end if;
end if;
end process padd;
end topadder0;
|
apache-2.0
|
f5f1b4c2188554642397dcef6aa3a6ec
| 0.575972 | 3.493827 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/uart/libdcom.vhd
| 1 | 5,353 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libdcom
-- File: libdcom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Types, functions and components for DSU uart
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use gaisler.misc.all;
package libdcom is
type dcom_uart_in_type is record
read : std_ulogic;
write : std_ulogic;
data : std_logic_vector(7 downto 0);
end record;
type dcom_uart_out_type is record
dready : std_ulogic;
tsempty : std_ulogic;
thempty : std_ulogic;
lock : std_ulogic;
enable : std_ulogic;
data : std_logic_vector(7 downto 0);
end record;
component dcom_uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end component;
component dcom
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
uarti : out dcom_uart_in_type;
uarto : in dcom_uart_out_type;
ahbi : in ahb_mst_in_type
);
end component;
-- pragma translate_off
procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time);
procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time; lresp : boolean);
procedure txc(signal txd : out std_logic; td : integer;
txperiod : time);
procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
txperiod : time);
procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
td1, td2, td3, td4 : integer; txperiod : time;
lresp : boolean);
-- pragma translate_on
end;
-- pragma translate_off
package body libdcom is
procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time) is
variable rxdata : std_logic_vector(7 downto 0);
begin
wait until rxd = '0'; wait for TXPERIOD/2;
for i in 0 to 7 loop wait for TXPERIOD; rxdata(i):= rxd; end loop;
wait for TXPERIOD ;
d := rxdata;
end;
procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time; lresp : boolean) is
variable rxdata : std_logic_vector(31 downto 0);
variable resp : std_logic_vector(7 downto 0);
begin
for i in 3 downto 0 loop
rxc(rxd, rxdata((i*8 +7) downto i*8), txperiod);
end loop;
d := rxdata;
if LRESP then
rxc(rxd, resp, txperiod);
-- print("RESP : 0x" & tosth(resp));
end if;
end;
procedure txc(signal txd : out std_logic; td : integer;
txperiod : time) is
variable txdata : std_logic_vector(10 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td, 8) & '0';
for i in 0 to 10 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
end;
procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
txperiod : time) is
variable txdata : std_logic_vector(43 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
& "11" & conv_std_logic_vector(td3, 8) & '0'
& "11" & conv_std_logic_vector(td2, 8) & '0'
& "11" & conv_std_logic_vector(td1, 8) & '0';
for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
end;
procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
td1, td2, td3, td4 : integer; txperiod : time;
lresp : boolean) is
variable txdata : std_logic_vector(43 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
& "11" & conv_std_logic_vector(td3, 8) & '0'
& "11" & conv_std_logic_vector(td2, 8) & '0'
& "11" & conv_std_logic_vector(td1, 8) & '0';
for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
if LRESP then
rxc(rxd, txdata(7 downto 0), txperiod);
-- print("RESP : 0x" & tosth(txdata(7 downto 0)));
end if;
end;
end;
-- pragma translate_on
|
gpl-2.0
|
87a018a4c937dcffb847d5f3f4145e9d
| 0.606576 | 3.316605 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbram.vhd
| 1 | 9,212 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
aram : syncrambw generic map (tech, abits, dw, scantest) port map (
clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
|
gpl-2.0
|
e19b19565793b5c7cc6f1efc9e5d80d7
| 0.555797 | 3.3645 | false | false | false | false |
BOT-Man-JL/BUPT-Projects
|
2-2-Digital-Logic/Display.vhd
| 1 | 1,540 |
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Entity Display Is
Port (
counting_i: In std_logic_vector (23 downto 0);
blink_i: In std_logic;
out0_o: Out std_logic_vector (6 downto 0);
out1_o: Out std_logic_vector (3 downto 0);
out2_o: Out std_logic_vector (3 downto 0);
out3_o: Out std_logic_vector (3 downto 0);
out4_o: Out std_logic_vector (3 downto 0);
out5_o: Out std_logic_vector (3 downto 0)
);
End Entity;
Architecture fDisplay Of Display Is
Signal tmp: std_logic_vector (23 downto 0);
Begin
Process (blink_i, counting_i, tmp)
Begin
-- Lock Hell
-- If lock_i'Event And lock_i ='1' Then
tmp <= counting_i;
-- End If;
If blink_i = '1' Then
out5_o <= tmp (23 downto 20);
out4_o <= tmp (19 downto 16);
out3_o <= tmp (15 downto 12);
out2_o <= tmp (11 downto 8);
out1_o <= tmp (7 downto 4);
Case tmp (3 downto 0) Is
When "0000" => out0_o <= "1111110";
When "0001" => out0_o <= "0110000";
When "0010" => out0_o <= "1101101";
When "0011" => out0_o <= "1111001";
When "0100" => out0_o <= "0110011";
When "0101" => out0_o <= "1011011";
When "0110" => out0_o <= "0011111";
When "0111" => out0_o <= "1110000";
When "1000" => out0_o <= "1111111";
When "1001" => out0_o <= "1111011";
When Others => out0_o <= "0000000";
End Case;
Else
out5_o <= "1111";
out4_o <= "1111";
out3_o <= "1111";
out2_o <= "1111";
out1_o <= "1111";
out0_o <= "0000000";
End If;
End Process;
End Architecture;
|
gpl-3.0
|
de92365009adcc9d81a9d3c0634ea453
| 0.585714 | 2.601351 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys4/leon3mp.vhd
| 1 | 26,816 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.BUFG;
use unisim.PLLE2_ADV;
use unisim.STARTUPE2;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
clk : in std_ulogic;
-- onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
--RamWait : in std_ulogic;
QspiCSn : out std_ulogic;
QspiDB : inout std_logic_vector(3 downto 0);
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- 7 segment display
--seg : out std_logic_vector(6 downto 0);
--an : out std_logic_vector(7 downto 0);
-- LEDs
Led : out std_logic_vector(15 downto 0);
-- Switches
sw : in std_logic_vector(15 downto 0);
-- Buttons
btnCpuResetn : in std_ulogic;
btn : in std_logic_vector(4 downto 0);
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
PhyRstn : out std_ulogic;
PhyCrs : in std_ulogic;
PhyClk50Mhz : out std_ulogic;
PhyTxd : out std_logic_vector(1 downto 0);
PhyTxEn : out std_ulogic;
PhyRxd : in std_logic_vector(1 downto 0);
PhyRxEr : in std_ulogic;
PhyMdc : out std_ulogic;
PhyMdio : inout std_logic;
-- Pic USB-HID interface
--~ PS2KeyboardData : inout std_logic;
--~ PS2KeyboardClk : inout std_logic;
--~ PS2MouseData : inout std_logic;
--~ PS2MouseClk : inout std_logic;
--~ PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal eth_pll_rst : std_logic;
signal eth_clk_nobuf : std_logic;
signal eth_clk90_nobuf : std_logic;
signal eth_clk : std_logic;
signal eth_clk90 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal btnCpuReset : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(15 downto 4) <= (others =>'0'); -- unused leds off
btnCpuReset<= not btnCpuResetn;
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 23)
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech)
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech)
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech)
port map (RamWE, memo.writen);
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
RamCRE <= '0';
RamClk <= '0';
RamAdv <= '0';
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 7, hirq => 7, faddr => 16#b00#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => 0, readcmd => 16#0B#, dummybyte => 1, dualoutput => 0,
scaler => 1, altscaler => 2)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--QspiDB(3) <= '1'; QspiDB(2) <= '1';
spi_QspiDB_2_pad : outpad generic map (tech => padtech)
port map (QspiDB(2), '1');
spi_QspiDB_3_pad : outpad generic map (tech => padtech)
port map (QspiDB(3), '1');
-- spi_bdr : iopad generic map (tech => padtech)
-- port map (QspiDB(0), spmo.mosi, spmo.mosioen, spmi.mosi);
spi_mosi_pad : outpad generic map (tech => padtech)
port map (QspiDB(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (QspiDB(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (QspiCSn, spmo.csn);
-- MACRO for assigning the SPI output clock
spicclk: STARTUPE2
port map (--CFGCLK => open, CFGMCLK => open, EOS => open, PREQ => open,
CLK => '0', GSR => '0', GTS => '0', KEYCLEARB => '0', PACK => '0',
USRCCLKO => spmo.sck, USRCCLKTS => '0', USRDONEO => '1', USRDONETS => '0' );
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G, rmii => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
PhyRstn<=rstn;
end generate;
etxc_pad : outpad generic map (tech => padtech)
port map (PhyClk50Mhz, eth_clk);
ethpads : if (CFG_GRETH = 1) generate
emdio_pad : iopad generic map (tech => padtech)
port map (PhyMdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
ethi.rmii_clk<=eth_clk90;
erxd_pad : inpadv generic map (tech => padtech, width => 2) --8
port map (PhyRxd, ethi.rxd(1 downto 0));
erxer_pad : inpad generic map (tech => padtech)
port map (PhyRxEr, ethi.rx_er);
erxcr_pad : inpad generic map (tech => padtech)
port map (PhyCrs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 2)
port map (PhyTxd, etho.txd(1 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (PhyTxEn, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (PhyMdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 4 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-----------------------------------------------------------------------
--- Ethernet Clock Generation ---------------------------------------
-----------------------------------------------------------------------
-- 50 MHz clock for output
bufgclk0 : BUFG port map (I => eth_clk_nobuf, O => eth_clk);
-- 50 MHz with +90 deg phase for Rx GRETH
bufgclk45 : BUFG port map (I => eth_clk90_nobuf, O => eth_clk90);
CLKFBIN <= CLKFBOUT;
eth_pll_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000000.0/real(100000.0),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 16,
CLKOUT1_DIVIDE => 16,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => eth_clk_nobuf,
CLKOUT1 => eth_clk90_nobuf,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => open,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => eth_pll_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
end rtl;
|
gpl-2.0
|
5e5cf9b1ada9cc9a0d6dffc7458b3a3b
| 0.522822 | 3.834692 | false | false | false | false |
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