repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc3s1000/leon3mp.vhd
| 1 | 17,011 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
error : out std_ulogic;
address : out std_logic_vector(19 downto 2);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (1 downto 0);
mben : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
-- switch : in std_logic_vector(7 downto 0); -- switches
-- button : in std_logic_vector(2 downto 0); -- buttons
ps2clk : inout std_logic;
ps2data : inout std_logic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic;
vid_g : out std_logic;
vid_b : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+
CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, nerror : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, rst : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkval : std_logic_vector(1 downto 0);
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 0;
signal stati : ahbstat_in_type;
signal dac_clk, clk1x, vid_clock, video_clk, clkvga : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
nerror <= not dbgo(0).error;
error_pad : outpad generic map (tech => padtech) port map (error, nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0: ahbuart -- Debug UART
-- generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
-- end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
rommask => 16#000#, iomask => 16#000#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 18, tech => padtech)
port map (address, memo.address(19 downto 2));
ramsa_pad : outpad generic map (tech => padtech)
port map (ramsn(0), memo.ramsn(0));
ramsb_pad : outpad generic map (tech => padtech)
port map (ramsn(1), memo.ramsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
mben_pads : outpadv generic map (tech => padtech, width => 4)
port map (mben, memo.mben);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (data, memo.data(31 downto 0),
memo.vbdrive(31 downto 0), memi.data(31 downto 0));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
dac_clk <= not video_clk;
b1 : techbuf generic map (2, virtex2) port map (clkval(0), video_clk);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
clkvga <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (clkvga, video_clk);
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 20000, clk2 => 25000)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_JTAG), clk_sel);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpad generic map (tech => padtech)
port map (vid_r, vgao.video_out_r(7));
video_out_g_pad : outpad generic map (tech => padtech)
port map (vid_g, vgao.video_out_g(7));
video_out_b_pad : outpad generic map (tech => padtech)
port map (vid_b, vgao.video_out_b(7));
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pads : iopadvv generic map (width => 18, tech => padtech)
port map (pio, gpioo.dout(17 downto 0), gpioo.oen(17 downto 0),
gpioi.din(17 downto 0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+FG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent XC3S1000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
bda7762cd92d5be325f1018d0d20397b
| 0.558991 | 3.655921 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbtrace_mb.vhd
| 1 | 3,192 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mb
-- File: ahbtrace_mb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end;
architecture rtl of ahbtrace_mb is
signal tahbmiv : ahb_mst_in_vector_type(0 to 0);
signal tahbsiv : ahb_slv_in_vector_type(0 to 0);
begin
tahbmiv(0) <= tahbmi;
tahbsiv(0) <= tahbsi;
ahbt0 : ahbtrace_mmb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
bwidth => bwidth,
ahbfilt => ahbfilt,
ntrace => 1,
scantest => scantest,
exttimer => exttimer,
exten => exten)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmiv => tahbmiv,
tahbsiv => tahbsiv,
timer => timer,
astat => astat,
resen => resen);
end;
|
gpl-2.0
|
53410d81e59cba2628400bcd5b1efeab
| 0.568609 | 3.897436 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/grethm_mb.vhd
| 1 | 7,131 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethm_mb
-- File: grethm_mb.vhd
-- Author: Andrea Gianarro
-- Description: Module to select between greth_mb and greth_gbit_mb
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
entity grethm_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of grethm_mb is
begin
m100 : if giga = 0 generate
u0 : greth_mb
generic map (
hindex => hindex,
ehindex => ehindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahb => edclsepahb,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
ahbmi2 => ahbmi2,
ahbmo2 => ahbmo2,
apbi => apbi,
apbo => apbo,
ethi => ethi,
etho => etho);
end generate;
m1000 : if giga = 1 generate
u0 : greth_gbit_mb
generic map (
hindex => hindex,
ehindex => ehindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahb => edclsepahb,
ramdebug => ramdebug,
mdiohold => mdiohold,
gmiimode => gmiimode
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
ahbmi2 => ahbmi2,
ahbmo2 => ahbmo2,
apbi => apbi,
apbo => apbo,
ethi => ethi,
etho => etho,
mdchain_ui => greth_mdiochain_down_first,
mdchain_uo => open,
mdchain_di => open,
mdchain_do => greth_mdiochain_up_last);
end generate;
end architecture;
|
gpl-2.0
|
da08dbb87d7338ae0b6de26c4ed55cba
| 0.46992 | 4.399136 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de2-115/leon3mp.vhd
| 1 | 26,928 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clock_50 : in std_logic;
sma_clkout : out std_ulogic;
errorn : out std_logic;
fl_addr : out std_logic_vector(22 downto 0);
fl_dq : inout std_logic_vector(7 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dq : inout std_logic_vector(31 downto 0);
dram_clk : out std_logic;
dram_cke : out std_logic;
dram_cs_n : out std_logic;
dram_we_n : out std_logic; -- sdram write enable
dram_ras_n : out std_logic; -- sdram ras
dram_cas_n : out std_logic; -- sdram cas
dram_dqm : out std_logic_vector (3 downto 0); -- sdram dqm
uart_txd : out std_logic; -- DSU tx data
uart_rxd : in std_logic; -- DSU rx data
dsubre : in std_logic;
dsuact : out std_logic;
fl_oe_n : out std_logic;
fl_we_n : out std_logic;
fl_rst_n : out std_logic;
fl_wp_n : out std_logic;
fl_ce_n : out std_logic;
-- gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpio : inout std_logic_vector(35 downto 0); -- I/O port
enet0_mdio : inout std_logic; -- ethernet PHY interface
enet0_gtx_clk : in std_logic;
enet0_rx_clk : in std_logic;
enet0_tx_clk : in std_logic;
enet0_rx_data: in std_logic_vector(3 downto 0);
enet0_rx_dv : in std_logic;
enet0_rx_er : in std_logic;
enet0_rx_col : in std_logic;
enet0_rx_crs : in std_logic;
enet0_int_n : in std_logic;
enet0_rst_n : out std_logic;
enet0_tx_data: out std_logic_vector(3 downto 0);
enet0_tx_en : out std_logic;
enet0_tx_er : out std_logic;
enet0_mdc : out std_logic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1);
sw : in std_logic_vector(0 to 2) := "000"
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal spii, spislvi : spi_in_type;
signal spio, spislvo : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal dsubren : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => BOARD_FREQ, clk2xen => 1)
port map (clkin => clock_50, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => sma_clkout, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
leon3 : leon3x -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => CFG_NWIN,
dsu => CFG_DSU,
fpu => CFG_FPU + 32*CFG_GRFPUSH,
v8 => CFG_V8,
cp => 0,
mac => CFG_MAC,
pclow => pclow,
notag => CFG_NOTAG,
nwp => CFG_NWP,
icen => CFG_ICEN,
irepl => CFG_IREPL,
isets => CFG_ISETS,
ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ,
isetlock => CFG_ILOCK,
dcen => CFG_DCEN,
drepl => CFG_DREPL,
dsets => CFG_DSETS,
dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ,
dsetlock => CFG_DLOCK,
dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN,
ilramsize => CFG_ILRAMSZ,
ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN,
dlramsize => CFG_DLRAMSZ,
dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN,
itlbnum => CFG_ITLBNUM,
dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE,
tlb_rep => CFG_TLB_REP,
lddel => CFG_LDDEL,
disas => disas,
tbuf => CFG_ITBSZ,
pwd => CFG_PWD,
svt => CFG_SVT,
rstaddr => CFG_RSTADDR,
smp => CFG_NCPU-1,
iuft => CFG_IUFT_EN,
fpft => CFG_FPUFT_EN,
cmft => CFG_CACHE_FT_EN,
iuinj => CFG_RF_ERRINJ,
ceinj => CFG_CACHE_ERRINJ,
cached => CFG_DFIXED,
clk2x => 0,
netlist => CFG_LEON3_NETLIST,
scantest => CFG_SCAN,
mmupgsz => CFG_MMU_PAGE,
bp => CFG_BP,
npasi => CFG_NP_ASI)
port map (
clk => clkm, gclk2 => clkm, gfclk2 => clkm, clk2 => clkm, rstn => rstn,
ahbi => ahbmi, ahbo => ahbmo(i), ahbsi => ahbsi, ahbso => ahbso,
irqi => irqi(i), irqo => irqo(i), dbgi => dbgi(i), dbgo => dbgo(i),
fpui => fpi(i), fpuo => fpo(i), clken => vcc(0));
end generate;
sh : if CFG_GRFPUSH /= 0 generate
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nosh : if CFG_GRFPUSH = 0 generate
fpo <= (others => grfpu_out_none);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dui.rxd <= uart_rxd when sw(0) = '0' else '1';
-- dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= '0'; memi.bwidth <= "00";
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL, iomask => 0,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (fl_addr, memo.address(22 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (fl_oe_n, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (fl_we_n, memo.writen);
fl_rst_pad : outpad generic map (tech => padtech)
port map (fl_rst_n, rstn);
fl_wp_pad : outpad generic map (tech => padtech)
port map (fl_wp_n, vcc(0));
data_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (fl_dq, memo.data(31 downto 24), memo.vbdrive(31 downto 24), memi.data(31 downto 24));
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 13)
port map (dram_addr, memo.sa(12 downto 0));
ba_pad : outpadv generic map (width => 2)
port map (dram_ba, memo.sa(14 downto 13));
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (dram_dq(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (dram_dqm, sdo.dqm(3 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, vcc(0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= '1' when sw(0) = '0' else uart_rxd; u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
uart_txd <= u1o.txd when sw(0) = '1' else duo.txd;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : iopad generic map (tech => padtech)
port map (gpio(35), spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (gpio(34), spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (gpio(33), spio.sck, spio.sckoen, spii.sck);
slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(32), slvsel(0), gnd(0), open);
end generate spic;
spibridge : if CFG_SPI2AHB /= 0 generate -- SPI to AHB bridge
withapb : if CFG_SPI2AHB_APB /= 0 generate
spi2ahb0 : spi2ahb_apb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
resen => CFG_SPI2AHB_RESEN, pindex => 11, paddr => 11, pmask => 16#fff#,
pirq => 11, filter => CFG_SPI2AHB_FILTER, cpol => CFG_SPI2AHB_CPOL,
cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi, apbo(11), spislvi, spislvo);
end generate;
woapb : if CFG_SPI2AHB_APB = 0 generate
spi2ahb0 : spi2ahb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
filter => CFG_SPI2AHB_FILTER,
cpol => CFG_SPI2AHB_CPOL, cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
spislvi, spislvo);
end generate;
spislv_miso_pad : iopad generic map (tech => padtech)
port map (gpio(31), spislvo.miso, spislvo.misooen, spislvi.miso);
spislvl_mosi_pad : iopad generic map (tech => padtech)
port map (gpio(30), spislvo.mosi, spislvo.mosioen, spislvi.mosi);
spislv_sck_pad : iopad generic map (tech => padtech)
port map (gpio(29), spislvo.sck, spislvo.sckoen, spislvi.sck);
spislv_slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(28), gnd(0), vcc(0), spislvi.spisel);
end generate;
nospibridge : if CFG_SPI2AHB = 0 or CFG_SPI2AHB_APB = 0 generate
apbo(11) <= apb_none;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 16,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (enet0_gtx_clk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (enet0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (enet0_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (enet0_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (enet0_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (enet0_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (enet0_rx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (enet0_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (enet0_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (enet0_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (enet0_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (enet0_mdc, etho.mdc);
eth0_rst_pad : odpad generic map (tech => padtech)
port map (enet0_rst_n, rstn);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 7, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(7));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 TerAsic DE2_115 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
a7c5a774a486d3d269c100110c2ec22d
| 0.553959 | 3.53525 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-de2-ep2c35/testbench.vhd
| 1 | 8,600 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 22 -- rom address depth (flash 4 MB)
-- sramwidth : integer := 32; -- ram data width (8/16/32)
-- sramdepth : integer := 20; -- ram address depth
-- srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal data : std_logic_vector(31 downto 24);
signal romsn : std_logic;
signal oen : std_logic;
signal writen : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal error : std_logic;
signal gpio_0 : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal gpio_1 : std_logic_vector(CFG_GRGPIO2_WIDTH-1 downto 0);
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal dram_ldqm : std_logic;
signal dram_udqm : std_logic;
signal sdclk : std_logic;
signal sw : std_logic_vector(0 to 2);
signal ps2_clk : std_logic;
signal ps2_dat : std_logic;
signal vga_clk : std_ulogic;
signal vga_blank : std_ulogic;
signal vga_sync : std_ulogic;
signal vga_hs : std_ulogic;
signal vga_vs : std_ulogic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(13 downto 0);
signal sd : std_logic_vector(15 downto 0);
begin
clk <= not clk after ct * 1 ns; --50 MHz clk
rst <= dsurst; --reset
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
sw(0) <= '1';
gpio_0(CFG_GRGPIO_WIDTH-1 downto 0) <= (others => 'H');
gpio_1(CFG_GRGPIO2_WIDTH-1 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, error, address(21 downto 0), data,
sa(11 downto 0), sa(12), sa(13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, dram_ldqm, dram_udqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, romsn, open, open, open, open, open, open, gpio_0, gpio_1,
ps2_clk, ps2_dat, vga_clk, vga_blank, vga_sync, vga_hs, vga_vs, vga_r,
vga_g, vga_b, sw);
sd1 : if (CFG_SDCTRL = 1) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 12, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(11 downto 0),
Ba => sa(13 downto 12), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0'; --reset low
wait for 500 ns;
dsurst <= '1'; --reset high
wait; --evig w8
wait for 5000 ns;
txc(dsutx, 16#55#, txp);
-- txc(dsutx, 16#c0#, txp); --control byte
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); --adress
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); --write data
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
891900818de1e60b92dbf9a6ae4fda99
| 0.579884 | 3.080229 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-pci-xc2v3000/testbench.vhd
| 1 | 11,762 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_logic;
constant lresp : boolean := false;
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal pllref : std_logic;
signal spw_rxd : std_logic_vector(0 to 1) := "00";
signal spw_rxs : std_logic_vector(0 to 1) := "00";
signal spw_txd : std_logic_vector(0 to 1);
signal spw_txs : std_logic_vector(0 to 1);
begin
-- clock and reset
spw_rxd(0) <= spw_txd(0);
spw_rxs(0) <= spw_txs(0);
spw_rxd(1) <= spw_txd(1);
spw_rxs(1) <= spw_txs(1);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
pllref <= sdclk;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, pllref, error, address(27 downto 0), data,
sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
spw_rxd, spw_rxs, spw_txd, spw_txs);
-- sdram
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
aa68b575e12b2e86b2390c46b5426ef0
| 0.577793 | 3.04952 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2sgx90-av/sram32.vhd
| 1 | 2,725 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram32
-- File: sram32.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 32-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram32 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1Kx32)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(31 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram32 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+3, abits, tacc, fname)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index+2, abits, tacc, fname)
port map (a, d(15 downto 8), cex(1), we, oe);
sr2 : sram generic map (index+1, abits, tacc, fname)
port map (a, d(23 downto 16), cex(1), we, oe);
sr3 : sram generic map (index, abits, tacc, fname)
port map (a, d(31 downto 24), cex(1), we, oe);
end sim;
-- pragma translate_on
|
gpl-2.0
|
d05e2c2a786727eeb79883f9bd533694
| 0.594128 | 3.707483 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-pci-xc5v/leon3mp.vhd
| 1 | 43,507 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
eth_macclk : in std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
emdintn : in std_logic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_clkl : std_logic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal tck, tms, tdi, tdo : std_logic;
signal usbi : grusb_in_vector(0 downto 0);
signal usbo : grusb_out_vector(0 downto 0);
signal uclk : std_ulogic := '0';
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_GRPCI2_MASTER + CFG_GRUSBHC +
CFG_GRUSBDC;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock and ulock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+
CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+
CFG_GRUSBHC*(CFG_GRUSBHC_EHC+CFG_GRUSBHC_UHC)+
CFG_GRUSBDC*CFG_GRUSBDC_AIFACE+
CFG_GRUSB_DCL,
nahbs => 8+CFG_GRUSBHC*CFG_GRUSBHC_UHC+CFG_GRUSBDC)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 6, paddr => 6, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(6), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(6) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pci : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
grpci2xt : if (CFG_GRPCI2_TARGET) /= 0 and (CFG_GRPCI2_MASTER+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech, oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#,
tbpmask => 16#C00#)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, open, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xmt : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) > 1 and (CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech, oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#,
tbpmask => 16#C00#)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech, oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#,
tbpmask => 16#C00#)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (eth_macclk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (emdintn, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i,
paddr => 10+i, pirq => 10+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN,
netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(0), spw_rxdn(0), spwi(0).d(0));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(0), spw_rxsn(0), spwi(0).s(0));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(0), spw_txdn(0), spwi(0).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(0), spw_txsn(0), spwi(0).s(0), gnd(0));
end generate;
-------------------------------------------------------------------------------
-- USB ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that more than one USB component can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
-- similiar.
usb_clkout_pad : clkpad
generic map (tech => padtech, arch => 3)
port map (usb_clkout, uclk, cgo.clklock, ulock);
usb_d_pad: iopadv
generic map(tech => padtech, width => 8)
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
usbi(0).datain(7 downto 0));
usb_nxt_pad : inpad generic map (tech => padtech)
port map (usb_nxt, usbi(0).nxt);
usb_dir_pad : inpad generic map (tech => padtech)
port map (usb_dir, usbi(0).dir);
usb_resetn_pad : outpad generic map (tech => padtech)
port map (usb_resetn, usbo(0).reset);
usb_stp_pad : outpad generic map (tech => padtech)
port map (usb_stp, usbo(0).stp);
end generate usbpads;
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
ulock <= '1';
end generate nousb;
-----------------------------------------------------------------------------
-- USB 2.0 Host Controller
-----------------------------------------------------------------------------
usbhc0: if CFG_GRUSBHC = 1 generate
usbhc0 : grusbhc
generic map (
ehchindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 13, ehcpmask => 16#fff#,
uhchindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1,
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 9, tech => fabtech,
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
port map (
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1
downto
CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1),
ahbso(8 downto 8),
usbo,usbi);
end generate usbhc0;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 8, hirq => 6, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech, keepclk => 1)
port map(
uclk => uclk,
usbi => usbi(0),
usbo => usbo(0),
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
memtech => memtech, keepclk => 1, uiface => 1)
port map (
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC5LX50 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
6a21bd5a49e3e73fd03df4c67a6b2060
| 0.553681 | 3.432776 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/testgrouppolito/pr/dprc.vhd
| 1 | 13,022 |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: dprc
-- File: dprc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: Top entity of the dynamic partial reconfiguration controller for Xilinx FPGAs
-- (see the DPRC IP-core user manual for configuration and operations).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library techmap;
use techmap.gencomp.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library unisim;
use unisim.vcomponents.all;
--pragma translate_off
use std.textio.all;
use ieee.std_logic_textio.all;
--pragma translate_on
entity dprc is
generic (
cfg_clkmul : integer := 2; -- clkraw multiplier
cfg_clkdiv : integer := 1; -- clkraw divisor
raw_freq : integer := 50000; -- Board frequency in KHz
clk_sel : integer := 0; -- Select between clkraw and clk100 for ICAP domain clk when configured in async or d2prc mode
hindex : integer := 2; -- AMBA AHB master index
vendorid : integer := VENDOR_CONTRIB; -- Vendor ID
deviceid : integer := CONTRIB_CORE1; -- Device ID
version : integer := 1; -- Device version
pindex : integer := 13; -- AMBA APB slave index
paddr : integer := 13; -- Address for APB I/O BAR
pmask : integer := 16#fff#; -- Mask for APB I/O BAR
technology : integer := virtex4; -- FPGA target technology
crc_en : integer := 0; -- Bitstream verification enable (d2prc mode)
words_block : integer := 10; -- Number of 32-bit words in a CRC-block
fifo_dcm_inst : integer := 0; -- Instantiate clock generator and fifo (async/sync mode)
fifo_depth : integer := 9); -- Number of addressing bits for the FIFO (true FIFO depth = 2**fifo_depth)
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clkraw : in std_ulogic; -- Raw Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
ahbmi : in ahb_mst_in_type; -- AHB master input
ahbmo : out ahb_mst_out_type; -- AHB master output
apbi : in apb_slv_in_type; -- APB slave input
apbo : out apb_slv_out_type; -- APB slave output
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition)
end dprc;
architecture dprc_rtl of dprc is
signal dma_in : DMA_In_Type;
signal dma_out : DMA_Out_Type;
signal icap_in, ricap_in : icap_in_type;
signal icap_out, ricap_out : icap_out_type;
signal clk_icap : std_ulogic;
signal icap_swapped : std_logic_vector(31 downto 0);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal sysrstn : std_ulogic;
signal rego, reg_apbout : dprc_apbregout_type;
signal regi, reg_apbin : dprc_apbregin_type;
signal regcontrol : dprc_apbcontrol_type;
signal wen_del : std_ulogic;
constant pconfig : apb_config_type := (0 => ahb_device_reg (vendorid, deviceid, 0, version, 0), 1 => apb_iobar(paddr, pmask));
--pragma translate_off
file icap_file: TEXT open write_mode is "icap_data";
--pragma translate_on
begin
-- ahb interface
dma2ahb_inst: DMA2AHB
generic map(hindex => hindex, vendorid => vendorid, deviceid => deviceid, version => version)
port map(HCLK => clkm, HRESETn => sysrstn, DMAIn => dma_in, DMAOut => dma_out, AHBIn => ahbmi, AHBOut => ahbmo);
-- apb interface
apbo.pirq <= (others => '0'); --no interrupt
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
comb : process(reg_apbout, reg_apbin, apbi, regcontrol)
variable readdata : std_logic_vector(31 downto 0);
variable regvi : dprc_apbregin_type;
variable regvo : dprc_apbregout_type;
begin
-- assign register outputs to variables
regvi := reg_apbin;
regvo := reg_apbout;
-- read register
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" =>
readdata := reg_apbin.control;
when "001" =>
readdata := reg_apbin.address;
when "010" =>
readdata := reg_apbout.status;
when "011" =>
readdata := reg_apbout.timer;
when "100" =>
readdata := reg_apbin.rm_reset;
when others =>
readdata := (others => '0');
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
regvi.control := apbi.pwdata;
when "001" =>
regvi.address := apbi.pwdata;
when "100" =>
regvi.rm_reset := apbi.pwdata;
when others =>
end case;
end if;
-- timer
if regcontrol.timer_clear='1' then
regvo.timer := (others=>'0');
elsif regcontrol.timer_en='1' then
regvo.timer := regvo.timer+'1';
end if;
-- clear control registers
if regcontrol.control_clr='1' then
regvi.control := (others=>'0');
end if;
-- update status
if (regcontrol.status_clr='1') then
regvo.status := (others=>'0');
elsif regcontrol.status_en='1' then
regvo.status := regcontrol.status_value;
end if;
-- assign variables to register inputs
regi <= regvi;
rego <= regvo;
-- drive bus with read data
apbo.prdata <= readdata;
end process;
regs : process(clkm,sysrstn)
begin
if (sysrstn='0') then
reg_apbin.control <= (others => '0');
reg_apbin.address <= (others => '0');
reg_apbin.rm_reset <= (others => '0');
reg_apbout.status(31 downto 4) <= (others => '0');
reg_apbout.status(3 downto 0) <= (others => '1');
reg_apbout.timer <= (others => '0');
elsif rising_edge(clkm) then
reg_apbin <= regi;
reg_apbout <= rego;
end if;
end process;
-- Register ICAP I/Os
regs_icap: process(clk_icap, sysrstn)
begin
if (sysrstn='0') then
ricap_out.odata<=(others=>'0');
ricap_out.busy<='0';
ricap_in.idata<=(others=>'0');
ricap_in.cen<='1';
ricap_in.wen<='1';
wen_del <= '1';
elsif rising_edge(clk_icap) then
ricap_out <= icap_out;
ricap_in <= icap_in;
wen_del <= ricap_in.wen;
end if;
end process;
-- operating mode selection
d2prc_gen: if crc_en=1 generate
d2prc_inst : d2prc
generic map (technology => technology, crc_block => words_block, fifo_depth => fifo_depth)
port map (rstn => sysrstn, clkm => clkm, clk100 => clk_icap, dmai => dma_in, dmao => dma_out, icapi => icap_in, icapo => ricap_out, apbregi => reg_apbin, apbcontrol => regcontrol, rm_reset => rm_reset);
end generate;
asyncsync_gen: if crc_en=0 generate
async_gen: if fifo_dcm_inst=1 generate
async_dprc_inst : async_dprc
generic map(technology => technology, fifo_depth => fifo_depth)
port map(rstn => sysrstn, clkm => clkm, clk100 => clk_icap, dmai => dma_in, dmao => dma_out, icapi => icap_in, icapo => ricap_out, apbregi => reg_apbin, apbcontrol => regcontrol, rm_reset => rm_reset);
end generate;
sync_gen: if fifo_dcm_inst=0 generate
sync_dprc_inst: sync_dprc
port map(rstn => sysrstn, clkm => clkm, dmai => dma_in, dmao => dma_out, icapi => icap_in, icapo => ricap_out, apbregi => reg_apbin, apbcontrol => regcontrol, rm_reset => rm_reset);
end generate;
end generate;
-- clock generation (if necessary)
clock_gen: if (crc_en=1 or fifo_dcm_inst=1) generate
ext_clk_gen: if clk_sel=1 generate
clk_icap <= clk100; -- 100 MHz external clock
sysrstn <= rstn;
end generate;
int_clk_gen: if clk_sel=0 generate -- instantiate internal clock generator
cgi.pllctrl <= "00"; cgi.pllrst <= rstn;
clkgen_inst : clkgen
generic map (technology, cfg_clkmul, cfg_clkdiv, 0, 0, 0, 0, 0, raw_freq)
port map (clkin => clkraw, pciclkin => '0', clk => clk_icap, cgi => cgi, cgo => cgo);
sysrstn <= cgo.clklock;
end generate;
end generate;
noclock_gen: if (crc_en=0 and fifo_dcm_inst=0) generate
clk_icap <= clkm; -- system clock
sysrstn <= rstn;
end generate;
-- ICAP input data byte swapping (if necessary)
swap_gen: if (technology=virtex5 or technology=virtex6 or technology=virtex7 or technology=artix7 or technology=kintex7 or technology=zynq7000) generate
icapbyteswap(ricap_in.idata,icap_swapped);
end generate;
-- ICAP instantiation
icapv4_gen: if (technology=virtex4) generate
icap_virtex4_inst: ICAP_VIRTEX4
generic map (ICAP_WIDTH => "X32")
port map (BUSY => icap_out.busy, O => icap_out.odata, CE => ricap_in.cen, CLK => clk_icap, I => ricap_in.idata, WRITE => wen_del);
end generate;
icapv5_gen: if (technology=virtex5) generate
icap_virtex5_inst: ICAP_VIRTEX5
generic map (ICAP_WIDTH => "X32") -- 32 bit data width
port map (BUSY => icap_out.busy, O => icap_out.odata, CE => ricap_in.cen, CLK => clk_icap, I => icap_swapped, WRITE => wen_del);
end generate;
icapv6_gen: if (technology=virtex6) generate
icap_virtex6_inst: ICAP_VIRTEX6
generic map (DEVICE_ID => X"04244093", ICAP_WIDTH => "X32", SIM_CFG_FILE_NAME => "NONE")
port map (BUSY => icap_out.busy, O => icap_out.odata, CSB => ricap_in.cen, CLK => clk_icap, I => icap_swapped, RDWRB => wen_del);
end generate;
icap7_gen: if (technology=virtex7 or technology=artix7 or technology=kintex7 or technology=zynq7000) generate
icap_7series_inst: ICAPE2
generic map ( DEVICE_ID => X"03631093", ICAP_WIDTH => "X32", SIM_CFG_FILE_NAME => "NONE")
port map (O => icap_out.odata, CSIB => ricap_in.cen, CLK => clk_icap, I => icap_swapped, RDWRB => wen_del);
end generate;
--pragma translate_off
-- write ICAP inputs to a file for verification purposes
wfile: process
variable l : line;
begin
while true loop
wait until rising_edge(clk_icap);
wait for 1 ns;
if ricap_in.cen='0' and wen_del='0' then
write(l, ricap_in.idata);
writeline(icap_file, l);
end if;
end loop;
end process;
--pragma translate_on
end dprc_rtl;
|
gpl-2.0
|
29d1a093b5c99acc697abc48a250e840
| 0.581631 | 4.049129 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/serdes_stratixiii.vhd
| 1 | 8,905 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes_stratixiii
-- File: serdes_stratixiii.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: Stratix III and IV SGMII Gigabit Ethernet Serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity serdes_stratixiii is
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end entity;
architecture rtl of serdes_stratixiii is
signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rst_int, pll_areset_int, rx_locked_int, rx_rstn_int_0, tx_locked_int : std_logic;
signal rx_cda_reset_int, bitslip_int, rx_in_int, rx_rst_int, rx_divfwdclk_int, tx_out_int : std_logic_vector(0 downto 0) ;
signal rx_clk_rstn_int, rx_pll_rstn_int, tx_pll_rstn_int, rx_cda_reset_int_0 : std_logic;
signal rx_out_int, tx_in_int : std_logic_vector(9 downto 0) ;
signal r0, r1, r2 : std_logic_vector(4 downto 0);
signal r3 : std_logic_vector(5 downto 0);
signal r4 : std_logic_vector(1 downto 0);
begin
bitslip_int(0) <= bitslip;
rx_in_int(0) <= rx_in;
tx_in_int <= tx_in;
rx_out <= rx_out_int;
tx_out <= tx_out_int(0);
-- output clocks
rx_clk <= rx_clk_int;
rx_pll_clk <= rx_pll_clk_int;
tx_pll_clk <= tx_pll_clk_int;
-- output synchronized resets
rx_rstn <= rx_clk_rstn_int;
rx_pll_rstn <= rx_pll_rstn_int;
tx_pll_rstn <= tx_pll_rstn_int;
--rx_cda_reset_int(0) <= rx_cda_reset_int_0;
rx_rst_int(0) <= not rx_rstn_int_0;
rx_clk_int <= rx_divfwdclk_int(0);
-- reset synchronizers
rst0 : process (rx_clk_int, rst_125) begin
if rising_edge(rx_clk_int) then
r0 <= r0(3 downto 0) & rx_locked_int;
rx_clk_rstn_int <= r0(4) and r0(3) and r0(2);
end if;
if (rst_125 = '1') then r0 <= "00000"; rx_clk_rstn_int <= '0'; end if;
end process;
rst1 : process (rx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(rx_pll_clk_int) then
r1 <= r1(3 downto 0) & rx_locked_int;
rx_pll_rstn_int <= r1(4) and r1(3) and r1(2);
end if;
if (rx_clk_rstn_int = '0') then r1 <= "00000"; rx_pll_rstn_int <= '0'; end if;
end process;
rst2 : process (tx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(tx_pll_clk_int) then
r2 <= r2(3 downto 0) & tx_locked_int;
tx_pll_rstn_int <= r2(4) and r2(3) and r2(2);
end if;
if (rx_clk_rstn_int = '0') then r2 <= "00000"; tx_pll_rstn_int <= '0'; end if;
end process;
-- 6 stages reset synchronizer
rst3 : process (clk_125, rst_125) begin
if rising_edge(clk_125) then
r3 <= r3(4 downto 0) & rx_locked_int;
rx_rstn_int_0 <= r3(5) and r3(4) and r3(3);
end if;
if (rst_125 = '1') then r3 <= "000000"; rx_rstn_int_0 <= '0'; end if;
end process;
lvds_rx0: altlvds_rx
generic map (
buffer_implementation => "RAM",
cds_mode => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
data_align_rollover => 10,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
dpa_initial_phase_value => 0,
dpll_lock_count => 0,
dpll_lock_window => 0,
--enable_clock_pin_mode => "UNUSED",
enable_dpa_align_to_rising_edge_only => "OFF",
enable_dpa_calibration => "ON",
enable_dpa_fifo => "UNUSED",
enable_dpa_initial_phase_selection => "OFF",
enable_dpa_mode => "ON",
enable_dpa_pll_calibration => "OFF",
enable_soft_cdr_mode => "ON",
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
input_data_rate => 1250,
intended_device_family => "Stratix IV",
lose_lock_on_one_change => "UNUSED",
lpm_hint => "UNUSED",
lpm_type => "altlvds_rx",
number_of_channels => 1,
outclock_resource => "AUTO",
pll_operation_mode => "UNUSED",
pll_self_reset_on_loss_lock => "UNUSED",
port_rx_channel_data_align => "PORT_USED",
port_rx_data_align => "PORT_UNUSED",
--refclk_frequency => "125.000000 MHz",
registered_data_align_input => "UNUSED",
registered_output => "ON",
reset_fifo_at_first_lock => "UNUSED",
rx_align_data_reg => "UNUSED",
sim_dpa_is_negative_ppm_drift => "OFF",
sim_dpa_net_ppm_variation => 0,
sim_dpa_output_clock_phase_shift => 0,
use_coreclock_input => "OFF",
use_dpll_rawperror => "OFF",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
x_on_bitslip => "ON"
)
port map (
pll_areset => rst_125, --pll_areset_int,
rx_channel_data_align => bitslip_int,
rx_in => rx_in_int,
rx_inclock => clk_125,
rx_reset => rx_rst_int,
rx_divfwdclk => rx_divfwdclk_int,
rx_locked => rx_locked_int,
rx_out => rx_out_int,
rx_outclock => rx_pll_clk_int,
dpa_pll_cal_busy => open,
dpa_pll_recal => '0',
pll_phasecounterselect => open,
pll_phasedone => '1',
pll_phasestep => open,
pll_phaseupdown => open,
pll_scanclk => open,
rx_cda_max => open,
rx_cda_reset => (others => '0'),
rx_coreclk => (others => '1'),
rx_data_align => '0',
rx_data_align_reset => '0',
--rx_data_reset => '0',
rx_deskew => '0',
rx_dpa_lock_reset => (others => '0'),
rx_dpa_locked => open,
--rx_dpaclock => '0',
rx_dpll_enable => (others => '1'),
rx_dpll_hold => (others => '0'),
rx_dpll_reset => (others => '0'),
rx_enable => '1',
rx_fifo_reset => (others => '0'),
rx_pll_enable => '1',
rx_readclock => '0',
rx_syncclock => '0'
);
lvds_tx0: altlvds_tx
generic map (
center_align_msb => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
coreclock_divide_by => 1,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
differential_drive => 0,
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
intended_device_family => "Stratix IV",
lpm_hint => "UNUSED",
lpm_type => "altlvds_tx",
multi_clock => "OFF",
number_of_channels => 1,
outclock_alignment => "EDGE_ALIGNED",
outclock_divide_by => 10,
outclock_duty_cycle => 50,
outclock_multiply_by => 1,
outclock_phase_shift => 0,
outclock_resource => "AUTO",
output_data_rate => 1250,
pll_self_reset_on_loss_lock => "OFF",
preemphasis_setting => 0,
--refclk_frequency => "125.00 MHz",
registered_input => "TX_CORECLK",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
vod_setting => 0
)
port map (
pll_areset => rst_125, --pll_areset_int,
tx_in => tx_in_int,
tx_inclock => clk_125,
tx_out => tx_out_int,
tx_locked => tx_locked_int,
tx_coreclock => tx_pll_clk_int,
sync_inclock => '0',
--tx_data_reset => '0',
tx_enable => '1',
tx_outclock => open,
tx_pll_enable => '1',
tx_syncclock => '0'
);
end architecture ;
|
gpl-2.0
|
059d302b08dae48fa4631eaf42882966
| 0.566199 | 2.753556 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-asic/pads.vhd
| 1 | 26,677 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity pads is
generic (
padtech : integer := 0;
padlevel : integer := 0;
padvoltage : integer := 0;
padfilter : integer := 0;
padstrength : integer := 0;
padslew : integer := 0;
padclkarch : integer := 0;
padhf : integer := 0;
spw_input_type : integer := 0;
jtag_padfilter : integer := 0;
testen_padfilter : integer := 0;
resetn_padfilter : integer := 0;
clk_padfilter : integer := 0;
spw_padstrength : integer := 0;
jtag_padstrength : integer := 0;
uart_padstrength : integer := 0;
dsu_padstrength : integer := 0;
oepol : integer := 0
);
port (
----------------------------------------------------------------------------
--to chip boundary
----------------------------------------------------------------------------
resetn : in std_ulogic;
clksel : in std_logic_vector (1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0);
sdwen : out std_ulogic;
sdrasn : out std_ulogic;
sdcasn : out std_ulogic;
sddqm : out std_logic_vector (3 downto 0);
dsutx : out std_ulogic;
dsurx : in std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic;
rxd1 : in std_ulogic;
txd2 : out std_ulogic;
rxd2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : inout std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector (1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
---------------------------------------------------------------------------
--to core
---------------------------------------------------------------------------
lresetn : out std_ulogic;
lclksel : out std_logic_vector (1 downto 0);
lclk : out std_ulogic;
llock : in std_ulogic;
lerrorn : in std_ulogic;
laddress : in std_logic_vector(27 downto 0);
ldatain : out std_logic_vector(31 downto 0);
ldataout : in std_logic_vector(31 downto 0);
ldataen : in std_logic_vector(31 downto 0);
lcbin : out std_logic_vector(7 downto 0);
lcbout : in std_logic_vector(7 downto 0);
lcben : in std_logic_vector(7 downto 0);
lsdclk : in std_ulogic;
lsdcsn : in std_logic_vector (1 downto 0);
lsdwen : in std_ulogic;
lsdrasn : in std_ulogic;
lsdcasn : in std_ulogic;
lsddqm : in std_logic_vector (3 downto 0);
ldsutx : in std_ulogic;
ldsurx : out std_ulogic;
ldsuen : out std_ulogic;
ldsubre : out std_ulogic;
ldsuact : in std_ulogic;
ltxd1 : in std_ulogic;
lrxd1 : out std_ulogic;
ltxd2 : in std_ulogic;
lrxd2 : out std_ulogic;
lramsn : in std_logic_vector (4 downto 0);
lramoen : in std_logic_vector (4 downto 0);
lrwen : in std_logic_vector (3 downto 0);
loen : in std_ulogic;
lwriten : in std_ulogic;
lread : in std_ulogic;
liosn : in std_ulogic;
lromsn : in std_logic_vector (1 downto 0);
lbrdyn : out std_ulogic;
lbexcn : out std_ulogic;
lwdogn : in std_ulogic;
lgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
li2c_sclout : in std_ulogic;
li2c_sclen : in std_ulogic;
li2c_sclin : out std_ulogic;
li2c_sdaout : in std_ulogic;
li2c_sdaen : in std_ulogic;
li2c_sdain : out std_ulogic;
lspi_miso : out std_ulogic;
lspi_mosi : in std_ulogic;
lspi_sck : in std_ulogic;
lspi_slvsel : in std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
lprom32 : out std_ulogic;
lspw_clksel : out std_logic_vector (1 downto 0);
lspw_clk : out std_ulogic;
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
lgtx_clk : out std_ulogic;
lerx_clk : out std_ulogic;
lerxd : out std_logic_vector(7 downto 0);
lerx_dv : out std_ulogic;
letx_clk : out std_ulogic;
letxd : in std_logic_vector(7 downto 0);
letx_en : in std_ulogic;
letx_er : in std_ulogic;
lerx_er : out std_ulogic;
lerx_col : out std_ulogic;
lerx_crs : out std_ulogic;
lemdint : out std_ulogic;
lemdioin : out std_logic;
lemdioout : in std_logic;
lemdioen : in std_logic;
lemdc : in std_ulogic;
ltesten : out std_ulogic;
ltrst : out std_ulogic;
ltck : out std_ulogic;
ltms : out std_ulogic;
ltdi : out std_ulogic;
ltdo : in std_ulogic;
ltdoen : in std_ulogic
);
end;
architecture rtl of pads is
signal vcc,gnd : std_logic;
begin
vcc <= '1';
gnd <= '0';
------------------------------------------------------------------------------
-- Clocking and clock pads
------------------------------------------------------------------------------
reset_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => resetn_padfilter,
strength => padstrength)
port map (
pad => resetn,
o => lresetn);
clk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => clk,
o => lclk);
clksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => clksel,
o => lclksel);
spwclk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => spw_clk,
o => lspw_clk);
spwclksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => spw_clksel,
o => lspw_clksel);
------------------------------------------------------------------------------
-- Test / Misc pads
------------------------------------------------------------------------------
wdogn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => wdogn,
en => lwdogn,
i => gnd);
testen_pad : inpad
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => testen_padfilter,
strength => padstrength)
port map(
pad => testen,
o => ltesten);
lockpad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => lock,
i => llock);
errorn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => errorn,
en => lerrorn,
i => gnd);
------------------------------------------------------------------------------
-- JTAG pads
------------------------------------------------------------------------------
trst_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => trst,
o => ltrst);
tck_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tck,
o => ltck);
tms_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tms,
o => ltms);
tdi_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tdi,
o => ltdi);
tdo_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => jtag_padstrength)
port map (
pad => tdo,
i => ltdo);
------------------------------------------------------------------------------
-- DSU pads
------------------------------------------------------------------------------
dsuen_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsuen,
o => ldsuen);
dsubre_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsubre,
o => ldsubre);
dsuact_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsuact,
i => ldsuact);
dsurx_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsurx,
o => ldsurx);
dsutx_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsutx,
i => ldsutx);
------------------------------------------------------------------------------
-- UART pads
------------------------------------------------------------------------------
rxd1_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd1,
o => lrxd1);
txd1_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd1,
i => ltxd1);
rxd2_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd2,
o => lrxd2);
txd2_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd2,
i => ltxd2);
------------------------------------------------------------------------------
-- SPI pads
------------------------------------------------------------------------------
miso_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map(
pad => spi_miso,
o => lspi_miso);
mosi_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_mosi,
i => lspi_mosi);
sck_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_sck,
i => lspi_sck);
slvsel_pad : outpadv
generic map (
width => CFG_SPICTRL_SLVS,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => spi_slvsel,
i => lspi_slvsel);
------------------------------------------------------------------------------
-- I2C pads
------------------------------------------------------------------------------
scl_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_scl,
i => li2c_sclout,
en => li2c_sclen,
o => li2c_sclin);
sda_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_sda,
i => li2c_sdaout,
en => li2c_sdaen,
o => li2c_sdain);
------------------------------------------------------------------------------
-- Memory Interface pads
------------------------------------------------------------------------------
addr_pad : outpadv generic map (width => 28, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (address, laddress);
data_pad : iopadvv generic map (width => 32, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => data, i => ldataout, en => ldataen, o => ldatain);
rams_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramsn, lramsn);
roms_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (romsn, lromsn);
ramoen_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramoen, lramoen);
rwen_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (rwen, lrwen);
oen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (oen, loen);
wri_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (writen, lwriten);
read_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (read, lread);
iosn_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (iosn, liosn);
cb_pad : iopadvv generic map (width => 8, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => cb, i => lcbout, en => lcben, o => lcbin);
sdpads : if CFG_MCTRL_SDEN = 1 generate
sdclk_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdclk, lsdclk);
sdwen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdwen, lsdwen);
sdras_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdrasn, lsdrasn);
sdcas_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcasn, lsdcasn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sddqm, lsddqm);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcsn, lsdcsn);
end generate;
brdyn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => brdyn,
o => lbrdyn);
bexcn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => bexcn,
o => lbexcn);
prom32_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => prom32,
o => lprom32);
------------------------------------------------------------------------------
-- GPIO pads
------------------------------------------------------------------------------
gpio_pads : iopadvv
generic map (
width => CFG_GRGPIO_WIDTH,
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => gpio,
i => lgpioout,
en => lgpioen,
o => lgpioin);
------------------------------------------------------------------------------
-- SpW pads
------------------------------------------------------------------------------
spwpads0 : if CFG_SPW_EN > 0 generate
spwlvttl_pads : entity work.spw_lvttl_pads
generic map(
padtech => padtech,
strength => spw_padstrength,
input_type => spw_input_type,
voltage => padvoltage,
level => padlevel)
port map(
spw_rxd => spw_rxd,
spw_rxs => spw_rxs,
spw_txd => spw_txd,
spw_txs => spw_txs,
lspw_rxd => lspw_rxd,
lspw_rxs => lspw_rxs,
lspw_txd => lspw_txd,
lspw_txs => lspw_txs);
end generate;
nospwpads0 : if CFG_SPW_EN = 0 generate
spw_txd <= (others => '0');
spw_txs <= (others => '0');
lspw_rxd <= (others => '0');
lspw_rxs <= (others => '0');
end generate;
------------------------------------------------------------------------------
-- ETHERNET
------------------------------------------------------------------------------
greth1g: if CFG_GRETH1G = 1 generate
gtx_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => gtx_clk,
o => lgtx_clk);
end generate;
nogreth1g: if CFG_GRETH1G = 0 generate
lgtx_clk <= '0';
end generate;
ethpads : if (CFG_GRETH = 1) generate
etxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (etx_clk, letx_clk);
erxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (erx_clk, lerx_clk);
erxd_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 8)
port map (erxd, lerxd);
erxdv_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_dv, lerx_dv);
erxer_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_er, lerx_er);
erxco_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_col, lerx_col);
erxcr_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_crs, lerx_crs);
etxd_pad : outpadv
generic map(
width => 8,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (etxd, letxd);
etxen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_en, letx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_er, letx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdc, lemdc);
emdio_pad : iopad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdio, lemdioout, lemdioen, lemdioin);
emdint_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (emdint, lemdint);
end generate;
end;
|
gpl-2.0
|
aa7e6b633f02a49fb1f4bda05d155e55
| 0.480189 | 4.205739 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-sockit/axi2ahb.vhd
| 1 | 15,897 |
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: axi2ahb
-- File: axi2ahb.vhd
-- Author: Martin George
--
-- AXI/AHB bridge allowing Altera HPS to access LEON3 bus.
-- AHB master interface currently only supports OKAY response from slave.
-- AXI slave only supports incrementing bursts of length 1-16 transfers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
Entity axi2ahb is
generic(
hindex : integer := 0;
idsize : integer := 6;
lensize : integer := 4;
fifo_depth : integer := 16
);
port(
ahb_clk : in std_logic;
axi_clk : in std_logic;
resetn : in std_logic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
s_axi_araddr : in std_logic_vector ( 31 downto 0 );
s_axi_arburst : in std_logic_vector ( 1 downto 0 );
s_axi_arcache : in std_logic_vector ( 3 downto 0 );
s_axi_arid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_arlen : in std_logic_vector ( lensize-1 downto 0 );
s_axi_arlock : in std_logic_vector (1 downto 0);
s_axi_arprot : in std_logic_vector ( 2 downto 0 );
s_axi_arqos : in std_logic_vector ( 3 downto 0 );
s_axi_arready : out std_logic;
s_axi_arsize : in std_logic_vector ( 2 downto 0 );
s_axi_arvalid : in std_logic;
s_axi_awaddr : in std_logic_vector ( 31 downto 0 );
s_axi_awburst : in std_logic_vector ( 1 downto 0 );
s_axi_awcache : in std_logic_vector ( 3 downto 0 );
s_axi_awid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_awlen : in std_logic_vector ( lensize-1 downto 0 );
s_axi_awlock : in std_logic_vector (1 downto 0);
s_axi_awprot : in std_logic_vector ( 2 downto 0 );
s_axi_awqos : in std_logic_vector ( 3 downto 0 );
s_axi_awready : out std_logic;
s_axi_awsize : in std_logic_vector ( 2 downto 0 );
s_axi_awvalid : in std_logic;
s_axi_bid : out std_logic_vector ( idsize-1 downto 0 );
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector ( 1 downto 0 );
s_axi_bvalid : out std_logic;
s_axi_rdata : out std_logic_vector ( 31 downto 0 );
s_axi_rid : out std_logic_vector ( idsize-1 downto 0 );
s_axi_rlast : out std_logic;
s_axi_rready : in std_logic;
s_axi_rresp : out std_logic_vector ( 1 downto 0 );
s_axi_rvalid : out std_logic;
s_axi_wdata : in std_logic_vector ( 31 downto 0 );
s_axi_wid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_wlast : in std_logic;
s_axi_wready : out std_logic;
s_axi_wstrb : in std_logic_vector ( 3 downto 0 );
s_axi_wvalid : in std_logic
);
end;
architecture rtl of axi2ahb is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AXI2AHB, 0, 0, 0),
others => zero32);
type axi_w_state_type is (w_start, w_wait, w_data_fifo, w_ahb, w_done);
type axi_r_state_type is (r_start, r_wait, r_data_fifo, r_done);
type ahb_rw_state_type is (idle, w_req, w_first_addr, w_data_addr, w_done, r_req,
r_first_addr, r_data_addr, r_done);
type fifo is array (fifo_depth-1 downto 0) of std_logic_vector(31 downto 0);
type ahb_record is record
--States--
ahb_rw_state : ahb_rw_state_type;
--Outputs--
hwrite : std_logic;
hbusreq : std_logic;
hlock : std_logic;
hsize : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hwdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hwaddr : std_logic_vector(9 downto 0);
hraddr : std_logic_vector(9 downto 0);
hburst : std_logic_vector(2 downto 0);
inc_sel : std_logic_vector(2 downto 0);
--FIFO signals--
rfifo : fifo;
rfifo_w_ptr : integer range 0 to fifo_depth-1;
wfifo_r_ptr : integer range 0 to fifo_depth-1;
--Control signals--
ahb_haddr_stop : std_logic;
ahb_w_en_ack : std_logic;
ahb_r_done : std_logic;
ahb_w_done : std_logic;
addr_incr : integer range 0 to 15;
end record;
type axi_record is record
--States--
axi_w_state : axi_w_state_type;
axi_r_state : axi_r_state_type;
--Outputs--
arready : std_logic;
awready : std_logic;
bvalid : std_logic;
rdata : std_logic_vector ( 31 downto 0 );
rlast : std_logic;
rvalid : std_logic;
wready : std_logic;
--FIFO signals--
wfifo : fifo;
wfifo_w_ptr : integer range 0 to fifo_depth-1;
rfifo_r_ptr : integer range 0 to fifo_depth-1;
--Control signals--
--Write--
awaddr : std_logic_vector(31 downto 0);
awburst : std_logic_vector(1 downto 0);
awlen : std_logic_vector(lensize-1 downto 0);
awsize : std_logic_vector(2 downto 0);
awid : std_logic_vector(idsize-1 downto 0);
--Read--
arid : std_logic_vector(idsize-1 downto 0);
araddr : std_logic_vector(31 downto 0);
arburst : std_logic_vector(1 downto 0);
arlen : std_logic_vector(lensize-1 downto 0);
arsize : std_logic_vector(2 downto 0);
--AHB--
ahb_r_en : std_logic;
ahb_w_en : std_logic;
end record;
signal h, hin : ahb_record;
signal x, xin : axi_record;
begin
comb: process(resetn, ahbi, x, h, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arid, s_axi_arlen, s_axi_arlock,
s_axi_arprot, s_axi_arqos, s_axi_arsize, s_axi_arvalid,
s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awid,
s_axi_awlen, s_axi_awlock, s_axi_awprot, s_axi_awqos,
s_axi_awsize, s_axi_awvalid, s_axi_bready, s_axi_rready,
s_axi_wdata, s_axi_wid, s_axi_wlast, s_axi_wstrb, s_axi_wvalid)
variable vx : axi_record;
variable vh : ahb_record;
begin
vx := x;
vh := h;
-- AXI WRITE STATES
case x.axi_w_state is
when w_start =>
vx.awready := '1';
vx.wready := '0';
vx.ahb_w_en := '0';
vx.bvalid := '0';
if s_axi_awvalid = '1' then
vx.axi_w_state := w_wait;
vx.awready := '0';
vx.awlen := s_axi_awlen;
vx.awburst := s_axi_awburst;
vx.awsize := s_axi_awsize;
vx.awaddr := s_axi_awaddr;
vx.awid := s_axi_awid;
end if;
when w_wait =>
vx.awready := '0';
if h.ahb_w_done = '1' then
vx.wfifo_w_ptr := 0;
vx.axi_w_state := w_data_fifo;
end if;
when w_data_fifo =>
vx.awready := '0';
vx.wfifo_w_ptr := x.wfifo_w_ptr;
vx.wready := '0';
if s_axi_wvalid = '1' then
vx.wready := '1';
if s_axi_wlast = '1' then
vx.axi_w_state := w_ahb;
else
vx.wfifo_w_ptr := x.wfifo_w_ptr + 1;
end if;
end if;
when w_ahb =>
vx.wready := '0';
vx.ahb_w_en := '1';
if h.ahb_w_en_ack = '1' then
vx.ahb_w_en := '0';
vx.bvalid := '1';
vx.axi_w_state := w_done;
end if;
when w_done =>
if s_axi_bready = '1' then
vx.bvalid := '0';
vx.axi_w_state := w_start;
else
end if;
end case;
-- AXI READ STATES
case x.axi_r_state is
when r_start =>
vx.arready := '1';
vx.rvalid := '0';
vx.rfifo_r_ptr := 0;
vx.rlast := '0';
if s_axi_arvalid = '1' then
vx.arready := '0';
vx.ahb_r_en := '1';
vx.arlen := s_axi_arlen;
vx.arburst := s_axi_arburst;
vx.arsize := s_axi_arsize;
vx.araddr := s_axi_araddr;
vx.arid := s_axi_arid;
vx.axi_r_state := r_wait;
end if;
when r_wait =>
vx.arready := '0';
if h.ahb_r_done = '1' then
vx.ahb_r_en := '0';
vx.axi_r_state := r_data_fifo;
end if;
when r_data_fifo =>
vx.rdata := h.rfifo(x.rfifo_r_ptr);
vx.rvalid := '1';
vx.rfifo_r_ptr := x.rfifo_r_ptr;
-- if x.rfifo_r_ptr = conv_integer(x.arlen) then
if x.rfifo_r_ptr = h.rfifo_w_ptr then
vx.rlast := '1';
vx.axi_r_state := r_done;
elsif s_axi_rready = '1' then
vx.rfifo_r_ptr := x.rfifo_r_ptr + 1;
end if;
when r_done =>
vx.rvalid := '1';
if s_axi_rready = '1' then
vx.rvalid := '0';
vx.rfifo_r_ptr := 0;
vx.rlast := '0';
vx.axi_r_state := r_start;
else
end if;
end case;
-- AHB READ/WRITE STATES
case h.ahb_rw_state is
when idle =>
vh.ahb_w_en_ack := '0';
vh.ahb_r_done := '0';
vh.htrans := "00";
if x.ahb_w_en = '1' then
vh.ahb_w_done := '0';
vh.ahb_rw_state := w_req;
vh.hsize := x.awsize;
vh.inc_sel := x.awsize;
elsif x.ahb_r_en = '1' then
vh.ahb_r_done := '0';
vh.ahb_rw_state := r_req;
vh.hsize := "010";
vh.inc_sel := x.arsize;
else
end if;
-- WRITE STATES
when w_req =>
vh.ahb_w_en_ack := '1';
vh.hbusreq := '1';
vh.hlock := '1';
vh.hwrite := '1';
if conv_integer(x.awlen) /= 0 then
vh.hburst := "001";
else
vh.hburst := "000";
end if;
if (ahbi.hgrant(hindex) and ahbi.hready) = '1' then
vh.ahb_rw_state := w_first_addr;
else
end if;
when w_first_addr =>
vh.htrans := "10";
vh.hwaddr := x.awaddr(9 downto 0);
vh.haddr := x.awaddr;
case h.hsize is
when "000" =>
vh.haddr(1 downto 0) := not x.awaddr(1 downto 0);
when "001" =>
vh.haddr(1) := not x.awaddr(1);
when others =>
end case;
vh.ahb_rw_state := w_data_addr;
when w_data_addr =>
vh.htrans := "11";
vh.hwdata := x.wfifo(h.wfifo_r_ptr);
if h.wfifo_r_ptr = x.wfifo_w_ptr then
vh.htrans := "00";
vh.ahb_rw_state := w_done;
elsif ahbi.hready = '1' then
vh.hwaddr := h.hwaddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hwaddr;
case h.hsize is
when "000" =>
vh.haddr(1 downto 0) := not vh.hwaddr(1 downto 0);
when "001" =>
vh.haddr(1) := not vh.hwaddr(1);
when others =>
end case;
vh.wfifo_r_ptr := h.wfifo_r_ptr + 1;
end if;
when w_done =>
if ahbi.hready = '1' then
vh.ahb_haddr_stop := '0';
vh.htrans := "00";
vh.wfifo_r_ptr := 0;
vh.ahb_w_en_ack := '0';
vh.ahb_w_done := '1';
vh.hbusreq := '0';
vh.hlock := '0';
vh.ahb_rw_state := idle;
else
end if;
-- READ STATES
when r_req =>
vh.rfifo_w_ptr := 0;
vh.hbusreq := '1';
vh.hlock := '1';
vh.hwrite := '0';
if conv_integer(x.arlen) /= 0 then
vh.hburst := "001";
else
vh.hburst := "000";
end if;
if (ahbi.hgrant(hindex) and ahbi.hready) = '1' then
vh.ahb_rw_state := r_first_addr;
vh.htrans := "10";
vh.haddr := x.araddr;
vh.hraddr := x.araddr(9 downto 0);
else
end if;
when r_first_addr =>
if ahbi.hready = '1' then
if h.rfifo_w_ptr /= conv_integer(x.arlen) then
vh.hraddr := h.hraddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hraddr(9 downto 2) & "00";
end if;
vh.ahb_rw_state := r_data_addr;
end if;
when r_data_addr =>
if ahbi.hready = '1' then
vh.rfifo(h.rfifo_w_ptr) := ahbi.hrdata;
if h.rfifo_w_ptr = conv_integer(x.arlen) then
vh.htrans := "00";
vh.ahb_rw_state := r_done;
else
vh.htrans := "11";
vh.rfifo_w_ptr := h.rfifo_w_ptr + 1;
vh.hraddr := h.hraddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hraddr(9 downto 2) & "00";
end if;
else
end if;
when r_done =>
vh.htrans := "00";
vh.ahb_r_done := '1';
vh.hbusreq := '0';
vh.hlock := '0';
vx.ahb_r_en := '0';
vh.ahb_rw_state := idle;
end case;
-- WDATA muxing
if (s_axi_wvalid and h.ahb_w_done) = '1' then
case s_axi_wstrb is
when "0001" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0);
when "0010" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8);
when "0100" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16);
when "1000" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24);
when "0011" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(15 downto 0)
& s_axi_wdata(15 downto 0);
when "1100" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(31 downto 16)
& s_axi_wdata(31 downto 16);
when "1111" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata;
when others =>
end case;
end if;
-- HADDR increment
case h.inc_sel is
when "000" =>
vh.addr_incr := 1;
when "001" =>
vh.addr_incr := 2;
when others =>
vh.addr_incr := 4;
end case;
if resetn = '0' then
vx.axi_w_state := w_start;
vx.axi_r_state := r_start;
vh.ahb_rw_state := idle;
vh.rfifo := (others => (others => '0'));
vx.wfifo := (others => (others => '0'));
vh.hbusreq := '0';
vh.hlock := '0';
vh.hwdata := (others => '0');
vh.haddr := (others => '0');
vx.awlen := (others => '0');
vx.awburst := (others => '0');
vx.awsize := (others => '0');
vx.awaddr := (others => '0');
vx.awid := (others => '0');
vx.wready := '0';
vx.arready := '0';
vx.awready := '0';
vx.rdata := (others => '0');
vx.araddr := (others => '0');
vx.arburst := (others => '0');
vx.arlen := (others => '0');
vx.arid := (others => '0');
vx.bvalid := '0';
vx.rlast := '0';
vx.rvalid := '0';
vx.wready := '0';
vh.ahb_r_done := '0';
vx.ahb_r_en := '0';
vx.ahb_w_en := '0';
vh.hwrite := '0';
vh.hsize := (others => '0');
vh.ahb_w_done := '1';
vx.arsize := (others => '0');
vh.hburst := (others => '0');
end if;
xin <= vx;
hin <= vh;
end process;
ahbo.hconfig <= hconfig;
ahbo.hindex <= hindex;
ahbo.hirq <= (others => '0');
ahbo.haddr <= h.haddr;
ahbo.htrans <= h.htrans;
ahbo.hprot <= "0011";
ahbo.hburst <= h.hburst;
ahbo.hbusreq <= h.hbusreq;
ahbo.hwrite <= h.hwrite;
ahbo.hwdata <= h.hwdata;
ahbo.hlock <= h.hlock;
ahbo.hsize <= h.hsize;
s_axi_bid <= x.awid;
s_axi_rid <= x.arid;
s_axi_arready <= x.arready;
s_axi_awready <= x.awready;
s_axi_bresp <= "00";
s_axi_bvalid <= x.bvalid;
s_axi_rdata <= x.rdata;
s_axi_rlast <= x.rlast;
s_axi_rresp <= "00";
s_axi_rvalid <= x.rvalid;
s_axi_wready <= x.wready;
--AXI synchronous--
axi_sync: process(axi_clk)
begin
if rising_edge(axi_clk) then
x <= xin;
end if;
end process;
--AHB synchronous--
ahb_sync: process(ahb_clk)
begin
if rising_edge(ahb_clk) then
h <= hin;
end if;
end process;
end;
|
gpl-2.0
|
df956366333ab162b226c9d64f242f78
| 0.543373 | 2.581101 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/esa/memoryctrl/mctrl.vhd
| 4 | 36,435 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rrsbdrive, rsbdrive, risbdrive : std_logic_vector(63 downto 0);
signal arst : std_ulogic;
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
attribute syn_preserve of rrsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
arst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else rst;
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive,
rsbdrive, rrsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
variable haddrsel : std_logic_vector(31 downto 13);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
haddrsel := (others => '0');
haddrsel(sdrasel downto 13) := haddr(sdrasel downto 13);
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddrsel(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddrsel(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbreadword(ahbsi.hwdata, r.address(4 downto 2));
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if r.address(1) = '1' then
writedata(31 downto 16) := writedata(15 downto 0);
end if;
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if (r.address(1) = '0') or (r.brmw = '1') then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 16) := sdmo.prdata(31 downto 16);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when "11" =>
if SDRAMEN then
regsd(31 downto 0) := sdmo.prdata(31 downto 0);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- scan support
if (syncrst = 1) and (rst = '0') then
memo.ramsn <= (others => '1');
memo.ramoen <= (others => '1');
memo.romsn <= (others => '1');
memo.iosn <= '1';
memo.oen <= '1';
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
if oepol = 0 then
memo.bdrive <= (others => '1');
memo.vbdrive <= (others => '1');
memo.svbdrive <= (others => '1');
else
memo.bdrive <= (others => '0');
memo.vbdrive <= (others => '0');
memo.svbdrive <= (others => '0');
end if;
end if;
else
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.iosn <= r.iosn(0);
memo.oen <= r.oen;
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
memo.bdrive <= bdrive;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rrsbdrive;
end if;
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.address;
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.svcdrive <= (others => '0');
memo.vcdrive <= (others => '0');
memo.scb <= (others => '0');
memo.cb <= (others => '0');
memo.romn <= r.romsn(0);
memo.ramn <= r.ramsn(0);
memo.sdram_en <= r.mcfg2.sdren; -- Unused
memo.rs_edac_en <= '0';
memo.ce <= '0';
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
sdi.edac <= '0';
sdi.brmw <= '0';
sdi.error <= '0';
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk, arst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (arst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst, mobile)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, arst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
if (syncrst = 0) and (arst = '0') then
if oepol = 0 then rrsbdrive <= (others => '1');
else rrsbdrive <= (others => '0'); end if;
end if;
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
memo.sddata <= (others => '0');
memo.sa <= (others => '0');
end generate;
end;
|
gpl-2.0
|
ec5b8231c3a7b4d61b2f823716c9570d
| 0.539234 | 3.22805 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/config.vhd
| 2 | 5,256 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := zynq7000;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (32);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
d52304f46ce82299c3572420559f4b86
| 0.640601 | 3.660167 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml403/leon3mp.vhd
| 1 | 26,058 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
sys_clk : in std_ulogic; -- 100 MHz main clock
--pragma translate_off
plb_error : out std_logic; -- ERRORn
--pragma translate_on
opb_error : out std_logic; -- DSU active
sram_flash_addr : out std_logic_vector(20 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_flash_oe_n : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
gpio : inout std_logic_vector(13 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
tft_lcd_clk : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 3);
vid_g : out std_logic_vector(7 downto 3);
vid_b : out std_logic_vector(7 downto 3);
usb_csn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDRSP;
signal stati : ahbstat_in_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
signal romsn : std_ulogic;
constant SPW_LOOP_BACK : integer := 0;
begin
usb_csn <= '1';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (sys_clk, lclk);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
g1clk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
egtx_clk_pad : outpad generic map (tech => padtech)
port map (phy_gtx_clk, egtx_clk);
clklock <= lock and cgo2.clklock;
end generate;
nog1clk : if CFG_GRETH1G = 0 generate
clklock <= lock;
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
--pragma translate_off
errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
--pragma translate_on
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(13) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(13) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
memi.brdyn <= '1'; memi.bexcn <= '1';
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#C00#, rammask => 16#FF0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
romsn <= not memo.romsn(0);
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
addr_pad : outpadv generic map (width => 21, tech => padtech)
port map (sram_flash_addr, memo.address(22 downto 2));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, romsn);
oen_pad : outpad generic map (tech => padtech)
port map (sram_flash_oe_n, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_bw, memo.wrn);
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32,
phyiconf => 1)
port map (
rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(13) = '0' else '1';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
dac_clk <= not clkvga;
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_r(7 downto 3), vgao.video_out_r(7 downto 3));
video_out_g_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_g(7 downto 3), vgao.video_out_g(7 downto 3));
video_out_b_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_b(7 downto 3), vgao.video_out_b(7 downto 3));
video_clock_pad : outpad generic map ( tech => padtech)
port map (tft_lcd_clk, dac_clk);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 14)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 14)
port map (gpio, gpioo.dout(13 downto 0), gpioo.oen(13 downto 0),
gpioi.din(13 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
3fa860b77560e9a8fef6b9b510e45f5f
| 0.573643 | 3.433654 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spimctrl.vhd
| 1 | 39,265 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spimctrl
-- File: spimctrl.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: SPI flash memory controller. Supports a wide range of SPI
-- memory devices with the data read instruction configurable via
-- generics. Also has limited support for initializing and reading
-- SD Cards in SPI mode.
--
-- The controller has two memory areas. The flash area where the flash memory
-- is directly mapped and the I/O area where core registers are mapped.
--
-- Revision 1 added support for burst reads when sdcard = 0
--
-- Post revision 1: Remove support for SD card by commenting out code
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spimctrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
faddr : integer := 16#000#; -- Flash map base address
fmask : integer := 16#fff#; -- Flash area mask
ioaddr : integer := 16#000#; -- I/O base address
iomask : integer := 16#fff#; -- I/O mask
spliten : integer := 0; -- AMBA SPLIT support
oepol : integer := 0; -- Output enable polarity
sdcard : integer range 0 to 0 := 0; -- Unused
readcmd : integer range 0 to 255 := 16#0B#; -- Mem. dev. READ command
dummybyte : integer range 0 to 1 := 1; -- Dummy byte after cmd
dualoutput : integer range 0 to 1 := 0; -- Enable dual output
scaler : integer range 1 to 512 := 1; -- SCK scaler
altscaler : integer range 1 to 512 := 1; -- Alternate SCK scaler
pwrupcnt : integer := 0; -- System clock cycles to init
maxahbaccsz : integer range 0 to 256 := AHBDW; -- Max AHB access size
offset : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
spii : in spimctrl_in_type;
spio : out spimctrl_out_type
);
end spimctrl;
architecture rtl of spimctrl is
constant REVISION : amba_version_type := 1;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPIMCTRL, 0, REVISION, hirq),
4 => ahb_iobar(ioaddr, iomask),
5 => ahb_membar(faddr, '1', '1', fmask),
others => zero32);
-- BANKs
constant CTRL_BANK : integer := 0;
constant FLASH_BANK : integer := 1;
constant MAXDW : integer := maxahbaccsz;
-----------------------------------------------------------------------------
-- SD card constants
-----------------------------------------------------------------------------
-- constant SD_BLEN : integer := 4;
-- constant SD_CRC_BYTE : std_logic_vector(7 downto 0) := X"95";
-- constant SD_BLOCKLEN : std_logic_vector(31 downto 0) :=
-- conv_std_logic_vector(SD_BLEN, 32);
-- -- Commands
-- constant SD_CMD0 : std_logic_vector(5 downto 0) := "000000";
-- constant SD_CMD16 : std_logic_vector(5 downto 0) := "010000";
-- constant SD_CMD17 : std_logic_vector(5 downto 0) := "010001";
-- constant SD_CMD55 : std_logic_vector(5 downto 0) := "110111";
-- constant SD_ACMD41 : std_logic_vector(5 downto 0) := "101001";
-- -- Command timeout
-- constant SD_CMD_TIMEOUT : integer := 100;
-- -- Data token timeout
-- constant SD_DATATOK_TIMEOUT : integer := 312500;
-----------------------------------------------------------------------------
-- SPI device constants
-----------------------------------------------------------------------------
-- Length of read instruction argument-1
constant SPI_ARG_LEN : integer := 2 + dummybyte;
-----------------------------------------------------------------------------
-- Core constants
-----------------------------------------------------------------------------
-- OEN
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1); -- Enable outputs
constant INPUT : std_ulogic := not OUTPUT; -- Tri-state outputs
-- Register offsets
constant CONF_REG_OFF : std_logic_vector(7 downto 2) := "000000";
constant CTRL_REG_OFF : std_logic_vector(7 downto 2) := "000001";
constant STAT_REG_OFF : std_logic_vector(7 downto 2) := "000010";
constant RX_REG_OFF : std_logic_vector(7 downto 2) := "000011";
constant TX_REG_OFF : std_logic_vector(7 downto 2) := "000100";
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- Description: Determines required size of timer used for clock scaling
function timer_size
return integer is
begin -- timer_size
if altscaler > scaler then
return altscaler;
end if;
return scaler;
end timer_size;
-- Description: Returns the number of bits required for the haddr vector to
-- be able to save the Flash area address.
function req_addr_bits
return integer is
begin -- req_addr_bits
case fmask is
when 16#fff# => return 20;
when 16#ffe# => return 21;
when 16#ffc# => return 22;
when 16#ff8# => return 23;
when 16#ff0# => return 24;
when 16#fe0# => return 25;
when 16#fc0# => return 26;
when 16#f80# => return 27;
when 16#f00# => return 28;
when 16#e00# => return 29;
when 16#c00# => return 30;
when others => return 31;
end case;
end req_addr_bits;
-- Description: Returns true if SCK clock should transition
function sck_toggle (
curr : std_logic_vector((timer_size-1) downto 0);
last : std_logic_vector((timer_size-1) downto 0);
usealtscaler : boolean)
return boolean is
begin -- sck_toggle
if usealtscaler then
return (curr(altscaler-1) xor last(altscaler-1)) = '1';
end if;
return (curr(scaler-1) xor last(scaler-1)) = '1';
end sck_toggle;
-- Description: Short for conv_std_logic_vector, avoiding an alias
function cslv (
i : integer;
w : integer)
return std_logic_vector is
begin -- cslv
return conv_std_logic_vector(i,w);
end cslv;
-- Description: Calculates value for spi.cnt based on AMBA HSIZE
function calc_spi_cnt (
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable cnt : std_logic_vector(4 downto 0) := (others => '0');
begin -- calc_spi_cnt
for i in 0 to 4 loop
if i < conv_integer(hsize) then
cnt(i) := '1';
end if;
end loop; -- i
return cnt;
end calc_spi_cnt;
-----------------------------------------------------------------------------
-- States
-----------------------------------------------------------------------------
-- Main FSM states
type spimstate_type is (IDLE, AHB_RESPOND, USER_SPI, BUSY);
-- SPI device FSM states
type spistate_type is (SPI_PWRUP, SPI_READY, SPI_READ, SPI_ADDR, SPI_DATA);
-- SD FSM states
type sdstate_type is (SD_CHECK_PRES, SD_PWRUP0, SD_PWRUP1, SD_INIT_IDLE,
SD_ISS_ACMD41, SD_CHECK_CMD16, SD_READY,
SD_CHECK_CMD17, SD_CHECK_TOKEN, SD_HANDLE_DATA,
SD_SEND_CMD, SD_GET_RESP);
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spim_ctrl_reg_type is record -- Control register
eas : std_ulogic; -- Enable alternate scaler
ien : std_ulogic; -- Interrupt enable
usrc : std_ulogic; -- User mode
end record;
type spim_stat_reg_type is record -- Status register
busy : std_ulogic; -- Core busy
done : std_ulogic; -- User operation done
end record;
type spim_regif_type is record -- Register bank
ctrl : spim_ctrl_reg_type; -- Control register
stat : spim_stat_reg_type; -- Status register
end record;
-- type sdcard_type is record -- Present when SD card
-- state : sdstate_type; -- SD state
-- tcnt : std_logic_vector(2 downto 0); -- Transmit count
-- rcnt : std_logic_vector(3 downto 0); -- Receive count
-- cmd : std_logic_vector(5 downto 0); -- SD command
-- rstate : sdstate_type; -- Return state
-- htb : std_ulogic; -- Handle trailing byte
-- vresp : std_ulogic; -- Valid response
-- cd : std_ulogic; -- Synchronized card detect
-- timeout : std_ulogic; -- Timeout status bit
-- dtocnt : std_logic_vector(18 downto 0); -- Data token timeout counter
-- ctocnt : std_logic_vector(6 downto 0); -- CMD resp. timeout counter
-- end record;
type spiflash_type is record -- Present when !SD card
state : spistate_type; -- Mem. device comm. state
cnt : std_logic_vector(4 downto 0); -- Generic counter
hsize : std_logic_vector(2 downto 0); -- Size of access
hburst : std_logic_vector(0 downto 0); -- Incremental burst
end record;
type spimctrl_in_array is array (1 downto 0) of spimctrl_in_type;
type spim_reg_type is record
-- Common
spimstate : spimstate_type; -- Main FSM
rst : std_ulogic; -- Reset
reg : spim_regif_type; -- Register bank
timer : std_logic_vector((timer_size-1) downto 0);
sample : std_logic_vector(1 downto 0); -- Sample data line
bd : std_ulogic;
sreg : std_logic_vector(7 downto 0); -- Shiftreg
bcnt : std_logic_vector(2 downto 0); -- Bit counter
go : std_ulogic; -- SPI comm. active
stop : std_ulogic; -- Stop SPI comm.
ar : std_logic_vector(MAXDW-1 downto 0); -- argument/response
hold : std_ulogic; -- Do not shift ar
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
-- SPI flash device
spi : spiflash_type; -- Used when !SD card
-- SD
-- sd : sdcard_type; -- Used when SD card
-- AHB
irq : std_ulogic; -- Interrupt request
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector((req_addr_bits-1) downto 0);
hready : std_ulogic;
frdata : std_logic_vector(MAXDW-1 downto 0); -- Flash response data
rrdata : std_logic_vector(7 downto 0); -- Register response data
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
hburst : std_logic_vector(0 downto 0);
seq : std_ulogic; -- Sequential burst
-- Inputs and outputs
spii : spimctrl_in_array;
spio : spimctrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spim_reg_type;
begin -- rtl
comb: process (r, rstn, ahbsi, spii)
variable v : spim_reg_type;
variable change : std_ulogic;
variable regaddr : std_logic_vector(7 downto 2);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable ahbirq : std_logic_vector((NAHBIRQ-1) downto 0);
variable lastbit : std_ulogic;
variable enable_altscaler : boolean;
variable disable_flash : boolean;
variable read_flash : boolean;
variable hrdata : std_logic_vector(MAXDW-1 downto 0);
variable hwdatax : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(7 downto 0);
begin -- process comb
v := r; v.spii := r.spii(0) & spii; v.sample := r.sample(0) & '0';
change := '0'; v.irq := '0'; v.hresp := HRESP_OKAY; v.hready := '1';
regaddr := r.haddr(7 downto 2); hsplit := (others => '0');
hwdatax := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
hwdata := hwdatax(7 downto 0);
ahbirq := (others => '0'); ahbirq(hirq) := r.irq;
-- if sdcard = 1 then v.sd.cd := r.spii(0).cd; else v.sd.cd := '0'; end if;
read_flash := false;
enable_altscaler := (not r.spio.initialized or r.reg.ctrl.eas) = '1';
-- disable_flash := (r.spio.errorn = '0' or r.reg.ctrl.usrc = '1' or
disable_flash := (r.reg.ctrl.usrc = '1' or
r.spio.initialized = '0' or r.spimstate = USER_SPI);
if dualoutput = 1 and sdcard = 0 then
lastbit := andv(r.bcnt(1 downto 0)) and
((r.spio.mosioen xnor INPUT) or r.bcnt(2));
else
lastbit := andv(r.bcnt);
end if;
v.bd := lastbit and r.sample(0);
---------------------------------------------------------------------------
-- AHB communication
---------------------------------------------------------------------------
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if (spliten = 0 or r.spimstate /= AHB_RESPOND or
ahbsi.hmbsel(CTRL_BANK) = '1' or ahbsi.hmastlock = '1') then
-- Writes to register space have no wait state
v.hready := ahbsi.hmbsel(CTRL_BANK) and ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(r.haddr'range);
v.hsel := '1';
if ahbsi.hmbsel(FLASH_BANK) = '1' then
if sdcard = 0 then
v.hburst(r.hburst'range) := ahbsi.hburst(r.hburst'range);
v.seq := ahbsi.htrans(0);
end if;
if ahbsi.hwrite = '1' or disable_flash then
v.hresp := HRESP_ERROR;
v.hsel := '0';
else
if spliten /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
end if;
end if;
else
-- Core is busy, transfer is not locked and access was to flash
-- area. Respond with SPLIT or insert wait states
v.hready := '0';
if spliten /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
-- Read access to core registers
if (r.hsel and r.hmbsel(CTRL_BANK) and not r.hwrite) = '1' then
v.rrdata := (others => '0');
v.hready := '1';
v.hsel := '0';
case regaddr is
when CONF_REG_OFF =>
-- if sdcard = 1 then
-- v.rrdata := (others => '0');
-- else
v.rrdata := cslv(readcmd, 8);
-- end if;
when CTRL_REG_OFF =>
v.rrdata(3) := r.spio.csn;
v.rrdata(2) := r.reg.ctrl.eas;
v.rrdata(1) := r.reg.ctrl.ien;
v.rrdata(0) := r.reg.ctrl.usrc;
when STAT_REG_OFF =>
-- v.rrdata(5) := r.sd.cd;
-- v.rrdata(4) := r.sd.timeout;
-- v.rrdata(3) := not r.spio.errorn;
v.rrdata(2) := r.spio.initialized;
v.rrdata(1) := r.reg.stat.busy;
v.rrdata(0) := r.reg.stat.done;
when RX_REG_OFF => v.rrdata := r.ar(7 downto 0);
when others => null;
end case;
end if;
-- Write access to core registers
if (r.hsel and r.hmbsel(CTRL_BANK) and r.hwrite) = '1' then
case regaddr is
when CTRL_REG_OFF =>
v.rst := hwdata(4);
if (r.reg.ctrl.usrc and not hwdata(0)) = '1' then
v.spio.csn := '1';
elsif hwdata(0) = '1' then
v.spio.csn := hwdata(3);
end if;
v.reg.ctrl.eas := hwdata(2);
v.reg.ctrl.ien := hwdata(1);
v.reg.ctrl.usrc := hwdata(0);
when STAT_REG_OFF =>
-- v.spio.errorn := r.spio.errorn or hwdata(3);
v.reg.stat.done := r.reg.stat.done and not hwdata(0);
when RX_REG_OFF => null;
when TX_REG_OFF =>
if r.reg.ctrl.usrc = '1' then
v.sreg := hwdata(7 downto 0);
end if;
when others => null;
end case;
end if;
---------------------------------------------------------------------------
-- SPIMCTRL control FSM
---------------------------------------------------------------------------
v.reg.stat.busy := '1';
case r.spimstate is
when BUSY =>
-- Wait for core to finish user mode access
if (r.go or r.spio.sck) = '0' then
v.spimstate := IDLE;
v.reg.stat.done:= '1';
v.irq := r.reg.ctrl.ien;
end if;
when AHB_RESPOND =>
if r.spio.ready = '1' then
if spliten /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((spliten = 0 or v.ahbcancel = '0') and
(spliten = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((spliten = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.spimstate := IDLE;
v.hresp := HRESP_OKAY;
if spliten /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
-- if r.spio.errorn = '0' then
-- v.hready := '0';
-- v.hresp := HRESP_ERROR;
-- end if;
elsif spliten /= 0 and v.ahbcancel = '1' then
v.spimstate := IDLE;
v.ahbcancel := '0';
end if;
end if;
when USER_SPI =>
if r.bd = '1' then
v.spimstate := BUSY;
v.hold := '1';
end if;
when others => -- IDLE
if spliten /= 0 and r.hresp /= HRESP_SPLIT then
hsplit := r.hsplit;
v.hsplit := (others => '0');
end if;
v.reg.stat.busy := '0';
if r.hsel = '1' then
if r.hmbsel(FLASH_BANK) = '1' then
-- Access to memory mapped flash area
v.spimstate := AHB_RESPOND;
read_flash := true;
elsif regaddr = TX_REG_OFF and (r.hwrite and r.reg.ctrl.usrc) = '1' then
-- Access to core transmit register
v.spimstate := USER_SPI;
v.go := '1';
v.stop := '1';
change := '1';
v.hold := '0';
if sdcard = 0 and dualoutput = 1 then
v.spio.mosioen := OUTPUT;
end if;
end if;
end if;
end case;
---------------------------------------------------------------------------
-- SD Card specific code
---------------------------------------------------------------------------
-- SD card initialization sequence:
-- * Check if card is present
-- * Perform power-up initialization sequence
-- * Issue CMD0 GO_IDLE_STATE
-- * Issue CMD55 APP_CMD
-- * Issue ACMD41 SEND_OP_COND
-- * Issue CMD16 SET_BLOCKLEN
-- if sdcard = 1 then
-- case r.sd.state is
-- when SD_PWRUP0 =>
-- v.go := '1';
-- v.sd.vresp := '1';
-- v.sd.state := SD_GET_RESP;
-- v.sd.rstate := SD_PWRUP1;
-- v.sd.rcnt := cslv(2, r.sd.rcnt'length);
-- when SD_PWRUP1 =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.rstate := SD_INIT_IDLE;
-- v.sd.cmd := SD_CMD0;
-- v.sd.rcnt := (others => '0');
-- v.ar := (others => '0');
-- when SD_INIT_IDLE =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.rcnt := (others => '0');
-- if r.ar(0) = '0' and r.sd.cmd /= SD_CMD0 then
-- v.sd.cmd := SD_CMD16;
-- v.ar := SD_BLOCKLEN;
-- v.sd.rstate := SD_CHECK_CMD16;
-- else
-- v.sd.cmd := SD_CMD55;
-- v.ar := (others => '0');
-- v.sd.rstate := SD_ISS_ACMD41;
-- end if;
-- when SD_ISS_ACMD41 =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.cmd := SD_ACMD41;
-- v.sd.rcnt := (others => '0');
-- v.ar := (others => '0');
-- v.sd.rstate := SD_INIT_IDLE;
-- when SD_CHECK_CMD16 =>
-- if r.ar(7 downto 0) /= zero32(7 downto 0) then
-- v.spio.errorn := '0';
-- else
-- v.spio.errorn := '1';
-- v.spio.initialized := '1';
-- v.sd.timeout := '0';
-- end if;
-- v.sd.state := SD_READY;
-- when SD_READY =>
-- v.spio.ready := '1';
-- v.sd.cmd := SD_CMD17;
-- v.sd.rstate := SD_CHECK_CMD17;
-- if read_flash then
-- v.sd.state := SD_SEND_CMD;
-- v.spio.ready := '0';
-- v.ar := (others => '0');
-- v.ar(r.haddr'left downto 2) := r.haddr(r.haddr'left downto 2);
-- end if;
-- when SD_CHECK_CMD17 =>
-- if r.ar(7 downto 0) /= X"00" then
-- v.sd.state := SD_READY;
-- v.spio.errorn := '0';
-- else
-- v.sd.rstate := SD_CHECK_TOKEN;
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- end if;
-- v.sd.dtocnt := cslv(SD_DATATOK_TIMEOUT, r.sd.dtocnt'length);
-- v.sd.state := SD_GET_RESP;
-- v.sd.vresp := '1';
-- v.hold := '0';
-- when SD_CHECK_TOKEN =>
-- if (r.ar(7 downto 5) = "111" and
-- r.sd.dtocnt /= zero32(r.sd.dtocnt'range)) then
-- v.sd.dtocnt := r.sd.dtocnt - 1;
-- v.sd.state := SD_GET_RESP;
-- if r.ar(0) = '0' then
-- v.sd.rstate := SD_HANDLE_DATA;
-- v.sd.rcnt := cslv(SD_BLEN-1, r.sd.rcnt'length);
-- end if;
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- else
-- v.spio.errorn := '0';
-- v.sd.state := SD_READY;
-- end if;
-- v.sd.timeout := not orv(r.sd.dtocnt);
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- v.hold := '0';
-- when SD_HANDLE_DATA =>
-- v.frdata := r.ar;
-- -- Receive and discard CRC
-- v.sd.state := SD_GET_RESP;
-- v.sd.rstate := SD_READY;
-- v.sd.htb := '1';
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- v.sd.vresp := '1';
-- v.spio.errorn := '1';
-- when SD_SEND_CMD =>
-- v.sd.htb := '1';
-- v.sd.vresp := '0';
-- v.spio.csn := '0';
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- if (v.bd or not r.go) = '1'then
-- v.hold := '0';
-- case r.sd.tcnt is
-- when "000" => v.sreg := "01" & r.sd.cmd;
-- v.hold := '1'; change := '1';
-- when "001" => v.sreg := r.ar(31 downto 24);
-- when "010" => v.sreg := r.ar(30 downto 23);
-- when "011" => v.sreg := r.ar(30 downto 23);
-- when "100" => v.sreg := r.ar(30 downto 23);
-- when "101" => v.sreg := SD_CRC_BYTE;
-- when others => v.sd.state := SD_GET_RESP;
-- end case;
-- v.go := '1';
-- v.sd.tcnt := r.sd.tcnt + 1;
-- end if;
-- when SD_GET_RESP =>
-- if v.bd = '1' then
-- if r.sd.vresp = '1' or r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- if r.sd.rcnt = zero32(r.sd.rcnt'range) then
-- if r.sd.htb = '0' then
-- v.spio.csn := '1';
-- end if;
-- v.sd.htb := '0';
-- v.hold := '1';
-- else
-- v.sd.rcnt := r.sd.rcnt - 1;
-- end if;
-- else
-- v.sd.ctocnt := r.sd.ctocnt - 1;
-- end if;
-- end if;
-- if lastbit = '1' then
-- v.sd.vresp := r.sd.vresp or not r.ar(6);
-- if r.sd.rcnt = zero32(r.sd.rcnt'range) then
-- v.stop := r.sd.vresp and r.go and not r.sd.htb;
-- end if;
-- end if;
-- if r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- v.stop := r.go;
-- end if;
-- if (r.go or r.spio.sck) = '0' then
-- v.sd.state := r.sd.rstate;
-- if r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- if r.spio.initialized = '1' then
-- v.sd.state := SD_READY;
-- else
-- -- Try to initialize again
-- v.sd.state := SD_CHECK_PRES;
-- end if;
-- v.spio.errorn := '0';
-- v.sd.timeout := '1';
-- end if;
-- v.spio.csn := '1';
-- end if;
-- v.sd.tcnt := (others => '0');
-- when others => -- SD_CHECK_PRES
-- if r.sd.cd = '1' then
-- v.go := '1';
-- v.spio.csn := '0';
-- v.sd.state := SD_GET_RESP;
-- v.spio.cdcsnoen := OUTPUT;
-- end if;
-- v.sd.htb := '0';
-- v.sd.vresp := '1';
-- v.sd.rstate := SD_PWRUP0;
-- v.sd.rcnt := cslv(10, r.sd.rcnt'length);
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- end case;
-- end if;
---------------------------------------------------------------------------
-- SPI Flash (non SD) specific code
---------------------------------------------------------------------------
if sdcard = 0 then
case r.spi.state is
when SPI_READ =>
if r.go = '0' then
v.go := '1';
change := '1';
end if;
v.spi.cnt := cslv(SPI_ARG_LEN, r.spi.cnt'length);
if v.bd = '1' then
v.sreg := r.ar(23 downto 16);
end if;
if r.bd = '1' then
v.hold := '0';
v.spi.state := SPI_ADDR;
end if;
when SPI_ADDR =>
if v.bd = '1' then
v.sreg := r.ar(22 downto 15);
if dualoutput = 1 then
if r.spi.cnt = zero32(r.spi.cnt'range) then
v.spio.mosioen := INPUT;
end if;
end if;
end if;
if r.bd = '1' then
if r.spi.cnt = zero32(r.spi.cnt'range) then
v.spi.state := SPI_DATA;
v.spi.cnt := calc_spi_cnt(r.spi.hsize);
else
v.spi.cnt := r.spi.cnt - 1;
end if;
end if;
when SPI_DATA =>
if v.bd = '1' then
v.spi.cnt := r.spi.cnt - 1;
end if;
if lastbit = '1' and r.spi.cnt = zero32(r.spi.cnt'range) then
v.stop := r.go;
end if;
if (r.go or r.spio.sck) = '0' then
if r.spi.hburst(0) = '0' then -- not an incrementing burst
v.spi.state := SPI_PWRUP; -- CSN wait
v.spio.csn := '1';
v.go := '1';
v.stop := '1';
v.seq := '1'; -- Make right choice in SPI_PWRUP
v.bcnt := "110";
else
v.spi.state := SPI_READY;
end if;
v.hold := '1';
end if;
when SPI_READY =>
v.spio.ready := '1';
if read_flash then
v.go := '1';
if dualoutput = 1 then
v.bcnt(2) := '0';
end if;
if r.spio.csn = '1' then
-- New access, command and address
v.go := '0';
v.spio.csn := '0';
v.spi.state := SPI_READ;
elsif r.seq = '1' then
-- Continuation of burst
v.spi.state := SPI_DATA;
v.hold := '0';
else
-- Burst ended and new access
v.stop := '1';
v.spio.csn := '1';
v.spi.state := SPI_PWRUP;
v.bcnt := "011";
end if;
v.ar := (others => '0');
if offset /= 0 then
v.ar(r.haddr'range) := r.haddr + cslv(offset, req_addr_bits);
else
v.ar(r.haddr'range) := r.haddr;
end if;
v.spio.ready := '0';
v.sreg := cslv(readcmd, 8);
end if;
if r.spio.ready = '0' then
case r.spi.hsize is
when HSIZE_BYTE =>
for i in 0 to (MAXDW/8-1) loop
v.frdata(7+8*i downto 8*i):= r.ar(7 downto 0);
end loop; -- i
when HSIZE_HWORD =>
for i in 0 to (MAXDW/16-1) loop
v.frdata(15+16*i downto 16*i) := r.ar(15 downto 0);
end loop; -- i
when HSIZE_WORD =>
for i in 0 to (MAXDW/32-1) loop
v.frdata(31+32*i downto 32*i) := r.ar(31 downto 0);
end loop; -- i
when HSIZE_DWORD =>
if MAXDW > 32 and AHBDW > 32 then
for i in 0 to (MAXDW/64-1) loop
if MAXDW = 64 then
v.frdata(MAXDW-1+MAXDW*i downto MAXDW*i) :=
r.ar(MAXDW-1 downto 0);
elsif MAXDW = 128 then
v.frdata(MAXDW/2-1+MAXDW/2*i downto MAXDW/2*i) :=
r.ar(MAXDW/2-1 downto 0);
else
v.frdata(MAXDW/4-1+MAXDW/4*i downto MAXDW/4*i) :=
r.ar(MAXDW/4-1 downto 0);
end if;
end loop; -- i
else
null;
end if;
when HSIZE_4WORD =>
if MAXDW > 64 and AHBDW > 64 then
for i in 0 to (MAXDW/128-1) loop
if MAXDW = 128 then
v.frdata(MAXDW-1+MAXDW*i downto MAXDW*i) :=
r.ar(MAXDW-1 downto 0);
else
v.frdata(MAXDW/2-1+MAXDW/2*i downto MAXDW/2*i) :=
r.ar(MAXDW/2-1 downto 0);
end if;
end loop; -- i
else
null;
end if;
when others =>
if MAXDW > 128 and AHBDW > 128 then
v.frdata := r.ar;
else
null;
end if;
end case;
end if;
v.spi.hsize := r.hsize;
v.spi.hburst(0) := r.hburst(0);
v.spi.cnt := calc_spi_cnt(r.spi.hsize);
when others => -- SPI_PWRUP
v.hold := '1';
if r.spio.initialized = '1' then
-- Chip select wait
if (r.go or r.spio.sck) = '0' then
if r.seq = '1' then
v.spi.state := SPI_READY;
else
v.spi.state := SPI_READ;
v.spio.csn := '0';
end if;
if dualoutput = 1 then
v.spio.mosioen := OUTPUT;
v.bcnt(2) := '0';
end if;
end if;
else
-- Power up wait
if pwrupcnt /= 0 then
v.frdata := r.frdata - 1;
if r.frdata = zahbdw(r.frdata'range) then
v.spio.initialized := '1';
v.spi.state := SPI_READY;
end if;
else
v.spio.initialized := '1';
v.spi.state := SPI_READY;
end if;
end if;
end case;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
-- Clock generation
if (r.go or r.spio.sck) = '1' then
v.timer := r.timer - 1;
if sck_toggle(v.timer, r.timer, enable_altscaler) then
v.spio.sck := not r.spio.sck;
v.sample(0) := not r.spio.sck;
change := r.spio.sck and r.go;
if (v.stop and lastbit and not r.spio.sck) = '1' then
v.go := '0';
v.stop := '0';
end if;
end if;
else
v.timer := (others => '1');
end if;
if r.sample(0) = '1' then
v.bcnt := r.bcnt + 1;
end if;
if r.sample(1-sdcard) = '1' then
if r.hold = '0' then
if sdcard = 0 and dualoutput = 1 and r.spio.mosioen = INPUT then
v.ar := r.ar(r.ar'left-2 downto 0) & r.spii(1-sdcard).miso & r.spii(1-sdcard).mosi;
else
v.ar := r.ar(r.ar'left-1 downto 0) & r.spii(1-sdcard).miso;
end if;
end if;
end if;
if change = '1' then
v.spio.mosi := v.sreg(7);
if sdcard = 1 or r.spi.state /= SPI_PWRUP then
v.sreg(7 downto 0) := v.sreg(6 downto 0) & '1';
end if;
end if;
---------------------------------------------------------------------------
-- System and core reset
---------------------------------------------------------------------------
if (not rstn or r.rst) = '1' then
-- if sdcard = 1 then
-- v.sd.state := SD_CHECK_PRES;
-- v.spio.cdcsnoen := INPUT;
-- v.sd.timeout := '0';
-- else
v.spi.state := SPI_PWRUP;
v.frdata := cslv(pwrupcnt, r.frdata'length);
v.spio.cdcsnoen := OUTPUT;
-- end if;
v.spimstate := IDLE;
v.rst := '0';
--
v.reg.ctrl := ('0', '0', '0');
v.reg.stat.done := '0';
--
v.sample := (others => '0');
v.sreg := (others => '1');
v.bcnt := (others => '0');
v.go := '0';
v.stop := '0';
v.hold := '0';
v.unsplit := '0';
--
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
--
v.spio.sck := '0';
v.spio.mosi := '1';
v.spio.mosioen := OUTPUT;
v.spio.csn := '1';
-- v.spio.errorn := '1';
v.spio.initialized := '0';
v.spio.ready := '0';
end if;
---------------------------------------------------------------------------
-- Drive unused signals
---------------------------------------------------------------------------
-- if sdcard = 1 then
-- v.spi.state := SPI_PWRUP;
-- v.spi.cnt := (others => '0');
-- v.spi.hsize := (others => '0');
-- v.spi.hburst := (others => '0');
-- v.hburst := (others => '0');
-- v.seq := '0';
-- else
-- v.sd.state := SD_CHECK_PRES;
-- v.sd.tcnt := (others => '0');
-- v.sd.rcnt := (others => '0');
-- v.sd.cmd := (others => '0');
-- v.sd.rstate := SD_CHECK_PRES;
-- v.sd.htb := '0';
-- v.sd.vresp := '0';
-- v.sd.timeout := '0';
-- v.sd.dtocnt := (others => '0');
-- v.sd.ctocnt := (others => '0');
-- end if;
if spliten = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
---------------------------------------------------------------------------
-- Signal assignments
---------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
if r.hmbsel(CTRL_BANK) = '1' then
for i in 0 to (MAXDW/32-1) loop
hrdata(31 + 32*i downto 32*i) := zero32(31 downto 8) & r.rrdata;
end loop;
else
hrdata := r.frdata;
end if;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= ahbirq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
-- SPI signals
spio <= r.spio;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spimctrl" & tost(hindex) & ": SPI memory controller rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
|
gpl-2.0
|
2a8661631445a02176b81576ba045790
| 0.443678 | 3.719333 | false | false | false | false |
aortiz49/MIPS-Processor
|
Hardware/alu32.vhd
| 1 | 2,727 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu32 is
port(
ia : in std_logic_vector(31 downto 0);
ib : in std_logic_vector(31 downto 0);
shamt : in std_logic_vector(4 downto 0);
shdir : in std_logic;
C : out std_logic;
control : in std_logic_vector(3 downto 0);
output : out std_logic_vector(31 downto 0);
Z : out std_logic;
S : out std_logic;
V : out std_logic
);
end alu32;
architecture arch of alu32 is
signal temp_c : std_logic_vector(32 downto 0);
signal temp_o : std_logic_vector(31 downto 0);
signal temp_less: std_logic_vector(31 downto 0);
signal temp_out : std_logic_vector(31 downto 0);
signal temp_shift : std_logic_vector(31 downto 0);
signal sh_en : std_logic;
begin
alu: for i in 0 to 30 generate --generate 32 1-bit adders for alu32 entity
alu: entity work.alu1
port map(
ia => ia(i),
ib => ib(i),
less => temp_less(i),
cout=> temp_c(i+1),-- Cin will be previous value temp signal
cin => temp_c(i), -- cout will feed into cin
control => control,
output => temp_o(i)
);
end generate;
alu32: entity work.alu1_last
port map(
ia => ia(31),
ib => ib(31),
less => temp_less(31),
cout=> temp_c(32),-- Cin will be previous value temp signal
cin => temp_c(31), -- cout will feed into cin
control => control,
slt_en => temp_less(0),
output => temp_o(31)
);
shift: entity work.shifter
port map(
ib => ib,
shdir => shdir,
shamt => shamt,
q => temp_shift
);
mux: entity work.mux_gen
generic map(width => 32)
port map(
in0 => temp_o,
in1 => temp_shift,
sel => sh_en,
output => temp_out
);
temp_c(0) <= control(2); -- Set cin to first adder to 0. Leaving it blank will result in an 'X' for sum(0)
C <= temp_c(32);
-- Z flag
Z <= not (temp_out(31) or temp_out(30) or temp_out(29) or temp_out(28) or temp_out(27) or temp_out(26) or
temp_out(25) or temp_out(24) or temp_out(23) or temp_out(22) or temp_out(21) or temp_out(20) or
temp_out(19) or temp_out(18) or temp_out(17) or temp_out(16) or temp_out(15) or temp_out(14) or
temp_out(13) or temp_out(12) or temp_out(11) or temp_out(10) or temp_out(9) or temp_out(8)or
temp_out(7) or temp_out(6) or temp_out(5) or temp_out(4) or temp_out(3) or temp_out(2) or temp_out(1) or
temp_out(0));
-- S flag
S <= temp_out(31);
-- V flag
V <= (temp_c(32) xor temp_c(31));
-- shift enable
sh_en <= (not control(3) and not control(2) and control(1) and control(0));
temp_less(31 downto 1) <= (others => '0');
output <= temp_out;
end arch;
|
mit
|
afec00b50e6327a220a1b4e6ded71f62
| 0.591126 | 2.592205 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/libiu.vhd
| 1 | 8,958 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libiu
-- File: libiu.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 IU types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
use gaisler.mmuconfig.all;
package libiu is
constant RDBITS : integer := 32;
constant IDBITS : integer := 32;
subtype cword is std_logic_vector(IDBITS-1 downto 0);
type cdatatype is array (0 to 3) of cword;
type iregfile_in_type is record
raddr1 : std_logic_vector(9 downto 0); -- read address 1
raddr2 : std_logic_vector(9 downto 0); -- read address 2
waddr : std_logic_vector(9 downto 0); -- write address
wdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type iregfile_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
type cctrltype is record
burst : std_ulogic; -- icache burst enable
dfrz : std_ulogic; -- dcache freeze enable
ifrz : std_ulogic; -- icache freeze enable
dsnoop : std_ulogic; -- data cache snooping
dcs : std_logic_vector(1 downto 0); -- dcache state
ics : std_logic_vector(1 downto 0); -- icache state
end record;
constant cctrl_none : cctrltype := (
burst => '0', dfrz => '0', ifrz => '0', dsnoop => '0',
dcs => (others => '0'), ics => (others => '0')
);
type icache_in_type is record
rpc : std_logic_vector(31 downto 0); -- raw address (npc)
fpc : std_logic_vector(31 downto 0); -- latched address (fpc)
dpc : std_logic_vector(31 downto 0); -- latched address (dpc)
rbranch : std_ulogic; -- Instruction branch
fbranch : std_ulogic; -- Instruction branch
inull : std_ulogic; -- instruction nullify
su : std_ulogic; -- super-user
flush : std_ulogic; -- flush icache
fline : std_logic_vector(31 downto 3); -- flush line offset
nobpmiss : std_ulogic; -- Predicted instruction, block hold
end record;
type icache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic; -- flush in progress
diagrdy : std_ulogic; -- diagnostic access ready
diagdata : std_logic_vector(IDBITS-1 downto 0);-- diagnostic data
mds : std_ulogic; -- memory data strobe
cfg : std_logic_vector(31 downto 0);
idle : std_ulogic; -- idle mode
cstat : l3_cstat_type;
bpmiss : std_ulogic;
eocl : std_ulogic;
end record;
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_ulogic;
end record;
type dcache_in_type is record
asi : std_logic_vector(7 downto 0);
maddress : std_logic_vector(31 downto 0);
eaddress : std_logic_vector(31 downto 0);
edata : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic; -- flush line
dsuen : std_ulogic;
msu : std_ulogic; -- memory stage supervisor
esu : std_ulogic; -- execution stage supervisor
intack : std_ulogic;
end record;
type dcache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic; -- idle mode
hit : std_ulogic;
cstat : l3_cstat_type;
wbhold : std_ulogic;
end record;
component iu3
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15 := 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
tbo_2p : in tracebuf_2p_out_type;
tbi_2p : out tracebuf_2p_in_type;
sclk : in std_ulogic
);
end component;
end;
|
gpl-2.0
|
7d8e760316895325d86c8c072abfe326
| 0.490511 | 4.07367 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-kc705/config.vhd
| 1 | 7,221 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := kintex7;
constant CFG_MEMTECH : integer := kintex7;
constant CFG_PADTECH : integer := kintex7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := kintex7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 1 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 16;
constant CFG_DTLBNUM : integer := 16;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 0;
constant CFG_L2_SIZE : integer := 64;
constant CFG_L2_WAYS : integer := 1;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#00AA#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := 1;
constant CFG_MIG_7SERIES_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (7);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
4df401b8ce2eaccaddf55fc3d03795f5
| 0.648525 | 3.565926 | false | false | false | false |
aprgl/dead_time
|
vhdl/dead_time.vhd
| 1 | 5,384 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
--============================================================================
-- Dead Time Generation Block
--============================================================================
-- Generate dead time to avoid shoot through caused by high or low side being
-- commanded on before power device has fully turned off.
-- Version: 0.0.0 Initial Commit - haven't even tried to compile -Shaun
-- Version: 0.0.1 Fixed github linter errors - still haven't compiled -Shaun
-- Version: 0.0.2 Added enable signals -still haven't compiled -Inigo Montoya
------------------------------------------------------------------------------
entity dead_time is
Port (
rst_n_in : in std_logic;
clk_in : in std_logic;
ena_in : in std_logic;
high_side_in : in std_logic;
low_side_in : in std_logic;
dead_time_in : in std_logic_vector(7 downto 0);
high_side_out : out std_logic;
low_side_out : out std_logic
);
end entity dead_time;
architecture rtl of dead_time is
-- State Machine Signals
signal dead_time_counter : std_logic_vector(7 downto 0) := '0';
signal low_side_signal, head_side_signal : std_logic;
-- State Machine Signals
type state_type is (state_reset,
state_hold,
state_standby,
state_h,
state_l);
signal state, next_state: state_type := state_reset; -- legal?
begin
--========================================================================
-- State Machine Control
--========================================================================
-- State machine control block - reset and next state indexing
--------------------------------------------------------------------------
-- State machine control block - reset and next state indexing
state_machine_ctrl: process (rst_n_in, clk_in) begin
if (rst_n_in = '0') then
state <= state_reset; -- default state on reset
elsif (rising_edge(sys_clk)) then
state <= next_state; -- clocked change of state
end if;
end process state_machine_ctrl;
-- State machine for our little dead time controller
state_machine: process (state,
dead_time_complete,
high_side_in,
low_side_in) begin
case state is
-- If we're in a reset state, kill our outputs and assume they were
-- previously commanded high, so reset our dead time counter to 0.
when state_reset =>
low_side_signal <= '0';
high_side_signal <= '0';
next_state <= state_hold;
-- We're ready to start our dead time counter
when state_hold =>
low_side_signal <= '0';
high_side_signal <= '0';
if(dead_time_complete = '1') then
next_state <= state_standby;
else
next_state <= state_hold;
end if;
-- Ready to drive an output
when state_standby =>
low_side_signal <= '0';
high_side_signal <= '0';
if (low_side_in = '1') then
next_state <= state_l;
elsif (high_side_in = '1') then
next_state <= state_h;
else
next_state <= state_standby;
end if;
-- Low side is being commanded on and we are not in dead time
when state_l =>
low_side_signal <= '1';
high_side_signal <= '0';
if (low_side_in = '1') then
next_state <= state_l;
else
next_state <= state_reset;
end if;
-- High side is being commanded on and we are not in dead time
when state_h =>
low_side_signal <= '0';
high_side_signal <= '1';
if (high_side_in = '1') then
next_state <= state_h;
else
next_state <= state_reset;
end if;
end case;
end process state_machine;
--------------------------------------------------------------------------
--========================================================================
-- Dead Time Counter Logic
--========================================================================
dead_time_counter_proc: process (state, clk_in) begin
if (state = state_reset) then
dead_time_complete <= '0';
dead_time_counter <= (others => '0');
elsif (rising_edge(clk_in) and (state = state_hold)) then
if(dead_time_counter < dead_time_in) then
dead_time_counter <= dead_time_counter + 1;
else
dead_time_complete <= '1';
end if;
end if;
end process dead_time_counter_proc;
-------------------------------------------------------------------------
--=======================================================================
-- Stateless Signals
--=======================================================================
low_side_out <= '1' when (low_side_signal & ena_in) else '0';
high_side_out <= '1' when (high_side_signal & ena_in) else '0';
--------------------------------------------------------------------------
end architecture rtl;
|
gpl-2.0
|
114631167d8ce96f8fb823dc6788ce0c
| 0.445951 | 4.62543 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-sockit/testbench.vhd
| 2 | 20,229 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 25; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- --DDR3--
DDR3_A : out std_logic_vector(14 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_CAS_n : out std_logic;
DDR3_CKE : out std_logic;
DDR_CK_n : out std_logic;
DDR3_CK_p : out std_logic;
DDR3_CS_n : out std_logic;
DDR3_DM : out std_logic_vector(3 downto 0);
DDR3_DQ : inout std_logic_vector(31 downto 0);
DDR3_DQS_n : inout std_logic_vector(3 downto 0);
DDR3_DQS_p : inout std_logic_vector(3 downto 0);
DDR3_ODT : out std_logic;
DDR3_RAS_n : out std_logic;
DDR3_RESET_n : out std_logic;
DDR3_RZQ : in std_logic;
DDR3_WE_n : out std_logic;
--
-- --FAN CONTROL--
-- FAN_CTRL : out std_logic;
--
--
-- --HPS--
HPS_CONV_USB_n : inout std_logic; --input HPS_CONV_USB_n,
HPS_DDR3_A : out std_logic_vector(14 downto 0); --output [14:0] HPS_DDR3_A,
HPS_DDR3_BA : out std_logic_vector(2 downto 0); --output [2:0] HPS_DDR3_BA,
HPS_DDR3_CAS_n : out std_logic; --output HPS_DDR3_CAS_n,
HPS_DDR3_CKE : out std_logic; --output HPS_DDR3_CKE,
HPS_DDR3_CK_n : out std_logic; --output HPS_DDR3_CK_n,
HPS_DDR3_CK_p : out std_logic; --output HPS_DDR3_CK_p,
HPS_DDR3_CS_n : out std_logic; --output HPS_DDR3_CS_n,
HPS_DDR3_DM : out std_logic_vector(3 downto 0); --output [3:0] HPS_DDR3_DM,
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); --inout [31:0] HPS_DDR3_DQ,
HPS_DDR3_DQS_n : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_DDR3_DQS_n,
HPS_DDR3_DQS_p : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_DDR3_DQS_p,
HPS_DDR3_ODT : out std_logic; --output HPS_DDR3_ODT,
HPS_DDR3_RAS_n : out std_logic; --output HPS_DDR3_RAS_n,
HPS_DDR3_RESET_n : out std_logic; --output HPS_DDR3_RESET_n,
HPS_DDR3_RZQ : in std_logic; --input HPS_DDR3_RZQ,
HPS_DDR3_WE_n : out std_logic; --output HPS_DDR3_WE_n,
HPS_ENET_GTX_CLK : out std_logic; --output HPS_ENET_GTX_CLK,
HPS_ENET_INT_n : inout std_logic; --inout HPS_ENET_INT_n,
HPS_ENET_MDC : out std_logic; --output HPS_ENET_MDC,
HPS_ENET_MDIO : inout std_logic; --inout HPS_ENET_MDIO,
HPS_ENET_RX_CLK : in std_logic; --input HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); --input [3:0] HPS_ENET_RX_DATA,
HPS_ENET_RX_DV : in std_logic; --input HPS_ENET_RX_DV,
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); --output [3:0] HPS_ENET_TX_DATA,
HPS_ENET_TX_EN : out std_logic; --output HPS_ENET_TX_EN,
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_FLASH_DATA,
HPS_FLASH_DCLK : out std_logic; --output HPS_FLASH_DCLK,
HPS_FLASH_NCSO : out std_logic; --output HPS_FLASH_NCSO,
HPS_GSENSOR_INT : inout std_logic; --inout HPS_GSENSOR_INT,
HPS_I2C_CLK : inout std_logic; --inout HPS_I2C_CLK,
HPS_I2C_SDA : inout std_logic; --inout HPS_I2C_SDA,
-- HPS_KEY : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_KEY,
HPS_LCM_BK : inout std_logic; --inout HPS_LCM_BK,
HPS_LCM_D_C : inout std_logic; --output HPS_LCM_D_C,
HPS_LCM_RST_N : inout std_logic; --output HPS_LCM_RST_N,
HPS_LCM_SPIM_CLK : out std_logic; --input HPS_LCM_SPIM_CLK,
HPS_LCM_SPIM_MOSI : out std_logic; --output HPS_LCM_SPIM_MOSI,
HPS_LCM_SPIM_SS : out std_logic; --output HPS_LCM_SPIM_SS,
HPS_LCM_SPIM_MISO : in std_logic;
HPS_LED : inout std_logic_vector(3 downto 0); --output [3:0] HPS_LED,
HPS_LTC_GPIO : inout std_logic; --inout HPS_LTC_GPIO,
HPS_SD_CLK : out std_logic; --output HPS_SD_CLK,
HPS_SD_CMD : inout std_logic; --inout HPS_SD_CMD,
HPS_SD_DATA : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_SD_DATA,
HPS_SPIM_CLK : out std_logic; --output HPS_SPIM_CLK,
HPS_SPIM_MISO : in std_logic; --input HPS_SPIM_MISO,
HPS_SPIM_MOSI : out std_logic; --output HPS_SPIM_MOSI,
HPS_SPIM_SS : out std_logic; --output HPS_SPIM_SS,
-- HPS_SW : in std_logic_vector(3 downto 0); --input [3:0] HPS_SW,
HPS_UART_RX : in std_logic; --input HPS_UART_RX,
HPS_UART_TX : out std_logic; --output HPS_UART_TX,
HPS_USB_CLKOUT : in std_logic; --input HPS_USB_CLKOUT,
HPS_USB_DATA : inout std_logic_vector(7 downto 0); --inout [7:0] HPS_USB_DATA,
HPS_USB_DIR : in std_logic; --input HPS_USB_DIR,
HPS_USB_NXT : in std_logic; --input HPS_USB_NXT,
HPS_USB_STP : out std_logic; --output HPS_USB_STP,
--
-- --Audio--
-- AUD_ADCDAT : in std_logic; --input AUD_ADCDAT,
-- AUD_ADCLRCK : inout std_logic; --inout AUD_ADCLRCK,
-- AUD_BCLK : inout std_logic; --inout AUD_BCLK,
-- AUD_DACDAT : out std_logic; --output AUD_DACDAT,
-- AUD_DACLRCK : inout std_logic; --inout AUD_DACLRCK,
-- AUD_I2C_SCLK : out std_logic; --output AUD_I2C_SCLK,
-- AUD_I2C_SDAT : inout std_logic; --inout AUD_I2C_SDAT,
-- AUD_MUTE : out std_logic; --output AUD_MUTE,
-- AUD_XCK : out std_logic; --output AUD_XCK,
--
-- --HSMC--
-- HSMC_CLKIN_n : in std_logic_vector(2 downto 1); --input [2:1] HSMC_CLKIN_n,
-- HSMC_CLKIN_p : in std_logic_vector(2 downto 1); --input [2:1] HSMC_CLKIN_p,
-- HSMC_CLKOUT_n : out std_logic_vector(2 downto 1); --output [2:1] HSMC_CLKOUT_n,
-- HSMC_CLKOUT_p : out std_logic_vector(2 downto 1); --output [2:1] HSMC_CLKOUT_p,
-- HSMC_CLK_IN0 : out std_logic; --output HSMC_CLK_IN0,
-- HSMC_CLK_OUT0 : out std_logic; --output HSMC_CLK_OUT0,
-- HSMC_D : inout std_logic_vector(3 downto 0); --inout [3:0] HSMC_D,
-- HSMC_GXB_RX_p : in std_logic_vector(7 downto 0); --input [7:0] HSMC_GXB_RX_p,
-- HSMC_GXB_TX_p : out std_logic_vector(7 downto 0); --output [7:0] HSMC_GXB_TX_p,
-- HSMC_REF_CLK_p : in std_logic; --input HSMC_REF_CLK_p,
-- HSMC_RX_n : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_RX_n,
-- HSMC_RX_p : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_RX_p,
-- HSMC_SCL : out std_logic; --output HSMC_SCL,
-- HSMC_SDA : inout std_logic; --inout HSMC_SDA,
-- HSMC_TX_n : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_TX_n,
-- HSMC_TX_p : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_TX_p,
--
-- --IRDA--
-- IRDA_RXD : in std_logic; --input IRDA_RXD,
--
-- --PCIE--
-- PCIE_PERST_n : in std_logic; --input PCIE_PERST_n,
-- PCIE_WAKE_n : out std_logic; --output PCIE_WAKE_n,
--
-- --SI5338--
-- SI5338_SCL : in std_logic; --inout SI5338_SCL,
-- SI5338_SDA : in std_logic; --inout SI5338_SDA,
--
-- --TEMP--
-- TEMP_CS_n : out std_logic; --output TEMP_CS_n,
-- TEMP_DIN : out std_logic; --output TEMP_DIN,
-- TEMP_DOUT : in std_logic; --input TEMP_DOUT,
-- TEMP_SCLK : out std_logic; --output TEMP_SCLK,
--
-- --USB--
-- USB_B2_CLK : in std_logic; --input USB_B2_CLK,
-- USB_B2_DATA : inout std_logic_vector(7 downto 0); --inout [7:0] USB_B2_DATA,
-- USB_EMPTY : out std_logic; --output USB_EMPTY,
-- USB_FULL : out std_logic; --output USB_FULL,
-- USB_OE_n : in std_logic; --input USB_OE_n,
-- USB_RD_n : in std_logic; --input USB_RD_n,
-- USB_RESET_n : in std_logic; --input USB_RESET_n,
-- USB_SCL : inout std_logic; --inout USB_SCL,
-- USB_SDA : inout std_logic; --inout USB_SDA,
-- USB_WR_n : in std_logic; --input USB_WR_n,
--
-- --VGA--
-- VGA_B : out std_logic_vector(7 downto 0); --output [7:0] VGA_B,
-- VGA_BLANK_n : out std_logic; --output VGA_BLANK_n,
-- VGA_CLK : out std_logic; --output VGA_CLK,
-- VGA_G : out std_logic_vector(7 downto 0); --output [7:0] VGA_G,
-- VGA_HS : out std_logic; --output VGA_HS,
-- VGA_R : out std_logic_vector(7 downto 0); --output [7:0] VGA_R,
-- VGA_SYNC_n : out std_logic; --output VGA_SYNC_n,
-- VGA_VS : out std_logic; --output VGA_VS
--OSC (CLOCKS)--
OSC_50_B3B : in std_logic; --input OSC_50_B3B,
OSC_50_B4A : in std_logic; --input OSC_50_B4A,
OSC_50_B5B : in std_logic; --input OSC_50_B5B,
OSC_50_B8A : in std_logic; --input OSC_50_B8A,
--RESET--
RESET_n : in std_logic; --input RESET_n,
--KEY (PUSHBUTTONS)--
KEY : in std_logic_vector(3 downto 0); --input [3:0] KEY,
--LED--
LED : out std_logic_vector(3 downto 0); --output [3:0] LED,
--SW (SWITCHES)--
SW : in std_logic_vector(3 downto 0) --input [3:0] SW,
);
end component;
signal clk50, clkout: std_ulogic := '0';
signal rst: std_ulogic;
signal user_led: std_logic_vector(3 downto 0);
signal address : std_logic_vector(26 downto 1);
signal data : std_logic_vector(15 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
constant lresp : boolean := false;
begin
-- clock and reset
clk50 <= not clk50 after 20 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : leon3mp
generic map ( fabtech, memtech, padtech, disas, dbguart, pclow )
port map (
DDR3_A => open,
DDR3_BA => open,
DDR3_CAS_n => open,
DDR3_CKE => open,
DDR_CK_n => open,
DDR3_CK_p => open,
DDR3_CS_n => open,
DDR3_DM => open,
DDR3_DQ => open,
DDR3_DQS_n => open,
DDR3_DQS_p => open,
DDR3_ODT => open,
DDR3_RAS_n => open,
DDR3_RESET_n => open,
DDR3_RZQ => '0',
DDR3_WE_n => open,
HPS_CONV_USB_n => open,
HPS_DDR3_A => open,
HPS_DDR3_BA => open,
HPS_DDR3_CAS_n => open,
HPS_DDR3_CKE => open,
HPS_DDR3_CK_n => open,
HPS_DDR3_CK_p => open,
HPS_DDR3_CS_n => open,
HPS_DDR3_DM => open,
HPS_DDR3_DQ => open,
HPS_DDR3_DQS_n => open,
HPS_DDR3_DQS_p => open,
HPS_DDR3_ODT => open,
HPS_DDR3_RAS_n => open,
HPS_DDR3_RESET_n => open,
HPS_DDR3_RZQ => '0',
HPS_DDR3_WE_n => open,
HPS_ENET_GTX_CLK => open,
HPS_ENET_INT_n => open,
HPS_ENET_MDC => open,
HPS_ENET_MDIO => open,
HPS_ENET_RX_CLK => '0',
HPS_ENET_RX_DATA => (others => '0'),
HPS_ENET_RX_DV => '0',
HPS_ENET_TX_DATA => open,
HPS_ENET_TX_EN => open,
HPS_FLASH_DATA => open,
HPS_FLASH_DCLK => open,
HPS_FLASH_NCSO => open,
HPS_GSENSOR_INT => open,
HPS_I2C_CLK => open,
HPS_I2C_SDA => open,
HPS_LCM_BK => open,
HPS_LCM_D_C => open,
HPS_LCM_RST_N => open,
HPS_LCM_SPIM_CLK => open,
HPS_LCM_SPIM_MOSI => open,
HPS_LCM_SPIM_SS => open,
HPS_LCM_SPIM_MISO => '0',
HPS_LED => open,
HPS_LTC_GPIO => open,
HPS_SD_CLK => open,
HPS_SD_CMD => open,
HPS_SD_DATA => open,
HPS_SPIM_CLK => open,
HPS_SPIM_MISO => '0',
HPS_SPIM_MOSI => open,
HPS_SPIM_SS => open,
HPS_UART_RX => '0',
HPS_UART_TX => open,
HPS_USB_CLKOUT => '0',
HPS_USB_DATA => open,
HPS_USB_DIR => '0',
HPS_USB_NXT => '0',
HPS_USB_STP => open,
OSC_50_B3B => clk50,
OSC_50_B4A => clk50,
OSC_50_B5B => clk50,
OSC_50_B8A => clk50,
--RESET--
RESET_n => rst,
--KEY (PUSHBUTTONS)--
KEY => "0000",
--LED--
LED => user_led,
--SW (SWITCHES)--
SW => "1111"
);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data,
romsn, romsn, romsn, rwen, oen);
data <= buskeep(data), (others => 'H') after 250 ns;
error <= user_led(3);
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod generic map (width => 16)
port map ( rst, clk50, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
7823e35ad77c2ea530fe75d4b150754e
| 0.520144 | 2.827254 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/iopad.vhd
| 1 | 7,616 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopad is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen) and slew = 0
else 'X' when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else 'Z';
o <= transport to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_iopad port map (pad, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhs : if (tech = rhs65) generate
x0 : rhs65_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0), cfgi(2), cfgi(1));
end generate;
dar : if (tech = dare) generate
x0 : dare_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, i, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, i, oen, o);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopadv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en, o(j), cfgi);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopadvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en(j), o(j), cfgi);
end generate;
end;
|
gpl-2.0
|
5c820cabbd5047856c0592fba7dded66
| 0.635373 | 3.378882 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/ec/orca/orca.vhd
| 5 | 898,554 |
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_SEQ.vhd,v 1.1 2005/12/06 13:00:24 tame Exp $
--
----- cell gsr -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
-- entity declaration --
ENTITY gsr IS
GENERIC(
timingcheckson : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "gsr");
PORT(
gsr : IN std_logic := 'Z');
END gsr;
-- architecture body --
ARCHITECTURE v OF gsr IS
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
-- empty
END BLOCK;
--------------------
-- behavior section
--------------------
gsrnet <= gsr;
END v;
--
----- cell pur -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.purnet;
-- entity declaration --
ENTITY pur IS
GENERIC(
timingcheckson : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "pur");
PORT(
pur : IN std_logic := 'Z');
END pur;
-- architecture body --
ARCHITECTURE v OF pur IS
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
-- empty
END BLOCK;
--------------------
-- behavior section
--------------------
purnet <= pur;
END v;
--
----- cell fd1p3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1p3ax IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1p3ax";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1p3ax : ENTITY IS TRUE;
END fd1p3ax ;
-- architecture body --
ARCHITECTURE v OF fd1p3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(sp_ipd, sp, tipd_sp);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 8) := (
-- viol clr ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '1', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd,
TestSignalname => "d",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sp_ipd='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_sp OR tviol_ck;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, sp_ipd, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1p3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1p3ay IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1p3ay";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1p3ay : ENTITY IS TRUE;
END fd1p3ay ;
-- architecture body --
ARCHITECTURE v OF fd1p3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(sp_ipd, sp, tipd_sp);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 8) := (
-- viol pre ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '1', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd,
TestSignalname => "d",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sp_ipd='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_sp OR tviol_ck;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, sp_ipd, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1p3bx IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1p3bx";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
pd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1p3bx : ENTITY IS TRUE;
END fd1p3bx ;
-- architecture body --
ARCHITECTURE v OF fd1p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, ck_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 8) := (
-- viol pre ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '-', '1', '0' ), -- async. preset
( '-', '0', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '0', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '0', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '0', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd,
TestSignalname => "d",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd,
TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd,
Violation => tviol_pd,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_sp OR tviol_ck OR tviol_pd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => not(set_reset), b => pd_ipd);
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, preset, sp_ipd, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1p3dx IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1p3dx";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
cd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1p3dx : ENTITY IS TRUE;
END fd1p3dx ;
-- architecture body --
ARCHITECTURE v OF fd1p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, ck_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 8) := (
-- viol clr ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '-', '0', '1' ), -- async. clear
( '-', '0', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '0', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '0', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '0', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd,
TestSignalname => "d",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sp_ipd='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd,
TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd,
Violation => tviol_cd,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_sp OR tviol_ck OR tviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => not(set_reset), b => cd_ipd);
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, clear, sp_ipd, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1p3ix IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1p3ix";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_cd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_cd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
cd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1p3ix : ENTITY IS TRUE;
END fd1p3ix ;
-- architecture body --
ARCHITECTURE v OF fd1p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, ck_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 9) := (
-- viol clr scl ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '0', '1' ), -- sync. clear
( '-', '1', '0', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '0', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '0', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tsviol_cd : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE cd_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd,
TestSignalname => "d",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sp_ipd ='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd,
TestSignalname => "cd",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_cd_ck_noedge_posedge,
SetupLow => tsetup_cd_ck_noedge_posedge,
HoldHigh => thold_cd_ck_noedge_posedge,
HoldLow => thold_cd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => cd_ck_timingdatash,
Violation => tsviol_cd,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd,
TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd,
Violation => tviol_cd,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tsviol_cd OR tviol_sp OR tviol_ck OR tviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, cd_ipd, sp_ipd, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1p3jx IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1p3jx";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_pd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_pd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
pd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1p3jx : ENTITY IS TRUE;
END fd1p3jx ;
-- architecture body --
ARCHITECTURE v OF fd1p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, ck_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 9) := (
-- viol pre spr ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '1', '0' ), -- sync. preset
( '-', '1', '0', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '0', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '0', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tsviol_pd : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE pd_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd ='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_ck_timingdatash,
Violation => tviol_d, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_pd_ck_noedge_posedge,
SetupLow => tsetup_pd_ck_noedge_posedge,
HoldHigh => thold_pd_ck_noedge_posedge,
HoldLow => thold_pd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_ck_timingdatash,
Violation => tsviol_pd, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalname => "sp",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_ck_timingdatash,
Violation => tviol_sp, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd,
TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd,
Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tsviol_pd OR tviol_sp OR tviol_ck OR tviol_pd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, pd_ipd, sp_ipd, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s1a -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s1a IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s1a";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s1a : ENTITY IS TRUE;
END fd1s1a ;
-- architecture body --
ARCHITECTURE v OF fd1s1a IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0', '1' ), -- low d->q on high ck
( '-', '1', '1', '1', '-', '1', '0' ), -- high d->q on high ck
( '-', '1', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_negedge,
SetupLow => tsetup_d_ck_noedge_negedge,
HoldHigh => thold_d_ck_noedge_negedge,
HoldLow => thold_d_ck_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_ck_timingdatash,
Violation => tviol_d, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_ck;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, set_reset, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s1ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s1ay IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s1ay";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s1ay : ENTITY IS TRUE;
END fd1s1ay ;
-- architecture body --
ARCHITECTURE v OF fd1s1ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0', '1' ), -- low d->q on high ck
( '-', '1', '1', '1', '-', '1', '0' ), -- high d->q on high ck
( '-', '1', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_negedge,
SetupLow => tsetup_d_ck_noedge_negedge,
HoldHigh => thold_d_ck_noedge_negedge,
HoldLow => thold_d_ck_noedge_negedge,
CheckEnabled => (set_reset='1'),
RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_ck_timingdatash,
Violation => tviol_d, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_ck;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, set_reset, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s1b -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s1b IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s1b";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s1b : ENTITY IS TRUE;
END fd1s1b ;
-- architecture body --
ARCHITECTURE v OF fd1s1b IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, pd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '1', '0' ), -- async. preset
( '-', '0', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '0', '1', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '0', '1', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '0', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_negedge,
SetupLow => tsetup_d_ck_noedge_negedge,
HoldHigh => thold_d_ck_noedge_negedge,
HoldLow => thold_d_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_ck_timingdatash,
Violation => tviol_d, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_ck OR tviol_pd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => not(set_reset), b => pd_ipd);
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, preset, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s1d -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s1d IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s1d";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s1d : ENTITY IS TRUE;
END fd1s1d ;
-- architecture body --
ARCHITECTURE v OF fd1s1d IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, cd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '0', '1' ), -- async. clear
( '-', '0', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '0', '1', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '0', '1', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '0', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_negedge,
SetupLow => tsetup_d_ck_noedge_negedge,
HoldHigh => thold_d_ck_noedge_negedge,
HoldLow => thold_d_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_ck_timingdatash,
Violation => tviol_d, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd,
TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd,
Violation => tviol_cd,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_ck OR tviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => not(set_reset), b => cd_ipd);
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, clear, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (cd_ipd'last_event, tpd_cd_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s1i -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s1i IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s1i";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_cd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_cd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s1i : ENTITY IS TRUE;
END fd1s1i ;
-- architecture body --
ARCHITECTURE v OF fd1s1i IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, cd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '1', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tsviol_cd : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE cd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synclr : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_negedge,
SetupLow => tsetup_d_ck_noedge_negedge,
HoldHigh => thold_d_ck_noedge_negedge,
HoldLow => thold_d_ck_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_ck_timingdatash,
Violation => tviol_d, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalname => "cd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_cd_ck_noedge_negedge,
SetupLow => tsetup_cd_ck_noedge_negedge,
HoldHigh => thold_cd_ck_noedge_negedge,
HoldLow => thold_cd_ck_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_ck_timingdatash,
Violation => tsviol_cd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd,
TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd,
Violation => tviol_cd,
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tsviol_cd OR tviol_ck OR tviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
synclr := VitalAND2 (a => d_ipd, b => not(cd_ipd));
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, set_reset, ck_ipd, synclr),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s1j -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s1j IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s1j";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_pd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_pd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s1j : ENTITY IS TRUE;
END fd1s1j ;
-- architecture body --
ARCHITECTURE v OF fd1s1j IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, pd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '1', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tsviol_pd : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE pd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synpre : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_negedge,
SetupLow => tsetup_d_ck_noedge_negedge,
HoldHigh => thold_d_ck_noedge_negedge,
HoldLow => thold_d_ck_noedge_negedge,
CheckEnabled => (set_reset='1'),
RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_ck_timingdatash,
Violation => tviol_d, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_pd_ck_noedge_negedge,
SetupLow => tsetup_pd_ck_noedge_negedge,
HoldHigh => thold_pd_ck_noedge_negedge,
HoldLow => thold_pd_ck_noedge_negedge,
CheckEnabled => (set_reset='1'),
RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_ck_timingdatash,
Violation => tsviol_pd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd,
Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tsviol_pd OR tviol_ck OR tviol_pd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
synpre := VitalOR2 (a => d_ipd, b => pd_ipd);
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, set_reset, ck_ipd, synpre),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s3ax IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s3ax";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s3ax : ENTITY IS TRUE;
END fd1s3ax ;
-- architecture body --
ARCHITECTURE v OF fd1s3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_ck;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (gsrnet'last_event, tpd_gsr_q, TRUE),
2 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s3ay IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s3ay";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s3ay : ENTITY IS TRUE;
END fd1s3ay ;
-- architecture body --
ARCHITECTURE v OF fd1s3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_ck;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (gsrnet'last_event, tpd_gsr_q, TRUE),
2 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s3bx IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s3bx";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s3bx : ENTITY IS TRUE;
END fd1s3bx ;
-- architecture body --
ARCHITECTURE v OF fd1s3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '1', '0' ), -- async. preset
( '-', '0', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '0', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '0', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '0', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd,
Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_ck OR tviol_pd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => not(set_reset), b => pd_ipd);
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, preset, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (pd_ipd'last_event, tpd_pd_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s3dx IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s3dx";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s3dx : ENTITY IS TRUE;
END fd1s3dx ;
-- architecture body --
ARCHITECTURE v OF fd1s3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '0', '1' ), -- async. clear
( '-', '0', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '0', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '0', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '0', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd,
TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd,
Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_ck OR tviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => not(set_reset), b => cd_ipd);
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, clear, ck_ipd, d_ipd),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (cd_ipd'last_event, tpd_cd_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s3ix IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s3ix";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_cd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_cd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s3ix : ENTITY IS TRUE;
END fd1s3ix ;
-- architecture body --
ARCHITECTURE v OF fd1s3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tsviol_cd : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE cd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synclr : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalname => "cd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_cd_ck_noedge_posedge,
SetupLow => tsetup_cd_ck_noedge_posedge,
HoldHigh => thold_cd_ck_noedge_posedge,
HoldLow => thold_cd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => cd_ck_timingdatash,
Violation => tsviol_cd,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd,
TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_posedge,
Perioddata => periodcheckinfo_cd,
Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_cd OR tviol_ck OR tsviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
synclr := VitalAND2 (a => d_ipd, b => not(cd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, ck_ipd, synclr),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (gsrnet'last_event, tpd_gsr_q, TRUE),
2 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fd1s3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fd1s3jx IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fd1s3jx";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_pd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_pd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ck : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fd1s3jx : ENTITY IS TRUE;
END fd1s3jx ;
-- architecture body --
ARCHITECTURE v OF fd1s3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising edge ck
( '-', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising edge ck
( '-', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tsviol_pd : X01 := '0';
VARIABLE d_ck_TimingDatash : VitalTimingDataType;
VARIABLE pd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synpre : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalname => "d",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d_ck_noedge_posedge,
SetupLow => tsetup_d_ck_noedge_posedge,
HoldHigh => thold_d_ck_noedge_posedge,
HoldLow => thold_d_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d_ck_timingdatash,
Violation => tviol_d,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_pd_ck_noedge_posedge,
SetupLow => tsetup_pd_ck_noedge_posedge,
HoldHigh => thold_pd_ck_noedge_posedge,
HoldLow => thold_pd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => pd_ck_timingdatash,
Violation => tsviol_pd,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd,
TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd,
Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d OR tviol_pd OR tviol_ck OR tsviol_pd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
synpre := VitalOR2 (a => d_ipd, b => pd_ipd);
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, ck_ipd, synpre),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (gsrnet'last_event, tpd_gsr_q, TRUE),
2 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1p3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1p3ay IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1p3ay";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
sp : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1p3ay : ENTITY IS TRUE;
END fl1p3ay ;
-- architecture body --
ARCHITECTURE v OF fl1p3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, sd_ipd, sp_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 8) := (
-- viol pre ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '1', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising ck
( '-', '1', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising ck
( '-', '1', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd,
TestSignalname => "d0",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_posedge,
SetupLow => tsetup_d0_ck_noedge_posedge,
HoldHigh => thold_d0_ck_noedge_posedge,
HoldLow => thold_d0_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sp_ipd='1' AND sd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d0_ck_timingdatash,
Violation => tviol_d0,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd,
TestSignalname => "d1",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_posedge,
SetupLow => tsetup_d1_ck_noedge_posedge,
HoldHigh => thold_d1_ck_noedge_posedge,
HoldLow => thold_d1_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sp_ipd='1' AND sd_ipd='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d1_ck_timingdatash,
Violation => tviol_d1,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd,
TestSignalname => "sd",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_posedge,
SetupLow => tsetup_sd_ck_noedge_posedge,
HoldHigh => thold_sd_ck_noedge_posedge,
HoldLow => thold_sd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sd_ck_timingdatash,
Violation => tviol_sd,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sp OR tviol_sd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, sp_ipd, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (sd_ipd'last_event, tpd_sd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1p3az -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1p3az IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1p3az";
-- propagation delayS
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
sp : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1p3az : ENTITY IS TRUE;
END fl1p3az ;
-- architecture body --
ARCHITECTURE v OF fl1p3az IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, sd_ipd, sp_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 8) := (
-- viol clr ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '1', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising ck
( '-', '1', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising ck
( '-', '1', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd,
TestSignalname => "d0",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_posedge,
SetupLow => tsetup_d0_ck_noedge_posedge,
HoldHigh => thold_d0_ck_noedge_posedge,
HoldLow => thold_d0_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sp_ipd='1' AND sd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d0_ck_timingdatash,
Violation => tviol_d0,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd,
TestSignalname => "d1",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_posedge,
SetupLow => tsetup_d1_ck_noedge_posedge,
HoldHigh => thold_d1_ck_noedge_posedge,
HoldLow => thold_d1_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sp_ipd='1' AND sd_ipd='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d1_ck_timingdatash,
Violation => tviol_d1,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd,
TestSignalname => "sd",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_posedge,
SetupLow => tsetup_sd_ck_noedge_posedge,
HoldHigh => thold_sd_ck_noedge_posedge,
HoldLow => thold_sd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sd_ck_timingdatash,
Violation => tviol_sd,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sp OR tviol_sd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, sp_ipd, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (sd_ipd'last_event, tpd_sd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1p3bx IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1p3bx";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sp : IN std_logic;
ck : IN std_logic;
sd : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1p3bx : ENTITY IS TRUE;
END fl1p3bx ;
-- architecture body --
ARCHITECTURE v OF fl1p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, pd_ipd, sd_ipd, sp_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 8) := (
-- viol pre ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '-', '1', '0' ), -- async. preset
( '-', '0', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising ck
( '-', '0', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising ck
( '-', '0', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '0', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd,
TestSignalname => "d0",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_posedge,
SetupLow => tsetup_d0_ck_noedge_posedge,
HoldHigh => thold_d0_ck_noedge_posedge,
HoldLow => thold_d0_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd='1'
AND sd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d0_ck_timingdatash,
Violation => tviol_d0,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd,
TestSignalname => "d1",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_posedge,
SetupLow => tsetup_d1_ck_noedge_posedge,
HoldHigh => thold_d1_ck_noedge_posedge,
HoldLow => thold_d1_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd='1'
AND sd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d1_ck_timingdatash,
Violation => tviol_d1,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd,
TestSignalname => "sd",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_posedge,
SetupLow => tsetup_sd_ck_noedge_posedge,
HoldHigh => thold_sd_ck_noedge_posedge,
HoldLow => thold_sd_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sd_ck_timingdatash,
Violation => tviol_sd,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd,
TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd,
Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sp OR tviol_sd OR tviol_pd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => not(set_reset), b => pd_ipd);
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, preset, sp_ipd, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (gsrnet'last_event, tpd_gsr_q, TRUE),
5 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1p3dx IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1p3dx";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sp : IN std_logic;
ck : IN std_logic;
sd : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1p3dx : ENTITY IS TRUE;
END fl1p3dx ;
-- architecture body --
ARCHITECTURE v OF fl1p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, cd_ipd, sd_ipd, sp_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 8) := (
-- viol clr ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '-', '0', '1' ), -- async. clear
( '-', '0', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising ck
( '-', '0', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising ck
( '-', '0', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '0', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd,
TestSignalname => "d0",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_posedge,
SetupLow => tsetup_d0_ck_noedge_posedge,
HoldHigh => thold_d0_ck_noedge_posedge,
HoldLow => thold_d0_ck_noedge_posedge,
CheckEnabled => (purnet='1' AND cd_ipd='0' AND sp_ipd='1'
AND sd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d0_ck_timingdatash,
Violation => tviol_d0,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd,
TestSignalname => "d1",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_posedge,
SetupLow => tsetup_d1_ck_noedge_posedge,
HoldHigh => thold_d1_ck_noedge_posedge,
HoldLow => thold_d1_ck_noedge_posedge,
CheckEnabled => (purnet='1' AND cd_ipd='0' AND sp_ipd='1'
AND sd_ipd='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => d1_ck_timingdatash,
Violation => tviol_d1,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd,
TestSignalname => "sp",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (purnet='1' AND cd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sp_ck_timingdatash,
Violation => tviol_sp,
MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd,
TestSignalname => "sd",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_posedge,
SetupLow => tsetup_sd_ck_noedge_posedge,
HoldHigh => thold_sd_ck_noedge_posedge,
HoldLow => thold_sd_ck_noedge_posedge,
CheckEnabled => (purnet='1' AND cd_ipd='0'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => sd_ck_timingdatash,
Violation => tviol_sd,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd,
TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd,
Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sp OR tviol_sd OR tviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => not(set_reset), b => cd_ipd);
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, preset, sp_ipd, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (gsrnet'last_event, tpd_gsr_q, TRUE),
5 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1p3iy -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1p3iy IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1p3iy";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_cd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_cd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sp : IN std_logic;
ck : IN std_logic;
sd : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1p3iy : ENTITY IS TRUE;
END fl1p3iy ;
-- architecture body --
ARCHITECTURE v OF fl1p3iy IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, cd_ipd, sd_ipd, sp_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 9) := (
-- viol clr scl ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '0', '1' ), -- sync. clear
( '-', '1', '0', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising ck
( '-', '1', '0', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising ck
( '-', '1', '0', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tsviol_cd : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE cd_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_posedge,
SetupLow => tsetup_d0_ck_noedge_posedge,
HoldHigh => thold_d0_ck_noedge_posedge,
HoldLow => thold_d0_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='1' AND sp_ipd='1'
AND sd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_posedge,
SetupLow => tsetup_d1_ck_noedge_posedge,
HoldHigh => thold_d1_ck_noedge_posedge,
HoldLow => thold_d1_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='1' AND sp_ipd='1'
AND sd_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalname => "cd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_cd_ck_noedge_posedge,
SetupLow => tsetup_cd_ck_noedge_posedge,
HoldHigh => thold_cd_ck_noedge_posedge,
HoldLow => thold_cd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_ck_timingdatash,
Violation => tsviol_cd, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalname => "sp",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_ck_timingdatash,
Violation => tviol_sp, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_posedge,
SetupLow => tsetup_sd_ck_noedge_posedge,
HoldHigh => thold_sd_ck_noedge_posedge,
HoldLow => thold_sd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd, TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd, Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sp OR tviol_cd OR tviol_sd OR tsviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, cd_ipd, sp_ipd, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (gsrnet'last_event, tpd_gsr_q, TRUE),
5 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1p3jy -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1p3jy IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1p3jy";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_pd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_pd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sp : IN std_logic;
ck : IN std_logic;
sd : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1p3jy : ENTITY IS TRUE;
END fl1p3jy ;
-- architecture body --
ARCHITECTURE v OF fl1p3jy IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, pd_ipd, sd_ipd, sp_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 9) := (
-- viol pre spr ce ck d q qnew qnnew
( 'X', '-', '-', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '1', '0' ), -- sync. preset
( '-', '1', '0', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising ck
( '-', '1', '0', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising ck
( '-', '1', '0', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', '-', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tsviol_pd : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE pd_ck_TimingDatash : VitalTimingDataType;
VARIABLE sp_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_posedge,
SetupLow => tsetup_d0_ck_noedge_posedge,
HoldHigh => thold_d0_ck_noedge_posedge,
HoldLow => thold_d0_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='1' AND sp_ipd='1'
AND sd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_posedge,
SetupLow => tsetup_d1_ck_noedge_posedge,
HoldHigh => thold_d1_ck_noedge_posedge,
HoldLow => thold_d1_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='1' AND sp_ipd='1'
AND sd_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_pd_ck_noedge_posedge,
SetupLow => tsetup_pd_ck_noedge_posedge,
HoldHigh => thold_pd_ck_noedge_posedge,
HoldLow => thold_pd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_ck_timingdatash,
Violation => tsviol_pd, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalname => "sp",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sp_ck_noedge_posedge,
SetupLow => tsetup_sp_ck_noedge_posedge,
HoldHigh => thold_sp_ck_noedge_posedge,
HoldLow => thold_sp_ck_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_ck_timingdatash,
Violation => tviol_sp, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_posedge,
SetupLow => tsetup_sd_ck_noedge_posedge,
HoldHigh => thold_sd_ck_noedge_posedge,
HoldLow => thold_sd_ck_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd, Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sp OR tviol_pd OR tviol_sd OR tsviol_pd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, pd_ipd, sp_ipd, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (gsrnet'last_event, tpd_gsr_q, TRUE),
5 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1s1a -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1s1a IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1s1a";
-- propagation delays
tpd_d0_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d1_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1s1a : ENTITY IS TRUE;
END fl1s1a ;
-- architecture body --
ARCHITECTURE v OF fl1s1a IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, sd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0', '1' ), -- low d->q on high ck
( '-', '1', '1', '1', '-', '1', '0' ), -- high d->q on high ck
( '-', '1', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_negedge,
SetupLow => tsetup_d0_ck_noedge_negedge,
HoldHigh => thold_d0_ck_noedge_negedge,
HoldLow => thold_d0_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_negedge,
SetupLow => tsetup_d1_ck_noedge_negedge,
HoldHigh => thold_d1_ck_noedge_negedge,
HoldLow => thold_d1_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_negedge,
SetupLow => tsetup_sd_ck_noedge_negedge,
HoldHigh => thold_sd_ck_noedge_negedge,
HoldLow => thold_sd_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, set_reset, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d0_ipd'last_event, tpd_d0_q, TRUE),
2 => (d1_ipd'last_event, tpd_d1_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (gsrnet'last_event, tpd_gsr_q, TRUE),
5 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1s1ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1s1ay IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1s1ay";
-- propagation delays
tpd_d0_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d1_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1s1ay : ENTITY IS TRUE;
END fl1s1ay ;
-- architecture body --
ARCHITECTURE v OF fl1s1ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, sd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0', '1' ), -- low d->q on high ck
( '-', '1', '1', '1', '-', '1', '0' ), -- high d->q on high ck
( '-', '1', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_negedge,
SetupLow => tsetup_d0_ck_noedge_negedge,
HoldHigh => thold_d0_ck_noedge_negedge,
HoldLow => thold_d0_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_negedge,
SetupLow => tsetup_d1_ck_noedge_negedge,
HoldHigh => thold_d1_ck_noedge_negedge,
HoldLow => thold_d1_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_negedge,
SetupLow => tsetup_sd_ck_noedge_negedge,
HoldHigh => thold_sd_ck_noedge_negedge,
HoldLow => thold_sd_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, set_reset, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d0_ipd'last_event, tpd_d0_q, TRUE),
2 => (d1_ipd'last_event, tpd_d1_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (gsrnet'last_event, tpd_gsr_q, TRUE),
5 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1s1b -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1s1b IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1s1b";
-- propagation delays
tpd_d0_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d1_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
pd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1s1b : ENTITY IS TRUE;
END fl1s1b ;
-- architecture body --
ARCHITECTURE v OF fl1s1b IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, pd_ipd, sd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '1', '0' ), -- async. preset
( '-', '0', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '0', '1', '0', '-', '0', '1' ), -- low d->q on high ck
( '-', '0', '1', '1', '-', '1', '0' ), -- high d->q on high ck
( '-', '0', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_negedge,
SetupLow => tsetup_d0_ck_noedge_negedge,
HoldHigh => thold_d0_ck_noedge_negedge,
HoldLow => thold_d0_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_negedge,
SetupLow => tsetup_d1_ck_noedge_negedge,
HoldHigh => thold_d1_ck_noedge_negedge,
HoldLow => thold_d1_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sd_ipd='1'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_negedge,
SetupLow => tsetup_sd_ck_noedge_negedge,
HoldHigh => thold_sd_ck_noedge_negedge,
HoldLow => thold_sd_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sd_ipd='1'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd, Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_pd OR tviol_sd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => not(set_reset), b => pd_ipd);
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, preset, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d0_ipd'last_event, tpd_d0_q, TRUE),
2 => (d1_ipd'last_event, tpd_d1_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (pd_ipd'last_event, tpd_pd_q, TRUE),
5 => (gsrnet'last_event, tpd_gsr_q, TRUE),
6 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1s1d -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1s1d IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1s1d";
-- propagation delays
tpd_d0_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d1_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
cd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1s1d : ENTITY IS TRUE;
END fl1s1d ;
-- architecture body --
ARCHITECTURE v OF fl1s1d IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, cd_ipd, sd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '1', '-', '-', '-', '0', '1' ), -- async. clear
( '-', '0', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '0', '1', '0', '-', '0', '1' ), -- low d->q on high ck
( '-', '0', '1', '1', '-', '1', '0' ), -- high d->q on high ck
( '-', '0', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_negedge,
SetupLow => tsetup_d0_ck_noedge_negedge,
HoldHigh => thold_d0_ck_noedge_negedge,
HoldLow => thold_d0_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_negedge,
SetupLow => tsetup_d1_ck_noedge_negedge,
HoldHigh => thold_d1_ck_noedge_negedge,
HoldLow => thold_d1_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_negedge,
SetupLow => tsetup_sd_ck_noedge_negedge,
HoldHigh => thold_sd_ck_noedge_negedge,
HoldLow => thold_sd_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd, TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd, Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sd OR tviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => not(set_reset), b => cd_ipd);
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, clear, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d0_ipd'last_event, tpd_d0_q, TRUE),
2 => (d1_ipd'last_event, tpd_d1_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (cd_ipd'last_event, tpd_cd_q, TRUE),
5 => (gsrnet'last_event, tpd_gsr_q, TRUE),
6 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1s1i -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1s1i IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1s1i";
-- propagation delays
tpd_d0_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d1_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_cd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_cd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
cd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1s1i : ENTITY IS TRUE;
END fl1s1i ;
-- architecture body --
ARCHITECTURE v OF fl1s1i IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, cd_ipd, sd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0', '1' ), -- low d->q on high ck
( '-', '1', '1', '1', '-', '1', '0' ), -- high d->q on high ck
( '-', '1', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tsviol_cd : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE cd_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synclr : std_logic := 'X';
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_negedge,
SetupLow => tsetup_d0_ck_noedge_negedge,
HoldHigh => thold_d0_ck_noedge_negedge,
HoldLow => thold_d0_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_negedge,
SetupLow => tsetup_d1_ck_noedge_negedge,
HoldHigh => thold_d1_ck_noedge_negedge,
HoldLow => thold_d1_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalname => "cd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_cd_ck_noedge_negedge,
SetupLow => tsetup_cd_ck_noedge_negedge,
HoldHigh => thold_cd_ck_noedge_negedge,
HoldLow => thold_cd_ck_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_ck_timingdatash,
Violation => tsviol_cd, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_negedge,
SetupLow => tsetup_sd_ck_noedge_negedge,
HoldHigh => thold_sd_ck_noedge_negedge,
HoldLow => thold_sd_ck_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd, TestSignalname => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
Perioddata => periodcheckinfo_cd, Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_cd OR tviol_ck OR tviol_sd OR tsviol_cd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
synclr := VitalAND2 (a => muxout, b => not(cd_ipd));
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, set_reset, ck_ipd, synclr),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d0_ipd'last_event, tpd_d0_q, TRUE),
2 => (d1_ipd'last_event, tpd_d1_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (cd_ipd'last_event, tpd_cd_q, TRUE),
5 => (gsrnet'last_event, tpd_gsr_q, TRUE),
6 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1s1j -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1s1j IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1s1j";
-- propagation delays
tpd_d0_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d1_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_pd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_pd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
pd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1s1j : ENTITY IS TRUE;
END fl1s1j ;
-- architecture body --
ARCHITECTURE v OF fl1s1j IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, pd_ipd, sd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '0', '-', '-', 'S', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0', '1' ), -- low d->q on high ck
( '-', '1', '1', '1', '-', '1', '0' ), -- high d->q on high ck
( '-', '1', '1', 'X', '-', 'X', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tsviol_pd : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE pd_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synpre : std_logic := 'X';
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_negedge,
SetupLow => tsetup_d0_ck_noedge_negedge,
HoldHigh => thold_d0_ck_noedge_negedge,
HoldLow => thold_d0_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_negedge,
SetupLow => tsetup_d1_ck_noedge_negedge,
HoldHigh => thold_d1_ck_noedge_negedge,
HoldLow => thold_d1_ck_noedge_negedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_pd_ck_noedge_negedge,
SetupLow => tsetup_pd_ck_noedge_negedge,
HoldHigh => thold_pd_ck_noedge_negedge,
HoldLow => thold_pd_ck_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_ck_timingdatash,
Violation => tsviol_pd, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_negedge,
SetupLow => tsetup_sd_ck_noedge_negedge,
HoldHigh => thold_sd_ck_noedge_negedge,
HoldLow => thold_sd_ck_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalname => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
Perioddata => periodcheckinfo_pd, Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_pd OR tviol_ck OR tsviol_pd OR tviol_sd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
synpre := VitalOR2 (a => muxout, b => pd_ipd);
VitalStateTable (StateTable => latch_table,
DataIn => (Violation, set_reset, ck_ipd, synpre),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (d0_ipd'last_event, tpd_d0_q, TRUE),
2 => (d1_ipd'last_event, tpd_d1_q, TRUE),
3 => (sd_ipd'last_event, tpd_sd_q, TRUE),
4 => (pd_ipd'last_event, tpd_pd_q, TRUE),
5 => (gsrnet'last_event, tpd_gsr_q, TRUE),
6 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1s3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1s3ax IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1s3ax";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1s3ax : ENTITY IS TRUE;
END fl1s3ax ;
-- architecture body --
ARCHITECTURE v OF fl1s3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, sd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol clr ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '0', '1' ), -- async. clear (active low)
( '-', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising ck
( '-', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising ck
( '-', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "01";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_posedge,
SetupLow => tsetup_d0_ck_noedge_posedge,
HoldHigh => thold_d0_ck_noedge_posedge,
HoldLow => thold_d0_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_posedge,
SetupLow => tsetup_d1_ck_noedge_posedge,
HoldHigh => thold_d1_ck_noedge_posedge,
HoldLow => thold_d1_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_posedge,
SetupLow => tsetup_sd_ck_noedge_posedge,
HoldHigh => thold_sd_ck_noedge_posedge,
HoldLow => thold_sd_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (gsrnet'last_event, tpd_gsr_q, TRUE),
2 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fl1s3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY fl1s3ay IS
GENERIC (
gsr : String := "ENABLED";
timingcheckson : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fl1s3ay";
-- propagation delays
tpd_ck_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sd_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns);
PORT (
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
ck : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fl1s3ay : ENTITY IS TRUE;
END fl1s3ay ;
-- architecture body --
ARCHITECTURE v OF fl1s3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := '0';
SIGNAL d1_ipd : std_logic := '0';
SIGNAL sd_ipd : std_logic := '0';
SIGNAL ck_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d0_ipd, d0, tipd_d0);
VitalWireDelay(d1_ipd, d1, tipd_d1);
VitalWireDelay(sd_ipd, sd, tipd_sd);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, sd_ipd, ck_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 6, 1 to 7) := (
-- viol pre ck d q qnew qnnew
( 'X', '-', '-', '-', '-', 'X', 'X' ), -- timing Violation
( '-', '0', '-', '-', '-', '1', '0' ), -- async. preset (active low)
( '-', '1', '/', '0', '-', '0', '1' ), -- low d->q on rising ck
( '-', '1', '/', '1', '-', '1', '0' ), -- high d->q on rising ck
( '-', '1', '/', 'X', '-', 'X', 'X' ), -- clock an x if d is x
( '-', '1', 'B', '-', '-', 'S', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_ck : X01 := '0';
VARIABLE tviol_d0 : X01 := '0';
VARIABLE tviol_d1 : X01 := '0';
VARIABLE tviol_sd : X01 := '0';
VARIABLE d0_ck_TimingDatash : VitalTimingDataType;
VARIABLE d1_ck_TimingDatash : VitalTimingDataType;
VARIABLE sd_ck_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_ck : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE Violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 2) := "10";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE muxout : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (timingcheckson) THEN
VitalSetupHoldCheck (
TestSignal => d0_ipd, TestSignalname => "d0",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d0_ck_noedge_posedge,
SetupLow => tsetup_d0_ck_noedge_posedge,
HoldHigh => thold_d0_ck_noedge_posedge,
HoldLow => thold_d0_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d0_ck_timingdatash,
Violation => tviol_d0, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => d1_ipd, TestSignalname => "d1",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_d1_ck_noedge_posedge,
SetupLow => tsetup_d1_ck_noedge_posedge,
HoldHigh => thold_d1_ck_noedge_posedge,
HoldLow => thold_d1_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d1_ck_timingdatash,
Violation => tviol_d1, MsgSeverity => Warning);
VitalSetupHoldCheck (
TestSignal => sd_ipd, TestSignalname => "sd",
RefSignal => ck_ipd, RefSignalName => "ck",
SetupHigh => tsetup_sd_ck_noedge_posedge,
SetupLow => tsetup_sd_ck_noedge_posedge,
HoldHigh => thold_sd_ck_noedge_posedge,
HoldLow => thold_sd_ck_noedge_posedge,
CheckEnabled => (set_reset='1' AND sd_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sd_ck_timingdatash,
Violation => tviol_sd, MsgSeverity => Warning);
VitalPeriodPulseCheck (
TestSignal => ck_ipd, TestSignalname => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_negedge,
Perioddata => periodcheckinfo_ck, Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => Warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
Violation := tviol_d0 OR tviol_d1 OR tviol_ck OR tviol_sd;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
muxout := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
VitalStateTable (StateTable => ff_table,
DataIn => (Violation, set_reset, ck_ipd, muxout),
Numstates => 1,
Result =>results,
PreviousDataIn => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalname => "q",
OutTemp => q_zd,
Paths => (0 => (InputChangeTime => ck_ipd'last_event,
PathDelay => tpd_ck_q,
PathCondition => TRUE),
1 => (gsrnet'last_event, tpd_gsr_q, TRUE),
2 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_IO.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
--
----- cell tsall -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY tsall IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "tsall");
PORT(
tsall : IN std_logic := 'Z');
END tsall;
-- architecture body --
ARCHITECTURE v OF tsall IS
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
-- empty
END BLOCK;
--------------------
-- behavior section
--------------------
tsallnet <= tsall;
END v;
--
----- cell bb -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY bb IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "bb";
tpd_i_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_t_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_b_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
b : INOUT std_logic;
i : IN std_logic;
t : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF bb : ENTITY IS TRUE;
END bb;
-- architecture body --
ARCHITECTURE v OF bb IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL b_ipd : std_logic := 'X';
SIGNAL i_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (t_ipd, t, tipd_t);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (b_ipd, i_ipd, t_ipd, tsallnet)
-- functionality results
VARIABLE results : std_logic_vector(1 to 2) := (others => 'X');
ALIAS b_zd : std_ulogic IS results(1);
ALIAS o_zd : std_ulogic IS results(2);
VARIABLE tri : std_logic := 'X';
VARIABLE tpd_tsall_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE b_GlitchData : VitalGlitchDataType;
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
tri := VitalOR2 (a => NOT(tsallnet), b => t_ipd);
b_zd := VitalBUFIF0 (data => i_ipd, enable => tri);
o_zd := VitalBUF(b_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01z (
OutSignal => b,
OutSignalName => "b",
OutTemp => b_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_b, TRUE),
1 => (t_ipd'last_event, tpd_t_b, TRUE),
2 => (tsallnet'last_event, tpd_tsall_b, TRUE)),
GlitchData => b_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (b_ipd'last_event, tpd_b_o, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell bbpd -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY bbpd IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "bbpd";
tpd_i_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_t_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_b_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
b : INOUT std_logic;
i : IN std_logic;
t : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF bbpd : ENTITY IS TRUE;
END bbpd;
-- architecture body --
ARCHITECTURE v OF bbpd IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL b_ipd : std_logic := 'X';
SIGNAL i_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (t_ipd, t, tipd_t);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (b_ipd, i_ipd, t_ipd, tsallnet)
-- functionality results
VARIABLE b_ipd2 : std_ulogic := 'X';
VARIABLE results : std_logic_vector(1 to 2) := (others => 'X');
ALIAS b_zd : std_ulogic IS results(1);
ALIAS o_zd : std_ulogic IS results(2);
VARIABLE tri : std_logic := 'X';
VARIABLE tpd_tsall_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE b_GlitchData : VitalGlitchDataType;
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
b_ipd2 := VitalIDENT (data => b_ipd,
resultmap => ('U','X','0','1','L'));
tri := VitalOR2 (a => NOT(tsallnet), b => t_ipd);
b_zd := VitalBUFIF0 (data => i_ipd, enable => tri,
resultmap => ('U','X','0','1','L'));
o_zd := VitalBUF(b_ipd2);
----------------------
-- path delay section
----------------------
VitalPathDelay01z (
OutSignal => b,
OutSignalName => "b",
OutTemp => b_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_b, TRUE),
1 => (t_ipd'last_event, tpd_t_b, TRUE),
2 => (tsallnet'last_event, tpd_tsall_b, TRUE)),
GlitchData => b_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (b_ipd'last_event, tpd_b_o, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell bbpu -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY bbpu IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "bbpu";
tpd_i_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_t_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_b_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
b : INOUT std_logic;
i : IN std_logic;
t : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF bbpu : ENTITY IS TRUE;
END bbpu;
-- architecture body --
ARCHITECTURE v OF bbpu IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL b_ipd : std_logic := 'X';
SIGNAL i_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (t_ipd, t, tipd_t);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (b_ipd, i_ipd, t_ipd, tsallnet)
-- functionality results
VARIABLE b_ipd2 : std_ulogic := 'X';
VARIABLE results : std_logic_vector(1 to 2) := (others => 'X');
ALIAS b_zd : std_ulogic IS results(1);
ALIAS o_zd : std_ulogic IS results(2);
VARIABLE tri : std_logic := 'X';
VARIABLE tpd_tsall_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE b_GlitchData : VitalGlitchDataType;
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
b_ipd2 := VitalIDENT (data => b_ipd,
resultmap => ('U','X','0','1','H'));
tri := VitalOR2 (a => NOT(tsallnet), b => t_ipd);
b_zd := VitalBUFIF0 (data => i_ipd, enable => tri,
resultmap => ('U','X','0','1','H'));
o_zd := VitalBUF(b_ipd2);
----------------------
-- path delay section
----------------------
VitalPathDelay01z (
OutSignal => b,
OutSignalName => "b",
OutTemp => b_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_b, TRUE),
1 => (t_ipd'last_event, tpd_t_b, TRUE),
2 => (tsallnet'last_event, tpd_tsall_b, TRUE)),
GlitchData => b_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (b_ipd'last_event, tpd_b_o, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell bbw -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY bbw IS
GENERIC(
Keepermode : boolean := FALSE;
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "bbw";
tpd_i_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_t_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_b_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
b : INOUT std_logic;
i : IN std_logic;
t : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF bbw : ENTITY IS TRUE;
END bbw;
-- architecture body --
ARCHITECTURE v OF bbw IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL b_int : std_logic := 'L';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL i_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (t_ipd, t, tipd_t);
END BLOCK;
--------------------
-- behavior section
--------------------
KEEP : PROCESS (b)
BEGIN
IF (b'event) THEN
IF (b = '1') THEN
b_int <= 'H';
ELSIF (b = '0') THEN
b_int <= 'L';
END IF;
END IF;
END PROCESS;
b <= b_int;
VitalBehavior : PROCESS (b_ipd, i_ipd, t_ipd, tsallnet)
-- functionality results
VARIABLE results : std_logic_vector(1 to 2) := (others => 'X');
ALIAS b_zd : std_ulogic IS results(1);
ALIAS o_zd : std_ulogic IS results(2);
VARIABLE tri : std_logic := 'X';
VARIABLE tpd_tsall_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE b_GlitchData : VitalGlitchDataType;
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
tri := VitalOR2 (a => NOT(tsallnet), b => t_ipd);
b_zd := VitalBUFIF0 (data => i_ipd, enable => tri);
o_zd := VitalBUF(b_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01z (
OutSignal => b,
OutSignalName => "b",
OutTemp => b_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_b, TRUE),
1 => (t_ipd'last_event, tpd_t_b, TRUE),
2 => (tsallnet'last_event, tpd_tsall_b, TRUE)),
GlitchData => b_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (b_ipd'last_event, tpd_b_o, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ib -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
ENTITY ib IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ib";
tpd_i_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
i : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ib : ENTITY IS TRUE;
END ib;
-- architecture body --
ARCHITECTURE v OF ib IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL i_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (i_ipd, i, tipd_i);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (i_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS o_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
o_zd := VitalBUF(i_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (i_ipd'last_event, (tpd_i_o), TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ibpd -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
ENTITY ibpd IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ibpd";
tpd_i_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
i : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ibpd : ENTITY IS TRUE;
END ibpd;
-- architecture body --
ARCHITECTURE v OF ibpd IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL i_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (i_ipd, i, tipd_i);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (i_ipd)
-- functionality results
VARIABLE i_ipd2 : std_ulogic := 'X';
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS o_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
i_ipd2 := VitalIDENT (data => i_ipd,
resultmap => ('U','X','0','1','L'));
o_zd := VitalBUF(i_ipd2);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (i_ipd'last_event, (tpd_i_o), TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ibpu -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
ENTITY ibpu IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ibpu";
tpd_i_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
i : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ibpu : ENTITY IS TRUE;
END ibpu;
-- architecture body --
ARCHITECTURE v OF ibpu IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL i_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (i_ipd, i, tipd_i);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (i_ipd)
-- functionality results
VARIABLE i_ipd2 : std_ulogic := 'X';
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS o_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
i_ipd2 := VitalIDENT (data => i_ipd,
resultmap => ('U','X','0','1','H'));
o_zd := VitalBUF(i_ipd2);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (i_ipd'last_event, (tpd_i_o), TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ifs1p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ifs1p3bx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ifs1p3bx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
sclk : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ifs1p3bx : ENTITY IS TRUE;
END ifs1p3bx ;
-- architecture body --
ARCHITECTURE v OF ifs1p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd: std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, sclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol pre ce sclk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '-', '1' ), -- async. preset
( '-', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of sclk
( '-', '0', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk_noedge_posedge,
SetupLow => tsetup_d_sclk_noedge_posedge,
HoldHigh => thold_d_sclk_noedge_posedge,
HoldLow => thold_d_sclk_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk_noedge_posedge,
SetupLow => tsetup_sp_sclk_noedge_posedge,
HoldHigh => thold_sp_sclk_noedge_posedge,
HoldLow => thold_sp_sclk_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk_posedge,
PulseWidthLow => tpw_sclk_negedge,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
PeriodData => periodcheckinfo_pd, Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sp or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => NOT(set_reset), b => pd_ipd);
vitalstatetable (statetable => ff_table,
datain => (violation, preset, sp_ipd, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ifs1p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ifs1p3dx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ifs1p3dx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
sclk : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ifs1p3dx : ENTITY IS TRUE;
END ifs1p3dx ;
-- architecture body --
ARCHITECTURE v OF ifs1p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, sclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol clr ce sclk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '-', '0' ), -- async. clear
( '-', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of sclk
( '-', '0', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk_noedge_posedge,
SetupLow => tsetup_d_sclk_noedge_posedge,
HoldHigh => thold_d_sclk_noedge_posedge,
HoldLow => thold_d_sclk_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sp_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk_noedge_posedge,
SetupLow => tsetup_sp_sclk_noedge_posedge,
HoldHigh => thold_sp_sclk_noedge_posedge,
HoldLow => thold_sp_sclk_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk_posedge,
PulseWidthLow => tpw_sclk_negedge,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
PeriodData => periodcheckinfo_cd, Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sp or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => NOT(set_reset), b => cd_ipd);
vitalstatetable (statetable => ff_table,
datain => (violation, clear, sp_ipd, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ifs1p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ifs1p3ix IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ifs1p3ix";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_cd_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_cd_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
sclk : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ifs1p3ix : ENTITY IS TRUE;
END ifs1p3ix ;
-- architecture body --
ARCHITECTURE v OF ifs1p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, sclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 8) := (
-- viol clr scl ce sclk d q qnew
( 'X', '-', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '-', '0' ), -- async. clear (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '0' ), -- sync. clear
( '-', '1', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '1', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '1', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of sclk
( '-', '1', '-', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tsviol_cd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE cd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk_noedge_posedge,
SetupLow => tsetup_d_sclk_noedge_posedge,
HoldHigh => thold_d_sclk_noedge_posedge,
HoldLow => thold_d_sclk_noedge_posedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sp_ipd ='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_cd_sclk_noedge_posedge,
SetupLow => tsetup_cd_sclk_noedge_posedge,
HoldHigh => thold_cd_sclk_noedge_posedge,
HoldLow => thold_cd_sclk_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_sclk_timingdatash,
Violation => tsviol_cd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk_noedge_posedge,
SetupLow => tsetup_sp_sclk_noedge_posedge,
HoldHigh => thold_sp_sclk_noedge_posedge,
HoldLow => thold_sp_sclk_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk_posedge,
PulseWidthLow => tpw_sclk_negedge,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
PeriodData => periodcheckinfo_cd, Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_cd or tviol_sp or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, cd_ipd, sp_ipd, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ifs1p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ifs1p3jx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ifs1p3jx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_pd_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_pd_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_sp_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_sp_sclk_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
sclk : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ifs1p3jx : ENTITY IS TRUE;
END ifs1p3jx ;
-- architecture body --
ARCHITECTURE v OF ifs1p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, sclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 8) := (
-- viol pre spr ce sclk d q qnew
( 'X', '-', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '-', '1' ), -- async. preset (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '1' ), -- sync. preset
( '-', '1', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '1', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '1', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of sclk
( '-', '1', '-', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tsviol_pd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE pd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk_noedge_posedge,
SetupLow => tsetup_d_sclk_noedge_posedge,
HoldHigh => thold_d_sclk_noedge_posedge,
HoldLow => thold_d_sclk_noedge_posedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd ='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_pd_sclk_noedge_posedge,
SetupLow => tsetup_pd_sclk_noedge_posedge,
HoldHigh => thold_pd_sclk_noedge_posedge,
HoldLow => thold_pd_sclk_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_sclk_timingdatash,
Violation => tsviol_pd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk_noedge_posedge,
SetupLow => tsetup_sp_sclk_noedge_posedge,
HoldHigh => thold_sp_sclk_noedge_posedge,
HoldLow => thold_sp_sclk_noedge_posedge,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk_posedge,
PulseWidthLow => tpw_sclk_negedge,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
PeriodData => periodcheckinfo_pd, Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_pd or tviol_sp or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, pd_ipd, sp_ipd, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ifs1s1b -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ifs1s1b IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ifs1s1b";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sclk : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ifs1s1b : ENTITY IS TRUE;
END ifs1s1b ;
-- architecture body --
ARCHITECTURE v OF ifs1s1b IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 6) := (
-- viol pre sclk d q qnew
( 'X', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '1' ), -- async. preset
( '-', '0', '0', '-', '-', 'S' ), -- clock low
( '-', '0', '1', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '0', '1', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '0', '1', 'X', '-', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk_noedge_negedge,
SetupLow => tsetup_d_sclk_noedge_negedge,
HoldHigh => thold_d_sclk_noedge_negedge,
HoldLow => thold_d_sclk_noedge_negedge,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk_posedge,
PulseWidthLow => tpw_sclk_negedge,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
PeriodData => periodcheckinfo_pd, Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => NOT(set_reset), b => pd_ipd);
vitalstatetable (statetable => latch_table,
datain => (violation, preset, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ifs1s1d -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ifs1s1d IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ifs1s1d";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sclk : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ifs1s1d : ENTITY IS TRUE;
END ifs1s1d ;
-- architecture body --
ARCHITECTURE v OF ifs1s1d IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 6) := (
-- viol clr sclk d q qnew
( 'X', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '0' ), -- async. clear
( '-', '0', '0', '-', '-', 'S' ), -- clock low
( '-', '0', '1', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '0', '1', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '0', '1', 'X', '-', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk_noedge_negedge,
SetupLow => tsetup_d_sclk_noedge_negedge,
HoldHigh => thold_d_sclk_noedge_negedge,
HoldLow => thold_d_sclk_noedge_negedge,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk_posedge,
PulseWidthLow => tpw_sclk_negedge,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
PeriodData => periodcheckinfo_cd, Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => NOT(set_reset), b => cd_ipd);
vitalstatetable (statetable => latch_table,
datain => (violation, clear, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ifs1s1i -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ifs1s1i IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ifs1s1i";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_cd_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
thold_cd_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_cd : VitalDelayType := 0.001 ns;
tpw_cd_posedge : VitalDelayType := 0.001 ns;
tpw_cd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sclk : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ifs1s1i : ENTITY IS TRUE;
END ifs1s1i ;
-- architecture body --
ARCHITECTURE v OF ifs1s1i IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, cd_ipd, sclk_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 6) := (
-- viol clr sclk d q qnew
( 'X', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '0' ), -- async. clear (active low)
( '-', '1', '0', '-', '-', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '1', '1', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '1', '1', 'X', '-', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tsviol_cd : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE cd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_cd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synclr : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk_noedge_negedge,
SetupLow => tsetup_d_sclk_noedge_negedge,
HoldHigh => thold_d_sclk_noedge_negedge,
HoldLow => thold_d_sclk_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_cd_sclk_noedge_negedge,
SetupLow => tsetup_cd_sclk_noedge_negedge,
HoldHigh => thold_cd_sclk_noedge_negedge,
HoldLow => thold_cd_sclk_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_sclk_timingdatash,
Violation => tsviol_cd, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk_posedge,
PulseWidthLow => tpw_sclk_negedge,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
Period => tperiod_cd,
PulseWidthHigh => tpw_cd_posedge,
PulseWidthLow => tpw_cd_negedge,
PeriodData => periodcheckinfo_cd, Violation => tviol_cd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_cd or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
synclr := VitalAND2 (a => d_ipd, b => NOT(cd_ipd));
vitalstatetable (statetable => latch_table,
datain => (violation, set_reset, sclk_ipd, synclr),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ifs1s1j -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ifs1s1j IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ifs1s1j";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_d_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
thold_d_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
tsetup_pd_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
thold_pd_sclk_noedge_negedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_pd : VitalDelayType := 0.001 ns;
tpw_pd_posedge : VitalDelayType := 0.001 ns;
tpw_pd_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sclk : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ifs1s1j : ENTITY IS TRUE;
END ifs1s1j ;
-- architecture body --
ARCHITECTURE v OF ifs1s1j IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, pd_ipd, sclk_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 6, 1 to 6) := (
-- viol pre sclk d q qnew
( 'X', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '1' ), -- async. preset (active low)
( '-', '1', '0', '-', '-', 'S' ), -- clock low
( '-', '1', '1', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '1', '1', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '1', '1', 'X', '-', 'X' ) ); -- clock an x if d is x
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tsviol_pd : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE pd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_pd : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synpre : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk_noedge_negedge,
SetupLow => tsetup_d_sclk_noedge_negedge,
HoldHigh => thold_d_sclk_noedge_negedge,
HoldLow => thold_d_sclk_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_pd_sclk_noedge_negedge,
SetupLow => tsetup_pd_sclk_noedge_negedge,
HoldHigh => thold_pd_sclk_noedge_negedge,
HoldLow => thold_pd_sclk_noedge_negedge,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_sclk_timingdatash,
Violation => tsviol_pd, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk_posedge,
PulseWidthLow => tpw_sclk_negedge,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
Period => tperiod_pd,
PulseWidthHigh => tpw_pd_posedge,
PulseWidthLow => tpw_pd_negedge,
PeriodData => periodcheckinfo_pd, Violation => tviol_pd,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_pd or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
synpre := VitalOR2 (a => d_ipd, b => pd_ipd);
vitalstatetable (statetable => latch_table,
datain => (violation, set_reset, sclk_ipd, synpre),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (d_ipd'last_event, tpd_d_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- ilf2p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ilf2p3bx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ilf2p3bx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns;
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
eclk : IN std_logic;
sclk : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ilf2p3bx : ENTITY IS TRUE;
END ilf2p3bx ;
-- architecture body --
ARCHITECTURE v OF ilf2p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, sclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 5, 1 to 5) := (
-- viol ck d q qnew
( 'X', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', 'S' ), -- clock low
( '-', '0', '0', '-', '0' ), -- low d->q on rising edge ck
( '-', '0', '1', '-', '1' ), -- high d->q on rising edge ck
( '-', '0', 'X', '-', 'X' ) ); -- clock an x if d is x
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol pre ce clk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '-', '1' ), -- async. preset
( '-', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge clk
( '-', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge clk
( '-', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of ck
( '-', '0', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata1 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE prevdata2 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE latched : std_logic_vector (1 to 1) := "1";
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sp or tviol_eclk or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => NOT(set_reset), b => pd_ipd);
vitalstatetable (statetable => latch_table,
datain => (violation, eclk_ipd, d_ipd),
numstates => 1,
result => latched,
previousdatain => prevdata1);
vitalstatetable (statetable => ff_table,
datain => (violation, preset, sp_ipd, sclk_ipd, latched(1)),
numstates => 1,
result => results,
previousdatain => prevdata2);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- ilf2p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ilf2p3dx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ilf2p3dx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns;
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
eclk : IN std_logic;
sclk : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ilf2p3dx : ENTITY IS TRUE;
END ilf2p3dx ;
-- architecture body --
ARCHITECTURE v OF ilf2p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, sclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 5, 1 to 5) := (
-- viol ck d q qnew
( 'X', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', 'S' ), -- clock high
( '-', '0', '0', '-', '0' ), -- low d->q on falling edge ck
( '-', '0', '1', '-', '1' ), -- high d->q on falling edge ck
( '-', '0', 'X', '-', 'X' ) ); -- clock an x if d is x
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol clr ce clk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '-', '0' ), -- async. clear
( '-', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge clk
( '-', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge clk
( '-', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of ck
( '-', '0', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata1 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE prevdata2 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE latched : std_logic_vector (1 to 1) := "0";
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '\', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sp or tviol_eclk or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => NOT(set_reset), b => cd_ipd);
vitalstatetable (statetable => latch_table,
datain => (violation, eclk_ipd, d_ipd),
numstates => 1,
result => latched,
previousdatain => prevdata1);
vitalstatetable (statetable => ff_table,
datain => (violation, clear, sp_ipd, sclk_ipd, latched(1)),
numstates => 1,
result => results,
previousdatain => prevdata2);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- ilf2p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ilf2p3ix IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ilf2p3ix";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_cd_sclk : VitalDelayType := 0.0 ns;
thold_sclk_cd : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns;
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
eclk : IN std_logic;
sclk : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ilf2p3ix : ENTITY IS TRUE;
END ilf2p3ix ;
-- architecture body --
ARCHITECTURE v OF ilf2p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, sclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 5, 1 to 5) := (
-- viol ck d q qnew
( 'X', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', 'S' ), -- clock high
( '-', '0', '0', '-', '0' ), -- low d->q on falling edge ck
( '-', '0', '1', '-', '1' ), -- high d->q on falling edge ck
( '-', '0', 'X', '-', 'X' ) ); -- clock an x if d is x
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 8) := (
-- viol clr scl ce clk d q qnew
( 'X', '-', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '-', '0' ), -- async. clear (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '0' ), -- sync. clear
( '-', '1', '-', '1', '/', '0', '-', '0' ), -- low d->q on rising edge clk
( '-', '1', '-', '1', '/', '1', '-', '1' ), -- high d->q on rising edge clk
( '-', '1', '-', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE cd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata1 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE prevdata2 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE latched : std_logic_vector (1 to 1) := "0";
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synclr : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_cd_sclk, SetupLow => tsetup_cd_sclk,
HoldHigh => thold_sclk_cd, HoldLow => thold_sclk_cd,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_sclk_timingdatash,
Violation => tviol_cd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_cd or tviol_sp or tviol_eclk or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => latch_table,
datain => (violation, eclk_ipd, d_ipd),
numstates => 1,
result => latched,
previousdatain => prevdata1);
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, cd_ipd, sp_ipd, sclk_ipd, latched(1)),
numstates => 1,
result => results,
previousdatain => prevdata2);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- ilf2p3iz -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ilf2p3iz IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ilf2p3iz";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_cd_sclk : VitalDelayType := 0.0 ns;
thold_sclk_cd : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns;
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
eclk : IN std_logic;
sclk : IN std_logic;
cd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ilf2p3iz : ENTITY IS TRUE;
END ilf2p3iz ;
-- architecture body --
ARCHITECTURE v OF ilf2p3iz IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, sclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 5, 1 to 5) := (
-- viol ck d q qnew
( 'X', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', 'S' ), -- clock high
( '-', '0', '0', '-', '0' ), -- low d->q on faling edge ck
( '-', '0', '1', '-', '1' ), -- high d->q on faling edge ck
( '-', '0', 'X', '-', 'X' ) ); -- clock an x if d is x
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol clr ce clk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '0' ), -- async. clear (active low)
( '-', '1', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '/', '0', '-', '0' ), -- low d->q on rising edge clk
( '-', '1', '1', '/', '1', '-', '1' ), -- high d->q on rising edge clk
( '-', '1', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE cd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata1 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE prevdata2 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE latched : std_logic_vector (1 to 1) := "0";
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synclr1 : std_logic := 'X';
VARIABLE synclr2 : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_cd_sclk, SetupLow => tsetup_cd_sclk,
HoldHigh => thold_sclk_cd, HoldLow => thold_sclk_cd,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_sclk_timingdatash,
Violation => tviol_cd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_cd or tviol_sp or tviol_eclk or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => latch_table,
datain => (violation, eclk_ipd, d_ipd),
numstates => 1,
result => latched,
previousdatain => prevdata1);
synclr2 := VitalAND2 (a => latched(1), b => NOT(cd_ipd));
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, sp_ipd, sclk_ipd, synclr2),
numstates => 1,
result => results,
previousdatain => prevdata2);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- ilf2p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ilf2p3jx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ilf2p3jx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_pd_sclk : VitalDelayType := 0.0 ns;
thold_sclk_pd : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns;
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
eclk : IN std_logic;
sclk : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ilf2p3jx : ENTITY IS TRUE;
END ilf2p3jx ;
-- architecture body --
ARCHITECTURE v OF ilf2p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, sclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 5, 1 to 5) := (
-- viol ck d q qnew
( 'X', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', 'S' ), -- clock high
( '-', '0', '0', '-', '0' ), -- low d->q on falling edge ck
( '-', '0', '1', '-', '1' ), -- high d->q on falling edge ck
( '-', '0', 'X', '-', 'X' ) ); -- clock an x if d is x
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 8) := (
-- viol pre spr ce clk d q qnew
( 'X', '-', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '-', '1' ), -- async. preset (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '1' ), -- sync. preset
( '-', '1', '-', '1', '/', '0', '-', '0' ), -- low d->q on rising edge clk
( '-', '1', '-', '1', '/', '1', '-', '1' ), -- high d->q on rising edge clk
( '-', '1', '-', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE pd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata1 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE prevdata2 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE latched : std_logic_vector (1 to 1) := "1";
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synpre : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_pd_sclk, SetupLow => tsetup_pd_sclk,
HoldHigh => thold_sclk_pd, HoldLow => thold_sclk_pd,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_sclk_timingdatash,
Violation => tviol_pd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_pd or tviol_sp or tviol_eclk or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => latch_table,
datain => (violation, eclk_ipd, d_ipd),
numstates => 1,
result => latched,
previousdatain => prevdata1);
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, pd_ipd, sp_ipd, sclk_ipd, latched(1)),
numstates => 1,
result => results,
previousdatain => prevdata2);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- ilf2p3jz -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ilf2p3jz IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ilf2p3jz";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_pd_sclk : VitalDelayType := 0.0 ns;
thold_sclk_pd : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns;
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
eclk : IN std_logic;
sclk : IN std_logic;
pd : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ilf2p3jz : ENTITY IS TRUE;
END ilf2p3jz ;
-- architecture body --
ARCHITECTURE v OF ilf2p3jz IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, sclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT latch_table : VitalStateTableType (1 to 5, 1 to 5) := (
-- viol ck d q qnew
( 'X', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', 'S' ), -- clock high
( '-', '0', '0', '-', '0' ), -- low d->q on falling edge ck
( '-', '0', '1', '-', '1' ), -- high d->q on falling edge ck
( '-', '0', 'X', '-', 'X' ) ); -- clock an x if d is x
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol pre ce clk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '1' ), -- async. preset (active low)
( '-', '1', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '/', '0', '-', '0' ), -- low d->q on rising edge clk
( '-', '1', '1', '/', '1', '-', '1' ), -- high d->q on rising edge clk
( '-', '1', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of ck
( '-', '1', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE pd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata1 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE prevdata2 : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE latched : std_logic_vector (1 to 1) := "1";
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE synpre1 : std_logic := 'X';
VARIABLE synpre2 : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1'), RefTransition => '\',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_pd_sclk, SetupLow => tsetup_pd_sclk,
HoldHigh => thold_sclk_pd, HoldLow => thold_sclk_pd,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_sclk_timingdatash,
Violation => tviol_pd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_pd or tviol_sp or tviol_eclk or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => latch_table,
datain => (violation, eclk_ipd, d_ipd),
numstates => 1,
result => latched,
previousdatain => prevdata1);
synpre2 := VitalOR2 (a => latched(1), b => pd_ipd);
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, sp_ipd, sclk_ipd, synpre2),
numstates => 1,
result => results,
previousdatain => prevdata2);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ob -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY ob IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ob";
tpd_i_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
i : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ob : ENTITY IS TRUE;
END ob;
-- architecture body --
ARCHITECTURE v OF ob IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL i_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (i_ipd, i, tipd_i);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (i_ipd, tsallnet)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS o_zd : std_ulogic IS results(1);
VARIABLE tpd_tsall_o : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
o_zd := VitalBUFIF1 (data => i_ipd, enable => tsallnet);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (tsallnet'last_event, tpd_tsall_o, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell obz -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY obz IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "obz";
tpd_i_o : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_t_o : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
i : IN std_logic;
t : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF obz : ENTITY IS TRUE;
END obz;
-- architecture body --
ARCHITECTURE v OF obz IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL i_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (t_ipd, t, tipd_t);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (i_ipd, t_ipd, tsallnet)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS o_zd : std_ulogic IS results(1);
VARIABLE tri : std_logic := 'X';
VARIABLE tpd_tsall_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
tri := VitalOR2 (a => NOT(tsallnet), b => t_ipd);
o_zd := VitalBUFIF0 (data => i_ipd, enable => tri);
----------------------
-- path delay section
----------------------
VitalPathDelay01z (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (t_ipd'last_event, tpd_t_o, TRUE),
2 => (tsallnet'last_event, tpd_tsall_b, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell obzpd -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY obzpd IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "obzpd";
tpd_i_o : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_t_o : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
i : IN std_logic;
t : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF obzpd : ENTITY IS TRUE;
END obzpd;
-- architecture body --
ARCHITECTURE v OF obzpd IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL i_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (t_ipd, t, tipd_t);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (i_ipd, t_ipd, tsallnet)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS o_zd : std_ulogic IS results(1);
VARIABLE tri : std_logic := 'X';
VARIABLE tpd_tsall_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
tri := VitalOR2 (a => NOT(tsallnet), b => t_ipd);
o_zd := VitalBUFIF0 (data => i_ipd, enable => tri,
resultmap => ('U','X','0','1','L'));
----------------------
-- path delay section
----------------------
VitalPathDelay01z (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (t_ipd'last_event, tpd_t_o, TRUE),
2 => (tsallnet'last_event, tpd_tsall_b, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell obzpu -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY obzpu IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "obzpu";
tpd_i_o : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_t_o : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
i : IN std_logic;
t : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF obzpu : ENTITY IS TRUE;
END obzpu;
-- architecture body --
ARCHITECTURE v OF obzpu IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL i_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (t_ipd, t, tipd_t);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (i_ipd, t_ipd, tsallnet)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS o_zd : std_ulogic IS results(1);
VARIABLE tri : std_logic := 'X';
VARIABLE tpd_tsall_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
tri := VitalOR2 (a => NOT(tsallnet), b => t_ipd);
o_zd := VitalBUFIF0 (data => i_ipd, enable => tri,
resultmap => ('U','X','0','1','H'));
----------------------
-- path delay section
----------------------
VitalPathDelay01z (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (t_ipd'last_event, tpd_t_o, TRUE),
2 => (tsallnet'last_event, tpd_tsall_b, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell obw -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.tsallnet;
-- entity declaration --
ENTITY obw IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "obw";
tpd_i_o : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tpd_t_o : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
i : IN std_logic;
t : IN std_logic;
o : OUT std_logic);
ATTRIBUTE Vital_Level0 OF obw : ENTITY IS TRUE;
END obw;
-- architecture body --
ARCHITECTURE v OF obw IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL o_int : std_logic := 'X';
SIGNAL b_int : std_logic := 'L';
SIGNAL i_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (t_ipd, t, tipd_t);
END BLOCK;
--------------------
-- behavior section
--------------------
KEEP : PROCESS (o_int)
BEGIN
IF (o_int'event) THEN
IF (o_int = '1') THEN
b_int <= 'H';
ELSIF (o_int = '0') THEN
b_int <= 'L';
END IF;
END IF;
END PROCESS;
o_int <= b_int;
VitalBehavior : PROCESS (i_ipd, t_ipd, tsallnet, o_int)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS o_zd : std_ulogic IS results(1);
VARIABLE tri : std_logic := 'X';
VARIABLE tpd_tsall_b : VitalDelayType01z :=
(0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE o_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
tri := VitalOR2 (a => NOT(tsallnet), b => t_ipd);
o_int <= VitalBUFIF0 (data => i_ipd, enable => tri);
o_zd := o_int;
----------------------
-- path delay section
----------------------
VitalPathDelay01z (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_zd,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (t_ipd'last_event, tpd_t_o, TRUE),
2 => (tsallnet'last_event, tpd_tsall_b, TRUE)),
GlitchData => o_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
-----cell ofs1p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ofs1p3bx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ofs1p3bx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk : VitalDelayType := 0.0 ns;
thold_sclk_d : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
pd : IN std_logic;
sclk : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ofs1p3bx : ENTITY IS TRUE;
END ofs1p3bx ;
-- architecture body --
ARCHITECTURE v OF ofs1p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, sclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol pre ce sclk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '-', '1' ), -- async. preset
( '-', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of sclk
( '-', '0', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk, SetupLow => tsetup_d_sclk,
HoldHigh => thold_sclk_d, HoldLow => thold_sclk_d,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sp or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => NOT(set_reset), b => pd_ipd);
vitalstatetable (statetable => ff_table,
datain => (violation, preset, sp_ipd, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ofs1p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ofs1p3dx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ofs1p3dx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk : VitalDelayType := 0.0 ns;
thold_sclk_d : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
cd : IN std_logic;
sclk : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ofs1p3dx : ENTITY IS TRUE;
END ofs1p3dx ;
-- architecture body --
ARCHITECTURE v OF ofs1p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, sclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol clr ce sclk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '-', '0' ), -- async. clear
( '-', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of sclk
( '-', '0', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk, SetupLow => tsetup_d_sclk,
HoldHigh => thold_sclk_d, HoldLow => thold_sclk_d,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sp_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sp or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => NOT(set_reset), b => cd_ipd);
vitalstatetable (statetable => ff_table,
datain => (violation, clear, sp_ipd, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ofs1p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ofs1p3ix IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ofs1p3ix";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk : VitalDelayType := 0.0 ns;
thold_sclk_d : VitalDelayType := 0.0 ns;
tsetup_cd_sclk : VitalDelayType := 0.0 ns;
thold_sclk_cd : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
cd : IN std_logic;
sclk : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ofs1p3ix : ENTITY IS TRUE;
END ofs1p3ix ;
-- architecture body --
ARCHITECTURE v OF ofs1p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, sclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 8) := (
-- viol clr scl ce sclk d q qnew
( 'X', '-', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '-', '0' ), -- async. clear (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '0' ), -- sync. clear
( '-', '1', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '1', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '1', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of sclk
( '-', '1', '-', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g.falling) preserve q
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE cd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk, SetupLow => tsetup_d_sclk,
HoldHigh => thold_sclk_d, HoldLow => thold_sclk_d,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sp_ipd ='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_cd_sclk, SetupLow => tsetup_cd_sclk,
HoldHigh => thold_sclk_cd, HoldLow => thold_sclk_cd,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_sclk_timingdatash,
Violation => tviol_cd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_cd or tviol_sp or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, cd_ipd, sp_ipd, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ofs1p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ofs1p3jx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ofs1p3jx";
-- propagation delays
tpd_sclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_sclk : VitalDelayType := 0.0 ns;
thold_sclk_d : VitalDelayType := 0.0 ns;
tsetup_pd_sclk : VitalDelayType := 0.0 ns;
thold_sclk_pd : VitalDelayType := 0.0 ns;
tsetup_sp_sclk : VitalDelayType := 0.0 ns;
thold_sclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
pd : IN std_logic;
sclk : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ofs1p3jx : ENTITY IS TRUE;
END ofs1p3jx ;
-- architecture body --
ARCHITECTURE v OF ofs1p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, sclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 8) := (
-- viol pre spr ce sclk d q qnew
( 'X', '-', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '-', '1' ), -- async. preset (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '1' ), -- sync. preset
( '-', '1', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge sclk
( '-', '1', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge sclk
( '-', '1', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of sclk
( '-', '1', '-', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_sclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_sclk_TimingDatash : VitalTimingDataType;
VARIABLE pd_sclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_sclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_d_sclk, SetupLow => tsetup_d_sclk,
HoldHigh => thold_sclk_d, HoldLow => thold_sclk_d,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd ='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_sclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_pd_sclk, SetupLow => tsetup_pd_sclk,
HoldHigh => thold_sclk_pd, HoldLow => thold_sclk_pd,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_sclk_timingdatash,
Violation => tviol_pd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => sclk_ipd, RefSignalName => "sclk",
SetupHigh => tsetup_sp_sclk, SetupLow => tsetup_sp_sclk,
HoldHigh => thold_sclk_sp, HoldLow => thold_sclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_sclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => sclk_ipd, TestSignalName => "sclk",
Period => tperiod_sclk,
PulseWidthHigh => tpw_sclk,
PulseWidthLow => tpw_sclk,
PeriodData => periodcheckinfo_sclk, Violation => tviol_sclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_pd or tviol_sp or tviol_sclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, pd_ipd, sp_ipd, sclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ofe1p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ofe1p3bx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ofe1p3bx";
-- propagation delays
tpd_eclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_pd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_sp_eclk : VitalDelayType := 0.0 ns;
thold_eclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
pd : IN std_logic;
eclk : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ofe1p3bx : ENTITY IS TRUE;
END ofe1p3bx ;
-- architecture body --
ARCHITECTURE v OF ofe1p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol pre ce eclk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '-', '1' ), -- async. preset
( '-', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge eclk
( '-', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge eclk
( '-', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of eclk
( '-', '0', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_eclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE preset : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_sp_eclk, SetupLow => tsetup_sp_eclk,
HoldHigh => thold_eclk_sp, HoldLow => thold_eclk_sp,
CheckEnabled => (set_reset='1' AND pd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_eclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sp or tviol_eclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
preset := VitalOR2 (a => NOT(set_reset), b => pd_ipd);
vitalstatetable (statetable => ff_table,
datain => (violation, preset, sp_ipd, eclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => eclk_ipd'last_event,
pathdelay => tpd_eclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (pd_ipd'last_event, tpd_pd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ofe1p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ofe1p3dx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ofe1p3dx";
-- propagation delays
tpd_eclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_cd_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_sp_eclk : VitalDelayType := 0.0 ns;
thold_eclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
cd : IN std_logic;
eclk : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ofe1p3dx : ENTITY IS TRUE;
END ofe1p3dx ;
-- architecture body --
ARCHITECTURE v OF ofe1p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 8, 1 to 7) := (
-- viol clr ce eclk d q qnew
( 'X', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '1', '-', '-', '-', '-', '0' ), -- async. clear
( '-', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge eclk
( '-', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge eclk
( '-', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of eclk
( '-', '0', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_eclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE clear : std_logic := 'X';
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sp_ipd='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_sp_eclk, SetupLow => tsetup_sp_eclk,
HoldHigh => thold_eclk_sp, HoldLow => thold_eclk_sp,
CheckEnabled => (set_reset='1' AND cd_ipd='0'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_eclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_sp or tviol_eclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
clear := VitalOR2 (a => NOT(set_reset), b => cd_ipd);
vitalstatetable (statetable => ff_table,
datain => (violation, clear, sp_ipd, eclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => eclk_ipd'last_event,
pathdelay => tpd_eclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (cd_ipd'last_event, tpd_cd_q, TRUE),
3 => (gsrnet'last_event, tpd_gsr_q, TRUE),
4 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ofe1p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ofe1p3ix IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ofe1p3ix";
-- propagation delays
tpd_eclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_cd_eclk : VitalDelayType := 0.0 ns;
thold_eclk_cd : VitalDelayType := 0.0 ns;
tsetup_sp_eclk : VitalDelayType := 0.0 ns;
thold_eclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
cd : IN std_logic;
eclk : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ofe1p3ix : ENTITY IS TRUE;
END ofe1p3ix ;
-- architecture body --
ARCHITECTURE v OF ofe1p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL cd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(cd_ipd, cd, tipd_cd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, cd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 8) := (
-- viol clr scl ce eclk d q qnew
( 'X', '-', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '-', '0' ), -- async. clear (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '0' ), -- sync. clear
( '-', '1', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge eclk
( '-', '1', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge eclk
( '-', '1', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of eclk
( '-', '1', '-', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_cd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE cd_eclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_eclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "0";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1' AND cd_ipd='0' AND sp_ipd ='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => cd_ipd, TestSignalName => "cd",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_cd_eclk, SetupLow => tsetup_cd_eclk,
HoldHigh => thold_eclk_cd, HoldLow => thold_eclk_cd,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => cd_eclk_timingdatash,
Violation => tviol_cd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_sp_eclk, SetupLow => tsetup_sp_eclk,
HoldHigh => thold_eclk_sp, HoldLow => thold_eclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_eclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_cd or tviol_sp or tviol_eclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, cd_ipd, sp_ipd, eclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => eclk_ipd'last_event,
pathdelay => tpd_eclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ofe1p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.global.gsrnet;
USE work.global.purnet;
ENTITY ofe1p3jx IS
GENERIC (
gsr : String := "ENABLED";
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "ofe1p3jx";
-- propagation delays
tpd_eclk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sp_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk : VitalDelayType := 0.0 ns;
thold_eclk_d : VitalDelayType := 0.0 ns;
tsetup_pd_eclk : VitalDelayType := 0.0 ns;
thold_eclk_pd : VitalDelayType := 0.0 ns;
tsetup_sp_eclk : VitalDelayType := 0.0 ns;
thold_eclk_sp : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sp : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_pd : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
sp : IN std_logic;
pd : IN std_logic;
eclk : IN std_logic;
q : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ofe1p3jx : ENTITY IS TRUE;
END ofe1p3jx ;
-- architecture body --
ARCHITECTURE v OF ofe1p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sp_ipd : std_logic := '0';
SIGNAL pd_ipd : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(eclk_ipd, eclk , tipd_eclk);
VitalWireDelay(sp_ipd, sp, tipd_sp);
VitalWireDelay(pd_ipd, pd, tipd_pd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d_ipd, sp_ipd, eclk_ipd, pd_ipd, gsrnet, purnet)
CONSTANT ff_table : VitalStateTableType (1 to 9, 1 to 8) := (
-- viol pre spr ce eclk d q qnew
( 'X', '-', '-', '-', '-', '-', '-', 'X' ), -- timing violation
( '-', '0', '-', '-', '-', '-', '-', '1' ), -- async. preset (active low)
( '-', '1', '0', '0', '-', '-', '-', 'S' ), -- clock disabled
( '-', '1', '1', '-', '/', '-', '-', '1' ), -- sync. preset
( '-', '1', '0', '1', '/', '0', '-', '0' ), -- low d->q on rising edge eclk
( '-', '1', '0', '1', '/', '1', '-', '1' ), -- high d->q on rising edge eclk
( '-', '1', '0', '1', '/', 'X', '-', 'X' ), -- clock an x if d is x
( '-', '1', '0', 'X', '/', '-', '-', 'X' ), -- ce is x on rising edge of eclk
( '-', '1', '-', '-', 'B', '-', '-', 'S' ) ); -- non-x clock (e.g. falling) preserve q
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_pd : X01 := '0';
VARIABLE tviol_sp : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE pd_eclk_TimingDatash : VitalTimingDataType;
VARIABLE sp_eclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
-- functionality results
VARIABLE set_reset : std_logic := '1';
VARIABLE violation : X01 := '0';
VARIABLE prevdata : std_logic_vector (0 to 5) := (others=>'X');
VARIABLE results : std_logic_vector (1 to 1) := "1";
ALIAS q_zd : std_ulogic IS results(1);
VARIABLE tpd_gsr_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
VARIABLE tpd_pur_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk, SetupLow => tsetup_d_eclk,
HoldHigh => thold_eclk_d, HoldLow => thold_eclk_d,
CheckEnabled => (set_reset='1' AND pd_ipd='0' AND sp_ipd ='1'),
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => pd_ipd, TestSignalName => "pd",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_pd_eclk, SetupLow => tsetup_pd_eclk,
HoldHigh => thold_eclk_pd, HoldLow => thold_eclk_pd,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => pd_eclk_timingdatash,
Violation => tviol_pd, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => sp_ipd, TestSignalName => "sp",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_sp_eclk, SetupLow => tsetup_sp_eclk,
HoldHigh => thold_eclk_sp, HoldLow => thold_eclk_sp,
CheckEnabled => (set_reset='1'), RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => sp_eclk_timingdatash,
Violation => tviol_sp, MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => eclk_ipd, TestSignalName => "eclk",
Period => tperiod_eclk,
PulseWidthHigh => tpw_eclk,
PulseWidthLow => tpw_eclk,
PeriodData => periodcheckinfo_eclk, Violation => tviol_eclk,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
violation := tviol_d or tviol_pd or tviol_sp or tviol_eclk;
IF (gsr = "DISABLED") THEN
set_reset := purnet;
ELSE
set_reset := purnet AND gsrnet;
END IF;
vitalstatetable (statetable => ff_table,
datain => (violation, set_reset, pd_ipd, sp_ipd, eclk_ipd, d_ipd),
numstates => 1,
result => results,
previousdatain => prevdata);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => eclk_ipd'last_event,
pathdelay => tpd_eclk_q,
pathcondition => TRUE),
1 => (sp_ipd'last_event, tpd_sp_q, TRUE),
2 => (gsrnet'last_event, tpd_gsr_q, TRUE),
3 => (purnet'last_event, tpd_pur_q, TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell ilvds -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
ENTITY ilvds IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ilvds";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_an_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_an : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
an : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ilvds : ENTITY IS TRUE;
END ilvds;
-- architecture body --
ARCHITECTURE v OF ilvds IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL an_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (an_ipd, an, tipd_an);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := VitalBUF(a_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, (tpd_a_z), TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell olvds -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
ENTITY olvds IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "olvds";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a_zn : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
z : OUT std_logic;
zn : OUT std_logic);
ATTRIBUTE Vital_Level0 OF olvds : ENTITY IS TRUE;
END olvds;
-- architecture body --
ARCHITECTURE v OF olvds IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 2) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
ALIAS zn_zd : std_ulogic IS results(2);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
VARIABLE zn_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := VitalBUF(a_ipd);
zn_zd := VitalINV(a_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, (tpd_a_z), TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => zn,
OutSignalName => "zn",
OutTemp => zn_zd,
Paths => (0 => (a_ipd'last_event, (tpd_a_zn), TRUE)),
GlitchData => zn_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_LUT.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
----- CELL ORCALUT4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity ORCALUT4 is
generic(
TimingChecksOn: Boolean := TRUE;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := False;
tpd_A_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_C_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_D_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
INIT : bit_vector);
port(
Z : out STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC);
attribute VITAL_LEVEL0 of ORCALUT4 : entity is TRUE;
end ORCALUT4;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture V of ORCALUT4 is
attribute VITAL_LEVEL1 of V : architecture is TRUE;
SIGNAL A_ipd : STD_ULOGIC := 'X';
SIGNAL B_ipd : STD_ULOGIC := 'X';
SIGNAL C_ipd : STD_ULOGIC := 'X';
SIGNAL D_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (C_ipd, C, tipd_C);
VitalWireDelay (D_ipd, D, tipd_D);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Z_zd : STD_LOGIC is Results(1);
-- output glitch detection variables
VARIABLE Z_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Z_zd := VitalMUX
(data => To_StdLogicVector(INIT),
dselect => (D_ipd, C_ipd, B_ipd, A_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Z,
GlitchData => Z_GlitchData,
OutSignalName => "Z",
OutTemp => Z_zd,
Paths => (0 => (A_ipd'last_event, tpd_A_Z, TRUE),
1 => (B_ipd'last_event, tpd_B_Z, TRUE),
2 => (C_ipd'last_event, tpd_C_Z, TRUE),
3 => (D_ipd'last_event, tpd_D_Z, TRUE)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end V;
configuration CFG_ORCALUT4_V of ORCALUT4 is
for V
end for;
end CFG_ORCALUT4_V;
----- CELL ORCALUT5 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity ORCALUT5 is
generic(
TimingChecksOn: Boolean := TRUE;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := False;
tpd_A_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_C_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_D_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_E_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
INIT : bit_vector);
port(
Z : out STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC);
attribute VITAL_LEVEL0 of ORCALUT5 : entity is TRUE;
end ORCALUT5;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture V of ORCALUT5 is
attribute VITAL_LEVEL1 of V : architecture is TRUE;
SIGNAL A_ipd : STD_ULOGIC := 'X';
SIGNAL B_ipd : STD_ULOGIC := 'X';
SIGNAL C_ipd : STD_ULOGIC := 'X';
SIGNAL D_ipd : STD_ULOGIC := 'X';
SIGNAL E_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (C_ipd, C, tipd_C);
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (E_ipd, E, tipd_E);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Z_zd : STD_LOGIC is Results(1);
-- output glitch detection variables
VARIABLE Z_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Z_zd := VitalMUX
(data => To_StdLogicVector(INIT),
dselect => (E_ipd, D_ipd, C_ipd, B_ipd, A_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Z,
GlitchData => Z_GlitchData,
OutSignalName => "Z",
OutTemp => Z_zd,
Paths => (0 => (A_ipd'last_event, tpd_A_Z, TRUE),
1 => (B_ipd'last_event, tpd_B_Z, TRUE),
2 => (C_ipd'last_event, tpd_C_Z, TRUE),
3 => (D_ipd'last_event, tpd_D_Z, TRUE),
4 => (E_ipd'last_event, tpd_E_Z, TRUE)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end V;
configuration CFG_ORCALUT5_V of ORCALUT5 is
for V
end for;
end CFG_ORCALUT5_V;
----- CELL ORCALUT6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity ORCALUT6 is
generic(
TimingChecksOn: Boolean := TRUE;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := False;
tpd_A_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_C_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_D_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_E_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_F_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_F : VitalDelayType01 := (0.000 ns, 0.000 ns);
INIT : bit_vector);
port(
Z : out STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC);
attribute VITAL_LEVEL0 of ORCALUT6 : entity is TRUE;
end ORCALUT6;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture V of ORCALUT6 is
attribute VITAL_LEVEL1 of V : architecture is TRUE;
SIGNAL A_ipd : STD_ULOGIC := 'X';
SIGNAL B_ipd : STD_ULOGIC := 'X';
SIGNAL C_ipd : STD_ULOGIC := 'X';
SIGNAL D_ipd : STD_ULOGIC := 'X';
SIGNAL E_ipd : STD_ULOGIC := 'X';
SIGNAL F_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (C_ipd, C, tipd_C);
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (E_ipd, E, tipd_E);
VitalWireDelay (F_ipd, F, tipd_F);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd, F_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Z_zd : STD_LOGIC is Results(1);
-- output glitch detection variables
VARIABLE Z_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Z_zd := VitalMUX
(data => To_StdLogicVector(INIT),
dselect => (F_ipd, E_ipd, D_ipd, C_ipd, B_ipd, A_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Z,
GlitchData => Z_GlitchData,
OutSignalName => "Z",
OutTemp => Z_zd,
Paths => (0 => (A_ipd'last_event, tpd_A_Z, TRUE),
1 => (B_ipd'last_event, tpd_B_Z, TRUE),
2 => (C_ipd'last_event, tpd_C_Z, TRUE),
3 => (D_ipd'last_event, tpd_D_Z, TRUE),
4 => (E_ipd'last_event, tpd_E_Z, TRUE),
5 => (F_ipd'last_event, tpd_F_Z, TRUE)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end V;
configuration CFG_ORCALUT6_V of ORCALUT6 is
for V
end for;
end CFG_ORCALUT6_V;
----- CELL ORCALUT7 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity ORCALUT7 is
generic(
TimingChecksOn: Boolean := TRUE;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := False;
tpd_A_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_C_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_D_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_E_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_F_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_G_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_F : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
INIT : bit_vector);
port(
Z : out STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
G : in STD_ULOGIC);
attribute VITAL_LEVEL0 of ORCALUT7 : entity is TRUE;
end ORCALUT7;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture V of ORCALUT7 is
attribute VITAL_LEVEL1 of V : architecture is TRUE;
SIGNAL A_ipd : STD_ULOGIC := 'X';
SIGNAL B_ipd : STD_ULOGIC := 'X';
SIGNAL C_ipd : STD_ULOGIC := 'X';
SIGNAL D_ipd : STD_ULOGIC := 'X';
SIGNAL E_ipd : STD_ULOGIC := 'X';
SIGNAL F_ipd : STD_ULOGIC := 'X';
SIGNAL G_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (C_ipd, C, tipd_C);
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (E_ipd, E, tipd_E);
VitalWireDelay (F_ipd, F, tipd_F);
VitalWireDelay (G_ipd, G, tipd_G);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd, F_ipd, G_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Z_zd : STD_LOGIC is Results(1);
-- output glitch detection variables
VARIABLE Z_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Z_zd := VitalMUX
(data => To_StdLogicVector(INIT),
dselect => (G_ipd, F_ipd, E_ipd, D_ipd, C_ipd, B_ipd, A_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Z,
GlitchData => Z_GlitchData,
OutSignalName => "Z",
OutTemp => Z_zd,
Paths => (0 => (A_ipd'last_event, tpd_A_Z, TRUE),
1 => (B_ipd'last_event, tpd_B_Z, TRUE),
2 => (C_ipd'last_event, tpd_C_Z, TRUE),
3 => (D_ipd'last_event, tpd_D_Z, TRUE),
4 => (E_ipd'last_event, tpd_E_Z, TRUE),
5 => (F_ipd'last_event, tpd_F_Z, TRUE),
6 => (G_ipd'last_event, tpd_G_Z, TRUE)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end V;
configuration CFG_ORCALUT7_V of ORCALUT7 is
for V
end for;
end CFG_ORCALUT7_V;
----- CELL ORCALUT8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity ORCALUT8 is
generic(
TimingChecksOn: Boolean := TRUE;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := False;
tpd_A_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_C_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_D_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_E_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_F_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_G_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_H_Z : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_F : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_H : VitalDelayType01 := (0.000 ns, 0.000 ns);
INIT : bit_vector);
port(
Z : out STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
G : in STD_ULOGIC;
H : in STD_ULOGIC);
attribute VITAL_LEVEL0 of ORCALUT8 : entity is TRUE;
end ORCALUT8;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture V of ORCALUT8 is
attribute VITAL_LEVEL1 of V : architecture is TRUE;
SIGNAL A_ipd : STD_ULOGIC := 'X';
SIGNAL B_ipd : STD_ULOGIC := 'X';
SIGNAL C_ipd : STD_ULOGIC := 'X';
SIGNAL D_ipd : STD_ULOGIC := 'X';
SIGNAL E_ipd : STD_ULOGIC := 'X';
SIGNAL F_ipd : STD_ULOGIC := 'X';
SIGNAL G_ipd : STD_ULOGIC := 'X';
SIGNAL H_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (C_ipd, C, tipd_C);
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (E_ipd, E, tipd_E);
VitalWireDelay (F_ipd, F, tipd_F);
VitalWireDelay (G_ipd, G, tipd_G);
VitalWireDelay (H_ipd, H, tipd_H);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd, F_ipd, G_ipd, H_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Z_zd : STD_LOGIC is Results(1);
-- output glitch detection variables
VARIABLE Z_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Z_zd := VitalMUX
(data => To_StdLogicVector(INIT),
dselect => (H_ipd, G_ipd, F_ipd, E_ipd, D_ipd, C_ipd, B_ipd, A_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Z,
GlitchData => Z_GlitchData,
OutSignalName => "Z",
OutTemp => Z_zd,
Paths => (0 => (A_ipd'last_event, tpd_A_Z, TRUE),
1 => (B_ipd'last_event, tpd_B_Z, TRUE),
2 => (C_ipd'last_event, tpd_C_Z, TRUE),
3 => (D_ipd'last_event, tpd_D_Z, TRUE),
4 => (E_ipd'last_event, tpd_E_Z, TRUE),
5 => (F_ipd'last_event, tpd_F_Z, TRUE),
6 => (G_ipd'last_event, tpd_G_Z, TRUE),
7 => (H_ipd'last_event, tpd_H_Z, TRUE)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end V;
configuration CFG_ORCALUT8_V of ORCALUT8 is
for V
end for;
end CFG_ORCALUT8_V;
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_CMB.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
--
----- cell ageb2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY ageb2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "ageb4";
tpd_a0_ge : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_ge : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_ge : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_ge : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ci_ge : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_a1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ci : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a0 : IN std_logic;
a1 : IN std_logic;
b0 : IN std_logic;
b1 : IN std_logic;
ci : IN std_logic := '1';
ge : OUT std_logic);
ATTRIBUTE Vital_Level0 OF ageb2 : ENTITY IS TRUE;
END ageb2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF ageb2 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL a0_ipd : std_logic := 'X';
SIGNAL a1_ipd : std_logic := 'X';
SIGNAL b0_ipd : std_logic := 'X';
SIGNAL b1_ipd : std_logic := 'X';
SIGNAL ci_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a0_ipd, a0, tipd_a0);
VitalWireDelay (a1_ipd, a1, tipd_a1);
VitalWireDelay (b0_ipd, b0, tipd_b0);
VitalWireDelay (b1_ipd, b1, tipd_b1);
VitalWireDelay (ci_ipd, ci, tipd_ci);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a0_ipd, a1_ipd, b0_ipd, b1_ipd, ci_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS ge_zd : std_ulogic IS results(1);
VARIABLE a, b : std_logic_vector(0 to 1) := (others => 'X');
-- output glitch detection VARIABLEs
VARIABLE ge_GlitchData : VitalGlitchDataType;
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-------------------------
-- functionality section
-------------------------
a := std_logic_vector'(a1_ipd, a0_ipd);
b := std_logic_vector'(b1_ipd, b0_ipd);
-- if a = b, then output carry-in (ge from the lower stage)
-- note: carry-in on the first stage is tied high
IF (a > b) THEN
ge_zd := '1';
ELSIF (a = b) THEN
ge_zd := ci_ipd;
ELSE
ge_zd := '0';
END IF;
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => ge,
OutSignalName => "ge",
OutTemp => ge_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_ge, TRUE),
1 => (a1_ipd'last_event, tpd_a1_ge, TRUE),
2 => (b0_ipd'last_event, tpd_b0_ge, TRUE),
3 => (b1_ipd'last_event, tpd_b1_ge, TRUE),
4 => (ci_ipd'last_event, tpd_ci_ge, TRUE)),
GlitchData => ge_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell aleb2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY aleb2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "aleb4";
tpd_a0_le : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_le : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_le : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_le : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ci_le : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_a1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ci : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a0, a1 : IN std_logic;
b0, b1 : IN std_logic;
ci : IN std_logic := '1';
le : OUT std_logic);
ATTRIBUTE Vital_Level0 OF aleb2 : ENTITY IS TRUE;
END aleb2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF aleb2 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL a0_ipd : std_logic := 'X';
SIGNAL a1_ipd : std_logic := 'X';
SIGNAL b0_ipd : std_logic := 'X';
SIGNAL b1_ipd : std_logic := 'X';
SIGNAL ci_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a0_ipd, a0, tipd_a0);
VitalWireDelay (a1_ipd, a1, tipd_a1);
VitalWireDelay (b0_ipd, b0, tipd_b0);
VitalWireDelay (b1_ipd, b1, tipd_b1);
VitalWireDelay (ci_ipd, ci, tipd_ci);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a0_ipd, a1_ipd, b0_ipd, b1_ipd, ci_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS le_zd : std_ulogic IS results(1);
VARIABLE a, b : std_logic_vector(0 to 1) := (others => 'X');
-- output glitch detection VARIABLEs
VARIABLE le_GlitchData : VitalGlitchDataType;
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-------------------------
-- functionality section
-------------------------
a := std_logic_vector'(a1_ipd, a0_ipd);
b := std_logic_vector'(b1_ipd, b0_ipd);
-- if a = b, then output carry-in (le from the lower stage)
-- note: carry-in on the first stage is tied high
IF (a < b) THEN
le_zd := '1';
ELSIF (a = b) THEN
le_zd := ci_ipd;
ELSE
le_zd := '0';
END IF;
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => le,
OutSignalName => "le",
OutTemp => le_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_le, TRUE),
1 => (a1_ipd'last_event, tpd_a1_le, TRUE),
2 => (b0_ipd'last_event, tpd_b0_le, TRUE),
3 => (b1_ipd'last_event, tpd_b1_le, TRUE),
4 => (ci_ipd'last_event, tpd_ci_le, TRUE)),
GlitchData => le_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell aneb2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY aneb2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "aneb4";
tpd_a0_ne : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_ne : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_ne : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_ne : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ci_ne : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_a1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ci : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a0 : IN std_logic;
a1 : IN std_logic;
b0 : IN std_logic;
b1 : IN std_logic;
ci : IN std_logic := '0';
ne : OUT std_logic);
ATTRIBUTE Vital_Level0 OF aneb2 : ENTITY IS TRUE;
END aneb2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF aneb2 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL a0_ipd : std_logic := 'X';
SIGNAL a1_ipd : std_logic := 'X';
SIGNAL b0_ipd : std_logic := 'X';
SIGNAL b1_ipd : std_logic := 'X';
SIGNAL ci_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a0_ipd, a0, tipd_a0);
VitalWireDelay (a1_ipd, a1, tipd_a1);
VitalWireDelay (b0_ipd, b0, tipd_b0);
VitalWireDelay (b1_ipd, b1, tipd_b1);
VitalWireDelay (ci_ipd, ci, tipd_ci);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a0_ipd, a1_ipd, b0_ipd, b1_ipd, ci_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS ne_zd : std_ulogic IS results(1);
VARIABLE a, b : std_logic_vector(0 to 1) := (others => 'X');
-- output glitch detection VARIABLEs
VARIABLE ne_GlitchData : VitalGlitchDataType;
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-------------------------
-- functionality section
-------------------------
a := std_logic_vector'(a1_ipd, a0_ipd);
b := std_logic_vector'(b1_ipd, b0_ipd);
-- IF a = b, THEN pass on carry-in input (ne from the previous stage)
-- note: carry-in on the first stage is tied low
IF (a = b) THEN
ne_zd := ci_ipd;
ELSE
ne_zd := '1';
END IF;
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => ne,
OutSignalName => "ne",
OutTemp => ne_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_ne, TRUE),
1 => (a1_ipd'last_event, tpd_a1_ne, TRUE),
2 => (b0_ipd'last_event, tpd_b0_ne, TRUE),
3 => (b1_ipd'last_event, tpd_b1_ne, TRUE),
4 => (ci_ipd'last_event, tpd_ci_ne, TRUE)),
GlitchData => ne_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell and2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY and2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "and2";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF and2 : ENTITY IS TRUE;
END and2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF and2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd AND b_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell and3 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY and3 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "and3";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF and3 : ENTITY IS TRUE;
END and3;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF and3 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd AND b_ipd AND c_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell and4 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY and4 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "and4";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF and4 : ENTITY IS TRUE;
END and4;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF and4 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd AND b_ipd AND c_ipd AND d_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell and5 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY and5 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "and5";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_e_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_e : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
e : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF and5 : ENTITY IS TRUE;
END and5;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF and5 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
SIGNAL e_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (e_ipd, e, tipd_e);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd, e_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd AND b_ipd AND c_ipd AND d_ipd AND e_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE),
4 => (e_ipd'last_event, tpd_e_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fadd2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY fadd2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fadd2";
tpd_a0_cout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_cout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_cout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_cout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ci_cout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a0_cout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_cout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_cout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_cout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ci_cout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a0_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a0_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ci_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ci_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_a1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ci : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a0 : IN std_logic;
a1 : IN std_logic;
b0 : IN std_logic;
b1 : IN std_logic;
ci : IN std_logic;
s0 : OUT std_logic;
s1 : OUT std_logic;
cout0 : OUT std_logic;
cout1 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fadd2 : ENTITY IS TRUE;
END fadd2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF fadd2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a0_ipd : std_logic := 'X';
SIGNAL a1_ipd : std_logic := 'X';
SIGNAL b0_ipd : std_logic := 'X';
SIGNAL b1_ipd : std_logic := 'X';
SIGNAL ci_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a0_ipd, a0, tipd_a0);
VitalWireDelay (a1_ipd, a1, tipd_a1);
VitalWireDelay (b0_ipd, b0, tipd_b0);
VitalWireDelay (b1_ipd, b1, tipd_b1);
VitalWireDelay (ci_ipd, ci, tipd_ci);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a0_ipd, a1_ipd, b0_ipd,
b1_ipd, ci_ipd)
-- functionality results
VARIABLE results1 : std_logic_vector(1 to 2) := (others => 'X');
VARIABLE results2 : std_logic_vector(1 to 2) := (others => 'X');
ALIAS cout0_zd : std_ulogic IS results1(1);
ALIAS s0_zd : std_ulogic IS results1(2);
ALIAS cout1_zd : std_ulogic IS results2(1);
ALIAS s1_zd : std_ulogic IS results2(2);
-- output glitch detection VARIABLEs
VARIABLE cout0_GlitchData : VitalGlitchDataType;
VARIABLE s0_GlitchData : VitalGlitchDataType;
VARIABLE cout1_GlitchData : VitalGlitchDataType;
VARIABLE s1_GlitchData : VitalGlitchDataType;
constant add_table : vitaltruthtabletype := (
--------------------------------------------
-- a b ci | co s
--------------------------------------------
( '0', '0', '0', '0', '0'),
( '1', '0', '0', '0', '1'),
( '0', '1', '0', '0', '1'),
( '1', '1', '0', '1', '0'),
( '0', '0', '1', '0', '1'),
( '1', '0', '1', '1', '0'),
( '0', '1', '1', '1', '0'),
( '1', '1', '1', '1', '1'));
BEGIN
-------------------------
-- functionality section
-------------------------
results1 := vitaltruthtable (
truthtable => add_table,
datain => (a0_ipd, b0_ipd, ci_ipd)
);
results2 := vitaltruthtable (
truthtable => add_table,
datain => (a1_ipd, b1_ipd, cout0_zd)
);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "cout0",
OutTemp => cout0_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_cout0, TRUE),
1 => (a1_ipd'last_event, tpd_a1_cout0, TRUE),
2 => (b0_ipd'last_event, tpd_b0_cout0, TRUE),
3 => (b1_ipd'last_event, tpd_b1_cout0, TRUE),
4 => (ci_ipd'last_event, tpd_ci_cout0, TRUE)),
GlitchData => cout0_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => s0,
OutSignalName => "s0",
OutTemp => s0_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_s0, TRUE),
1 => (a1_ipd'last_event, tpd_a1_s0, TRUE),
2 => (b0_ipd'last_event, tpd_b0_s0, TRUE),
3 => (b1_ipd'last_event, tpd_b1_s0, TRUE),
4 => (ci_ipd'last_event, tpd_ci_s0, TRUE)),
GlitchData => s0_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => s1,
OutSignalName => "s1",
OutTemp => s1_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_s1, TRUE),
1 => (a1_ipd'last_event, tpd_a1_s1, TRUE),
2 => (b0_ipd'last_event, tpd_b0_s1, TRUE),
3 => (b1_ipd'last_event, tpd_b1_s1, TRUE),
4 => (ci_ipd'last_event, tpd_ci_s1, TRUE)),
GlitchData => s1_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "cout1",
OutTemp => cout1_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_cout1, TRUE),
1 => (a1_ipd'last_event, tpd_a1_cout1, TRUE),
2 => (b0_ipd'last_event, tpd_b0_cout1, TRUE),
3 => (b1_ipd'last_event, tpd_b1_cout1, TRUE),
4 => (ci_ipd'last_event, tpd_ci_cout1, TRUE)),
GlitchData => cout1_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell fsub2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY fsub2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fsub2";
tpd_a0_bout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_bout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_bout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_bout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_bi_bout0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a0_bout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_bout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_bout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_bout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_bi_bout1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a0_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_bi_s0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a0_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_a1_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b0_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b1_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_bi_s1 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_a1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_bi : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a0 : IN std_logic;
a1 : IN std_logic;
b0 : IN std_logic;
b1 : IN std_logic;
bi : IN std_logic;
bout0 : OUT std_logic;
bout1 : OUT std_logic;
s0 : OUT std_logic;
s1 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fsub2 : ENTITY IS TRUE;
END fsub2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF fsub2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a0_ipd : std_logic := 'X';
SIGNAL a1_ipd : std_logic := 'X';
SIGNAL b0_ipd : std_logic := 'X';
SIGNAL b1_ipd : std_logic := 'X';
SIGNAL bi_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a0_ipd, a0, tipd_a0);
VitalWireDelay (a1_ipd, a1, tipd_a1);
VitalWireDelay (b0_ipd, b0, tipd_b0);
VitalWireDelay (b1_ipd, b1, tipd_b1);
VitalWireDelay (bi_ipd, bi, tipd_bi);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a0_ipd, a1_ipd, b0_ipd,
b1_ipd, bi_ipd)
-- functionality results
VARIABLE results1 : std_logic_vector(1 to 2) := (others => 'X');
VARIABLE results2 : std_logic_vector(1 to 2) := (others => 'X');
ALIAS bout0_zd : std_ulogic IS results1(1);
ALIAS s0_zd : std_ulogic IS results1(2);
ALIAS bout1_zd : std_ulogic IS results2(1);
ALIAS s1_zd : std_ulogic IS results2(2);
-- output glitch detection VARIABLEs
VARIABLE bout0_GlitchData : VitalGlitchDataType;
VARIABLE s0_GlitchData : VitalGlitchDataType;
VARIABLE bout1_GlitchData : VitalGlitchDataType;
VARIABLE s1_GlitchData : VitalGlitchDataType;
constant sub_table : vitaltruthtabletype := (
--------------------------------------------
-- a b bi | bo s
--------------------------------------------
( '0', '0', '0', '0', '1'),
( '1', '0', '0', '1', '0'),
( '0', '1', '0', '0', '0'),
( '1', '1', '0', '0', '1'),
( '0', '0', '1', '1', '0'),
( '1', '0', '1', '1', '1'),
( '0', '1', '1', '0', '1'),
( '1', '1', '1', '1', '0'));
BEGIN
-------------------------
-- functionality section
-------------------------
results1 := vitaltruthtable (
truthtable => sub_table,
datain => (a0_ipd, b0_ipd, bi_ipd)
);
results2 := vitaltruthtable (
truthtable => sub_table,
datain => (a1_ipd, b1_ipd, bout0_zd)
);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => bout0,
OutSignalName => "bout0",
OutTemp => bout0_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_bout0, TRUE),
1 => (a1_ipd'last_event, tpd_a1_bout0, TRUE),
2 => (b0_ipd'last_event, tpd_b0_bout0, TRUE),
3 => (b1_ipd'last_event, tpd_b1_bout0, TRUE),
4 => (bi_ipd'last_event, tpd_bi_bout0, TRUE)),
GlitchData => bout0_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => s0,
OutSignalName => "s0",
OutTemp => s0_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_s0, TRUE),
1 => (a1_ipd'last_event, tpd_a1_s0, TRUE),
2 => (b0_ipd'last_event, tpd_b0_s0, TRUE),
3 => (b1_ipd'last_event, tpd_b1_s0, TRUE),
4 => (bi_ipd'last_event, tpd_bi_s0, TRUE)),
GlitchData => s0_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => s1,
OutSignalName => "s1",
OutTemp => s1_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_s1, TRUE),
1 => (a1_ipd'last_event, tpd_a1_s1, TRUE),
2 => (b0_ipd'last_event, tpd_b0_s1, TRUE),
3 => (b1_ipd'last_event, tpd_b1_s1, TRUE),
4 => (bi_ipd'last_event, tpd_bi_s1, TRUE)),
GlitchData => s1_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => bout1,
OutSignalName => "bout1",
OutTemp => bout1_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_bout1, TRUE),
1 => (a1_ipd'last_event, tpd_a1_bout1, TRUE),
2 => (b0_ipd'last_event, tpd_b0_bout1, TRUE),
3 => (b1_ipd'last_event, tpd_b1_bout1, TRUE),
4 => (bi_ipd'last_event, tpd_bi_bout1, TRUE)),
GlitchData => bout1_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
----- cell fadsu2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY fadsu2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fadsu2";
tpd_a0_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a1_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b0_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b1_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_bci_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_con_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a0_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a0_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a1_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a1_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a1_s2 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b0_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b0_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b1_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b1_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_bci_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_bci_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_con_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_con_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_a0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_a1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_bci : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_con : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a0 : IN std_logic;
a1 : IN std_logic;
b0 : IN std_logic;
b1 : IN std_logic;
bci : IN std_logic;
con : IN std_logic;
bco : OUT std_logic;
s0 : OUT std_logic;
s1 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fadsu2 : ENTITY IS TRUE;
END fadsu2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF fadsu2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a0_ipd : std_logic := 'X';
SIGNAL a1_ipd : std_logic := 'X';
SIGNAL b0_ipd : std_logic := 'X';
SIGNAL b1_ipd : std_logic := 'X';
SIGNAL bci_ipd : std_logic := 'X';
SIGNAL con_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a0_ipd, a0, tipd_a0);
VitalWireDelay (a1_ipd, a1, tipd_a1);
VitalWireDelay (b0_ipd, b0, tipd_b0);
VitalWireDelay (b1_ipd, b1, tipd_b1);
VitalWireDelay (bci_ipd, bci, tipd_bci);
VitalWireDelay (con_ipd, con, tipd_con);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a0_ipd, a1_ipd, b0_ipd, b1_ipd, bci_ipd, con_ipd)
-- functionality results
VARIABLE results1 : std_logic_vector(1 to 2) := (others => 'X');
VARIABLE results2 : std_logic_vector(1 to 2) := (others => 'X');
VARIABLE results3 : std_logic_vector(1 to 2) := (others => 'X');
VARIABLE results4 : std_logic_vector(1 to 2) := (others => 'X');
ALIAS bc0_zd : std_ulogic IS results1(1);
ALIAS s0_zd : std_ulogic IS results1(2);
ALIAS bco_zd : std_ulogic IS results2(1);
ALIAS s1_zd : std_ulogic IS results2(2);
-- output glitch detection VARIABLEs
VARIABLE bco_GlitchData : VitalGlitchDataType;
VARIABLE s0_GlitchData : VitalGlitchDataType;
VARIABLE s1_GlitchData : VitalGlitchDataType;
constant adsu_table : vitaltruthtabletype := (
--------------------------------------------
-- a b bci con | bco s
--------------------------------------------
('0', '0', '0', '1', '0', '0'),
('1', '0', '0', '1', '0', '1'),
('0', '1', '0', '1', '0', '1'),
('1', '1', '0', '1', '1', '0'),
('0', '0', '1', '1', '0', '1'),
('1', '0', '1', '1', '1', '0'),
('0', '1', '1', '1', '1', '0'),
('1', '1', '1', '1', '1', '1'),
('0', '0', '0', '0', '0', '1'),
('1', '0', '0', '0', '1', '0'),
('0', '1', '0', '0', '0', '0'),
('1', '1', '0', '0', '0', '1'),
('0', '0', '1', '0', '1', '0'),
('1', '0', '1', '0', '1', '1'),
('0', '1', '1', '0', '0', '1'),
('1', '1', '1', '0', '1', '0'));
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-------------------------
-- functionality section
-------------------------
results1 := vitaltruthtable (
truthtable => adsu_table,
datain => (a0_ipd, b0_ipd, bci_ipd, con_ipd)
);
results2 := vitaltruthtable (
truthtable => adsu_table,
datain => (a1_ipd, b1_ipd, bc0_zd, con_ipd)
);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => bco,
OutSignalName => "bco",
OutTemp => bco_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_bco, TRUE),
1 => (a1_ipd'last_event, tpd_a1_bco, TRUE),
2 => (b0_ipd'last_event, tpd_b0_bco, TRUE),
3 => (b1_ipd'last_event, tpd_b1_bco, TRUE),
4 => (bci_ipd'last_event, tpd_bci_bco, TRUE),
5 => (con_ipd'last_event, tpd_con_bco, TRUE)),
GlitchData => bco_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => s0,
OutSignalName => "s0",
OutTemp => s0_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_s0, TRUE),
1 => (a1_ipd'last_event, tpd_a1_s0, TRUE),
2 => (b0_ipd'last_event, tpd_b0_s0, TRUE),
3 => (b1_ipd'last_event, tpd_b1_s0, TRUE),
4 => (bci_ipd'last_event, tpd_bci_s0, TRUE),
5 => (con_ipd'last_event, tpd_con_s0, TRUE)),
GlitchData => s0_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => s1,
OutSignalName => "s1",
OutTemp => s1_zd,
Paths => (0 => (a0_ipd'last_event, tpd_a0_s1, TRUE),
1 => (a1_ipd'last_event, tpd_a1_s1, TRUE),
2 => (b0_ipd'last_event, tpd_b0_s1, TRUE),
3 => (b1_ipd'last_event, tpd_b1_s1, TRUE),
4 => (bci_ipd'last_event, tpd_bci_s1, TRUE),
5 => (con_ipd'last_event, tpd_con_s1, TRUE)),
GlitchData => s1_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell inv -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY inv IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "inv";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF inv : ENTITY IS TRUE;
END inv;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF inv IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (NOT a_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell mux21 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY mux21 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "mux21";
tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF mux21 : ENTITY IS TRUE;
END mux21;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF mux21 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := 'X';
SIGNAL d1_ipd : std_logic := 'X';
SIGNAL sd_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (d0_ipd, d0, tipd_d0);
VitalWireDelay (d1_ipd, d1, tipd_d1);
VitalWireDelay (sd_ipd, sd, tipd_sd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, sd_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (d0_ipd'last_event, tpd_d0_z, TRUE),
1 => (d1_ipd'last_event, tpd_d1_z, TRUE),
2 => (sd_ipd'last_event, tpd_sd_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell l6mux21 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY l6mux21 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "l6mux21";
tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
d0 : IN std_logic;
d1 : IN std_logic;
sd : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF l6mux21 : ENTITY IS TRUE;
END l6mux21;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF l6mux21 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := 'X';
SIGNAL d1_ipd : std_logic := 'X';
SIGNAL sd_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (d0_ipd, d0, tipd_d0);
VitalWireDelay (d1_ipd, d1, tipd_d1);
VitalWireDelay (sd_ipd, sd, tipd_sd);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, sd_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := vitalmux
(data => (d1_ipd, d0_ipd),
dselect => (0 => sd_ipd));
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (d0_ipd'last_event, tpd_d0_z, TRUE),
1 => (d1_ipd'last_event, tpd_d1_z, TRUE),
2 => (sd_ipd'last_event, tpd_sd_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell mux41 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
ENTITY mux41 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "mux41";
tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d2_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d3_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd2_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd2 : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
d0 : IN std_logic;
d1 : IN std_logic;
d2 : IN std_logic;
d3 : IN std_logic;
sd1 : IN std_logic;
sd2 : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF mux41 : ENTITY IS TRUE;
END mux41;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF mux41 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := 'X';
SIGNAL d1_ipd : std_logic := 'X';
SIGNAL d2_ipd : std_logic := 'X';
SIGNAL d3_ipd : std_logic := 'X';
SIGNAL sd1_ipd : std_logic := 'X';
SIGNAL sd2_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (d0_ipd, d0, tipd_d0);
VitalWireDelay (d1_ipd, d1, tipd_d1);
VitalWireDelay (d2_ipd, d2, tipd_d2);
VitalWireDelay (d3_ipd, d3, tipd_d3);
VitalWireDelay (sd1_ipd, sd1, tipd_sd1);
VitalWireDelay (sd2_ipd, sd2, tipd_sd2);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, d2_ipd, d3_ipd, sd1_ipd, sd2_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := vitalmux
(data => (d3_ipd, d2_ipd, d1_ipd, d0_ipd),
dselect => (sd2_ipd, sd1_ipd));
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (d0_ipd'last_event, tpd_d0_z, TRUE),
1 => (d1_ipd'last_event, tpd_d1_z, TRUE),
2 => (d2_ipd'last_event, tpd_d2_z, TRUE),
3 => (d3_ipd'last_event, tpd_d3_z, TRUE),
4 => (sd1_ipd'last_event, tpd_sd1_z, TRUE),
5 => (sd2_ipd'last_event, tpd_sd2_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell mux81 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY mux81 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "mux81";
tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d2_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d3_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d4_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d5_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d6_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d7_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd2_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd3_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd3 : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
d0 : IN std_logic;
d1 : IN std_logic;
d2 : IN std_logic;
d3 : IN std_logic;
d4 : IN std_logic;
d5 : IN std_logic;
d6 : IN std_logic;
d7 : IN std_logic;
sd1 : IN std_logic;
sd2 : IN std_logic;
sd3 : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF mux81 : ENTITY IS TRUE;
END mux81;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF mux81 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := 'X';
SIGNAL d1_ipd : std_logic := 'X';
SIGNAL d2_ipd : std_logic := 'X';
SIGNAL d3_ipd : std_logic := 'X';
SIGNAL d4_ipd : std_logic := 'X';
SIGNAL d5_ipd : std_logic := 'X';
SIGNAL d6_ipd : std_logic := 'X';
SIGNAL d7_ipd : std_logic := 'X';
SIGNAL sd1_ipd : std_logic := 'X';
SIGNAL sd2_ipd : std_logic := 'X';
SIGNAL sd3_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (d0_ipd, d0, tipd_d0);
VitalWireDelay (d1_ipd, d1, tipd_d1);
VitalWireDelay (d2_ipd, d2, tipd_d2);
VitalWireDelay (d3_ipd, d3, tipd_d3);
VitalWireDelay (d4_ipd, d4, tipd_d4);
VitalWireDelay (d5_ipd, d5, tipd_d5);
VitalWireDelay (d6_ipd, d6, tipd_d6);
VitalWireDelay (d7_ipd, d7, tipd_d7);
VitalWireDelay (sd1_ipd, sd1, tipd_sd1);
VitalWireDelay (sd2_ipd, sd2, tipd_sd2);
VitalWireDelay (sd3_ipd, sd3, tipd_sd3);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, d2_ipd, d3_ipd, d4_ipd, d5_ipd, d6_ipd, d7_ipd, sd1_ipd, sd2_ipd, sd3_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := vitalmux
(data => (d7_ipd, d6_ipd, d5_ipd, d4_ipd, d3_ipd, d2_ipd, d1_ipd, d0_ipd),
dselect => (sd3_ipd, sd2_ipd, sd1_ipd));
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (d0_ipd'last_event, tpd_d0_z, TRUE),
1 => (d1_ipd'last_event, tpd_d1_z, TRUE),
2 => (d2_ipd'last_event, tpd_d2_z, TRUE),
3 => (d3_ipd'last_event, tpd_d3_z, TRUE),
4 => (d4_ipd'last_event, tpd_d4_z, TRUE),
5 => (d5_ipd'last_event, tpd_d5_z, TRUE),
6 => (d6_ipd'last_event, tpd_d6_z, TRUE),
7 => (d7_ipd'last_event, tpd_d7_z, TRUE),
8 => (sd1_ipd'last_event, tpd_sd1_z, TRUE),
9 => (sd2_ipd'last_event, tpd_sd2_z, TRUE),
10 => (sd3_ipd'last_event, tpd_sd3_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell mux161 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY mux161 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "mux81";
tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d2_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d3_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d4_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d5_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d6_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d7_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d8_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d9_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d10_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d11_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d12_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d13_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d14_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d15_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd2_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd3_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd4_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd4 : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
d0 : IN std_logic;
d1 : IN std_logic;
d2 : IN std_logic;
d3 : IN std_logic;
d4 : IN std_logic;
d5 : IN std_logic;
d6 : IN std_logic;
d7 : IN std_logic;
d8 : IN std_logic;
d9 : IN std_logic;
d10 : IN std_logic;
d11 : IN std_logic;
d12 : IN std_logic;
d13 : IN std_logic;
d14 : IN std_logic;
d15 : IN std_logic;
sd1 : IN std_logic;
sd2 : IN std_logic;
sd3 : IN std_logic;
sd4 : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF mux161 : ENTITY IS TRUE;
END mux161;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF mux161 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := 'X';
SIGNAL d1_ipd : std_logic := 'X';
SIGNAL d2_ipd : std_logic := 'X';
SIGNAL d3_ipd : std_logic := 'X';
SIGNAL d4_ipd : std_logic := 'X';
SIGNAL d5_ipd : std_logic := 'X';
SIGNAL d6_ipd : std_logic := 'X';
SIGNAL d7_ipd : std_logic := 'X';
SIGNAL d8_ipd : std_logic := 'X';
SIGNAL d9_ipd : std_logic := 'X';
SIGNAL d10_ipd : std_logic := 'X';
SIGNAL d11_ipd : std_logic := 'X';
SIGNAL d12_ipd : std_logic := 'X';
SIGNAL d13_ipd : std_logic := 'X';
SIGNAL d14_ipd : std_logic := 'X';
SIGNAL d15_ipd : std_logic := 'X';
SIGNAL sd1_ipd : std_logic := 'X';
SIGNAL sd2_ipd : std_logic := 'X';
SIGNAL sd3_ipd : std_logic := 'X';
SIGNAL sd4_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (d0_ipd, d0, tipd_d0);
VitalWireDelay (d1_ipd, d1, tipd_d1);
VitalWireDelay (d2_ipd, d2, tipd_d2);
VitalWireDelay (d3_ipd, d3, tipd_d3);
VitalWireDelay (d4_ipd, d4, tipd_d4);
VitalWireDelay (d5_ipd, d5, tipd_d5);
VitalWireDelay (d6_ipd, d6, tipd_d6);
VitalWireDelay (d7_ipd, d7, tipd_d7);
VitalWireDelay (d8_ipd, d8, tipd_d8);
VitalWireDelay (d9_ipd, d9, tipd_d9);
VitalWireDelay (d10_ipd, d10, tipd_d10);
VitalWireDelay (d11_ipd, d11, tipd_d11);
VitalWireDelay (d12_ipd, d12, tipd_d12);
VitalWireDelay (d13_ipd, d13, tipd_d13);
VitalWireDelay (d14_ipd, d14, tipd_d14);
VitalWireDelay (d15_ipd, d15, tipd_d15);
VitalWireDelay (sd1_ipd, sd1, tipd_sd1);
VitalWireDelay (sd2_ipd, sd2, tipd_sd2);
VitalWireDelay (sd3_ipd, sd3, tipd_sd3);
VitalWireDelay (sd4_ipd, sd4, tipd_sd4);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, d2_ipd, d3_ipd, d4_ipd, d5_ipd, d6_ipd, d7_ipd, d8_ipd, d9_ipd, d10_ipd, d11_ipd, d12_ipd, d13_ipd, d14_ipd, d15_ipd, sd1_ipd, sd2_ipd, sd3_ipd, sd4_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := vitalmux
(data => (d15_ipd, d14_ipd, d13_ipd, d12_ipd, d11_ipd, d10_ipd, d9_ipd, d8_ipd, d7_ipd, d6_ipd, d5_ipd, d4_ipd, d3_ipd, d2_ipd, d1_ipd, d0_ipd),
dselect => (sd4_ipd, sd3_ipd, sd2_ipd, sd1_ipd));
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (d0_ipd'last_event, tpd_d0_z, TRUE),
1 => (d1_ipd'last_event, tpd_d1_z, TRUE),
2 => (d2_ipd'last_event, tpd_d2_z, TRUE),
3 => (d3_ipd'last_event, tpd_d3_z, TRUE),
4 => (d4_ipd'last_event, tpd_d4_z, TRUE),
5 => (d5_ipd'last_event, tpd_d5_z, TRUE),
6 => (d6_ipd'last_event, tpd_d6_z, TRUE),
7 => (d7_ipd'last_event, tpd_d7_z, TRUE),
8 => (d8_ipd'last_event, tpd_d8_z, TRUE),
9 => (d9_ipd'last_event, tpd_d9_z, TRUE),
10 => (d10_ipd'last_event, tpd_d10_z, TRUE),
11 => (d11_ipd'last_event, tpd_d11_z, TRUE),
12 => (d12_ipd'last_event, tpd_d12_z, TRUE),
13 => (d13_ipd'last_event, tpd_d13_z, TRUE),
14 => (d14_ipd'last_event, tpd_d14_z, TRUE),
15 => (d15_ipd'last_event, tpd_d15_z, TRUE),
16 => (sd1_ipd'last_event, tpd_sd1_z, TRUE),
17 => (sd2_ipd'last_event, tpd_sd2_z, TRUE),
18 => (sd3_ipd'last_event, tpd_sd3_z, TRUE),
19 => (sd4_ipd'last_event, tpd_sd4_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell mux321 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY mux321 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "mux81";
tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d2_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d3_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d4_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d5_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d6_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d7_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d8_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d9_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d10_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d11_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d12_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d13_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d14_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d15_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d16_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d17_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d18_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d19_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d20_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d21_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d22_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d23_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d24_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d25_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d26_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d27_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d28_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d29_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d30_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d31_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd1_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd2_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd3_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd4_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_sd5_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d18 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d19 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d20 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d21 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d22 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d23 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d24 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d25 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d26 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d27 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d28 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d29 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d30 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d31 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sd5 : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
d0 : IN std_logic;
d1 : IN std_logic;
d2 : IN std_logic;
d3 : IN std_logic;
d4 : IN std_logic;
d5 : IN std_logic;
d6 : IN std_logic;
d7 : IN std_logic;
d8 : IN std_logic;
d9 : IN std_logic;
d10 : IN std_logic;
d11 : IN std_logic;
d12 : IN std_logic;
d13 : IN std_logic;
d14 : IN std_logic;
d15 : IN std_logic;
d16 : IN std_logic;
d17 : IN std_logic;
d18 : IN std_logic;
d19 : IN std_logic;
d20 : IN std_logic;
d21 : IN std_logic;
d22 : IN std_logic;
d23 : IN std_logic;
d24 : IN std_logic;
d25 : IN std_logic;
d26 : IN std_logic;
d27 : IN std_logic;
d28 : IN std_logic;
d29 : IN std_logic;
d30 : IN std_logic;
d31 : IN std_logic;
sd1 : IN std_logic;
sd2 : IN std_logic;
sd3 : IN std_logic;
sd4 : IN std_logic;
sd5 : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF mux321 : ENTITY IS TRUE;
END mux321;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF mux321 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL d0_ipd : std_logic := 'X';
SIGNAL d1_ipd : std_logic := 'X';
SIGNAL d2_ipd : std_logic := 'X';
SIGNAL d3_ipd : std_logic := 'X';
SIGNAL d4_ipd : std_logic := 'X';
SIGNAL d5_ipd : std_logic := 'X';
SIGNAL d6_ipd : std_logic := 'X';
SIGNAL d7_ipd : std_logic := 'X';
SIGNAL d8_ipd : std_logic := 'X';
SIGNAL d9_ipd : std_logic := 'X';
SIGNAL d10_ipd : std_logic := 'X';
SIGNAL d11_ipd : std_logic := 'X';
SIGNAL d12_ipd : std_logic := 'X';
SIGNAL d13_ipd : std_logic := 'X';
SIGNAL d14_ipd : std_logic := 'X';
SIGNAL d15_ipd : std_logic := 'X';
SIGNAL d16_ipd : std_logic := 'X';
SIGNAL d17_ipd : std_logic := 'X';
SIGNAL d18_ipd : std_logic := 'X';
SIGNAL d19_ipd : std_logic := 'X';
SIGNAL d20_ipd : std_logic := 'X';
SIGNAL d21_ipd : std_logic := 'X';
SIGNAL d22_ipd : std_logic := 'X';
SIGNAL d23_ipd : std_logic := 'X';
SIGNAL d24_ipd : std_logic := 'X';
SIGNAL d25_ipd : std_logic := 'X';
SIGNAL d26_ipd : std_logic := 'X';
SIGNAL d27_ipd : std_logic := 'X';
SIGNAL d28_ipd : std_logic := 'X';
SIGNAL d29_ipd : std_logic := 'X';
SIGNAL d30_ipd : std_logic := 'X';
SIGNAL d31_ipd : std_logic := 'X';
SIGNAL sd1_ipd : std_logic := 'X';
SIGNAL sd2_ipd : std_logic := 'X';
SIGNAL sd3_ipd : std_logic := 'X';
SIGNAL sd4_ipd : std_logic := 'X';
SIGNAL sd5_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (d0_ipd, d0, tipd_d0);
VitalWireDelay (d1_ipd, d1, tipd_d1);
VitalWireDelay (d2_ipd, d2, tipd_d2);
VitalWireDelay (d3_ipd, d3, tipd_d3);
VitalWireDelay (d4_ipd, d4, tipd_d4);
VitalWireDelay (d5_ipd, d5, tipd_d5);
VitalWireDelay (d6_ipd, d6, tipd_d6);
VitalWireDelay (d7_ipd, d7, tipd_d7);
VitalWireDelay (d8_ipd, d8, tipd_d8);
VitalWireDelay (d9_ipd, d9, tipd_d9);
VitalWireDelay (d10_ipd, d10, tipd_d10);
VitalWireDelay (d11_ipd, d11, tipd_d11);
VitalWireDelay (d12_ipd, d12, tipd_d12);
VitalWireDelay (d13_ipd, d13, tipd_d13);
VitalWireDelay (d14_ipd, d14, tipd_d14);
VitalWireDelay (d15_ipd, d15, tipd_d15);
VitalWireDelay (d16_ipd, d16, tipd_d16);
VitalWireDelay (d17_ipd, d17, tipd_d17);
VitalWireDelay (d18_ipd, d18, tipd_d18);
VitalWireDelay (d19_ipd, d19, tipd_d19);
VitalWireDelay (d20_ipd, d20, tipd_d20);
VitalWireDelay (d21_ipd, d21, tipd_d21);
VitalWireDelay (d22_ipd, d22, tipd_d22);
VitalWireDelay (d23_ipd, d23, tipd_d23);
VitalWireDelay (d24_ipd, d24, tipd_d24);
VitalWireDelay (d25_ipd, d25, tipd_d25);
VitalWireDelay (d26_ipd, d26, tipd_d26);
VitalWireDelay (d27_ipd, d27, tipd_d27);
VitalWireDelay (d28_ipd, d28, tipd_d28);
VitalWireDelay (d29_ipd, d29, tipd_d29);
VitalWireDelay (d30_ipd, d30, tipd_d30);
VitalWireDelay (d31_ipd, d31, tipd_d31);
VitalWireDelay (sd1_ipd, sd1, tipd_sd1);
VitalWireDelay (sd2_ipd, sd2, tipd_sd2);
VitalWireDelay (sd3_ipd, sd3, tipd_sd3);
VitalWireDelay (sd4_ipd, sd4, tipd_sd4);
VitalWireDelay (sd5_ipd, sd5, tipd_sd5);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (d0_ipd, d1_ipd, d2_ipd, d3_ipd, d4_ipd, d5_ipd, d6_ipd, d7_ipd, d8_ipd, d9_ipd, d10_ipd, d11_ipd, d12_ipd, d13_ipd, d14_ipd, d15_ipd, d16_ipd, d17_ipd, d18_ipd, d19_ipd, d20_ipd, d21_ipd, d22_ipd, d23_ipd, d24_ipd, d25_ipd, d26_ipd, d27_ipd, d28_ipd, d29_ipd, d30_ipd, d31_ipd, sd1_ipd, sd2_ipd, sd3_ipd, sd4_ipd, sd5_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := vitalmux
(data => (d31_ipd, d30_ipd, d29_ipd, d28_ipd, d27_ipd, d26_ipd, d25_ipd, d24_ipd, d23_ipd, d22_ipd, d21_ipd, d20_ipd, d19_ipd, d18_ipd, d17_ipd, d16_ipd, d15_ipd, d14_ipd, d13_ipd, d12_ipd, d11_ipd, d10_ipd, d9_ipd, d8_ipd, d7_ipd, d6_ipd, d5_ipd, d4_ipd, d3_ipd, d2_ipd, d1_ipd, d0_ipd),
dselect => (sd5_ipd, sd4_ipd, sd3_ipd, sd2_ipd, sd1_ipd));
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (d0_ipd'last_event, tpd_d0_z, TRUE),
1 => (d1_ipd'last_event, tpd_d1_z, TRUE),
2 => (d2_ipd'last_event, tpd_d2_z, TRUE),
3 => (d3_ipd'last_event, tpd_d3_z, TRUE),
4 => (d4_ipd'last_event, tpd_d4_z, TRUE),
5 => (d5_ipd'last_event, tpd_d5_z, TRUE),
6 => (d6_ipd'last_event, tpd_d6_z, TRUE),
7 => (d7_ipd'last_event, tpd_d7_z, TRUE),
8 => (d8_ipd'last_event, tpd_d8_z, TRUE),
9 => (d9_ipd'last_event, tpd_d9_z, TRUE),
10 => (d10_ipd'last_event, tpd_d10_z, TRUE),
11 => (d11_ipd'last_event, tpd_d11_z, TRUE),
12 => (d12_ipd'last_event, tpd_d12_z, TRUE),
13 => (d13_ipd'last_event, tpd_d13_z, TRUE),
14 => (d14_ipd'last_event, tpd_d14_z, TRUE),
15 => (d15_ipd'last_event, tpd_d15_z, TRUE),
16 => (d16_ipd'last_event, tpd_d16_z, TRUE),
17 => (d17_ipd'last_event, tpd_d17_z, TRUE),
18 => (d18_ipd'last_event, tpd_d18_z, TRUE),
19 => (d19_ipd'last_event, tpd_d19_z, TRUE),
20 => (d20_ipd'last_event, tpd_d20_z, TRUE),
21 => (d21_ipd'last_event, tpd_d21_z, TRUE),
22 => (d22_ipd'last_event, tpd_d22_z, TRUE),
23 => (d23_ipd'last_event, tpd_d23_z, TRUE),
24 => (d24_ipd'last_event, tpd_d24_z, TRUE),
25 => (d25_ipd'last_event, tpd_d25_z, TRUE),
26 => (d26_ipd'last_event, tpd_d26_z, TRUE),
27 => (d27_ipd'last_event, tpd_d27_z, TRUE),
28 => (d28_ipd'last_event, tpd_d28_z, TRUE),
29 => (d29_ipd'last_event, tpd_d29_z, TRUE),
30 => (d30_ipd'last_event, tpd_d30_z, TRUE),
31 => (d31_ipd'last_event, tpd_d31_z, TRUE),
32 => (sd1_ipd'last_event, tpd_sd1_z, TRUE),
33 => (sd2_ipd'last_event, tpd_sd2_z, TRUE),
34 => (sd3_ipd'last_event, tpd_sd3_z, TRUE),
35 => (sd4_ipd'last_event, tpd_sd4_z, TRUE),
36 => (sd5_ipd'last_event, tpd_sd5_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell nd2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY nd2 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "nd2";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF nd2 : ENTITY IS TRUE;
END nd2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF nd2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd AND b_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell nd3 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY nd3 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "nd3";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF nd3 : ENTITY IS TRUE;
END nd3;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF nd3 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd AND b_ipd AND c_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell nd4 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY nd4 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "nd4";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF nd4 : ENTITY IS TRUE;
END nd4;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF nd4 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd AND b_ipd AND c_ipd AND d_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell nd5 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY nd5 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "nd5";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_e_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_e : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
e : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF nd5 : ENTITY IS TRUE;
END nd5;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF nd5 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
SIGNAL e_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (e_ipd, e, tipd_e);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd, e_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd AND b_ipd AND c_ipd AND d_ipd AND e_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE),
4 => (e_ipd'last_event, tpd_e_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell nr2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY nr2 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "nr2";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF nr2 : ENTITY IS TRUE;
END nr2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF nr2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd OR b_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell nr3 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY nr3 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "nr3";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF nr3 : ENTITY IS TRUE;
END nr3;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF nr3 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd OR b_ipd OR c_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell nr4 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY nr4 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "nr4";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF nr4 : ENTITY IS TRUE;
END nr4;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF nr4 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd OR b_ipd OR c_ipd OR d_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell nr5 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY nr5 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "nr5";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_e_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_e : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
e : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF nr5 : ENTITY IS TRUE;
END nr5;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF nr5 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
SIGNAL e_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (e_ipd, e, tipd_e);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd, e_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd OR b_ipd OR c_ipd OR d_ipd OR e_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE),
4 => (e_ipd'last_event, tpd_e_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell or2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY or2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "or2";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF or2 : ENTITY IS TRUE;
END or2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF or2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd OR b_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell or3 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY or3 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "or3";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF or3 : ENTITY IS TRUE;
END or3;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF or3 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd OR b_ipd OR c_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell or4 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY or4 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "or4";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF or4 : ENTITY IS TRUE;
END or4;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF or4 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd OR b_ipd OR c_ipd OR d_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell or5 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY or5 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "or5";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_e_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_e : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
e : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF or5 : ENTITY IS TRUE;
END or5;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF or5 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
SIGNAL e_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (e_ipd, e, tipd_e);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd, e_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd OR b_ipd OR c_ipd OR d_ipd OR e_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE),
4 => (e_ipd'last_event, tpd_e_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell pfumx -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY pfumx IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "pfumx";
tpd_c0_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_alut_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_blut_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_alut : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_blut : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c0 : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
alut : IN std_logic;
blut : IN std_logic;
c0 : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF pfumx : ENTITY IS TRUE;
END pfumx;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF pfumx IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL alut_ipd : std_logic := 'X';
SIGNAL blut_ipd : std_logic := 'X';
SIGNAL c0_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (alut_ipd, alut, tipd_alut);
VitalWireDelay (blut_ipd, blut, tipd_blut);
VitalWireDelay (c0_ipd, c0, tipd_c0);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (alut_ipd, blut_ipd, c0_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := vitalmux
(data => (alut_ipd, blut_ipd),
dselect => (0 => c0_ipd));
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (c0_ipd'last_event, tpd_c0_z, TRUE),
1 => (alut_ipd'last_event, tpd_alut_z, TRUE),
2 => (blut_ipd'last_event, tpd_blut_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell strtup -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
ENTITY strtup IS
GENERIC (
TimingChecksOn : Boolean := TRUE;
XOn : Boolean := FALSE;
MsgOn : Boolean := FALSE;
InstancePath : String := "strtup");
PORT(
uclk : in std_logic);
ATTRIBUTE Vital_Level0 OF strtup : ENTITY IS TRUE;
END strtup ;
-- ARCHITECTURE body --
ARCHITECTURE V OF strtup IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
BEGIN
END V;
--
----- cell vhi -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY vhi IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "vhi");
PORT(
z : OUT std_logic := '1');
ATTRIBUTE Vital_Level0 OF vhi : ENTITY IS TRUE;
END vhi;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF vhi IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
-- empty
END BLOCK;
--------------------
-- behavior section
--------------------
z <= '1';
END v;
--
----- cell vlo -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY vlo IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "vlo");
PORT(
z : OUT std_logic := '0');
ATTRIBUTE Vital_Level0 OF vlo : ENTITY IS TRUE;
END vlo;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF vlo IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
-- empty
END BLOCK;
--------------------
-- behavior section
--------------------
z <= '0';
END v;
--
----- cell xnor2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xnor2 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "xnor2";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xnor2 : ENTITY IS TRUE;
END xnor2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xnor2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd XOR b_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xnor3 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xnor3 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "xnor3";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xnor3 : ENTITY IS TRUE;
END xnor3;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xnor3 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd XOR b_ipd XOR c_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xnor4 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xnor4 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "xnor4";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xnor4 : ENTITY IS TRUE;
END xnor4;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xnor4 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd XOR b_ipd XOR c_ipd XOR d_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xnor5 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xnor5 IS
GENERIC(
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "xnor5";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_e_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_e : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
e : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xnor5 : ENTITY IS TRUE;
END xnor5;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xnor5 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
SIGNAL e_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (e_ipd, e, tipd_e);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd, e_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := NOT (a_ipd XOR b_ipd XOR c_ipd XOR d_ipd XOR e_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE),
4 => (e_ipd'last_event, tpd_e_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xor2 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xor2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "xor2";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xor2 : ENTITY IS TRUE;
END xor2;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xor2 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd XOR b_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xor3 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xor3 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "xor3";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xor3 : ENTITY IS TRUE;
END xor3;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xor3 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd XOR b_ipd XOR c_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xor4 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xor4 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "xor4";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xor4 : ENTITY IS TRUE;
END xor4;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xor4 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd XOR b_ipd XOR c_ipd XOR d_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xor5 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xor5 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "xor5";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_e_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_e : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
e : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xor5 : ENTITY IS TRUE;
END xor5;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xor5 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
SIGNAL e_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (e_ipd, e, tipd_e);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd, e_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd XOR b_ipd XOR c_ipd XOR d_ipd XOR e_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE),
4 => (e_ipd'last_event, tpd_e_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xor11 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xor11 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "xor11";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_e_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_f_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_g_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_h_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_i_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_j_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_k_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_e : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_f : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_g : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_h : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_j : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_k : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a, b, c, d, e, f, g, h, i, j, k : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xor11 : ENTITY IS TRUE;
END xor11;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xor11 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
SIGNAL e_ipd : std_logic := 'X';
SIGNAL f_ipd : std_logic := 'X';
SIGNAL g_ipd : std_logic := 'X';
SIGNAL h_ipd : std_logic := 'X';
SIGNAL i_ipd : std_logic := 'X';
SIGNAL j_ipd : std_logic := 'X';
SIGNAL k_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (e_ipd, e, tipd_e);
VitalWireDelay (f_ipd, f, tipd_f);
VitalWireDelay (g_ipd, g, tipd_g);
VitalWireDelay (h_ipd, h, tipd_h);
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (j_ipd, j, tipd_j);
VitalWireDelay (k_ipd, k, tipd_k);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd, e_ipd, f_ipd,
g_ipd, h_ipd, i_ipd, j_ipd, k_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd XOR b_ipd XOR c_ipd XOR d_ipd XOR e_ipd xor
f_ipd XOR g_ipd XOR h_ipd XOR i_ipd XOR j_ipd XOR
k_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE),
4 => (e_ipd'last_event, tpd_e_z, TRUE),
5 => (f_ipd'last_event, tpd_f_z, TRUE),
6 => (g_ipd'last_event, tpd_g_z, TRUE),
7 => (h_ipd'last_event, tpd_h_z, TRUE),
8 => (i_ipd'last_event, tpd_i_z, TRUE),
9 => (j_ipd'last_event, tpd_j_z, TRUE),
10 => (k_ipd'last_event, tpd_k_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell xor21 -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY xor21 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "xor21";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_b_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_c_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_d_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_e_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_f_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_g_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_h_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_i_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_j_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_k_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_l_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_m_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_n_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_o_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_p_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_q_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_r_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_s_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_t_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_u_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_c : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_e : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_f : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_g : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_h : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_i : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_j : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_k : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_l : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_m : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_n : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_o : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_p : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_q : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_r : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_s : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_t : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_u : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a, b, c, d, e, f, g, h, i, j, k : IN std_logic;
l, m, n, o, p, q, r, s, t, u : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF xor21 : ENTITY IS TRUE;
END xor21;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF xor21 IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
SIGNAL b_ipd : std_logic := 'X';
SIGNAL c_ipd : std_logic := 'X';
SIGNAL d_ipd : std_logic := 'X';
SIGNAL e_ipd : std_logic := 'X';
SIGNAL f_ipd : std_logic := 'X';
SIGNAL g_ipd : std_logic := 'X';
SIGNAL h_ipd : std_logic := 'X';
SIGNAL i_ipd : std_logic := 'X';
SIGNAL j_ipd : std_logic := 'X';
SIGNAL k_ipd : std_logic := 'X';
SIGNAL l_ipd : std_logic := 'X';
SIGNAL m_ipd : std_logic := 'X';
SIGNAL n_ipd : std_logic := 'X';
SIGNAL o_ipd : std_logic := 'X';
SIGNAL p_ipd : std_logic := 'X';
SIGNAL q_ipd : std_logic := 'X';
SIGNAL r_ipd : std_logic := 'X';
SIGNAL s_ipd : std_logic := 'X';
SIGNAL t_ipd : std_logic := 'X';
SIGNAL u_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
VitalWireDelay (b_ipd, b, tipd_b);
VitalWireDelay (c_ipd, c, tipd_c);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (e_ipd, e, tipd_e);
VitalWireDelay (f_ipd, f, tipd_f);
VitalWireDelay (g_ipd, g, tipd_g);
VitalWireDelay (h_ipd, h, tipd_h);
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (j_ipd, j, tipd_j);
VitalWireDelay (k_ipd, k, tipd_k);
VitalWireDelay (l_ipd, l, tipd_l);
VitalWireDelay (m_ipd, m, tipd_m);
VitalWireDelay (n_ipd, n, tipd_n);
VitalWireDelay (o_ipd, o, tipd_o);
VitalWireDelay (p_ipd, p, tipd_p);
VitalWireDelay (q_ipd, q, tipd_q);
VitalWireDelay (r_ipd, r, tipd_r);
VitalWireDelay (s_ipd, s, tipd_s);
VitalWireDelay (t_ipd, t, tipd_t);
VitalWireDelay (u_ipd, u, tipd_u);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd, b_ipd, c_ipd, d_ipd, e_ipd, f_ipd,
g_ipd, h_ipd, i_ipd, j_ipd, k_ipd, l_ipd, m_ipd, n_ipd,
o_ipd, p_ipd, q_ipd, r_ipd, s_ipd, t_ipd, u_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := (a_ipd XOR b_ipd XOR c_ipd XOR d_ipd XOR e_ipd xor
f_ipd XOR g_ipd XOR h_ipd XOR i_ipd XOR j_ipd XOR
k_ipd XOR l_ipd XOR m_ipd XOR n_ipd XOR o_ipd xor
p_ipd) XOR (q_ipd XOR r_ipd XOR s_ipd XOR t_ipd XOR
u_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, tpd_a_z, TRUE),
1 => (b_ipd'last_event, tpd_b_z, TRUE),
2 => (c_ipd'last_event, tpd_c_z, TRUE),
3 => (d_ipd'last_event, tpd_d_z, TRUE),
4 => (e_ipd'last_event, tpd_e_z, TRUE),
5 => (f_ipd'last_event, tpd_f_z, TRUE),
6 => (g_ipd'last_event, tpd_g_z, TRUE),
7 => (h_ipd'last_event, tpd_h_z, TRUE),
8 => (i_ipd'last_event, tpd_i_z, TRUE),
9 => (j_ipd'last_event, tpd_j_z, TRUE),
10 => (k_ipd'last_event, tpd_k_z, TRUE),
11 => (l_ipd'last_event, tpd_l_z, TRUE),
12 => (m_ipd'last_event, tpd_m_z, TRUE),
13 => (n_ipd'last_event, tpd_n_z, TRUE),
14 => (o_ipd'last_event, tpd_o_z, TRUE),
15 => (p_ipd'last_event, tpd_p_z, TRUE),
16 => (q_ipd'last_event, tpd_q_z, TRUE),
17 => (r_ipd'last_event, tpd_r_z, TRUE),
18 => (s_ipd'last_event, tpd_s_z, TRUE),
19 => (t_ipd'last_event, tpd_t_z, TRUE),
20 => (u_ipd'last_event, tpd_u_z, TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell bufba -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
ENTITY bufba IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "bufba";
tpd_a_z : VitalDelayType01 := (0.01 ns, 0.01 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF bufba : ENTITY IS TRUE;
END bufba;
-- architecture body --
ARCHITECTURE v OF bufba IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (a_ipd, a, tipd_a);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : PROCESS (a_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
z_zd := VitalBUF(a_ipd);
----------------------
-- path delay section
----------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (a_ipd'last_event, (tpd_a_z), TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_MISC.vhd,v 1.1 2005/12/06 13:00:24 tame Exp $
--
--
----- cell dcs -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
-- entity declaration --
ENTITY dcs IS
GENERIC(
DCSMODE : String := "POS";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dcs";
tpd_clk0_dcsout : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_clk1_dcsout : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sel_dcsout : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_clk0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clk1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sel : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
clk0 : IN std_logic;
clk1 : IN std_logic;
sel : IN std_logic;
dcsout : OUT std_logic);
ATTRIBUTE Vital_Level0 OF dcs : ENTITY IS TRUE;
END dcs;
-- architecture body --
LIBRARY ieee;
USE ieee.vital_primitives.all;
ARCHITECTURE v OF dcs IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL clk0_ipd : std_logic := 'X';
SIGNAL clk1_ipd : std_logic := 'X';
SIGNAL sel_ipd : std_logic := 'X';
SIGNAL sel_int1 : std_logic := '0';
SIGNAL sel_int2 : std_logic := '0';
SIGNAL sel_int3 : std_logic_vector(1 downto 0) := "00";
SIGNAL dcsout_int1 : std_logic := '0';
SIGNAL sel_int4 : std_logic := '0';
SIGNAL sel_int5 : std_logic := '0';
SIGNAL sel_int6 : std_logic_vector(1 downto 0) := "00";
SIGNAL dcsout_int2 : std_logic := '0';
SIGNAL sel_int7 : std_logic := '0';
SIGNAL sel_int8 : std_logic := '0';
SIGNAL sel_int9 : std_logic := '0';
SIGNAL sel_int10 : std_logic := '0';
SIGNAL dcsout_int3 : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (clk1_ipd, clk1, tipd_clk1);
VitalWireDelay (sel_ipd, sel, tipd_sel);
END BLOCK;
--------------------
-- behavior section
--------------------
P1 : PROCESS (clk0_ipd, clk1_ipd)
BEGIN
IF (clk0_ipd'event and clk0_ipd = '0') THEN
IF (sel_ipd = '1') THEN
sel_int1 <= sel_ipd;
END IF;
-- ELSIF (sel_ipd = '0') THEN
IF (sel_int1 = '0') THEN
sel_int2 <= sel_int1;
END IF;
END IF;
IF (clk1_ipd'event and clk1_ipd = '0') THEN
IF (sel_ipd = '0') THEN
sel_int1 <= sel_ipd;
END IF;
-- ELSIF (sel_ipd = '1') THEN
IF (sel_int1 = '1') THEN
sel_int2 <= sel_int1;
END IF;
END IF;
END PROCESS;
sel_int3 <= (sel_int2, sel_int1);
P2 : PROCESS (clk0_ipd, clk1_ipd, sel_int3)
BEGIN
case sel_int3 is
when "00" => dcsout_int1 <= clk0_ipd;
when "01" => dcsout_int1 <= '0';
when "10" => dcsout_int1 <= '0';
when "11" => dcsout_int1 <= clk1_ipd;
when others => NULL;
end case;
END PROCESS;
P3 : PROCESS (clk0_ipd, clk1_ipd)
BEGIN
IF (clk0_ipd'event and clk0_ipd = '1') THEN
IF (sel_ipd = '1') THEN
sel_int4 <= sel_ipd;
END IF;
IF (sel_int4 = '0') THEN
sel_int5 <= sel_int4;
END IF;
END IF;
IF (clk1_ipd'event and clk1_ipd = '1') THEN
IF (sel_ipd = '0') THEN
sel_int4 <= sel_ipd;
END IF;
IF (sel_int4 = '1') THEN
sel_int5 <= sel_int4;
END IF;
END IF;
END PROCESS;
sel_int6 <= (sel_int5, sel_int4);
P4 : PROCESS (clk0_ipd, clk1_ipd, sel_int6)
BEGIN
case sel_int6 is
when "00" => dcsout_int2 <= clk0_ipd;
when "01" => dcsout_int2 <= '1';
when "10" => dcsout_int2 <= '1';
when "11" => dcsout_int2 <= clk1_ipd;
when others => NULL;
end case;
END PROCESS;
P7 : PROCESS (clk1_ipd)
BEGIN
IF (clk1_ipd'event and clk1_ipd = '0') THEN
sel_int7 <= sel_ipd;
END IF;
END PROCESS;
P8 : PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'event and clk0_ipd = '0') THEN
sel_int8 <= sel_ipd;
END IF;
END PROCESS;
P9 : PROCESS (clk1_ipd)
BEGIN
IF (clk1_ipd'event and clk1_ipd = '1') THEN
sel_int9 <= sel_ipd;
END IF;
END PROCESS;
P10 : PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'event and clk0_ipd = '1') THEN
sel_int10 <= sel_ipd;
END IF;
END PROCESS;
P11 : PROCESS (clk0_ipd, clk1_ipd, sel_ipd, sel_int7, sel_int8, sel_int9, sel_int10)
BEGIN
IF (DCSMODE = "HIGH_LOW") THEN
dcsout_int3 <= vitalmux
(data => (clk1_ipd, '0'),
dselect => (0 => sel_int7));
ELSIF (DCSMODE = "HIGH_HIGH") THEN
dcsout_int3 <= vitalmux
(data => (clk1_ipd, '1'),
dselect => (0 => sel_int9));
ELSIF (DCSMODE = "LOW_LOW") THEN
dcsout_int3 <= vitalmux
(data => ('0', clk0_ipd),
dselect => (0 => sel_int8));
ELSIF (DCSMODE = "LOW_HIGH") THEN
dcsout_int3 <= vitalmux
(data => ('1', clk0_ipd),
dselect => (0 => sel_int10));
ELSIF (DCSMODE = "CLK0") THEN
dcsout_int3 <= vitalmux
(data => (clk0_ipd, clk0_ipd),
dselect => (0 => sel_ipd));
ELSIF (DCSMODE = "CLK1") THEN
dcsout_int3 <= vitalmux
(data => (clk1_ipd, clk1_ipd),
dselect => (0 => sel_ipd));
END IF;
END PROCESS;
VitalBehavior : PROCESS (dcsout_int1, dcsout_int2, dcsout_int3)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS dcsout_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE dcsout_GlitchData : VitalGlitchDataType;
BEGIN
-------------------------
-- functionality section
-------------------------
IF (DCSMODE = "NEG") THEN
dcsout_zd := dcsout_int1;
ELSIF (DCSMODE = "POS") THEN
dcsout_zd := dcsout_int2;
ELSE
dcsout_zd := dcsout_int3;
END IF;
-----------------------------------
-- Path Delay Section.
-----------------------------------
VitalPathDelay01 (
OutSignal => dcsout,
OutSignalName => "dcsout",
OutTemp => dcsout_zd,
Paths => (0 => (clk0_ipd'last_event, tpd_clk0_dcsout, TRUE),
1 => (clk1_ipd'last_event, tpd_clk1_dcsout, TRUE),
2 => (sel_ipd'last_event, tpd_sel_dcsout, TRUE)),
GlitchData => dcsout_GlitchData,
Mode => OnDetect,
XOn => XOn,
MsgOn => MsgOn);
END PROCESS;
END v;
--******************************************************************
----- VITAL model for cell GENERIC_PLLB -----
--******************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use IEEE.VITAL_Timing.all;
library ec;
use ec.components.all;
-- entity declaration --
entity GENERIC_PLLB is
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "1";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
CLKOK_DIV : string := "2";
WAKE_ON_LOCK : string := "off";
DELAY_CNTL : string := "STATIC";
PHASEADJ : string := "0";
DUTY : string := "4";
lock_cyc : integer := 2;
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := True;
tpd_RST_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_CLKOP : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_CLKOK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_CLKI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns)
);
port(
CLKI : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
RST : in STD_ULOGIC := '0';
DDAMODE : in STD_ULOGIC;
DDAIZR : in STD_ULOGIC;
DDAILAG : in STD_ULOGIC;
DDAIDEL0 : in STD_ULOGIC;
DDAIDEL1 : in STD_ULOGIC;
DDAIDEL2 : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
CLKOS : out STD_ULOGIC;
CLKOK : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
DDAOZR : out STD_ULOGIC;
DDAOLAG : out STD_ULOGIC;
DDAODEL0 : out STD_ULOGIC;
DDAODEL1 : out STD_ULOGIC;
DDAODEL2 : out STD_ULOGIC
);
--attribute VITAL_LEVEL0 of GENERIC_PLLB : entity is FALSE;
end GENERIC_PLLB;
-- architecture body --
architecture V of GENERIC_PLLB is
attribute VITAL_LEVEL1 of V : architecture is FALSE;
SIGNAL CLKI_ipd : STD_ULOGIC := 'X';
SIGNAL RST_ipd : STD_ULOGIC := 'X';
CONSTANT input_frequency : REAL := str2real(FIN);
SIGNAL start_inclk : STD_LOGIC ;
SIGNAL clklock_half_period1 : TIME :=100 ns;
SIGNAL clklock_half_period0 : TIME :=100 ns;
SIGNAL clklock_half_period : TIME :=100 ns;
SIGNAL clklock_period : TIME :=100 ns;
SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
SIGNAL secd_delay_minus1 : TIME :=100 ns;
SIGNAL secd_delay_minus0 : TIME :=100 ns;
SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
SIGNAL clklock_last_rising_edge : TIME ;
SIGNAL clklock_last_falling_edge : TIME ;
SIGNAL clkop_err_0 : TIME := 0 ns;
SIGNAL clkop_err_1 : TIME := 0 ns;
SIGNAL clock_count : INTEGER := -1 ;
SIGNAL clock_f_count : INTEGER := -1 ;
SIGNAL clklock_lock : BOOLEAN := TRUE;
SIGNAL CLK_OUT_sig_d : std_logic := '0';
SIGNAL CLK_OUT_sig_d_not : std_logic := '0';
SIGNAL CLK_OUT_sig_3d : std_logic := '0';
SIGNAL CLK_OUT_sig_3d_not : std_logic := '0';
SIGNAL CLK_OUT_sig_d_start : std_logic := '0';
SIGNAL CLK_OUT_start : std_logic := '0';
SIGNAL CLK_OUT_plus_delay : std_logic := '0';
SIGNAL SEC_OUT_sig_d : std_logic := '0';
SIGNAL SEC_OUT_sig_d_not : std_logic := '0';
SIGNAL SEC_OUT_sig_3d : std_logic := '0';
SIGNAL SEC_OUT_sig_3d_not : std_logic := '0';
SIGNAL SEC_OUT_sig_d_start : std_logic := '0';
SIGNAL SEC_OUT_start : std_logic := '0';
SIGNAL SEC_OUT_plus_delay : std_logic := '0';
SIGNAL CLK_OUT_sig1 : std_logic := '0';
SIGNAL PLL_LOCK_plus : std_logic := '0';
SIGNAL PLL_LOCK_minus : std_logic := '0';
CONSTANT secdiv_p: integer := str2int(CLKOK_DIV);
CONSTANT clockboost: real := real(str2int(CLKFB_DIV)) / real(str2int(CLKI_DIV));
CONSTANT div_r: real := real(str2int(CLKI_DIV));
CONSTANT mult_r: real := real(str2int(CLKFB_DIV));
CONSTANT div_i: integer := str2int(CLKI_DIV);
CONSTANT mult_i: integer := str2int(CLKFB_DIV);
SIGNAL RST_int : STD_LOGIC:= '0';
SIGNAL RST_int_o : STD_LOGIC:= '0'; --071504
SIGNAL RST_int_o2 : STD_LOGIC:= '0'; --081504
SIGNAL clkp_half_period1 : TIME :=100 ns;
SIGNAL clkp_half_period0 : TIME :=100 ns;
SIGNAL phase_shift : TIME :=0 ns;
SIGNAL phase_shift_value : integer := 0;
CONSTANT duty_i: integer := str2int(duty);
CONSTANT phase_i: integer := str2int(PHASEADJ);
SIGNAL CLKP_OUT_sig_d : std_logic := '0';
SIGNAL CLKP_OUT_sig_d_not : std_logic := '0';
SIGNAL CLKP_OUT_sig_3d : std_logic := '0';
SIGNAL CLKP_OUT_sig_3d_not : std_logic := '0';
SIGNAL CLKP_OUT_plus_delay : std_logic := '0';
SIGNAL CLKP_OUT_sig_d_start : std_logic := '0';
SIGNAL CLKP_OUT_start : std_logic := '0';
SIGNAL pll_dly_user : integer := str2int(FDEL);
SIGNAL pll_dly_value : integer := 0;
SIGNAL pll_dly_values : integer := 0;
SIGNAL pll_dly_valued : integer := 0;
SIGNAL clklock_period_c1 : TIME := 0 ns;
SIGNAL clklock_period_c2 : TIME := 0 ns;
SIGNAL clklock_period_c3 : TIME := 0 ns;
SIGNAL clk_lock_o : std_logic := '1'; --071404
SIGNAL clk_lock_o2 : std_logic := '1'; --081504
SIGNAL clk_lock : std_logic := '1';
SIGNAL lock_int1 : std_logic;
SIGNAL tpd: time;
SIGNAL tpd_r1: time := 0 ns;
SIGNAL tpd_r2: time := 0 ns;
SIGNAL tpd_r3: time := 0 ns;
SIGNAL tpd_r4: time := 0 ns;
SIGNAL tpd_f1: time := 0 ns;
SIGNAL tpd_f2: time := 0 ns;
SIGNAL tpd_f3: time := 0 ns;
SIGNAL tpd_f4: time := 0 ns;
SIGNAL DDA_DLY : std_logic_vector(2 downto 0);
SIGNAL op_i, os_i, ok_i : integer := 0;
--------------------------------------------------------------------------------
signal old_clkop, old_clkos, old_clkok : std_logic;
signal new_clkop, new_clkos, new_clkok : std_logic;
--signal new_clkop_tmp, new_clkos_tmp, new_clkok_tmp : std_logic_vector(99 downto 0); --071304
signal use_new_clk_op, use_new_clk_os, use_new_clk_ok : std_logic := '0';
signal old_lock : std_logic;
SIGNAL CLKOP1 : std_logic := '0';
SIGNAL CLKOS1 : std_logic := '0';
SIGNAL clk_first_time : std_logic := '1';
SIGNAL fb_count : Integer := 0;
---------------signal clkop_period : time := 10 ns;
signal clkin_period : time := 10 ns; --071304
signal clkref_rise1 : time:=0 ns;
---------signal op_low2high : time:=0 ns;
signal ref2fb_dly : time:=0 ns;
signal ref2fb_dly_tmp : time:=0 ns;
signal fb_dly_rdy : std_logic := '0'; --071404
signal fb_dly_rdy_r1 : std_logic := '0'; --071404
signal fb_low2high: time:=0 ns;
signal fb_adjust : time:=0 ns;
signal fb_adjust_divide_by_100 : time:=0 ns; --071304
signal last_fb_adjust : time:=0 ns;
signal clkref : std_logic := '0';
signal rst_pause : time := 1 ns; --081504
type state_val is
( WAIT_OLD_LOCK_FALL, WAIT_OLD_LOCK_RISE,
WAIT_CLKREF_RISE1,
WAIT_CLKFB_RISE,
WAIT_NEW_CLKOP_FALL, WAIT_NEW_CLKOS_CLKOK_FALL,
WAIT_NEW_CLKOK_FALL, WAIT_NEW_CLKOS_FALL);
signal state: state_val := WAIT_OLD_LOCK_RISE;
SIGNAL clkin_half_period0 : TIME :=100 ns; --071304
SIGNAL clkin_half_period1 : TIME :=100 ns; --071304
---------------------------------------------------------------
BEGIN
---------------------------------------------------------------
------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------
process (old_lock, clkref, CLKFB, new_clkop, new_clkok, new_clkos)
variable ref2fb_dly_tmp : time := 0 ns;
begin
case state is
--when IDLE =>
when WAIT_OLD_LOCK_FALL =>
if (old_lock'event and old_lock = '0') then
state <= WAIT_OLD_LOCK_RISE;
use_new_clk_op <= '0';
use_new_clk_ok <= '0';
use_new_clk_os <= '0';
ref2fb_dly <= 0 ns;
fb_dly_rdy <= '0'; -- 071404
end if;
----------------------------------------------------
when WAIT_OLD_LOCK_RISE =>
if rising_edge (old_lock) then
state <= WAIT_CLKREF_RISE1;
end if;
----------------------------------------------------
when WAIT_CLKREF_RISE1 =>
if (old_lock'event and old_lock = '0') then
state <= WAIT_OLD_LOCK_RISE;
use_new_clk_op <= '0';
use_new_clk_ok <= '0';
use_new_clk_os <= '0';
ref2fb_dly <= 0 ns;
fb_dly_rdy <= '0'; -- 071404
elsif rising_edge(clkref) then
state <= WAIT_CLKFB_RISE;
clkref_rise1 <= now;
end if;
----------------------------------------------------
when WAIT_CLKFB_RISE =>
if (old_lock'event and old_lock = '0') then
state <= WAIT_OLD_LOCK_RISE;
use_new_clk_op <= '0';
use_new_clk_ok <= '0';
use_new_clk_os <= '0';
ref2fb_dly <= 0 ns;
fb_dly_rdy <= '0'; -- 071404
elsif rising_edge(CLKFB) then
state <= WAIT_NEW_CLKOP_FALL;
if now - clkref_rise1 /= clkin_period then
ref2fb_dly_tmp := now - clkref_rise1 ;
else
ref2fb_dly_tmp := 0 ns ;
end if;
if ( clkin_period - ref2fb_dly_tmp + tpd ) < 0 ns or
( clkin_period - ref2fb_dly_tmp ) < 0 ns then
assert false
report "Module EHXPLLB: Delay adjustment exceeds the clock period. Simulation Aborted!!!"
severity FAILURE;
else
ref2fb_dly <= ref2fb_dly_tmp;
fb_dly_rdy <= '1'; --071404
end if;
end if;
----------------------------------------------------
when WAIT_NEW_CLKOP_FALL =>
if (old_lock'event and old_lock = '0') then
state <= WAIT_OLD_LOCK_RISE;
use_new_clk_op <= '0';
use_new_clk_ok <= '0';
use_new_clk_os <= '0';
ref2fb_dly <= 0 ns;
fb_dly_rdy <= '0'; -- 071404
elsif falling_edge(new_clkop) then
use_new_clk_op <= '1';
------------------------------------------
if new_clkos = '0' and new_clkok ='0' then
state <= WAIT_OLD_LOCK_FALL;
use_new_clk_os <= '1';
use_new_clk_ok <= '1';
elsif (new_clkos = '0') then
state <= WAIT_NEW_CLKOK_FALL;
use_new_clk_os <= '1';
elsif (new_clkok = '0') then
state <= WAIT_NEW_CLKOS_FALL;
use_new_clk_ok <= '1';
else
state <= WAIT_NEW_CLKOS_CLKOK_FALL;
end if;
end if;
----------------------------------------------------
when WAIT_NEW_CLKOS_CLKOK_FALL =>
if (old_lock'event and old_lock = '0') then
state <= WAIT_OLD_LOCK_RISE;
use_new_clk_op <= '0';
use_new_clk_ok <= '0';
use_new_clk_os <= '0';
ref2fb_dly <= 0 ns;
fb_dly_rdy <= '0'; -- 071404
elsif falling_edge(new_clkos) or falling_edge (new_clkok) then
if (new_clkos ='0' and new_clkok = '0') then
state <= WAIT_OLD_LOCK_FALL;
use_new_clk_os <= '1';
use_new_clk_ok <= '1';
elsif (new_clkos = '0') then
state <= WAIT_NEW_CLKOK_FALL;
use_new_clk_os <= '1';
elsif (new_clkok = '0') then
state <= WAIT_NEW_CLKOS_FALL;
use_new_clk_ok <= '1';
end if;
end if;
----------------------------------------------------
when WAIT_NEW_CLKOS_FALL =>
if (old_lock'event and old_lock = '0') then
state <= WAIT_OLD_LOCK_RISE;
use_new_clk_op <= '0';
use_new_clk_ok <= '0';
use_new_clk_os <= '0';
ref2fb_dly <= 0 ns;
fb_dly_rdy <= '0'; -- 071404
elsif falling_edge(new_clkos) then
state <= WAIT_OLD_LOCK_FALL;
use_new_clk_os<= '1';
end if;
----------------------------------------------------
when WAIT_NEW_CLKOK_FALL =>
if (old_lock'event and old_lock = '0') then
state <= WAIT_OLD_LOCK_RISE;
use_new_clk_op <= '0';
use_new_clk_ok <= '0';
use_new_clk_os <= '0';
ref2fb_dly <= 0 ns;
fb_dly_rdy <= '0'; -- 071404
elsif falling_edge(new_clkok) then
state <= WAIT_OLD_LOCK_FALL;
use_new_clk_ok<= '1';
end if;
end case;
end process;
---------clkop_period <= clklock_half_period0 + clklock_half_period1 when old_lock = '1'
--------- else 10 ns;
clkin_period <= clkin_half_period0 + clkin_half_period1 when old_lock = '1' -- 071304
else 10 ns;
--fb_adjust <= clkin_period - ref2fb_dly when (ref2fb_dly /= 0 ns) else 0 ns; --071304
------------------------------------------------------------------
-- CLK GENERATION
------------------------------------------------------------------
--clkop
process
variable hp1: time := 0 ns;
variable hp0: time := 0 ns;
begin
wait on old_lock;
if (old_lock = '1') then
--wait until rising_edge(fb_dly_rdy);
--wait until rising_edge(CLKI_ipd);
wait until rising_edge(fb_dly_rdy_r1); --081804
wait for (clkin_period - ref2fb_dly + tpd);
while (old_lock = '1') loop
for op_i in 1 to mult_i loop
if (old_lock = '0') then
exit;
elsif (op_i = mult_i) then
hp1 := clklock_half_period1 + clkop_err_1 ;
hp0 := clklock_half_period0 + clkop_err_0 ;
else
hp1 := clklock_half_period1 ;
hp0 := clklock_half_period0;
end if;
new_clkop <= not(new_clkop) and old_lock;
wait for hp1;
new_clkop <= not(new_clkop) and old_lock;
wait for hp0;
end loop;
end loop;
------------------------------------------------
elsif (old_lock = '0') then
new_clkop <= '0';
end if;
end process;
--clkos
process
variable hp1: time := 0 ns;
variable hp0: time := 0 ns;
begin
wait on old_lock;
if (old_lock = '1') then
--wait until rising_edge(fb_dly_rdy);
--wait until rising_edge(CLKI_ipd);
wait until rising_edge(fb_dly_rdy_r1); --081804
wait for (clkin_period - ref2fb_dly + tpd + phase_shift);
while (old_lock = '1') loop
for os_i in 1 to mult_i loop
if (old_lock = '0') then
exit;
elsif (os_i = mult_i) then
hp1 := (clklock_half_period0 + clklock_half_period1 +
clkop_err_0 + clkop_err_1) * duty_i/8;
hp0 := (clklock_half_period0 + clklock_half_period1 +
clkop_err_0 + clkop_err_1) - hp1;
else
hp1 := (clklock_half_period0 + clklock_half_period1 ) * duty_i/8;
hp0 := (clklock_half_period0 + clklock_half_period1 ) - hp1;
end if;
new_clkos <= not(new_clkos) and old_lock;
wait for hp1;
new_clkos <= not(new_clkos) and old_lock;
wait for hp0;
--os_i <= os_i + 1;
end loop;
end loop;
------------------------------------------------
elsif (old_lock = '0') then
new_clkos <= '0';
end if;
end process;
--clkok
process
variable hp1: time := 0 ns;
variable hp0: time := 0 ns;
begin
wait on old_lock;
if (old_lock = '1') then
--wait until rising_edge(fb_dly_rdy);
--wait until rising_edge(CLKI_ipd);
wait until rising_edge(fb_dly_rdy_r1); --081804
wait for (clkin_period - ref2fb_dly + tpd);
while (old_lock = '1') loop
for ok_i in 1 to mult_i loop
if (old_lock = '0') then
exit;
elsif (ok_i = mult_i) then
hp1 := (clklock_half_period1 + clkop_err_1)* secdiv_p;
hp0 := (clklock_half_period0 + clkop_err_0)* secdiv_p;
else
hp1 := (clklock_half_period1 )* secdiv_p;
hp0 := (clklock_half_period0 )* secdiv_p;
end if;
new_clkok <= not(new_clkok) and old_lock;
wait for hp1;
new_clkok <= not(new_clkok) and old_lock;
wait for hp0;
end loop;
end loop;
------------------------------------------------
elsif (old_lock = '0') then
new_clkok <= '0';
end if;
end process;
------------------------------------------------------------------
clkref <= CLKI_ipd; --071404
old_clkop <= clkref; --071404
P100 : PROCESS (CLKFB)
BEGIN
IF (CLKFB'event and CLKFB = '1') THEN
fb_count <= fb_count + 1;
IF (fb_count = 3) THEN
clk_first_time <= '0';
END IF;
END IF;
END PROCESS;
CLKOP1 <= new_clkop when fb_dly_rdy = '1' and old_lock = '1' else old_clkop; --071404
S11 : PROCESS (CLKOP1, rst_int)
BEGIN
IF (clk_first_time = '1') THEN
CLKOP <= CLKOP1;
ELSIF (rst_int = '1') THEN
CLKOP <= '0';
ELSIF (rst_int = '0') THEN
CLKOP <= CLKOP1;
END IF;
END PROCESS;
old_clkos <= clkref;
CLKOS1 <= new_clkos when fb_dly_rdy = '1' and old_lock = '1' else old_clkos; --071404
S12 : PROCESS (CLKOS1, rst_int)
BEGIN
IF (clk_first_time = '1') THEN
CLKOS <= CLKOS1;
ELSIF (rst_int = '1') THEN
CLKOS <= '0';
ELSIF (rst_int = '0') THEN
CLKOS <= CLKOS1;
END IF;
END PROCESS;
old_clkok <= SEC_OUT_plus_delay and not RST_int;
CLKOK <= new_clkok when fb_dly_rdy = '1' and old_lock = '1' else '0'; --071404
old_lock <= PLL_LOCK_plus and not RST_int when tpd >= 0 ns else
PLL_LOCK_minus and not RST_int;
process (CLKI_ipd) --071404
begin
if rising_edge (CLKI_ipd) then
fb_dly_rdy_r1 <= fb_dly_rdy;
end if;
end process;
LOCK <= old_lock and fb_dly_rdy_r1; --071404
-------------------------------------------------------------------------------------
DDAOZR <= DDAIZR;
DDAOLAG <= DDAILAG;
DDA_DLY <= DDAIDEL2 & DDAIDEL1 & DDAIDEL0;
DDAODEL0 <= DDAIDEL0;
DDAODEL1 <= DDAIDEL1;
DDAODEL2 <= DDAIDEL2;
pll_dly_values <= pll_dly_user;
tpd <= 0.25 ns * pll_dly_value;
---------------------------------------------------------------------------
-- RST
---------------------------------------------------------------------------
process (old_lock)
begin
if (rising_edge(old_lock)) then
rst_pause <= (clklock_half_period0 + clklock_half_period1) * secdiv_p;
end if;
end process;
RST_int_o <= RST_ipd WHEN (RST_ipd = '0' or RST_ipd = '1') else
'0'; --081504
process --081504
begin
wait until rising_edge (RST_int_o);
--wait until rising_edge(CLKI_ipd);
RST_int_o2 <= '1';
wait for rst_pause;
wait until rising_edge(CLKI_ipd);
RST_int_o2 <= '0';
end process;
RST_int <= RST_int_o or RST_int_o2;
WireDelay : block
begin
VitalWireDelay (CLKI_ipd, CLKI, tipd_CLKI);
VitalWireDelay (RST_ipd, RST, tipd_RST);
end block;
static_dynamic : process(pll_dly_values,pll_dly_valued)
begin
if (DELAY_CNTL = "STATIC") then
pll_dly_value <= pll_dly_values;
elsif (DELAY_CNTL = "DYNAMIC") then
pll_dly_value <= pll_dly_valued;
end if;
end process;
----------------------------------------------------------------------------
edge_count: PROCESS
VARIABLE input_cycle : REAL;
VARIABLE real_cycle : REAL;
VARIABLE clkop_period0 : TIME;
VARIABLE clkop_period1 : TIME;
BEGIN
if (DDAMODE = '0') then
pll_dly_valued <= pll_dly_user;
elsif (DDAMODE = '1') then
if (DDAIZR = '1') then
pll_dly_valued <= 0;
elsif (DDAIZR = '0') then
if (DDAILAG = '1') then
case DDA_DLY is
when "111" => pll_dly_valued <= -8;
when "110" => pll_dly_valued <= -7;
when "101" => pll_dly_valued <= -6;
when "100" => pll_dly_valued <= -5;
when "011" => pll_dly_valued <= -4;
when "010" => pll_dly_valued <= -3;
when "001" => pll_dly_valued <= -2;
when "000" => pll_dly_valued <= -1;
when others => pll_dly_valued <= 0;
end case;
elsif (DDAILAG = '0') then
case DDA_DLY is
when "111" => pll_dly_valued <= 8;
when "110" => pll_dly_valued <= 7;
when "101" => pll_dly_valued <= 6;
when "100" => pll_dly_valued <= 5;
when "011" => pll_dly_valued <= 4;
when "010" => pll_dly_valued <= 3;
when "001" => pll_dly_valued <= 2;
when "000" => pll_dly_valued <= 1;
when others => pll_dly_valued <= 0;
end case;
end if;
end if;
end if;
case phase_i is
when 0 => phase_shift_value <= 0;
when 45 => phase_shift_value <= 1;
when 90 => phase_shift_value <= 2;
when 135 => phase_shift_value <= 3;
when 180 => phase_shift_value <= 4;
when 225 => phase_shift_value <= 5;
when 270 => phase_shift_value <= 6;
when 315 => phase_shift_value <= 7;
when others => phase_shift_value <= 0;
end case;
clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;
clklock_period <= clklock_half_period * 2;
phase_shift <= (clklock_half_period0 + clklock_half_period1) * phase_shift_value/8;
clkp_half_period1 <= (clklock_half_period0 + clklock_half_period1) * duty_i/8;
clkp_half_period0 <= (clklock_half_period0 + clklock_half_period1) * (8 - duty_i)/8;
WAIT UNTIL (CLKI_ipd'EVENT AND CLKI_ipd='1');
clklock_rising_edge_count <= clklock_rising_edge_count +1;
-- IF clklock_rising_edge_count = 0 THEN
clklock_last_rising_edge <= NOW;
start_inclk <= CLKI_ipd;
-- ELSE
-- IF clklock_rising_edge_count = 2 THEN
--clklock_half_period0 <= (NOW - clklock_last_falling_edge)/clockboost;
clkop_period0 := (NOW - clklock_last_falling_edge) *div_r/mult_r; --081504
clklock_half_period0 <= clkop_period0;
clkop_err_0 <= (NOW - clklock_last_falling_edge) *div_r -
clkop_period0 * mult_r;
clkin_half_period0 <= (NOW - clklock_last_falling_edge) ; --071304
input_cycle := 1000.0 / input_frequency;
real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
IF ( real_cycle < 0.9 * input_cycle OR
real_cycle > 1.1 * input_cycle ) THEN
ASSERT TRUE
REPORT " Input_Frequency Violation "
SEVERITY WARNING;
clklock_lock <= FALSE;
END IF;
-- elsif clklock_rising_edge_count = 2 THEN
clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
secd_delay_minus0 <= (NOW - clklock_last_falling_edge) + tpd;
-- END IF;
-- END IF;
WAIT UNTIL (CLKI_ipd'EVENT AND CLKI_ipd='0');
clklock_falling_edge_count <= clklock_falling_edge_count +1;
-- IF clklock_falling_edge_count = 0 THEN
clklock_last_falling_edge <= NOW;
--clklock_half_period1 <= (NOW - clklock_last_rising_edge)/clockboost;
clkop_period1 := (NOW - clklock_last_rising_edge) *div_r/mult_r; --081504
clklock_half_period1 <= clkop_period1;
clkop_err_1 <= (NOW - clklock_last_rising_edge) *div_r -
clkop_period1 * mult_r;
clkin_half_period1 <= (NOW - clklock_last_rising_edge) ; --071304
IF clklock_falling_edge_count = 2 THEN
clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
secd_delay_minus1 <= (NOW - clklock_last_rising_edge) + tpd;
END IF;
END PROCESS edge_count;
-------------------------------------------------------------------------------
ddy_change_r: PROCESS (clklock_rising_edge_count)
begin
tpd_r1 <= tpd;
tpd_r2 <= tpd_r1;
tpd_r3 <= tpd_r2;
tpd_r4 <= tpd_r3;
end process;
ddy_change_f: PROCESS (clklock_falling_edge_count)
begin
tpd_f1 <= tpd;
tpd_f2 <= tpd_f1;
tpd_f3 <= tpd_f2;
tpd_f4 <= tpd_f3;
end process;
--toggle: PROCESS (clklock_rising_edge_count)
toggle: PROCESS
BEGIN
WAIT ON clklock_rising_edge_count;
if (RST_int = '1' or clk_lock = '0') then
clock_count <= 0;
elsif (tpd_r1 /= tpd_r4) then
clock_count <= 0;
elsif clklock_rising_edge_count > lock_cyc + 1 and RST_int = '0' THEN
if(clockboost >1.0) then
FOR i IN 1 TO integer(2.0*clockboost) LOOP
clock_count <= clock_count + 1;
WAIT FOR clklock_half_period;
END LOOP;
else
clock_count <= clock_count + 1;
WAIT FOR (clklock_half_period);
end if;
ELSE
clock_count <= 0;
END IF;
END PROCESS toggle;
toggle_0: PROCESS
BEGIN
WAIT ON clklock_falling_edge_count;
if (RST_int = '1' or clk_lock = '0') then
clock_f_count <= 0;
elsif clklock_falling_edge_count > lock_cyc + 1 and RST_int = '0' THEN
if(clockboost >1.0) then
FOR i IN 1 TO integer(2.0*clockboost) LOOP
clock_f_count <= clock_f_count + 1;
WAIT FOR clklock_half_period;
END LOOP;
else
clock_f_count <= clock_f_count + 1;
WAIT FOR (clklock_half_period);
end if;
ELSE
clock_f_count <= 0;
END IF;
END PROCESS toggle_0;
lock_detect : process (CLKI_ipd,tpd_r1,tpd_r2,clklock_half_period)
begin
if (CLKI_ipd'event and CLKI_ipd = '1') THEN
clklock_period_c1 <= clklock_period_c2;
clklock_period_c2 <= clklock_period_c3;
clklock_period_c3 <= clklock_half_period;
if (clklock_period_c1 > 0 ps) then
if (clklock_period_c1 = clklock_period_c3) then
clk_lock_o <= '1'; --071404
else
if (clklock_falling_edge_count >5) then
clk_lock_o <= '0'; --071404
end if;
end if;
end if;
if (tpd_r1 /= tpd_r2) then
clk_lock_o <= '0'; --071404
end if;
end if;
end process;
process --081504
begin
wait until falling_edge (clk_lock_o);
--wait until rising_edge(CLKI_ipd);
clk_lock_o2 <= '0';
wait for rst_pause;
wait until rising_edge(CLKI_ipd);
clk_lock_o2 <= '1';
end process;
clk_lock <= clk_lock_o and clk_lock_o2;
gen_pll_lock_plus:process( clock_count, RST_int, clk_lock)
begin
if (RST_int = '1' or clk_lock = '0') then
PLL_LOCK_plus <= '0';
elsif (clock_count=1) then
PLL_LOCK_plus <= '1';
end if;
end process;
gen_pll_lock_minus:process ( clock_f_count, RST_int, clk_lock)
begin
if (RST_int = '1' or clk_lock = '0') then
PLL_LOCK_minus <= '0';
elsif (clock_f_count=1) then
PLL_LOCK_minus <= '1';
end if;
end process;
process(clock_count, tpd, RST_int, clk_lock)
begin
if( RST_int ='1') then
CLK_OUT_sig_d_start <='0';
SEC_OUT_sig_d_start <='0';
elsif(clk_lock = '0') then
CLK_OUT_sig_d_start <='0';
SEC_OUT_sig_d_start <='0';
elsif(clock_count = 1 and tpd >= 0 ns) then
CLK_OUT_sig_d_start <='1' after tpd;
SEC_OUT_sig_d_start <='1' after tpd;
end if;
end process;
process
begin
wait on CLK_OUT_sig_d_start;
while (CLK_OUT_sig_d_start = '1') LOOP
wait for clklock_half_period1;
CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
wait for clklock_half_period0;
CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
END LOOP;
end process;
process
begin
wait on CLK_OUT_start;
while (CLK_OUT_start = '1') LOOP
wait for clklock_half_period1;
CLK_OUT_sig_3d_not <= not CLK_OUT_sig_3d_not;
wait for clklock_half_period0;
CLK_OUT_sig_3d_not <= not CLK_OUT_sig_3d_not ;
END LOOP;
end process;
process
begin
wait on SEC_OUT_sig_d_start;
while (SEC_OUT_sig_d_start = '1') LOOP
wait for clklock_half_period1 * secdiv_p;
SEC_OUT_sig_d_not <= not SEC_OUT_sig_d_not;
wait for clklock_half_period0 * secdiv_p;
SEC_OUT_sig_d_not <= not SEC_OUT_sig_d_not ;
end LOOP;
end process;
process(clock_f_count,RST_int,clk_lock)
begin
-- wait until clklock_falling_edge_count >= lock_cyc + 1 and RST_int = '0';
if (RST_int = '1') then
SEC_OUT_start <= '0';
CLK_OUT_start <= '0';
CLKP_OUT_start <= '0';
elsif (clk_lock= '0') then
SEC_OUT_start <= '0';
CLK_OUT_start <= '0';
CLKP_OUT_start <= '0';
elsif (clock_f_count = 1) then
SEC_OUT_start <= '1' after clklock_half_period_minus_dly0;
CLK_OUT_start <= '1' after clklock_half_period_minus_dly0;
CLKP_OUT_start <= '1' after clklock_half_period_minus_dly0+phase_shift;
end if;
end process;
process
begin
wait on SEC_OUT_start;
while (SEC_OUT_start = '1') LOOP
wait for clklock_half_period1 * secdiv_p;
SEC_OUT_sig_3d_not <= not SEC_OUT_sig_3d_not;
wait for clklock_half_period0 * secdiv_p;
SEC_OUT_sig_3d_not <= not SEC_OUT_sig_3d_not ;
END LOOP;
end process;
--------Implement CLKOS
process(clock_count, tpd, phase_shift, RST_int, clk_lock)
begin
-- wait until clock_count = 1;
-- wait for phase_shift;
if( RST_int ='1') then
CLKP_OUT_sig_d_start <='0';
elsif(clk_lock = '0') then
CLKP_OUT_sig_d_start <='0';
elsif (clock_count = 1 and tpd >= 0 ns) then
CLKP_OUT_sig_d_start <='1' after (phase_shift + tpd);
end if;
end process;
process
begin
wait on CLKP_OUT_sig_d_start;
while (CLKP_OUT_sig_d_start = '1') LOOP
wait for clkp_half_period1;
CLKP_OUT_sig_d_not <= not CLKP_OUT_sig_d_not;
wait for clkp_half_period0;
CLKP_OUT_sig_d_not <= not CLKP_OUT_sig_d_not ;
END LOOP;
end process;
process
begin
wait on CLKP_OUT_start;
while ( CLKP_OUT_start = '1') LOOP
wait for clkp_half_period1;
CLKP_OUT_sig_3d_not <= not CLKP_OUT_sig_3d_not;
wait for clkp_half_period0;
CLKP_OUT_sig_3d_not <= not CLKP_OUT_sig_3d_not ;
END LOOP;
end process;
CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not;
CLK_OUT_sig_3d <= CLK_OUT_start and not CLK_OUT_sig_3d_not;
CLKP_OUT_sig_d <= CLKP_OUT_sig_d_start and not CLKP_OUT_sig_d_not;
CLKP_OUT_sig_3d <= CLKP_OUT_start and not CLKP_OUT_sig_3d_not;
SEC_OUT_sig_d <= SEC_OUT_sig_d_start and not SEC_OUT_sig_d_not;
SEC_OUT_sig_3d <= SEC_OUT_start and not SEC_OUT_sig_3d_not;
CLK_OUT_plus_delay <= CLK_OUT_sig_d when tpd >= 0 ns else
CLK_OUT_sig_3d;
CLKP_OUT_plus_delay <= CLKP_OUT_sig_d when tpd >= 0 ns else
CLKP_OUT_sig_3d;
SEC_OUT_plus_delay <= SEC_OUT_sig_d when tpd >= 0 ns else
SEC_OUT_sig_3d;
LOCK_int1 <= PLL_LOCK_plus and not RST_int when tpd >= 0 ns else
PLL_LOCK_minus and not RST_int;
end V;
configuration CFG_GENERIC_PLLB_V of GENERIC_PLLB is
for V
end for;
end CFG_GENERIC_PLLB_V;
--**********************************************************************
----- VITAL model for cell EPLLB -----
--**********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use IEEE.VITAL_Timing.all;
library ec;
use ec.components.all;
-- entity declaration --
entity EPLLB is
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "1";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
WAKE_ON_LOCK : string := "off";
lock_cyc : integer := 2;
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := True;
tpd_CLKI_CLKOP : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_CLKI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns)
);
port(
CLKI : in STD_ULOGIC;
RST : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
LOCK : out STD_ULOGIC
);
--attribute VITAL_LEVEL0 of EPLLB : entity is FALSE;
end EPLLB;
-- architecture body --
architecture V of EPLLB is
attribute VITAL_LEVEL1 of V : architecture is FALSE;
---------------------------------------------------------------------
-- Component Declaration
---------------------------------------------------------------------
component GENERIC_PLLB
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "1";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
CLKOK_DIV : string := "2";
WAKE_ON_LOCK : string := "off";
DELAY_CNTL : string := "STATIC";
PHASEADJ : string := "0";
DUTY : string := "4";
lock_cyc : integer := 2;
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := True;
tpd_RST_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_CLKOP : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_CLKOK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_CLKI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns)
);
port(
CLKI : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
RST : in STD_ULOGIC := '0';
DDAMODE : in STD_ULOGIC;
DDAIZR : in STD_ULOGIC;
DDAILAG : in STD_ULOGIC;
DDAIDEL0 : in STD_ULOGIC;
DDAIDEL1 : in STD_ULOGIC;
DDAIDEL2 : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
CLKOS : out STD_ULOGIC;
CLKOK : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
DDAOZR : out STD_ULOGIC;
DDAOLAG : out STD_ULOGIC;
DDAODEL0 : out STD_ULOGIC;
DDAODEL1 : out STD_ULOGIC;
DDAODEL2 : out STD_ULOGIC
);
end component;
signal open1,open2,open3,open4,open5,open6,open7 : std_logic;
signal gnd_sig : std_logic;
begin
-----------------------------------------------------------------------
gnd_sig <= '0';
GENERIC_PLLB_u1: GENERIC_PLLB
generic map (
FIN => FIN,
CLKI_DIV => CLKI_DIV ,
CLKOP_DIV => "1",
CLKFB_DIV => CLKFB_DIV ,
FDEL => FDEL,
FB_MODE => FB_MODE,
CLKOK_DIV => "2",
WAKE_ON_LOCK => WAKE_ON_LOCK,
DELAY_CNTL => "STATIC",
PHASEADJ => "0",
DUTY => "4",
lock_cyc => lock_cyc,
TimingChecksOn =>TimingChecksOn,
InstancePath => InstancePath,
Xon => Xon,
MsgOn =>MsgOn,
tpd_RST_LOCK => (0.0 ns, 0.0 ns),
tpd_CLKI_CLKOP => tpd_CLKI_CLKOP,
tpd_CLKI_LOCK => (0.0 ns, 0.0 ns),
tpd_CLKI_CLKOK => tpd_CLKI_LOCK,
tipd_CLKI => tipd_CLKI,
tipd_CLKFB => tipd_CLKFB,
tipd_RST => (0.000 ns, 0.000 ns)
)
port map(
CLKI => CLKI,
CLKFB => CLKFB,
RST => RST,
DDAMODE => gnd_sig,
DDAIZR => gnd_sig,
DDAILAG => gnd_sig,
DDAIDEL0 => gnd_sig,
DDAIDEL1 => gnd_sig,
DDAIDEL2 => gnd_sig,
CLKOP => CLKOP,
CLKOS => open1,
CLKOK => open2,
LOCK => LOCK,
DDAOZR => open3,
DDAOLAG => open4,
DDAODEL0 => open5,
DDAODEL1 => open6,
DDAODEL2 => open7
);
end V;
configuration CFG_EPLLB_V of EPLLB is
for V
end for;
end CFG_EPLLB_V;
--******************************************************************
----- VITAL model for cell EHXPLLB -----
--******************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use IEEE.VITAL_Timing.all;
library ec;
use ec.components.all;
-- entity declaration --
entity EHXPLLB is
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "1";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
CLKOK_DIV : string := "2";
WAKE_ON_LOCK : string := "off";
DELAY_CNTL : string := "STATIC";
PHASEADJ : string := "0";
DUTY : string := "4";
lock_cyc : integer := 2;
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := True;
tpd_RST_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_CLKOP : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_CLKOK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_CLKI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns)
);
port(
CLKI : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
RST : in STD_ULOGIC := '0';
DDAMODE : in STD_ULOGIC;
DDAIZR : in STD_ULOGIC;
DDAILAG : in STD_ULOGIC;
DDAIDEL0 : in STD_ULOGIC;
DDAIDEL1 : in STD_ULOGIC;
DDAIDEL2 : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
CLKOS : out STD_ULOGIC;
CLKOK : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
DDAOZR : out STD_ULOGIC;
DDAOLAG : out STD_ULOGIC;
DDAODEL0 : out STD_ULOGIC;
DDAODEL1 : out STD_ULOGIC;
DDAODEL2 : out STD_ULOGIC
);
--attribute VITAL_LEVEL0 of EHXPLLB : entity is FALSE;
end EHXPLLB;
-- architecture body --
architecture V of EHXPLLB is
attribute VITAL_LEVEL1 of V : architecture is FALSE;
---------------------------------------------------------------------
-- Component Declaration
---------------------------------------------------------------------
component GENERIC_PLLB
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "1";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
CLKOK_DIV : string := "2";
WAKE_ON_LOCK : string := "off";
DELAY_CNTL : string := "STATIC";
PHASEADJ : string := "0";
DUTY : string := "4";
lock_cyc : integer := 2;
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := True;
tpd_RST_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_CLKOP : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_LOCK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tpd_CLKI_CLKOK : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_CLKI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns)
);
port(
CLKI : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
RST : in STD_ULOGIC := '0';
DDAMODE : in STD_ULOGIC;
DDAIZR : in STD_ULOGIC;
DDAILAG : in STD_ULOGIC;
DDAIDEL0 : in STD_ULOGIC;
DDAIDEL1 : in STD_ULOGIC;
DDAIDEL2 : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
CLKOS : out STD_ULOGIC;
CLKOK : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
DDAOZR : out STD_ULOGIC;
DDAOLAG : out STD_ULOGIC;
DDAODEL0 : out STD_ULOGIC;
DDAODEL1 : out STD_ULOGIC;
DDAODEL2 : out STD_ULOGIC
);
end component;
begin
-----------------------------------------------------------------------
GENERIC_PLLB_u2: GENERIC_PLLB
generic map (
FIN => FIN,
CLKI_DIV => CLKI_DIV ,
CLKOP_DIV => CLKOP_DIV,
CLKFB_DIV => CLKFB_DIV ,
FDEL => FDEL,
FB_MODE => FB_MODE,
CLKOK_DIV => CLKOK_DIV,
WAKE_ON_LOCK => WAKE_ON_LOCK,
DELAY_CNTL => DELAY_CNTL,
PHASEADJ => PHASEADJ,
DUTY => DUTY,
lock_cyc => lock_cyc,
TimingChecksOn =>TimingChecksOn,
InstancePath => InstancePath,
Xon => Xon,
MsgOn =>MsgOn,
tpd_RST_LOCK => tpd_RST_LOCK,
tpd_CLKI_CLKOP => tpd_CLKI_CLKOP,
tpd_CLKI_LOCK => tpd_CLKI_LOCK,
tpd_CLKI_CLKOK => tpd_CLKI_LOCK,
tipd_CLKI => tipd_CLKI,
tipd_CLKFB => tipd_CLKFB,
tipd_RST => tipd_RST
)
port map(
CLKI => CLKI,
CLKFB => CLKFB,
RST => RST,
DDAMODE => DDAMODE,
DDAIZR => DDAIZR,
DDAILAG => DDAILAG,
DDAIDEL0 => DDAIDEL0,
DDAIDEL1 => DDAIDEL1,
DDAIDEL2 => DDAIDEL2,
CLKOP => CLKOP,
CLKOS => CLKOS,
CLKOK => CLKOK,
LOCK => LOCK,
DDAOZR => DDAOZR,
DDAOLAG => DDAOLAG,
DDAODEL0 => DDAODEL0,
DDAODEL1 => DDAODEL1,
DDAODEL2 => DDAODEL2
);
end V;
configuration CFG_EHXPLLB_V of EHXPLLB is
for V
end for;
end CFG_EHXPLLB_V;
--*********************************************************************
----- CELL MULT2 -----
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity MULT2 is
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := False;
tpd_A0_P0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A1_P0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A2_P1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A3_P1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B0_P0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B1_P0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B2_P1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B3_P1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_CI_P0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_CI_P1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A0_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A1_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A2_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A3_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B0_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B1_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B2_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_B3_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_CI_CO : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns));
port(
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
B2 : in STD_ULOGIC;
B3 : in STD_ULOGIC;
CI : in STD_ULOGIC;
P0 : out STD_ULOGIC;
P1 : out STD_ULOGIC;
CO : out STD_ULOGIC);
attribute VITAL_LEVEL0 of MULT2 : entity is TRUE;
end MULT2;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture V of MULT2 is
attribute VITAL_LEVEL1 of V : architecture is TRUE;
SIGNAL A0_ipd : STD_ULOGIC := 'X';
SIGNAL A1_ipd : STD_ULOGIC := 'X';
SIGNAL A2_ipd : STD_ULOGIC := 'X';
SIGNAL A3_ipd : STD_ULOGIC := 'X';
SIGNAL B0_ipd : STD_ULOGIC := 'X';
SIGNAL B1_ipd : STD_ULOGIC := 'X';
SIGNAL B2_ipd : STD_ULOGIC := 'X';
SIGNAL B3_ipd : STD_ULOGIC := 'X';
SIGNAL CI_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A0_ipd, A0, tipd_A0);
VitalWireDelay (A1_ipd, A1, tipd_A1);
VitalWireDelay (A2_ipd, A2, tipd_A2);
VitalWireDelay (A3_ipd, A3, tipd_A3);
VitalWireDelay (B0_ipd, B0, tipd_B0);
VitalWireDelay (B1_ipd, B1, tipd_B1);
VitalWireDelay (B2_ipd, B2, tipd_B2);
VitalWireDelay (B3_ipd, B3, tipd_B3);
VitalWireDelay (CI_ipd, CI, tipd_CI);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A0_ipd, B0_ipd, A1_ipd, B1_ipd, A2_ipd, B2_ipd, A3_ipd, B3_ipd, CI_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 3) := (others => 'X');
ALIAS P0_zd : STD_LOGIC is Results(1);
ALIAS P1_zd : STD_LOGIC is Results(2);
ALIAS CO_zd : STD_LOGIC is Results(3);
-- output glitch detection variables
VARIABLE P0_GlitchData : VitalGlitchDataType;
VARIABLE P1_GlitchData : VitalGlitchDataType;
VARIABLE CO_GlitchData : VitalGlitchDataType;
VARIABLE C_int : STD_LOGIC := 'X';
begin
-------------------------
-- Functionality Section
-------------------------
P0_zd := ((B0_ipd) AND (A0_ipd)) XOR ((B1_ipd) AND (A1_ipd)) XOR (CI_ipd);
C_int :=
(A0_ipd AND B0_ipd AND A1_ipd AND B1_ipd) OR (A0_ipd AND B0_ipd AND CI_ipd) OR (A1_ipd AND B1_ipd AND CI_ipd);
P1_zd := ((B2_ipd) AND (A2_ipd)) XOR ((B3_ipd) AND (A3_ipd)) XOR (C_int);
CO_zd :=
(A2_ipd AND B2_ipd AND A3_ipd AND B3_ipd) OR (A2_ipd AND B2_ipd AND C_int) OR (A3_ipd AND B3_ipd AND C_int);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => P0,
GlitchData => P0_GlitchData,
OutSignalName => "P0",
OutTemp => P0_zd,
Paths => (0 => (A0_ipd'last_event, tpd_A0_P0, TRUE),
1 => (A1_ipd'last_event, tpd_A1_P0, TRUE),
2 => (B0_ipd'last_event, tpd_B0_P0, TRUE),
3 => (B1_ipd'last_event, tpd_B1_P0, TRUE),
4 => (CI_ipd'last_event, tpd_CI_P0, TRUE)),
Mode => OnDetect,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
VitalPathDelay01 (
OutSignal => P1,
GlitchData => P1_GlitchData,
OutSignalName => "P1",
OutTemp => P1_zd,
Paths => (0 => (A2_ipd'last_event, tpd_A2_P1, TRUE),
1 => (A3_ipd'last_event, tpd_A3_P1, TRUE),
2 => (B2_ipd'last_event, tpd_B2_P1, TRUE),
3 => (B3_ipd'last_event, tpd_B3_P1, TRUE),
4 => (CI_ipd'last_event, tpd_CI_P1, TRUE)),
Mode => OnDetect,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
VitalPathDelay01 (
OutSignal => CO,
GlitchData => CO_GlitchData,
OutSignalName => "CO",
OutTemp => CO_zd,
Paths => (0 => (A0_ipd'last_event, tpd_A0_CO, TRUE),
1 => (A1_ipd'last_event, tpd_A1_CO, TRUE),
2 => (A2_ipd'last_event, tpd_A2_CO, TRUE),
3 => (A3_ipd'last_event, tpd_A3_CO, TRUE),
4 => (B0_ipd'last_event, tpd_B0_CO, TRUE),
5 => (B1_ipd'last_event, tpd_B1_CO, TRUE),
6 => (B2_ipd'last_event, tpd_B2_CO, TRUE),
7 => (B3_ipd'last_event, tpd_B3_CO, TRUE),
8 => (CI_ipd'last_event, tpd_CI_CO, TRUE)),
Mode => OnDetect,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end V;
configuration CFG_MULT2_V of MULT2 is
for V
end for;
end CFG_MULT2_V;
--
----- cell iddrxb -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
ENTITY iddrxb IS
GENERIC (
REGSET : string := "RESET";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "iddrxb";
-- propagation delays
tpd_sclk_qa : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_sclk_qb : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_d_eclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_d_eclk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_lsr_eclk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_lsr_eclk_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_d : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ce : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_lsr : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_eclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_sclk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ddrclkpol : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- pulse width constraints
tperiod_eclk : VitalDelayType := 0.001 ns;
tpw_eclk_posedge : VitalDelayType := 0.001 ns;
tpw_eclk_negedge : VitalDelayType := 0.001 ns;
tperiod_sclk : VitalDelayType := 0.001 ns;
tpw_sclk_posedge : VitalDelayType := 0.001 ns;
tpw_sclk_negedge : VitalDelayType := 0.001 ns;
tperiod_lsr : VitalDelayType := 0.001 ns;
tpw_lsr_posedge : VitalDelayType := 0.001 ns;
tpw_lsr_negedge : VitalDelayType := 0.001 ns);
PORT (
d : IN std_logic;
ce : IN std_logic;
eclk : IN std_logic;
sclk : IN std_logic;
lsr : IN std_logic;
ddrclkpol : IN std_logic;
qa : OUT std_logic;
qb : OUT std_logic);
ATTRIBUTE Vital_Level0 OF iddrxb : ENTITY IS TRUE;
END iddrxb ;
-- architecture body --
ARCHITECTURE v OF iddrxb IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL d_ipd : std_logic := '0';
SIGNAL ce_ipd : std_logic := '0';
SIGNAL eclk_ipd : std_logic := '0';
SIGNAL sclk_ipd : std_logic := '0';
SIGNAL lsr_ipd : std_logic := '0';
SIGNAL ddrclkpol_ipd : std_logic := '0';
SIGNAL QP : std_logic := '0';
SIGNAL QN : std_logic := '0';
SIGNAL QP_n : std_logic := '0';
SIGNAL QPreg : std_logic := '0';
SIGNAL QNreg : std_logic := '0';
SIGNAL sclk_pol : std_logic := '0';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(d_ipd, d, tipd_d);
VitalWireDelay(ce_ipd, ce, tipd_ce);
VitalWireDelay(eclk_ipd, eclk, tipd_eclk);
VitalWireDelay(sclk_ipd, sclk, tipd_sclk);
VitalWireDelay(lsr_ipd, lsr, tipd_lsr);
VitalWireDelay(ddrclkpol_ipd, ddrclkpol, tipd_ddrclkpol);
END BLOCK;
--------------------
-- behavior section
--------------------
S1 : PROCESS (sclk_ipd, ddrclkpol_ipd)
BEGIN
IF (ddrclkpol_ipd = '1') THEN
sclk_pol <= not sclk_ipd;
ELSIF (ddrclkpol_ipd = '0') THEN
sclk_pol <= sclk_ipd;
END IF;
END PROCESS;
P1 : PROCESS (eclk_ipd)
BEGIN
IF (eclk_ipd = 'X') THEN
IF (QP /= d_ipd) THEN
QP <= 'X';
END IF;
ELSIF (eclk_ipd'event and eclk_ipd'last_value = '0' and eclk_ipd = '1') THEN
QP <= d_ipd;
END IF;
END PROCESS;
P2 : PROCESS (eclk_ipd)
BEGIN
IF (eclk_ipd = 'X') THEN
IF (QP_n /= QP) THEN
QP_n <= 'X';
END IF;
IF (QN /= d_ipd) THEN
QN <= 'X';
END IF;
ELSIF (eclk_ipd'event and eclk_ipd'last_value = '1' and eclk_ipd = '0') THEN
QP_n <= QP;
QN <= d_ipd;
END IF;
END PROCESS;
P3 : PROCESS (sclk_pol)
BEGIN
IF (sclk_pol = 'X') THEN
IF (QPreg /= QP_n) THEN
QPreg <= 'X';
END IF;
IF (QNreg /= QN) THEN
QNreg <= 'X';
END IF;
ELSIF (sclk_pol'event and sclk_pol'last_value = '0' and sclk_pol = '1') THEN
IF (lsr_ipd = '1') THEN
IF (REGSET = "RESET") THEN
QPreg <= '0';
QNreg <= '0';
ELSIF (REGSET = "SET") THEN
QPreg <= '1';
QNreg <= '1';
END IF;
ELSIF (lsr_ipd = '0') THEN
QPreg <= QP_n;
QNreg <= QN;
END IF;
END IF;
END PROCESS;
VitalBehavior : PROCESS (QPreg, QNreg)
-- timing check results
VARIABLE tviol_eclk : X01 := '0';
VARIABLE tviol_d : X01 := '0';
VARIABLE tviol_lsr : X01 := '0';
VARIABLE d_eclk_TimingDatash : VitalTimingDataType;
VARIABLE lsr_eclk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_eclk : VitalPeriodDataType;
VARIABLE periodcheckinfo_sclk : VitalPeriodDataType;
-- functionality results
VARIABLE violation : X01 := '0';
VARIABLE results : std_logic_vector(1 to 2) := (others => 'X');
ALIAS qa_zd : std_ulogic IS results(1);
ALIAS qb_zd : std_ulogic IS results(2);
-- output glitch detection VARIABLEs
VARIABLE qa_GlitchData : VitalGlitchDataType;
VARIABLE qb_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => d_ipd, TestSignalName => "d",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_d_eclk_noedge_posedge,
SetupLow => tsetup_d_eclk_noedge_posedge,
HoldHigh => thold_d_eclk_noedge_posedge,
HoldLow => thold_d_eclk_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => d_eclk_timingdatash,
Violation => tviol_d, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => lsr_ipd, TestSignalName => "lsr",
RefSignal => eclk_ipd, RefSignalName => "eclk",
SetupHigh => tsetup_lsr_eclk_noedge_posedge,
SetupLow => tsetup_lsr_eclk_noedge_posedge,
HoldHigh => thold_lsr_eclk_noedge_posedge,
HoldLow => thold_lsr_eclk_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => lsr_eclk_timingdatash,
Violation => tviol_lsr, MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
qa_zd := VitalBUF(QPreg);
qb_zd := VitalBUF(QNreg);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => qa,
OutSignalName => "qa",
OutTemp => qa_zd,
Paths => (0 => (inputchangetime => sclk_ipd'last_event,
pathdelay => tpd_sclk_qa,
pathcondition => TRUE)),
GlitchData => qa_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => qb,
OutSignalName => "qb",
OutTemp => qb_zd,
Paths => (0 => (inputchangetime => sclk_pol'last_event,
pathdelay => tpd_sclk_qb,
pathcondition => TRUE)),
GlitchData => qb_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
------CELL ODDRXB------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
entity ODDRXB is
GENERIC (
REGSET : string := "RESET";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "oddrxb";
-- propagation delays
tpd_clk_q : VitalDelayType01 := (0.001 ns, 0.001 ns);
-- setup and hold constraints
tsetup_da_clk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_da_clk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_db_clk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_db_clk_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_lsr_clk_noedge_posedge : VitalDelayType := 0.0 ns;
thold_lsr_clk_noedge_posedge : VitalDelayType := 0.0 ns;
-- input SIGNAL delays
tipd_da : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_db : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_lsr : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clk : VitalDelayType01 := (0.0 ns, 0.0 ns));
port(
da : in STD_LOGIC;
db : in STD_LOGIC;
clk : in STD_LOGIC;
lsr : in STD_LOGIC;
q : out STD_LOGIC
);
attribute VITAL_LEVEL0 of ODDRXB : entity is TRUE;
end ODDRXB;
-- architecture body --
architecture V of ODDRXB is
attribute VITAL_LEVEL0 of V : architecture is TRUE;
SIGNAL da_ipd : std_logic := '0';
SIGNAL db_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL lsr_ipd : std_logic := '0';
SIGNAL QP : std_logic := '0';
SIGNAL QN : std_logic := '0';
begin
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(da_ipd, da, tipd_da);
VitalWireDelay(db_ipd, db, tipd_db);
VitalWireDelay(clk_ipd, clk, tipd_clk);
VitalWireDelay(lsr_ipd, lsr, tipd_lsr);
END BLOCK;
--------------------
-- behavior section
--------------------
P1: PROCESS(clk_ipd)
BEGIN
IF (clk_ipd = 'X') THEN
IF (QN /= db_ipd) THEN
QN <= 'X';
END IF;
ELSIF (clk_ipd'event and clk_ipd'last_value = '0' and clk_ipd = '1') THEN
IF (lsr_ipd = '1') THEN
IF (REGSET = "RESET") THEN
QN <= '0';
ELSIF (REGSET = "SET") THEN
QN <= '1';
END IF;
ELSE
QN <= db_ipd;
END IF;
END IF;
END PROCESS;
P2 : PROCESS(clk_ipd, da_ipd)
begin
if (clk_ipd = '0') then
QP <= da_ipd;
else
QP <= QP;
end if;
end process;
VitalBehavior : PROCESS (clk_ipd, QP, QN)
-- timing check results
VARIABLE tviol_clk : X01 := '0';
VARIABLE tviol_da : X01 := '0';
VARIABLE tviol_db : X01 := '0';
VARIABLE tviol_lsr : X01 := '0';
VARIABLE da_clk_TimingDatash : VitalTimingDataType;
VARIABLE db_clk_TimingDatash : VitalTimingDataType;
VARIABLE lsr_clk_TimingDatash : VitalTimingDataType;
VARIABLE periodcheckinfo_clk : VitalPeriodDataType;
-- functionality results
VARIABLE violation : X01 := '0';
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS q_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE q_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- timing check section
------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => da_ipd, TestSignalName => "da",
RefSignal => clk_ipd, RefSignalName => "clk",
SetupHigh => tsetup_da_clk_noedge_posedge,
SetupLow => tsetup_da_clk_noedge_posedge,
HoldHigh => thold_da_clk_noedge_posedge,
HoldLow => thold_da_clk_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => da_clk_timingdatash,
Violation => tviol_da, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => db_ipd, TestSignalName => "db",
RefSignal => clk_ipd, RefSignalName => "clk",
SetupHigh => tsetup_db_clk_noedge_posedge,
SetupLow => tsetup_db_clk_noedge_posedge,
HoldHigh => thold_db_clk_noedge_posedge,
HoldLow => thold_db_clk_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => db_clk_timingdatash,
Violation => tviol_db, MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => lsr_ipd, TestSignalName => "lsr",
RefSignal => clk_ipd, RefSignalName => "clk",
SetupHigh => tsetup_lsr_clk_noedge_posedge,
SetupLow => tsetup_lsr_clk_noedge_posedge,
HoldHigh => thold_lsr_clk_noedge_posedge,
HoldLow => thold_lsr_clk_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/', MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath, TimingData => lsr_clk_timingdatash,
Violation => tviol_lsr, MsgSeverity => warning);
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
q_zd := vitalmux
(data => (QP, QN),
dselect => (0 => clk_ipd));
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (inputchangetime => clk_ipd'last_event,
pathdelay => tpd_clk_q,
pathcondition => TRUE)),
GlitchData => q_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
configuration CFG_ODDRXB_V of ODDRXB is
for V
end for;
end CFG_ODDRXB_V;
--*********************************************************************
------CELL DQSDLL------
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
-- entity declaration --
entity DQSDLL is
generic(LOCK_CYC : integer := 2;
DEL_ADJ : string := "PLUS";
DEL_VAL : string := "0";
LOCK_SENSITIVITY : string := "LOW");
port(
CLK : in STD_ULOGIC;
RST : in STD_ULOGIC;
UDDCNTL : in STD_ULOGIC;
LOCK : out STD_ULOGIC;
DQSDEL : out STD_ULOGIC
);
attribute VITAL_LEVEL0 of DQSDLL : entity is FALSE;
end DQSDLL;
-- architecture body --
architecture V of DQSDLL is
attribute VITAL_LEVEL0 of V : architecture is FALSE;
signal RST_int : std_logic;
signal UDDCNTL_int : std_logic;
signal LOCK_int : std_logic;
signal DQSDEL_int : std_logic;
signal clkin_in : std_logic;
signal clk_rising_edge_count : integer := 0;
begin
clkin_in <= VitalBUF(CLK);
RST_int <= VitalBUF(RST);
UDDCNTL_int <= VitalBUF(UDDCNTL);
LOCK <= VitalBUF(LOCK_int);
DQSDEL <= VitalBUF(DQSDEL_int);
process(clkin_in, RST_int)
begin
if (RST_int = '1') then
clk_rising_edge_count <= 0;
elsif (clkin_in'event and clkin_in = '1') then
clk_rising_edge_count <= clk_rising_edge_count + 1;
end if;
end process;
process(clk_rising_edge_count, RST_int)
begin
if (RST_int = '1') then
LOCK_int <= '0';
elsif (clk_rising_edge_count > LOCK_CYC) then
LOCK_int <= '1';
end if;
end process;
process(LOCK_int, UDDCNTL_int, RST_int)
begin
if (RST_int = '1') then
DQSDEL_int <= '0';
elsif (UDDCNTL_int = '1') then
DQSDEL_int <= LOCK_int;
else
DQSDEL_int <= DQSDEL_int;
end if;
end process;
end V;
configuration CFG_DQSDLL_V of DQSDLL is
for V
end for;
end CFG_DQSDLL_V;
------cell dqsbufb------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.components.all;
-- entity declaration --
ENTITY dqsbufb IS
GENERIC(
DEL_ADJ : String := "PLUS";
DEL_VAL : String := "0";
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dqsbufb";
tipd_dqsi : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clk : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_read : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dqsdel : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
dqsi : IN std_logic;
clk : IN std_logic;
read : IN std_logic;
dqsdel : IN std_logic;
dqso : OUT std_logic;
ddrclkpol : OUT std_logic;
dqsc : OUT std_logic;
prmbdet : OUT std_logic
);
ATTRIBUTE vital_level0 OF dqsbufb : ENTITY IS TRUE;
END dqsbufb;
-- architecture body --
architecture V of DQSBUFB is
ATTRIBUTE vital_level0 OF v : ARCHITECTURE IS TRUE;
---
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
---
SIGNAL dqsi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL read_ipd : std_logic := '0';
SIGNAL dqsdel_ipd : std_logic := '0';
SIGNAL quarter_period : time := 0 ns;
SIGNAL clk_last_rising_edge : time := 0 ns;
SIGNAL A, C : std_logic := '0';
SIGNAL B, D, E : std_logic := '0';
SIGNAL A_inv, C_inv : std_logic := '0';
SIGNAL B_inv, D_inv, E_inv : std_logic := '0';
SIGNAL DDRCLKPOL_int : std_logic := '0';
SIGNAL CLKP : std_logic := '0';
SIGNAL DQSO_int : std_logic := '0';
SIGNAL DQSC_int : std_logic := '0';
SIGNAL DQSO_int1 : std_logic := '0';
SIGNAL PRMBDET_int : std_logic := '0';
SIGNAL DQSO_int0 : std_logic := '0';
SIGNAL DQSO_int2 : std_logic := '0';
SIGNAL clk_rising_edge_count : integer := 0;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(dqsi_ipd, dqsi, tipd_dqsi);
VitalWireDelay(clk_ipd, clk, tipd_clk);
VitalWireDelay(read_ipd, read, tipd_read);
VitalWireDelay(dqsdel_ipd, dqsdel, tipd_dqsdel);
END BLOCK;
--------------------
-- BEHAVIOR SECTION
--------------------
inst10: or2 PORT MAP (a=>read_ipd, b=>A, z=>C_inv);
inst11: inv PORT MAP (a=>C_inv, z=>C);
inst12: or2 PORT MAP (a=>C, b=>D, z=>A_inv);
inst13: inv PORT MAP (a=>A_inv, z=>A);
inst14: or2 PORT MAP (a=>D, b=>E, z=>B_inv);
inst15: inv PORT MAP (a=>B_inv, z=>B);
inst16: or2 PORT MAP (a=>C, b=>PRMBDET_int, z=>E_inv);
inst17: inv PORT MAP (a=>E_inv, z=>E);
inst18: or3 PORT MAP (a=>B, b=>read_ipd, c=>PRMBDET_int, z=>D_inv);
inst19: inv PORT MAP (a=>D_inv, z=>D);
P1 : PROCESS (dqsi_ipd)
BEGIN
IF (dqsi_ipd = 'X') THEN
PRMBDET_int <= '1';
ELSE
PRMBDET_int <= dqsi_ipd;
END IF;
END PROCESS;
P2 : PROCESS (D)
BEGIN
IF (D'event and D = '0') THEN
DDRCLKPOL_int <= clk_ipd;
END IF;
END PROCESS;
P3 : PROCESS (clk_ipd, DDRCLKPOL_int)
BEGIN
IF (DDRCLKPOL_int = '0') THEN
CLKP <= clk_ipd;
ELSIF (DDRCLKPOL_int = '1') THEN
CLKP <= not clk_ipd;
END IF;
END PROCESS;
P4 : PROCESS (clk_ipd)
BEGIN
IF (clk_ipd'event and clk_ipd = '1') THEN
clk_rising_edge_count <= clk_rising_edge_count + 1;
clk_last_rising_edge <= NOW;
END IF;
END PROCESS;
P5 : PROCESS (clk_ipd)
BEGIN
IF (clk_ipd'event and clk_ipd = '0') THEN
IF (clk_rising_edge_count >= 1) THEN
quarter_period <= (NOW - clk_last_rising_edge) / 2;
END IF;
END IF;
END PROCESS;
P6 : PROCESS (dqsi_ipd, dqsdel_ipd)
BEGIN
IF (dqsdel_ipd = '1') THEN
IF (quarter_period > 0 ps) THEN
DQSO_int <= transport dqsi_ipd after (quarter_period - 0.8 ns);
DQSC_int <= dqsi_ipd;
END IF;
ELSE
DQSO_int <= '0';
DQSC_int <= '0';
END IF;
END PROCESS;
P7 : PROCESS (DQSO_int, CLKP)
BEGIN
IF (CLKP = '1') THEN
DQSO_int1 <= '0';
ELSIF (DQSO_int'event and DQSO_int'last_value = '0') THEN
DQSO_int1 <= '1';
END IF;
END PROCESS;
DQSO_int0 <= DQSO_int;
DQSO_int2 <= transport (DQSO_int1 or DQSO_int0) after 0.8 ns;
ddrclkpol <= DDRCLKPOL_int;
prmbdet <= PRMBDET_int;
dqso <= DQSO_int2;
dqsc <= DQSC_int;
END v;
CONFIGURATION dqsbufbc OF dqsbufb IS
FOR v
FOR ALL: or2 USE ENTITY work.or2(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
END FOR;
END dqsbufbc;
--
---
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- ************************************************************************
entity CCU2 is
generic (
inject1_0 : string := "YES";
inject1_1 : string := "YES";
init0: string := "0x0000";
init1: string := "0x0000"
);
port (
A0,A1 : in std_ulogic;
B0,B1 : in std_ulogic;
C0,C1 : in std_ulogic;
D0,D1 : in std_ulogic;
CIN : in std_ulogic;
S0,S1 : out std_ulogic;
COUT0,COUT1 : out std_ulogic
);
end CCU2;
architecture bev of CCU2 is
------------------------------------------------------------------
function hex2bin (hex: Character) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (3 downto 0);
begin
case hex is
when '0' =>
result := "0000";
when '1' =>
result := "0001";
when '2' =>
result := "0010";
when '3' =>
result := "0011";
when '4' =>
result := "0100";
when '5' =>
result := "0101";
when '6' =>
result := "0110";
when '7' =>
result := "0111";
when '8' =>
result := "1000";
when '9' =>
result := "1001";
when 'A'|'a' =>
result := "1010";
when 'B'|'b' =>
result := "1011";
when 'C'|'c' =>
result := "1100";
when 'D'|'d' =>
result := "1101";
when 'E'|'e' =>
result := "1110";
when 'F'|'f' =>
result := "1111";
when others =>
null;
end case;
return result;
end;
function hex2bin (hex: String) return STD_LOGIC_VECTOR is
-- skip 0x of hex string
constant length : Integer := hex'length - 2;
variable result : STD_LOGIC_VECTOR (4*length-1 downto 0);
begin
for i in 0 to length-1 loop
result ((length-i)*4-1 downto (length-i-1)*4) := hex2bin(hex(i+3));
end loop;
return result;
end;
-----------------------------------------------------
signal init_vec0 : std_logic_vector( 15 downto 0);
signal init_vec1 : std_logic_vector( 15 downto 0);
signal lut2_init0 : std_logic_vector (3 downto 0);
signal lut2_init1 : std_logic_vector (3 downto 0);
signal lut2_sel0, lut2_sel1, lut4_sel0, lut4_sel1 : integer :=0;
signal lut2_out0, lut2_out1 : std_ulogic;
signal prop0, prop1, gen0, gen1, cout_sig0, cout_sig1 : std_ulogic;
-----------------------------------------------------
begin
init_vec0 <= hex2bin(init0);
init_vec1 <= hex2bin(init1);
lut2_init0 <= init_vec0( 15 downto 12 );
lut2_init1 <= init_vec1( 15 downto 12 );
lut2_sel0 <= conv_integer (B0 & A0);
lut2_sel1 <= conv_integer (B1 & A1);
lut4_sel0 <= conv_integer (D0 & C0 & B0 & A0);
lut4_sel1 <= conv_integer (D1 & C1 & B1 & A1);
prop0 <= init_vec0(lut4_sel0) ;
prop1 <= init_vec1(lut4_sel1);
lut2_out0 <= lut2_init0(lut2_sel0);
lut2_out1 <= lut2_init1(lut2_sel1);
gen0 <= '1' when (inject1_0 = "YES") else
'1' when (inject1_0 = "yes") else
not(lut2_out0) ;
gen1 <= '1' when (inject1_1 = "YES") else
'1' when (inject1_0 = "yes") else
not(lut2_out1) ;
cout_sig0 <= (not(prop0) and gen0 ) or (prop0 and CIN);
cout_sig1 <= (not(prop1) and gen1 ) or (prop1 and cout_sig0);
COUT0 <= cout_sig0;
COUT1 <= cout_sig1;
S0 <= prop0 xor CIN;
S1 <= prop1 xor cout_sig0;
end bev;
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_CNT.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
--
----- buf -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
-- entity declaration --
ENTITY buf IS
GENERIC (
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "buf";
tpd_a_z : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_a : VitalDelayType01 := (0.0 ns, 0.0 ns)) ;
PORT (
a : IN std_logic;
z : OUT std_logic);
ATTRIBUTE Vital_Level0 OF buf : ENTITY IS TRUE;
END buf ;
-- architecture body --
ARCHITECTURE v OF buf IS
ATTRIBUTE Vital_Level1 OF v : ARCHITECTURE IS TRUE;
SIGNAL a_ipd : std_logic := 'X';
BEGIN
---------------------
-- input path delays
---------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(a_ipd, a, tipd_a);
END BLOCK;
--------------------
-- behavior section
--------------------
VitalBehavior : process (a_ipd)
-- functionality results
VARIABLE results : std_logic_vector(1 to 1) := (others => 'X');
ALIAS z_zd : std_ulogic IS results(1);
-- output glitch detection VARIABLEs
VARIABLE z_GlitchData : VitalGlitchDatatype;
BEGIN
IF (TimingChecksOn) THEN
-----------------------------------
-- no timing checks for a comb gate
-----------------------------------
END IF;
-----------------------------------
-- functionality section.
-----------------------------------
z_zd := VitalBuf(a_ipd);
-----------------------------------
-- path delay section.
-----------------------------------
VitalPathDelay01 (
OutSignal => z,
OutSignalName => "z",
OutTemp => z_zd,
Paths => (0 => (InputChangeTime => a_ipd'last_event,
PathDelay => tpd_a_z,
PathCondition => TRUE)),
GlitchData => z_GlitchData,
Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);
END process;
END v;
--
----- cd2 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY cd2 IS
GENERIC (
InstancePath : string := "cd2");
PORT (
ci, pc0, pc1 : IN std_logic;
co, nc0, nc1 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF cd2 : ENTITY IS TRUE;
END cd2;
ARCHITECTURE v OF cd2 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL cii, i4, i6, i16, i18, i29, i31, i42: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>pc0, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>pc0, z=>i6);
inst13: xnor2 PORT MAP (a=>pc0, b=>cii, z=>nc0);
inst24: and2 PORT MAP (a=>pc1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>pc1, z=>co);
inst26: xnor2 PORT MAP (a=>pc1, b=>i6, z=>nc1);
inst990: buf PORT MAP (a=>ci, z=>cii);
END v;
CONFIGURATION cd2c OF cd2 IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END cd2c;
--
----- cu2 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY cu2 IS
GENERIC (
InstancePath : string := "cu2");
PORT (
ci, pc0, pc1: IN std_logic;
co, nc0, nc1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF cu2 : ENTITY IS TRUE;
END cu2;
ARCHITECTURE v OF cu2 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL cii, i6, i18, i31: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>pc0, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>pc0, b=>cii, z=>nc0);
inst24: and2 PORT MAP (a=>pc1, b=>i6, z=>co);
inst26: xor2 PORT MAP (a=>pc1, b=>i6, z=>nc1);
inst990: buf PORT MAP (a=>ci, z=>cii);
END v;
CONFIGURATION cu2c OF cu2 IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END cu2c;
--
----- cb2 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
----LIBRARY work;
USE work.components.all;
ENTITY cb2 IS
GENERIC (
InstancePath : string := "cb2");
PORT (
ci, pc0, pc1, con: IN std_logic;
co, nc0, nc1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF cb2 : ENTITY IS TRUE;
END cb2;
ARCHITECTURE v OF cb2 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL cii, conn, i3, i4, i5, i6, i17, i15, i16, coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>pc0, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>pc0, b=>conn, c=>cii, z=>nc0);
inst2: and2 PORT MAP (a=>conn, b=>pc0, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>pc1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>pc1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>co);
inst26: xor3 PORT MAP (a=>pc1, b=>conn, c=>i6, z=>nc1);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
END v;
CONFIGURATION cb2c OF cb2 IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END cb2c;
--
----- lb2p3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb2p3ax IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb2p3ax");
PORT (
d0, d1, ci, sp, ck, sd, con: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb2p3ax : ENTITY IS TRUE;
END lb2p3ax;
ARCHITECTURE v OF lb2p3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3az
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i19, coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>co);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=> q0_1);
inst69: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=> q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lb2p3axc OF lb2p3ax IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3az USE ENTITY work.fl1p3az(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb2p3axc;
--
----- lb2p3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb2p3ay IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb2p3ay");
PORT (
d0, d1, ci, sp, ck, sd, con: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb2p3ay : ENTITY IS TRUE;
END lb2p3ay;
ARCHITECTURE v OF lb2p3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3ay
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i19, coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>co);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=> q0_1);
inst69: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=> q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lb2p3ayc OF lb2p3ay IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3ay USE ENTITY work.fl1p3ay(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb2p3ayc;
--
----- lb2p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb2p3bx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb2p3bx");
PORT (
d0, d1, ci, sp, ck, sd, pd, con: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb2p3bx : ENTITY IS TRUE;
END lb2p3bx;
ARCHITECTURE v OF lb2p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3bx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i19, coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>co);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lb2p3bxc OF lb2p3bx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3bx USE ENTITY work.fl1p3bx(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb2p3bxc;
--
----- lb2p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb2p3dx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb2p3dx");
PORT (
d0, d1, ci, sp, ck, sd, cd, con: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb2p3dx : ENTITY IS TRUE;
END lb2p3dx;
ARCHITECTURE v OF lb2p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3dx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i19, coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>co);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lb2p3dxc OF lb2p3dx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3dx USE ENTITY work.fl1p3dx(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb2p3dxc;
--
----- lb2p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb2p3ix IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb2p3ix");
PORT (
d0, d1, ci, sp, ck, sd, cd, con: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb2p3ix : ENTITY IS TRUE;
END lb2p3ix;
ARCHITECTURE v OF lb2p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3iy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i19, coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>co);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lb2p3ixc OF lb2p3ix IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3iy USE ENTITY work.fl1p3iy(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb2p3ixc;
--
----- lb2p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb2p3jx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb2p3jx");
PORT (
d0, d1, ci, sp, ck, sd, pd, con: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb2p3jx : ENTITY IS TRUE;
END lb2p3jx;
ARCHITECTURE v OF lb2p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3jy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i19, coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>co);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lb2p3jxc OF lb2p3jx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3jy USE ENTITY work.fl1p3jy(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb2p3jxc;
--
----- lb4p3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb4p3ax IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb4p3ax");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, con: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb4p3ax : ENTITY IS TRUE;
END lb4p3ax;
ARCHITECTURE v OF lb4p3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3az
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i18, i19, i30, i28, i29, i31, i32, i43, i41, i42, i45,
coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>i18);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst35: and2 PORT MAP (a=>conn, b=>q2_1, z=>i30);
inst36: and2 PORT MAP (a=>i18, b=>conn, z=>i28);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i28, b=>i29, c=>i30, z=>i31);
inst39: xor3 PORT MAP (a=>q2_1, b=>conn, c=>i18, z=>i32);
inst48: and2 PORT MAP (a=>conn, b=>q3_1, z=>i43);
inst49: and2 PORT MAP (a=>i31, b=>conn, z=>i41);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i41, b=>i42, c=>i43, z=>co);
inst52: xor3 PORT MAP (a=>q3_1, b=>conn, c=>i31, z=>i45);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=> q0_1);
inst69: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=> q1_1);
inst70: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, q=> q2_1);
inst71: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, q=> q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lb4p3axc OF lb4p3ax IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3az USE ENTITY work.fl1p3az(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb4p3axc;
--
----- lb4p3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb4p3ay IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb4p3ay");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, con: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb4p3ay : ENTITY IS TRUE;
END lb4p3ay;
ARCHITECTURE v OF lb4p3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3ay
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i18, i19, i30, i28, i29, i31, i32, i43, i41, i42, i45,
coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>i18);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst35: and2 PORT MAP (a=>conn, b=>q2_1, z=>i30);
inst36: and2 PORT MAP (a=>i18, b=>conn, z=>i28);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i28, b=>i29, c=>i30, z=>i31);
inst39: xor3 PORT MAP (a=>q2_1, b=>conn, c=>i18, z=>i32);
inst48: and2 PORT MAP (a=>conn, b=>q3_1, z=>i43);
inst49: and2 PORT MAP (a=>i31, b=>conn, z=>i41);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i41, b=>i42, c=>i43, z=>co);
inst52: xor3 PORT MAP (a=>q3_1, b=>conn, c=>i31, z=>i45);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=> q0_1);
inst69: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=> q1_1);
inst70: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, q=> q2_1);
inst71: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, q=> q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lb4p3ayc OF lb4p3ay IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3ay USE ENTITY work.fl1p3ay(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb4p3ayc;
--
----- lb4p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb4p3bx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb4p3bx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, pd, con: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb4p3bx : ENTITY IS TRUE;
END lb4p3bx;
ARCHITECTURE v OF lb4p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3bx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i18, i19, i30, i28, i29, i31, i32, i43, i41, i42, i45,
coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>i18);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst35: and2 PORT MAP (a=>conn, b=>q2_1, z=>i30);
inst36: and2 PORT MAP (a=>i18, b=>conn, z=>i28);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i28, b=>i29, c=>i30, z=>i31);
inst39: xor3 PORT MAP (a=>q2_1, b=>conn, c=>i18, z=>i32);
inst48: and2 PORT MAP (a=>conn, b=>q3_1, z=>i43);
inst49: and2 PORT MAP (a=>i31, b=>conn, z=>i41);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i41, b=>i42, c=>i43, z=>co);
inst52: xor3 PORT MAP (a=>q3_1, b=>conn, c=>i31, z=>i45);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst70: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q2_1);
inst71: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lb4p3bxc OF lb4p3bx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3bx USE ENTITY work.fl1p3bx(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb4p3bxc;
--
----- lb4p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb4p3dx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb4p3dx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, cd, con: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb4p3dx : ENTITY IS TRUE;
END lb4p3dx;
ARCHITECTURE v OF lb4p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3dx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i18, i19, i30, i28, i29, i31, i32, i43, i41, i42, i45,
coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>i18);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst35: and2 PORT MAP (a=>conn, b=>q2_1, z=>i30);
inst36: and2 PORT MAP (a=>i18, b=>conn, z=>i28);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i28, b=>i29, c=>i30, z=>i31);
inst39: xor3 PORT MAP (a=>q2_1, b=>conn, c=>i18, z=>i32);
inst48: and2 PORT MAP (a=>conn, b=>q3_1, z=>i43);
inst49: and2 PORT MAP (a=>i31, b=>conn, z=>i41);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i41, b=>i42, c=>i43, z=>co);
inst52: xor3 PORT MAP (a=>q3_1, b=>conn, c=>i31, z=>i45);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst70: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q2_1);
inst71: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lb4p3dxc OF lb4p3dx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3dx USE ENTITY work.fl1p3dx(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb4p3dxc;
--
----- lb4p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb4p3ix IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb4p3ix");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, cd, con: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb4p3ix : ENTITY IS TRUE;
END lb4p3ix;
ARCHITECTURE v OF lb4p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3iy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i18, i19, i30, i28, i29, i31, i32, i43, i41, i42, i45,
coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>i18);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst35: and2 PORT MAP (a=>conn, b=>q2_1, z=>i30);
inst36: and2 PORT MAP (a=>i18, b=>conn, z=>i28);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i28, b=>i29, c=>i30, z=>i31);
inst39: xor3 PORT MAP (a=>q2_1, b=>conn, c=>i18, z=>i32);
inst48: and2 PORT MAP (a=>conn, b=>q3_1, z=>i43);
inst49: and2 PORT MAP (a=>i31, b=>conn, z=>i41);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i41, b=>i42, c=>i43, z=>co);
inst52: xor3 PORT MAP (a=>q3_1, b=>conn, c=>i31, z=>i45);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst70: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q2_1);
inst71: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lb4p3ixc OF lb4p3ix IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3iy USE ENTITY work.fl1p3iy(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb4p3ixc;
--
----- lb4p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lb4p3jx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lb4p3jx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, pd, con: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lb4p3jx : ENTITY IS TRUE;
END lb4p3jx;
ARCHITECTURE v OF lb4p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3jy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT inv
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xor3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, conn, i3, i4, i5, i6, i7, i17,
i15, i16, i18, i19, i30, i28, i29, i31, i32, i43, i41, i42, i45,
coni: std_logic;
BEGIN
inst10: and2 PORT MAP (a=>cii, b=>conn, z=>i3);
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>i3, b=>i4, c=>i5, z=>i6);
inst13: xor3 PORT MAP (a=>q0_1, b=>conn, c=>cii, z=>i7);
inst2: and2 PORT MAP (a=>conn, b=>q0_1, z=>i5);
inst22: and2 PORT MAP (a=>conn, b=>q1_1, z=>i17);
inst23: and2 PORT MAP (a=>i6, b=>conn, z=>i15);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i15, b=>i16, c=>i17, z=>i18);
inst26: xor3 PORT MAP (a=>q1_1, b=>conn, c=>i6, z=>i19);
inst35: and2 PORT MAP (a=>conn, b=>q2_1, z=>i30);
inst36: and2 PORT MAP (a=>i18, b=>conn, z=>i28);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i28, b=>i29, c=>i30, z=>i31);
inst39: xor3 PORT MAP (a=>q2_1, b=>conn, c=>i18, z=>i32);
inst48: and2 PORT MAP (a=>conn, b=>q3_1, z=>i43);
inst49: and2 PORT MAP (a=>i31, b=>conn, z=>i41);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i41, b=>i42, c=>i43, z=>co);
inst52: xor3 PORT MAP (a=>q3_1, b=>conn, c=>i31, z=>i45);
inst96: inv PORT MAP (a=>coni, z=>conn);
inst68: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst70: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q2_1);
inst71: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
inst991: buf PORT MAP (a=>con, z=>coni);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lb4p3jxc OF lb4p3jx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3jy USE ENTITY work.fl1p3jy(v); END FOR;
FOR ALL: inv USE ENTITY work.inv(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xor3 USE ENTITY work.xor3(v); END FOR;
END FOR;
END lb4p3jxc;
--
----- ld2p3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld2p3ax IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld2p3ax");
PORT (
d0, d1, ci, sp, ck, sd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld2p3ax : ENTITY IS TRUE;
END ld2p3ax;
ARCHITECTURE v OF ld2p3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3az
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i4, i6, i7, i16, i19 : std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>co);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=>
q0_1);
inst69: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=>
q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION ld2p3axc OF ld2p3ax IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3az USE ENTITY work.fl1p3az(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld2p3axc;
--
----- ld2p3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld2p3ay IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld2p3ay");
PORT (
d0, d1, ci, sp, ck, sd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld2p3ay : ENTITY IS TRUE;
END ld2p3ay;
ARCHITECTURE v OF ld2p3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3ay
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i4, i6, i7, i16, i19 : std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>co);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=>
q0_1);
inst69: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=>
q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION ld2p3ayc OF ld2p3ay IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3ay USE ENTITY work.fl1p3ay(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld2p3ayc;
--
----- ld2p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld2p3bx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld2p3bx");
PORT (
d0, d1, ci, sp, ck, sd, pd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld2p3bx : ENTITY IS TRUE;
END ld2p3bx;
ARCHITECTURE v OF ld2p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3bx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i4, i6, i7, i16, i19 : std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>co);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION ld2p3bxc OF ld2p3bx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3bx USE ENTITY work.fl1p3bx(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld2p3bxc;
--
----- ld2p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld2p3dx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld2p3dx");
PORT (
d0, d1, ci, sp, ck, sd, cd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld2p3dx : ENTITY IS TRUE;
END ld2p3dx;
ARCHITECTURE v OF ld2p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3dx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i4, i6, i7, i16, i19 : std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>co);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION ld2p3dxc OF ld2p3dx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3dx USE ENTITY work.fl1p3dx(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld2p3dxc;
--
----- ld2p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld2p3ix IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld2p3ix");
PORT (
d0, d1, ci, sp, ck, sd, cd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld2p3ix : ENTITY IS TRUE;
END ld2p3ix;
ARCHITECTURE v OF ld2p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3iy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i4, i6, i7, i16, i19 : std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>co);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION ld2p3ixc OF ld2p3ix IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3iy USE ENTITY work.fl1p3iy(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld2p3ixc;
--
----- ld2p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld2p3jx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld2p3jx");
PORT (
d0, d1, ci, sp, ck, sd, pd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld2p3jx : ENTITY IS TRUE;
END ld2p3jx;
ARCHITECTURE v OF ld2p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3jy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i4, i6, i7, i16, i19 : std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>co);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION ld2p3jxc OF ld2p3jx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3jy USE ENTITY work.fl1p3jy(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld2p3jxc;
--
----- ld4p3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld4p3ax IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld4p3ax");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld4p3ax : ENTITY IS TRUE;
END ld4p3ax;
ARCHITECTURE v OF ld4p3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3az
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i4, i6, i7, i16, i18, i19, i29,
i31, i32, i42, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>i18);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i18, b=>i29, c=>q2_1, z=>i31);
inst39: xnor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i31, b=>i42, c=>q3_1, z=>co);
inst52: xnor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=>
q0_1);
inst69: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=>
q1_1);
inst70: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, q=>
q2_1);
inst71: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, q=>
q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION ld4p3axc OF ld4p3ax IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3az USE ENTITY work.fl1p3az(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld4p3axc;
--
----- ld4p3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld4p3ay IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld4p3ay");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld4p3ay : ENTITY IS TRUE;
END ld4p3ay;
ARCHITECTURE v OF ld4p3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3ay
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i4, i6, i7, i16, i18, i19, i29,
i31, i32, i42, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>i18);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i18, b=>i29, c=>q2_1, z=>i31);
inst39: xnor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i31, b=>i42, c=>q3_1, z=>co);
inst52: xnor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=>
q0_1);
inst69: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=>
q1_1);
inst70: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, q=>
q2_1);
inst71: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, q=>
q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION ld4p3ayc OF ld4p3ay IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3ay USE ENTITY work.fl1p3ay(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld4p3ayc;
--
----- ld4p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld4p3bx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld4p3bx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, pd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld4p3bx : ENTITY IS TRUE;
END ld4p3bx;
ARCHITECTURE v OF ld4p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3bx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i4, i6, i7, i16, i18, i19, i29,
i31, i32, i42, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>i18);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i18, b=>i29, c=>q2_1, z=>i31);
inst39: xnor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i31, b=>i42, c=>q3_1, z=>co);
inst52: xnor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst70: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q2_1);
inst71: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION ld4p3bxc OF ld4p3bx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3bx USE ENTITY work.fl1p3bx(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld4p3bxc;
--
----- ld4p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld4p3dx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld4p3dx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, cd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld4p3dx : ENTITY IS TRUE;
END ld4p3dx;
ARCHITECTURE v OF ld4p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3dx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i4, i6, i7, i16, i18, i19, i29,
i31, i32, i42, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>i18);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i18, b=>i29, c=>q2_1, z=>i31);
inst39: xnor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i31, b=>i42, c=>q3_1, z=>co);
inst52: xnor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst70: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q2_1);
inst71: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION ld4p3dxc OF ld4p3dx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3dx USE ENTITY work.fl1p3dx(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld4p3dxc;
--
----- ld4p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld4p3ix IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld4p3ix");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, cd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld4p3ix : ENTITY IS TRUE;
END ld4p3ix;
ARCHITECTURE v OF ld4p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3iy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i4, i6, i7, i16, i18, i19, i29,
i31, i32, i42, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>i18);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i18, b=>i29, c=>q2_1, z=>i31);
inst39: xnor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i31, b=>i42, c=>q3_1, z=>co);
inst52: xnor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst70: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q2_1);
inst71: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION ld4p3ixc OF ld4p3ix IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3iy USE ENTITY work.fl1p3iy(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld4p3ixc;
--
----- ld4p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY ld4p3jx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "ld4p3jx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, pd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF ld4p3jx : ENTITY IS TRUE;
END ld4p3jx;
ARCHITECTURE v OF ld4p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3jy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT or3
PORT (
a, b, c: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT xnor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i4, i6, i7, i16, i18, i19, i29,
i31, i32, i42, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i4);
inst12: or3 PORT MAP (a=>cii, b=>i4, c=>q0_1, z=>i6);
inst13: xnor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i16);
inst25: or3 PORT MAP (a=>i6, b=>i16, c=>q1_1, z=>i18);
inst26: xnor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i29);
inst38: or3 PORT MAP (a=>i18, b=>i29, c=>q2_1, z=>i31);
inst39: xnor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>i42);
inst51: or3 PORT MAP (a=>i31, b=>i42, c=>q3_1, z=>co);
inst52: xnor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst70: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q2_1);
inst71: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION ld4p3jxc OF ld4p3jx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3jy USE ENTITY work.fl1p3jy(v); END FOR;
FOR ALL: or3 USE ENTITY work.or3(v); END FOR;
FOR ALL: xnor2 USE ENTITY work.xnor2(v); END FOR;
END FOR;
END ld4p3jxc;
--
----- lu2p3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu2p3ax IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu2p3ax");
PORT (
d0, d1, ci, sp, ck, sd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu2p3ax : ENTITY IS TRUE;
END lu2p3ax;
ARCHITECTURE v OF lu2p3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3az
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i6, i7, i19 : std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>co);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=>
q0_1);
inst69: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=>
q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lu2p3axc OF lu2p3ax IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3az USE ENTITY work.fl1p3az(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu2p3axc;
--
----- lu2p3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu2p3ay IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu2p3ay");
PORT (
d0, d1, ci, sp, ck, sd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu2p3ay : ENTITY IS TRUE;
END lu2p3ay;
ARCHITECTURE v OF lu2p3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3ay
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i6, i7, i19: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>co);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=>
q0_1);
inst69: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=>
q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lu2p3ayc OF lu2p3ay IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3ay USE ENTITY work.fl1p3ay(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu2p3ayc;
--
----- lu2p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu2p3bx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu2p3bx");
PORT (
d0, d1, ci, sp, ck, sd, pd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu2p3bx : ENTITY IS TRUE;
END lu2p3bx;
ARCHITECTURE v OF lu2p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3bx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i6, i7, i19: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>co);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lu2p3bxc OF lu2p3bx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3bx USE ENTITY work.fl1p3bx(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu2p3bxc;
--
----- lu2p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu2p3dx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu2p3dx");
PORT (
d0, d1, ci, sp, ck, sd, cd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu2p3dx : ENTITY IS TRUE;
END lu2p3dx;
ARCHITECTURE v OF lu2p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3dx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i6, i7, i19: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>co);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lu2p3dxc OF lu2p3dx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3dx USE ENTITY work.fl1p3dx(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu2p3dxc;
--
----- lu2p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu2p3ix IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu2p3ix");
PORT (
d0, d1, ci, sp, ck, sd, cd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu2p3ix : ENTITY IS TRUE;
END lu2p3ix;
ARCHITECTURE v OF lu2p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3iy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i6, i7, i19: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>co);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lu2p3ixc OF lu2p3ix IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3iy USE ENTITY work.fl1p3iy(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu2p3ixc;
--
----- lu2p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu2p3jx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu2p3jx");
PORT (
d0, d1, ci, sp, ck, sd, pd: IN std_logic;
co, q0, q1: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu2p3jx : ENTITY IS TRUE;
END lu2p3jx;
ARCHITECTURE v OF lu2p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3jy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, cii, i6, i7, i19: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>co);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst68: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
END v;
CONFIGURATION lu2p3jxc OF lu2p3jx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3jy USE ENTITY work.fl1p3jy(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu2p3jxc;
--
----- lu4p3ax -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu4p3ax IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu4p3ax");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu4p3ax : ENTITY IS TRUE;
END lu4p3ax;
ARCHITECTURE v OF lu4p3ax IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3az
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i6, i7, i18, i19, i31, i32, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i18);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i31);
inst39: xor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>co);
inst52: xor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=>
q0_1);
inst69: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=>
q1_1);
inst70: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, q=>
q2_1);
inst71: fl1p3az generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, q=>
q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lu4p3axc OF lu4p3ax IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3az USE ENTITY work.fl1p3az(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu4p3axc;
--
----- lu4p3ay -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu4p3ay IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu4p3ay");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu4p3ay : ENTITY IS TRUE;
END lu4p3ay;
ARCHITECTURE v OF lu4p3ay IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3ay
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i6, i7, i18, i19, i31, i32, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i18);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i31);
inst39: xor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>co);
inst52: xor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, q=>
q0_1);
inst69: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, q=>
q1_1);
inst70: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, q=>
q2_1);
inst71: fl1p3ay generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, q=>
q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lu4p3ayc OF lu4p3ay IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3ay USE ENTITY work.fl1p3ay(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu4p3ayc;
--
----- lu4p3bx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu4p3bx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu4p3bx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, pd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu4p3bx : ENTITY IS TRUE;
END lu4p3bx;
ARCHITECTURE v OF lu4p3bx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3bx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i6, i7, i18, i19, i31, i32, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i18);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i31);
inst39: xor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>co);
inst52: xor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst70: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q2_1);
inst71: fl1p3bx generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lu4p3bxc OF lu4p3bx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3bx USE ENTITY work.fl1p3bx(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu4p3bxc;
--
----- lu4p3dx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu4p3dx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu4p3dx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, cd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu4p3dx : ENTITY IS TRUE;
END lu4p3dx;
ARCHITECTURE v OF lu4p3dx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3dx
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i6, i7, i18, i19, i31, i32, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i18);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i31);
inst39: xor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>co);
inst52: xor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst70: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q2_1);
inst71: fl1p3dx generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lu4p3dxc OF lu4p3dx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3dx USE ENTITY work.fl1p3dx(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu4p3dxc;
--
----- lu4p3ix -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu4p3ix IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu4p3ix");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, cd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu4p3ix : ENTITY IS TRUE;
END lu4p3ix;
ARCHITECTURE v OF lu4p3ix IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3iy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, cd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i6, i7, i18, i19, i31, i32, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i18);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i31);
inst39: xor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>co);
inst52: xor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q0_1);
inst69: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q1_1);
inst70: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q2_1);
inst71: fl1p3iy generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, cd=>
cd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lu4p3ixc OF lu4p3ix IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3iy USE ENTITY work.fl1p3iy(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu4p3ixc;
--
----- lu4p3jx -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
--LIBRARY work;
USE work.components.all;
ENTITY lu4p3jx IS
GENERIC (
gsr : String := "ENABLED";
InstancePath : string := "lu4p3jx");
PORT (
d0, d1, d2, d3, ci, sp, ck, sd, pd: IN std_logic;
co, q0, q1, q2, q3: OUT std_logic);
ATTRIBUTE Vital_Level0 OF lu4p3jx : ENTITY IS TRUE;
END lu4p3jx;
ARCHITECTURE v OF lu4p3jx IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
COMPONENT and2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT buf
PORT (
a: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT fl1p3jy
generic (gsr : String := "ENABLED");
PORT (
d0, d1, sp, ck, sd, pd: IN std_logic;
q: OUT std_logic);
END COMPONENT;
COMPONENT xor2
PORT (
a, b: IN std_logic;
z: OUT std_logic);
END COMPONENT;
SIGNAL q0_1, q1_1, q2_1, q3_1, cii, i6, i7, i18, i19, i31, i32, i45: std_logic;
BEGIN
inst11: and2 PORT MAP (a=>q0_1, b=>cii, z=>i6);
inst13: xor2 PORT MAP (a=>q0_1, b=>cii, z=>i7);
inst24: and2 PORT MAP (a=>q1_1, b=>i6, z=>i18);
inst26: xor2 PORT MAP (a=>q1_1, b=>i6, z=>i19);
inst37: and2 PORT MAP (a=>q2_1, b=>i18, z=>i31);
inst39: xor2 PORT MAP (a=>q2_1, b=>i18, z=>i32);
inst50: and2 PORT MAP (a=>q3_1, b=>i31, z=>co);
inst52: xor2 PORT MAP (a=>q3_1, b=>i31, z=>i45);
inst68: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i7, d1=>d0, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q0_1);
inst69: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i19, d1=>d1, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q1_1);
inst70: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i32, d1=>d2, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q2_1);
inst71: fl1p3jy generic map (gsr => gsr)
PORT MAP (d0=>i45, d1=>d3, sp=>sp, ck=>ck, sd=>sd, pd=>
pd, q=>q3_1);
inst990: buf PORT MAP (a=>ci, z=>cii);
q0 <= q0_1;
q1 <= q1_1;
q2 <= q2_1;
q3 <= q3_1;
END v;
CONFIGURATION lu4p3jxc OF lu4p3jx IS
FOR v
FOR ALL: and2 USE ENTITY work.and2(v); END FOR;
FOR ALL: buf USE ENTITY work.buf(v); END FOR;
FOR ALL: fl1p3jy USE ENTITY work.fl1p3jy(v); END FOR;
FOR ALL: xor2 USE ENTITY work.xor2(v); END FOR;
END FOR;
END lu4p3jxc;
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_MEM.vhd,v 1.1 2005/12/06 13:00:24 tame Exp $
--
--
----- package mem1 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mem1 IS
TYPE mem_type_1 IS array (natural range <>) OF std_logic;
TYPE mem_type_2 IS array (natural range <>) OF std_logic_vector(1 downto 0);
TYPE mem_type_4 IS array (natural range <>) OF std_logic_vector(3 downto 0);
function hex2bin_2 (hex: Character) return STD_LOGIC_VECTOR;
FUNCTION hex2bin_4 (hex: character) RETURN std_logic_vector;
FUNCTION init_ram (hex: string) RETURN mem_type_4;
FUNCTION init_ram (hex: string) RETURN mem_type_2;
FUNCTION init_ram_1 (hex: string) RETURN mem_type_1;
END mem1;
PACKAGE BODY mem1 IS
FUNCTION init_ram (hex: string) RETURN mem_type_2 IS
-- skip 0x OF hex string
CONSTANT length : integer := hex'length - 2;
VARIABLE result : mem_type_2 (length-1 downto 0);
BEGIN
FOR i in 0 to length-1 LOOP
result (length-1-i) := hex2bin_2 (hex(i+3));
END LOOP;
RETURN result;
END;
function hex2bin_2 (hex: Character) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (1 downto 0);
begin
case hex is
when '0' =>
result := "00";
when '1' =>
result := "01";
when '2' =>
result := "10";
when '3' =>
result := "11";
when '4' =>
result := "00";
when '5' =>
result := "01";
when '6' =>
result := "10";
when '7' =>
result := "11";
when '8' =>
result := "00";
when '9' =>
result := "01";
when 'A'|'a' =>
result := "10";
when 'B'|'b' =>
result := "11";
when 'C'|'c' =>
result := "00";
when 'D'|'d' =>
result := "01";
when 'E'|'e' =>
result := "10";
when 'F'|'f' =>
result := "11";
when others =>
null;
end case;
return result;
end;
FUNCTION hex2bin_4 (hex: character) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector (3 downto 0);
BEGIN
CASE hex IS
WHEN '0' =>
result := "0000";
WHEN '1' =>
result := "0001";
WHEN '2' =>
result := "0010";
WHEN '3' =>
result := "0011";
WHEN '4' =>
result := "0100";
WHEN '5' =>
result := "0101";
WHEN '6' =>
result := "0110";
WHEN '7' =>
result := "0111";
WHEN '8' =>
result := "1000";
WHEN '9' =>
result := "1001";
WHEN 'A'|'a' =>
result := "1010";
WHEN 'B'|'b' =>
result := "1011";
WHEN 'C'|'c' =>
result := "1100";
WHEN 'D'|'d' =>
result := "1101";
WHEN 'E'|'e' =>
result := "1110";
WHEN 'F'|'f' =>
result := "1111";
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION init_ram (hex: string) RETURN mem_type_4 IS
-- skip 0x OF hex string
CONSTANT length : integer := hex'length - 2;
VARIABLE result : mem_type_4 (length-1 downto 0);
BEGIN
FOR i in 0 to length-1 LOOP
result (length-1-i) := hex2bin_4 (hex(i+3));
END LOOP;
RETURN result;
END;
FUNCTION init_ram_1 (hex: string) RETURN mem_type_1 IS
-- skip 0x OF hex string
CONSTANT length : integer := hex'length - 2;
VARIABLE result : mem_type_1 ((4*length)-1 downto 0);
VARIABLE result1 : std_logic_vector((4*length)-1 downto 0);
BEGIN
FOR i in 0 to length-1 LOOP
result1 ((4*(length-i))-1 downto (4*(length-1-i))) := hex2bin_4 (hex(i+3));
FOR j in 0 to 3 LOOP
result(((4*length)-1)-j-(4*i)) := result1(((4*length)-1)-j-(4*i));
END LOOP;
END LOOP;
RETURN result;
END;
END mem1;
--
----- PACKAGE mem2 -----
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mem2 is
function hex2bin (hex: String) return STD_LOGIC_VECTOR;
function hex2bin (hex: Character) return STD_LOGIC_VECTOR;
end mem2;
package body mem2 is
function hex2bin (hex: Character) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (3 downto 0);
begin
case hex is
when '0' =>
result := "0000";
when '1' =>
result := "0001";
when '2' =>
result := "0010";
when '3' =>
result := "0011";
when '4' =>
result := "0100";
when '5' =>
result := "0101";
when '6' =>
result := "0110";
when '7' =>
result := "0111";
when '8' =>
result := "1000";
when '9' =>
result := "1001";
when 'A'|'a' =>
result := "1010";
when 'B'|'b' =>
result := "1011";
when 'C'|'c' =>
result := "1100";
when 'D'|'d' =>
result := "1101";
when 'E'|'e' =>
result := "1110";
when 'F'|'f' =>
result := "1111";
when others =>
null;
end case;
return result;
end;
function hex2bin (hex: String) return STD_LOGIC_VECTOR is
-- skip 0x of hex string
constant length : Integer := hex'length - 2;
variable result : STD_LOGIC_VECTOR (4*length-1 downto 0);
begin
for i in 0 to length-1 loop
result ((length-i)*4-1 downto (length-i-1)*4) := hex2bin(hex(i+3));
end loop;
return result;
end;
end mem2;
--
----- package mem3 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
PACKAGE mem3 IS
TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector;
FUNCTION data2data (data_w: integer) RETURN integer;
FUNCTION data2addr_w (data_w: integer) RETURN integer;
FUNCTION data2data_w (data_w: integer) RETURN integer;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6;
FUNCTION str2slv (str: in string) RETURN std_logic_vector;
FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;
END mem3;
PACKAGE BODY mem3 IS
FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector (3 downto 0);
BEGIN
CASE hex IS
WHEN '0' =>
result := "0000";
WHEN '1' =>
result := "0001";
WHEN '2' =>
result := "0010";
WHEN '3' =>
result := "0011";
WHEN '4' =>
result := "0100";
WHEN '5' =>
result := "0101";
WHEN '6' =>
result := "0110";
WHEN '7' =>
result := "0111";
WHEN '8' =>
result := "1000";
WHEN '9' =>
result := "1001";
WHEN 'A'|'a' =>
result := "1010";
WHEN 'B'|'b' =>
result := "1011";
WHEN 'C'|'c' =>
result := "1100";
WHEN 'D'|'d' =>
result := "1101";
WHEN 'E'|'e' =>
result := "1110";
WHEN 'F'|'f' =>
result := "1111";
WHEN 'X'|'x' =>
result := "XXXX";
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(17 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
result(17 downto 16) := hex2bin(s(5))(1 downto 0);
RETURN result;
END;
FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(15 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
RETURN result;
END;
FUNCTION str3_slv12 (hex: string) return std_logic_vector is
VARIABLE result : std_logic_vector(11 downto 0);
BEGIN
FOR i in 0 to 2 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1));
END LOOP;
RETURN result;
END;
FUNCTION data2addr_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 13;
WHEN 2 =>
result := 12;
WHEN 4 =>
result := 11;
WHEN 9 =>
result := 10;
WHEN 18 =>
result := 9;
WHEN 36 =>
result := 8;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 1;
WHEN 2 =>
result := 2;
WHEN 4 =>
result := 4;
WHEN 9 =>
result := 9;
WHEN 18 =>
result := 18;
WHEN 36 =>
result := 18;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 8;
WHEN 2 =>
result := 4;
WHEN 4 =>
result := 2;
WHEN 9 =>
result := 36864;
WHEN 18 =>
result := 36864;
WHEN 36 =>
result := 36864;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector IS
CONSTANT length : integer := hex'length;
VARIABLE result1 : mem_type_5 (0 to ((length/5)-1));
VARIABLE result : std_logic_vector(((length*18)/5)-1 downto 0);
BEGIN
FOR i in 0 to ((length/5)-1) LOOP
result1(i) := str5_slv18(hex((i+1)*5 downto (i*5)+1));
END LOOP;
IF (DATA_WIDTH_A >= 9 and DATA_WIDTH_B >= 9) THEN
FOR j in 0 to 511 LOOP
result(((j*18) + 17) downto (j*18)) := result1(j)(17 downto 0);
END LOOP;
ELSE
FOR j in 0 to 511 LOOP
result(((j*18) + 7) downto (j*18)) := result1(j)(7 downto 0);
result((j*18) + 8) := '0';
result(((j*18) + 16) downto ((j*18) + 9)) := result1(j)(15 downto 8);
result((j*18) + 17) := '0';
END LOOP;
END IF;
RETURN result;
END;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6 IS
CONSTANT length : integer := hex'length;
VARIABLE result : mem_type_6 (0 to ((length/4)-1));
BEGIN
FOR i in 0 to ((length/4)-1) LOOP
result(i) := str4_slv16(hex((i+1)*4 downto (i*4)+1));
END LOOP;
RETURN result;
END;
-- String to std_logic_vector
FUNCTION str2slv (
str : in string
) return std_logic_vector is
variable j : integer := str'length;
variable slv : std_logic_vector (str'length downto 1);
begin
for i in str'low to str'high loop
case str(i) is
when '0' => slv(j) := '0';
when '1' => slv(j) := '1';
when 'X' => slv(j) := 'X';
when 'U' => slv(j) := 'U';
when others => slv(j) := 'X';
end case;
j := j - 1;
end loop;
return slv;
end str2slv;
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
END mem3 ;
--
----- cell rom256x1 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.mem2.all;
-- entity declaration --
ENTITY rom256x1 IS
GENERIC (
initval : string := "0x0000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "rom256x1";
-- input SIGNAL delays
tipd_ad0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
tpd_ad0_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad1_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad2_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad3_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad4_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad5_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad6_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad7_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns));
port (ad0 : IN std_logic;
ad1 : IN std_logic;
ad2 : IN std_logic;
ad3 : IN std_logic;
ad4 : IN std_logic;
ad5 : IN std_logic;
ad6 : IN std_logic;
ad7 : IN std_logic;
do0 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF rom256x1 : ENTITY IS TRUE;
END rom256x1;
-- architecture body --
ARCHITECTURE v OF rom256x1 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL ad0_ipd : std_logic := 'X';
SIGNAL ad1_ipd : std_logic := 'X';
SIGNAL ad2_ipd : std_logic := 'X';
SIGNAL ad3_ipd : std_logic := 'X';
SIGNAL ad4_ipd : std_logic := 'X';
SIGNAL ad5_ipd : std_logic := 'X';
SIGNAL ad6_ipd : std_logic := 'X';
SIGNAL ad7_ipd : std_logic := 'X';
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ad0_ipd, ad0, tipd_ad0);
VitalWireDelay(ad1_ipd, ad1, tipd_ad1);
VitalWireDelay(ad2_ipd, ad2, tipd_ad2);
VitalWireDelay(ad3_ipd, ad3, tipd_ad3);
VitalWireDelay(ad4_ipd, ad4, tipd_ad4);
VitalWireDelay(ad5_ipd, ad5, tipd_ad5);
VitalWireDelay(ad6_ipd, ad6, tipd_ad6);
VitalWireDelay(ad7_ipd, ad7, tipd_ad7);
END BLOCK;
-----------------------
-- behavior section
-----------------------
VitalBehavior : PROCESS (ad0_ipd, ad1_ipd, ad2_ipd, ad3_ipd, ad4_ipd, ad5_ipd, ad6_ipd, ad7_ipd)
VARIABLE memory : std_logic_vector((2**8)-1 downto 0) := hex2bin(initval);
-- functionality results
VARIABLE do0_zd : std_logic :='X';
-- output glitch results
VARIABLE do0_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- functionality section
------------------------
do0_zd := VitalMUX (data => memory,
dselect => (ad7_ipd, ad6_ipd, ad5_ipd, ad4_ipd, ad3_ipd, ad2_ipd, ad1_ipd, ad0_ipd));
------------------------
-- path delay section
------------------------
VitalPathDelay01 (
OutSignal => do0,
OutSignalName => "do0",
OutTemp => do0_zd,
Paths => (0 => (ad0_ipd'last_event, tpd_ad0_do0, TRUE),
1 => (ad1_ipd'last_event, tpd_ad1_do0, TRUE),
2 => (ad2_ipd'last_event, tpd_ad2_do0, TRUE),
3 => (ad3_ipd'last_event, tpd_ad3_do0, TRUE),
4 => (ad4_ipd'last_event, tpd_ad4_do0, TRUE),
5 => (ad5_ipd'last_event, tpd_ad5_do0, TRUE),
6 => (ad6_ipd'last_event, tpd_ad6_do0, TRUE),
7 => (ad7_ipd'last_event, tpd_ad7_do0, TRUE)),
GlitchData => do0_glitchdata,
Mode => ondetect,
XOn => XOn,
MsgOn => MsgOn);
end process;
end V;
--
----- cell rom128x1 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.mem2.all;
-- entity declaration --
ENTITY rom128x1 IS
GENERIC (
initval : string := "0x00000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "rom128x1";
-- input SIGNAL delays
tipd_ad0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
tpd_ad0_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad1_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad2_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad3_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad4_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad5_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad6_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns));
port (ad0 : IN std_logic;
ad1 : IN std_logic;
ad2 : IN std_logic;
ad3 : IN std_logic;
ad4 : IN std_logic;
ad5 : IN std_logic;
ad6 : IN std_logic;
do0 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF rom128x1 : ENTITY IS TRUE;
END rom128x1;
-- architecture body --
ARCHITECTURE v OF rom128x1 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL ad0_ipd : std_logic := 'X';
SIGNAL ad1_ipd : std_logic := 'X';
SIGNAL ad2_ipd : std_logic := 'X';
SIGNAL ad3_ipd : std_logic := 'X';
SIGNAL ad4_ipd : std_logic := 'X';
SIGNAL ad5_ipd : std_logic := 'X';
SIGNAL ad6_ipd : std_logic := 'X';
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ad0_ipd, ad0, tipd_ad0);
VitalWireDelay(ad1_ipd, ad1, tipd_ad1);
VitalWireDelay(ad2_ipd, ad2, tipd_ad2);
VitalWireDelay(ad3_ipd, ad3, tipd_ad3);
VitalWireDelay(ad4_ipd, ad4, tipd_ad4);
VitalWireDelay(ad5_ipd, ad5, tipd_ad5);
VitalWireDelay(ad6_ipd, ad6, tipd_ad6);
END BLOCK;
-----------------------
-- behavior section
-----------------------
VitalBehavior : PROCESS (ad0_ipd, ad1_ipd, ad2_ipd, ad3_ipd, ad4_ipd, ad5_ipd, ad6_ipd)
VARIABLE memory : std_logic_vector((2**7)-1 downto 0) := hex2bin(initval);
-- functionality results
VARIABLE do0_zd : std_logic :='X';
-- output glitch results
VARIABLE do0_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- functionality section
------------------------
do0_zd := VitalMUX (data => memory,
dselect => (ad6_ipd, ad5_ipd, ad4_ipd, ad3_ipd, ad2_ipd, ad1_ipd, ad0_ipd));
------------------------
-- path delay section
------------------------
VitalPathDelay01 (
OutSignal => do0,
OutSignalName => "do0",
OutTemp => do0_zd,
Paths => (0 => (ad0_ipd'last_event, tpd_ad0_do0, TRUE),
1 => (ad1_ipd'last_event, tpd_ad1_do0, TRUE),
2 => (ad2_ipd'last_event, tpd_ad2_do0, TRUE),
3 => (ad3_ipd'last_event, tpd_ad3_do0, TRUE),
4 => (ad4_ipd'last_event, tpd_ad4_do0, TRUE),
5 => (ad5_ipd'last_event, tpd_ad5_do0, TRUE),
6 => (ad6_ipd'last_event, tpd_ad6_do0, TRUE)),
GlitchData => do0_glitchdata,
Mode => ondetect,
XOn => XOn,
MsgOn => MsgOn);
end process;
end V;
--
----- cell rom64x1 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.mem2.all;
-- entity declaration --
ENTITY rom64x1 IS
GENERIC (
initval : string := "0x0000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "rom64x1";
-- input SIGNAL delays
tipd_ad0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
tpd_ad0_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad1_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad2_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad3_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad4_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad5_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns));
port (ad0 : IN std_logic;
ad1 : IN std_logic;
ad2 : IN std_logic;
ad3 : IN std_logic;
ad4 : IN std_logic;
ad5 : IN std_logic;
do0 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF rom64x1 : ENTITY IS TRUE;
END rom64x1;
-- architecture body --
ARCHITECTURE v OF rom64x1 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL ad0_ipd : std_logic := 'X';
SIGNAL ad1_ipd : std_logic := 'X';
SIGNAL ad2_ipd : std_logic := 'X';
SIGNAL ad3_ipd : std_logic := 'X';
SIGNAL ad4_ipd : std_logic := 'X';
SIGNAL ad5_ipd : std_logic := 'X';
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ad0_ipd, ad0, tipd_ad0);
VitalWireDelay(ad1_ipd, ad1, tipd_ad1);
VitalWireDelay(ad2_ipd, ad2, tipd_ad2);
VitalWireDelay(ad3_ipd, ad3, tipd_ad3);
VitalWireDelay(ad4_ipd, ad4, tipd_ad4);
VitalWireDelay(ad5_ipd, ad5, tipd_ad5);
END BLOCK;
-----------------------
-- behavior section
-----------------------
VitalBehavior : PROCESS (ad0_ipd, ad1_ipd, ad2_ipd, ad3_ipd, ad4_ipd, ad5_ipd)
VARIABLE memory : std_logic_vector((2**6)-1 downto 0) := hex2bin(initval);
-- functionality results
VARIABLE do0_zd : std_logic :='X';
-- output glitch results
VARIABLE do0_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- functionality section
------------------------
do0_zd := VitalMUX (data => memory,
dselect => (ad5_ipd, ad4_ipd, ad3_ipd, ad2_ipd, ad1_ipd, ad0_ipd));
------------------------
-- path delay section
------------------------
VitalPathDelay01 (
OutSignal => do0,
OutSignalName => "do0",
OutTemp => do0_zd,
Paths => (0 => (ad0_ipd'last_event, tpd_ad0_do0, TRUE),
1 => (ad1_ipd'last_event, tpd_ad1_do0, TRUE),
2 => (ad2_ipd'last_event, tpd_ad2_do0, TRUE),
3 => (ad3_ipd'last_event, tpd_ad3_do0, TRUE),
4 => (ad4_ipd'last_event, tpd_ad4_do0, TRUE),
5 => (ad5_ipd'last_event, tpd_ad5_do0, TRUE)),
GlitchData => do0_glitchdata,
Mode => ondetect,
XOn => XOn,
MsgOn => MsgOn);
end process;
end V;
--
----- cell rom32x1 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.mem2.all;
-- entity declaration --
ENTITY rom32x1 IS
GENERIC (
initval : string := "0x00000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := FALSE;
XOn : boolean := FALSE;
MsgOn : boolean := FALSE;
InstancePath : string := "rom32x1";
-- input SIGNAL delays
tipd_ad0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
tpd_ad0_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad1_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad2_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad3_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad4_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns));
port (ad0 : IN std_logic;
ad1 : IN std_logic;
ad2 : IN std_logic;
ad3 : IN std_logic;
ad4 : IN std_logic;
do0 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF rom32x1 : ENTITY IS TRUE;
END rom32x1;
-- architecture body --
ARCHITECTURE v OF rom32x1 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL ad0_ipd : std_logic := 'X';
SIGNAL ad1_ipd : std_logic := 'X';
SIGNAL ad2_ipd : std_logic := 'X';
SIGNAL ad3_ipd : std_logic := 'X';
SIGNAL ad4_ipd : std_logic := 'X';
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ad0_ipd, ad0, tipd_ad0);
VitalWireDelay(ad1_ipd, ad1, tipd_ad1);
VitalWireDelay(ad2_ipd, ad2, tipd_ad2);
VitalWireDelay(ad3_ipd, ad3, tipd_ad3);
VitalWireDelay(ad4_ipd, ad4, tipd_ad4);
END BLOCK;
-----------------------
-- behavior section
-----------------------
VitalBehavior : PROCESS (ad0_ipd, ad1_ipd, ad2_ipd, ad3_ipd, ad4_ipd)
VARIABLE memory : std_logic_vector((2**5)-1 downto 0) := hex2bin(initval);
-- functionality results
VARIABLE do0_zd : std_logic :='X';
-- output glitch results
VARIABLE do0_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- functionality section
------------------------
do0_zd := VitalMUX (data => memory,
dselect => (ad4_ipd, ad3_ipd, ad2_ipd, ad1_ipd, ad0_ipd));
------------------------
-- path delay section
------------------------
VitalPathDelay01 (
OutSignal => do0,
OutSignalName => "do0",
OutTemp => do0_zd,
Paths => (0 => (ad0_ipd'last_event, tpd_ad0_do0, TRUE),
1 => (ad1_ipd'last_event, tpd_ad1_do0, TRUE),
2 => (ad2_ipd'last_event, tpd_ad2_do0, TRUE),
3 => (ad3_ipd'last_event, tpd_ad3_do0, TRUE),
4 => (ad4_ipd'last_event, tpd_ad4_do0, TRUE)),
GlitchData => do0_glitchdata,
Mode => ondetect,
XOn => XOn,
MsgOn => MsgOn);
end process;
end V;
--
----- cell rom16x1 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.mem2.all;
-- entity declaration --
ENTITY rom16x1 IS
GENERIC (
initval : string := "0x0000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "rom16x1";
-- input SIGNAL delays
tipd_ad0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
tpd_ad0_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad1_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad2_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns);
tpd_ad3_do0 : VitalDelayType01 := (0.01 ns, 0.01 ns));
port (ad0 : IN std_logic;
ad1 : IN std_logic;
ad2 : IN std_logic;
ad3 : IN std_logic;
do0 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF rom16x1 : ENTITY IS TRUE;
END rom16x1;
-- architecture body --
ARCHITECTURE v OF rom16x1 IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL ad0_ipd : std_logic := 'X';
SIGNAL ad1_ipd : std_logic := 'X';
SIGNAL ad2_ipd : std_logic := 'X';
SIGNAL ad3_ipd : std_logic := 'X';
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ad0_ipd, ad0, tipd_ad0);
VitalWireDelay(ad1_ipd, ad1, tipd_ad1);
VitalWireDelay(ad2_ipd, ad2, tipd_ad2);
VitalWireDelay(ad3_ipd, ad3, tipd_ad3);
END BLOCK;
-----------------------
-- behavior section
-----------------------
VitalBehavior : PROCESS (ad0_ipd, ad1_ipd, ad2_ipd, ad3_ipd)
VARIABLE memory : std_logic_vector((2**4)-1 downto 0) := hex2bin(initval);
-- functionality results
VARIABLE do0_zd : std_logic :='X';
-- output glitch results
VARIABLE do0_GlitchData : VitalGlitchDataType;
BEGIN
------------------------
-- functionality section
------------------------
do0_zd := VitalMUX (data => memory,
dselect => (ad3_ipd, ad2_ipd, ad1_ipd, ad0_ipd));
------------------------
-- path delay section
------------------------
VitalPathDelay01 (
OutSignal => do0,
OutSignalName => "do0",
OutTemp => do0_zd,
Paths => (0 => (ad0_ipd'last_event, tpd_ad0_do0, TRUE),
1 => (ad1_ipd'last_event, tpd_ad1_do0, TRUE),
2 => (ad2_ipd'last_event, tpd_ad2_do0, TRUE),
3 => (ad3_ipd'last_event, tpd_ad3_do0, TRUE)),
GlitchData => do0_glitchdata,
Mode => ondetect,
XOn => XOn,
MsgOn => MsgOn);
end process;
end V;
----- cell dpr16x2b -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.mem1.all;
USE work.global.gsrnet;
USE work.global.purnet;
-- entity declaration --
ENTITY dpr16x2b IS
GENERIC (
disabled_gsr : Integer := 0;
initval : string := "0x0000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dpr16x2b";
-- input SIGNAL delays
tipd_rad0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rad1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rad2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rad3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wad0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wad1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wad2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wad3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_di0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_di1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wre : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- setup and hold constraints
tsetup_wad0_wck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_wad1_wck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_wad2_wck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_wad3_wck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_wre_wck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_di0_wck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_di1_wck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_wad0_wck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_wad1_wck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_wad2_wck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_wad3_wck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_wre_wck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_di0_wck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_di1_wck_noedge_posedge : VitalDelayType := 0.0 ns;
-- pulse width constraints
tperiod_wre : VitalDelayType := 0.001 ns;
tpw_wre_posedge : VitalDelayType := 0.001 ns;
tpw_wre_negedge : VitalDelayType := 0.001 ns;
tperiod_wck : VitalDelayType := 0.001 ns;
tpw_wck_posedge : VitalDelayType := 0.001 ns;
tpw_wck_negedge : VitalDelayType := 0.001 ns;
-- propagation delays
tpd_wck_wdo0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_wck_wdo1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_rad0_rdo0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_rad1_rdo0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_rad2_rdo0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_rad3_rdo0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_rad0_rdo1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_rad1_rdo1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_rad2_rdo1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_rad3_rdo1 : VitalDelayType01 := (0.001 ns, 0.001 ns));
port (di0 : IN std_logic;
di1 : IN std_logic;
wck : IN std_logic;
wre : IN std_logic;
rad0 : IN std_logic;
rad1 : IN std_logic;
rad2 : IN std_logic;
rad3 : IN std_logic;
wad0 : IN std_logic;
wad1 : IN std_logic;
wad2 : IN std_logic;
wad3 : IN std_logic;
wdo0 : OUT std_logic;
wdo1 : OUT std_logic;
rdo0 : OUT std_logic;
rdo1 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF dpr16x2b : ENTITY IS TRUE;
END dpr16x2b;
-- architecture body --
ARCHITECTURE v OF dpr16x2b IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL di0_ipd : std_logic := 'X';
SIGNAL di1_ipd : std_logic := 'X';
SIGNAL rad0_ipd : std_logic := 'X';
SIGNAL rad1_ipd : std_logic := 'X';
SIGNAL rad2_ipd : std_logic := 'X';
SIGNAL rad3_ipd : std_logic := 'X';
SIGNAL wad0_ipd : std_logic := 'X';
SIGNAL wad1_ipd : std_logic := 'X';
SIGNAL wad2_ipd : std_logic := 'X';
SIGNAL wad3_ipd : std_logic := 'X';
SIGNAL wre_ipd : std_logic := 'X';
SIGNAL wck_ipd : std_logic := 'X';
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(di0_ipd, di0, tipd_di0);
VitalWireDelay(di1_ipd, di1, tipd_di1);
VitalWireDelay(rad0_ipd, rad0, tipd_rad0);
VitalWireDelay(rad1_ipd, rad1, tipd_rad1);
VitalWireDelay(rad2_ipd, rad2, tipd_rad2);
VitalWireDelay(rad3_ipd, rad3, tipd_rad3);
VitalWireDelay(wad0_ipd, wad0, tipd_wad0);
VitalWireDelay(wad1_ipd, wad1, tipd_wad1);
VitalWireDelay(wad2_ipd, wad2, tipd_wad2);
VitalWireDelay(wad3_ipd, wad3, tipd_wad3);
VitalWireDelay(wre_ipd, wre, tipd_wre);
VitalWireDelay(wck_ipd, wck, tipd_wck);
END BLOCK;
-----------------------
-- behavior section
-----------------------
VitalBehavior : PROCESS (wck_ipd, wre_ipd, wad0_ipd,
wad1_ipd, wad2_ipd, wad3_ipd, rad0_ipd, rad1_ipd, rad2_ipd,
rad3_ipd, di0_ipd, di1_ipd, gsrnet, purnet)
VARIABLE memory : mem_type_2 ((2**4)-1 downto 0) := init_ram(initval);
VARIABLE radr_reg, wadr_reg, wadr_reg1 : std_logic_vector(3 downto 0) := "0000";
VARIABLE din_reg : std_logic_vector(1 downto 0) := "00";
VARIABLE wre_reg : std_logic := '0';
VARIABLE rindex, windex, windex1 : integer := 0;
VARIABLE set_reset : std_logic := '1';
-- timing check results
VARIABLE tviol_di0 : x01 := '0';
VARIABLE tviol_di1 : x01 := '0';
VARIABLE tviol_wad0 : x01 := '0';
VARIABLE tviol_wad1 : x01 := '0';
VARIABLE tviol_wad2 : x01 := '0';
VARIABLE tviol_wad3 : x01 := '0';
VARIABLE tviol_wre : x01 := '0';
VARIABLE tsviol_wre : x01 := '0';
VARIABLE tviol_wck : x01 := '0';
VARIABLE PeriodCheckInfo_wre : VitalPeriodDataType;
VARIABLE PeriodCheckInfo_wck : VitalPeriodDataType;
VARIABLE wad0_wck_TimingDatash : VitalTimingDataType;
VARIABLE wad1_wck_TimingDatash : VitalTimingDataType;
VARIABLE wad2_wck_TimingDatash : VitalTimingDataType;
VARIABLE wad3_wck_TimingDatash : VitalTimingDataType;
VARIABLE wre_wck_TimingDatash : VitalTimingDataType;
VARIABLE di0_wck_TimingDatash : VitalTimingDataType;
VARIABLE di1_wck_TimingDatash : VitalTimingDataType;
-- functionality results
VARIABLE violation : x01 := '0';
VARIABLE results : std_logic_vector (3 downto 0) := (others => 'X');
ALIAS wdo0_zd : std_ulogic IS results(0);
ALIAS wdo1_zd : std_ulogic IS results(1);
ALIAS rdo0_zd : std_ulogic IS results(2);
ALIAS rdo1_zd : std_ulogic IS results(3);
-- output glitch results
VARIABLE wdo0_GlitchData : VitalGlitchDataType;
VARIABLE wdo1_GlitchData : VitalGlitchDataType;
VARIABLE rdo0_GlitchData : VitalGlitchDataType;
VARIABLE rdo1_GlitchData : VitalGlitchDataType;
BEGIN
-----------------------
-- timing check section
-----------------------
IF (TimingChecksOn) THEN
-- setup and hold checks on the write address lines
VitalSetupHoldCheck (
TestSignal => wad0_ipd,
TestSignalName => "wad0",
RefSignal => wck_ipd,
RefSignalName => "wck",
SetupHigh => tsetup_wad0_wck_noedge_posedge,
setuplow => tsetup_wad0_wck_noedge_posedge,
HoldHigh => thold_wad0_wck_noedge_posedge,
HoldLow => thold_wad0_wck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => wad0_wck_timingdatash,
Violation => tviol_wad0,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => wad1_ipd,
TestSignalName => "wad1",
RefSignal => wck_ipd,
RefSignalName => "wck",
SetupHigh => tsetup_wad1_wck_noedge_posedge,
setuplow => tsetup_wad1_wck_noedge_posedge,
HoldHigh => thold_wad1_wck_noedge_posedge,
HoldLow => thold_wad1_wck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => wad1_wck_timingdatash,
Violation => tviol_wad1,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => wad2_ipd,
TestSignalName => "wad2",
RefSignal => wck_ipd,
RefSignalName => "wck",
SetupHigh => tsetup_wad2_wck_noedge_posedge,
setuplow => tsetup_wad2_wck_noedge_posedge,
HoldHigh => thold_wad2_wck_noedge_posedge,
HoldLow => thold_wad2_wck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => wad2_wck_timingdatash,
Violation => tviol_wad2,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => wad3_ipd,
TestSignalName => "wad3",
RefSignal => wck_ipd,
RefSignalName => "wck",
SetupHigh => tsetup_wad3_wck_noedge_posedge,
setuplow => tsetup_wad3_wck_noedge_posedge,
HoldHigh => thold_wad3_wck_noedge_posedge,
HoldLow => thold_wad3_wck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => wad3_wck_timingdatash,
Violation => tviol_wad3,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => wre_ipd,
TestSignalName => "wre",
RefSignal => wck_ipd,
RefSignalName => "wck",
SetupHigh => tsetup_wre_wck_noedge_posedge,
setuplow => tsetup_wre_wck_noedge_posedge,
HoldHigh => thold_wre_wck_noedge_posedge,
HoldLow => thold_wre_wck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => wre_wck_timingdatash,
Violation => tsviol_wre,
MsgSeverity => warning);
-- setup and hold checks on data
VitalSetupHoldCheck (
TestSignal => di0_ipd,
TestSignalName => "di0",
RefSignal => wck_ipd,
RefSignalName => "wck",
SetupHigh => tsetup_di0_wck_noedge_posedge,
setuplow => tsetup_di0_wck_noedge_posedge,
HoldHigh => thold_di0_wck_noedge_posedge,
HoldLow => thold_di0_wck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => di0_wck_timingdatash,
Violation => tviol_di0,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => di1_ipd,
TestSignalName => "di1",
RefSignal => wck_ipd,
RefSignalName => "wck",
SetupHigh => tsetup_di1_wck_noedge_posedge,
setuplow => tsetup_di1_wck_noedge_posedge,
HoldHigh => thold_di1_wck_noedge_posedge,
HoldLow => thold_di1_wck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => di1_wck_timingdatash,
Violation => tviol_di1,
MsgSeverity => warning);
-- Period and pulse width checks on write and port enables
VitalPeriodPulseCheck (
TestSignal => wck_ipd,
TestSignalName => "wck",
Period => tperiod_wck,
PulseWidthHigh => tpw_wck_posedge,
PulseWidthLow => tpw_wck_posedge,
Perioddata => periodcheckinfo_wck,
Violation => tviol_wck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => wre_ipd,
TestSignalName => "wre",
Period => tperiod_wre,
PulseWidthHigh => tpw_wre_posedge,
PulseWidthLow => tpw_wre_posedge,
Perioddata => periodcheckinfo_wre,
Violation => tviol_wre,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
------------------------
-- functionality section
------------------------
-- IF (disabled_gsr = 1) THEN
-- set_reset := purnet;
-- ELSE
-- set_reset := purnet AND gsrnet;
-- END IF;
-- IF (set_reset= '0') THEN
-- wre_reg := '0';
-- wadr_reg := "0000";
-- END IF;
Violation := tviol_di0 or tviol_di1 or tviol_wad0 or tviol_wad1 or tviol_wad2 or
tviol_wad3 or tviol_wre or tviol_wck or tsviol_wre ;
IF ((is_x(wre_ipd)) and (set_reset='1')) THEN
assert FALSE
report "dpr16x2b memory hazard write enable unknown!"
severity warning;
results := (others => 'X');
ELSIF (is_x(rad0_ipd) or is_x(rad1_ipd) or is_x(rad2_ipd)
or is_x(rad3_ipd)) THEN
assert FALSE
report "dpr16x2b memory hazard read address unknown!"
severity warning;
results := (others => 'X');
ELSIF ((is_x(wad0_ipd) or is_x(wad1_ipd) or is_x(wad2_ipd)
or is_x(wad3_ipd)) and (set_reset='1')) THEN
assert FALSE
report "dpr16x2b memory hazard write address unknown!"
severity warning;
results := (others => 'X');
ELSE
-- register the write address, write enables and data but not the
-- read address
IF ((wck_ipd'event and wck_ipd = '1') and (set_reset= '1')) THEN
wre_reg := (wre_ipd);
din_reg := (di1_ipd, di0_ipd);
wadr_reg := (wad3_ipd, wad2_ipd, wad1_ipd, wad0_ipd);
END IF;
windex := conv_integer(wadr_reg);
radr_reg := (rad3_ipd, rad2_ipd, rad1_ipd, rad0_ipd);
rindex := conv_integer(radr_reg);
wadr_reg1 := (wad3_ipd, wad2_ipd, wad1_ipd, wad0_ipd);
windex1 := conv_integer(wadr_reg1);
-- at the falling edge of wck, write to memory at address
IF (wre_reg = '1') THEN
IF (wck_ipd'event and wck_ipd = '1') THEN
memory(windex) := din_reg;
END IF;
END IF;
-- asynchronous and synchronous reads
IF (violation = '0') THEN
results(3 downto 2) := memory(rindex);
results(1 downto 0) := memory(windex1);
ELSE
results := (others => 'X');
END IF;
END IF;
------------------------
-- path delay section
------------------------
VitalPathDelay01 (
OutSignal => wdo0,
OutSignalName => "wdo0",
OutTemp => wdo0_zd,
Paths => (0 => (wck_ipd'last_event, tpd_wck_wdo0, TRUE)),
GlitchData => wdo0_glitchdata,
Mode => ondetect,
XOn => XOn, MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => wdo1,
OutSignalName => "wdo1",
OutTemp => wdo1_zd,
Paths => (0 => (wck_ipd'last_event, tpd_wck_wdo1, TRUE)),
GlitchData => wdo1_glitchdata,
Mode => ondetect,
XOn => XOn, MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => rdo0,
OutSignalName => "rdo0",
OutTemp => rdo0_zd,
Paths => (0 => (rad0_ipd'last_event, tpd_rad0_rdo0, TRUE),
1 => (rad1_ipd'last_event, tpd_rad1_rdo0, TRUE),
2 => (rad2_ipd'last_event, tpd_rad2_rdo0, TRUE),
3 => (rad3_ipd'last_event, tpd_rad3_rdo0, TRUE)),
GlitchData => rdo0_glitchdata,
Mode => ondetect,
XOn => XOn, MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => rdo1,
OutSignalName => "rdo1",
OutTemp => rdo1_zd,
Paths => (0 => (rad0_ipd'last_event, tpd_rad0_rdo1, TRUE),
1 => (rad1_ipd'last_event, tpd_rad1_rdo1, TRUE),
2 => (rad2_ipd'last_event, tpd_rad2_rdo1, TRUE),
3 => (rad3_ipd'last_event, tpd_rad3_rdo1, TRUE)),
GlitchData => rdo1_glitchdata,
Mode => ondetect,
XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
--
----- cell spr16x2b -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.vital_timing.all;
USE ieee.vital_primitives.all;
USE work.mem1.all;
USE work.global.gsrnet;
USE work.global.purnet;
-- entity declaration --
ENTITY spr16x2b IS
GENERIC (
disabled_gsr : Integer := 0;
initval : string := "0x0000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "spr16x2b";
-- input SIGNAL delays
tipd_ad0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ad3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_di0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_di1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wre : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ck : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- setup and hold constraints
tsetup_ad0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_ad1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_ad2_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_ad3_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_wre_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_di0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
tsetup_di1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_ad0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_ad1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_ad2_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_ad3_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_wre_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_di0_ck_noedge_posedge : VitalDelayType := 0.0 ns;
thold_di1_ck_noedge_posedge : VitalDelayType := 0.0 ns;
-- pulse width constraints
tperiod_wre : VitalDelayType := 0.001 ns;
tpw_wre_posedge : VitalDelayType := 0.001 ns;
tpw_wre_negedge : VitalDelayType := 0.001 ns;
tperiod_ck : VitalDelayType := 0.001 ns;
tpw_ck_posedge : VitalDelayType := 0.001 ns;
tpw_ck_negedge : VitalDelayType := 0.001 ns;
-- propagation delays
tpd_ck_do0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_ck_do1 : VitalDelayType01 := (0.001 ns, 0.001 ns));
port (di0 : IN std_logic;
di1 : IN std_logic;
ck : IN std_logic;
wre : IN std_logic;
ad0 : IN std_logic;
ad1 : IN std_logic;
ad2 : IN std_logic;
ad3 : IN std_logic;
do0 : OUT std_logic;
do1 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF spr16x2b : ENTITY IS TRUE;
END spr16x2b;
-- architecture body --
ARCHITECTURE v OF spr16x2b IS
ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE;
SIGNAL di0_ipd : std_logic := 'X';
SIGNAL di1_ipd : std_logic := 'X';
SIGNAL ad0_ipd : std_logic := 'X';
SIGNAL ad1_ipd : std_logic := 'X';
SIGNAL ad2_ipd : std_logic := 'X';
SIGNAL ad3_ipd : std_logic := 'X';
SIGNAL wre_ipd : std_logic := 'X';
SIGNAL ck_ipd : std_logic := 'X';
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(di0_ipd, di0, tipd_di0);
VitalWireDelay(di1_ipd, di1, tipd_di1);
VitalWireDelay(ad0_ipd, ad0, tipd_ad0);
VitalWireDelay(ad1_ipd, ad1, tipd_ad1);
VitalWireDelay(ad2_ipd, ad2, tipd_ad2);
VitalWireDelay(ad3_ipd, ad3, tipd_ad3);
VitalWireDelay(wre_ipd, wre, tipd_wre);
VitalWireDelay(ck_ipd, ck, tipd_ck);
END BLOCK;
-----------------------
-- behavior section
-----------------------
VitalBehavior : PROCESS (ck_ipd, wre_ipd, ad0_ipd,
ad1_ipd, ad2_ipd, ad3_ipd, di0_ipd, di1_ipd, gsrnet, purnet)
VARIABLE memory : mem_type_2 ((2**4)-1 downto 0) := init_ram(initval);
VARIABLE radr_reg, wadr_reg : std_logic_vector(3 downto 0) := "0000";
VARIABLE din_reg : std_logic_vector(1 downto 0) := "00";
VARIABLE wre_reg : std_logic := '0';
VARIABLE rindex, windex : integer := 0;
VARIABLE set_reset : std_logic := '1';
-- timing check results
VARIABLE tviol_di0 : x01 := '0';
VARIABLE tviol_di1 : x01 := '0';
VARIABLE tviol_ad0 : x01 := '0';
VARIABLE tviol_ad1 : x01 := '0';
VARIABLE tviol_ad2 : x01 := '0';
VARIABLE tviol_ad3 : x01 := '0';
VARIABLE tviol_wre : x01 := '0';
VARIABLE tsviol_wre : x01 := '0';
VARIABLE tviol_ck : x01 := '0';
VARIABLE PeriodCheckInfo_wre : VitalPeriodDataType;
VARIABLE PeriodCheckInfo_ck : VitalPeriodDataType;
VARIABLE ad0_ck_TimingDatash : VitalTimingDataType;
VARIABLE ad1_ck_TimingDatash : VitalTimingDataType;
VARIABLE ad2_ck_TimingDatash : VitalTimingDataType;
VARIABLE ad3_ck_TimingDatash : VitalTimingDataType;
VARIABLE wre_ck_TimingDatash : VitalTimingDataType;
VARIABLE di0_ck_TimingDatash : VitalTimingDataType;
VARIABLE di1_ck_TimingDatash : VitalTimingDataType;
-- functionality results
VARIABLE violation : x01 := '0';
VARIABLE results : std_logic_vector (1 downto 0) := (others => 'X');
ALIAS do0_zd : std_ulogic IS results(0);
ALIAS do1_zd : std_ulogic IS results(1);
-- output glitch results
VARIABLE do0_GlitchData : VitalGlitchDataType;
VARIABLE do1_GlitchData : VitalGlitchDataType;
BEGIN
-----------------------
-- timing check section
-----------------------
IF (TimingChecksOn) THEN
-- setup and hold checks on the write address lines
VitalSetupHoldCheck (
TestSignal => ad0_ipd,
TestSignalName => "ad0",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_ad0_ck_noedge_posedge,
setuplow => tsetup_ad0_ck_noedge_posedge,
HoldHigh => thold_ad0_ck_noedge_posedge,
HoldLow => thold_ad0_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => ad0_ck_timingdatash,
Violation => tviol_ad0,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => ad1_ipd,
TestSignalName => "ad1",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_ad1_ck_noedge_posedge,
setuplow => tsetup_ad1_ck_noedge_posedge,
HoldHigh => thold_ad1_ck_noedge_posedge,
HoldLow => thold_ad1_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => ad1_ck_timingdatash,
Violation => tviol_ad1,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => ad2_ipd,
TestSignalName => "ad2",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_ad2_ck_noedge_posedge,
setuplow => tsetup_ad2_ck_noedge_posedge,
HoldHigh => thold_ad2_ck_noedge_posedge,
HoldLow => thold_ad2_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => ad2_ck_timingdatash,
Violation => tviol_ad2,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => ad3_ipd,
TestSignalName => "ad3",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_ad3_ck_noedge_posedge,
setuplow => tsetup_ad3_ck_noedge_posedge,
HoldHigh => thold_ad3_ck_noedge_posedge,
HoldLow => thold_ad3_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => ad3_ck_timingdatash,
Violation => tviol_ad3,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => wre_ipd,
TestSignalName => "wre",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_wre_ck_noedge_posedge,
setuplow => tsetup_wre_ck_noedge_posedge,
HoldHigh => thold_wre_ck_noedge_posedge,
HoldLow => thold_wre_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => wre_ck_timingdatash,
Violation => tsviol_wre,
MsgSeverity => warning);
-- setup and hold checks on data
VitalSetupHoldCheck (
TestSignal => di0_ipd,
TestSignalName => "di0",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_di0_ck_noedge_posedge,
setuplow => tsetup_di0_ck_noedge_posedge,
HoldHigh => thold_di0_ck_noedge_posedge,
HoldLow => thold_di0_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => di0_ck_timingdatash,
Violation => tviol_di0,
MsgSeverity => warning);
VitalSetupHoldCheck (
TestSignal => di1_ipd,
TestSignalName => "di1",
RefSignal => ck_ipd,
RefSignalName => "ck",
SetupHigh => tsetup_di1_ck_noedge_posedge,
setuplow => tsetup_di1_ck_noedge_posedge,
HoldHigh => thold_di1_ck_noedge_posedge,
HoldLow => thold_di1_ck_noedge_posedge,
CheckEnabled => (set_reset='1'),
RefTransition => '/',
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
TimingData => di1_ck_timingdatash,
Violation => tviol_di1,
MsgSeverity => warning);
-- Period and pulse width checks on write and port enables
VitalPeriodPulseCheck (
TestSignal => ck_ipd,
TestSignalName => "ck",
Period => tperiod_ck,
PulseWidthHigh => tpw_ck_posedge,
PulseWidthLow => tpw_ck_posedge,
Perioddata => periodcheckinfo_ck,
Violation => tviol_ck,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => warning);
VitalPeriodPulseCheck (
TestSignal => wre_ipd,
TestSignalName => "wre",
Period => tperiod_wre,
PulseWidthHigh => tpw_wre_posedge,
PulseWidthLow => tpw_wre_posedge,
Perioddata => periodcheckinfo_wre,
Violation => tviol_wre,
MsgOn => MsgOn, XOn => XOn,
HeaderMsg => InstancePath,
CheckEnabled => TRUE,
MsgSeverity => warning);
END IF;
------------------------
-- functionality section
------------------------
-- IF (disabled_gsr = 1) THEN
-- set_reset := purnet;
-- ELSE
-- set_reset := purnet AND gsrnet;
-- END IF;
-- IF (set_reset= '0') THEN
-- wre_reg := '0';
-- wadr_reg := "0000";
-- END IF;
Violation := tviol_di0 or tviol_di0 or tviol_ad0 or tviol_ad1 or tviol_ad2 or
tviol_ad3 or tviol_wre or tviol_ck or tsviol_wre;
IF ((is_x(wre_ipd)) and (set_reset='1')) THEN
assert FALSE
report "spr16x2b memory hazard write enable unknown!"
severity warning;
results := (others => 'X');
ELSIF (is_x(ad0_ipd) or is_x(ad1_ipd) or is_x(ad2_ipd)
or is_x(ad3_ipd)) THEN
assert FALSE
report "spr16x2b memory hazard read address unknown!"
severity warning;
results := (others => 'X');
ELSE
-- register the write address, write enables and data but not the
-- read address
IF ((ck_ipd'event and ck_ipd = '1') and (set_reset= '1')) THEN
wre_reg := (wre_ipd);
din_reg := (di1_ipd, di0_ipd);
wadr_reg := (ad3_ipd, ad2_ipd, ad1_ipd, ad0_ipd);
END IF;
windex := conv_integer(wadr_reg);
radr_reg := (ad3_ipd, ad2_ipd, ad1_ipd, ad0_ipd);
rindex := conv_integer(radr_reg);
-- at the falling edge of ck, write to memory at address
IF (wre_reg = '1') THEN
IF (ck_ipd'event and ck_ipd = '1') THEN
memory(windex) := din_reg;
END IF;
END IF;
-- asynchronous and synchronous reads
IF (violation = '0') THEN
results(1 downto 0) := memory(rindex);
ELSE
results := (others => 'X');
END IF;
END IF;
------------------------
-- path delay section
------------------------
VitalPathDelay01 (
OutSignal => do0,
OutSignalName => "do0",
OutTemp => do0_zd,
Paths => (0 => (ck_ipd'last_event, tpd_ck_do0, TRUE)),
GlitchData => do0_glitchdata,
Mode => ondetect,
XOn => XOn, MsgOn => MsgOn);
VitalPathDelay01 (
OutSignal => do1,
OutSignalName => "do1",
OutTemp => do1_zd,
Paths => (0 => (ck_ipd'last_event, tpd_ck_do1, TRUE)),
GlitchData => do1_glitchdata,
Mode => ondetect,
XOn => XOn, MsgOn => MsgOn);
END PROCESS;
END v;
----- CELL MULT18X18 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.components.all;
use work.global.gsrnet;
use work.global.purnet;
-- entity declaration --
entity MULT18X18 is
generic(
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
REG_SIGNEDAB_0_CLK : string := "NONE";
REG_SIGNEDAB_0_CE : string := "CE0";
REG_SIGNEDAB_0_RST : string := "RST0";
REG_SIGNEDAB_1_CLK : string := "NONE";
REG_SIGNEDAB_1_CE : string := "CE0";
REG_SIGNEDAB_1_RST : string := "RST0";
SHIFT_IN_A : string := "FALSE";
SHIFT_IN_B : string := "FALSE";
GSR : string := "ENABLED");
port (
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
A5 : in STD_ULOGIC;
A6 : in STD_ULOGIC;
A7 : in STD_ULOGIC;
A8 : in STD_ULOGIC;
A9 : in STD_ULOGIC;
A10 : in STD_ULOGIC;
A11 : in STD_ULOGIC;
A12 : in STD_ULOGIC;
A13 : in STD_ULOGIC;
A14 : in STD_ULOGIC;
A15 : in STD_ULOGIC;
A16 : in STD_ULOGIC;
A17 : in STD_ULOGIC;
SRIA0 : in STD_ULOGIC;
SRIA1 : in STD_ULOGIC;
SRIA2 : in STD_ULOGIC;
SRIA3 : in STD_ULOGIC;
SRIA4 : in STD_ULOGIC;
SRIA5 : in STD_ULOGIC;
SRIA6 : in STD_ULOGIC;
SRIA7 : in STD_ULOGIC;
SRIA8 : in STD_ULOGIC;
SRIA9 : in STD_ULOGIC;
SRIA10 : in STD_ULOGIC;
SRIA11 : in STD_ULOGIC;
SRIA12 : in STD_ULOGIC;
SRIA13 : in STD_ULOGIC;
SRIA14 : in STD_ULOGIC;
SRIA15 : in STD_ULOGIC;
SRIA16 : in STD_ULOGIC;
SRIA17 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
B2 : in STD_ULOGIC;
B3 : in STD_ULOGIC;
B4 : in STD_ULOGIC;
B5 : in STD_ULOGIC;
B6 : in STD_ULOGIC;
B7 : in STD_ULOGIC;
B8 : in STD_ULOGIC;
B9 : in STD_ULOGIC;
B10 : in STD_ULOGIC;
B11 : in STD_ULOGIC;
B12 : in STD_ULOGIC;
B13 : in STD_ULOGIC;
B14 : in STD_ULOGIC;
B15 : in STD_ULOGIC;
B16 : in STD_ULOGIC;
B17 : in STD_ULOGIC;
SRIB0 : in STD_ULOGIC;
SRIB1 : in STD_ULOGIC;
SRIB2 : in STD_ULOGIC;
SRIB3 : in STD_ULOGIC;
SRIB4 : in STD_ULOGIC;
SRIB5 : in STD_ULOGIC;
SRIB6 : in STD_ULOGIC;
SRIB7 : in STD_ULOGIC;
SRIB8 : in STD_ULOGIC;
SRIB9 : in STD_ULOGIC;
SRIB10 : in STD_ULOGIC;
SRIB11 : in STD_ULOGIC;
SRIB12 : in STD_ULOGIC;
SRIB13 : in STD_ULOGIC;
SRIB14 : in STD_ULOGIC;
SRIB15 : in STD_ULOGIC;
SRIB16 : in STD_ULOGIC;
SRIB17 : in STD_ULOGIC;
SIGNEDAB : in STD_ULOGIC;
CE0 : in STD_ULOGIC;
CE1 : in STD_ULOGIC;
CE2 : in STD_ULOGIC;
CE3 : in STD_ULOGIC;
CLK0 : in STD_ULOGIC;
CLK1 : in STD_ULOGIC;
CLK2 : in STD_ULOGIC;
CLK3 : in STD_ULOGIC;
RST0 : in STD_ULOGIC;
RST1 : in STD_ULOGIC;
RST2 : in STD_ULOGIC;
RST3 : in STD_ULOGIC;
SROA0 : out STD_ULOGIC;
SROA1 : out STD_ULOGIC;
SROA2 : out STD_ULOGIC;
SROA3 : out STD_ULOGIC;
SROA4 : out STD_ULOGIC;
SROA5 : out STD_ULOGIC;
SROA6 : out STD_ULOGIC;
SROA7 : out STD_ULOGIC;
SROA8 : out STD_ULOGIC;
SROA9 : out STD_ULOGIC;
SROA10 : out STD_ULOGIC;
SROA11 : out STD_ULOGIC;
SROA12 : out STD_ULOGIC;
SROA13 : out STD_ULOGIC;
SROA14 : out STD_ULOGIC;
SROA15 : out STD_ULOGIC;
SROA16 : out STD_ULOGIC;
SROA17 : out STD_ULOGIC;
SROB0 : out STD_ULOGIC;
SROB1 : out STD_ULOGIC;
SROB2 : out STD_ULOGIC;
SROB3 : out STD_ULOGIC;
SROB4 : out STD_ULOGIC;
SROB5 : out STD_ULOGIC;
SROB6 : out STD_ULOGIC;
SROB7 : out STD_ULOGIC;
SROB8 : out STD_ULOGIC;
SROB9 : out STD_ULOGIC;
SROB10 : out STD_ULOGIC;
SROB11 : out STD_ULOGIC;
SROB12 : out STD_ULOGIC;
SROB13 : out STD_ULOGIC;
SROB14 : out STD_ULOGIC;
SROB15 : out STD_ULOGIC;
SROB16 : out STD_ULOGIC;
SROB17 : out STD_ULOGIC;
P0 : out STD_ULOGIC;
P1 : out STD_ULOGIC;
P2 : out STD_ULOGIC;
P3 : out STD_ULOGIC;
P4 : out STD_ULOGIC;
P5 : out STD_ULOGIC;
P6 : out STD_ULOGIC;
P7 : out STD_ULOGIC;
P8 : out STD_ULOGIC;
P9 : out STD_ULOGIC;
P10 : out STD_ULOGIC;
P11 : out STD_ULOGIC;
P12 : out STD_ULOGIC;
P13 : out STD_ULOGIC;
P14 : out STD_ULOGIC;
P15 : out STD_ULOGIC;
P16 : out STD_ULOGIC;
P17 : out STD_ULOGIC;
P18 : out STD_ULOGIC;
P19 : out STD_ULOGIC;
P20 : out STD_ULOGIC;
P21 : out STD_ULOGIC;
P22 : out STD_ULOGIC;
P23 : out STD_ULOGIC;
P24 : out STD_ULOGIC;
P25 : out STD_ULOGIC;
P26 : out STD_ULOGIC;
P27 : out STD_ULOGIC;
P28 : out STD_ULOGIC;
P29 : out STD_ULOGIC;
P30 : out STD_ULOGIC;
P31 : out STD_ULOGIC;
P32 : out STD_ULOGIC;
P33 : out STD_ULOGIC;
P34 : out STD_ULOGIC;
P35 : out STD_ULOGIC
);
attribute VITAL_LEVEL0 of MULT18X18 : entity is TRUE;
end MULT18X18;
--- Architecture
library IEEE;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture V of MULT18X18 is
attribute VITAL_LEVEL0 of V : architecture is TRUE;
-- Local signals used to propagate input wire delay
signal A_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal SRIA_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal SROA_reg : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal B_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal SRIB_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal SROB_reg : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal P_ipd : std_logic_vector(35 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
signal SIGNEDAB_ipd : std_logic := 'X';
signal CE0_ipd : std_logic := 'X';
signal CE1_ipd : std_logic := 'X';
signal CE2_ipd : std_logic := 'X';
signal CE3_ipd : std_logic := 'X';
signal CLK0_ipd : std_logic := 'X';
signal CLK1_ipd : std_logic := 'X';
signal CLK2_ipd : std_logic := 'X';
signal CLK3_ipd : std_logic := 'X';
signal RST0_ipd : std_logic := 'X';
signal RST1_ipd : std_logic := 'X';
signal RST2_ipd : std_logic := 'X';
signal RST3_ipd : std_logic := 'X';
signal A_reg : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal B_reg : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal A_p : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal B_p : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal A_gen : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal B_gen : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
signal P_i : std_logic_vector(35 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
signal P_o : std_logic_vector(35 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
signal P_ps : std_logic_vector(35 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
signal P_o1 : std_logic_vector(35 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
signal input_a_clk : std_logic := 'X';
signal input_a_ce : std_logic := 'X';
signal input_a_rst : std_logic := 'X';
signal input_b_clk : std_logic := 'X';
signal input_b_ce : std_logic := 'X';
signal input_b_rst : std_logic := 'X';
signal pipeline_clk : std_logic := 'X';
signal pipeline_ce : std_logic := 'X';
signal pipeline_rst : std_logic := 'X';
signal output_clk : std_logic := 'X';
signal output_ce : std_logic := 'X';
signal output_rst : std_logic := 'X';
signal signedab_0_clk : std_logic := 'X';
signal signedab_0_ce : std_logic := 'X';
signal signedab_0_rst : std_logic := 'X';
signal signedab_1_clk : std_logic := 'X';
signal signedab_1_ce : std_logic := 'X';
signal signedab_1_rst : std_logic := 'X';
signal signedab_0_reg : std_logic := 'X';
signal signedab_1_reg : std_logic := 'X';
signal signedab_p1 : std_logic := 'X';
signal signedab_p2 : std_logic := 'X';
signal SRN : std_logic;
signal input_a_rst_ogsr : std_logic := 'X';
signal input_b_rst_ogsr : std_logic := 'X';
signal pipeline_rst_ogsr : std_logic := 'X';
signal output_rst_ogsr : std_logic := 'X';
signal signedab_0_rst_ogsr : std_logic := 'X';
signal signedab_1_rst_ogsr : std_logic := 'X';
begin
global_reset : process (purnet, gsrnet)
begin
if (GSR = "DISABLED") then
SRN <= purnet;
else
SRN <= purnet AND gsrnet;
end if;
end process;
input_a_rst_ogsr <= input_a_rst or not SRN;
input_b_rst_ogsr <= input_b_rst or not SRN;
pipeline_rst_ogsr <= pipeline_rst or not SRN;
output_rst_ogsr <= output_rst or not SRN;
signedab_0_rst_ogsr <= signedab_0_rst or not SRN;
signedab_1_rst_ogsr <= signedab_1_rst or not SRN;
A_ipd <= (A17 & A16 & A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0);
B_ipd <= (B17 & B16 & B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0);
SRIA_ipd <= (SRIA17 & SRIA16 & SRIA15 & SRIA14 & SRIA13 & SRIA12 & SRIA11 & SRIA10 & SRIA9 & SRIA8 & SRIA7 & SRIA6 & SRIA5 & SRIA4 & SRIA3 & SRIA2 & SRIA1 & SRIA0);
SRIB_ipd <= (SRIB17 & SRIB16 & SRIB15 & SRIB14 & SRIB13 & SRIB12 & SRIB11 & SRIB10 & SRIB9 & SRIB8 & SRIB7 & SRIB6 & SRIB5 & SRIB4 & SRIB3 & SRIB2 & SRIB1 & SRIB0);
SIGNEDAB_ipd <= SIGNEDAB;
CE0_ipd <= CE0;
CE1_ipd <= CE1;
CE2_ipd <= CE2;
CE3_ipd <= CE3;
CLK0_ipd <= CLK0;
CLK1_ipd <= CLK1;
CLK2_ipd <= CLK2;
CLK3_ipd <= CLK3;
RST0_ipd <= RST0;
RST1_ipd <= RST1;
RST2_ipd <= RST2;
RST3_ipd <= RST3;
SROA0 <= SROA_reg(0);
SROA1 <= SROA_reg(1);
SROA2 <= SROA_reg(2);
SROA3 <= SROA_reg(3);
SROA4 <= SROA_reg(4);
SROA5 <= SROA_reg(5);
SROA6 <= SROA_reg(6);
SROA7 <= SROA_reg(7);
SROA8 <= SROA_reg(8);
SROA9 <= SROA_reg(9);
SROA10 <= SROA_reg(10);
SROA11 <= SROA_reg(11);
SROA12 <= SROA_reg(12);
SROA13 <= SROA_reg(13);
SROA14 <= SROA_reg(14);
SROA15 <= SROA_reg(15);
SROA16 <= SROA_reg(16);
SROA17 <= SROA_reg(17);
SROB0 <= SROB_reg(0);
SROB1 <= SROB_reg(1);
SROB2 <= SROB_reg(2);
SROB3 <= SROB_reg(3);
SROB4 <= SROB_reg(4);
SROB5 <= SROB_reg(5);
SROB6 <= SROB_reg(6);
SROB7 <= SROB_reg(7);
SROB8 <= SROB_reg(8);
SROB9 <= SROB_reg(9);
SROB10 <= SROB_reg(10);
SROB11 <= SROB_reg(11);
SROB12 <= SROB_reg(12);
SROB13 <= SROB_reg(13);
SROB14 <= SROB_reg(14);
SROB15 <= SROB_reg(15);
SROB16 <= SROB_reg(16);
SROB17 <= SROB_reg(17);
P0 <= P_ipd(0);
P1 <= P_ipd(1);
P2 <= P_ipd(2);
P3 <= P_ipd(3);
P4 <= P_ipd(4);
P5 <= P_ipd(5);
P6 <= P_ipd(6);
P7 <= P_ipd(7);
P8 <= P_ipd(8);
P9 <= P_ipd(9);
P10 <= P_ipd(10);
P11 <= P_ipd(11);
P12 <= P_ipd(12);
P13 <= P_ipd(13);
P14 <= P_ipd(14);
P15 <= P_ipd(15);
P16 <= P_ipd(16);
P17 <= P_ipd(17);
P18 <= P_ipd(18);
P19 <= P_ipd(19);
P20 <= P_ipd(20);
P21 <= P_ipd(21);
P22 <= P_ipd(22);
P23 <= P_ipd(23);
P24 <= P_ipd(24);
P25 <= P_ipd(25);
P26 <= P_ipd(26);
P27 <= P_ipd(27);
P28 <= P_ipd(28);
P29 <= P_ipd(29);
P30 <= P_ipd(30);
P31 <= P_ipd(31);
P32 <= P_ipd(32);
P33 <= P_ipd(33);
P34 <= P_ipd(34);
P35 <= P_ipd(35);
Input_A_Clock : process(CLK0_ipd, CLK1_ipd, CLK2_ipd, CLK3_ipd)
begin
if (REG_INPUTA_CLK = "CLK0") then
input_a_clk <= CLK0_ipd;
elsif (REG_INPUTA_CLK = "CLK1") then
input_a_clk <= CLK1_ipd;
elsif (REG_INPUTA_CLK = "CLK2") then
input_a_clk <= CLK2_ipd;
elsif (REG_INPUTA_CLK = "CLK3") then
input_a_clk <= CLK3_ipd;
end if;
end process;
Input_A_ClockEnable : process(CE0_ipd, CE1_ipd, CE2_ipd, CE3_ipd)
begin
if (REG_INPUTA_CE = "CE0") then
input_a_ce <= CE0_ipd;
elsif (REG_INPUTA_CE = "CE1") then
input_a_ce <= CE1_ipd;
elsif (REG_INPUTA_CE = "CE2") then
input_a_ce <= CE2_ipd;
elsif (REG_INPUTA_CE = "CE3") then
input_a_ce <= CE3_ipd;
end if;
end process;
Input_A_Reset : process(RST0_ipd, RST1_ipd, RST2_ipd, RST3_ipd)
begin
if (REG_INPUTA_RST = "RST0") then
input_a_rst <= RST0_ipd;
elsif (REG_INPUTA_RST = "RST1") then
input_a_rst <= RST1_ipd;
elsif (REG_INPUTA_RST = "RST2") then
input_a_rst <= RST2_ipd;
elsif (REG_INPUTA_RST = "RST3") then
input_a_rst <= RST3_ipd;
end if;
end process;
Register_A_Input : process(input_a_clk, input_a_rst_ogsr, input_a_ce, A_ipd, a_gen)
begin
if (input_a_rst_ogsr = '1') then
A_reg <= (others => '0');
SROA_reg <= (others => '0');
elsif (rising_edge(input_a_clk)) then
if (input_a_ce = '1') then
A_reg <= A_ipd;
SROA_reg <= a_gen;
end if;
end if;
end process;
Select_A_OR_A_reg : process (A_ipd, A_reg)
begin
if (REG_INPUTA_CLK = "NONE") then
A_p <= A_ipd;
else
A_p <= A_reg;
end if;
end process;
Select_A_p_OR_SRIA_ipd : process(A_p, SRIA_ipd)
begin
if (SHIFT_IN_A = "TRUE") then
a_gen <= SRIA_ipd;
elsif (SHIFT_IN_A = "FALSE") then
a_gen <= A_p;
end if;
end process;
Input_B_Clock : process(CLK0_ipd, CLK1_ipd, CLK2_ipd, CLK3_ipd)
begin
if (REG_INPUTB_CLK = "CLK0") then
input_b_clk <= CLK0_ipd;
elsif (REG_INPUTB_CLK = "CLK1") then
input_b_clk <= CLK1_ipd;
elsif (REG_INPUTB_CLK = "CLK2") then
input_b_clk <= CLK2_ipd;
elsif (REG_INPUTB_CLK = "CLK3") then
input_b_clk <= CLK3_ipd;
end if;
end process;
Input_B_ClockEnable : process(CE0_ipd, CE1_ipd, CE2_ipd, CE3_ipd)
begin
if (REG_INPUTB_CE = "CE0") then
input_b_ce <= CE0_ipd;
elsif (REG_INPUTB_CE = "CE1") then
input_b_ce <= CE1_ipd;
elsif (REG_INPUTB_CE = "CE2") then
input_b_ce <= CE2_ipd;
elsif (REG_INPUTB_CE = "CE3") then
input_b_ce <= CE3_ipd;
end if;
end process;
Input_B_Reset : process(RST0_ipd, RST1_ipd, RST2_ipd, RST3_ipd)
begin
if (REG_INPUTB_RST = "RST0") then
input_b_rst <= RST0_ipd;
elsif (REG_INPUTB_RST = "RST1") then
input_b_rst <= RST1_ipd;
elsif (REG_INPUTB_RST = "RST2") then
input_b_rst <= RST2_ipd;
elsif (REG_INPUTB_RST = "RST3") then
input_b_rst <= RST3_ipd;
end if;
end process;
Register_B_Input : process(input_b_clk, input_b_rst_ogsr, input_b_ce, B_ipd, b_gen)
begin
if (input_b_rst_ogsr = '1') then
B_reg <= (others => '0');
SROB_reg <= (others => '0');
elsif (rising_edge(input_b_clk)) then
if (input_b_ce = '1') then
B_reg <= B_ipd;
SROB_reg <= b_gen;
end if;
end if;
end process;
Select_B_OR_B_reg : process (B_ipd, B_reg)
begin
if (REG_INPUTB_CLK = "NONE") then
B_p <= B_ipd;
else
B_p <= B_reg;
end if;
end process;
Select_B_p_OR_SRIB_ipd : process(B_p, SRIB_ipd)
begin
if (SHIFT_IN_B = "TRUE") then
b_gen <= SRIB_ipd;
elsif (SHIFT_IN_B = "FALSE") then
b_gen <= B_p;
end if;
end process;
SIGNEDAB_0_Clock : process(CLK0_ipd, CLK1_ipd, CLK2_ipd, CLK3_ipd)
begin
if (REG_SIGNEDAB_0_CLK = "CLK0") then
signedab_0_clk <= CLK0_ipd;
elsif (REG_SIGNEDAB_0_CLK = "CLK1") then
signedab_0_clk <= CLK1_ipd;
elsif (REG_SIGNEDAB_0_CLK = "CLK2") then
signedab_0_clk <= CLK2_ipd;
elsif (REG_SIGNEDAB_0_CLK = "CLK3") then
signedab_0_clk <= CLK3_ipd;
end if;
end process;
SIGNEDAB_0_ClockEnable : process(CE0_ipd, CE1_ipd, CE2_ipd, CE3_ipd)
begin
if (REG_SIGNEDAB_0_CE = "CE0") then
signedab_0_ce <= CE0_ipd;
elsif (REG_SIGNEDAB_0_CE = "CE1") then
signedab_0_ce <= CE1_ipd;
elsif (REG_SIGNEDAB_0_CE = "CE2") then
signedab_0_ce <= CE2_ipd;
elsif (REG_SIGNEDAB_0_CE = "CE3") then
signedab_0_ce <= CE3_ipd;
end if;
end process;
SIGNEDAB_0_Reset : process(RST0_ipd, RST1_ipd, RST2_ipd, RST3_ipd)
begin
if (REG_SIGNEDAB_0_RST = "RST0") then
signedab_0_rst <= RST0_ipd;
elsif (REG_SIGNEDAB_0_RST = "RST1") then
signedab_0_rst <= RST1_ipd;
elsif (REG_SIGNEDAB_0_RST = "RST2") then
signedab_0_rst <= RST2_ipd;
elsif (REG_SIGNEDAB_0_RST = "RST3") then
signedab_0_rst <= RST3_ipd;
end if;
end process;
Register_0_SIGNEDAB : process(signedab_0_clk, signedab_0_rst_ogsr, signedab_0_ce, SIGNEDAB_ipd)
begin
if (signedab_0_rst_ogsr = '1') then
signedab_0_reg <= '0';
elsif (rising_edge(signedab_0_clk)) then
if (signedab_0_ce = '1') then
signedab_0_reg <= SIGNEDAB_ipd;
end if;
end if;
end process;
Select_SIGNEDAB_ipd_OR_SIGNEDAB_0_reg : process (SIGNEDAB_ipd, signedab_0_reg)
begin
if (REG_SIGNEDAB_0_CLK = "NONE") then
signedab_p1 <= SIGNEDAB_ipd;
else
signedab_p1 <= signedab_0_reg;
end if;
end process;
SIGNEDAB_1_Clock : process(CLK0_ipd, CLK1_ipd, CLK2_ipd, CLK3_ipd)
begin
if (REG_SIGNEDAB_1_CLK = "CLK0") then
signedab_1_clk <= CLK0_ipd;
elsif (REG_SIGNEDAB_1_CLK = "CLK1") then
signedab_1_clk <= CLK1_ipd;
elsif (REG_SIGNEDAB_1_CLK = "CLK2") then
signedab_1_clk <= CLK2_ipd;
elsif (REG_SIGNEDAB_1_CLK = "CLK3") then
signedab_1_clk <= CLK3_ipd;
end if;
end process;
SIGNEDAB_1_ClockEnable : process(CE0_ipd, CE1_ipd, CE2_ipd, CE3_ipd)
begin
if (REG_SIGNEDAB_1_CE = "CE0") then
signedab_1_ce <= CE0_ipd;
elsif (REG_SIGNEDAB_1_CE = "CE1") then
signedab_1_ce <= CE1_ipd;
elsif (REG_SIGNEDAB_1_CE = "CE2") then
signedab_1_ce <= CE2_ipd;
elsif (REG_SIGNEDAB_1_CE = "CE3") then
signedab_1_ce <= CE3_ipd;
end if;
end process;
SIGNEDAB_1_Reset : process(RST0_ipd, RST1_ipd, RST2_ipd, RST3_ipd)
begin
if (REG_SIGNEDAB_1_RST = "RST0") then
signedab_1_rst <= RST0_ipd;
elsif (REG_SIGNEDAB_1_RST = "RST1") then
signedab_1_rst <= RST1_ipd;
elsif (REG_SIGNEDAB_0_RST = "RST2") then
signedab_1_rst <= RST2_ipd;
elsif (REG_SIGNEDAB_1_RST = "RST3") then
signedab_1_rst <= RST3_ipd;
end if;
end process;
Register_1_SIGNEDAB : process(signedab_1_clk, signedab_1_rst_ogsr, signedab_1_ce, signedab_p1)
begin
if (signedab_0_rst_ogsr = '1') then
signedab_1_reg <= '0';
elsif (rising_edge(signedab_1_clk)) then
if (signedab_1_ce = '1') then
signedab_1_reg <= signedab_p1;
end if;
end if;
end process;
Select_SIGNEDAB_ipd_OR_SIGNEDAB_1_reg : process (signedab_p1, signedab_1_reg)
begin
if (REG_SIGNEDAB_1_CLK = "NONE") then
signedab_p2 <= signedab_p1;
else
signedab_p2 <= signedab_1_reg;
end if;
end process;
VITALMultBehavior : process(A_gen, B_gen)
variable O_zd, OT1_zd, OT2_zd : std_logic_vector( 35 downto 0);
variable IA,IBL,IBU : integer ;
variable sign : std_logic := '0';
variable A_i : std_logic_vector(17 downto 0);
variable B_i : std_logic_vector(17 downto 0);
begin -- process
if ((A_gen = "000000000000000000") or (B_gen = "000000000000000000")) then
O_zd := (others => '0');
elsif (VECX(A_gen) or VECX(B_gen) ) then
O_zd := (others => 'X');
else
if (signedab_p2 = '1') then
if (A_gen(17) = '1' ) then
A_i := TSCOMP(A_gen);
else
A_i := A_gen;
end if;
if (B_gen(17) = '1') then
B_i := TSCOMP(B_gen);
else
B_i := B_gen;
end if;
IA := VEC2INT(A_i);
IBU := VEC2INT(B_i (17 downto 9));
IBL := VEC2INT(B_i (8 downto 0));
OT1_zd := INT2VEC((IA * IBU), 36);
for idex in 0 to 8 loop
OT1_zd(35 downto 0) := OT1_zd(34 downto 0) & '0';
end loop;
OT2_zd := INT2VEC((IA * IBL), 36);
O_zd := ADDVECT(OT1_zd,OT2_zd);
sign := A_gen(17) xor B_gen(17);
if (sign = '1' ) then
O_zd := TSCOMP(O_zd);
end if;
else
A_i := A_gen;
B_i := B_gen;
IA := VEC2INT(A_i);
IBU := VEC2INT(B_i (17 downto 9));
IBL := VEC2INT(B_i (8 downto 0));
OT1_zd := INT2VEC((IA * IBU), 36);
for idex in 0 to 8 loop
OT1_zd(35 downto 0) := OT1_zd(34 downto 0) & '0';
end loop;
OT2_zd := INT2VEC((IA * IBL), 36);
O_zd := ADDVECT(OT1_zd,OT2_zd);
end if;
end if;
p_i <= O_ZD;
end process;
PipeLine_Clock : process(CLK0_ipd, CLK1_ipd, CLK2_ipd, CLK3_ipd)
begin
if (REG_PIPELINE_CLK = "CLK0") then
pipeline_clk <= CLK0_ipd;
elsif (REG_PIPELINE_CLK = "CLK1") then
pipeline_clk <= CLK1_ipd;
elsif (REG_PIPELINE_CLK = "CLK2") then
pipeline_clk <= CLK2_ipd;
elsif (REG_PIPELINE_CLK = "CLK3") then
pipeline_clk <= CLK3_ipd;
end if;
end process;
PipeLine_ClockEnable : process(CE0_ipd, CE1_ipd, CE2_ipd, CE3_ipd)
begin
if (REG_PIPELINE_CE = "CE0") then
pipeline_ce <= CE0_ipd;
elsif (REG_PIPELINE_CE = "CE1") then
pipeline_ce <= CE1_ipd;
elsif (REG_PIPELINE_CE = "CE2") then
pipeline_ce <= CE2_ipd;
elsif (REG_PIPELINE_CE = "CE3") then
pipeline_ce <= CE3_ipd;
end if;
end process;
PipeLine_Reset : process(RST0_ipd, RST1_ipd, RST2_ipd, RST3_ipd)
begin
if (REG_PIPELINE_RST = "RST0") then
pipeline_rst <= RST0_ipd;
elsif (REG_PIPELINE_RST = "RST1") then
pipeline_rst <= RST1_ipd;
elsif (REG_PIPELINE_RST = "RST2") then
pipeline_rst <= RST2_ipd;
elsif (REG_PIPELINE_RST = "RST3") then
pipeline_rst <= RST3_ipd;
end if;
end process;
Pipeline_p_i : process(pipeline_clk, pipeline_rst_ogsr, pipeline_ce, p_i)
begin
if (pipeline_rst_ogsr = '1') then
p_o <= (others => '0');
elsif (rising_edge(pipeline_clk)) then
if (pipeline_ce = '1') then
p_o <= p_i;
end if;
end if;
end process;
Select_NOPIPELINE_OR_PIPELINE : process (p_i, p_o)
begin
if (REG_PIPELINE_CLK = "NONE") then
p_ps <= p_i;
else
p_ps <= p_o;
end if;
end process;
Output_Clock : process(CLK0_ipd, CLK1_ipd, CLK2_ipd, CLK3_ipd)
begin
if (REG_OUTPUT_CLK = "CLK0") then
output_clk <= CLK0_ipd;
elsif (REG_OUTPUT_CLK = "CLK1") then
output_clk <= CLK1_ipd;
elsif (REG_OUTPUT_CLK = "CLK2") then
output_clk <= CLK2_ipd;
elsif (REG_OUTPUT_CLK = "CLK3") then
output_clk <= CLK3_ipd;
end if;
end process;
Output_ClockEnable : process(CE0_ipd, CE1_ipd, CE2_ipd, CE3_ipd)
begin
if (REG_OUTPUT_CE = "CE0") then
output_ce <= CE0_ipd;
elsif (REG_OUTPUT_CE = "CE1") then
output_ce <= CE1_ipd;
elsif (REG_OUTPUT_CE = "CE2") then
output_ce <= CE2_ipd;
elsif (REG_OUTPUT_CE = "CE3") then
output_ce <= CE3_ipd;
end if;
end process;
Output_Reset : process(RST0_ipd, RST1_ipd, RST2_ipd, RST3_ipd)
begin
if (REG_OUTPUT_RST = "RST0") then
output_rst <= RST0_ipd;
elsif (REG_OUTPUT_RST = "RST1") then
output_rst <= RST1_ipd;
elsif (REG_OUTPUT_RST = "RST2") then
output_rst <= RST2_ipd;
elsif (REG_OUTPUT_RST = "RST3") then
output_rst <= RST3_ipd;
end if;
end process;
Output_Register : process(output_clk, output_rst_ogsr, output_ce, p_ps)
begin
if (output_rst_ogsr = '1') then
p_o1 <= (others => '0');
elsif (rising_edge(output_clk)) then
if (output_ce = '1') then
p_o1 <= p_ps;
end if;
end if;
end process;
Select_OUTREG_OR_NOREG : process (p_ps, p_o1)
begin
if (REG_OUTPUT_CLK = "NONE") then
P_ipd <= p_ps;
else
P_ipd <= p_o1;
end if;
end process;
end V;
|
gpl-2.0
|
1307f19cfeaf55718c37a3e6916fee41
| 0.520749 | 3.503367 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/allmul.vhd
| 1 | 3,192 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: allmul
-- File: allmul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multiplier components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package allmul is
component mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component gen_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component axcel_mul_33x33_signed
generic (
pipe: Integer := 0);
port (
a: in Std_Logic_Vector(32 downto 0);
b: in Std_Logic_Vector(32 downto 0);
en: in Std_Logic;
clk: in Std_Logic;
p: out Std_Logic_Vector(65 downto 0));
end component;
end;
|
gpl-2.0
|
a23fc738e3f4d0a620432122e0e363aa
| 0.54292 | 4.113402 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/memifsim.vhd
| 1 | 12,406 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr3ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_a : out std_logic_vector(13 downto 0);
mem_ba : out std_logic_vector(2 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(3 downto 0);
mem_ras_n : out std_logic_vector(0 downto 0);
mem_cas_n : out std_logic_vector(0 downto 0);
mem_we_n : out std_logic_vector(0 downto 0);
mem_reset_n : out std_logic;
mem_dq : inout std_logic_vector(31 downto 0);
mem_dqs : inout std_logic_vector(3 downto 0);
mem_dqs_n : inout std_logic_vector(3 downto 0);
mem_odt : out std_logic_vector(0 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(127 downto 0);
avl_wdata : in std_logic_vector(127 downto 0);
avl_be : in std_logic_vector(15 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of ddr3ctrl1 is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_reset_n <= '0';
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 3.3 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 128;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_ca : out std_logic_vector(9 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(1 downto 0);
mem_dq : inout std_logic_vector(15 downto 0);
mem_dqs : inout std_logic_vector(1 downto 0);
mem_dqs_n : inout std_logic_vector(1 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(63 downto 0);
avl_wdata : in std_logic_vector(63 downto 0);
avl_be : in std_logic_vector(7 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of lpddr2ctrl1 is
signal lafi_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_reset_n <= '0';
afi_reset_export_n <= '0';
mem_ca <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
avl_ready <= '1';
avl_rdata_valid <= '1';
avl_rdata <= (others => '0');
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
variable vclk,vhclk: std_logic := '0';
begin
lafi_clk <= vclk;
afi_half_clk <= vhclk;
wait for 4 ns;
vclk := not vclk;
if vclk='0' then vhclk:=not vhclk; end if;
end process;
rstproc: process
begin
afi_reset_n <= '0';
for x in 1 to 10 loop
wait until rising_edge(lafi_clk);
end loop;
afi_reset_n <= '1';
wait;
end process;
end;
|
gpl-2.0
|
c1fd92e1868a9adf465788f5bdd0b80c
| 0.509189 | 3.331364 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/eclipsee/simprims/eclipse.vhd
| 5 | 3,888 |
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
end eclipse_components;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity eclipse_sim_ram is
generic (abits : integer := 8; dbits : integer := 16);
port (WA, RA : in std_logic_vector (abits-1 downto 0);
WD : in std_logic_vector (dbits-1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (dbits-1 downto 0) );
end;
architecture arch of eclipse_sim_ram is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
begin
rp : process(rclk, wclk, re, ra, asyncrd)
variable rfd : dregtype;
begin
if rising_edge(wclk) then
if we = '1' then rfd(conv_integer(wa)) := WD; end if;
end if;
if (re = '1') and (ASYNCRD = '1') then
RD <= rfd(conv_integer(ra));
end if;
if rising_edge(rclk) and (re = '1') and (ASYNCRD = '0') then
RD <= rfd(conv_integer(ra));
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end RAM128X18_25um;
architecture arch of RAM128X18_25um is
begin
x : entity work.eclipse_sim_ram generic map (7, 18)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end RAM256X9_25um;
architecture arch of RAM256X9_25um is
begin
x : entity work.eclipse_sim_ram generic map (8, 9)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM512X4_25um is
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end RAM512X4_25um;
architecture arch of RAM512X4_25um is
begin
x : entity work.eclipse_sim_ram generic map (9, 4)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end RAM1024X2_25um;
architecture arch of RAM1024X2_25um is
begin
x : entity work.eclipse_sim_ram generic map (10, 2)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
|
gpl-2.0
|
34a181780ab96d66ea5ec656b1eaa8b4
| 0.628858 | 3.009288 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/dsu3_mb.vhd
| 1 | 2,679 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Aeroflex Gaisler AB
-- Description: Combined LEON3 debug support with AHB trace unit
-- connected on separate bus.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3_mb is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3_mb is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen, bwidth, ahbpf)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, tahbsi, dbgi, dbgo, dsui, dsuo, vcc
);
end;
|
gpl-2.0
|
3a29337a301621ecb005c2056bc5007c
| 0.590146 | 3.773239 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/inferred/mul_inferred.vhd
| 1 | 4,283 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity gen_mult_pipe is
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end ;
architecture simple of gen_mult_pipe is
subtype resw is std_logic_vector(A_width+B_width-1 downto 0);
type pipet is array (num_stages-1 downto 1) of resw;
signal p_i : pipet;
signal prod : resw;
begin
comb : process(A, B, TC)
begin
-- pragma translate_off
if notx(A) and notx(B) and notx(tc) then
-- pragma translate_on
if TC = '1' then
prod <= signed(A) * signed(B);
else
prod <= unsigned(A) * unsigned(B);
end if;
-- pragma translate_off
else
prod <= (others => 'X');
end if;
-- pragma translate_on
end process;
w2 : if num_stages = 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i(1) <= prod;
end if;
end if;
end process;
end generate;
w3 : if num_stages > 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i <= p_i(num_stages-2 downto 1) & prod;
end if;
end if;
end process;
end generate;
product <= p_i(num_stages-1);
end;
|
gpl-2.0
|
90cfad967885b46216e1ef94a37e5cfe
| 0.570628 | 3.566195 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmutlbcam.vhd
| 1 | 9,953 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlbcam
-- File: mmutlbcam.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlbcam is
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end mmutlbcam;
architecture rtl of mmutlbcam is
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
type tlbcam_rtype is record
btag : tlbcam_reg;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tlbcam_rtype := (btag => tlbcam_reg_none);
signal r,c : tlbcam_rtype;
begin
p0: process (rst, r, tlbcami)
variable v : tlbcam_rtype;
variable hm, hf : std_logic;
variable h_i1, h_i2, h_i3, h_c : std_logic;
variable h_l2, h_l3 : std_logic;
variable h_su_cnt : std_logic;
variable blvl : std_logic_vector(1 downto 0);
variable bet : std_logic_vector(1 downto 0);
variable bsu : std_logic;
variable blvl_decode : std_logic_vector(3 downto 0);
variable bet_decode : std_logic_vector(3 downto 0);
variable ref, modified : std_logic;
variable tlbcamo_pteout : std_logic_vector(31 downto 0);
variable tlbcamo_LVL : std_logic_vector(1 downto 0);
variable tlbcamo_NEEDSYNC : std_logic;
variable tlbcamo_WBNEEDSYNC : std_logic;
variable vaddr_r : std_logic_vector(31 downto 12);
variable vaddr_i : std_logic_vector(31 downto 12);
variable pagesize : integer range 0 to 3;
begin
v := r;
--#init
h_i1 := '0'; h_i2 := '0'; h_i3 := '0'; h_c := '0';
hm := '0'; pagesize := 0;
hf := r.btag.VALID;
blvl := r.btag.LVL;
bet := r.btag.ET;
bsu := r.btag.SU;
bet_decode := decode(bet);
blvl_decode := decode(blvl);
ref := r.btag.R;
modified := r.btag.M;
tlbcamo_pteout := (others => '0');
tlbcamo_lvl := (others => '0');
vaddr_r := r.btag.I1 & r.btag.I2 & r.btag.I3;
vaddr_i := tlbcami.tagin.I1 & tlbcami.tagin.I2 & tlbcami.tagin.I3;
-- prepare tag comparision
pagesize := MMU_getpagesize(mmupgsz,tlbcami.mmctrl);
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
if (vaddr_r(P8K_VA_I1_U downto P8K_VA_I1_D) = vaddr_i(P8K_VA_I1_U downto P8K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P8K_VA_I2_U downto P8K_VA_I2_D) = vaddr_i(P8K_VA_I2_U downto P8K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P8K_VA_I3_U downto P8K_VA_I3_D) = vaddr_i(P8K_VA_I3_U downto P8K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
if (vaddr_r(P16K_VA_I1_U downto P16K_VA_I1_D) = vaddr_i(P16K_VA_I1_U downto P16K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P16K_VA_I2_U downto P16K_VA_I2_D) = vaddr_i(P16K_VA_I2_U downto P16K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P16K_VA_I3_U downto P16K_VA_I3_D) = vaddr_i(P16K_VA_I3_U downto P16K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
if (vaddr_r(P32K_VA_I1_U downto P32K_VA_I1_D) = vaddr_i(P32K_VA_I1_U downto P32K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P32K_VA_I2_U downto P32K_VA_I2_D) = vaddr_i(P32K_VA_I2_U downto P32K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P32K_VA_I3_U downto P32K_VA_I3_D) = vaddr_i(P32K_VA_I3_U downto P32K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when others => -- standard 4k tag comparision [ 8 6 6 ]
if (r.btag.I1 = tlbcami.tagin.I1) then h_i1 := '1'; else h_i1 := '0'; end if;
if (r.btag.I2 = tlbcami.tagin.I2) then h_i2 := '1'; else h_i2 := '0'; end if;
if (r.btag.I3 = tlbcami.tagin.I3) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
end case;
-- #level 2 hit (segment)
h_l2 := h_i1 and h_i2 ;
-- #level 3 hit (page)
h_l3 := h_i1 and h_i2 and h_i3;
-- # context + su
h_su_cnt := h_c or bsu;
--# translation (match) op
case blvl is
when LVL_PAGE => hm := h_l3 and h_c and r.btag.VALID;
when LVL_SEGMENT => hm := h_l2 and h_c and r.btag.VALID;
when LVL_REGION => hm := h_i1 and h_c and r.btag.VALID;
when LVL_CTX => hm := h_c and r.btag.VALID;
when others => hm := 'X';
end case;
--# translation: update ref/mod bit
tlbcamo_NEEDSYNC := '0';
if (tlbcami.trans_op and hm ) = '1' then
v.btag.R := '1';
v.btag.M := r.btag.M or tlbcami.tagin.M;
tlbcamo_NEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
tlbcamo_WBNEEDSYNC := '0';
if ( hm ) = '1' then
tlbcamo_WBNEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
--# flush operation
-- tlbcam only stores PTEs, tlb does not store PTDs
case tlbcami.tagin.TYP is
when FPTY_PAGE => -- page
hf := hf and h_su_cnt and h_l3 and (blvl_decode(0)); -- only level 3 (page)
when FPTY_SEGMENT => -- segment
hf := hf and h_su_cnt and h_l2 and (blvl_decode(0) or blvl_decode(1)); -- only level 2+3 (segment,page)
when FPTY_REGION => -- region
hf := hf and h_su_cnt and h_i1 and (not blvl_decode(3)); -- only level 1+2+3 (region,segment,page)
when FPTY_CTX => -- context
hf := hf and (h_c and (not bsu));
when FPTY_N => -- entire
when others =>
hf := '0';
end case;
--# flush: invalidate on flush hit
--if (tlbcami.flush_op and hf ) = '1' then
if (tlbcami.flush_op ) = '1' then
v.btag.VALID := '0';
end if;
--# write op
if ( tlbcami.write_op = '1' ) then
v.btag := tlbcami.tagwrite;
end if;
--# reset
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (tlbcami.mmuen = '0') then
v.btag.VALID := RRES.btag.VALID;
end if;
tlbcamo_pteout(PTE_PPN_U downto PTE_PPN_D) := r.btag.PPN;
tlbcamo_pteout(PTE_C) := r.btag.C;
tlbcamo_pteout(PTE_M) := r.btag.M;
tlbcamo_pteout(PTE_R) := r.btag.R;
tlbcamo_pteout(PTE_ACC_U downto PTE_ACC_D) := r.btag.ACC;
tlbcamo_pteout(PT_ET_U downto PT_ET_D) := r.btag.ET;
tlbcamo_LVL(1 downto 0) := r.btag.LVL;
--# drive signals
tlbcamo.pteout <= tlbcamo_pteout;
tlbcamo.LVL <= tlbcamo_LVL;
--tlbcamo.hit <= (tlbcami.trans_op and hm) or (tlbcami.flush_op and hf);
tlbcamo.hit <= (hm) or (tlbcami.flush_op and hf);
tlbcamo.ctx <= r.btag.CTX; -- for diagnostic only
tlbcamo.valid <= r.btag.VALID; -- for diagnostic only
tlbcamo.vaddr <= r.btag.I1 & r.btag.I2 & r.btag.I3 & "000000000000"; -- for diagnostic only
tlbcamo.NEEDSYNC <= tlbcamo_NEEDSYNC;
tlbcamo.WBNEEDSYNC <= tlbcamo_WBNEEDSYNC;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
end rtl;
|
gpl-2.0
|
e9214d24edc2ba4acb707ad5583d72fa
| 0.561941 | 2.998795 | false | false | false | false |
aortiz49/MIPS-Processor
|
Testbenches/mux32_tb.vhd
| 1 | 1,071 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux32_tb is
end mux32_tb;
architecture TB of mux32_tb is
component mux32
port(
in0 : in std_logic_vector(31 downto 0);
in1 : in std_logic_vector(31 downto 0);
sel : in std_logic;
output : out std_logic_vector(31 downto 0));
end component;
signal in0 : std_logic_vector(31 downto 0);
signal in1 : std_logic_vector(31 downto 0);
signal sel : std_logic := '1';
signal output : std_logic_vector(31 downto 0);
begin -- TB
UUT: entity work.mux32
port map(in0 => in0,
in1 => in1,
sel => sel,
output => output);
process
begin
for i in 2048 to 4096 loop --random values. since 2^32-1 values is way too much
in1 <= std_logic_vector(to_unsigned(i,32));
for j in 0 to 255 loop
in0 <= std_logic_vector(to_unsigned(j,32));
sel<= not sel;
wait for 10 ns;
end loop; -- j
end loop; -- i
wait;
report "SIMULATION FINISHED!";
wait;
end process;
end TB;
|
mit
|
54599a566cb63b011569c83efffd8687
| 0.600373 | 2.825858 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/clkpad.vhd
| 1 | 4,598 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0; filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1'; lock : out std_ulogic);
end;
architecture rtl of clkpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= to_X01(pad); lock <= '1';
end generate;
xcv2 : if (is_unisim(tech) = 1) generate
u0 : unisim_clkpad generic map (level, voltage, arch, hf, tech) port map (pad, o, rstn, lock);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_clkpad generic map (level, voltage, arch) port map (pad, o); lock <= '1';
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
igl2 : if (tech = igloo2) generate
u0 : igloo2_clkpad port map (pad, o); lock <= '1';
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
fus : if (tech = actfus) generate
u0 : fusion_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
um : if (tech = umc) generate
u0 : umc_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o); lock <= '1';
end generate;
saed : if (tech = saed32) generate
u0 : saed32_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
rhs : if (tech = rhs65) generate
u0 : rhs65_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
dar : if (tech = dare) generate
u0 : dare_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad port map (pad, o); lock <= '1';
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_inpad port map (pad, o); lock <= '1';
end generate;
ut13 : if (tech = ut130) generate
u0 : ut130hbd_inpad generic map (level, voltage, filter)
port map (pad, o); lock <= '1';
end generate;
ut9 : if (tech = ut90) generate
u0 : ut90nhbd_inpad port map (pad, o); lock <= '1';
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_inpad port map (pad, o); lock <= '1';
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
end;
|
gpl-2.0
|
09aaa447441246f3aa37b9913c449119
| 0.617877 | 3.457143 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/and00.vhd
| 1 | 1,322 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity and00 is
port(
clka: in std_logic ;
codopa: in std_logic_vector ( 3 downto 0 );
portAa: in std_logic_vector ( 7 downto 0 );
portBa: in std_logic_vector ( 7 downto 0 );
inFlaga: in std_logic ;
outa: out std_logic_vector ( 7 downto 0 );
outFlaga: out std_logic );
end;
architecture and0 of and00 is
begin
pand: process(codopa, portAa, portBa)
begin
if(codopa = "0001") then
outa <= portAa and portBa;
outFlaga <= '1';
else
outa <= (others => 'Z');
outFlaga <= 'Z';
end if;
end process pand;
-- pand: process(clka, codopa, inFlaga)
-- --variable auxa: bit:='0';
-- begin
-- if (clka'event and clka = '1') then
-- if (codopa = "0000") then
-- if (inFlaga = '1') then
-- --if (auxa = '0') then
-- --auxa:= '1';
-- outa <= portAa and portBa;
-- outFlaga <= '1';
-- --end if;
-- else
-- outFlaga <= '0';
-- end if;
-- else
-- outa <= (others => 'Z');
-- outFlaga <= 'Z';
-- --auxa:='0';
-- end if;
-- end if;
-- end process pand;
end and0;
|
apache-2.0
|
f43f27644b8035d5055304ae310325d2
| 0.492436 | 2.861472 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-vc707/ddr_dummy.vhd
| 8 | 5,346 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2012 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Package: ddr_dummy
-- File:ddr_dummy.vhd
-- Author:Fredrik Ringhage - Gaisler Research
-- Description: Xilinx MIG wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
library work;
entity ddr_dummy is
generic (
USE_MIG_INTERFACE_MODEL : boolean := false;
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
BANK_WIDTH : integer := 3; -- # of bank address
CKE_WIDTH : integer := 1; -- # of clock enable outputs
CS_WIDTH : integer := 1; -- # of chip select
DM_WIDTH : integer := 8; -- # of data mask
DQ_WIDTH : integer := 64; -- # of data bits
DQS_WIDTH : integer := 8; -- # of strobe pairs
ODT_WIDTH : integer := 1; -- # of ODT outputs
ROW_WIDTH : integer := 14 -- # of row/column address
);
port (
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0)
);
end;
architecture rtl of ddr_dummy is
component OBUF generic (IOSTANDARD : string := "SSTL15");
port (O : out std_ulogic; I : in std_ulogic);
end component;
component IOBUF generic (IOSTANDARD : string := "SSTL15_T_DCI");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic);
end component;
component OBUFDS generic(IOSTANDARD : string := "DIFF_SSTL15");
port(O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
component IOBUFDS generic (IOSTANDARD : string := "DIFF_SSTL15");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic);
end component;
signal in_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal in_dqs : std_logic_vector(DQS_WIDTH-1 downto 0);
begin
io_cas : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cas_n, I => '0');
io_ras : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_ras_n, I => '0');
io_we : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_we_n, I => '0');
io_ck : OBUFDS generic map (IOSTANDARD => "DIFF_SSTL15")
port map (O => ddr_ck_p(0), OB => ddr_ck_n(0), I => '0');
io_addr_gen : for i in 0 to ROW_WIDTH-1 generate
begin
io_addr : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_addr(i), I => '0');
end generate io_addr_gen;
io_ba_gen : for i in 0 to BANK_WIDTH-1 generate
begin
io_addr : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_ba(i), I => '0');
end generate io_ba_gen;
io_cs_gen : for i in 0 to CS_WIDTH*nCS_PER_RANK-1 generate
begin
io_cs : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cs_n(i), I => '0');
end generate io_cs_gen;
io_odt_gen : for i in 0 to ODT_WIDTH-1 generate
begin
io_odt : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_odt(i), I => '0');
end generate io_odt_gen;
io_dm_gen : for i in 0 to DM_WIDTH-1 generate
begin
io_dm : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_dm(i), I => '0');
end generate io_dm_gen;
io_cke_gen : for i in 0 to CKE_WIDTH-1 generate
begin
io_cke : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cke(i), I => '0');
end generate io_cke_gen;
op_reset : OBUF generic map (IOSTANDARD => "LVCMOS15")
port map (O => ddr_reset_n, I => '1');
io_dq_gen : for i in 0 to DQ_WIDTH-1 generate
begin
io_dq : IOBUF generic map (IOSTANDARD => "SSTL15_T_DCI")
port map (O => in_dq(i), IO => ddr_dq(i), I => '0', T => '0');
end generate io_dq_gen;
io_dqs_gen : for i in 0 to DQS_WIDTH-1 generate
begin
io_dqs : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL15_T_DCI")
port map (O => in_dqs(i), IO => ddr_dqs(i), IOB => ddr_dqs_n(i), I => '0', T => '1');
end generate io_dqs_gen;
end architecture rtl;
|
gpl-2.0
|
572172cb53bd3e5e781bb1759be1099c
| 0.53685 | 3.435733 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-arrow-bemicro-sdk/leon3mp.vhd
| 1 | 27,561 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 - 2012 Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
cpu_rst_n : in std_ulogic;
clk_fpga_50m : in std_ulogic;
-- DDR SDRAM
ram_a : out std_logic_vector (13 downto 0); -- ddr address
ram_ck_p : out std_logic;
ram_ck_n : out std_logic;
ram_cke : out std_logic;
ram_cs_n : out std_logic;
ram_ws_n : out std_ulogic; -- ddr write enable
ram_ras_n : out std_ulogic; -- ddr ras
ram_cas_n : out std_ulogic; -- ddr cas
ram_dm : out std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
ram_dqs : inout std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
ram_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ram_d : inout std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
txd : out std_logic_vector(3 downto 0);
rxd : in std_logic_vector(3 downto 0);
tx_clk : in std_logic;
rx_clk : in std_logic;
tx_en : out std_logic;
rx_dv : in std_logic;
eth_crs : in std_logic;
rx_er : in std_logic;
eth_col : in std_logic;
mdio : inout std_logic;
mdc : out std_logic;
eth_reset_n : out std_logic;
-- Temperature sensor
temp_sc : inout std_logic;
temp_cs_n : out std_logic;
temp_sio : inout std_logic;
-- LEDs
f_led : inout std_logic_vector(7 downto 0);
-- User push-button
pbsw_n : in std_logic;
-- Reconfig SW1 and SW2
reconfig_sw : in std_logic_vector(2 downto 1);
-- SD card interface
sd_dat0 : inout std_logic;
sd_dat1 : inout std_logic;
sd_dat2 : inout std_logic;
sd_dat3 : inout std_logic;
sd_cmd : inout std_logic;
sd_clk : inout std_logic;
-- EPCS
epcs_data : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_csn : out std_ulogic;
epcs_asdi : out std_ulogic
-- Expansion connector on card edge (set as reserved in design's QSF)
--reset_exp_n : out std_logic;
--exp_present : in std_logic;
--p : inout std_logic_vector(64 downto 1)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbs : integer := 6
--pragma translate_off
+1 -- one more in simulation (AHBREP)
--pragma translate_on
;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal clkm, clkml : std_ulogic;
signal lclk, resetn : std_ulogic;
signal clklock, lock : std_ulogic;
signal rstn, rawrstn : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal tck : std_ulogic;
signal tckn : std_ulogic;
signal tms : std_ulogic;
signal tdi : std_ulogic;
signal tdo : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u0i : uart_in_type;
signal u0o : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spii2 : spi_in_type;
signal spio2 : spi_out_type;
signal slvsel2 : std_logic_vector(0 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsu_breakn : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
cgi.pllctrl <= "00"; cgi.pllrst <= not rawrstn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech)
port map (clk_fpga_50m, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (
tech => CFG_CLKTECH,
clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV,
sdramen => 0,
freq => freq)
port map (
clkin => lclk,
pciclkin => gnd(0),
clk => clkm,
clkn => open,
clk2x => open,
sdclk => open,
pciclk => open,
cgi => cgi,
cgo => cgo);
reset_pad : inpad generic map (tech => padtech) port map (cpu_rst_n, resetn);
rst0 : rstgen -- reset generator
port map (
rstin => resetn,
clk => clkm,
clklock => clklock,
rstout => rstn,
rstoutraw => rawrstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (
defmast => CFG_DEFMST,
split => CFG_SPLIT,
rrobin => CFG_RROBIN,
ioaddr => CFG_AHBIO,
ioen => IOAEN,
nahbm => maxahbm,
nahbs => maxahbs)
port map (
rst => rstn,
clk => clkm,
msti => ahbmi,
msto => ahbmo,
slvi => ahbsi,
slvo => ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => CFG_NWIN,
dsu => CFG_DSU,
fpu => CFG_FPU,
v8 => CFG_V8,
cp => 0,
mac => CFG_MAC,
pclow => pclow,
notag => CFG_NOTAG,
nwp => CFG_NWP,
icen => CFG_ICEN,
irepl => CFG_IREPL,
isets => CFG_ISETS,
ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ,
isetlock => CFG_ILOCK,
dcen => CFG_DCEN,
drepl => CFG_DREPL,
dsets => CFG_DSETS,
dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ,
dsetlock => CFG_DLOCK,
dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN,
ilramsize => CFG_ILRAMSZ,
ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN,
dlramsize => CFG_DLRAMSZ,
dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN,
itlbnum => CFG_ITLBNUM,
dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE,
tlb_rep => CFG_TLB_REP,
lddel => CFG_LDDEL,
disas => disas,
tbuf => CFG_ITBSZ,
pwd => CFG_PWD,
svt => CFG_SVT,
rstaddr => CFG_RSTADDR,
smp => NCPU-1,
cached => CFG_DFIXED,
scantest => CFG_SCAN,
mmupgsz => CFG_MMU_PAGE,
bp => CFG_BP,
npasi => CFG_NP_ASI,
pwrpsr => CFG_WRPSR)
port map (
clk => clkm,
rstn => rstn,
ahbi => ahbmi,
ahbo => ahbmo(i),
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => dbgi(i),
dbgo => dbgo(i));
end generate;
errorn_pad : toutpad generic map (tech => padtech) port map (f_led(6), gnd(0), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (
hindex => 2,
haddr => 16#900#,
hmask => 16#F00#,
ncpu => NCPU,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => CFG_ATBSZ)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(2),
dbgi => dbgo,
dbgo => dbgi,
dsui => dsui,
dsuo => dsuo);
dsui.enable <= '1';
dsui.break <= not dsu_breakn; -- Switch polarity
dsubre_pad : inpad generic map (tech => padtech) port map (pbsw_n, dsu_breakn);
dsuact_pad : toutpad generic map (tech => padtech) port map (f_led(7), gnd(0), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(
rst => rstn,
clk => clkm,
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
ahbi => ahbmi,
ahbo => ahbmo(NCPU+CFG_AHB_UART),
tapo_tck => open,
tapo_tdi => open,
tapo_inst => open,
tapo_rst => open,
tapo_capt => open,
tapo_shft => open,
tapo_upd => open,
tapi_tdo => gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR memory controller
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa
generic map (
fabtech => fabtech,
memtech => memtech,
hindex => 0,
haddr => 16#400#,
hmask => 16#F00#,
ioaddr => 1,
pwron => CFG_DDRSP_INIT,
MHz => BOARD_FREQ/1000,
rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5,
clkdiv => 10,
ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE,
ddrbits => 16,
regoutput => 1,
mobile => 0)
port map (
rst_ddr => rawrstn,
rst_ahb => rstn,
clk_ddr => lclk,
clk_ahb => clkm,
lock => lock,
clkddro => clkml,
clkddri => clkml,
ahbsi => ahbsi,
ahbso => ahbso(0),
ddr_clk => ddr_clkv,
ddr_clkb => ddr_clkbv,
ddr_clk_fb_out => open,
ddr_clk_fb => gnd(0),
ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv,
ddr_web => ram_ws_n,
ddr_rasb => ram_ras_n,
ddr_casb => ram_cas_n,
ddr_dm => ram_dm,
ddr_dqs => ram_dqs,
ddr_ad => ram_a,
ddr_ba => ram_ba,
ddr_dq => ram_d);
end generate;
ram_ck_p <= ddr_clkv(0);
ram_ck_n <= ddr_clkbv(0);
ram_cke <= ddr_ckev(0);
ram_cs_n <= ddr_csbv(0);
ddrsp1 : if (CFG_DDRSP = 0) generate
ahbso(0) <= ahbs_none;
lock <= '1';
ddr_clkv <= (others => '0');
ddr_clkbv <= (others => '0');
ddr_ckev <= (others => '1');
ddr_csbv <= (others => '1');
end generate;
-- SPI Memory Controller
spimc: if CFG_SPIMCTRL /= 0 and CFG_AHBROMEN = 0 generate
spimctrl0 : spimctrl
generic map (
hindex => 4,
hirq => 9,
faddr => 16#000#,
fmask => 16#f00#,
ioaddr => 16#002#,
iomask => 16#fff#,
spliten => CFG_SPLIT,
oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4),
spii => spmi,
spio => spmo);
end generate;
epcs_miso_pad : inpad generic map (tech => padtech)
port map (epcs_data, spmi.miso);
epcs_mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdi, spmo.mosi);
epcs_sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
epcs_slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_csn, spmo.csn);
nospimc : if CFG_SPIMCTRL /= 1 or CFG_AHBROMEN /= 0 generate
spmo <= spimctrl_out_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- AHB/APB bridge
apb0 : apbctrl
generic map (
hindex => 1,
haddr => CFG_APBADDR,
nslaves => 7)
port map (
rst => rstn,
clk => clkm,
ahbi => ahbsi,
ahbo => ahbso(1),
apbi => apbi,
apbo => apbo);
-- 8-bit UART, not connected off-chip, use in loopback with GRMON
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (
pindex => 1,
paddr => 1,
pirq => 2,
console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(1),
uarti => u0i,
uarto => u0o);
end generate;
u0i.rxd <= '0'; u0i.ctsn <= '0'; u0i.extclk <= '0';
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (
pindex => 2,
paddr => 2,
ncpu => NCPU)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(2),
irqi => irqo,
irqo => irqi);
end generate;
noirqctrl : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (
pindex => 3,
paddr => 3,
pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ,
sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(3),
gpti => gpti,
gpto => open);
end generate;
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
gpti.wdogen <= '0';
notim : if CFG_GPT_ENABLE = 0 generate
apbo(3) <= apb_none;
end generate;
-- GPIO unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(
pindex => 0,
paddr => 0,
imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map(
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(0),
gpioi => gpioi,
gpioo => gpioo);
end generate;
gpio_pads : iopadvv generic map (tech => padtech, width => 6)
port map (f_led(5 downto 0), gpioo.dout(5 downto 0),
gpioo.oen(5 downto 0), gpioi.din(5 downto 0));
gpioi.din(31 downto 6) <= (others => '0');
nogpio : if CFG_GRGPIO_ENABLE = 0 generate
apbo(0) <= apb_none;
end generate;
-- SPI controller connected to temperature sensor
spic: if CFG_SPICTRL_ENABLE /= 0 generate
spi1 : spictrl
generic map (
pindex => 4,
paddr => 4,
pmask => 16#fff#,
pirq => 9,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 1,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(4),
spii => spii,
spio => spio,
slvsel => slvsel);
end generate spic;
-- MISO signal not used
spii.miso <= '0';
mosi_pad : iopad generic map (tech => padtech)
port map (temp_sio, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (temp_sc, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (temp_cs_n, slvsel(0));
spii.spisel <= '1'; -- Master only
nospic : if CFG_SPICTRL_ENABLE = 0 generate
apbo(4) <= apb_none;
spio.misooen <= '1';
spio.mosioen <= '1';
spio.sckoen <= '1';
slvsel <= (others => '1');
end generate;
-- SPI controller connected to SD card slot
spic2: if CFG_SPICTRL_ENABLE /= 0 and CFG_SPICTRL_NUM > 1 generate
spi1 : spictrl
generic map (
pindex => 5,
paddr => 5,
pmask => 16#fff#,
pirq => 11,
fdepth => CFG_SPICTRL_FIFO,
slvselen => 1,
slvselsz => 1,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 0,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(5),
spii => spii2,
spio => spio2,
slvsel => slvsel2);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat0, spio2.miso, spio2.misooen, spii2.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio2.mosi, spio2.mosioen, spii2.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_clk, spio2.sck, spio2.sckoen, spii2.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel2(0));
spii2.spisel <= '1'; -- Master only
end generate;
nospic2 : if CFG_SPICTRL_ENABLE = 0 or CFG_SPICTRL_NUM < 2 generate
apbo(5) <= apb_none;
spio2.misooen <= '1';
spio2.mosioen <= '1';
spio2.sckoen <= '1';
slvsel2(0) <= '0';
end generate;
-- sd_dat1 and sd_dat2 are unused
unuseddat1_pad : iopad generic map (tech => padtech)
port map (sd_dat1, gnd(0), vcc(1), open);
unuseddat2_pad : iopad generic map (tech => padtech)
port map (sd_dat2, gnd(0), vcc(1), open);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler Ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 6,
paddr => 6,
pirq => 10,
memtech => memtech,
mdcscaler => CPU_FREQ/(4*1000)-1,
enable_mdio => 1,
fifosize => CFG_ETH_FIFO,
nsync => 1,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 1,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG),
apbi => apbi,
apbo => apbo(6),
ethi => ethi,
etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eth_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eth_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eth_reset_n, rawrstn);
end generate;
noeth : if CFG_GRETH = 0 generate
apbo(6) <= apb_none;
ethi <= eth_in_none;
etho <= eth_out_none;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (
hindex => 3,
haddr => CFG_AHBRODDR,
pipe => CFG_AHBROPIP)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(3) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (
hindex => 5,
haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(5) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- AHB Report Module for simulation ----------------------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
driveahbm : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
driveahbs : for i in maxahbs to NAHBSLV-1 generate
ahbso(i) <= ahbs_none;
end generate;
driveapb : for i in 7 to NAPBSLV-1 generate
apbo(i) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 BeMicro SDK Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
f76d7e47d122b7a43a5f262b886c1953
| 0.477414 | 3.950265 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/amba/dma2ahb.vhd
| 1 | 25,668 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB (Entity & architecture declarations)
--
-- File name : dma2ahb.vhd
--
-- Purpose : AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : The AMBA AHB interface has been reduced in function to support
-- only what is required. The following features are constrained:
-- Optionally generates HSIZE=BYTE, HWORD and WORD
-- Only generates HPROT="0011"
-- Allways generates HBURST=HBURST_SINGLE, HBURST_INCR
-- Optionally generates HBURST_INCR4, HBURST_INCR8, HBURST_INCR16
--
-- Generates the following on reponses on DMA interface:
-- HRESP=HRESP_OKAY => DMAOut.Ready
-- HRESP=HRESP_ERROR => DMAOut.Fault
-- HRESP=HRESP_RETRY => DMAOut.Retry (normally not used)
-- HRESP=HRESP_SPLIT => DMAOut.Retry (normally not used)
--
-- Assumes pipelined data input (after OKAY asserted).
--
-- Only big-endianness is supported.
--
-- Supports Early Bus Termination with automatic restart.
-- Supports Retry/Split with automatic restart.
--
-- Library : gaisler
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jul 2003 New version
-- 0.2 SH 21 Jul 2003 Combinatorial response introduced
-- 0.3 SH 25 Jan 2004 Support for interrupted bursts introduced
-- (early burst termination)
-- Optimised coding
-- Idle transfer initiated in 1st error phase
-- 1.3 SH 1 Oct 2004 Ported to GRLIB
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.6 SH 1 Nov 2005 DMAOut.Grant asserted only while HREADY high
-- 1.8 SH 10 Nov 2005 Re-ported to GRLIB
-- 1.8.1 SH 12 Dec 2005 Ensured no HTRANS=seq occurs after idle
-- 1.9 SH 1 Jan 2006 Resolve retry/early burst termination
-- 1.9.2 SH 3 Jan 2006 DelDataPhase dealyed with HREADY signal
-- 1.9.3 SH 24 Feb 2006 Added syncrst generic
-- 1.9.4 MI 27 Mar 2007 Driving HSIZE with address
-- 1.9.5 SH 14 Dec 2007 Automatic 1kbyte boundary crossing (merged)
-- 1.9.6 JA 14 Dec 2007 Support for halfword and byte bursts
-- 1.9.7 MI 4 Aug 2008 Support for Lock
-- 1.9.8 SH 16 Apr 2009 Address recovery after SPLIT/RETRY moved
-- 1.9.9 SH 9 Oct 2009 HPROT defult to 0x3
-- 2.0 SH 4 Mar 2011 DMAOut.Grant masked while ReAddrPhase set
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDLIB.all;
use GRLIB.DMA2AHB_Package.all;
entity DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic; -- system clock
HRESETn: in Std_ULogic; -- asynchronous reset
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end entity DMA2AHB;
--============================== Architecture ================================--
architecture RTL of DMA2AHB is
--=========================================================================--
-- Configuration GRLIB
-----------------------------------------------------------------------------
constant HConfig: AHB_Config_Type := (
0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
others => (others => '0'));
--=========================================================================--
-----------------------------------------------------------------------------
-- Local signals
-----------------------------------------------------------------------------
signal Address: Std_Logic_Vector(31 downto 0);
signal AddressSave: Std_Logic_Vector(31 downto 0);
signal ActivePhase: Std_ULogic; -- ongoing access
signal AddressPhase: Std_ULogic; -- address phase
signal DataPhase: Std_ULogic; -- data phase
signal ReDataPhase: Std_ULogic; -- restart first
signal ReAddrPhase: Std_ULogic; -- restart second
signal IdlePhase: Std_ULogic; -- idle phase
signal EarlyPhase: Std_ULogic; -- early termination
signal BoundaryPhase: Std_ULogic; -- boundary crossing
signal SingleAcc: Std_ULogic; -- single access
signal WriteAcc: Std_ULogic; -- write access
signal DelDataPhase: Std_ULogic; -- restart first
signal DelAddrPhase: Std_ULogic; -- restart second
signal AHBInHGRANTx: Std_ULogic; -- decoded grant
begin
--=========================================================================--
-- AMBA AHB master interface
-----------------------------------------------------------------------------
AHBOut.HIRQ <= (others => '0');
AHBOut.HCONFIG <= HConfig;
AHBOut.HINDEX <= hindex;
AHBInHGRANTx <= AHBIn.HGRANT(hindex);
--=========================================================================--
-----------------------------------------------------------------------------
-- AMBA AHB Master interface with fast issuing of accesses
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Fixed AMBA AHB signals
-----------------------------------------------------------------------------
AHBOut.HPROT <= "0011";
-----------------------------------------------------------------------------
-- Combinatorial paths
-----------------------------------------------------------------------------
AHBOut.HADDR <= Address; -- internal to external
AHBOut.HWDATA <= ahbdrivedata(DMAIn.Data); -- combinatorial path
DMAOut.OKAY <= '1' when AHBIn.HREADY='1' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_OKAY else
'0';
DMAOut.Retry <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
(AHBIN.HRESP=HRESP_RETRY or
AHBIN.HRESP=HRESP_SPLIT) else
'0';
DMAOut.Fault <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_ERROR else
'0';
DMAOut.Grant <= '0' when ReDataPhase='1' or ReAddrPhase='1' else
'1' when AHBIn.HREADY='1' and
AHBInHGRANTx='1' and
DMAIn.Request='1' else
'0';
AHBOut.HBUSREQ <= '0' when IdlePhase='1' else
'1' when DMAIn.Request='1' else
'1' when DMAIn.Burst='1' else
'1' when ReDataPhase='1' else
'1' when ReAddrPhase='1' else
'0';
AHBOut.HLOCK <= '0' when IdlePhase='1' else
'1' when (DMAIn.Lock and
(DMAIn.Request or ReDataPhase)) = '1'else
'0';
-----------------------------------------------------------------------------
-- The AMBA AHB interfacing is done in this process
-----------------------------------------------------------------------------
AHBMaster: process(HCLK, HRESETn)
variable BoundaryCrossing: Std_ULogic;
variable AddressInc: Std_Logic_Vector(3 downto 0);
--------------------------------------------------------------------------
-- This procedure is used to define all reset values for the
-- asynchronous or synchronous reset statements in this process. This
-- is done to avoid source code duplication.
--------------------------------------------------------------------------
procedure Reset is
begin
ActivePhase <= '0';
EarlyPhase <= '0';
AddressPhase <= '0';
DataPhase <= '0';
ReDataPhase <= '0';
ReAddrPhase <= '0';
DelDataPhase <= '0';
DelAddrPhase <= '0';
BoundaryPhase <= '0';
IdlePhase <= '0';
EarlyPhase <= '0';
SingleAcc <= '0';
WriteAcc <= '0';
Address <= (others => '0');
AddressSave <= (others => '0');
DMAOut.Ready <= '0';
DMAOut.Data <= (others => '0');
AHBOut.HSIZE <= HSIZE_BYTE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HWRITE <= '0';
end Reset; ---------------------------------------------------------------
begin
if HRESETn='0' and syncrst=0 then -- asynchronous reset
Reset;
elsif Rising_Edge(HCLK) then
if DMAIn.Reset='1' or -- functional reset
(syncrst/=0 and HRESETn='0') then -- synchronous reset
Reset;
else -- no reset
--------------------------------------------------------------------
-- Temporary variables
--------------------------------------------------------------------
BoundaryCrossing := '0';
AddressInc := (others => '0');
--------------------------------------------------------------------
-- AMBA AHB interface - data phase handling
--------------------------------------------------------------------
-- indicate when no more activies are pending
if AddressPhase='0' and DataPhase='0' and
ReDataPhase='0' and ReAddrPhase='0' and
DMAIn.Burst='0' then
ActivePhase <= '0';
end if;
if AHBIn.HREADY='0' and DataPhase='1' then
-- error check
if AHBIN.HRESP=HRESP_ERROR then
DataPhase <= '0'; -- data phase aborted
end if;
-- split or retry check
if AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
ReDataPhase <= DataPhase; -- restart phases
ReAddrPhase <= AddressPhase or ReAddrPhase;
AddressPhase <= '0'; -- addr phase aborted
DataPhase <= '0'; -- data phase aborted
end if;
end if;
if AHBIn.HREADY='1' and DataPhase='1' then
-- sample AHB input data at end of data phase
DMAOut.Data <= ahbreadword(AHBIn.HRDATA);
DataPhase <= '0'; -- data phase ends
DMAOut.Ready <= '1';
else
-- remove acknowledgement after one cycle
DMAOut.Ready <= '0';
end if;
--------------------------------------------------------------------
-- AMBA AHB interface - address phase handling
--------------------------------------------------------------------
-- initialize data phase on AHB after previous address phase
if AddressPhase='1' and AHBIn.HREADY='1' then
DataPhase <= '1'; -- data phase start
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
if AddressPhase='1' then
-- burst continuation, sequential transfer
AddressInc(conv_integer(DMAIn.Size)) := '1';
if boundary=1 then -- automatic boundary
Address <= Address + AddressInc;
AddressSave <= Address;
if Address(9 downto 2)="11111111" then
BoundaryCrossing := '1';
BoundaryPhase <= '1';
end if;
else
Address(31 downto 10) <= DMAIn.Address(31 downto 10);
Address( 9 downto 0) <= Address(9 downto 0) + AddressInc;
AddressSave(9 downto 0) <= Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
elsif AHBInHGRANTx='1' and ActivePhase='0' and DMAIn.Request='1' then
-- start of burst, non-sequential transfer
-- start of single, non-sequential transfer
if boundary=1 then -- automatic boundary
Address <= DMAIn.Address;
AddressSave <= DMAIn.Address;
BoundaryCrossing := '0';
BoundaryPhase <= '0';
else
Address <= DMAIn.Address;
AddressSave(9 downto 0) <= DMAIn.Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
end if;
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
IdlePhase <= '0'; -- one clock cycle only
end if;
-- initialize address phase on AHB
if AHBIn.HREADY='1' then
-- granted the AHB bus
if AHBInHGRANTx='1' then
if ReDataPhase='1' then
ReDataPhase <= '0';
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
-- go back with address
if boundary=1 then
Address <= AddressSave;
else
Address(9 downto 0) <= AddressSave(9 downto 0);
end if;
elsif ReAddrPhase='1' then
AddressPhase <= '1'; -- address phase start
ReAddrPhase <= '0';
if AddressPhase='1' then
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
AHBOut.HTRANS <= HTRANS_NONSEQ;
end if;
EarlyPhase <= '0';
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
elsif EarlyPhase='1' then
-- early terminated burst resumed
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_INCR;
AHBOut.HWRITE <= WriteAcc;
elsif DMAIn.Request='1' and DMAIn.Burst='1' then
AddressPhase <= '1'; -- address phase start
if ActivePhase='1' then
-- burst continuation, sequential transfer
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
-- start of burst, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
if DMAIn.Beat ="00" then
AHBOut.HBURST <= HBURST_INCR;
elsif DMAIn.Beat ="01" then
AHBOut.HBURST <= HBURST_INCR4;
elsif DMAIn.Beat ="10" then
AHBOut.HBURST <= HBURST_INCR8;
else
AHBOut.HBURST <= HBURST_INCR16;
end if;
AHBOut.HWRITE <= DMAIn.Store;
ActivePhase <= '1';
SingleAcc <= '0';
WriteAcc <= DMAIn.Store;
end if;
elsif DMAIn.Request='0' and DMAIn.Burst='1' and ActivePhase='1' then
-- burst in wait state
AddressPhase <= '0'; -- no address phase
AHBOut.HTRANS <= HTRANS_BUSY;
elsif DMAIn.Request='1' and DMAIn.Burst='0' then
-- start of single, non-sequential transfer
AddressPhase <= '1'; -- address phase start
ActivePhase <= '1';
SingleAcc <= '1';
WriteAcc <= DMAIn.Store;
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= DMAIn.Store;
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
-- not granted the AHB bus, but early burst termination
elsif (DMAIn.Request='1' or DMAIn.Burst='1') and ActivePhase='1'then
-- must restart a burst transfer since grant removed
AddressPhase <= '0'; -- no address phase
EarlyPhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
-- not granted the AHB bus
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
elsif AHBIn.HREADY='0' and DataPhase='1' then
if AHBIN.HRESP=HRESP_ERROR or
AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
-- drive idle transfer due to error, retry or split
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
IdlePhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
end if;
end if;
if AHBIn.HREADY='1' then -- delay one phase
DelDataPhase <= ReDataPhase;
DelAddrPhase <= ReAddrPhase;
end if;
-- temporary variables cleared
BoundaryCrossing := '0';
AddressInc := (others => '0');
else
null;
end if;
end process AHBMaster;
end architecture RTL; --======================================================--
|
gpl-2.0
|
06cbacd64700ef3eccc772400f0d2ba8
| 0.406343 | 5.672486 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/inpad_ddr.vhd
| 1 | 3,743 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ddr, inpad_ddrv
-- File: inpad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates an input pad connected to a DDR_IREG.
-- The generic tech wrappers are not used for nextreme since this
-- technology is not wrapped by ddr_ireg.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity inpad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
voltage : integer := x33v;
filter : integer := 0;
strength : integer := 0
);
port (
pad : in std_ulogic;
o1, o2 : out std_ulogic;
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of inpad_ddr is
signal d : std_ulogic;
begin
def: if (tech /= easic90) and (tech /= easic45) generate
p : inpad generic map (tech, level, voltage, filter, strength)
port map (pad, d);
ddrreg : ddr_ireg generic map (tech)
port map (o1, o2, c1, c2, ce, d, r, s);
end generate def;
nex : if (tech = easic90) generate
p : nextreme_inpad generic map (level, voltage)
port map(pad, d);
ddrreg : nextreme_iddr_reg
port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r);
end generate;
n2x : if (tech = easic45) generate
p : n2x_inpad_ddr generic map (level, voltage)
port map (pad, o1, o2, c1, c2, ce, r, s);
d <= '0';
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
voltage : integer := 0;
filter : integer := 0;
strength : integer := 0;
width : integer := 1
);
port (
pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of inpad_ddrv is
begin
n2x : if (tech = easic45) generate
p : n2x_inpad_ddrv generic map (level, voltage, width)
port map (pad, o1, o2, c1, c2, ce, r, s);
end generate;
base : if (tech /= easic45) generate
v : for i in width-1 downto 0 generate
x0 : inpad_ddr generic map (tech, level, voltage, filter, strength)
port map (pad(i), o1(i), o2(i), c1, c2, ce, r, s);
end generate;
end generate;
end;
|
gpl-2.0
|
8aae96b9116db7c14a0ffcfd29f5de60
| 0.589901 | 3.511257 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-3s1500/mctrl_avnet.vhd
| 4 | 34,646 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl_avnet is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
avnetmezz : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl_avnet is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
addressx : std_logic_vector(31 downto 0); -- shifted memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rsbdrive, risbdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive, rsbdrive, lsdo)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbsi.hwdata;
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if r.address(1) = '0' then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 17) := sdmo.prdata(31 downto 17);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
v.addressx := v.address;
if avnetmezz = 1 then
if v.ramsn(1 downto 0) = "11" then -- SDRAM/SRAM shares strobes
v.mben := lsdo.dqm(3 downto 0);
end if;
if ((v.ramsn(0) and r.ramsn(0)) = '0') then -- mezz address shift
v.addressx := "00" & v.address(31 downto 2);
else
v.addressx := v.address;
end if;
else
v.addressx := "00" & v.address(31 downto 2);
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.addressx;
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
if (avnetmezz = 1) then
memo.writen <= r.writen and lsdo.sdwen;
else
memo.writen <= r.writen;
end if;
memo.bdrive <= bdrive;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.vbdrive <= rbdrive;
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
ahbso.hrdata <= dataout;
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (rst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
end generate;
end;
|
gpl-2.0
|
749f6ca4f3fea4b99f82ebaaf03ebb4a
| 0.542978 | 3.207369 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2c2ahb_gen.vhd
| 1 | 4,200 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_gen
-- File: i2c2ahb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_gen;
architecture rtl of i2c2ahb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, i2ci, i2co);
end architecture rtl;
|
gpl-2.0
|
5eab1f7bcc7ecce56b4534b7c04128b1
| 0.598095 | 3.317536 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc7z020/leon3_zedboard_stub_sim.vhd
| 3 | 9,633 |
-------------------------------------------------------------------------------
-- leon3_zedboard_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity leon3_zedboard_stub is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end leon3_zedboard_stub;
architecture STRUCTURE of leon3_zedboard_stub is
signal clk : std_logic := '0';
signal clk0 : std_logic := '0';
signal clk1 : std_logic := '0';
signal rst : std_logic := '0';
type memstatetype is (idle, read1, read2, read3, write1, write2, write3);
type blane is array (0 to 2**18-1) of natural;
type memtype is array (0 to 3) of blane;
constant abits : integer := 20;
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**abits)-1)) of BYTE;
type regtype is record
memstate : memstatetype;
addr : integer;
arlen : integer;
mem : memtype;
rcnt : integer;
end record;
signal S_AXI_GP0_rvalid_i : std_logic;
signal r, rin : regtype;
begin
clk0 <= not clk0 after 6.0 ns; -- 83.33 MHz
clk1 <= not clk1 after 2.5 ns; -- 200 MHz
rst <= '1' after 1 us;
S_AXI_GP0_rvalid <= S_AXI_GP0_rvalid_i;
FCLK_CLK0 <= clk0;
clk <= clk0;
FCLK_CLK1 <= clk1;
-- FCLK_CLK2 <= clk2;
-- FCLK_CLK3 <= clk3;
FCLK_RESET0_N <= rst;
mem0 : process(clk)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is "ram.srec";
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable memstate : memstatetype;
variable addr : integer;
-- variable len : integer;
-- variable mem : memtype;
variable rcnt : integer;
begin
if FIRST then
-- if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
elsif rising_edge(clk) then
case memstate is
when idle =>
S_AXI_GP0_arready <= '0'; S_AXI_GP0_rvalid_i <= '0'; S_AXI_GP0_rlast <= '0';
S_AXI_GP0_awready <= '0'; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '0';
if S_AXI_GP0_arvalid = '1' then
memstate := read1; S_AXI_GP0_arready <= '1';
elsif S_AXI_GP0_awvalid = '1' then
memstate := write1; S_AXI_GP0_awready <= '1';
end if;
when read1 =>
addr:= conv_integer(S_AXI_GP0_araddr(19 downto 0));
len := conv_integer(S_AXI_GP0_arlen);
S_AXI_GP0_arready <= '0'; memstate := read2; rcnt := 23;
when read2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
S_AXI_GP0_rvalid_i <= '1';
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
if (S_AXI_GP0_rready and S_AXI_GP0_rvalid_i) = '1' then
if len = 0 then
S_AXI_GP0_rlast <= '0'; S_AXI_GP0_rvalid_i <= '0';
memstate := idle;
else
addr := addr + 4; len := len - 1;
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
end if;
end if;
for i in 0 to 3 loop
S_AXI_GP0_rdata(i*8+7 downto i*8) <= MEMA(addr+3-i);
end loop;
end if;
when write1 =>
addr:= conv_integer(S_AXI_GP0_awaddr(19 downto 0));
len := conv_integer(S_AXI_GP0_awlen);
S_AXI_GP0_awready <= '0'; memstate := write2; rcnt := 0;
when write2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
memstate := write3;
S_AXI_GP0_wready <= '1';
end if;
when write3 =>
if S_AXI_GP0_wvalid = '1' then
for i in 0 to 3 loop
if S_AXI_GP0_wstrb(i) = '1' then
MEMA(addr+3-i) := S_AXI_GP0_wdata(i*8+7 downto i*8);
end if;
end loop;
if (len = 0) or (S_AXI_GP0_wlast = '1') then
memstate := idle; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '1';
else
addr := addr + 1; len := len - 1;
end if;
end if;
when others =>
end case;
end if;
end process;
S_AXI_GP0_bid <= (others => '0');
S_AXI_GP0_bresp <= (others => '0');
S_AXI_GP0_rresp <= (others => '0');
S_AXI_GP0_rid <= (others => '0');
DDR_addr <= (others => '0');
DDR_ba <= (others => '0');
DDR_cas_n <= '0';
DDR_ck_n <= '0';
DDR_ck_p <= '0';
DDR_cke <= '0';
DDR_cs_n <= '0';
DDR_dm <= (others => '0');
DDR_dq <= (others => '0');
DDR_dqs_n <= (others => '0');
DDR_dqs_p <= (others => '0');
DDR_odt <= '0';
DDR_ras_n <= '0';
DDR_reset_n <= '0';
DDR_we_n <= '0';
FIXED_IO_ddr_vrn <= '0';
FIXED_IO_ddr_vrp <= '0';
FIXED_IO_mio <= (others => '0');
FIXED_IO_ps_clk <= '0';
FIXED_IO_ps_porb <= '0';
FIXED_IO_ps_srstb <= '0';
end architecture STRUCTURE;
|
gpl-2.0
|
18687f4608ccb45e6d383390507411ba
| 0.521956 | 3.137785 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ambatest/ahbtbs.vhd
| 1 | 5,472 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbs
-- File: ahbtbs.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AMBA testbench slave
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use work.ahbtbp.all;
entity ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbtbs is
constant abits : integer := log2(kbytes) + 8;
constant ws : std_logic_vector(7 downto 0) :="00000000";
constant retry : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, 0, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
ws : std_logic_vector(7 downto 0);
rty : std_logic_vector(3 downto 0);
retry : std_logic;
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal write : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
v.hresp := HRESP_OKAY;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
v.ws := ws;
--v.retry := retry;
if retry = 1 then
if v.hsel = '1' then
v.rty := r.rty - 1;
if r.rty = "0000" then
v.retry := '0';
v.rty := "0010";
else
v.retry := '1';
end if;
end if;
else
v.retry := '0';
end if;
end if;
if r.ws /= "00000000" and r.hsel = '1' then
v.ws := r.ws - 1;
end if;
if v.ws /= "00000000" and v.hsel = '1' then
v.hready := '0';
elsif v.hsel = '1' and v.retry = '1' then
if r.hresp = HRESP_OKAY then
v.hready := '0';
v.hresp := HRESP_RETRY;
else
v.hready := '1';
v.hresp := HRESP_RETRY;
v.retry := '0';
end if;
end if;
if (r.hwrite or not r.hready) = '1' then
haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if r.hwrite = '1' and r.hready = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
--v.hready := not (v.hsel and not ahbsi.hwrite);
--v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then
v.hwrite := '0'; v.hready := '1'; v.ws := ws;
v.rty := "0010";
end if;
write <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ramdata;
end process;
ahbso.hresp <= r.hresp; --"00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
ra : for i in 0 to 3 generate
aram : syncram generic map (tech, abits, 8) port map (
clk, ramaddr, ahbsi.hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, write(3-i));
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
|
gpl-2.0
|
01bbe165721236f1ae5cfc27370d745f
| 0.566338 | 3.369458 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-111/ahb2mig_ztex.vhd
| 1 | 15,304 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN"
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
|
gpl-2.0
|
06f25a94dcfadd4707439743689a88b3
| 0.507776 | 3.046785 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-sockit/ahbrom.vhd
| 28 | 6,162 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
23115658272ccfeb960b03ead7a4ec23
| 0.5852 | 3.406302 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-pci-xc5v/config.vhd
| 1 | 10,841 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#0d0007#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 1;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 1;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 1024;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- USB Host Controller
constant CFG_GRUSBHC : integer := 0;
constant CFG_GRUSBHC_NPORTS : integer := 1;
constant CFG_GRUSBHC_EHC : integer := 0;
constant CFG_GRUSBHC_UHC : integer := 0;
constant CFG_GRUSBHC_NCC : integer := 1;
constant CFG_GRUSBHC_NPCC : integer := 1;
constant CFG_GRUSBHC_PRR : integer := 0;
constant CFG_GRUSBHC_PR1 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1/4);
constant CFG_GRUSBHC_PR2 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1 mod 4);
constant CFG_GRUSBHC_ENDIAN : integer := 1;
constant CFG_GRUSBHC_BEREGS : integer := 0;
constant CFG_GRUSBHC_BEDESC : integer := 0;
constant CFG_GRUSBHC_BLO : integer := 3;
constant CFG_GRUSBHC_BWRD : integer := 16;
constant CFG_GRUSBHC_UTM : integer := 2;
constant CFG_GRUSBHC_VBUSCONF : integer := 1;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
06a67e84473109707bb805dc3fd60b91
| 0.655659 | 3.481374 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ahb2mig_7series.vhd
| 1 | 28,497 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_7series_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_7series is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_7series is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant maxburst : integer := 8;
constant maxmigcmds : integer := nbrmaxmigcmds(AHBDW);
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_7SERIES, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_7SERIES, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(512*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(64*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(512*maxmigcmds-1 downto 0);
rd_buffer : unsigned(512*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(511 downto 0);
wdf_mask_buffer : std_logic_vector(63 downto 0);
migcommands : integer;
nxt : std_logic;
end record;
type mig_in_type is record
app_addr : std_logic_vector(27 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(511 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(63 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(511 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
signal debug : std_logic := '0';
signal size_to_watch : std_logic_vector(2 downto 0) := HSIZE_4WORD;
component mig is
port (
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
component mig_interface_model is
port (
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig_interface_model;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-3 downto 8)) & "00000"),startaddress'length);
-- Adjust offset in memory buffer
startaddress := resize(startaddress + unsigned(unsigned(ahbsi.haddr(7 downto 6))&"000"),startaddress'length);
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 6))&"000000");
step_offset := resize(unsigned(haddr_offset(7 downto 6)&"0000"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(511 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(1023 downto 512) := unsigned(migout.app_rd_data);
elsif (AHBDW > 64) then
if (r.rd_count = 2) then
v.int_buffer(1535 downto 1024) := unsigned(migout.app_rd_data);
else
v.int_buffer(2047 downto 1536) := unsigned(migout.app_rd_data);
end if;
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit/64bit/128bit to output
v.hrdata := ahbselectdatanoreplicaoutput(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,true);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Check if this was the last transaction
if (r.wr_count >= maxburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= maxburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0';
--v.wdf_mask_buffer := (others => '0'); v.wdf_data_buffer := (others => '0'); v.haddr := (others => '0');
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(27 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(63 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(511 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(127 downto 64);
r.wdf_data_buffer <= r.hwdata_burst(1023 downto 512);
elsif (AHBDW > 64) then
if (r.wr_count = 1) then
r.wdf_mask_buffer <= not r.mask_burst(191 downto 128);
r.wdf_data_buffer <= r.hwdata_burst(1535 downto 1024);
else
r.wdf_mask_buffer <= not r.mask_burst(255 downto 192);
r.wdf_data_buffer <= r.hwdata_burst(2047 downto 1536);
end if;
else
r.wdf_mask_buffer <= not r.mask_burst(127 downto 64);
r.wdf_data_buffer <= r.hwdata_burst(1023 downto 512);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
MCB_inst : mig
port map (
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
MCB_model_inst : mig_interface_model
port map (
-- user interface signals
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
end generate gen_mig_model;
end;
|
gpl-2.0
|
dfb2ead2506fa1a0e6aa6c2236b2877b
| 0.516967 | 3.428417 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/unisim/buffer_unisim.vhd
| 1 | 2,796 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_xilinx
-- File: clkbuf_xilinx.vhd
-- Author: Marko Isomaki, Jiri GAisler - Gaisler Research
-- Description: Clock buffer generator for Xilinx devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
use unisim.BUFG;
-- pragma translate_on
entity clkbuf_xilinx is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal gnd : std_ulogic;
signal x : std_ulogic;
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of x : signal is true;
begin
gnd <= '0';
buf0 : if (buftype = 0) or (buftype > 2) generate
x <= i; o <= x;
end generate;
buf1 : if buftype = 1 generate
buf : bufgmux port map(S => gnd, I0 => i, I1 => gnd, O => o);
end generate;
buf2 : if (buftype = 2) generate
buf : bufg port map(I => i, O => o);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_xilinx is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
|
gpl-2.0
|
e5e0ba5adab74ee35994f9e434eed3e8
| 0.621245 | 3.747989 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbdma.vhd
| 3 | 5,554 |
-- GAISLER_LICENSE
-----------------------------------------------------------------------------
-- Entity: dma
-- File: dma.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple DMA (needs the AHB master interface)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity ahbdma is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 4);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture struct of ahbdma is
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBDMA, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type dma_state_type is (readc, writec);
subtype word32 is std_logic_vector(31 downto 0);
type datavec is array (0 to dbuf-1) of word32;
type reg_type is record
srcaddr : std_logic_vector(31 downto 0);
srcinc : std_logic_vector(1 downto 0);
dstaddr : std_logic_vector(31 downto 0);
dstinc : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
enable : std_logic;
write : std_logic;
inhibit : std_logic;
status : std_logic_vector(1 downto 0);
dstate : dma_state_type;
data : datavec;
cnt : integer range 0 to dbuf-1;
end record;
signal r, rin : reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
begin
comb : process(apbi, dmao, rst, r)
variable v : reg_type;
variable regd : std_logic_vector(31 downto 0); -- data from registers
variable start : std_logic;
variable burst : std_logic;
variable write : std_logic;
variable ready : std_logic;
variable retry : std_logic;
variable mexc : std_logic;
variable irq : std_logic;
variable address : std_logic_vector(31 downto 0); -- DMA address
variable size : std_logic_vector( 1 downto 0); -- DMA transfer size
variable newlen : std_logic_vector(15 downto 0);
variable oldaddr : std_logic_vector(9 downto 0);
variable newaddr : std_logic_vector(9 downto 0);
variable oldsize : std_logic_vector( 1 downto 0);
variable ainc : std_logic_vector( 3 downto 0);
begin
v := r; regd := (others => '0'); burst := '0'; start := '0';
write := '0'; ready := '0'; mexc := '0';
size := r.srcinc; irq := '0'; v.inhibit := '0';
if r.write = '0' then address := r.srcaddr;
else address := r.dstaddr; end if;
newlen := r.len - 1;
if (r.cnt < dbuf-1) or (r.len(9 downto 2) = "11111111") then burst := '1';
else burst := '0'; end if;
start := r.enable;
if dmao.active = '1' then
if r.write = '0' then
if dmao.ready = '1' then
v.data(r.cnt) := ahbreadword(dmao.rdata);
if r.cnt = dbuf-1 then
v.write := '1'; v.cnt := 0; v.inhibit := '1';
address := r.dstaddr; size := r.dstinc;
else v.cnt := r.cnt + 1; end if;
end if;
else
if r.cnt = dbuf-1 then start := '0'; end if;
if dmao.ready = '1' then
if r.cnt = dbuf-1 then v.cnt := 0;
v.write := '0'; v.len := newlen; v.enable := start; irq := start;
else v.cnt := r.cnt + 1; end if;
end if;
end if;
end if;
if r.write = '0' then oldaddr := r.srcaddr(9 downto 0); oldsize := r.srcinc;
else oldaddr := r.dstaddr(9 downto 0); oldsize := r.dstinc; end if;
ainc := decode(oldsize);
newaddr := oldaddr + ainc(3 downto 0);
if (dmao.active and dmao.ready) = '1' then
if r.write = '0' then v.srcaddr(9 downto 0) := newaddr;
else v.dstaddr(9 downto 0) := newaddr; end if;
end if;
-- read DMA registers
case apbi.paddr(3 downto 2) is
when "00" => regd := r.srcaddr;
when "01" => regd := r.dstaddr;
when "10" => regd(20 downto 0) := r.enable & r.srcinc & r.dstinc & r.len;
when others => null;
end case;
-- write DMA registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
v.srcaddr := apbi.pwdata;
when "01" =>
v.dstaddr := apbi.pwdata;
when "10" =>
v.len := apbi.pwdata(15 downto 0);
v.srcinc := apbi.pwdata(17 downto 16);
v.dstinc := apbi.pwdata(19 downto 18);
v.enable := apbi.pwdata(20);
when others => null;
end case;
end if;
if rst = '0' then
v.dstate := readc; v.enable := '0'; v.write := '0';
v.cnt := 0;
end if;
rin <= v;
apbo.prdata <= regd;
dmai.address <= address;
dmai.wdata <= ahbdrivedata(r.data(r.cnt));
dmai.start <= start and not v.inhibit;
dmai.burst <= burst;
dmai.write <= v.write;
dmai.size <= '0' & size;
apbo.pirq <= (others =>'0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
end process;
ahbif : ahbmst generic map (hindex => hindex, devid => 16#26#, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbdma" & tost(pindex) &
": AHB DMA Unit rev " & tost(0) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
gpl-2.0
|
cf3c017dcf46da66887e51c78babb978
| 0.57256 | 3.227193 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/leon4_net.vhd
| 1 | 22,988 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.gencomp.all;
entity leon4_net is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqi_hrdrst: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(63 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
dbgo_ducnt : out std_ulogic);
end ;
architecture rtl of leon4_net is
signal disasen : std_ulogic;
component leon4_ut90nhbd
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk: in std_ulogic;
gclk: in std_ulogic;
hclken: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(127 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(127 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(127 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
disasen : in std_ulogic);
end component;
signal ahbi_hgrant: std_logic_vector(0 to NAHBMST-1);
signal ahbi_hready: std_ulogic;
signal ahbi_hresp: std_logic_vector(1 downto 0);
signal ahbi_hrdata: std_logic_vector(127 downto 0);
signal ahbi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbi_testen: std_ulogic;
signal ahbi_testrst: std_ulogic;
signal ahbi_scanen: std_ulogic;
signal ahbi_testoen: std_ulogic;
signal ahbo_hbusreq: std_ulogic;
signal ahbo_hlock: std_ulogic;
signal ahbo_htrans: std_logic_vector(1 downto 0);
signal ahbo_haddr: std_logic_vector(31 downto 0);
signal ahbo_hwrite: std_ulogic;
signal ahbo_hsize: std_logic_vector(2 downto 0);
signal ahbo_hburst: std_logic_vector(2 downto 0);
signal ahbo_hprot: std_logic_vector(3 downto 0);
signal ahbo_hwdata: std_logic_vector(127 downto 0);
signal ahbo_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbsi_hsel: std_logic_vector(0 to NAHBSLV-1);
signal ahbsi_haddr: std_logic_vector(31 downto 0);
signal ahbsi_hwrite: std_ulogic;
signal ahbsi_htrans: std_logic_vector(1 downto 0);
signal ahbsi_hsize: std_logic_vector(2 downto 0);
signal ahbsi_hburst: std_logic_vector(2 downto 0);
signal ahbsi_hwdata: std_logic_vector(127 downto 0);
signal ahbsi_hprot: std_logic_vector(3 downto 0);
signal ahbsi_hready: std_ulogic;
signal ahbsi_hmaster: std_logic_vector(3 downto 0);
signal ahbsi_hmastlock: std_ulogic;
signal ahbsi_hmbsel: std_logic_vector(0 to NAHBAMR-1);
signal ahbsi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
constant hconfig: ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON4, 0, 0, 0),
others => zero32);
begin
disasen <= '1' when disas /= 0 else '0';
-- Plug&Play information
ahbox.hconfig <= hconfig;
ahbox.hindex <= hindex;
ut09 : if fabtech = ut90 generate
wrp: leon4_ut90nhbd
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize, smp => smp)
port map(
clk => clk,
gclk => gclk,
hclken => hclken,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqi_rstvec => irqi_rstvec,
irqi_iact => irqi_iact,
irqi_index => irqi_index,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
irqo_fpen => irqo_fpen,
irqo_idle => irqo_idle,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer(30 downto 0),
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
dbgo_fcnt => dbgo_fcnt,
dbgo_optype => dbgo_optype,
dbgo_bpmiss => dbgo_bpmiss,
dbgo_istat_cmiss => dbgo_istat_cmiss,
dbgo_istat_tmiss => dbgo_istat_tmiss,
dbgo_istat_chold => dbgo_istat_chold,
dbgo_istat_mhold => dbgo_istat_mhold,
dbgo_dstat_cmiss => dbgo_dstat_cmiss,
dbgo_dstat_tmiss => dbgo_dstat_tmiss,
dbgo_dstat_chold => dbgo_dstat_chold,
dbgo_dstat_mhold => dbgo_dstat_mhold,
dbgo_wbhold => dbgo_wbhold,
dbgo_su => dbgo_su,
disasen => disasen);
dbgo_ducnt <= '1';
end generate;
ahbi_hgrant(0) <= ahbix.hgrant(hindex);
ahbi_hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi_hready <= ahbix.hready;
ahbi_hresp <= ahbix.hresp;
ahbi_hrdata(127 mod AHBDW downto 0) <= ahbix.hrdata(127 mod AHBDW downto 0);
ahbi_hirq <= ahbix.hirq;
ahbi_testen <= ahbix.testen;
ahbi_testrst <= ahbix.testrst;
ahbi_scanen <= ahbix.scanen;
ahbi_testoen <= ahbix.testoen;
ahbox.hbusreq <= ahbo_hbusreq;
ahbox.hlock <= ahbo_hlock;
ahbox.htrans <= ahbo_htrans;
ahbox.haddr <= ahbo_haddr;
ahbox.hwrite <= ahbo_hwrite;
ahbox.hsize <= ahbo_hsize(2 downto 0);
ahbox.hburst <= "00" & ahbo_hburst(0);
ahbox.hprot <= ahbo_hprot;
ahbox.hwdata(127 mod AHBDW downto 0) <= ahbo_hwdata(127 mod AHBDW downto 0);
ahbox.hirq <= (others => '0'); --ahbo_hirq;
ahbsi_hsel <= ahbsix.hsel;
ahbsi_haddr <= ahbsix.haddr;
ahbsi_hwrite <= ahbsix.hwrite;
ahbsi_htrans <= ahbsix.htrans;
ahbsi_hsize <= ahbsix.hsize;
ahbsi_hburst <= ahbsix.hburst;
ahbsi_hwdata(127 mod AHBDW downto 0) <= ahbsix.hwdata(127 mod AHBDW downto 0);
ahbsi_hprot <= ahbsix.hprot;
ahbsi_hready <= ahbsix.hready;
ahbsi_hmaster <= ahbsix.hmaster;
ahbsi_hmastlock <= ahbsix.hmastlock;
ahbsi_hmbsel <= ahbsix.hmbsel;
ahbsi_hirq <= ahbsix.hirq;
-- pragma translate_off
assert NAHBSLV=16
report "LEON4FT netlist: Only NAHBSLV=16 supported by wrapper"
severity Failure;
-- pragma translate_on
end architecture;
|
gpl-2.0
|
9f06970a6effc1ea09643c495537ab95
| 0.51118 | 3.873294 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/allclkgen.vhd
| 1 | 21,570 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allclkgen
-- File: allclkgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock generator interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allclkgen is
component clkgen_virtex2
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_spartan3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex5
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex7
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 25000);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_axcelerator
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_altera_mf
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_cycloneiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_rh_lib18t
generic (
clk_mul : integer := 1;
clk_div : integer := 1);
port (
rst : in std_logic;
clkin : in std_logic;
clk : out std_logic;
sdclk : out std_logic; -- SDRAM clock
clk2x : out std_logic;
clk4x : out std_logic
);
end component;
component clkmul_virtex2
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end component;
component clkand_unisim
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut025crh
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkand_ut90nhbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkrand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_rh_lib18t
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkmux_unisim
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut130hbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut90nhbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_fusion
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_proasic3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_fusion
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3e
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3l
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_rhumc
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_saed32
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_saed32
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_saed32
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_saed32
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_rhs65
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_rhs65
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_rhs65
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_rhs65
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_dare
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_dare
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_rhumc
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_dare
generic (
noclkfb : integer := 1
);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clk8x : out std_logic
);
end component;
component clkgen_easic90
generic (
clk_mul : integer;
clk_div : integer;
freq : integer;
pcisysclk : integer;
pcien : integer);
port (
clkin : in std_ulogic;
pciclkin : in std_ulogic;
clk : out std_ulogic;
clk2x : out std_ulogic;
clk4x : out std_ulogic;
clkn : out std_ulogic;
lock : out std_ulogic);
end component;
component clkmux_dare
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkmux_rhlib18t
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_n2x
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_n2x
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_n2x
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk270en : integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic; -- unscaled 2X clock
clk270 : out std_ulogic -- clk shifted 270 degrees
);
end component;
component clkgen_ut130hbd
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
clk4x : out std_ulogic;
clk8x : out std_ulogic;
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component clkgen_ut90nhbd is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
end;
|
gpl-2.0
|
1d1057f713ef2839258662f7de0938c6
| 0.550487 | 3.344705 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml605/ahbrom.vhd
| 3 | 11,169 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 752;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"1280000A";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE03";
when 16#00069# => romdata <= X"8410A250";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"05000080";
when 16#0006E# => romdata <= X"82100000";
when 16#0006F# => romdata <= X"80A0E000";
when 16#00070# => romdata <= X"02800005";
when 16#00071# => romdata <= X"01000000";
when 16#00072# => romdata <= X"82004002";
when 16#00073# => romdata <= X"10BFFFFC";
when 16#00074# => romdata <= X"8620E001";
when 16#00075# => romdata <= X"3D1003FF";
when 16#00076# => romdata <= X"BC17A3E0";
when 16#00077# => romdata <= X"BC278001";
when 16#00078# => romdata <= X"9C27A060";
when 16#00079# => romdata <= X"03100000";
when 16#0007A# => romdata <= X"07200001";
when 16#0007B# => romdata <= X"8610E200";
when 16#0007C# => romdata <= X"C220E014";
when 16#0007D# => romdata <= X"0500FFC0";
when 16#0007E# => romdata <= X"8410A2FF";
when 16#0007F# => romdata <= X"C420E004";
when 16#00080# => romdata <= X"05000280";
when 16#00081# => romdata <= X"8410A00A";
when 16#00082# => romdata <= X"C420E008";
when 16#00083# => romdata <= X"C420E00C";
when 16#00084# => romdata <= X"050104C0";
when 16#00085# => romdata <= X"8410A313";
when 16#00086# => romdata <= X"C420E004";
when 16#00087# => romdata <= X"84102021";
when 16#00088# => romdata <= X"C420E000";
when 16#00089# => romdata <= X"84102040";
when 16#0008A# => romdata <= X"84A0A001";
when 16#0008B# => romdata <= X"36BFFFFF";
when 16#0008C# => romdata <= X"C4284002";
when 16#0008D# => romdata <= X"84102040";
when 16#0008E# => romdata <= X"84A0A001";
when 16#0008F# => romdata <= X"36BFFFFF";
when 16#00090# => romdata <= X"C6084002";
when 16#00091# => romdata <= X"82006040";
when 16#00092# => romdata <= X"84102040";
when 16#00093# => romdata <= X"84A0A002";
when 16#00094# => romdata <= X"36BFFFFF";
when 16#00095# => romdata <= X"C4304002";
when 16#00096# => romdata <= X"84102040";
when 16#00097# => romdata <= X"84A0A002";
when 16#00098# => romdata <= X"36BFFFFF";
when 16#00099# => romdata <= X"C6104002";
when 16#0009A# => romdata <= X"82006040";
when 16#0009B# => romdata <= X"84102040";
when 16#0009C# => romdata <= X"84A0A004";
when 16#0009D# => romdata <= X"36BFFFFF";
when 16#0009E# => romdata <= X"C4204002";
when 16#0009F# => romdata <= X"84102040";
when 16#000A0# => romdata <= X"84A0A004";
when 16#000A1# => romdata <= X"36BFFFFF";
when 16#000A2# => romdata <= X"C6004002";
when 16#000A3# => romdata <= X"82006040";
when 16#000A4# => romdata <= X"84102040";
when 16#000A5# => romdata <= X"84A0A008";
when 16#000A6# => romdata <= X"36BFFFFF";
when 16#000A7# => romdata <= X"C4384002";
when 16#000A8# => romdata <= X"84102040";
when 16#000A9# => romdata <= X"84A0A008";
when 16#000AA# => romdata <= X"36BFFFFF";
when 16#000AB# => romdata <= X"C8184002";
when 16#000AC# => romdata <= X"10BFFFC9";
when 16#000AD# => romdata <= X"01000000";
when 16#000AE# => romdata <= X"C4004000";
when 16#000AF# => romdata <= X"C4184000";
when 16#000B0# => romdata <= X"C4186010";
when 16#000B1# => romdata <= X"82006020";
when 16#000B2# => romdata <= X"10BFFFF3";
when 16#000B3# => romdata <= X"01000000";
when 16#000B4# => romdata <= X"81C04000";
when 16#000B5# => romdata <= X"01000000";
when 16#000B6# => romdata <= X"01000000";
when 16#000B7# => romdata <= X"01000000";
when 16#000B8# => romdata <= X"00000000";
when 16#000B9# => romdata <= X"00000000";
when 16#000BA# => romdata <= X"00000000";
when 16#000BB# => romdata <= X"00000000";
when 16#000BC# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
8c837e58310e6375dbaee4ec0f004eb3
| 0.582057 | 3.179334 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmutw.vhd
| 1 | 10,764 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutw
-- File: mmutw.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU table-walk logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutw is
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end mmutw;
architecture rtl of mmutw is
type write_buffer_type is record -- write buffer
addr, data : std_logic_vector(31 downto 0);
read : std_logic;
end record;
constant write_buffer_none : write_buffer_type := (
addr => (others => '0'), data => (others => '0'), read => '0');
type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);
type tw_rtype is record
state : states;
wb : write_buffer_type;
req : std_logic;
walk_op : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tw_rtype := (
state => idle,
wb => write_buffer_none,
req => '0',
walk_op => '0');
signal c,r : tw_rtype;
begin
p0: process (rst, r, twi, mcmmo, mmctrl1)
variable v : tw_rtype;
variable finish : std_logic;
variable index : std_logic_vector(31-2 downto 0);
variable lvl : std_logic_vector(1 downto 0);
variable fault_mexc : std_logic;
variable fault_trans : std_logic;
variable fault_inv : std_logic;
variable fault_lvl : std_logic_vector(1 downto 0);
variable pte,ptd,inv,rvd : std_logic;
variable goon, found : std_logic;
variable base : std_logic_vector(31 downto 0);
variable pagesize : integer range 0 to 3;
begin
v := r;
--#init
finish := '0';
index := (others => '0');
lvl := (others => '0');
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_lvl := (others => '0');
pte := '0';ptd := '0';inv := '0';rvd := '0';
goon := '0'; found := '0';
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mcmmo.data(PTD_PTP32_U downto PTD_PTP32_D);
if mcmmo.grant = '1' then
v.req := '0';
end if;
if mcmmo.retry = '1' then v.req := '1'; end if;
-- # pte/ptd
if ((mcmmo.ready and not r.req)= '1') then -- context
case mcmmo.data(PT_ET_U downto PT_ET_D) is
when ET_INV => inv := '1';
when ET_PTD => ptd := '1'; goon := '1';
when ET_PTE => pte := '1'; found := '1';
when ET_RVD => rvd := '1'; null;
when others => null;
end case;
end if;
fault_trans := (rvd);
fault_inv := inv;
pagesize := MMU_getpagesize(mmupgsz,mmctrl1);
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
when others => -- standard 4k tag comparision [ 8 6 6 ]
end case;
-- # state machine
case r.state is
when idle =>
if (twi.walk_op_ur) = '1' then
v.walk_op := '1';
index(M_CTX_SZ-1 downto 0) := mmctrl1.ctx;
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mmctrl1.ctxp(MMCTRL_PTP32_U downto MMCTRL_PTP32_D);
v.wb.addr := base or (index&"00");
v.wb.read := '1';
v.req := '1';
v.state := lv1;
elsif (twi.areq_ur) = '1' then
index := (others => '0');
v.wb.addr := twi.aaddr;
v.wb.data := twi.adata;
v.wb.read := '0';
v.req := '1';
v.state := waitm;
end if;
when waitm =>
if ((mcmmo.ready and not r.req)= '1') then -- amba: result ready current cycle
fault_mexc := mcmmo.mexc;
v.state := idle;
finish := '1';
end if;
when lv1 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_CTX; fault_lvl := FS_L_CTX;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I1_SZ-1 downto 0) := twi.data(P8K_VA_I1_U downto P8K_VA_I1_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I1_SZ-1 downto 0) := twi.data(P16K_VA_I1_U downto P16K_VA_I1_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I1_SZ-1 downto 0) := twi.data(P32K_VA_I1_U downto P32K_VA_I1_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I1_SZ-1 downto 0) := twi.data(VA_I1_U downto VA_I1_D);
end case;
v.state := lv2;
end if;
when lv2 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_REGION; fault_lvl := FS_L_L1;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I2_SZ-1 downto 0) := twi.data(P8K_VA_I2_U downto P8K_VA_I2_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I2_SZ-1 downto 0) := twi.data(P16K_VA_I2_U downto P16K_VA_I2_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I2_SZ-1 downto 0) := twi.data(P32K_VA_I2_U downto P32K_VA_I2_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I2_SZ-1 downto 0) := twi.data(VA_I2_U downto VA_I2_D);
end case;
v.state := lv3;
end if;
when lv3 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_SEGMENT; fault_lvl := FS_L_L2;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I3_SZ-1 downto 0) := twi.data(P8K_VA_I3_U downto P8K_VA_I3_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I3_SZ-1 downto 0) := twi.data(P16K_VA_I3_U downto P16K_VA_I3_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I3_SZ-1 downto 0) := twi.data(P32K_VA_I3_U downto P32K_VA_I3_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I3_SZ-1 downto 0) := twi.data(VA_I3_U downto VA_I3_D);
end case;
v.state := lv4;
end if;
when lv4 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_PAGE; fault_lvl := FS_L_L3;
fault_trans := fault_trans or ptd;
v.state := idle;
finish := '1';
end if;
when others =>
v.state := idle;
finish := '0';
end case;
base := base or (index&"00");
if r.walk_op = '1' then
if (mcmmo.ready and (not r.req)) = '1' then
fault_mexc := mcmmo.mexc;
if (( ptd and
(not fault_mexc ) and
(not fault_trans) and
(not fault_inv )) = '1') then -- tw : break table walk?
v.wb.addr := base;
v.req := '1';
else
v.walk_op := '0';
finish := '1';
v.state := idle;
end if;
end if;
end if;
-- # reset
if (not ASYNC_RESET) and (not RESET_ALL) and ( rst = '0' ) then
v.state := RRES.state;
v.req := RRES.req;
v.walk_op := RRES.walk_op;
v.wb.read := RRES.wb.read;
end if;
--# drive signals
two.finish <= finish;
two.data <= mcmmo.data;
two.addr <= r.wb.addr(31 downto 0);
two.lvl <= lvl;
two.fault_mexc <= fault_mexc;
two.fault_trans <= fault_trans;
two.fault_inv <= fault_inv;
two.fault_lvl <= fault_lvl;
mcmmi.address <= r.wb.addr;
mcmmi.data <= r.wb.data;
mcmmi.burst <= '0';
mcmmi.size <= "10";
mcmmi.read <= r.wb.read;
mcmmi.lock <= '0';
mcmmi.req <= r.req;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
end rtl;
|
gpl-2.0
|
c3dc29c0019e9884f6b8ad6e6d451b82
| 0.48207 | 3.500488 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmuconfig.vhd
| 1 | 22,446 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: mmuconfig
-- File: mmuconfig.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU types and constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
package mmuconfig is
constant M_CTX_SZ : integer := 8;
constant M_ENT_MAX : integer := 64;
constant XM_ENT_MAX_LOG : integer := log2(M_ENT_MAX);
constant M_ENT_MAX_LOG : integer := XM_ENT_MAX_LOG;
type mmu_idcache is (id_icache, id_dcache);
-- ##############################################################
-- 1.0 virtual address [sparc V8: p.243,Appx.H,Figure H-4]
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 24 23 18 17 12 11 0
constant VA_I1_SZ : integer := 8;
constant VA_I2_SZ : integer := 6;
constant VA_I3_SZ : integer := 6;
constant VA_I_SZ : integer := VA_I1_SZ+VA_I2_SZ+VA_I3_SZ;
constant VA_I_MAX : integer := 8;
constant VA_I1_U : integer := 31;
constant VA_I1_D : integer := 32-VA_I1_SZ;
constant VA_I2_U : integer := 31-VA_I1_SZ;
constant VA_I2_D : integer := 32-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_D : integer := 32-VA_I_SZ;
constant VA_I_U : integer := 31;
constant VA_I_D : integer := 32-VA_I_SZ;
constant VA_OFF_U : integer := 31-VA_I_SZ;
constant VA_OFF_D : integer := 0;
constant VA_OFFCTX_U : integer := 31;
constant VA_OFFCTX_D : integer := 0;
constant VA_OFFREG_U : integer := 31-VA_I1_SZ;
constant VA_OFFREG_D : integer := 0;
constant VA_OFFSEG_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_OFFSEG_D : integer := 0;
constant VA_OFFPAG_U : integer := 31-VA_I_SZ;
constant VA_OFFPAG_D : integer := 0;
-- 8k pages
-- 7 6 6 13
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 25 24 19 18 13 12 0
constant P8K_VA_I1_SZ : integer := 7;
constant P8K_VA_I2_SZ : integer := 6;
constant P8K_VA_I3_SZ : integer := 6;
constant P8K_VA_I_SZ : integer := P8K_VA_I1_SZ+P8K_VA_I2_SZ+P8K_VA_I3_SZ;
constant P8K_VA_I_MAX : integer := 7;
constant P8K_VA_I1_U : integer := 31;
constant P8K_VA_I1_D : integer := 32-P8K_VA_I1_SZ;
constant P8K_VA_I2_U : integer := 31-P8K_VA_I1_SZ;
constant P8K_VA_I2_D : integer := 32-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_I3_U : integer := 31-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_I3_D : integer := 32-P8K_VA_I_SZ;
constant P8K_VA_I_U : integer := 31;
constant P8K_VA_I_D : integer := 32-P8K_VA_I_SZ;
constant P8K_VA_OFF_U : integer := 31-P8K_VA_I_SZ;
constant P8K_VA_OFF_D : integer := 0;
constant P8K_VA_OFFCTX_U : integer := 31;
constant P8K_VA_OFFCTX_D : integer := 0;
constant P8K_VA_OFFREG_U : integer := 31-P8K_VA_I1_SZ;
constant P8K_VA_OFFREG_D : integer := 0;
constant P8K_VA_OFFSEG_U : integer := 31-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_OFFSEG_D : integer := 0;
constant P8K_VA_OFFPAG_U : integer := 31-P8K_VA_I_SZ;
constant P8K_VA_OFFPAG_D : integer := 0;
-- 16k pages
-- 6 6 6 14
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 26 25 20 19 14 13 0
constant P16K_VA_I1_SZ : integer := 6;
constant P16K_VA_I2_SZ : integer := 6;
constant P16K_VA_I3_SZ : integer := 6;
constant P16K_VA_I_SZ : integer := P16K_VA_I1_SZ+P16K_VA_I2_SZ+P16K_VA_I3_SZ;
constant P16K_VA_I_MAX : integer := 6;
constant P16K_VA_I1_U : integer := 31;
constant P16K_VA_I1_D : integer := 32-P16K_VA_I1_SZ;
constant P16K_VA_I2_U : integer := 31-P16K_VA_I1_SZ;
constant P16K_VA_I2_D : integer := 32-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_I3_U : integer := 31-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_I3_D : integer := 32-P16K_VA_I_SZ;
constant P16K_VA_I_U : integer := 31;
constant P16K_VA_I_D : integer := 32-P16K_VA_I_SZ;
constant P16K_VA_OFF_U : integer := 31-P16K_VA_I_SZ;
constant P16K_VA_OFF_D : integer := 0;
constant P16K_VA_OFFCTX_U : integer := 31;
constant P16K_VA_OFFCTX_D : integer := 0;
constant P16K_VA_OFFREG_U : integer := 31-P16K_VA_I1_SZ;
constant P16K_VA_OFFREG_D : integer := 0;
constant P16K_VA_OFFSEG_U : integer := 31-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_OFFSEG_D : integer := 0;
constant P16K_VA_OFFPAG_U : integer := 31-P16K_VA_I_SZ;
constant P16K_VA_OFFPAG_D : integer := 0;
-- 32k pages
-- 4 7 6 15
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 28 27 21 20 15 14 0
constant P32K_VA_I1_SZ : integer := 4;
constant P32K_VA_I2_SZ : integer := 7;
constant P32K_VA_I3_SZ : integer := 6;
constant P32K_VA_I_SZ : integer := P32K_VA_I1_SZ+P32K_VA_I2_SZ+P32K_VA_I3_SZ;
constant P32K_VA_I_MAX : integer := 7;
constant P32K_VA_I1_U : integer := 31;
constant P32K_VA_I1_D : integer := 32-P32K_VA_I1_SZ;
constant P32K_VA_I2_U : integer := 31-P32K_VA_I1_SZ;
constant P32K_VA_I2_D : integer := 32-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_I3_U : integer := 31-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_I3_D : integer := 32-P32K_VA_I_SZ;
constant P32K_VA_I_U : integer := 31;
constant P32K_VA_I_D : integer := 32-P32K_VA_I_SZ;
constant P32K_VA_OFF_U : integer := 31-P32K_VA_I_SZ;
constant P32K_VA_OFF_D : integer := 0;
constant P32K_VA_OFFCTX_U : integer := 31;
constant P32K_VA_OFFCTX_D : integer := 0;
constant P32K_VA_OFFREG_U : integer := 31-P32K_VA_I1_SZ;
constant P32K_VA_OFFREG_D : integer := 0;
constant P32K_VA_OFFSEG_U : integer := 31-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_OFFSEG_D : integer := 0;
constant P32K_VA_OFFPAG_U : integer := 31-P32K_VA_I_SZ;
constant P32K_VA_OFFPAG_D : integer := 0;
-- ##############################################################
-- 2.0 PAGE TABE DESCRIPTOR (PTD) [sparc V8: p.247,Appx.H,Figure H-7]
--
-- +-------------------------------------------------+---+---+
-- | Page Table Pointer (PTP) | 0 | 0 |
-- +-------------------------------------------------+---+---+
-- 31 2 1 0
--
-- 2.1 PAGE TABE ENTRY (PTE) [sparc V8: p.247,Appx.H,Figure H-8]
--
-- +-----------------------------+---+---+---+-----------+---+
-- |Physical Page Number (PPN) | C | M | R | ACC | ET|
-- +-----------------------------+---+---+---+-----------+---+
-- 31 8 7 6 5 4 2 1 0
--
constant PTD_PTP_U : integer := 31; -- PTD: page table pointer
constant PTD_PTP_D : integer := 2;
constant PTD_PTP32_U : integer := 27; -- PTD: page table pointer 32 bit
constant PTD_PTP32_D : integer := 2;
constant PTE_PPN_U : integer := 31; -- PTE: physical page number
constant PTE_PPN_D : integer := 8;
constant PTE_PPN_S : integer := (PTE_PPN_U+1)-PTE_PPN_D; -- PTE: pysical page number size
constant PTE_PPN32_U : integer := 27; -- PTE: physical page number 32 bit addr
constant PTE_PPN32_D : integer := 8;
constant PTE_PPN32_S : integer := (PTE_PPN32_U+1)-PTE_PPN32_D; -- PTE: pysical page number 32 bit size
constant PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant PTE_PPN32REG_D : integer := PTE_PPN32_U+1-VA_I1_SZ;
constant PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-VA_I1_SZ-VA_I2_SZ;
constant PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-VA_I_SZ;
-- 8k pages
constant P8K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P8K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P8K_VA_I1_SZ;
constant P8K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P8K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P8K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P8K_VA_I_SZ;
-- 16k pages
constant P16K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P16K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P16K_VA_I1_SZ;
constant P16K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P16K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P16K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P16K_VA_I_SZ;
-- 32k pages
constant P32K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P32K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P32K_VA_I1_SZ;
constant P32K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P32K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P32K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P32K_VA_I_SZ;
constant PTE_C : integer := 7; -- PTE: Cacheable bit
constant PTE_M : integer := 6; -- PTE: Modified bit
constant PTE_R : integer := 5; -- PTE: Reference Bit - a "1" indicates an PTE
constant PTE_ACC_U : integer := 4; -- PTE: Access field
constant PTE_ACC_D : integer := 2;
constant ACC_W : integer := 2; -- PTE::ACC : write permission
constant ACC_E : integer := 3; -- PTE::ACC : exec permission
constant ACC_SU : integer := 4; -- PTE::ACC : privileged
constant PT_ET_U : integer := 1; -- PTD/PTE: PTE Type
constant PT_ET_D : integer := 0;
constant ET_INV : std_logic_vector(1 downto 0) := "00";
constant ET_PTD : std_logic_vector(1 downto 0) := "01";
constant ET_PTE : std_logic_vector(1 downto 0) := "10";
constant ET_RVD : std_logic_vector(1 downto 0) := "11";
constant PADDR_PTD_U : integer := 31;
constant PADDR_PTD_D : integer := 6;
-- ##############################################################
-- 3.0 TLBCAM TAG hardware representation (TTG)
--
type tlbcam_reg is record
ET : std_logic_vector(1 downto 0); -- et field
ACC : std_logic_vector(2 downto 0); -- on flush/probe this will become FPTY
M : std_logic; -- modified
R : std_logic; -- referenced
SU : std_logic; -- equal ACC >= 6
VALID : std_logic;
LVL : std_logic_vector(1 downto 0); -- level in pth
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
PPN : std_logic_vector(PTE_PPN_S-1 downto 0); -- physical page number
C : std_logic; -- cachable
end record;
constant tlbcam_reg_none : tlbcam_reg := ("00", "000", '0', '0', '0', '0',
"00", "00000000", "000000", "000000", "00000000", (others => '0'), '0');
-- tlbcam_reg::LVL
constant LVL_PAGE : std_logic_vector(1 downto 0) := "00"; -- equal tlbcam_tfp::TYP FPTY_PAGE
constant LVL_SEGMENT : std_logic_vector(1 downto 0) := "01"; -- equal tlbcam_tfp::TYP FPTY_SEGMENT
constant LVL_REGION : std_logic_vector(1 downto 0) := "10"; -- equal tlbcam_tfp::TYP FPTY_REGION
constant LVL_CTX : std_logic_vector(1 downto 0) := "11"; -- equal tlbcam_tfp::TYP FPTY_CTX
-- ##############################################################
-- 4.0 TLBCAM tag i/o for translation/flush/(probe)
--
type tlbcam_tfp is record
TYP : std_logic_vector(2 downto 0); -- f/(p) type
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
M : std_logic;
end record;
constant tlbcam_tfp_none : tlbcam_tfp := ("000", "00000000", "000000", "000000", "00000000", '0');
--tlbcam_tfp::TYP
constant FPTY_PAGE : std_logic_vector(2 downto 0) := "000"; -- level 3 PTE match I1+I2+I3
constant FPTY_SEGMENT : std_logic_vector(2 downto 0) := "001"; -- level 2/3 PTE/PTD match I1+I2
constant FPTY_REGION : std_logic_vector(2 downto 0) := "010"; -- level 1/2/3 PTE/PTD match I1
constant FPTY_CTX : std_logic_vector(2 downto 0) := "011"; -- level 0/1/2/3 PTE/PTD ctx
constant FPTY_N : std_logic_vector(2 downto 0) := "100"; -- entire tlb
-- ##############################################################
-- 5.0 MMU Control Register [sparc V8: p.253,Appx.H,Figure H-10]
--
-- +-------+-----+------------------+-----+-------+--+--+
-- | IMPL | VER | SC | PSO | resvd |NF|E |
-- +-------+-----+------------------+-----+-------+--+--+
-- 31 28 27 24 23 8 7 6 2 1 0
--
-- MMU Context Pointer [sparc V8: p.254,Appx.H,Figure H-11]
-- +-------------------------------------------+--------+
-- | Context Table Pointer | resvd |
-- +-------------------------------------------+--------+
-- 31 2 1 0
--
-- MMU Context Number [sparc V8: p.255,Appx.H,Figure H-12]
-- +----------------------------------------------------+
-- | Context Table Pointer |
-- +----------------------------------------------------+
-- 31 0
--
-- fault status/address register [sparc V8: p.256,Appx.H,Table H-13/14]
-- +------------+-----+---+----+----+-----+----+
-- | reserved | EBE | L | AT | FT | FAV | OW |
-- +------------+-----+---+----+----+-----+----+
-- 31 18 17 10 9 8 7 5 4 2 1 0
--
-- +----------------------------------------------------+
-- | fault address register |
-- +----------------------------------------------------+
-- 31 0
constant MMCTRL_CTXP_SZ : integer := 30;
constant MMCTRL_PTP32_U : integer := 25;
constant MMCTRL_PTP32_D : integer := 0;
constant MMCTRL_E : integer := 0;
constant MMCTRL_NF : integer := 1;
constant MMCTRL_PSO : integer := 7;
constant MMCTRL_SC_U : integer := 23;
constant MMCTRL_SC_D : integer := 8;
constant MMCTRL_PGSZ_U : integer := 17;
constant MMCTRL_PGSZ_D : integer := 16;
constant MMCTRL_VER_U : integer := 27;
constant MMCTRL_VER_D : integer := 24;
constant MMCTRL_IMPL_U : integer := 31;
constant MMCTRL_IMPL_D : integer := 28;
constant MMCTRL_TLBDIS : integer := 15;
constant MMCTRL_TLBSEP : integer := 14;
constant MMCTXP_U : integer := 31;
constant MMCTXP_D : integer := 2;
constant MMCTXNR_U : integer := M_CTX_SZ-1;
constant MMCTXNR_D : integer := 0;
constant FS_SZ : integer := 18; -- fault status size
constant FS_EBE_U : integer := 17;
constant FS_EBE_D : integer := 10;
constant FS_L_U : integer := 9;
constant FS_L_D : integer := 8;
constant FS_L_CTX : std_logic_vector(1 downto 0) := "00";
constant FS_L_L1 : std_logic_vector(1 downto 0) := "01";
constant FS_L_L2 : std_logic_vector(1 downto 0) := "10";
constant FS_L_L3 : std_logic_vector(1 downto 0) := "11";
constant FS_AT_U : integer := 7;
constant FS_AT_D : integer := 5;
constant FS_AT_LS : natural := 7; --L=0 S=1
constant FS_AT_ID : natural := 6; --D=0 I=1
constant FS_AT_SU : natural := 5; --U=0 SU=1
constant FS_AT_LUDS : std_logic_vector(2 downto 0) := "000";
constant FS_AT_LSDS : std_logic_vector(2 downto 0) := "001";
constant FS_AT_LUIS : std_logic_vector(2 downto 0) := "010";
constant FS_AT_LSIS : std_logic_vector(2 downto 0) := "011";
constant FS_AT_SUDS : std_logic_vector(2 downto 0) := "100";
constant FS_AT_SSDS : std_logic_vector(2 downto 0) := "101";
constant FS_AT_SUIS : std_logic_vector(2 downto 0) := "110";
constant FS_AT_SSIS : std_logic_vector(2 downto 0) := "111";
constant FS_FT_U : integer := 4;
constant FS_FT_D : integer := 2;
constant FS_FT_NONE : std_logic_vector(2 downto 0) := "000";
constant FS_FT_INV : std_logic_vector(2 downto 0) := "001";
constant FS_FT_PRO : std_logic_vector(2 downto 0) := "010";
constant FS_FT_PRI : std_logic_vector(2 downto 0) := "011";
constant FS_FT_TRANS : std_logic_vector(2 downto 0):= "100";
constant FS_FT_BUS : std_logic_vector(2 downto 0) := "101";
constant FS_FT_INT : std_logic_vector(2 downto 0) := "110";
constant FS_FT_RVD : std_logic_vector(2 downto 0) := "111";
constant FS_FAV : natural := 1;
constant FS_OW : natural := 0;
--# mmu ctrl reg
type mmctrl_type1 is record
e : std_logic; -- enable
nf : std_logic; -- no fault
pso : std_logic; -- partial store order
-- pre : std_logic; -- pretranslation source
-- pri : std_logic; -- i/d priority
pagesize : std_logic_vector(1 downto 0);-- page size
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);-- context nr
ctxp : std_logic_vector(MMCTRL_CTXP_SZ-1 downto 0); -- context table pointer
tlbdis : std_logic; -- tlb disabled
bar : std_logic_vector(1 downto 0); -- preplace barrier
end record;
constant mmctrl_type1_none : mmctrl_type1 := ('0', '0', '0', (others => '0'), (others => '0'), (others => '0'), '0', (others => '0'));
--# fault status reg
type mmctrl_fs_type is record
ow : std_logic;
fav : std_logic;
ft : std_logic_vector(2 downto 0); -- fault type
at_ls : std_logic; -- access type, load/store
at_id : std_logic; -- access type, i/dcache
at_su : std_logic; -- access type, su/user
l : std_logic_vector(1 downto 0); -- level
ebe : std_logic_vector(7 downto 0);
end record;
constant mmctrl_fs_zero : mmctrl_fs_type :=
('0', '0', "000", '0', '0', '0', "00", "00000000");
type mmctrl_type2 is record
fs : mmctrl_fs_type;
valid : std_logic;
fa : std_logic_vector(VA_I_SZ-1 downto 0); -- fault address register
end record;
constant mmctrl2_zero : mmctrl_type2 :=
(mmctrl_fs_zero, '0', zero32(VA_I_SZ-1 downto 0));
-- ##############################################################
-- 6. Virtual Flush/Probe address [sparc V8: p.249,Appx.H,Figure H-9]
-- +---------------------------------------+--------+-------+
-- | VIRTUAL FLUSH&Probe Address (VFPA) | type | rvd |
-- +---------------------------------------+--------+-------+
-- 31 12 11 8 7 0
--
--
subtype FPA is natural range 31 downto 12;
constant FPA_I1_U : integer := 31;
constant FPA_I1_D : integer := 24;
constant FPA_I2_U : integer := 23;
constant FPA_I2_D : integer := 18;
constant FPA_I3_U : integer := 17;
constant FPA_I3_D : integer := 12;
constant FPTY_U : integer := 10; -- only 3 bits
constant FPTY_D : integer := 8;
-- ##############################################################
-- 7. control register virtual address [sparc V8: p.253,Appx.H,Table H-5]
-- +---------------------------------+-----+--------+
-- | | CNR | rsvd |
-- +---------------------------------+-----+--------+
-- 31 10 8 7 0
constant CNR_U : integer := 10;
constant CNR_D : integer := 8;
constant CNR_CTRL : std_logic_vector(2 downto 0) := "000";
constant CNR_CTXP : std_logic_vector(2 downto 0) := "001";
constant CNR_CTX : std_logic_vector(2 downto 0) := "010";
constant CNR_F : std_logic_vector(2 downto 0) := "011";
constant CNR_FADDR : std_logic_vector(2 downto 0) := "100";
-- ##############################################################
-- 8. Precise flush (ASI 0x10-14) [sparc V8: p.266,Appx.I]
-- supported: ASI_FLUSH_PAGE
-- ASI_FLUSH_CTX
constant PFLUSH_PAGE : std_logic := '0';
constant PFLUSH_CTX : std_logic := '1';
-- ##############################################################
-- 9. Diagnostic access
--
constant DIAGF_LVL_U : integer := 1;
constant DIAGF_LVL_D : integer := 0;
constant DIAGF_WR : integer := 3;
constant DIAGF_HIT : integer := 4;
constant DIAGF_CTX_U : integer := 12;
constant DIAGF_CTX_D : integer := 5;
constant DIAGF_VALID : integer := 13;
end mmuconfig;
|
gpl-2.0
|
c3b1d2bd3647cc357da01bbba2d048d1
| 0.522944 | 3.059706 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-clock-gate/config.vhd
| 1 | 8,781 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000017#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 1;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 0;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (12);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
0bc7cf58c5388f81510ba137e90d1080
| 0.652431 | 3.550748 | false | false | false | false |
lunod/lt24_ctrl
|
rtl/cpt_addr_rom.vhd
| 1 | 2,515 |
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity cpt_addr_rom is
port(clk : in std_logic;
resetn : in std_logic;
clr_init_rom_addr: in std_logic;
inc_init_rom_addr: in std_logic;
end_init_rom : out std_logic;
address : out std_logic_vector(6 downto 0));
end entity cpt_addr_rom;
---------------------------------------------------------------------------
architecture rtl of cpt_addr_rom is
constant ROM_SIZE : natural := 101;
signal counter : unsigned(address'range);
begin
update_cpt: process(clk, resetn)
begin
if resetn = '0' then
counter <= (others => '0');
end_init_rom <= '0';
elsif rising_edge(clk) then
if clr_init_rom_addr = '1' then
counter <= (others => '0');
elsif inc_init_rom_addr = '1' then
if counter = rom_size - 1 then
counter <= (others => '0');
else
counter <= counter + 1;
end if; -- counter = rom_size - 1
end if; -- clr_init_rom_addr = '1'
-- DFFs on output signals to minimise critical path
if counter = rom_size - 2 then
end_init_rom <= '1';
else
end_init_rom <= '0';
end if; -- counter = rom_size - 2
end if; -- resetn = '0'
end process update_cpt;
address <= std_logic_vector(counter);
end architecture rtl;
---------------------------------------------------------------------------
|
lgpl-3.0
|
a129079dfa041697614b2e62d3e8a0b2
| 0.534791 | 4.21273 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/opencores/i2c/i2c_master_bit_ctrl.vhd
| 4 | 31,534 |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]):
--
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
-- * Needed to differentiate between slave clock stretching and master
-- clock synchronization.
-- * Added register s_state which contains the next state in case
-- of clock synchronization
-- * Incorporated change in wr_b state from SVN rev. 72 of
-- original OC version (delay check of SDA).
-- * Added 'filter' generic that determines length of filter.
-- Original OC core has a median filter implemented. The solution
-- implemented in this version is a plain shift register with a
-- length determined by the new generic. All samples in this
-- register must be equal, otherwise the SCL or SDA value used by
-- the core will not be changed. Every SCL/SDA transition that is
-- not stable for 'filter' system clock cycles is disregarded.
-- This solution is potentially more vulnerable against short
-- periods of relatively quick fluctuations on the line, however
-- it should do a better job of ignoring 50 ns pulses and still
-- allow us to respond quickly to events on the line - assuming
-- that the core has been correctly configured.
-- Core revision has been increased to 2 (in GRLIB PnP)
-- * Added 'dynfilt' generic to allow dynamic adjustment of the
-- filter. This component takes in a filt vector that is used to
-- reload a filter counter. The filt vector is assigned via the
-- core's APB interface.
-- Reorganized parts of the code, moving signals into blocks.
-- Core revision increased to 3.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state, s_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal fSCL, fSDA : std_logic_vector(1 downto 0); -- Filtered SCL and SDA inputs
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter
signal csync : std_logic; -- Need to synchronize clock with other master
begin
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0' or csync = '1') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
signal slvw_dis : std_logic; -- Slave wait disable;
begin
-- Static filter
staticfilt : if dynfilt = 0 generate
sfblock : block
constant FR : integer := filter; -- Filter range MSb
constant DR : integer := filter + 1; -- Delayed SCL/SDA range MSb
signal sSCL, sSDA : std_logic_vector(FR downto 0); -- synchronized SCL and SDA inputs
signal discl_oen : std_logic_vector(DR downto 0); -- delayed scl_oen signal
signal disda_oen : std_logic_vector(DR downto 0); -- delayed isda_oen
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
else
sSCL <= sSCL(FR-1 downto 0) & scl_i;
sSDA <= sSDA(FR-1 downto 0) & sda_i;
-- Filtering
if andv(sSCL(FR downto 1)) = '1' then
fSCL <= fSCL(0) & '1';
elsif orv(sSCL(FR downto 1)) = '0' then
fSCL <= fSCL(0) & '0';
else
fSCL <= fSCL;
end if;
if andv(sSDA(FR downto 1)) = '1' then
fSDA <= fSDA(0) & '1';
elsif orv(sSDA(FR downto 1)) = '0' then
fSDA <= fSDA(0) & '0';
else
fSDA <= fSDA;
end if;
end if;
end if;
end process synch_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= (others => '1');
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= discl_oen(DR-1 downto 0) & iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen(0);
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(discl_oen(DR downto 1)) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(discl_oen(DR downto 1)) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and disda_oen(DR));
else
ial <= (sda_chk and not fSDA(0) and disda_oen(DR)) or
(sto_condition and not cmd_stop);
end if;
end if;
disda_oen <= disda_oen(DR-1 downto 0) & isda_oen;
end if;
end process gen_al;
end block sfblock;
end generate staticfilt;
-- Dynamic filter
dynamicfilt : if dynfilt /= 0 generate
-- Fixed window
dfblock : block
signal filtcnt : std_logic_vector(filter-1 downto 0);
signal sSCL, sSDA : std_logic_vector(1 downto 0); -- synchronized SCL and SDA inputs
signal fiscl_oen : std_logic_vector(1 downto 0); -- "filtered" scl_oen signal
signal fisda_oen : std_ulogic; -- "filtered" sda_oen signal
signal fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg : std_ulogic;
signal discl_oen : std_ulogic; -- delayed scl_oen signal
signal disda_oen : std_ulogic; -- delayed sda_oen signal
begin
-- Provides filtered signals for SCL and SDA, and corresponding
-- output enable signals.
sync_scl_sda: process(clk, nReset, fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg)
variable scl_chg, sda_chg, iscl_oen_chg, isda_oen_chg : std_ulogic;
begin
--scl_chg := fSCL_chg; sda_chg := fSDA_chg;
--iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (nReset = '0') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
elsif (clk'event and clk = '1') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (rst = '1') or (ena = '0') then
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
else
if (sSCL(1) xor fSCL(0)) = '0' then scl_chg := '0'; end if;
if (sSDA(1) xor fSDA(0)) = '0' then sda_chg := '0'; end if;
if (discl_oen xor fiscl_oen(0)) = '0' then iscl_oen_chg := '0'; end if;
if (disda_oen xor fisda_oen) = '0' then isda_oen_chg := '0'; end if;
if filtcnt = zero32((filter-1)*dynfilt downto 0) then
filtcnt <= filt;
fSCL <= fSCL(0) & (fSCL(0) xor scl_chg);
fSDA <= fSDA(0) & (fSDA(0) xor sda_chg);
fSCL_chg <= '1'; fSDA_chg <= '1';
fiscl_oen <= fiscl_oen(0) & (fiscl_oen(0) xor iscl_oen_chg);
fiscl_oen_chg <= '1';
fisda_oen <= fisda_oen xor isda_oen_chg;
fisda_oen_chg <= '1';
else
filtcnt <= filtcnt - 1;
fSDA <= fSDA; fSCL <= fSCL;
fSCL_chg <= scl_chg; fSDA_chg <= sda_chg;
fiscl_oen <= fiscl_oen;
fiscl_oen_chg <= iscl_oen_chg;
fisda_oen <= fisda_oen;
fisda_oen_chg <= isda_oen_chg;
end if;
end if;
sSCL <= sSCL(0) & scl_i;
sSDA <= sSDA(0) & sda_i;
end if;
end process sync_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= '1';
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen;
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(fiscl_oen) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(fiscl_oen) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_ald: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and fisda_oen);
else
ial <= (sda_chk and not fSDA(0) and fisda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_ald;
end block dfblock;
end generate dynamicfilt;
al <= ial;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if fSCL = "11" and fSDA = "10" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if fSCL = "11" and fSDA = "01" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if fSCL = "01" then
dout <= fSDA(1);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
s_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif csync = '1' then
c_state <= s_state;
else
cmd_ack <= '0'; -- default no acknowledge
-- csync is always '0' here, but including it in the expression
-- appears to let some compilers optimize the design more...
if (clk_en or csync) = '1' then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
s_state <= start_g;
when I2C_CMD_STOP => c_state <= stop_a;
s_state <= stop_d;
when I2C_CMD_WRITE => c_state <= wr_a;
s_state <= wr_d;
when I2C_CMD_READ => c_state <= rd_a;
s_state <= rd_d;
when others => c_state <= idle; -- NOP command
s_state <= idle;
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (allow signals to settle)
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
s_state <= idle;
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
gpl-2.0
|
983582e6a9995b77a13f8344334b0559
| 0.440128 | 4.225379 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaFinal/generic0x.vhd
| 1 | 3,586 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generic0x is
port(
clka:in std_logic;
codop0x: in std_logic_vector ( 3 downto 0 );
PortA0x: in std_logic_vector ( 7 downto 0 );
PortB0x: in std_logic_vector ( 7 downto 0 );
out0x: out std_logic_vector ( 7 downto 0 );
sinFlag0x: in std_logic ;
enable: in std_logic ;
en2: in std_logic ;
outFlag0x: out std_logic );
end;
architecture generic0 of generic0x is
signal sPortA0x , sPortB0x: std_logic_vector(7 downto 0);
begin
pgen0x : process (clka, enable, sinFlag0x)
variable aux: bit:='0';
begin
if (clka'event and clka = '1') then
if (sinFlag0x = '1' or enable ='0') then
sPortA0x <= PortA0x;
sPortB0x <= PortB0x;
outFlag0x <= '0';
elsif (enable = '1') then
case codop0x is
--xor
when "0000" =>
out0x <= sPortA0x xor sPortB0x;
outFlag0x <= '1';
--AND
when "0001" =>
out0x <= sPortA0x and sPortB0x;
outFlag0x <= '1';
--NAND
when "0010" =>
out0x <= not (sPortA0x and sPortB0x);
outFlag0x <= '1';
--NOR
when "0011" =>
out0x <= sPortA0x nor sPortB0x;
outFlag0x <= '1';
--or
when "0100" =>
out0x<= sPortA0x or sPortB0x;
outFlag0x <= '1';
--xnor
when "0101" =>
out0x <= sPortA0x xnor sPortB0x;
outFlag0x <= '1';
--not
when "0110" =>
out0x <= not(sPortA0x);
outFlag0x <= '1';
--com2
when "0111" =>
out0x <= not(sPortA0x) + 1;
outFlag0x <= '1';
--suma
when "1000" =>
out0x <= sPortA0x + sPortB0x;
outFlag0x <= '1';
--resta
when "1001" =>
out0x <= sPortA0x - sPortB0x;
outFlag0x <= '1';
--shiftr
when "1010" =>
if (aux = '0' and en2 = '0') then
aux:='1';
sPortA0x(7) <= '0';
sPortA0x(6 downto 0) <= sPortA0x(7 downto 1);
out0x <= sPortA0x;
outFlag0x <= '1';
elsif (en2 = '1') then
aux:='0';
end if;
--shiftl
when "1011" =>
sPortA0x(0) <= '0';
sPortA0x(7 downto 1) <= sPortA0x(6 downto 0);
out0x <= sPortA0x;
outFlag0x <= '1';
--rotr
when "1100" =>
sPortA0x(7) <= sPortA0x(0);
sPortA0x(6 downto 0) <= sPortA0x(7 downto 1);
out0x <= sPortA0x;
outFlag0x <= '1';
--rotl
when "1101" =>
sPortA0x(0) <= sPortA0x(7);
sPortA0x(7 downto 1) <= sPortA0x(6 downto 0);
out0x <= sPortA0x;
outFlag0x <= '1';
when "1110" =>
if (sPortA0x < sPortB0x) then
out0x <= "00000001";
elsif(sPortA0x = sPortB0x) then
out0x <= "00000010";
elsif(sPortA0x > sPortB0x) then
out0x <= "00000100";
end if;
outFlag0x <= '1';
when others => NULL;
end case;
else
out0x <= (others => 'Z');
outFlag0x <= 'Z';
end if;
end if;
end process pgen0x;
end generic0;
|
apache-2.0
|
b4b2c61e96ab36e738b6c04d11558788
| 0.442833 | 3.277879 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-minimal/ahbrom.vhd
| 6 | 8,961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE05";
when 16#00069# => romdata <= X"8410A25F";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"05248820";
when 16#00077# => romdata <= X"8410A3CD";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000080";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
7f3cb0185482aa8d605be407a8e2660b
| 0.58085 | 3.28844 | false | false | false | false |
lunod/lt24_ctrl
|
rtl/cpt_delay.vhd
| 1 | 2,891 |
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity cpt_delay is
generic(system_frequency: real := 50_000_000.0;
tmin_cycles : natural := 1);
port(clk : in std_logic;
resetn : in std_logic;
clr_cptdelay: in std_logic;
tick_1ms : out std_logic;
tick_10ms : out std_logic;
tick_120ms : out std_logic;
tick_tmin : out std_logic);
end entity cpt_delay;
---------------------------------------------------------------------------
architecture rtl of cpt_delay is
constant t1ms_cycles : natural := integer(system_frequency * 1.0e-3);
constant t10ms_cycles : natural := integer(system_frequency * 10.0e-3);
constant t120ms_cycles: natural := integer(system_frequency * 120.0e-3);
begin
update_cpt: process(clk, resetn)
variable counter : natural range 0 to (t120ms_cycles - 1);
begin
if resetn = '0' then
counter := 0;
tick_tmin <= '0';
tick_1ms <= '0';
tick_10ms <= '0';
tick_120ms <= '0';
elsif rising_edge(clk) then
tick_tmin <= '0';
tick_1ms <= '0';
tick_10ms <= '0';
tick_120ms <= '0';
if counter = t120ms_cycles - 1 then
tick_120ms <= '1';
elsif counter = t10ms_cycles - 1 then
tick_10ms <= '1';
elsif counter = t1ms_cycles - 1 then
tick_1ms <= '1';
elsif counter = tmin_cycles then
tick_tmin <= '1';
else
null;
end if; -- clr_cptdelay = '1'
if (clr_cptdelay = '1') or (counter = t120ms_cycles - 1) then
counter := 0;
else
counter := counter + 1;
end if;
end if; -- resetn = '0'
end process update_cpt;
end architecture rtl;
---------------------------------------------------------------------------
|
lgpl-3.0
|
bd5bfee718504136c26b3458ee443aec
| 0.531996 | 3.965706 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-atlys/testbench.vhd
| 2 | 8,434 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
-- Modified by Aeroflex Gaisler
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0'; -- Reset
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_cke : std_logic;
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
signal ddr_csb : std_ulogic := '0';
signal txd1, rxd1 : std_logic;
signal genio : std_logic_vector(7 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0) := (others => '0');
signal led : std_logic_vector(7 downto 0);
signal button : std_logic_vector(4 downto 0) := (others => '0');
-- Ethernet
signal erx_clk : std_ulogic;
signal erxd : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etx_clk : std_ulogic;
signal etxd : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal egtxclk : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_ulogic;
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
-- SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
signal errorn : std_logic;
begin
-- system clock
clk <= (not clk) after clkperiod * 0.5 ns;
-- reset
rst <= '0', '1' after 2500 ns;
rxd1 <= 'H';
ps2clk <= "HH"; ps2data <= "HH";
-- enable DSU
switch(7) <= '1';
switch(6) <= '0';
cpu : entity work.leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow )
port map (
resetn => rst,
clk => clk,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_odt => ddr_odt,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_dq => ddr_dq,
ddr_rzq => ddr_rzq,
ddr_zio => ddr_zio,
txd1 => txd1,
rxd1 => rxd1,
pmoda => genio,
switch => switch,
led => led,
button => button,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etx_clk => etx_clk,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
erst => open,
egtxclk => egtxclk,
emdc => emdc,
emdio => emdio,
emdint => emdint,
kbd_clk => ps2clk(0),
kbd_data => ps2data(0),
mou_clk => ps2clk(1),
mou_data => ps2data(1),
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
tmdstx_clk_p => open,
tmdstx_clk_n => open,
tmdstx_dat_p => open,
tmdstx_dat_n => open );
prom0 : spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => 16#200000# )
port map (
sck => spi_clk,
di => spi_mosi,
do => spi_miso,
csn => spi_sel_n );
-- NOTE: LEON3 expects DDR2 memory chip with eight banks, but simulation
-- model has only one (implbanks) bank. Therefore other banks will alias
-- to bank 0..
ddr2mem0 : for i in 0 to 0 generate
u1: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (base1000_t_fd => 0, base1000_t_hd => 0, address => 7)
port map (rst, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, egtxclk);
end generate;
-- Monitor error indication.
errorn <= not led(7);
iuerr: process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- Write serial port output to stdout.
--uart0: process
-- constant bit_interval : time := 1 sec / 38400.0;
-- variable d : std_logic_vector(7 downto 0);
-- variable c : character;
-- variable lin : line;
--begin
-- rxc(txd1, d, bit_interval);
-- c := character'val(conv_integer(d));
-- if c = LF then
-- std.textio.writeline(output, lin);
-- elsif c /= CR then
-- std.textio.write(lin, c);
-- end if;
--end process;
end;
|
gpl-2.0
|
4e01e59a3c1745856f83a03b4d732d7c
| 0.55217 | 3.482246 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddr2spa.vhd
| 1 | 8,981 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spa
-- File: ddr2spa.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 16-, 32- or 64-bit DDR2 memory controller module.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.ddrpkg.all;
library techmap;
use techmap.gencomp.all;
entity ddr2spa is
generic (
fabtech : integer := virtex4;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
TRFC : integer := 130;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1; -- 1 added read latency cycle
ddelayb0 : integer := 0; -- Data delay value (0 - 63)
ddelayb1 : integer := 0; -- Data delay value (0 - 63)
ddelayb2 : integer := 0; -- Data delay value (0 - 63)
ddelayb3 : integer := 0; -- Data delay value (0 - 63)
ddelayb4 : integer := 0; -- Data delay value (0 - 63)
ddelayb5 : integer := 0; -- Data delay value (0 - 63)
ddelayb6 : integer := 0; -- Data delay value (0 - 63)
ddelayb7 : integer := 0; -- Data delay value (0 - 63)
cbdelayb0 : integer := 0; -- Data delay value (0 - 63)
cbdelayb1 : integer := 0; -- Data delay value (0 - 63)
cbdelayb2 : integer := 0; -- Data delay value (0 - 63)
cbdelayb3 : integer := 0; -- Data delay value (0 - 63)
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0; -- Disable sync registers at CD crossings
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0; -- single ended DQS
burstlen : integer range 4 to 128 := 8;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
ftbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
nclk : integer range 1 to 3 := 3;
scantest : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_logic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DDR clock
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector(13 downto 0); -- ddr address
ddr_ba : out std_logic_vector(1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector((ddrbits+ftbits)-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
ce : out std_logic -- Corrected error (for FT)
);
end;
architecture rtl of ddr2spa is
constant DDR_FREQ : integer := (clkmul * MHz) / clkdiv;
signal sdi : ddrctrl_in_type;
signal sdo : ddrctrl_out_type;
--signal clkread : std_ulogic;
-- Reset scheme:
-- 1. rst_ddr inport is a raw async reset brought in from the outside - goes to PHY/PLL:s
-- 2. lock signal from PHY/PLLs goes out through lock outport to external
-- ahb rstgen and internal ddr reset gen
-- 3. AMBA synchronous reset signal rst_ahb comes back in
-- DDR Clock scheme:
-- 1. clk_ddr (and clkref200) goes into PHY
-- 2. clkddro comes out from PHY and goes out through clkddro port
-- 3. clkddri comes back in and is used to clock DDR-side logic
signal ilock: std_ulogic;
signal ddr_rst: std_logic;
signal ddr_rst_gen: std_logic_vector(3 downto 0);
constant ddr_syncrst: integer := 0;
begin
lock <= ilock;
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst_ahb); -- Reset signal in DDR clock domain
ddrrstproc: process(clkddri, ilock)
begin
if rising_edge(clkddri) then
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
if ddr_syncrst /= 0 and rst_ahb='0' then
ddr_rst_gen <= "0000";
end if;
end if;
if ddr_syncrst=0 and ilock='0' then
ddr_rst_gen <= "0000";
end if;
end process;
nftphy: if true generate
ddr_phy0 : ddr2phy_wrap_cbd
generic map (
tech => fabtech, MHz => MHz,
dbits => ddrbits, rstdelay => 0, clk_mul => clkmul,
clk_div => clkdiv,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7, cbdelayb0=> cbdelayb0,
cbdelayb1=> cbdelayb1, cbdelayb2=> cbdelayb2,cbdelayb3=> cbdelayb3,
numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
eightbanks => eightbanks, dqsse => dqsse,
chkbits => ftbits*ft, padbits => ftbits*(1-ft),
ctrl2en => 0, resync => 0, custombits => 8,
nclk => nclk, scantest => scantest )
port map (
rst_ddr, clk_ddr, clkref200, clkddro, clkddri, clkddri, ilock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn,
ddr_ad, ddr_ba, ddr_dq, ddr_odt,
open, open, open, open, open,
sdi, sdo, clkddri, "00000000", open,
ahbsi.testen, ahbsi.scanen, ahbsi.testrst, ahbsi.testoen);
end generate;
ddrc : ddr2spax generic map (memtech => memtech, phytech => fabtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask, ddrbits => ddrbits,
pwron => pwron, MHz => DDR_FREQ, TRFC => TRFC, col => col, Mbyte => Mbyte,
readdly => readdly, odten => odten, octen => octen, dqsgating => dqsgating,
nosync => nosync, eightbanks => eightbanks, dqsse => dqsse, burstlen => burstlen, ahbbits => ahbbits,
ft => ft, ddr_syncrst => ddr_syncrst, bigmem => bigmem, raspipe => raspipe, hwidthen => 0, rstdel => rstdel)
port map (ddr_rst, rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo, '0');
ce <= sdo.ce;
end;
|
gpl-2.0
|
e066e5c8129ab69f7bc1d1701dc527d1
| 0.542701 | 3.797463 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica02_Original/topfa4bit00txt.txt.vhd
| 1 | 844 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packagefa4bit00.all;
entity topfa4bit00 is
port(
C00: in std_logic ;
A00: in std_logic ;
B00: in std_logic ;
S00: out std_logic ;
C01: out std_logic );
end;
architecture topfa4bit0 of topfa4bit00 is
signal Sint1, Cint1, Cint2: std_logic;
begin
U3: or00 port map(Ao => Cint2,
Bo => Cint1,
Yo => C01);
U4: topha4bit00 port map(A0 => C00,
B0 => Sint1,
S0 => S00,
C0 => Cint2);
U5: topha4bit00 port map(A0 => A00,
B0 => B00,
S0 => Sint1,
C0 => Cint1);
end topfa4bit0;
|
apache-2.0
|
433bdb30f2d31ad82bd1f39d33d84cba
| 0.473934 | 3.209125 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/opencores/can/can_top.vhd
| 3 | 348,580 |
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_acf
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_acf.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_acf.v,v $
-- Revision 1.10 2005/04/08 13:03:07 igorm
-- In "Extended mode" when dual filter was used and standard frame received,
-- upper nibble of the data was not filtered ok.
--
-- Revision 1.9 2004/05/31 14:46:11 igorm
-- Bit acceptance_filter_mode was inverted.
--
-- Revision 1.8 2004/02/08 14:16:44 mohor
-- Header changed.
--
-- Revision 1.7 2003/07/16 13:41:34 mohor
-- Fixed according to the linter.
--
-- Revision 1.6 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.5 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.4 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.3 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.2 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.1 2003/01/08 02:13:15 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_acf IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END ENTITY can_acf;
ARCHITECTURE RTL OF can_acf IS
SIGNAL match : std_logic;
SIGNAL match_sf_std : std_logic;
SIGNAL match_sf_ext : std_logic;
SIGNAL match_df_std : std_logic;
SIGNAL match_df_ext : std_logic;
SIGNAL id_ok_xhdl1 : std_logic;
BEGIN
id_ok <= id_ok_xhdl1;
-- Working in basic mode. ID match for standard format (11-bit ID).
match <= (((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1)) OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3)) OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5)) OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7)) OR acceptance_mask_0(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using single filter.
match_sf_std <= (((((((((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_2(0)) OR acceptance_mask_2(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_2(1))
OR acceptance_mask_2(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_2(2)) OR acceptance_mask_2(2)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_2(3)) OR acceptance_mask_2(3) OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_2(4))
OR acceptance_mask_2(4) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_2(5)) OR acceptance_mask_2(5) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_2(6))
OR acceptance_mask_2(6) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_2(7)) OR acceptance_mask_2(7) OR no_byte0)) AND (CONV_STD_LOGIC(data1(0) = acceptance_code_3(0))
OR acceptance_mask_3(0) OR no_byte1)) AND (CONV_STD_LOGIC(data1(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte1)) AND (CONV_STD_LOGIC(data1(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte1)) AND (CONV_STD_LOGIC(data1(3) = acceptance_code_3(3)) OR acceptance_mask_3(3) OR no_byte1)) AND (CONV_STD_LOGIC(data1(4) = acceptance_code_3(4))
OR acceptance_mask_3(4) OR no_byte1)) AND (CONV_STD_LOGIC(data1(5) = acceptance_code_3(5)) OR acceptance_mask_3(5) OR no_byte1)) AND (CONV_STD_LOGIC(data1(6) = acceptance_code_3(6))
OR acceptance_mask_3(6) OR no_byte1)) AND (CONV_STD_LOGIC(data1(7) = acceptance_code_3(7)) OR acceptance_mask_3(7) OR no_byte1) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using single filter.
match_sf_ext <= (((((((((((((((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(0)) OR acceptance_mask_2(0))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(11) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(12) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr2 = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(3) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(4) = acceptance_code_3(7))
OR acceptance_mask_3(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using double filter.
match_df_std <= ((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_3(0)) OR acceptance_mask_3(0)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_3(3)) OR acceptance_mask_3(3)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_1(0)) OR acceptance_mask_1(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_1(1))
OR acceptance_mask_1(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_1(2))
OR acceptance_mask_1(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_1(3)) OR acceptance_mask_1(3) OR no_byte0))
OR ((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using double filter.
match_df_ext <= ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) OR ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_3(0)) OR acceptance_mask_3(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_3(1))
OR acceptance_mask_3(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- ID ok signal generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id_ok_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_rx_crc_lim = '1') THEN
-- sample_point is already included in go_rx_crc_lim
IF (extended_mode = '1') THEN
IF (NOT acceptance_filter_mode = '1') THEN
-- dual filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_df_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_df_std ;
END IF;
ELSE
-- single filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_sf_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_sf_std ;
END IF;
END IF;
ELSE
id_ok_xhdl1 <= match ;
END IF;
ELSE
IF ((reset_mode OR go_rx_inter OR go_error_frame) = '1') THEN
-- sample_point is already included in go_rx_inter
id_ok_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_btl
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_btl.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_btl.v,v $
-- Revision 1.30 2004/10/27 18:51:37 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.29 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.28 2004/02/08 14:25:26 mohor
-- Header changed.
--
-- Revision 1.27 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.26 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.25 2003/07/16 13:40:35 mohor
-- Fixed according to the linter.
--
-- Revision 1.24 2003/07/10 15:32:28 mohor
-- Unused signal removed.
--
-- Revision 1.23 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.22 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.21 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.20 2003/06/20 14:51:11 mohor
-- Previous change removed. When resynchronization occurs we go to seg1
-- stage. sync stage does not cause another start of seg1 stage.
--
-- Revision 1.19 2003/06/20 14:28:20 mohor
-- When hard_sync or resync occure we need to go to seg1 segment. Going to
-- sync segment is in that case blocked.
--
-- Revision 1.18 2003/06/17 15:53:33 mohor
-- clk_cnt reduced from [8:0] to [6:0].
--
-- Revision 1.17 2003/06/17 14:32:17 mohor
-- Removed few signals.
--
-- Revision 1.16 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.15 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.14 2003/06/13 14:55:11 mohor
-- Counters width changed.
--
-- Revision 1.13 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.12 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.11 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.10 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.9 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.8 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.6 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.5 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.4 2002/12/26 01:33:05 mohor
-- Tripple sampling supported.
--
-- Revision 1.3 2002/12/25 23:44:16 mohor
-- Commented lines removed.
--
-- Revision 1.2 2002/12/25 14:17:00 mohor
-- Synchronization working.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_btl IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
-- Bus Timing 0 register
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
-- Output signals from this module
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
-- Output from can_bsp module
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END ENTITY can_btl;
ARCHITECTURE RTL OF can_btl IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL clk_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL clk_en : std_logic;
SIGNAL clk_en_q : std_logic;
SIGNAL sync_blocked : std_logic;
SIGNAL hard_sync_blocked : std_logic;
SIGNAL quant_cnt : std_logic_vector(4 DOWNTO 0);
SIGNAL delay : std_logic_vector(3 DOWNTO 0);
SIGNAL sync : std_logic;
SIGNAL seg1 : std_logic;
SIGNAL seg2 : std_logic;
SIGNAL resync_latched : std_logic;
SIGNAL sample : std_logic_vector(1 DOWNTO 0);
SIGNAL tx_next_sp : std_logic;
SIGNAL go_sync : std_logic;
SIGNAL go_seg1 : std_logic;
SIGNAL go_seg2 : std_logic;
SIGNAL preset_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL sync_window : std_logic;
SIGNAL resync : std_logic;
-- when transmitting 0 with positive error delay is set to 0
SIGNAL temp_xhdl6 : std_logic_vector(4 DOWNTO 0);
SIGNAL sample_point_xhdl1 : std_logic;
SIGNAL sampled_bit_xhdl2 : std_logic;
SIGNAL sampled_bit_q_xhdl3 : std_logic;
SIGNAL tx_point_xhdl4 : std_logic;
SIGNAL hard_sync_xhdl5 : std_logic;
signal time_segment1_ext, delay_ext, add_ext: std_logic_vector(4 DOWNTO 0); --##
BEGIN
sample_point <= sample_point_xhdl1;
sampled_bit <= sampled_bit_xhdl2;
sampled_bit_q <= sampled_bit_q_xhdl3;
tx_point <= tx_point_xhdl4;
hard_sync <= hard_sync_xhdl5;
preset_cnt <= (('0' & baud_r_presc) + 1) & "0" ;
hard_sync_xhdl5 <= (((rx_idle OR rx_inter) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT hard_sync_blocked) ;
resync <= ((((NOT rx_idle) AND (NOT rx_inter)) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT sync_blocked) ;
-- Generating general enable signal that defines baud rate.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) >= (preset_cnt - "00000001")) THEN
clk_cnt <= "0000000" ;
ELSE
clk_cnt <= clk_cnt + "0000001" ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) = (preset_cnt - "00000001")) THEN
clk_en <= '1' ;
ELSE
clk_en <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
clk_en_q <= clk_en ;
END IF;
END PROCESS;
-- Changing states
go_sync <= (((clk_en_q AND seg2) AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) AND (NOT hard_sync_xhdl5)) AND (NOT resync) ;
go_seg1 <= clk_en_q AND (sync OR hard_sync_xhdl5 OR ((resync AND seg2) AND sync_window) OR (resync_latched AND sync_window)) ;
--## go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = ( '0' & (time_segment1 + delay)))) ;
go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = add_ext)) ;--##
time_segment1_ext <= '0' & time_segment1; --## fix comparison for max values
delay_ext <= '0' & delay; --##
add_ext <= time_segment1_ext + delay_ext; --##
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
tx_point_xhdl4 <= (NOT tx_point_xhdl4 AND seg2) AND ((clk_en AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) OR ((clk_en OR clk_en_q) AND (resync OR hard_sync_xhdl5))) ; -- When transmitter we should transmit as soon as possible.
END IF;
END PROCESS;
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- SJW is reached
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
resync_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg2) AND (NOT sync_window)) = '1') THEN
resync_latched <= '1' ;
ELSE
IF (go_seg1 = '1') THEN
resync_latched <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Synchronization stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sync <= go_sync ;
END IF;
END IF;
END PROCESS;
-- Seg1 stage/segment (together with propagation segment which is 1 quant long)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg1 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg1 = '1') THEN
seg1 <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
seg1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Seg2 stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg2 = '1') THEN
seg2 <= '1' ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
seg2 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Quant counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
quant_cnt <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_sync OR go_seg1 OR go_seg2) = '1') THEN
quant_cnt <= "00000" ;
ELSE
IF (clk_en_q = '1') THEN
quant_cnt <= quant_cnt + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
--## temp_xhdl6 <= ("0" & ("00" & sync_jump_width + "0001")) WHEN (quant_cnt > "000" & sync_jump_width) ELSE (quant_cnt + "00001");
temp_xhdl6 <= ("0" & (("00" & sync_jump_width) + "0001")) WHEN (quant_cnt > ("000" & sync_jump_width)) ELSE (quant_cnt + "00001");
-- When late edge is detected (in seg1 stage), stage seg1 is prolonged.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delay <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg1) AND (NOT transmitting OR (transmitting AND (tx_next_sp OR (tx AND (NOT rx)))))) = '1') THEN
delay <= temp_xhdl6(3 DOWNTO 0) ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
delay <= "0000" ;
END IF;
END IF;
END IF;
END PROCESS;
-- If early edge appears within this window (in seg2 stage), phase error is fully compensated
--## sync_window <= CONV_STD_LOGIC((time_segment2 - quant_cnt(2 DOWNTO 0)) < ('0' & (sync_jump_width + "01"))) ;
sync_window <= '1' when (time_segment2 - quant_cnt(2 DOWNTO 0)) < (('0' & sync_jump_width) + "01") else '0';
-- Sampling data (memorizing two samples all the time).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sample <= "11";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sample <= sample(0) & rx;
END IF;
END IF;
END PROCESS;
-- When enabled, tripple sampling is done here.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sampled_bit_xhdl2 <= '1';
sampled_bit_q_xhdl3 <= '1';
sample_point_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame = '1') THEN
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
sample_point_xhdl1 <= '0' ;
ELSE
IF ((clk_en_q AND (NOT hard_sync_xhdl5)) = '1') THEN
--## IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = ('0' & (time_segment1 + delay)))) = '1') then
IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = add_ext )) = '1') then --##
sample_point_xhdl1 <= '1' ;
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
IF (triple_sampling = '1') THEN
sampled_bit_xhdl2 <= (sample(0) AND sample(1)) OR (sample(0) AND rx) OR (sample(1) AND rx) ;
ELSE
sampled_bit_xhdl2 <= rx ;
END IF;
-- kc fix
ELSE
sample_point_xhdl1 <= '0' ;
--
END IF;
ELSE
sample_point_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
-- need to synchronize (even when we are a transmitter)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_next_sp <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_overload_frame OR (go_error_frame AND (NOT node_error_passive)) OR go_tx OR send_ack) = '1') THEN
tx_next_sp <= '0' ;
ELSE
IF ((go_error_frame AND node_error_passive) = '1') THEN
tx_next_sp <= '1' ;
ELSE
IF (sample_point_xhdl1 = '1') THEN
tx_next_sp <= tx_next ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking synchronization (can occur only once in a bit time)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync_blocked <= '1' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
IF (resync = '1') THEN
sync_blocked <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking hard synchronization when occurs once or when we are transmitting a msg
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
hard_sync_blocked <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((hard_sync_xhdl5 AND clk_en_q) OR ((((transmitting AND transmitter) OR go_tx) AND tx_point_xhdl4) AND (NOT tx_next))) = '1') THEN
hard_sync_blocked <= '1' ;
ELSE
IF ((go_rx_inter OR (((rx_idle OR rx_inter) AND sample_point_xhdl1) AND sampled_bit_xhdl2)) = '1') THEN
-- When a glitch performed synchronization
hard_sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_fifo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_fifo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- Rev 1.28 rd_info_pointer fix from opencores merged. /Kristoffer
--
-- $Log: can_fifo.v,v $
-- Revision 1.27 2004/11/18 12:39:34 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.26 2004/02/08 14:30:57 mohor
-- Header changed.
--
-- Revision 1.25 2003/10/23 16:52:17 mohor
-- Active high/low problem when Altera devices are used. Bug fixed by
-- Rojhalat Ibrahim.
--
-- Revision 1.24 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.23 2003/09/05 12:46:41 mohor
-- ALTERA_RAM supported.
--
-- Revision 1.22 2003/08/20 09:59:16 mohor
-- Artisan RAM fixed (when not using BIST).
--
-- Revision 1.21 2003/08/14 16:04:52 simons
-- Artisan ram instances added.
--
-- Revision 1.20 2003/07/16 14:00:45 mohor
-- Fixed according to the linter.
--
-- Revision 1.19 2003/07/03 09:30:44 mohor
-- PCI_BIST replaced with CAN_BIST.
--
-- Revision 1.18 2003/06/27 22:14:23 simons
-- Overrun fifo implemented with FFs, because it is not possible to create such a memory.
--
-- Revision 1.17 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.16 2003/06/18 23:03:44 mohor
-- Typo fixed.
--
-- Revision 1.15 2003/06/11 09:37:05 mohor
-- overrun and length_info fifos are initialized at the end of reset.
--
-- Revision 1.14 2003/03/05 15:02:30 mohor
-- Xilinx RAM added.
--
-- Revision 1.13 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.12 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.11 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.10 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.9 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.8 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.7 2003/01/17 17:44:31 mohor
-- Fifo corrected to be synthesizable.
--
-- Revision 1.6 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.5 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.4 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.3 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.2 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.1 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_fifo IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
--------------------------------------------------
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_fifo;
ARCHITECTURE RTL OF can_fifo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
--------------------------------------------------
SIGNAL fifo : xhdl_15;
SIGNAL length_fifo : xhdl_16;
SIGNAL overrun_info : xhdl_17;
SIGNAL rd_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL read_address : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL rd_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_q : std_logic;
SIGNAL len_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL fifo_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL latch_overrun : std_logic;
SIGNAL initialize_memories : std_logic;
SIGNAL length_info : std_logic_vector(3 DOWNTO 0);
SIGNAL write_length_info : std_logic;
SIGNAL fifo_empty : std_logic;
SIGNAL fifo_full : std_logic;
SIGNAL info_full : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL overrun_xhdl2 : std_logic;
SIGNAL info_empty_xhdl3 : std_logic;
SIGNAL info_cnt_xhdl4 : std_logic_vector(6 DOWNTO 0);
SIGNAL data_64x8_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl6 : std_logic;
SIGNAL rden_64x8_xhdl7 : std_logic;
SIGNAL wraddress_64x8_xhdl8 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl9 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl10 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl11 : std_logic;
SIGNAL wraddress_64x4x1_xhdl12 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl13 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl14 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
overrun <= overrun_xhdl2;
info_empty <= info_empty_xhdl3;
info_cnt <= info_cnt_xhdl4;
data_64x8 <= data_64x8_xhdl5;
wren_64x8 <= wren_64x8_xhdl6;
rden_64x8 <= rden_64x8_xhdl7;
wraddress_64x8 <= wraddress_64x8_xhdl8;
rdaddress_64x8 <= rdaddress_64x8_xhdl9;
data_64x4 <= data_64x4_xhdl10;
wren_64x4x1 <= wren_64x4x1_xhdl11;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl12;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl13;
data_64x1 <= data_64x1_xhdl14;
write_length_info <= (NOT wr) AND wr_q ;
-- Delayed write signal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_q <= '0' ;
ELSE
wr_q <= wr ;
END IF;
END IF;
END PROCESS;
-- length counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
len_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
len_cnt <= "0000" ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
len_cnt <= len_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- wr_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((write_length_info AND (NOT info_full)) OR initialize_memories) = '1') THEN
wr_info_pointer <= wr_info_pointer + "000001" ;
ELSE
IF (reset_mode = '1') THEN
wr_info_pointer <= rd_info_pointer ;
END IF;
END IF;
END IF;
END PROCESS;
-- rd_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
-- Fix from opencores rev 1.28
-- IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_info_pointer <= rd_info_pointer + "000001" ;
END IF;
END IF;
END PROCESS;
-- rd_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_pointer <= rd_pointer + ("00" & length_info) ;
END IF;
END IF;
END PROCESS;
-- wr_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_pointer <= rd_pointer ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
wr_pointer <= wr_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- latch_overrun
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
latch_overrun <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
latch_overrun <= '0' ;
ELSE
IF ((wr AND fifo_full) = '1') THEN
latch_overrun <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Counting data in fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
fifo_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
fifo_cnt <= "0000000" ;
ELSE
IF (((wr AND (NOT release_buffer)) AND (NOT fifo_full)) = '1') THEN
fifo_cnt <= fifo_cnt + "0000001" ;
ELSE
IF ((((NOT wr) AND release_buffer) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) ;
ELSE
IF ((((wr AND release_buffer) AND (NOT fifo_full)) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
fifo_full <= CONV_STD_LOGIC(fifo_cnt = "1000000") ;
fifo_empty <= CONV_STD_LOGIC(fifo_cnt = "0000000") ;
-- Counting data in length_fifo and overrun_info fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSE
IF ((write_length_info XOR release_buffer) = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 - "0000001" ;
ELSE
IF ((write_length_info AND (NOT info_full)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
info_full <= CONV_STD_LOGIC(info_cnt_xhdl4 = "1000000") ;
info_empty_xhdl3 <= CONV_STD_LOGIC(info_cnt_xhdl4 = "0000000") ;
-- Selecting which address will be used for reading data from rx fifo
PROCESS (extended_mode, rd_pointer, addr)
VARIABLE read_address_xhdl18 : std_logic_vector(5 DOWNTO 0);
BEGIN
IF (extended_mode = '1') THEN
-- extended mode
read_address_xhdl18 := rd_pointer + (addr - "010000");
ELSE
-- normal mode
read_address_xhdl18 := rd_pointer + (addr - "010100");
END IF;
read_address <= read_address_xhdl18;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
initialize_memories <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (andv(wr_info_pointer) = '1') THEN
initialize_memories <= '0' ;
END IF;
END IF;
END PROCESS;
-- port connections for Ram
--64x8
data_out_xhdl1 <= q_dp_64x8 ;
data_64x8_xhdl5 <= data_in ;
wren_64x8_xhdl6 <= wr AND (NOT fifo_full) ;
rden_64x8_xhdl7 <= fifo_selected ;
wraddress_64x8_xhdl8 <= wr_pointer ;
rdaddress_64x8_xhdl9 <= read_address ;
--64x4
length_info <= q_dp_64x4 ;
data_64x4_xhdl10 <= len_cnt AND NOT initialize_memories & NOT initialize_memories & NOT initialize_memories & NOT initialize_memories ;
wren_64x4x1_xhdl11 <= (write_length_info AND (NOT info_full)) OR initialize_memories ;
wraddress_64x4x1_xhdl12 <= wr_info_pointer ;
rdaddress_64x4x1_xhdl13 <= rd_info_pointer ;
--64x1
overrun_xhdl2 <= q_dp_64x1 ;
data_64x1_xhdl14 <= (latch_overrun OR (wr AND fifo_full)) AND (NOT initialize_memories) ;
-- `ifdef ALTERA_RAM
-- // altera_ram_64x8_sync fifo
-- lpm_ram_dp fifo
-- (
-- .q (data_out),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (data_in),
-- .wren (wr & (~fifo_full)),
-- .rden (fifo_selected),
-- .wraddress (wr_pointer),
-- .rdaddress (read_address)
-- );
-- defparam fifo.lpm_width = 8;
-- defparam fifo.lpm_widthad = 6;
-- defparam fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x4_sync info_fifo
-- lpm_ram_dp info_fifo
-- (
-- .q (length_info),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (len_cnt & {4{~initialize_memories}}),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam info_fifo.lpm_width = 4;
-- defparam info_fifo.lpm_widthad = 6;
-- defparam info_fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x1_sync overrun_fifo
-- lpm_ram_dp overrun_fifo
-- (
-- .q (overrun),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam overrun_fifo.lpm_width = 1;
-- defparam overrun_fifo.lpm_widthad = 6;
-- defparam overrun_fifo.lpm_numwords = 64;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_crc
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_crc.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_crc.v,v $
-- Revision 1.5 2004/02/08 14:25:57 mohor
-- Header changed.
--
-- Revision 1.4 2003/07/16 13:16:51 mohor
-- Fixed according to the linter.
--
-- Revision 1.3 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/01/08 02:10:54 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_crc IS
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END ENTITY can_crc;
ARCHITECTURE RTL OF can_crc IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL crc_next : std_logic;
SIGNAL crc_tmp : std_logic_vector(14 DOWNTO 0);
SIGNAL crc_xhdl1 : std_logic_vector(14 DOWNTO 0);
BEGIN
crc <= crc_xhdl1;
crc_next <= data XOR crc_xhdl1(14) ;
crc_tmp <= crc_xhdl1(13 DOWNTO 0) & '0' ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (initialize = '1') THEN
crc_xhdl1 <= "000000000000000";
ELSE
IF (enable = '1') THEN
IF (crc_next = '1') THEN
crc_xhdl1 <= crc_tmp XOR "100010110011001";
ELSE
crc_xhdl1 <= crc_tmp ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_ibo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_ibo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_ibo.v,v $
-- Revision 1.3 2004/02/08 14:31:44 mohor
-- Header changed.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
-- This module only inverts bit order
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_ibo IS
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_ibo;
ARCHITECTURE RTL OF can_ibo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL do_xhdl1 : std_logic_vector(7 DOWNTO 0);
BEGIN
do <= do_xhdl1;
do_xhdl1(0) <= di(7) ;
do_xhdl1(1) <= di(6) ;
do_xhdl1(2) <= di(5) ;
do_xhdl1(3) <= di(4) ;
do_xhdl1(4) <= di(3) ;
do_xhdl1(5) <= di(2) ;
do_xhdl1(6) <= di(1) ;
do_xhdl1(7) <= di(0) ;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_bsp
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_bsp.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_bsp.v,v $
-- Revision 1.52 2004/11/18 12:39:21 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.51 2004/11/15 18:23:21 igorm
-- When CAN was reset by setting the reset_mode signal in mode register, it
-- was possible that CAN was blocked for a short period of time. Problem
-- occured very rarly.
--
-- Revision 1.50 2004/10/27 18:51:36 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.49 2004/10/25 06:37:51 igorm
-- Arbitration bug fixed.
--
-- Revision 1.48 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.47 2004/02/08 14:24:10 mohor
-- Error counters changed.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 21:14:33 mohor
-- Error counters changed.
--
-- Revision 1.44 2003/09/30 00:55:12 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.43 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.42 2003/08/29 07:01:14 mohor
-- When detecting bus-free, signal bus_free_cnt_en was cleared to zero
-- although the last sampled bit was zero instead of one.
--
-- Revision 1.41 2003/07/18 15:23:31 tadejm
-- Tx and rx length are limited to 8 bytes regardless to the DLC value.
--
-- Revision 1.40 2003/07/16 15:10:17 mohor
-- Fixed according to the linter.
--
-- Revision 1.39 2003/07/16 13:12:46 mohor
-- Fixed according to the linter.
--
-- Revision 1.38 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.37 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.36 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.35 2003/06/27 20:56:12 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.34 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.33 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.32 2003/06/17 14:28:32 mohor
-- Form error was detected when stuff bit occured at the end of crc.
--
-- Revision 1.31 2003/06/16 14:31:29 tadejm
-- Bit stuffing corrected when stuffing comes at the end of the crc.
--
-- Revision 1.30 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.29 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.28 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.27 2003/02/20 00:26:02 mohor
-- When a dominant bit was detected at the third bit of the intermission and
-- node had a message to transmit, bit_stuff error could occur. Fixed.
--
-- Revision 1.26 2003/02/19 23:21:54 mohor
-- When bit error occured while active error flag was transmitted, counter was
-- not incremented.
--
-- Revision 1.25 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.24 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.23 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.22 2003/02/12 14:23:59 mohor
-- abort_tx added. Bit destuff fixed.
--
-- Revision 1.21 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.20 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.19 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.18 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.17 2003/02/04 17:24:41 mohor
-- Backup.
--
-- Revision 1.16 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.15 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.14 2003/01/16 13:36:19 mohor
-- Form error supported. When receiving messages, last bit of the end-of-frame
-- does not generate form error. Receiver goes to the idle mode one bit sooner.
-- (CAN specification ver 2.0, part B, page 57).
--
-- Revision 1.13 2003/01/15 21:59:45 mohor
-- Data is stored to fifo at the end of ack stage.
--
-- Revision 1.12 2003/01/15 21:05:11 mohor
-- CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
--
-- Revision 1.11 2003/01/15 14:40:23 mohor
-- RX state machine fixed to receive "remote request" frames correctly.
-- No data bytes are written to fifo when such frames are received.
--
-- Revision 1.10 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.9 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.8 2003/01/10 17:51:33 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.6 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.5 2003/01/08 13:30:31 mohor
-- Temp version.
--
-- Revision 1.4 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_bsp IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
-- Command register
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic; -- When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
overload_frame : OUT std_logic; -- be send in a row. This is not implemented, yet, because host can not send an overload request.
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: IN std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
-- Error Warning Limit register
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : IN std_logic;
-- Tx Error Counter register
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers -- Tx signal
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
-- Bist -- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_bsp;
ARCHITECTURE RTL OF can_bsp IS
COMPONENT can_acf
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END COMPONENT;
COMPONENT can_crc
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END COMPONENT;
COMPONENT can_fifo
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_ibo
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
------------------------------
SIGNAL reset_mode_q : std_logic;
SIGNAL bit_cnt : std_logic_vector(5 DOWNTO 0);
SIGNAL data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL id : std_logic_vector(28 DOWNTO 0);
SIGNAL bit_stuff_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_tx : std_logic_vector(2 DOWNTO 0);
SIGNAL tx_point_q : std_logic;
SIGNAL rx_id1 : std_logic;
SIGNAL rx_rtr1 : std_logic;
SIGNAL rx_ide : std_logic;
SIGNAL rx_id2 : std_logic;
SIGNAL rx_rtr2 : std_logic;
SIGNAL rx_r1 : std_logic;
SIGNAL rx_r0 : std_logic;
SIGNAL rx_dlc : std_logic;
SIGNAL rx_data : std_logic;
SIGNAL rx_crc : std_logic;
SIGNAL rx_crc_lim : std_logic;
SIGNAL rx_ack : std_logic;
SIGNAL rx_ack_lim : std_logic;
SIGNAL rx_eof : std_logic;
SIGNAL go_early_tx_latched : std_logic;
SIGNAL rtr1 : std_logic;
SIGNAL ide : std_logic;
SIGNAL rtr2 : std_logic;
SIGNAL crc_in : std_logic_vector(14 DOWNTO 0);
SIGNAL tmp_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tmp_fifo : xhdl_46;
SIGNAL write_data_to_tmp_fifo : std_logic;
SIGNAL byte_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_en : std_logic;
SIGNAL crc_enable : std_logic;
SIGNAL eof_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL passive_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_frame : std_logic;
SIGNAL enable_error_cnt2 : std_logic;
SIGNAL error_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL error_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL delayed_dominant_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL enable_overload_cnt2 : std_logic;
SIGNAL overload_frame_blocked : std_logic;
SIGNAL overload_request_cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL overload_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL overload_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL crc_err : std_logic;
SIGNAL arbitration_lost : std_logic;
SIGNAL arbitration_lost_q : std_logic;
SIGNAL read_arbitration_lost_capture_reg_q: std_logic;
signal read_error_code_capture_reg_q : std_logic;
signal reset_error_code_capture_reg : std_logic;
SIGNAL arbitration_cnt_en : std_logic;
SIGNAL arbitration_blocked : std_logic;
SIGNAL tx_q : std_logic;
SIGNAL data_cnt : std_logic_vector(3 DOWNTO 0); -- Counting the data bytes that are written to FIFO
SIGNAL header_cnt : std_logic_vector(2 DOWNTO 0); -- Counting header length
SIGNAL wr_fifo : std_logic; -- Write data and header to 64-byte fifo
SIGNAL data_for_fifo : std_logic_vector(7 DOWNTO 0); -- Multiplexed data that is stored to 64-byte fifo
SIGNAL tx_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL tx_bit : std_logic;
SIGNAL finish_msg : std_logic;
SIGNAL bus_free_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL bus_free_cnt_en : std_logic;
SIGNAL bus_free : std_logic;
SIGNAL waiting_for_bus_free : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL ack_err_latched : std_logic;
SIGNAL bit_err_latched : std_logic;
SIGNAL stuff_err_latched : std_logic;
SIGNAL form_err_latched : std_logic;
SIGNAL rule3_exc1_1 : std_logic;
SIGNAL rule3_exc1_2 : std_logic;
SIGNAL suspend : std_logic;
SIGNAL susp_cnt_en : std_logic;
SIGNAL susp_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_flag_over_latched : std_logic;
SIGNAL error_capture_code_type : std_logic_vector(7 DOWNTO 6);
SIGNAL error_capture_code_blocked : std_logic;
SIGNAL first_compare_bit : std_logic;
SIGNAL error_capture_code_segment : std_logic_vector(4 DOWNTO 0);
SIGNAL error_capture_code_direction : std_logic;
SIGNAL bit_de_stuff : std_logic;
SIGNAL bit_de_stuff_tx : std_logic;
SIGNAL rule5 : std_logic;
-- Rx state machine
SIGNAL go_rx_idle : std_logic;
SIGNAL go_rx_id1 : std_logic;
SIGNAL go_rx_rtr1 : std_logic;
SIGNAL go_rx_ide : std_logic;
SIGNAL go_rx_id2 : std_logic;
SIGNAL go_rx_rtr2 : std_logic;
SIGNAL go_rx_r1 : std_logic;
SIGNAL go_rx_r0 : std_logic;
SIGNAL go_rx_dlc : std_logic;
SIGNAL go_rx_data : std_logic;
SIGNAL go_rx_crc : std_logic;
SIGNAL go_rx_crc_lim : std_logic;
SIGNAL go_rx_ack : std_logic;
SIGNAL go_rx_ack_lim : std_logic;
SIGNAL go_rx_eof : std_logic;
SIGNAL last_bit_of_inter : std_logic;
SIGNAL go_crc_enable : std_logic;
SIGNAL rst_crc_enable : std_logic;
SIGNAL bit_de_stuff_set : std_logic;
SIGNAL bit_de_stuff_reset : std_logic;
SIGNAL go_early_tx : std_logic;
SIGNAL calculated_crc : std_logic_vector(14 DOWNTO 0);
SIGNAL r_calculated_crc : std_logic_vector(15 DOWNTO 0);
SIGNAL remote_rq : std_logic;
SIGNAL limited_data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL form_err : std_logic;
SIGNAL error_frame_ended : std_logic;
SIGNAL overload_frame_ended : std_logic;
SIGNAL bit_err : std_logic;
SIGNAL ack_err : std_logic;
SIGNAL stuff_err : std_logic;
SIGNAL id_ok : std_logic; -- If received ID matches ID set in registers
SIGNAL no_byte0 : std_logic; -- There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
SIGNAL no_byte1 : std_logic; -- There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
SIGNAL header_len : std_logic_vector(2 DOWNTO 0);
SIGNAL storing_header : std_logic;
SIGNAL limited_data_len_minus1 : std_logic_vector(3 DOWNTO 0);
SIGNAL reset_wr_fifo : std_logic;
SIGNAL err : std_logic;
SIGNAL arbitration_field : std_logic;
SIGNAL basic_chain : std_logic_vector(18 DOWNTO 0);
SIGNAL basic_chain_data : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_std : std_logic_vector(18 DOWNTO 0);
SIGNAL extended_chain_ext : std_logic_vector(38 DOWNTO 0);
SIGNAL extended_chain_data_std : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_data_ext : std_logic_vector(63 DOWNTO 0);
SIGNAL rst_tx_pointer : std_logic;
SIGNAL r_tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_12 : std_logic_vector(7 DOWNTO 0);
SIGNAL bit_err_exc1 : std_logic;
SIGNAL bit_err_exc2 : std_logic;
SIGNAL bit_err_exc3 : std_logic;
SIGNAL bit_err_exc4 : std_logic;
SIGNAL bit_err_exc5 : std_logic;
SIGNAL bit_err_exc6 : std_logic;
SIGNAL error_flag_over : std_logic;
SIGNAL overload_flag_over : std_logic;
SIGNAL limited_tx_cnt_ext : std_logic_vector(5 DOWNTO 0);
SIGNAL limited_tx_cnt_std : std_logic_vector(5 DOWNTO 0);
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
SIGNAL temp_xhdl47 : std_logic_vector(3 DOWNTO 0);
-- Instantiation of the RX CRC module
SIGNAL xhdl_49 : std_logic;
-- Mode register
-- Clock Divider register
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for EXTENDED mode
SIGNAL port_xhdl73 : std_logic_vector(7 DOWNTO 0);
SIGNAL port_xhdl74 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl75 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl76 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl77 : std_logic_vector(3 DOWNTO 0);
SIGNAL temp_xhdl78 : std_logic_vector(3 DOWNTO 0); -- - 1 because counter counts from 0
SIGNAL xhdl_106 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl108 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl109 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl110 : boolean;
SIGNAL temp_xhdl111 : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_state_xhdl2 : std_logic;
SIGNAL tx_state_q_xhdl3 : std_logic;
SIGNAL overload_frame_xhdl4 : std_logic;
SIGNAL error_capture_code_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_idle_xhdl6 : std_logic;
SIGNAL transmitting_xhdl7 : std_logic;
SIGNAL transmitter_xhdl8 : std_logic;
SIGNAL go_rx_inter_xhdl9 : std_logic;
SIGNAL not_first_bit_of_inter_xhdl10 : std_logic;
SIGNAL rx_inter_xhdl11 : std_logic;
SIGNAL set_reset_mode_xhdl12 : std_logic;
SIGNAL node_bus_off_xhdl13 : std_logic;
SIGNAL error_status_xhdl14 : std_logic;
SIGNAL rx_err_cnt_xhdl15 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_err_cnt_xhdl16 : std_logic_vector(8 DOWNTO 0);
SIGNAL transmit_status_xhdl17 : std_logic;
SIGNAL receive_status_xhdl18 : std_logic;
SIGNAL tx_successful_xhdl19 : std_logic;
SIGNAL need_to_tx_xhdl20 : std_logic;
SIGNAL overrun_xhdl21 : std_logic;
SIGNAL info_empty_xhdl22 : std_logic;
SIGNAL set_bus_error_irq_xhdl23 : std_logic;
SIGNAL set_arbitration_lost_irq_xhdl24 : std_logic;
SIGNAL arbitration_lost_capture_xhdl25 : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive_xhdl26: std_logic;
SIGNAL node_error_active_xhdl27 : std_logic;
SIGNAL rx_message_counter_xhdl28: std_logic_vector(6 DOWNTO 0);
SIGNAL tx_xhdl29 : std_logic;
SIGNAL tx_next_xhdl30 : std_logic;
SIGNAL bus_off_on_xhdl31 : std_logic;
SIGNAL go_overload_frame_xhdl32 : std_logic;
SIGNAL go_error_frame_xhdl33 : std_logic;
SIGNAL go_tx_xhdl34 : std_logic;
SIGNAL send_ack_xhdl35 : std_logic;
SIGNAL data_64x8_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl37 : std_logic;
SIGNAL rden_64x8_xhdl38 : std_logic;
SIGNAL wraddress_64x8_xhdl39 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl40 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl41 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl42 : std_logic;
SIGNAL wraddress_64x4x1_xhdl43 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl44 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl45 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
tx_state <= tx_state_xhdl2;
tx_state_q <= tx_state_q_xhdl3;
overload_frame <= overload_frame_xhdl4;
error_capture_code <= error_capture_code_xhdl5;
rx_idle <= rx_idle_xhdl6;
transmitting <= transmitting_xhdl7;
transmitter <= transmitter_xhdl8;
go_rx_inter <= go_rx_inter_xhdl9;
not_first_bit_of_inter <= not_first_bit_of_inter_xhdl10;
rx_inter <= rx_inter_xhdl11;
set_reset_mode <= set_reset_mode_xhdl12;
node_bus_off <= node_bus_off_xhdl13;
error_status <= error_status_xhdl14;
rx_err_cnt <= rx_err_cnt_xhdl15;
tx_err_cnt <= tx_err_cnt_xhdl16;
transmit_status <= transmit_status_xhdl17;
receive_status <= receive_status_xhdl18;
tx_successful <= tx_successful_xhdl19;
need_to_tx <= need_to_tx_xhdl20;
overrun <= overrun_xhdl21;
info_empty <= info_empty_xhdl22;
set_bus_error_irq <= set_bus_error_irq_xhdl23;
set_arbitration_lost_irq <= set_arbitration_lost_irq_xhdl24;
arbitration_lost_capture <= arbitration_lost_capture_xhdl25;
node_error_passive <= node_error_passive_xhdl26;
node_error_active <= node_error_active_xhdl27;
rx_message_counter <= rx_message_counter_xhdl28;
tx <= tx_xhdl29;
tx_next <= tx_next_xhdl30;
bus_off_on <= bus_off_on_xhdl31;
go_overload_frame <= go_overload_frame_xhdl32;
go_error_frame <= go_error_frame_xhdl33;
go_tx <= go_tx_xhdl34;
send_ack <= send_ack_xhdl35;
data_64x8 <= data_64x8_xhdl36;
wren_64x8 <= wren_64x8_xhdl37;
rden_64x8 <= rden_64x8_xhdl38;
wraddress_64x8 <= wraddress_64x8_xhdl39;
rdaddress_64x8 <= rdaddress_64x8_xhdl40;
data_64x4 <= data_64x4_xhdl41;
wren_64x4x1 <= wren_64x4x1_xhdl42;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl43;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl44;
data_64x1 <= data_64x1_xhdl45;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl36 <= w_data_64x8 ;
wren_64x8_xhdl37 <= w_wren_64x8 ;
rden_64x8_xhdl38 <= w_rden_64x8 ;
wraddress_64x8_xhdl39 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl40 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl41 <= w_data_64x4 ;
wren_64x4x1_xhdl42 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl43 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl44 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl45 <= w_data_64x1 ;
-- ----------------------
go_rx_idle <= ((sample_point AND sampled_bit) AND last_bit_of_inter) OR (bus_free AND (NOT node_bus_off_xhdl13)) ;
go_rx_id1 <= (sample_point AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_rx_rtr1 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id1) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1010") ;
go_rx_ide <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr1 ;
go_rx_id2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_ide) AND sampled_bit ;
go_rx_rtr2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id2) AND CONV_STD_LOGIC(bit_cnt(4 DOWNTO 0) = "10001") ;
go_rx_r1 <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr2 ;
go_rx_r0 <= ((NOT bit_de_stuff) AND sample_point) AND ((rx_ide AND (NOT sampled_bit)) OR rx_r1) ;
go_rx_dlc <= ((NOT bit_de_stuff) AND sample_point) AND rx_r0 ;
go_rx_data <= (((((NOT bit_de_stuff) AND sample_point) AND rx_dlc) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (sampled_bit OR (orv(data_len(2 DOWNTO 0))))) AND (NOT remote_rq) ;
--## go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC('0' & bit_cnt(5 DOWNTO 0) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC(('0' & bit_cnt(5 DOWNTO 0)) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc_lim <= (((NOT bit_de_stuff) AND sample_point) AND rx_crc) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1110") ;
go_rx_ack <= ((NOT bit_de_stuff) AND sample_point) AND rx_crc_lim ;
go_rx_ack_lim <= sample_point AND rx_ack ;
go_rx_eof <= sample_point AND rx_ack_lim ;
go_rx_inter_xhdl9 <= (((sample_point AND rx_eof) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended) AND (NOT overload_request) ;
go_error_frame_xhdl33 <= form_err OR stuff_err OR bit_err OR ack_err OR (crc_err AND go_rx_eof) ;
error_frame_ended <= CONV_STD_LOGIC(error_cnt2 = "111") AND tx_point ;
overload_frame_ended <= CONV_STD_LOGIC(overload_cnt2 = "111") AND tx_point ;
go_overload_frame_xhdl32 <= (((sample_point AND ((NOT sampled_bit) OR overload_request)) AND (((rx_eof AND (NOT transmitter_xhdl8)) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended)) OR (((sample_point AND (NOT sampled_bit)) AND rx_inter_xhdl11) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) < "10")) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt2 = "111") OR (overload_cnt2 = "111")))) AND (NOT overload_frame_blocked) ;
go_crc_enable <= hard_sync OR go_tx_xhdl34 ;
rst_crc_enable <= go_rx_crc ;
bit_de_stuff_set <= go_rx_id1 AND (NOT go_error_frame_xhdl33) ;
bit_de_stuff_reset <= go_rx_ack OR reset_mode OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 ;
remote_rq <= ((NOT ide) AND rtr1) OR (ide AND rtr2) ;
temp_xhdl47 <= data_len WHEN (data_len < "1000") ELSE "1000";
limited_data_len <= temp_xhdl47 ;
ack_err <= (((rx_ack AND sample_point) AND sampled_bit) AND tx_state_xhdl2) AND (NOT self_test_mode) ;
bit_err <= ((((((((tx_state_xhdl2 OR error_frame OR overload_frame_xhdl4 OR rx_ack) AND sample_point) AND CONV_STD_LOGIC(tx_xhdl29 /= sampled_bit)) AND (NOT bit_err_exc1)) AND (NOT bit_err_exc2)) AND (NOT bit_err_exc3)) AND (NOT bit_err_exc4)) AND (NOT bit_err_exc5)) AND (NOT bit_err_exc6) ;
bit_err_exc1 <= (tx_state_xhdl2 AND arbitration_field) AND tx_xhdl29 ;
bit_err_exc2 <= rx_ack AND tx_xhdl29 ;
bit_err_exc3 <= (error_frame AND node_error_passive_xhdl26) AND CONV_STD_LOGIC(error_cnt1 < "111") ;
bit_err_exc4 <= ((error_frame AND CONV_STD_LOGIC(error_cnt1 = "111")) AND (NOT enable_error_cnt2)) OR ((overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2)) ;
bit_err_exc5 <= (error_frame AND CONV_STD_LOGIC(error_cnt2 = "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt2 = "111")) ;
bit_err_exc6 <= (CONV_STD_LOGIC(eof_cnt = "110") AND rx_eof) AND (NOT transmitter_xhdl8) ;
arbitration_field <= rx_id1 OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 ;
last_bit_of_inter <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "10") ;
not_first_bit_of_inter_xhdl10 <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) /= "00") ;
-- Rx idle state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_idle_xhdl6 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_id1 OR go_error_frame_xhdl33) = '1') THEN
rx_idle_xhdl6 <= '0' ;
ELSE
IF (go_rx_idle = '1') THEN
rx_idle_xhdl6 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr1 OR go_error_frame_xhdl33) = '1') THEN
rx_id1 <= '0' ;
ELSE
IF (go_rx_id1 = '1') THEN
rx_id1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ide OR go_error_frame_xhdl33) = '1') THEN
rx_rtr1 <= '0' ;
ELSE
IF (go_rx_rtr1 = '1') THEN
rx_rtr1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ide state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_rx_id2 OR go_error_frame_xhdl33) = '1') THEN
rx_ide <= '0' ;
ELSE
IF (go_rx_ide = '1') THEN
rx_ide <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr2 OR go_error_frame_xhdl33) = '1') THEN
rx_id2 <= '0' ;
ELSE
IF (go_rx_id2 = '1') THEN
rx_id2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r1 OR go_error_frame_xhdl33) = '1') THEN
rx_rtr2 <= '0' ;
ELSE
IF (go_rx_rtr2 = '1') THEN
rx_rtr2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_error_frame_xhdl33) = '1') THEN
rx_r1 <= '0' ;
ELSE
IF (go_rx_r1 = '1') THEN
rx_r1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r0 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_dlc OR go_error_frame_xhdl33) = '1') THEN
rx_r0 <= '0' ;
ELSE
IF (go_rx_r0 = '1') THEN
rx_r0 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx dlc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_dlc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_data OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_dlc <= '0' ;
ELSE
IF (go_rx_dlc = '1') THEN
rx_dlc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx data state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_data <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_data <= '0' ;
ELSE
IF (go_rx_data = '1') THEN
rx_data <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc_lim OR go_error_frame_xhdl33) = '1') THEN
rx_crc <= '0' ;
ELSE
IF (go_rx_crc = '1') THEN
rx_crc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack OR go_error_frame_xhdl33) = '1') THEN
rx_crc_lim <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
rx_crc_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack_lim OR go_error_frame_xhdl33) = '1') THEN
rx_ack <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
rx_ack <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_eof OR go_error_frame_xhdl33) = '1') THEN
rx_ack_lim <= '0' ;
ELSE
IF (go_rx_ack_lim = '1') THEN
rx_ack_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx eof state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_eof <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
rx_eof <= '0' ;
ELSE
IF (go_rx_eof = '1') THEN
rx_eof <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Interframe space
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_inter_xhdl11 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_idle OR go_rx_id1 OR go_overload_frame_xhdl32 OR go_error_frame_xhdl33) = '1') THEN
rx_inter_xhdl11 <= '0' ;
ELSE
IF (go_rx_inter_xhdl9 = '1') THEN
rx_inter_xhdl11 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- ID register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id <= "00000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
id <= "00000000000000000000000000000";
ELSE
IF (((sample_point AND (rx_id1 OR rx_id2)) AND (NOT bit_de_stuff)) = '1') THEN
id <= id(27 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr1 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr1 <= '0';
ELSE
IF (((sample_point AND rx_rtr1) AND (NOT bit_de_stuff)) = '1') THEN
rtr1 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr2 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr2 <= '0';
ELSE
IF (((sample_point AND rx_rtr2) AND (NOT bit_de_stuff)) = '1') THEN
rtr2 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- ide bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
ide <= '0';
ELSE
IF (((sample_point AND rx_ide) AND (NOT bit_de_stuff)) = '1') THEN
ide <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data length
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_len <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
data_len <= "0000";
ELSE
IF (((sample_point AND rx_dlc) AND (NOT bit_de_stuff)) = '1') THEN
data_len <= data_len(2 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tmp_data <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tmp_data <= "00000000";
ELSE
IF (((sample_point AND rx_data) AND (NOT bit_de_stuff)) = '1') THEN
tmp_data <= tmp_data(6 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSE
IF ((((sample_point AND rx_data) AND (NOT bit_de_stuff)) AND (andv(bit_cnt(2 DOWNTO 0)))) = '1') THEN
write_data_to_tmp_fifo <= '1' ;
ELSE
write_data_to_tmp_fifo <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
byte_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
byte_cnt <= "000";
ELSE
IF (write_data_to_tmp_fifo = '1') THEN
byte_cnt <= byte_cnt + "001" ;
ELSE
--## IF ((sample_point AND go_rx_crc_lim) = '1') THEN
IF (((sample_point AND go_rx_crc_lim) or rx_dlc) = '1') then --## OpenCores: byte count when recovering from error frame
byte_cnt <= "000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (write_data_to_tmp_fifo = '1') THEN
tmp_fifo(conv_integer(byte_cnt)) <= tmp_data ;
END IF;
END IF;
END PROCESS;
-- CRC
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_in <= "000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
crc_in <= "000000000000000";
ELSE
IF (((sample_point AND rx_crc) AND (NOT bit_de_stuff)) = '1') THEN
crc_in <= crc_in(13 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_cnt <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_cnt <= "000000";
ELSE
IF ((go_rx_id1 OR go_rx_id2 OR go_rx_dlc OR go_rx_data OR go_rx_crc OR go_rx_ack OR go_rx_eof OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
bit_cnt <= "000000" ;
ELSE
IF ((sample_point AND (NOT bit_de_stuff)) = '1') THEN
bit_cnt <= bit_cnt + "000001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- eof_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
eof_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
eof_cnt <= "000";
ELSE
IF (sample_point = '1') THEN
IF ((go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
eof_cnt <= "000" ;
ELSE
IF (rx_eof = '1') THEN
eof_cnt <= eof_cnt + "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Enabling bit de-stuffing
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_en <= '0';
ELSE
IF (bit_de_stuff_set = '1') THEN
bit_stuff_cnt_en <= '1' ;
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt <= "001" ;
ELSE
IF ((sample_point AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt = "101") THEN
bit_stuff_cnt <= "001" ;
ELSE
IF (sampled_bit = sampled_bit_q) THEN
bit_stuff_cnt <= bit_stuff_cnt + "001" ;
ELSE
bit_stuff_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt_tx
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF ((tx_point_q AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt_tx = "101") THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF (tx_xhdl29 = tx_q) THEN
bit_stuff_cnt_tx <= bit_stuff_cnt_tx + "001" ;
ELSE
bit_stuff_cnt_tx <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bit_de_stuff <= CONV_STD_LOGIC(bit_stuff_cnt = "101") ;
bit_de_stuff_tx <= CONV_STD_LOGIC(bit_stuff_cnt_tx = "101") ;
-- stuff_err
stuff_err <= ((sample_point AND bit_stuff_cnt_en) AND bit_de_stuff) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q) ;
-- Generating delayed signals
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
reset_mode_q <= '0' ;
node_bus_off_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
reset_mode_q <= reset_mode ;
node_bus_off_q <= node_bus_off_xhdl13 ;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_enable <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR rst_crc_enable) = '1') THEN
crc_enable <= '0' ;
ELSE
IF (go_crc_enable = '1') THEN
crc_enable <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- CRC error generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_err <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended) = '1') THEN
crc_err <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
crc_err <= CONV_STD_LOGIC(crc_in /= calculated_crc) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Conditions for form error
form_err <= sample_point AND ((((NOT bit_de_stuff) AND rx_crc_lim) AND (NOT sampled_bit)) OR (rx_ack_lim AND (NOT sampled_bit)) OR (((CONV_STD_LOGIC(eof_cnt < "110") AND rx_eof) AND (NOT sampled_bit)) AND (NOT transmitter_xhdl8)) OR (((rx_eof) AND (NOT sampled_bit)) AND transmitter_xhdl8)) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ack_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
ack_err_latched <= '0' ;
ELSE
IF (ack_err = '1') THEN
ack_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
bit_err_latched <= '0' ;
ELSE
IF (bit_err = '1') THEN
bit_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 5 (Fault confinement).
rule5 <= bit_err AND ((((NOT node_error_passive_xhdl26) AND error_frame) AND CONV_STD_LOGIC(error_cnt1 < "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 < "111"))) ;
-- Rule 3 exception 1 - first part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_flag_over OR rule3_exc1_2) = '1') THEN
rule3_exc1_1 <= '0' ;
ELSE
IF (((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err) = '1') THEN
rule3_exc1_1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 3 exception 1 - second part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR rule3_exc1_2) = '1') THEN
rule3_exc1_2 <= '0' ;
ELSE
IF ((((rule3_exc1_1 AND CONV_STD_LOGIC(error_cnt1 < "111")) AND sample_point) AND (NOT sampled_bit)) = '1') THEN
rule3_exc1_2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
stuff_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
stuff_err_latched <= '0' ;
ELSE
IF (stuff_err = '1') THEN
stuff_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
form_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
form_err_latched <= '0' ;
ELSE
IF (form_err = '1') THEN
form_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
xhdl_49 <= ((crc_enable AND sample_point) AND (NOT bit_de_stuff));
i_can_crc_rx : can_crc
PORT MAP (
clk => clk,
data => sampled_bit,
enable => xhdl_49,
initialize => go_crc_enable,
crc => calculated_crc);
no_byte0 <= rtr1 OR CONV_STD_LOGIC(data_len < "0001") ;
no_byte1 <= rtr1 OR CONV_STD_LOGIC(data_len < "0010") ;
port_xhdl73 <= tmp_fifo(0);
port_xhdl74 <= tmp_fifo(1);
i_can_acf : can_acf
PORT MAP (
clk => clk,
rst => rst,
id => id,
reset_mode => reset_mode,
acceptance_filter_mode => acceptance_filter_mode,
extended_mode => extended_mode,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
go_rx_crc_lim => go_rx_crc_lim,
go_rx_inter => go_rx_inter_xhdl9,
go_error_frame => go_error_frame_xhdl33,
data0 => port_xhdl73,
data1 => port_xhdl74,
rtr1 => rtr1,
rtr2 => rtr2,
ide => ide,
no_byte0 => no_byte0,
no_byte1 => no_byte1,
id_ok => id_ok);
temp_xhdl75 <= "101" WHEN ide = '1' ELSE "011";
temp_xhdl76 <= (temp_xhdl75) WHEN extended_mode = '1' ELSE "010";
header_len(2 DOWNTO 0) <= temp_xhdl76 ;
storing_header <= CONV_STD_LOGIC(header_cnt < header_len) ;
temp_xhdl77 <= (data_len - "0001") WHEN (data_len < "1000") ELSE "0111";
temp_xhdl78 <= "1111" WHEN remote_rq = '1' ELSE (temp_xhdl77);
limited_data_len_minus1(3 DOWNTO 0) <= temp_xhdl78 ;
reset_wr_fifo <= CONV_STD_LOGIC(data_cnt = (limited_data_len_minus1 + ('0' & header_len))) OR reset_mode ;
err <= form_err OR stuff_err OR bit_err OR ack_err OR form_err_latched OR stuff_err_latched OR bit_err_latched OR ack_err_latched OR crc_err ;
-- Write enable signal for 64-byte rx fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
wr_fifo <= '0' ;
ELSE
IF ((((go_rx_inter_xhdl9 AND id_ok) AND (NOT error_frame_ended)) AND ((NOT tx_state_xhdl2) OR self_rx_request)) = '1') THEN
wr_fifo <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Header counter. Header length depends on the mode of operation and frame format.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
header_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
header_cnt <= "000" ;
ELSE
IF ((wr_fifo AND storing_header) = '1') THEN
header_cnt <= header_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data counter. Length of the data is limited to 8 bytes.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
data_cnt <= "0000" ;
ELSE
IF (wr_fifo = '1') THEN
data_cnt <= data_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
PROCESS (extended_mode, ide, data_cnt, header_cnt, header_len, storing_header, id, rtr1, rtr2, data_len, tmp_fifo)
VARIABLE data_for_fifo_xhdl79 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl80 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl80 := storing_header & extended_mode & ide & header_cnt;
IF (std_match(temp_xhdl80, "111000")) THEN
data_for_fifo_xhdl79 := '1' & rtr2 & "00" & data_len; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111001")) THEN
data_for_fifo_xhdl79 := id(28 DOWNTO 21); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111010")) THEN
data_for_fifo_xhdl79 := id(20 DOWNTO 13); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111011")) THEN
data_for_fifo_xhdl79 := id(12 DOWNTO 5); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111100")) THEN
data_for_fifo_xhdl79 := id(4 DOWNTO 0) & rtr2 & "00"; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "110000")) THEN
data_for_fifo_xhdl79 := '0' & rtr1 & "00" & data_len; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110001")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110010")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & "0000"; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "10-000")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- normal mode header
ELSIF (std_match(temp_xhdl80, "10-001")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & data_len; -- normal mode header
ELSE
data_for_fifo_xhdl79 := tmp_fifo(conv_integer(data_cnt - ('0' & header_len)) mod 8); -- data
END IF;
data_for_fifo <= data_for_fifo_xhdl79;
END PROCESS;
-- Instantiation of the RX fifo module
-- port connections for Ram
--64x8
--64x4
--64x1
i_can_fifo : can_fifo
PORT MAP (
clk => clk,
rst => rst,
wr => wr_fifo,
data_in => data_for_fifo,
addr => addr(5 DOWNTO 0),
data_out => data_out_xhdl1,
fifo_selected => fifo_selected,
reset_mode => reset_mode,
release_buffer => release_buffer,
extended_mode => extended_mode,
overrun => overrun_xhdl21,
info_empty => info_empty_xhdl22,
info_cnt => rx_message_counter_xhdl28,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Transmitting error frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_frame <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
error_frame <= '0' ;
ELSE
IF (go_error_frame_xhdl33 = '1') THEN
error_frame <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt1 <= "000" ;
ELSE
IF (((error_frame AND tx_point) AND CONV_STD_LOGIC(error_cnt1 < "111")) = '1') THEN
error_cnt1 <= error_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
error_flag_over <= ((((NOT node_error_passive_xhdl26) AND sample_point) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR ((node_error_passive_xhdl26 AND sample_point) AND CONV_STD_LOGIC(passive_cnt = "110"))) AND (NOT enable_error_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_flag_over_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_flag_over_latched <= '0' ;
ELSE
IF (error_flag_over = '1') THEN
error_flag_over_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_error_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_error_cnt2 <= '0' ;
ELSE
IF ((error_frame AND (error_flag_over AND sampled_bit)) = '1') THEN
enable_error_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt2 <= "000" ;
ELSE
IF ((enable_error_cnt2 AND tx_point) = '1') THEN
error_cnt2 <= error_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delayed_dominant_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR enable_error_cnt2 OR go_error_frame_xhdl33 OR enable_overload_cnt2 OR go_overload_frame_xhdl32) = '1') THEN
delayed_dominant_cnt <= "000" ;
ELSE
IF (((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt1 = "111") OR (overload_cnt1 = "111"))) = '1') THEN
delayed_dominant_cnt <= delayed_dominant_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- passive_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
passive_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR first_compare_bit) = '1') THEN
passive_cnt <= "001" ;
ELSE
IF ((sample_point AND CONV_STD_LOGIC(passive_cnt < "110")) = '1') THEN
IF (((error_frame AND (NOT enable_error_cnt2)) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q)) = '1') THEN
passive_cnt <= passive_cnt + "001" ;
ELSE
passive_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- When comparing 6 equal bits, first is always equal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
first_compare_bit <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame_xhdl33 = '1') THEN
first_compare_bit <= '1' ;
ELSE
IF (sample_point = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Transmitting overload frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33) = '1') THEN
overload_frame_xhdl4 <= '0' ;
ELSE
IF (go_overload_frame_xhdl32 = '1') THEN
overload_frame_xhdl4 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt1 <= "000" ;
ELSE
IF (((overload_frame_xhdl4 AND tx_point) AND CONV_STD_LOGIC(overload_cnt1 < "111")) = '1') THEN
overload_cnt1 <= overload_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
overload_flag_over <= (sample_point AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_overload_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_overload_cnt2 <= '0' ;
ELSE
IF ((overload_frame_xhdl4 AND (overload_flag_over AND sampled_bit)) = '1') THEN
enable_overload_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt2 <= "000" ;
ELSE
IF ((enable_overload_cnt2 AND tx_point) = '1') THEN
overload_cnt2 <= overload_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_request_cnt <= "00";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_request_cnt <= "00" ;
ELSE
IF ((overload_request AND overload_frame_xhdl4) = '1') THEN
overload_request_cnt <= overload_request_cnt + "01" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_frame_blocked <= '0' ;
ELSE
IF (((overload_request AND overload_frame_xhdl4) AND CONV_STD_LOGIC(overload_request_cnt = "10")) = '1') THEN
-- This is a second sequential overload_request
overload_frame_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
send_ack_xhdl35 <= (((NOT tx_state_xhdl2) AND rx_ack) AND (NOT err)) AND (NOT listen_only_mode) ;
PROCESS (reset_mode, node_bus_off_xhdl13, tx_state_xhdl2, go_tx_xhdl34, bit_de_stuff_tx, tx_bit, tx_q, send_ack_xhdl35, go_overload_frame_xhdl32, overload_frame_xhdl4, overload_cnt1, go_error_frame_xhdl33, error_frame, error_cnt1, node_error_passive_xhdl26)
VARIABLE tx_next_xhdl30_xhdl105 : std_logic;
BEGIN
IF ((reset_mode OR node_bus_off_xhdl13) = '1') THEN
-- Reset or node_bus_off
tx_next_xhdl30_xhdl105 := '1';
ELSE
IF ((go_error_frame_xhdl33 OR error_frame) = '1') THEN
-- Transmitting error frame
IF (error_cnt1 < "110") THEN
IF (node_error_passive_xhdl26 = '1') THEN
tx_next_xhdl30_xhdl105 := '1';
ELSE
tx_next_xhdl30_xhdl105 := '0';
END IF;
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_overload_frame_xhdl32 OR overload_frame_xhdl4) = '1') THEN
-- Transmitting overload frame
IF (overload_cnt1 < "110") THEN
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_tx_xhdl34 OR tx_state_xhdl2) = '1') THEN
-- Transmitting message
tx_next_xhdl30_xhdl105 := ((NOT bit_de_stuff_tx) AND tx_bit) OR (bit_de_stuff_tx AND (NOT tx_q));
ELSE
IF (send_ack_xhdl35 = '1') THEN
-- Acknowledge
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
END IF;
END IF;
END IF;
END IF;
tx_next_xhdl30 <= tx_next_xhdl30_xhdl105;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_xhdl29 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_xhdl29 <= '1';
ELSE
IF (tx_point = '1') THEN
tx_xhdl29 <= tx_next_xhdl30 ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_q <= '0' ;
ELSE
IF (tx_point = '1') THEN
tx_q <= tx_xhdl29 AND (NOT go_early_tx_latched) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Delayed tx point
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_point_q <= '0' ;
ELSE
tx_point_q <= tx_point ;
END IF;
END IF;
END PROCESS;
-- Changing bit order from [7:0] to [0:7]
i_ibo_tx_data_0 : can_ibo
PORT MAP (
di => tx_data_0,
do => r_tx_data_0);
i_ibo_tx_data_1 : can_ibo
PORT MAP (
di => tx_data_1,
do => r_tx_data_1);
i_ibo_tx_data_2 : can_ibo
PORT MAP (
di => tx_data_2,
do => r_tx_data_2);
i_ibo_tx_data_3 : can_ibo
PORT MAP (
di => tx_data_3,
do => r_tx_data_3);
i_ibo_tx_data_4 : can_ibo
PORT MAP (
di => tx_data_4,
do => r_tx_data_4);
i_ibo_tx_data_5 : can_ibo
PORT MAP (
di => tx_data_5,
do => r_tx_data_5);
i_ibo_tx_data_6 : can_ibo
PORT MAP (
di => tx_data_6,
do => r_tx_data_6);
i_ibo_tx_data_7 : can_ibo
PORT MAP (
di => tx_data_7,
do => r_tx_data_7);
i_ibo_tx_data_8 : can_ibo
PORT MAP (
di => tx_data_8,
do => r_tx_data_8);
i_ibo_tx_data_9 : can_ibo
PORT MAP (
di => tx_data_9,
do => r_tx_data_9);
i_ibo_tx_data_10 : can_ibo
PORT MAP (
di => tx_data_10,
do => r_tx_data_10);
i_ibo_tx_data_11 : can_ibo
PORT MAP (
di => tx_data_11,
do => r_tx_data_11);
i_ibo_tx_data_12 : can_ibo
PORT MAP (
di => tx_data_12,
do => r_tx_data_12);
-- Changing bit order from [14:0] to [0:14]
i_calculated_crc0 : can_ibo
PORT MAP (
di => calculated_crc(14 DOWNTO 7),
do => r_calculated_crc(7 DOWNTO 0));
xhdl_106 <= calculated_crc(6 DOWNTO 0) & '0';
i_calculated_crc1 : can_ibo
PORT MAP (
di => xhdl_106,
do => r_calculated_crc(15 DOWNTO 8));
basic_chain <= r_tx_data_1(7 DOWNTO 4) & "00" & r_tx_data_1(3 DOWNTO 0) & r_tx_data_0(7 DOWNTO 0) & '0' ;
basic_chain_data <= r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 & r_tx_data_2 ;
extended_chain_std <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_ext <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_4(4 DOWNTO 0) & r_tx_data_3(7 DOWNTO 0) & r_tx_data_2(7 DOWNTO 3) & '1' & '1' & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_data_std <= r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 ;
extended_chain_data_ext <= r_tx_data_12 & r_tx_data_11 & r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 ;
PROCESS (extended_mode, rx_data, tx_pointer, extended_chain_data_std, extended_chain_data_ext, rx_crc, r_calculated_crc, r_tx_data_0, extended_chain_ext, extended_chain_std, basic_chain_data, basic_chain, finish_msg)
VARIABLE tx_bit_xhdl107 : std_logic;
BEGIN
IF (extended_mode = '1') THEN
IF (rx_data = '1') THEN
-- data stage
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_data_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_data_std(conv_integer(tx_pointer));
END IF;
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer(3 downto 0)));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_std(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
ELSE
-- Basic mode
IF (rx_data = '1') THEN
-- data stage
tx_bit_xhdl107 := basic_chain_data(conv_integer(tx_pointer));
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
tx_bit_xhdl107 := basic_chain(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
tx_bit <= tx_bit_xhdl107;
END PROCESS;
temp_xhdl108 <= "111111" WHEN tx_data_0(3) = '1' ELSE ((tx_data_0(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_ext <= temp_xhdl108 ;
temp_xhdl109 <= "111111" WHEN tx_data_1(3) = '1' ELSE ((tx_data_1(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_std <= temp_xhdl109 ;
-- arbitration + control for extended format
-- arbitration + control for extended format
-- arbitration + control for standard format
-- data (overflow is OK here)
-- data (overflow is OK here)
-- crc
-- at the end
rst_tx_pointer <= ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND r_tx_data_0(0)) AND CONV_STD_LOGIC(tx_pointer = "100110")) OR ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND (NOT r_tx_data_0(0))) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND extended_mode) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_ext)) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_std)) OR (tx_point AND rx_crc_lim) OR (go_rx_idle) OR (reset_mode) OR (overload_frame_xhdl4) OR (error_frame) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_tx_pointer = '1') THEN
tx_pointer <= "000000" ;
ELSE
IF ((go_early_tx OR ((tx_point AND (tx_state_xhdl2 OR go_tx_xhdl34)) AND (NOT bit_de_stuff_tx))) = '1') THEN
tx_pointer <= tx_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
tx_successful_xhdl19 <= ((((transmitter_xhdl8 AND go_rx_inter_xhdl9) AND (NOT go_error_frame_xhdl33)) AND (NOT error_frame_ended)) AND (NOT overload_frame_ended)) AND (NOT arbitration_lost) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
need_to_tx_xhdl20 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((tx_successful_xhdl19 OR reset_mode OR (abort_tx AND (NOT transmitting_xhdl7)) OR (((NOT tx_state_xhdl2) AND tx_state_q_xhdl3) AND single_shot_transmission)) = '1') THEN
need_to_tx_xhdl20 <= '0' ;
ELSE
IF ((tx_request AND sample_point) = '1') THEN
need_to_tx_xhdl20 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
go_early_tx <= ((((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR CONV_STD_LOGIC(susp_cnt = "111"))) AND sample_point) AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_tx_xhdl34 <= ((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111")))) AND (go_early_tx OR rx_idle_xhdl6) ;
-- go_early_tx latched (for proper bit_de_stuff generation)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
go_early_tx_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR tx_point) = '1') THEN
go_early_tx_latched <= '0' ;
ELSE
IF (go_early_tx = '1') THEN
go_early_tx_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Tx state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_xhdl2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR error_frame OR arbitration_lost) = '1') THEN
tx_state_xhdl2 <= '0' ;
ELSE
IF (go_tx_xhdl34 = '1') THEN
tx_state_xhdl2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSE
tx_state_q_xhdl3 <= tx_state_xhdl2 ;
END IF;
END IF;
END PROCESS;
-- Node is a transmitter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitter_xhdl8 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_tx_xhdl34 = '1') THEN
transmitter_xhdl8 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (suspend AND go_rx_id1)) = '1') THEN
transmitter_xhdl8 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
-- Node might be both transmitter or receiver (sending error or overload frame)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitting_xhdl7 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR go_tx_xhdl34 OR send_ack_xhdl35) = '1') THEN
transmitting_xhdl7 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (go_rx_id1 AND (NOT tx_state_xhdl2)) OR (arbitration_lost AND tx_state_xhdl2)) = '1') THEN
transmitting_xhdl7 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
suspend <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
suspend <= '0' ;
ELSE
IF (((not_first_bit_of_inter_xhdl10 AND transmitter_xhdl8) AND node_error_passive_xhdl26) = '1') THEN
suspend <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt_en <= '0' ;
ELSE
IF (((suspend AND sample_point) AND last_bit_of_inter) = '1') THEN
susp_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt <= "000" ;
ELSE
IF ((susp_cnt_en AND sample_point) = '1') THEN
susp_cnt <= susp_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
finish_msg <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR go_rx_id1 OR error_frame OR reset_mode) = '1') THEN
finish_msg <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
finish_msg <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR error_frame_ended OR reset_mode) = '1') THEN
arbitration_lost <= '0' ;
ELSE
IF (((((transmitter_xhdl8 AND sample_point) AND tx_xhdl29) AND arbitration_field) AND NOT sampled_bit) = '1') THEN
arbitration_lost <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_q <= '0' ;
read_arbitration_lost_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
arbitration_lost_q <= '0';
read_arbitration_lost_capture_reg_q <= '0';
ELSE
arbitration_lost_q <= arbitration_lost;
read_arbitration_lost_capture_reg_q <= read_arbitration_lost_capture_reg ;
END IF;
END IF;
END PROCESS;
set_arbitration_lost_irq_xhdl24 <= (arbitration_lost AND (NOT arbitration_lost_q)) AND (NOT arbitration_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
read_error_code_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
read_error_code_capture_reg_q <= read_error_code_capture_reg;
END IF;
END PROCESS;
reset_error_code_capture_reg <= read_error_code_capture_reg_q and not read_error_code_capture_reg;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR arbitration_blocked) = '1') THEN
arbitration_cnt_en <= '0' ;
ELSE
IF (((rx_id1 AND sample_point) AND (NOT arbitration_blocked)) = '1') THEN
arbitration_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR read_arbitration_lost_capture_reg) = '1') THEN
arbitration_blocked <= '0' ;
ELSE
IF (set_arbitration_lost_irq_xhdl24 = '1') THEN
arbitration_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_arbitration_lost_capture_reg_q = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000" ;
ELSE
IF ((((sample_point AND (NOT arbitration_blocked)) AND arbitration_cnt_en) AND (NOT bit_de_stuff)) = '1') THEN
arbitration_lost_capture_xhdl25 <= arbitration_lost_capture_xhdl25 + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_err_cnt_xhdl15 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((we_rx_err_cnt AND (NOT node_bus_off_xhdl13)) = '1') THEN
rx_err_cnt_xhdl15 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
rx_err_cnt_xhdl15 <= "000000000" ;
ELSE
IF (((NOT listen_only_mode) AND (NOT transmitter_xhdl8 OR arbitration_lost)) = '1') THEN
IF ((((go_rx_ack_lim AND (NOT go_error_frame_xhdl33)) AND (NOT crc_err)) AND CONV_STD_LOGIC(rx_err_cnt_xhdl15 > "000000000")) = '1') THEN
IF (rx_err_cnt_xhdl15 > "001111111") THEN
rx_err_cnt_xhdl15 <= "001111111" ;
ELSE
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 - "000000001" ;
END IF;
ELSE
IF (rx_err_cnt_xhdl15 < "010000000") THEN
IF ((go_error_frame_xhdl33 AND (NOT rule5)) = '1') THEN
-- 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000000001" ;
ELSE
IF ((((((error_flag_over AND (NOT error_flag_over_latched)) AND sample_point) AND (NOT sampled_bit)) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111"))) = '1') THEN
-- 2
-- 5
-- 6
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_err_cnt_xhdl16 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we_tx_err_cnt = '1') THEN
tx_err_cnt_xhdl16 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
tx_err_cnt_xhdl16 <= "010000000" ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 > "000000000") AND (tx_successful_xhdl19 OR bus_free)) = '1') THEN
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 - "000000001" ;
ELSE
IF ((transmitter_xhdl8 AND (NOT arbitration_lost)) = '1') THEN
IF ((((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((go_error_frame_xhdl33 AND (NOT ((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err))) AND (NOT (((((transmitter_xhdl8 AND stuff_err) AND arbitration_field) AND sample_point) AND tx_xhdl29) AND (NOT sampled_bit)))) OR (error_frame AND rule3_exc1_2)) = '1') THEN
-- 6
-- 4 (rule 5 is the same as rule 4)
-- 3
-- 3
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_error_passive_xhdl26 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((rx_err_cnt_xhdl15 < "010000000") AND (tx_err_cnt_xhdl16 < "010000000")) THEN
node_error_passive_xhdl26 <= '0' ;
ELSE
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 >= "010000000") OR (tx_err_cnt_xhdl16 >= "010000000")) AND (error_frame_ended OR go_error_frame_xhdl33 OR ((NOT reset_mode) AND reset_mode_q))) AND (NOT node_bus_off_xhdl13)) = '1') THEN
node_error_passive_xhdl26 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
node_error_active_xhdl27 <= NOT (node_error_passive_xhdl26 OR node_bus_off_xhdl13) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_bus_off_xhdl13 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 = "000000000") AND (tx_err_cnt_xhdl16 = "000000000")) AND (NOT reset_mode)) OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in < "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '0' ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 >= "100000000") OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in = "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free_cnt <= "0000" ;
ELSE
IF (sample_point = '1') THEN
IF (((sampled_bit AND bus_free_cnt_en) AND CONV_STD_LOGIC(bus_free_cnt < "1010")) = '1') THEN
bus_free_cnt <= bus_free_cnt + "0001" ;
ELSE
bus_free_cnt <= "0000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
bus_free_cnt_en <= '1' ;
ELSE
IF ((((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) AND (NOT node_bus_off_xhdl13)) = '1') THEN
bus_free_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free <= '0';
ELSE
IF (((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) = '1') THEN
bus_free <= '1' ;
ELSE
bus_free <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
waiting_for_bus_free <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
waiting_for_bus_free <= '1';
ELSE
IF ((bus_free AND (NOT node_bus_off_xhdl13)) = '1') THEN
waiting_for_bus_free <= '0' ;
ELSE
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
waiting_for_bus_free <= '1' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bus_off_on_xhdl31 <= NOT node_bus_off_xhdl13 ;
set_reset_mode_xhdl12 <= node_bus_off_xhdl13 AND (NOT node_bus_off_q) ;
--## temp_xhdl110 <= ((rx_err_cnt_xhdl15 >= ('0' & error_warning_limit)) OR (tx_err_cnt_xhdl16 >= ('0' & error_warning_limit))) WHEN extended_mode = '1' ELSE ((rx_err_cnt_xhdl15 >= "001100000") OR (tx_err_cnt_xhdl16 >= "001100000"));
temp_xhdl110 <= ((rx_err_cnt_xhdl15 >= ('0' & error_warning_limit)) OR (tx_err_cnt_xhdl16 >= ('0' & error_warning_limit)) or (node_bus_off_xhdl13='1')) WHEN extended_mode = '1' ELSE ((rx_err_cnt_xhdl15 >= "001100000") OR (tx_err_cnt_xhdl16 >= "001100000") or (node_bus_off_xhdl13='1')); --## OpenCores: Error in recovery from BUSOFF
error_status_xhdl14 <= CONV_STD_LOGIC(temp_xhdl110) ;
transmit_status_xhdl17 <= transmitting_xhdl7 OR (extended_mode AND waiting_for_bus_free) ;
temp_xhdl111 <= (waiting_for_bus_free OR ((NOT rx_idle_xhdl6) AND (NOT transmitting_xhdl7))) WHEN extended_mode = '1' ELSE (((NOT waiting_for_bus_free) AND (NOT rx_idle_xhdl6)) AND (NOT transmitting_xhdl7));
receive_status_xhdl18 <= temp_xhdl111 ;
-- Error code capture register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_xhdl5 <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_error_code_capture_reg = '1') THEN
error_capture_code_xhdl5 <= "00000000" ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_xhdl5 <= error_capture_code_type(7 DOWNTO 6) & error_capture_code_direction & error_capture_code_segment(4 DOWNTO 0) ;
END IF;
END IF;
END IF;
END PROCESS;
error_capture_code_segment(0) <= rx_idle_xhdl6 OR rx_ide OR (rx_id2 AND CONV_STD_LOGIC(bit_cnt < "001101")) OR rx_r1 OR rx_r0 OR rx_dlc OR rx_ack OR rx_ack_lim OR (error_frame AND node_error_active_xhdl27) ;
error_capture_code_segment(1) <= rx_idle_xhdl6 OR rx_id1 OR rx_id2 OR rx_dlc OR rx_data OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR (error_frame AND node_error_passive_xhdl26) ;
error_capture_code_segment(2) <= (rx_id1 AND CONV_STD_LOGIC(bit_cnt > "000111")) OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 OR rx_r1 OR (error_frame AND node_error_passive_xhdl26) OR overload_frame_xhdl4 ;
error_capture_code_segment(3) <= (rx_id2 AND CONV_STD_LOGIC(bit_cnt > "000100")) OR rx_rtr2 OR rx_r1 OR rx_r0 OR rx_dlc OR rx_data OR rx_crc OR rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR overload_frame_xhdl4 ;
error_capture_code_segment(4) <= rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR error_frame OR overload_frame_xhdl4 ;
error_capture_code_direction <= NOT transmitting_xhdl7 ;
PROCESS (bit_err, form_err, stuff_err)
VARIABLE error_capture_code_type_xhdl112 : std_logic_vector(7 DOWNTO 6);
BEGIN
IF (bit_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "00";
ELSE
IF (form_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "01";
ELSE
IF (stuff_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "10";
ELSE
error_capture_code_type_xhdl112(7 DOWNTO 6) := "11";
END IF;
END IF;
END IF;
error_capture_code_type <= error_capture_code_type_xhdl112;
END PROCESS;
set_bus_error_irq_xhdl23 <= go_error_frame_xhdl33 AND (NOT error_capture_code_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_error_code_capture_reg = '1') THEN
error_capture_code_blocked <= '0' ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register.v,v $
-- Revision 1.7 2004/02/08 14:32:31 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_register IS
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END ENTITY can_register;
ARCHITECTURE RTL OF can_register IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn.v,v $
-- Revision 1.7 2004/02/08 14:33:19 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END ENTITY can_register_asyn;
ARCHITECTURE RTL OF can_register_asyn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
-- asynchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn_syn.v,v $
-- Revision 1.7 2004/02/08 14:33:59 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:52:43 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_asyn_syn;
ARCHITECTURE RTL OF can_register_asyn_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_syn.v,v $
-- Revision 1.5 2004/02/08 14:34:40 mohor
-- Header changed.
--
-- Revision 1.4 2003/03/11 16:31:58 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_syn;
ARCHITECTURE RTL OF can_register_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, 8);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_registers
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_registers.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
-- Revision 1.36 2005/03/18 15:04:05 igorm
-- Wake-up interrupt was generated in some cases.
--
-- Revision 1.35 2004/11/30 15:08:26 igorm
-- irq is cleared after the release_buffer command. This bug was entered with
-- changes for the edge triggered interrupts.
--
-- Revision 1.34 2004/11/18 12:39:43 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.33 2004/10/25 11:44:38 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.32 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.31 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.30 2003/07/16 15:19:34 mohor
-- Fixed according to the linter.
-- Case statement for data_out joined.
--
-- Revision 1.29 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.28 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.27 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.26 2003/06/22 01:33:14 mohor
-- clkout is clk/2 after the reset.
--
-- Revision 1.25 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.24 2003/06/09 11:22:54 mohor
-- data_out is already registered in the can_top.v file.
--
-- Revision 1.23 2003/04/15 15:31:24 mohor
-- Some features are supported in extended mode only (listen_only_mode...).
--
-- Revision 1.22 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.20 2003/03/11 16:31:05 mohor
-- Mux used for clkout to avoid "gated clocks warning".
--
-- Revision 1.19 2003/03/10 17:34:25 mohor
-- Doubled declarations removed.
--
-- Revision 1.18 2003/03/01 22:52:11 mohor
-- Data is latched on read.
--
-- Revision 1.17 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.16 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.15 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.14 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.13 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.12 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.11 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.6 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.5 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.4 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_registers IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
-- Mode register
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
-- Command register
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: OUT std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
-- Error Warning Limit register
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : OUT std_logic;
-- Tx Error Counter register
we_tx_err_cnt : OUT std_logic;
-- Clock Divider register
extended_mode : OUT std_logic;
clkout : OUT std_logic;
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_registers;
ARCHITECTURE RTL OF can_registers IS
CONSTANT xhdl_timescale : time := 1 ns;
COMPONENT can_register
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn_syn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END COMPONENT;
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
signal read_irq_reg_q : std_logic;
signal reset_irq_reg : std_logic;
SIGNAL tx_successful_q : std_logic;
SIGNAL overrun_q : std_logic;
SIGNAL overrun_status : std_logic;
SIGNAL transmission_complete : std_logic;
SIGNAL transmit_buffer_status_q : std_logic;
SIGNAL receive_buffer_status : std_logic;
SIGNAL error_status_q : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL node_error_passive_q : std_logic;
SIGNAL transmit_buffer_status : std_logic;
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL data_overrun_irq_en : std_logic;
SIGNAL error_warning_irq_en : std_logic;
SIGNAL transmit_irq_en : std_logic;
SIGNAL receive_irq_en : std_logic;
SIGNAL irq_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL irq : std_logic;
SIGNAL we_mode : std_logic;
SIGNAL we_command : std_logic;
SIGNAL we_bus_timing_0 : std_logic;
SIGNAL we_bus_timing_1 : std_logic;
SIGNAL we_clock_divider_low : std_logic;
SIGNAL we_clock_divider_hi : std_logic;
SIGNAL read : std_logic;
SIGNAL read_irq_reg : std_logic;
-- This section is for BASIC and EXTENDED mode
SIGNAL we_acceptance_code_0 : std_logic;
SIGNAL we_acceptance_mask_0 : std_logic;
SIGNAL we_tx_data_0 : std_logic;
SIGNAL we_tx_data_1 : std_logic;
SIGNAL we_tx_data_2 : std_logic;
SIGNAL we_tx_data_3 : std_logic;
SIGNAL we_tx_data_4 : std_logic;
SIGNAL we_tx_data_5 : std_logic;
SIGNAL we_tx_data_6 : std_logic;
SIGNAL we_tx_data_7 : std_logic;
SIGNAL we_tx_data_8 : std_logic;
SIGNAL we_tx_data_9 : std_logic;
SIGNAL we_tx_data_10 : std_logic;
SIGNAL we_tx_data_11 : std_logic;
SIGNAL we_tx_data_12 : std_logic;
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
SIGNAL we_interrupt_enable : std_logic;
SIGNAL we_error_warning_limit : std_logic;
SIGNAL we_acceptance_code_1 : std_logic;
SIGNAL we_acceptance_code_2 : std_logic;
SIGNAL we_acceptance_code_3 : std_logic;
SIGNAL we_acceptance_mask_1 : std_logic;
SIGNAL we_acceptance_mask_2 : std_logic;
SIGNAL we_acceptance_mask_3 : std_logic;
-- Mode register
SIGNAL mode : std_logic;
SIGNAL mode_basic : std_logic_vector(4 DOWNTO 1);
SIGNAL mode_ext : std_logic_vector(3 DOWNTO 1);
SIGNAL receive_irq_en_basic : std_logic;
SIGNAL transmit_irq_en_basic : std_logic;
SIGNAL error_irq_en_basic : std_logic;
SIGNAL overrun_irq_en_basic : std_logic;
SIGNAL port_xhdl52 : std_logic;
SIGNAL xhdl_61 : std_logic;
-- End Mode register
-- Command register
SIGNAL command : std_logic_vector(4 DOWNTO 0);
SIGNAL xhdl_69 : std_logic;
SIGNAL port_xhdl70 : std_logic;
SIGNAL port_xhdl71 : std_logic;
SIGNAL xhdl_77 : std_logic;
SIGNAL port_xhdl78 : std_logic;
SIGNAL port_xhdl79 : std_logic;
SIGNAL xhdl_85 : std_logic;
SIGNAL xhdl_91 : std_logic;
SIGNAL port_xhdl92 : std_logic;
SIGNAL port_xhdl93 : std_logic;
-- End Command register
-- Status register
SIGNAL status : std_logic_vector(7 DOWNTO 0);
-- End Status register
-- Interrupt Enable register (extended mode)
SIGNAL irq_en_ext : std_logic_vector(7 DOWNTO 0);
SIGNAL bus_error_irq_en : std_logic;
SIGNAL arbitration_lost_irq_en : std_logic;
SIGNAL error_passive_irq_en : std_logic;
SIGNAL data_overrun_irq_en_ext : std_logic;
SIGNAL error_warning_irq_en_ext : std_logic;
SIGNAL transmit_irq_en_ext : std_logic;
SIGNAL receive_irq_en_ext : std_logic;
-- End Bus Timing 0 register
-- Bus Timing 0 register
SIGNAL bus_timing_0 : std_logic_vector(7 DOWNTO 0);
-- End Bus Timing 0 register
-- Bus Timing 1 register
SIGNAL bus_timing_1 : std_logic_vector(7 DOWNTO 0);
-- End Error Warning Limit register
-- Clock Divider register
SIGNAL clock_divider : std_logic_vector(7 DOWNTO 0);
SIGNAL clock_off : std_logic;
SIGNAL cd : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_div : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_tmp : std_logic;
SIGNAL port_xhdl116 : std_logic;
SIGNAL port_xhdl117 : std_logic;
SIGNAL port_xhdl123 : std_logic;
SIGNAL port_xhdl124 : std_logic;
SIGNAL temp_xhdl131 : std_logic;
SIGNAL temp_xhdl132 : std_logic;
SIGNAL temp_xhdl218 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl219 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl220 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl221 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl222 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl223 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl224 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl225 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl226 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl227 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl228 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl229 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl230 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl231 : std_logic_vector(7 DOWNTO 0); -- basic mode
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL temp_xhdl233 : std_logic;
SIGNAL temp_xhdl234 : std_logic;
SIGNAL temp_xhdl235 : std_logic;
SIGNAL temp_xhdl236 : std_logic;
SIGNAL data_overrun_irq : std_logic;
SIGNAL transmit_irq : std_logic;
SIGNAL receive_irq : std_logic;
SIGNAL error_irq : std_logic;
SIGNAL bus_error_irq : std_logic;
SIGNAL arbitration_lost_irq : std_logic;
SIGNAL error_passive_irq : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL irq_n_xhdl2 : std_logic;
SIGNAL reset_mode_xhdl3 : std_logic;
SIGNAL listen_only_mode_xhdl4 : std_logic;
SIGNAL acceptance_filter_mode_xhdl5 : std_logic;
SIGNAL self_test_mode_xhdl6 : std_logic;
SIGNAL clear_data_overrun_xhdl7 : std_logic;
SIGNAL release_buffer_xhdl8 : std_logic;
SIGNAL abort_tx_xhdl9 : std_logic;
SIGNAL tx_request_xhdl10 : std_logic;
SIGNAL self_rx_request_xhdl11 : std_logic;
SIGNAL single_shot_transmission_xhdl12 : std_logic;
SIGNAL overload_request_xhdl13 : std_logic;
SIGNAL read_arbitration_lost_capture_reg_xhdl14: std_logic;
SIGNAL read_error_code_capture_reg_xhdl15: std_logic;
SIGNAL baud_r_presc_xhdl16 : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width_xhdl17 : std_logic_vector(1 DOWNTO 0);
SIGNAL time_segment1_xhdl18 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2_xhdl19 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling_xhdl20 : std_logic;
SIGNAL error_warning_limit_xhdl21 : std_logic_vector(7 DOWNTO 0);
SIGNAL we_rx_err_cnt_xhdl22 : std_logic;
SIGNAL we_tx_err_cnt_xhdl23 : std_logic;
SIGNAL extended_mode_xhdl24 : std_logic;
SIGNAL clkout_xhdl25 : std_logic;
SIGNAL acceptance_code_0_xhdl26 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_0_xhdl27 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_1_xhdl28 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2_xhdl29 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3_xhdl30 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_1_xhdl31 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2_xhdl32 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3_xhdl33 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_0_xhdl34 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1_xhdl35 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3_xhdl37 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4_xhdl38 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5_xhdl39 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6_xhdl40 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7_xhdl41 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8_xhdl42 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9_xhdl43 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10_xhdl44 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11_xhdl45 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12_xhdl46 : std_logic_vector(7 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
irq_n <= irq_n_xhdl2;
reset_mode <= reset_mode_xhdl3;
listen_only_mode <= listen_only_mode_xhdl4;
acceptance_filter_mode <= acceptance_filter_mode_xhdl5;
self_test_mode <= self_test_mode_xhdl6;
clear_data_overrun <= clear_data_overrun_xhdl7;
release_buffer <= release_buffer_xhdl8;
abort_tx <= abort_tx_xhdl9;
tx_request <= tx_request_xhdl10;
self_rx_request <= self_rx_request_xhdl11;
single_shot_transmission <= single_shot_transmission_xhdl12;
overload_request <= overload_request_xhdl13;
read_arbitration_lost_capture_reg <= read_arbitration_lost_capture_reg_xhdl14;
read_error_code_capture_reg <= read_error_code_capture_reg_xhdl15;
baud_r_presc <= baud_r_presc_xhdl16;
sync_jump_width <= sync_jump_width_xhdl17;
time_segment1 <= time_segment1_xhdl18;
time_segment2 <= time_segment2_xhdl19;
triple_sampling <= triple_sampling_xhdl20;
error_warning_limit <= error_warning_limit_xhdl21;
we_rx_err_cnt <= we_rx_err_cnt_xhdl22;
we_tx_err_cnt <= we_tx_err_cnt_xhdl23;
extended_mode <= extended_mode_xhdl24;
clkout <= clkout_xhdl25;
acceptance_code_0 <= acceptance_code_0_xhdl26;
acceptance_mask_0 <= acceptance_mask_0_xhdl27;
acceptance_code_1 <= acceptance_code_1_xhdl28;
acceptance_code_2 <= acceptance_code_2_xhdl29;
acceptance_code_3 <= acceptance_code_3_xhdl30;
acceptance_mask_1 <= acceptance_mask_1_xhdl31;
acceptance_mask_2 <= acceptance_mask_2_xhdl32;
acceptance_mask_3 <= acceptance_mask_3_xhdl33;
tx_data_0 <= tx_data_0_xhdl34;
tx_data_1 <= tx_data_1_xhdl35;
tx_data_2 <= tx_data_2_xhdl36;
tx_data_3 <= tx_data_3_xhdl37;
tx_data_4 <= tx_data_4_xhdl38;
tx_data_5 <= tx_data_5_xhdl39;
tx_data_6 <= tx_data_6_xhdl40;
tx_data_7 <= tx_data_7_xhdl41;
tx_data_8 <= tx_data_8_xhdl42;
tx_data_9 <= tx_data_9_xhdl43;
tx_data_10 <= tx_data_10_xhdl44;
tx_data_11 <= tx_data_11_xhdl45;
tx_data_12 <= tx_data_12_xhdl46;
we_mode <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000000") ;
we_command <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000001") ;
we_bus_timing_0 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000110")) AND reset_mode_xhdl3 ;
we_bus_timing_1 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000111")) AND reset_mode_xhdl3 ;
we_clock_divider_low <= (cs AND we) AND CONV_STD_LOGIC(addr = "00011111") ;
we_clock_divider_hi <= we_clock_divider_low AND reset_mode_xhdl3 ;
read <= cs AND (NOT we) ;
read_irq_reg <= read AND CONV_STD_LOGIC(addr = "00000011") ;
reset_irq_reg <= read_irq_reg_q and not read_irq_reg;
read_arbitration_lost_capture_reg_xhdl14 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011") ;
read_error_code_capture_reg_xhdl15 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100") ;
we_acceptance_code_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000"))) ;
we_acceptance_mask_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100"))) ;
we_tx_data_0 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000")))) AND transmit_buffer_status ;
we_tx_data_1 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010001")))) AND transmit_buffer_status ;
we_tx_data_2 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010010")))) AND transmit_buffer_status ;
we_tx_data_3 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010011")))) AND transmit_buffer_status ;
we_tx_data_4 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001110")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100")))) AND transmit_buffer_status ;
we_tx_data_5 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001111")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010101")))) AND transmit_buffer_status ;
we_tx_data_6 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010000")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010110")))) AND transmit_buffer_status ;
we_tx_data_7 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010001")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010111")))) AND transmit_buffer_status ;
we_tx_data_8 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011000")))) AND transmit_buffer_status ;
we_tx_data_9 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011001")))) AND transmit_buffer_status ;
we_tx_data_10 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011010"))) AND transmit_buffer_status ;
we_tx_data_11 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011011"))) AND transmit_buffer_status ;
we_tx_data_12 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011100"))) AND transmit_buffer_status ;
we_interrupt_enable <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000100")) AND extended_mode_xhdl24 ;
we_error_warning_limit <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_rx_err_cnt_xhdl22 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_tx_err_cnt_xhdl23 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010001")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010010")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010011")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
-- End: This section is for EXTENDED mode
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
read_irq_reg_q <= read_irq_reg;
tx_successful_q <= tx_successful ;
overrun_q <= overrun ;
transmit_buffer_status_q <= transmit_buffer_status ;
error_status_q <= error_status ;
node_bus_off_q <= node_bus_off ;
node_error_passive_q <= node_error_passive ;
END IF;
END PROCESS;
port_xhdl52 <= data_in(0);
MODE_REG0 : can_register_asyn_syn
GENERIC MAP (1, 1)
PORT MAP (
data_in(0) => port_xhdl52,
data_out(0) => mode,
we => we_mode,
clk => clk,
rst => rst,
rst_sync => set_reset_mode);
MODE_REG_BASIC : can_register_asyn
GENERIC MAP (4, 0)
PORT MAP (
data_in => data_in(4 DOWNTO 1),
data_out => mode_basic(4 DOWNTO 1),
we => we_mode,
clk => clk,
rst => rst);
xhdl_61 <= (we_mode AND reset_mode_xhdl3);
MODE_REG_EXT : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 1),
data_out => mode_ext(3 DOWNTO 1),
we => xhdl_61,
clk => clk,
rst => rst);
reset_mode_xhdl3 <= mode ;
listen_only_mode_xhdl4 <= extended_mode_xhdl24 AND mode_ext(1) ;
self_test_mode_xhdl6 <= extended_mode_xhdl24 AND mode_ext(2) ;
acceptance_filter_mode_xhdl5 <= extended_mode_xhdl24 AND mode_ext(3) ;
receive_irq_en_basic <= mode_basic(1) ;
transmit_irq_en_basic <= mode_basic(2) ;
error_irq_en_basic <= mode_basic(3) ;
overrun_irq_en_basic <= mode_basic(4) ;
xhdl_69 <= (command(0) AND sample_point) OR reset_mode_xhdl3;
port_xhdl70 <= data_in(0);
command(0) <= port_xhdl71;
COMMAND_REG0 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl70,
data_out(0) => port_xhdl71,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_69);
xhdl_77 <= (sample_point AND (tx_request_xhdl10 OR (abort_tx_xhdl9 AND NOT transmitting))) OR reset_mode_xhdl3;
port_xhdl78 <= data_in(1);
command(1) <= port_xhdl79;
COMMAND_REG1 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl78,
data_out(0) => port_xhdl79,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_77);
xhdl_85 <= orv(command(3 DOWNTO 2)) OR reset_mode_xhdl3;
COMMAND_REG : can_register_asyn_syn
GENERIC MAP (2, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 2),
data_out => command(3 DOWNTO 2),
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_85);
xhdl_91 <= (command(4) AND sample_point) OR reset_mode_xhdl3;
port_xhdl92 <= data_in(4);
command(4) <= port_xhdl93;
COMMAND_REG4 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl92,
data_out(0) => port_xhdl93,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_91);
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
self_rx_request_xhdl11 <= '0';
ELSif clk'event and clk = '1' then
IF ((command(4) AND (NOT command(0))) = '1') THEN
self_rx_request_xhdl11 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
self_rx_request_xhdl11 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
clear_data_overrun_xhdl7 <= command(3) ;
release_buffer_xhdl8 <= command(2) ;
tx_request_xhdl10 <= command(0) OR command(4) ;
abort_tx_xhdl9 <= command(1) AND (NOT tx_request_xhdl10) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
single_shot_transmission_xhdl12 <= '0';
ELSif clk'event and clk = '1' then
IF (((tx_request_xhdl10 AND command(1)) AND sample_point) = '1') THEN
single_shot_transmission_xhdl12 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
single_shot_transmission_xhdl12 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
--
-- can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD // Uncomment this to enable overload requests !!!
-- ( .data_in(data_in[5]),
-- .data_out(overload_request),
-- .we(we_command),
-- .clk(clk),
-- .rst(rst),
-- .rst_sync(overload_frame & ~overload_frame_q)
-- );
-- reg overload_frame_q;
-- always @ (posedge clk or posedge rst)
-- begin
-- if (rst)
-- overload_frame_q <= 1'b0;
-- else
-- overload_frame_q <=#Tp overload_frame;
-- end
--
overload_request_xhdl13 <= '0' ;
status(7) <= node_bus_off ;
status(6) <= error_status ;
status(5) <= transmit_status ;
status(4) <= receive_status ;
status(3) <= transmission_complete ;
status(2) <= transmit_buffer_status ;
status(1) <= overrun_status ;
status(0) <= receive_buffer_status ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmission_complete <= '1';
ELSif clk'event and clk = '1' then
IF ((tx_successful AND ((NOT tx_successful_q) OR abort_tx_xhdl9)) = '1') THEN
-- transmission_complete was always set when abort_tx=1
-- Original code:
-- IF (((tx_successful AND (NOT tx_successful_q)) OR abort_tx_xhdl9) = '1') THEN
transmission_complete <= '1' ;
ELSE
IF (tx_request_xhdl10 = '1') THEN
transmission_complete <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_buffer_status <= '1';
ELSif clk'event and clk = '1' then
IF (tx_request_xhdl10 = '1') THEN
transmit_buffer_status <= '0' ;
ELSE
IF ((reset_mode_xhdl3 OR NOT need_to_tx) = '1') THEN
transmit_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overrun_status <= '0';
ELSif clk'event and clk = '1' then
IF ((overrun AND (NOT overrun_q)) = '1') THEN
overrun_status <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR clear_data_overrun_xhdl7) = '1') THEN
overrun_status <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_buffer_status <= '0';
ELSif clk'event and clk = '1' then
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_buffer_status <= '0' ;
ELSE
IF (NOT info_empty = '1') THEN
receive_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
IRQ_EN_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => irq_en_ext,
we => we_interrupt_enable,
clk => clk);
bus_error_irq_en <= irq_en_ext(7) ;
arbitration_lost_irq_en <= irq_en_ext(6) ;
error_passive_irq_en <= irq_en_ext(5) ;
data_overrun_irq_en_ext <= irq_en_ext(3) ;
error_warning_irq_en_ext <= irq_en_ext(2) ;
transmit_irq_en_ext <= irq_en_ext(1) ;
receive_irq_en_ext <= irq_en_ext(0) ;
BUS_TIMING_0_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_0,
we => we_bus_timing_0,
clk => clk);
baud_r_presc_xhdl16 <= bus_timing_0(5 DOWNTO 0) ;
sync_jump_width_xhdl17 <= bus_timing_0(7 DOWNTO 6) ;
BUS_TIMING_1_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_1,
we => we_bus_timing_1,
clk => clk);
time_segment1_xhdl18 <= bus_timing_1(3 DOWNTO 0) ;
time_segment2_xhdl19 <= bus_timing_1(6 DOWNTO 4) ;
triple_sampling_xhdl20 <= bus_timing_1(7) ;
-- End Bus Timing 1 register -- Error Warning Limit register
ERROR_WARNING_REG : can_register_asyn
GENERIC MAP (8, 96)
PORT MAP (
data_in => data_in,
data_out => error_warning_limit_xhdl21,
we => we_error_warning_limit,
clk => clk,
rst => rst);
port_xhdl116 <= data_in(7);
clock_divider(7) <= port_xhdl117;
CLOCK_DIVIDER_REG_7 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl116,
data_out(0) => port_xhdl117,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
clock_divider(6 DOWNTO 4) <= "000" ;
port_xhdl123 <= data_in(3);
clock_divider(3) <= port_xhdl124;
CLOCK_DIVIDER_REG_3 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl123,
data_out(0) => port_xhdl124,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
CLOCK_DIVIDER_REG_LOW : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(2 DOWNTO 0),
data_out => clock_divider(2 DOWNTO 0),
we => we_clock_divider_low,
clk => clk,
rst => rst);
extended_mode_xhdl24 <= clock_divider(7) ;
clock_off <= clock_divider(3) ;
cd(2 DOWNTO 0) <= clock_divider(2 DOWNTO 0) ;
PROCESS (cd)
VARIABLE clkout_div_xhdl130 : std_logic_vector(2 DOWNTO 0);
BEGIN
CASE cd IS
-- synthesis full_case parallel_case
WHEN "000" =>
clkout_div_xhdl130 := "000";
WHEN "001" =>
clkout_div_xhdl130 := "001";
WHEN "010" =>
clkout_div_xhdl130 := "010";
WHEN "011" =>
clkout_div_xhdl130 := "011";
WHEN "100" =>
clkout_div_xhdl130 := "100";
WHEN "101" =>
clkout_div_xhdl130 := "101";
WHEN "110" =>
clkout_div_xhdl130 := "110";
WHEN "111" =>
clkout_div_xhdl130 := "000";
WHEN OTHERS =>
NULL;
END CASE;
clkout_div <= clkout_div_xhdl130;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_cnt <= "000";
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_cnt <= "000" ;
ELSE
clkout_cnt <= clkout_cnt + "001";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_tmp <= '0';
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_tmp <= NOT clkout_tmp ;
END IF;
END IF;
END PROCESS;
temp_xhdl131 <= clk WHEN (andv(cd)) = '1' ELSE clkout_tmp;
temp_xhdl132 <= '1' WHEN clock_off = '1' ELSE (temp_xhdl131);
clkout_xhdl25 <= temp_xhdl132 ;
-- End Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register
ACCEPTANCE_CODE_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_0_xhdl26,
we => we_acceptance_code_0,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register
ACCEPTANCE_MASK_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_0_xhdl27,
we => we_acceptance_mask_0,
clk => clk);
-- End: Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- Tx data 0 register.
TX_DATA_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_0_xhdl34,
we => we_tx_data_0,
clk => clk);
-- End: Tx data 0 register. -- Tx data 1 register.
TX_DATA_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_1_xhdl35,
we => we_tx_data_1,
clk => clk);
-- End: Tx data 1 register. -- Tx data 2 register.
TX_DATA_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_2_xhdl36,
we => we_tx_data_2,
clk => clk);
-- End: Tx data 2 register. -- Tx data 3 register.
TX_DATA_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_3_xhdl37,
we => we_tx_data_3,
clk => clk);
-- End: Tx data 3 register. -- Tx data 4 register.
TX_DATA_REG4 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_4_xhdl38,
we => we_tx_data_4,
clk => clk);
-- End: Tx data 4 register. -- Tx data 5 register.
TX_DATA_REG5 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_5_xhdl39,
we => we_tx_data_5,
clk => clk);
-- End: Tx data 5 register. -- Tx data 6 register.
TX_DATA_REG6 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_6_xhdl40,
we => we_tx_data_6,
clk => clk);
-- End: Tx data 6 register. -- Tx data 7 register.
TX_DATA_REG7 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_7_xhdl41,
we => we_tx_data_7,
clk => clk);
-- End: Tx data 7 register. -- Tx data 8 register.
TX_DATA_REG8 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_8_xhdl42,
we => we_tx_data_8,
clk => clk);
-- End: Tx data 8 register. -- Tx data 9 register.
TX_DATA_REG9 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_9_xhdl43,
we => we_tx_data_9,
clk => clk);
-- End: Tx data 9 register. -- Tx data 10 register.
TX_DATA_REG10 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_10_xhdl44,
we => we_tx_data_10,
clk => clk);
-- End: Tx data 10 register. -- Tx data 11 register.
TX_DATA_REG11 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_11_xhdl45,
we => we_tx_data_11,
clk => clk);
-- End: Tx data 11 register. -- Tx data 12 register.
TX_DATA_REG12 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_12_xhdl46,
we => we_tx_data_12,
clk => clk);
-- End: Tx data 12 register. -- This section is for EXTENDED mode -- Acceptance code register 1
ACCEPTANCE_CODE_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_1_xhdl28,
we => we_acceptance_code_1,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 2
ACCEPTANCE_CODE_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_2_xhdl29,
we => we_acceptance_code_2,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 3
ACCEPTANCE_CODE_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_3_xhdl30,
we => we_acceptance_code_3,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 1
ACCEPTANCE_MASK_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_1_xhdl31,
we => we_acceptance_mask_1,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 2
ACCEPTANCE_MASK_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_2_xhdl32,
we => we_acceptance_mask_2,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 3
ACCEPTANCE_MASK_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_3_xhdl33,
we => we_acceptance_mask_3,
clk => clk);
temp_xhdl218 <= acceptance_code_0_xhdl26 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl219 <= acceptance_mask_0_xhdl27 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl220 <= bus_timing_0 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl221 <= bus_timing_1 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl222 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_0_xhdl34;
temp_xhdl223 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_1_xhdl35;
temp_xhdl224 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_2_xhdl36;
temp_xhdl225 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_3_xhdl37;
temp_xhdl226 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_4_xhdl38;
temp_xhdl227 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_5_xhdl39;
temp_xhdl228 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_6_xhdl40;
temp_xhdl229 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_7_xhdl41;
temp_xhdl230 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_8_xhdl42;
temp_xhdl231 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_9_xhdl43;
-- End: Acceptance code register -- End: This section is for EXTENDED mode -- Reading data from registers
PROCESS (addr, extended_mode_xhdl24, mode, bus_timing_0, bus_timing_1, clock_divider,
acceptance_code_0_xhdl26, acceptance_code_1_xhdl28, acceptance_code_2_xhdl29,
acceptance_code_3_xhdl30, acceptance_mask_0_xhdl27, acceptance_mask_1_xhdl31,
acceptance_mask_2_xhdl32, acceptance_mask_3_xhdl33, status,
error_warning_limit_xhdl21, rx_err_cnt, tx_err_cnt, irq_en_ext, irq_reg, mode_ext,
arbitration_lost_capture, rx_message_counter, mode_basic, error_capture_code,
temp_xhdl218, temp_xhdl219, temp_xhdl220, temp_xhdl221, temp_xhdl222, temp_xhdl223,
temp_xhdl224, temp_xhdl225, temp_xhdl226, temp_xhdl227, temp_xhdl228, temp_xhdl229,
temp_xhdl230, temp_xhdl231
)
VARIABLE data_out_xhdl1_xhdl217 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl232 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl232 := extended_mode_xhdl24 & addr(4 DOWNTO 0);
CASE temp_xhdl232 IS
WHEN "100000" =>
data_out_xhdl1_xhdl217 := "0000" & mode_ext(3 DOWNTO 1) & mode; -- extended mode
WHEN "100001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "100010" =>
data_out_xhdl1_xhdl217 := status; -- extended mode
WHEN "100011" =>
data_out_xhdl1_xhdl217 := irq_reg; -- extended mode
WHEN "100100" =>
data_out_xhdl1_xhdl217 := irq_en_ext; -- extended mode
WHEN "100110" =>
data_out_xhdl1_xhdl217 := bus_timing_0; -- extended mode
WHEN "100111" =>
data_out_xhdl1_xhdl217 := bus_timing_1; -- extended mode
WHEN "101011" =>
data_out_xhdl1_xhdl217 := "000" & arbitration_lost_capture(4 DOWNTO 0); -- extended mode
WHEN "101100" =>
data_out_xhdl1_xhdl217 := error_capture_code; -- extended mode
WHEN "101101" =>
data_out_xhdl1_xhdl217 := error_warning_limit_xhdl21; -- extended mode
WHEN "101110" =>
data_out_xhdl1_xhdl217 := rx_err_cnt; -- extended mode
WHEN "101111" =>
data_out_xhdl1_xhdl217 := tx_err_cnt; -- extended mode
WHEN "110000" =>
data_out_xhdl1_xhdl217 := acceptance_code_0_xhdl26; -- extended mode
WHEN "110001" =>
data_out_xhdl1_xhdl217 := acceptance_code_1_xhdl28; -- extended mode
WHEN "110010" =>
data_out_xhdl1_xhdl217 := acceptance_code_2_xhdl29; -- extended mode
WHEN "110011" =>
data_out_xhdl1_xhdl217 := acceptance_code_3_xhdl30; -- extended mode
WHEN "110100" =>
data_out_xhdl1_xhdl217 := acceptance_mask_0_xhdl27; -- extended mode
WHEN "110101" =>
data_out_xhdl1_xhdl217 := acceptance_mask_1_xhdl31; -- extended mode
WHEN "110110" =>
data_out_xhdl1_xhdl217 := acceptance_mask_2_xhdl32; -- extended mode
WHEN "110111" =>
data_out_xhdl1_xhdl217 := acceptance_mask_3_xhdl33; -- extended mode
WHEN "111000" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111010" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111011" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111100" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111101" =>
data_out_xhdl1_xhdl217 := '0' & rx_message_counter; -- extended mode
WHEN "111111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- extended mode
WHEN "000000" =>
data_out_xhdl1_xhdl217 := "001" & mode_basic(4 DOWNTO 1) & mode; -- basic mode
WHEN "000001" =>
data_out_xhdl1_xhdl217 := "11111111"; -- basic mode
WHEN "000010" =>
data_out_xhdl1_xhdl217 := status; -- basic mode
WHEN "000011" =>
data_out_xhdl1_xhdl217 := "1110" & irq_reg(3 DOWNTO 0); -- basic mode
WHEN "000100" =>
data_out_xhdl1_xhdl217 := temp_xhdl218;
WHEN "000101" =>
data_out_xhdl1_xhdl217 := temp_xhdl219;
WHEN "000110" =>
data_out_xhdl1_xhdl217 := temp_xhdl220;
WHEN "000111" =>
data_out_xhdl1_xhdl217 := temp_xhdl221;
WHEN "001010" =>
data_out_xhdl1_xhdl217 := temp_xhdl222;
WHEN "001011" =>
data_out_xhdl1_xhdl217 := temp_xhdl223;
WHEN "001100" =>
data_out_xhdl1_xhdl217 := temp_xhdl224;
WHEN "001101" =>
data_out_xhdl1_xhdl217 := temp_xhdl225;
WHEN "001110" =>
data_out_xhdl1_xhdl217 := temp_xhdl226;
WHEN "001111" =>
data_out_xhdl1_xhdl217 := temp_xhdl227;
WHEN "010000" =>
data_out_xhdl1_xhdl217 := temp_xhdl228;
WHEN "010001" =>
data_out_xhdl1_xhdl217 := temp_xhdl229;
WHEN "010010" =>
data_out_xhdl1_xhdl217 := temp_xhdl230;
WHEN "010011" =>
data_out_xhdl1_xhdl217 := temp_xhdl231;
WHEN "011111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- basic mode
WHEN OTHERS =>
data_out_xhdl1_xhdl217 := "00000000"; -- the rest is read as 0
END CASE;
data_out_xhdl1 <= data_out_xhdl1_xhdl217;
END PROCESS;
temp_xhdl233 <= data_overrun_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE overrun_irq_en_basic;
data_overrun_irq_en <= temp_xhdl233 ;
temp_xhdl234 <= error_warning_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE error_irq_en_basic;
error_warning_irq_en <= temp_xhdl234 ;
temp_xhdl235 <= transmit_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE transmit_irq_en_basic;
transmit_irq_en <= temp_xhdl235 ;
temp_xhdl236 <= receive_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE receive_irq_en_basic;
receive_irq_en <= temp_xhdl236 ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_overrun_irq <= '0';
ELSif clk'event and clk = '1' then
IF (((overrun AND (NOT overrun_q)) AND data_overrun_irq_en) = '1') THEN
data_overrun_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
data_overrun_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_irq <= '0';
ELSif clk'event and clk = '1' then
IF (reset_mode_xhdl3 = '1') THEN
transmit_irq <= '0' ;
ELSE
IF (((transmit_buffer_status AND (NOT transmit_buffer_status_q)) AND transmit_irq_en) = '1') THEN
transmit_irq <= '1' ;
elsif (reset_irq_reg = '1') then
transmit_irq <= '0';
end if;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((NOT info_empty) AND (NOT receive_irq)) AND receive_irq_en) = '1') THEN
receive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((error_status XOR error_status_q) OR (node_bus_off XOR node_bus_off_q)) AND error_warning_irq_en) = '1') THEN
error_irq <= '1' ;
ELSE
IF (reset_irq_reg = '1') THEN
error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_bus_error_irq AND bus_error_irq_en) = '1') THEN
bus_error_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
bus_error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_arbitration_lost_irq AND arbitration_lost_irq_en) = '1') THEN
arbitration_lost_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
arbitration_lost_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_passive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((node_error_passive AND (NOT node_error_passive_q)) OR (((NOT node_error_passive) AND node_error_passive_q) AND node_error_active)) AND error_passive_irq_en) = '1') THEN
error_passive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
error_passive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
irq_reg <= bus_error_irq & arbitration_lost_irq & error_passive_irq & '0' & data_overrun_irq & error_irq & transmit_irq & receive_irq ;
irq <= data_overrun_irq OR transmit_irq OR receive_irq OR error_irq OR bus_error_irq OR arbitration_lost_irq OR error_passive_irq ;
-- irq_o reset change /Kristoffer 2006-02-23 PROCESS (clk, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSif clk'event and clk = '1' then
-- IF (reset_irq_reg = '1' or release_buffer_xhdl8='1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSE
-- IF (irq = '1') THEN
-- irq_n_xhdl2 <= '0' ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
PROCESS (clk, rst, release_buffer_xhdl8)
BEGIN
IF (rst = '1' or release_buffer_xhdl8 = '1') THEN
irq_n_xhdl2 <= '1';
ELSif clk'event and clk = '1' then
irq_n_xhdl2 <= not irq;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_top
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_top.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_top.v,v $
-- Revision 1.48 2004/10/25 11:44:47 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.47 2004/02/08 14:53:54 mohor
-- Header changed. Address latched to posedge. bus_off_on signal added.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.44 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.43 2003/08/20 09:57:39 mohor
-- Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
-- to be joined together on higher level.
--
-- Revision 1.42 2003/07/16 15:11:28 mohor
-- Fixed according to the linter.
--
-- Revision 1.41 2003/07/10 15:32:27 mohor
-- Unused signal removed.
--
-- Revision 1.40 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.39 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.38 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.37 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.36 2003/06/17 14:30:30 mohor
-- "chip select" signal cs_can_i is used only when not using WISHBONE
-- interface.
--
-- Revision 1.35 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.34 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.33 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.32 2003/06/09 11:32:36 mohor
-- Ports added for the CAN_BIST.
--
-- Revision 1.31 2003/03/26 11:19:46 mohor
-- CAN interrupt is active low.
--
-- Revision 1.30 2003/03/20 17:01:17 mohor
-- unix.
--
-- Revision 1.28 2003/03/14 19:36:48 mohor
-- can_cs signal used for generation of the cs.
--
-- Revision 1.27 2003/03/12 05:56:33 mohor
-- Bidirectional port_0_i changed to port_0_io.
-- input cs_can changed to cs_can_i.
--
-- Revision 1.26 2003/03/12 04:39:40 mohor
-- rd_i and wr_i are active high signals. If 8051 is connected, these two signals
-- need to be negated one level higher.
--
-- Revision 1.25 2003/03/12 04:17:36 mohor
-- 8051 interface added (besides WISHBONE interface). Selection is made in
-- can_defines.v file.
--
-- Revision 1.24 2003/03/10 17:24:40 mohor
-- wire declaration added.
--
-- Revision 1.23 2003/03/05 15:33:13 mohor
-- tx_o is now tristated signal. tx_oen and tx_o combined together.
--
-- Revision 1.22 2003/03/05 15:01:56 mohor
-- Top level signal names changed.
--
-- Revision 1.21 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.20 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.19 2003/02/19 15:04:14 mohor
-- Typo fixed.
--
-- Revision 1.18 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.17 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.16 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.15 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.14 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.13 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.12 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.11 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.6 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.5 2003/01/08 02:10:56 mohor
-- Acceptance filter added.
--
-- Revision 1.4 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_top IS
PORT (
-- wb_clk_i : IN std_logic;
-- wb_rst_i : IN std_logic;
-- wb_dat_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_dat_o : OUT std_logic_vector(7 DOWNTO 0);
-- wb_cyc_i : IN std_logic;
-- wb_stb_i : IN std_logic;
-- wb_we_i : IN std_logic;
-- wb_adr_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_ack_o : OUT std_logic;
rst : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
cs : IN std_logic;
we : IN std_logic;
clk_i : IN std_logic;
rx_i : IN std_logic;
tx_o : OUT std_logic;
bus_off_on : OUT std_logic;
irq_on : OUT std_logic;
clkout_o : OUT std_logic;
-- Bist
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_top;
ARCHITECTURE RTL OF can_top IS
COMPONENT can_bsp
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic;
overload_frame : OUT std_logic;
read_arbitration_lost_capture_reg: IN std_logic;
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : IN std_logic;
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_btl
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END COMPONENT;
COMPONENT can_registers
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
read_arbitration_lost_capture_reg: OUT std_logic;
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : OUT std_logic;
we_tx_err_cnt : OUT std_logic;
extended_mode : OUT std_logic;
clkout : OUT std_logic;
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
-- SIGNAL cs_sync1 : std_logic;
-- SIGNAL cs_sync2 : std_logic;
-- SIGNAL cs_sync3 : std_logic;
-- SIGNAL cs_ack1 : std_logic;
-- SIGNAL cs_ack2 : std_logic;
-- SIGNAL cs_ack3 : std_logic;
-- SIGNAL cs_sync_rst1 : std_logic;
-- SIGNAL cs_sync_rst2 : std_logic;
-- SIGNAL cs_can_i : std_logic;
---------------------------------
SIGNAL data_out_fifo_selected : std_logic;
SIGNAL data_out_fifo : std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_regs : std_logic_vector(7 DOWNTO 0);
-- Mode register
SIGNAL reset_mode : std_logic;
SIGNAL listen_only_mode : std_logic;
SIGNAL acceptance_filter_mode : std_logic;
SIGNAL self_test_mode : std_logic;
-- Command register
SIGNAL release_buffer : std_logic;
SIGNAL tx_request : std_logic;
SIGNAL abort_tx : std_logic;
SIGNAL self_rx_request : std_logic;
SIGNAL single_shot_transmission : std_logic;
SIGNAL tx_state : std_logic;
SIGNAL tx_state_q : std_logic;
SIGNAL overload_request : std_logic;
SIGNAL overload_frame : std_logic;
-- Arbitration Lost Capture Register
SIGNAL read_arbitration_lost_capture_reg: std_logic;
-- Error Code Capture Register
SIGNAL read_error_code_capture_reg : std_logic;
SIGNAL error_capture_code : std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
SIGNAL baud_r_presc : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width : std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
SIGNAL time_segment1 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling : std_logic;
-- Error Warning Limit register
SIGNAL error_warning_limit : std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
SIGNAL we_rx_err_cnt : std_logic;
-- Tx Error Counter register
SIGNAL we_tx_err_cnt : std_logic;
-- Clock Divider register
SIGNAL extended_mode : std_logic;
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_0 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_0 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode
-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
SIGNAL tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12 : std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
-- SIGNAL cs : std_logic;
-- Output signals from can_btl module
SIGNAL sample_point : std_logic;
SIGNAL sampled_bit : std_logic;
SIGNAL sampled_bit_q : std_logic;
SIGNAL tx_point : std_logic;
SIGNAL hard_sync : std_logic;
-- output from can_bsp module
SIGNAL rx_idle : std_logic;
SIGNAL transmitting : std_logic;
SIGNAL transmitter : std_logic;
SIGNAL go_rx_inter : std_logic;
SIGNAL not_first_bit_of_inter : std_logic;
SIGNAL set_reset_mode : std_logic;
SIGNAL node_bus_off : std_logic;
SIGNAL error_status : std_logic;
SIGNAL rx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL tx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL transmit_status : std_logic;
SIGNAL receive_status : std_logic;
SIGNAL tx_successful : std_logic;
SIGNAL need_to_tx : std_logic;
SIGNAL overrun : std_logic;
SIGNAL info_empty : std_logic;
SIGNAL set_bus_error_irq : std_logic;
SIGNAL set_arbitration_lost_irq : std_logic;
SIGNAL arbitration_lost_capture : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive : std_logic;
SIGNAL node_error_active : std_logic;
SIGNAL rx_message_counter : std_logic_vector(6 DOWNTO 0);
SIGNAL tx_next : std_logic;
SIGNAL go_overload_frame : std_logic;
SIGNAL go_error_frame : std_logic;
SIGNAL go_tx : std_logic;
SIGNAL send_ack : std_logic;
-- SIGNAL rst : std_logic;
-- SIGNAL we : std_logic;
-- SIGNAL addr : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_in : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_out : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_sync_tmp : std_logic;
SIGNAL rx_sync : std_logic;
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
-- From btl module
-- Mode register
-- Command register
-- Arbitration Lost Capture Register
-- Error Code Capture Register
-- Error Warning Limit register
-- Rx Error Counter register
-- Tx Error Counter register
-- Clock Divider register
-- output from can_bsp module
SIGNAL xhdl_148 : std_logic_vector(8 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL xhdl_150 : std_logic_vector(8 DOWNTO 0);
-- SIGNAL wb_dat_o_xhdl1 : std_logic_vector(7 DOWNTO 0);
-- SIGNAL wb_ack_o_xhdl2 : std_logic;
SIGNAL tx_o_xhdl3 : std_logic;
SIGNAL bus_off_on_xhdl4 : std_logic;
SIGNAL irq_on_xhdl5 : std_logic;
SIGNAL clkout_o_xhdl6 : std_logic;
SIGNAL data_64x8_xhdl7 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl8 : std_logic;
SIGNAL rden_64x8_xhdl9 : std_logic;
SIGNAL wraddress_64x8_xhdl10 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl11 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl12 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl13 : std_logic;
SIGNAL wraddress_64x4x1_xhdl14 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl15 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl16 : std_logic;
SIGNAL rx_inter : std_logic;
BEGIN
-- wb_dat_o <= wb_dat_o_xhdl1;
-- wb_ack_o <= wb_ack_o_xhdl2;
tx_o <= tx_o_xhdl3;
bus_off_on <= bus_off_on_xhdl4;
irq_on <= irq_on_xhdl5;
clkout_o <= clkout_o_xhdl6;
data_64x8 <= data_64x8_xhdl7;
wren_64x8 <= wren_64x8_xhdl8;
rden_64x8 <= rden_64x8_xhdl9;
wraddress_64x8 <= wraddress_64x8_xhdl10;
rdaddress_64x8 <= rdaddress_64x8_xhdl11;
data_64x4 <= data_64x4_xhdl12;
wren_64x4x1 <= wren_64x4x1_xhdl13;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl14;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl15;
data_64x1 <= data_64x1_xhdl16;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl7 <= w_data_64x8 ;
wren_64x8_xhdl8 <= w_wren_64x8 ;
rden_64x8_xhdl9 <= w_rden_64x8 ;
wraddress_64x8_xhdl10 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl11 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl12 <= w_data_64x4 ;
wren_64x4x1_xhdl13 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl14 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl15 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl16 <= w_data_64x1 ;
-- Connecting can_registers module -- Mode register -- Command register -- Arbitration Lost Capture Register -- Error Code Capture Register -- Bus Timing 0 register -- Bus Timing 1 register -- Error Warning Limit register -- Rx Error Counter register -- Tx Error Counter register -- Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers
i_can_registers : can_registers
PORT MAP (
clk => clk_i,
rst => rst,
cs => cs,
we => we,
addr => addr,
data_in => data_in,
data_out => data_out_regs,
irq_n => irq_on_xhdl5,
sample_point => sample_point,
transmitting => transmitting,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => rx_err_cnt,
tx_err_cnt => tx_err_cnt,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
clear_data_overrun => open,
release_buffer => release_buffer,
abort_tx => abort_tx,
tx_request => tx_request,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
clkout => clkout_o_xhdl6,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12);
-- Connecting can_btl module -- Bus Timing 0 register -- Bus Timing 1 register -- Output signals from this module -- output from can_bsp module
i_can_btl : can_btl
PORT MAP (
clk => clk_i,
rst => rst,
rx => rx_sync,
tx => tx_o_xhdl3,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
rx_idle => rx_idle,
rx_inter => rx_inter,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
node_error_passive => node_error_passive);
-- xhdl_148 <= rx_err_cnt_dummy & rx_err_cnt(7 DOWNTO 0);
rx_err_cnt_dummy <= xhdl_148(8);
rx_err_cnt(7 DOWNTO 0) <= xhdl_148(7 DOWNTO 0);
-- xhdl_150 <= tx_err_cnt_dummy & tx_err_cnt(7 DOWNTO 0);
tx_err_cnt_dummy <= xhdl_150(8);
tx_err_cnt(7 DOWNTO 0) <= xhdl_150(7 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
-- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers -- Tx signal -- port connections for Ram
--64x8
--64x4
--64x1
i_can_bsp : can_bsp
PORT MAP (
clk => clk_i,
rst => rst,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
addr => addr,
data_in => data_in,
data_out => data_out_fifo,
fifo_selected => data_out_fifo_selected,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
release_buffer => release_buffer,
tx_request => tx_request,
abort_tx => abort_tx,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
rx_idle => rx_idle,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
not_first_bit_of_inter => not_first_bit_of_inter,
rx_inter => rx_inter,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => xhdl_148,
tx_err_cnt => xhdl_150,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12,
tx => tx_o_xhdl3,
tx_next => tx_next,
bus_off_on => bus_off_on_xhdl4,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Multiplexing wb_dat_o from registers and rx fifo
PROCESS (extended_mode, addr, reset_mode)
VARIABLE data_out_fifo_selected_xhdl203 : std_logic;
BEGIN
IF ((((extended_mode AND (NOT reset_mode)) AND CONV_STD_LOGIC((addr >= "00010000") AND (addr<="00011100"))) OR ((NOT extended_mode) AND CONV_STD_LOGIC((addr >= "00010100") AND (addr<="00011101")))) = '1') THEN
data_out_fifo_selected_xhdl203 := '1';
ELSE
data_out_fifo_selected_xhdl203 := '0';
END IF;
data_out_fifo_selected <= data_out_fifo_selected_xhdl203;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cs AND (NOT we)) = '1') THEN
IF (data_out_fifo_selected = '1') THEN
data_out <= data_out_fifo ;
ELSE
data_out <= data_out_regs ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i, rst)
BEGIN
IF (rst = '1') THEN
rx_sync_tmp <= '1';
rx_sync <= '1';
ELSIF (clk_i'EVENT AND clk_i = '1') THEN
rx_sync_tmp <= rx_i ;
rx_sync <= rx_sync_tmp ;
END IF;
END PROCESS;
-- cs_can_i <= '1' ;
-- Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
-- PROCESS (clk_i, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- cs_sync1 <= '0';
-- cs_sync2 <= '0';
-- cs_sync3 <= '0';
-- cs_sync_rst1 <= '0';
-- cs_sync_rst2 <= '0';
-- ELSIF (clk_i'EVENT AND clk_i = '1') THEN
-- cs_sync1 <= ((wb_cyc_i AND wb_stb_i) AND (NOT cs_sync_rst2)) AND cs_can_i ;
-- cs_sync2 <= cs_sync1 AND (NOT cs_sync_rst2) ;
-- cs_sync3 <= cs_sync2 AND (NOT cs_sync_rst2) ;
-- cs_sync_rst1 <= cs_ack3 ;
-- cs_sync_rst2 <= cs_sync_rst1 ;
-- END IF;
-- END PROCESS;
-- cs <= cs_sync2 AND (NOT cs_sync3) ;
--
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- cs_ack1 <= cs_sync3 ;
-- cs_ack2 <= cs_ack1 ;
-- cs_ack3 <= cs_ack2 ;
-- END IF;
-- END PROCESS;
-- Generating acknowledge signal
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- wb_ack_o_xhdl2 <= cs_ack2 AND (NOT cs_ack3) ;
-- END IF;
-- END PROCESS;
-- rst <= wb_rst_i ;
-- we <= wb_we_i ;
-- addr <= wb_adr_i ;
-- data_in <= wb_dat_i ;
-- wb_dat_o_xhdl1 <= data_out ;
END ARCHITECTURE RTL;
|
gpl-2.0
|
205f99e33d42167201ff80c457dd08e8
| 0.447487 | 4.179316 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/boards/terasic-de4/ddr2ctrl.vhd
| 2 | 38,923 |
-- megafunction wizard: %DDR2 SDRAM Controller with UniPHY v13.1%
-- GENERATION: XML
-- ddr2ctrl.vhd
-- Generated using ACDS version 13.1 162 at 2014.03.03.20:01:23
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end entity ddr2ctrl;
architecture rtl of ddr2ctrl is
component ddr2ctrl_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(13 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rdn : in std_logic := 'X'; -- rdn
oct_rup : in std_logic := 'X' -- rup
);
end component ddr2ctrl_0002;
begin
ddr2ctrl_inst : component ddr2ctrl_0002
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
afi_clk => afi_clk, -- afi_clk.clk
afi_half_clk => afi_half_clk, -- afi_half_clk.clk
afi_reset_n => afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
mem_a => mem_a, -- memory.mem_a
mem_ba => mem_ba, -- .mem_ba
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_ras_n => mem_ras_n, -- .mem_ras_n
mem_cas_n => mem_cas_n, -- .mem_cas_n
mem_we_n => mem_we_n, -- .mem_we_n
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
mem_odt => mem_odt, -- .mem_odt
avl_ready => avl_ready, -- avl.waitrequest_n
avl_burstbegin => avl_burstbegin, -- .beginbursttransfer
avl_addr => avl_addr, -- .address
avl_rdata_valid => avl_rdata_valid, -- .readdatavalid
avl_rdata => avl_rdata, -- .readdata
avl_wdata => avl_wdata, -- .writedata
avl_be => avl_be, -- .byteenable
avl_read_req => avl_read_req, -- .read
avl_write_req => avl_write_req, -- .write
avl_size => avl_size, -- .burstcount
local_init_done => local_init_done, -- status.local_init_done
local_cal_success => local_cal_success, -- .local_cal_success
local_cal_fail => local_cal_fail, -- .local_cal_fail
oct_rdn => oct_rdn, -- oct.rdn
oct_rup => oct_rup -- .rup
);
end architecture rtl; -- of ddr2ctrl
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2014 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_mem_if_ddr2_emif" version="13.1" >
-- Retrieval info: <generic name="RATE" value="Half" />
-- Retrieval info: <generic name="MEM_CLK_FREQ" value="400.0" />
-- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
-- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
-- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
-- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-- Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
-- Retrieval info: <generic name="MEM_FORMAT" value="UNBUFFERED" />
-- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
-- Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" />
-- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" />
-- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-- Retrieval info: <generic name="MEM_DQ_WIDTH" value="64" />
-- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-- Retrieval info: <generic name="MEM_CK_WIDTH" value="2" />
-- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
-- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-- Retrieval info: <generic name="NEXTGEN" value="true" />
-- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-- Retrieval info: <generic name="MEM_VERBOSE" value="true" />
-- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
-- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
-- Retrieval info: <generic name="MEM_BL" value="8" />
-- Retrieval info: <generic name="MEM_BT" value="Sequential" />
-- Retrieval info: <generic name="MEM_ASR" value="Manual" />
-- Retrieval info: <generic name="MEM_SRT" value="2x refresh rate" />
-- Retrieval info: <generic name="MEM_PD" value="Fast exit" />
-- Retrieval info: <generic name="MEM_DRV_STR" value="Full" />
-- Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-- Retrieval info: <generic name="MEM_RTT_NOM" value="50" />
-- Retrieval info: <generic name="MEM_ATCL" value="0" />
-- Retrieval info: <generic name="MEM_TCL" value="6" />
-- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-- Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-- Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="TIMING_TIS" value="375" />
-- Retrieval info: <generic name="TIMING_TIH" value="500" />
-- Retrieval info: <generic name="TIMING_TDS" value="250" />
-- Retrieval info: <generic name="TIMING_TDH" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSQ" value="200" />
-- Retrieval info: <generic name="TIMING_TQHS" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSCK" value="350" />
-- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
-- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
-- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
-- Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
-- Retrieval info: <generic name="TIMING_TDQSH" value="0.35" />
-- Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-- Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-- Retrieval info: <generic name="MEM_TINIT_US" value="200" />
-- Retrieval info: <generic name="MEM_TMRD_CK" value="5" />
-- Retrieval info: <generic name="MEM_TRAS_NS" value="40.0" />
-- Retrieval info: <generic name="MEM_TRCD_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TRP_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
-- Retrieval info: <generic name="MEM_TRFC_NS" value="127.5" />
-- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
-- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TWTR" value="3" />
-- Retrieval info: <generic name="MEM_TFAW_NS" value="37.5" />
-- Retrieval info: <generic name="MEM_TRRD_NS" value="7.5" />
-- Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" />
-- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Stratix IV" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="SPEED_GRADE" value="2" />
-- Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
-- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-- Retrieval info: <generic name="HARD_EMIF" value="false" />
-- Retrieval info: <generic name="HHP_HPS" value="false" />
-- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
-- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
-- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
-- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
-- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-- Retrieval info: <generic name="AVL_MAX_SIZE" value="8" />
-- Retrieval info: <generic name="BYTE_ENABLE" value="true" />
-- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
-- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
-- Retrieval info: <generic name="ADDR_ORDER" value="0" />
-- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-- Retrieval info: <generic name="CFG_REORDER_DATA" value="false" />
-- Retrieval info: <generic name="STARVE_LIMIT" value="10" />
-- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-- Retrieval info: <generic name="MULTICAST_EN" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-- Retrieval info: <generic name="DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="true" />
-- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="8" />
-- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="16" />
-- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-- Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
-- Retrieval info: <generic name="ENABLE_BONDING" value="false" />
-- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
-- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
-- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
-- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ" value="50.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-- Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" />
-- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
-- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
-- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
-- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
-- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
-- Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-- Retrieval info: <generic name="PHY_ONLY" value="false" />
-- Retrieval info: <generic name="SEQ_MODE" value="0" />
-- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-- Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
-- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-- Retrieval info: <generic name="CALIBRATION_MODE" value="Skip" />
-- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="1" />
-- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.6" />
-- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
-- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : ddr2ctrl.vho
-- RELATED_FILES: ddr2ctrl.vhd, ddr2ctrl_0002.v, ddr2ctrl_pll0.sv, ddr2ctrl_p0_clock_pair_generator.v, ddr2ctrl_p0_read_valid_selector.v, ddr2ctrl_p0_addr_cmd_datapath.v, ddr2ctrl_p0_reset.v, ddr2ctrl_p0_acv_ldc.v, ddr2ctrl_p0_memphy.sv, ddr2ctrl_p0_reset_sync.v, ddr2ctrl_p0_new_io_pads.v, ddr2ctrl_p0_fr_cycle_shifter.v, ddr2ctrl_p0_fr_cycle_extender.v, ddr2ctrl_p0_read_datapath.sv, ddr2ctrl_p0_write_datapath.v, ddr2ctrl_p0_simple_ddio_out.sv, ddr2ctrl_p0_phy_csr.sv, ddr2ctrl_p0_iss_probe.v, ddr2ctrl_p0_addr_cmd_pads.v, ddr2ctrl_p0_flop_mem.v, ddr2ctrl_p0.sv, ddr2ctrl_p0_altdqdqs.v, altdq_dqs2_ddio_3reg_stratixiv.sv, afi_mux_ddrx.v, ddr2ctrl_s0.v, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_mux_002.sv, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_mux_001.sv, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_mux.sv, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_demux_005.sv, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_demux_003.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_mux_005.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_mux_003.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_mux.sv, altera_merlin_arbitrator.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_demux_002.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_demux_001.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_demux.sv, altera_merlin_reorder_memory.sv, altera_merlin_traffic_limiter.sv, ddr2ctrl_s0_mm_interconnect_0_id_router_005.sv, ddr2ctrl_s0_mm_interconnect_0_id_router_003.sv, ddr2ctrl_s0_mm_interconnect_0_id_router.sv, ddr2ctrl_s0_mm_interconnect_0_addr_router_002.sv, ddr2ctrl_s0_mm_interconnect_0_addr_router_001.sv, ddr2ctrl_s0_mm_interconnect_0_addr_router.sv, altera_merlin_burst_uncompressor.sv, altera_merlin_slave_agent.sv, altera_merlin_master_agent.sv, ddr2ctrl_s0_irq_mapper.sv, ddr2ctrl_s0_mm_interconnect_0.v, altera_avalon_mm_bridge.v, altera_mem_if_sequencer_mem_no_ifdef_params.sv, rw_manager_inst_ROM_no_ifdef_params.v, rw_manager_ac_ROM_no_ifdef_params.v, rw_manager_write_decoder.v, rw_manager_read_datapath.v, rw_manager_ram_csr.v, rw_manager_ram.v, rw_manager_pattern_fifo.v, rw_manager_lfsr12.v, rw_manager_lfsr36.v, rw_manager_lfsr72.v, rw_manager_jumplogic.v, rw_manager_inst_ROM_reg.v, rw_manager_generic.sv, rw_manager_dm_decoder.v, rw_manager_di_buffer_wrap.v, rw_manager_di_buffer.v, rw_manager_datamux.v, rw_manager_data_decoder.v, rw_manager_data_broadcast.v, rw_manager_core.sv, rw_manager_bitcheck.v, rw_manager_ac_ROM_reg.v, rw_manager_ddr2.v, sequencer_data_mgr.sv, sequencer_phy_mgr.sv, sequencer_reg_file.sv, sequencer_scc_reg_file.v, sequencer_scc_acv_phase_decode.v, sequencer_scc_acv_wrapper.sv, sequencer_scc_sv_phase_decode.v, sequencer_scc_sv_wrapper.sv, sequencer_scc_siii_phase_decode.v, sequencer_scc_siii_wrapper.sv, sequencer_scc_mgr.sv, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v, altera_mem_if_sequencer_rst.sv, ddr2ctrl_dmaster.v, ddr2ctrl_c0.v, altera_mem_if_oct_stratixiv.sv, altera_mem_if_dll_stratixiv.sv, ddr2ctrl_mm_interconnect_0.v, altera_avalon_st_jtag_interface.v, altera_jtag_dc_streaming.v, altera_jtag_sld_node.v, altera_jtag_streaming.v, altera_pli_streaming.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_pipeline_base.v, altera_avalon_st_idle_remover.v, altera_avalon_st_idle_inserter.v, ddr2ctrl_dmaster_timing_adt.v, altera_avalon_sc_fifo.v, altera_avalon_st_bytes_to_packets.v, altera_avalon_st_packets_to_bytes.v, altera_avalon_packets_to_master.v, ddr2ctrl_dmaster_b2p_adapter.v, ddr2ctrl_dmaster_p2b_adapter.v, altera_reset_controller.v, altera_reset_synchronizer.v, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_axi_st_converter.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_controller_st_top.v, alt_mem_if_nextgen_ddr2_controller_core.sv, alt_mem_ddrx_mm_st_converter.v, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv
|
gpl-2.0
|
dd8aaea5298cf35c883444e23f27875f
| 0.611438 | 3.08301 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp605/ahb2mig_sp605.vhd
| 1 | 16,912 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_sp605
-- File: ahb2mig_sp605.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus, while
-- a second read-only port can be enabled for a VGA frame buffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_sp605 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
vgamst : integer := 0;
vgaburst : integer := 0
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbmi : out ahb_mst_in_type;
ahbmo : in ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem_p : in std_logic;
clk_mem_n : in std_logic;
clk_125 : out std_logic;
clk_50 : out std_logic
);
end ;
architecture rtl of ahb2mig_sp605 is
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
type reg2_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
end record;
type p2_if_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_bl : std_logic_vector(5 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
rd_en : std_logic;
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
end record;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
signal i : mcb_type;
signal p2 : p2_if_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
port2 : if vgamst /= 0 generate
comb2: process( rst_n_syn, r2, ahbmo, p2 )
variable v2 : reg2_type;
variable cmd_en : std_logic;
variable rd_en : std_logic;
begin
v2 := r2; cmd_en := '0'; rd_en := '0';
case r2.bstate is
when idle =>
if ahbmo.htrans(1) = '1' then
v2.bstate := start;
v2.hready := '0';
v2.haddr := ahbmo.haddr;
else v2.hready := '1'; end if;
v2.cmd_bl := (others => '0');
when start =>
if p2.cmd_full = '0' then
cmd_en := '1';
v2.cmd_bl := conv_std_logic_vector(vgaburst-1, 6);
v2.bstate := read1;
end if;
when read1 =>
v2.hready := '0';
if (r2.rd_cnt = "000000") then -- flush data from previous line
if (p2.rd_empty = '0') or ((r2.hready = '1') and (ahbmo.htrans /= "11")) then
v2.hrdata(31 downto 0) := p2.rd_data(15 downto 0) & p2.rd_data(31 downto 16);
v2.hready := '1';
if (p2.rd_empty = '0') then v2.cmd_bl := r2.cmd_bl - 1; rd_en := '1'; end if;
if (r2.cmd_bl = "000000") or (ahbmo.htrans /= "11") then
if (ahbmo.htrans = "10") and (r2.hready = '1') then
v2.bstate := start; v2.hready := '0';
v2.cmd_bl := (others => '0');
else
v2.bstate := idle;
end if;
if (p2.rd_empty = '1') then v2.rd_cnt := r2.cmd_bl + 1;
else v2.rd_cnt := r2.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
if (r2.rd_cnt /= "000000") and (p2.rd_empty = '0') then
rd_en := '1'; v2.rd_cnt := r2.rd_cnt - 1;
end if;
v2.haddr(1 downto 0) := "00";
if rst_n_syn = '0' then
v2.rd_cnt := "000000"; v2.bstate := idle; v2.hready := '1';
end if;
r2in <= v2;
p2.rd_en <= rd_en;
p2.cmd_bl <= v2.cmd_bl;
p2.cmd_en <= cmd_en;
p2.cmd_instr <= "001";
end process;
ahbmi.hrdata <= r2.hrdata;
ahbmi.hresp <= "00";
ahbmi.hgrant <= (others => '1');
ahbmi.hready <= r2.hready;
ahbmi.hirq <= (others => '0');
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r2 <= r2in;
end if;
end process;
end generate;
noport2 : if vgamst = 0 generate
p2.cmd_en <= '0';
p2.rd_en <= '0';
end generate;
MCB_inst : entity work.mig_38 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
-- C3_MEMCLK_PERIOD => 5000,
C3_RST_ACT_LOW => 1,
C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk_p => clk_mem_p,
c3_sys_clk_n => clk_mem_n,
c3_sys_rst_i => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error,
c3_p2_cmd_clk => clk_amba,
c3_p2_cmd_en => p2.cmd_en,
c3_p2_cmd_instr => p2.cmd_instr,
c3_p2_cmd_bl => p2.cmd_bl,
c3_p2_cmd_byte_addr => r2.haddr(29 downto 0),
c3_p2_cmd_empty => p2.cmd_empty,
c3_p2_cmd_full => p2.cmd_full,
c3_p2_rd_clk => clk_amba,
c3_p2_rd_en => p2.rd_en,
c3_p2_rd_data => p2.rd_data,
c3_p2_rd_full => p2.rd_full,
c3_p2_rd_empty => p2.rd_empty,
c3_p2_rd_count => p2.rd_count,
c3_p2_rd_overflow => p2.rd_overflow,
c3_p2_rd_error => p2.rd_error,
clk_125 => clk_125,
clk_50 => clk_50
);
end;
|
gpl-2.0
|
e7a8c583d837affafc1d1394c2181e05
| 0.519099 | 2.904844 | false | false | false | false |
ECE492W2014G4/G4Capstone
|
reverbBuffer.vhd
| 1 | 4,374 |
-- Design unit: reverb buffer
-- Authors : Aaron Arnason, Byron Maroney, Edrick De Guzman
-- reverbBuffer.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity reverbBuffer is
generic (
AUTO_CLOCK_CLOCK_RATE : string := "-1";
base_addr : std_logic_vector(31 downto 0) := X"00000000";
buffersize : std_logic_vector(31 downto 0) := X"000014A4"
);
port (
avm_m0_address : out std_logic_vector(31 downto 0);
avm_m0_read : out std_logic;
avm_m0_waitrequest : in std_logic := '0';
avm_m0_readdata : in std_logic_vector(15 downto 0) := (others => '0');
avm_m0_write : out std_logic;
avm_m0_writedata : out std_logic_vector(15 downto 0);
avm_m0_readdatavalid : in std_logic := '0';
dsp_ready : in std_logic;
dsp_in : in std_logic_vector(15 downto 0);
dsp_done : out std_logic;
dsp_out : out std_logic_vector(15 downto 0);
dsp_delayed_valid : out std_logic;
dsp_delayed : out std_logic_vector(15 downto 0);
clk : in std_logic := '0';
reset : in std_logic := '0'
);
end entity reverbBuffer;
architecture rtl of reverbBuffer is
type state is (idle, reading, reading2, writing);
signal current_state: state;
signal original,delayed: std_logic_vector(15 downto 0);
signal read_addr, read_delayed,write_addr: std_logic_vector(31 downto 0) := base_addr;
signal read_flag : std_logic := '0';
constant offset : std_logic_vector(31 downto 0) := std_logic_vector(signed(base_addr)+ 16);
begin
fsm: process(clk,reset)
begin
if reset = '0' then
write_addr <= base_addr;
read_addr <= offset;
current_state <= idle;
read_flag <= '0';
elsif rising_edge(clk) then
case current_state is
when idle =>
if dsp_ready = '1' then -- I have data avail.
avm_m0_write <= '1'; -- Telling the SDRAM we're writing to it.
current_state <= writing;
else
avm_m0_write <= '0';
end if;
when reading => -- Reading the SDRAM (normal read or write)
if avm_m0_waitrequest = '0' then
avm_m0_address <= read_addr;
dsp_out <= avm_m0_readdata;
if read_addr >= std_logic_vector(signed(buffersize) - 1) then
read_addr <= base_addr; -- To the beginning
elsif read_addr > write_addr then
read_addr <= std_logic_vector(signed(read_addr)+2);
else
read_addr <= std_logic_vector(signed(write_addr) - 2);
end if;
current_state <= reading2;
dsp_done <= '1';
else
dsp_done <= '0';
end if;
when reading2 => -- Reading the SDRAM (delayed read)
if avm_m0_waitrequest = '0' then
avm_m0_address <= read_delayed;
dsp_delayed <= avm_m0_readdata;
if read_delayed = std_logic_vector(signed(buffersize) - 1) then -- this line will overflow (intended behaviour).
read_delayed <= base_addr; -- To the beginning
avm_m0_read <= '0';
else
read_delayed <= std_logic_vector(signed(read_delayed) + 4096);
end if;
current_state <= idle;
dsp_delayed_valid <= '1';
else
dsp_delayed_valid <= '0';
end if;
when writing =>
if avm_m0_waitrequest = '0' then
avm_m0_address <= write_addr; -- can only write when waitrequest = 0
avm_m0_writedata <= dsp_in; -- Writes to SDRAM
if write_addr >= std_logic_vector(signed(buffersize)-1) then -- this line will overflow (intended behaviour).
write_addr <= base_addr; -- Reset the write addr
avm_m0_write <= '0'; -- Telling SDRAM we've stopped writing
avm_m0_read <= '1'; -- Read once SDRAM is full
read_flag <= '1';
else
write_addr <= std_logic_vector(signed(write_addr) + 2);
end if;
if read_flag = '1' then
current_state <= reading;
end if;
end if;
when others =>
current_state <= idle;
end case;
end if;
end process;
end architecture rtl;
|
gpl-3.0
|
1168f6217b0a714e83c08df60fc92c0b
| 0.54824 | 3.362029 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-xc3sd-1800/testbench.vhd
| 1 | 10,748 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 8 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk_vga : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(3 downto 0); -- dm
signal ddr_dqs : std_logic_vector(3 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(3 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(1 downto 0); -- bank address
signal ddr_dq : std_logic_vector(31 downto 0); -- data
signal ddr_dq2 : std_logic_vector(31 downto 0); -- data
signal ddr_odt : std_logic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(2 downto 0);
signal brdyn : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk_vga <= not clk_vga after 20 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => rst,
reset_o1 => rstn1,
reset_o2 => rstn2,
clk_in => clk,
clk_vga => clk_vga,
errorn => error,
-- PROM
address => address(23 downto 0),
data => data(31 downto 24),
romsn => romsn,
oen => oen,
writen => writen,
iosn => iosn,
testdata => data(23 downto 0),
-- DDR2
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_clk_fb_out => ddr_clk_fb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr_odt,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(3 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxdt(3 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- SVGA
vid_hsync => vid_hsync,
vid_vsync => vid_vsync,
vid_r => vid_r,
vid_g => vid_g,
vid_b => vid_b,
-- SPI flash select
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
-- Output signals for LEDs
led => led
);
ddr2mem : if (CFG_DDR2SP /= 0) generate
-- ddr2mem0 : for i in 0 to 1 generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => 1-i, bbits => 32, fname => sdramfile)
-- port map (DQ => ddr_dq2(i*16+15 downto i*16),
-- LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
-- UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
-- LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
-- RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba,
-- ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
-- CLK => ddr_clk(i), CLKB => ddr_clkb(i), UDM => ddr_dm(i*2+1));
-- end generate;
ddr0 : ddr2ram
generic map(width => 32, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2,
dqs => ddr_dqs);
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
prom0 : sram
generic map (index => 6, abits => 24, fname => promfile)
port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
etxdt(7 downto 4) <= "0000";
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
gpl-2.0
|
327ea65d6a3d8b5931974f4503bb00e9
| 0.536844 | 3.404498 | false | false | false | false |
aortiz49/MIPS-Processor
|
docs/MIPS_lib.vhd
| 1 | 2,063 |
library ieee;
use ieee.std_logic_1164.all;
package MIPS_lib is
--ALU CONSTANTS-----------------------------------------------------------------------------
constant F_SUM : std_logic_vector(3 downto 0) := "0010"; -- Add
constant F_SUB : std_logic_vector(3 downto 0) := "0110"; -- Subtract
constant F_AND : std_logic_vector(3 downto 0) := "0000"; -- AND
constant F_OR : std_logic_vector(3 downto 0) := "0001"; -- OR
constant F_NOR : std_logic_vector(3 downto 0) := "1100"; -- NOR
constant F_SLT : std_logic_vector(3 downto 0) := "0111"; -- Set if less than; signed
constant F_SLTU : std_logic_vector(3 downto 0) := "1111"; -- Set if less than; unsigned
--------------------------------------------------------------------------------------------
--ALU OP------------------------------------------------------------------------------------
constant LW_SW : std_logic_vector(2 downto 0) := "010"; -- add
constant BEQ : std_logic_vector(2 downto 0) := "001"; -- sub
constant ANDI : std_logic_vector(2 downto 0) := "000"; -- and
constant ORI : std_logic_vector(2 downto 0) := "011"; -- or
constant R_TYPE : std_logic_vector(2 downto 0) := "100"; -- R-type (varied)
--------------------------------------------------------------------------------------------
--ALU FUNCT---------------------------------------------------------------------------------
constant CTRL_ADD : std_logic_vector(5 downto 0) := "100000"; -- add
constant CTRL_SUB : std_logic_vector(5 downto 0) := "100010"; -- subtract
constant CTRL_AND : std_logic_vector(5 downto 0) := "100100"; -- and
constant CTRL_OR : std_logic_vector(5 downto 0) := "100101"; -- or
constant CTRL_NOR : std_logic_vector(5 downto 0) := "100111"; -- nor
constant CTRL_SLT : std_logic_vector(5 downto 0) := "101010"; -- slt
constant CTRL_SLTU : std_logic_vector(5 downto 0) := "101011"; -- sltu
--------------------------------------------------------------------------------------------
END MIPS_lib;
|
mit
|
f982fe51061cd74a5c2e679be051af5a
| 0.456617 | 3.233542 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/spw/comp/spwcomp.vhd
| 1 | 31,498 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spwcomp is
component grspwc2 is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspwc is
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
tech : integer;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
rmapact : out std_ulogic
);
end component;
component grspwc_axcelerator is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_unisim is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_codec_core is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
inputtest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx fifo signals
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(9 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(9 downto 0);
rxaccess : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx fifo signals
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(8 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(8 downto 0);
txaccess : out std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickin_busy : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
credcnt : out std_logic_vector(5 downto 0);
ocredcnt : out std_logic_vector(5 downto 0);
--misc
powerdown : out std_ulogic;
powerdownrx : out std_ulogic;
-- input timing testing
testdi : in std_logic_vector(1 downto 0) := "00";
testsi : in std_logic_vector(1 downto 0) := "00";
testinput : in std_ulogic := '0'
);
end component;
component grspw2_gen is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
techfifo : integer range 0 to 1 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspw_codec_gen is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--misc
merror : out std_ulogic
);
end component;
end package;
|
gpl-2.0
|
f3fcd1dd47ef37b3c9c18b923399b684
| 0.530732 | 3.670668 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml50x/ahb2mig_ml50x.vhd
| 2 | 23,812 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml50x is
constant BANK_WIDTH : integer := 2; -- # of memory bank addr bits.
constant CKE_WIDTH : integer := 2; -- # of memory clock enable outputs.
constant CLK_WIDTH : integer := 2; -- # of clock outputs.
constant COL_WIDTH : integer := 10; -- # of memory column bits.
constant CS_NUM : integer := 1; --2; -- # of separate memory chip selects.
constant CS_WIDTH : integer := 1; --2; -- # of total memory chip selects.
constant CS_BITS : integer := 0; --1; -- set to log2(CS_NUM) (rounded up).
constant DM_WIDTH : integer := 8; -- # of data mask bits.
constant DQ_WIDTH : integer := 64; -- # of data width.
constant DQ_PER_DQS : integer := 8; -- # of DQ data bits per strobe.
constant DQS_WIDTH : integer := 8; -- # of DQS strobes.
constant DQ_BITS : integer := 6; -- set to log2(DQS_WIDTH*DQ_PER_DQS).
constant DQS_BITS : integer := 3; -- set to log2(DQS_WIDTH).
constant ODT_WIDTH : integer := 1; -- # of memory on-die term enables.
constant ROW_WIDTH : integer := 13; -- # of memory row and # of addr bits.
constant APPDATA_WIDTH : integer := 128; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 31; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#F00#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component mig_36_1
generic(
BANK_WIDTH : integer := 2;
-- # of memory bank addr bits.
CKE_WIDTH : integer := 1;
-- # of memory clock enable outputs.
CLK_WIDTH : integer := 2;
-- # of clock outputs.
COL_WIDTH : integer := 10;
-- # of memory column bits.
CS_NUM : integer := 1;
-- # of separate memory chip selects.
CS_WIDTH : integer := 1;
-- # of total memory chip selects.
CS_BITS : integer := 0;
-- set to log2(CS_NUM) (rounded up).
DM_WIDTH : integer := 8;
-- # of data mask bits.
DQ_WIDTH : integer := 64;
-- # of data width.
DQ_PER_DQS : integer := 8;
-- # of DQ data bits per strobe.
DQS_WIDTH : integer := 8;
-- # of DQS strobes.
DQ_BITS : integer := 6;
-- set to log2(DQS_WIDTH*DQ_PER_DQS).
DQS_BITS : integer := 3;
-- set to log2(DQS_WIDTH).
ODT_WIDTH : integer := 1;
-- # of memory on-die term enables.
ROW_WIDTH : integer := 13;
-- # of memory row and # of addr bits.
ADDITIVE_LAT : integer := 0;
-- additive write latency.
BURST_LEN : integer := 4;
-- burst length (in double words).
BURST_TYPE : integer := 0;
-- burst type (=0 seq; =1 interleaved).
CAS_LAT : integer := 3;
-- CAS latency.
ECC_ENABLE : integer := 0;
-- enable ECC (=1 enable).
APPDATA_WIDTH : integer := 128;
-- # of usr read/write data bus bits.
MULTI_BANK_EN : integer := 1;
-- Keeps multiple banks open. (= 1 enable).
TWO_T_TIME_EN : integer := 1;
-- 2t timing for unbuffered dimms.
ODT_TYPE : integer := 1;
-- ODT (=0(none),=1(75),=2(150),=3(50)).
REDUCE_DRV : integer := 0;
-- reduced strength mem I/O (=1 yes).
REG_ENABLE : integer := 0;
-- registered addr/ctrl (=1 yes).
TREFI_NS : integer := 7800;
-- auto refresh interval (ns).
TRAS : integer := 40000;
-- active->precharge delay.
TRCD : integer := 15000;
-- active->read/write delay.
TRFC : integer := 105000;
-- refresh->refresh, refresh->active delay.
TRP : integer := 15000;
-- precharge->command delay.
TRTP : integer := 7500;
-- read->precharge delay.
TWR : integer := 15000;
-- used to determine write->precharge.
TWTR : integer := 10000;
-- write->read delay.
HIGH_PERFORMANCE_MODE : boolean := TRUE;
-- # = TRUE, the IODELAY performance mode is set
-- to high.
-- # = FALSE, the IODELAY performance mode is set
-- to low.
SIM_ONLY : integer := 0;
-- = 1 to skip SDRAM power up delay.
DEBUG_EN : integer := 0;
-- Enable debug signals/controls.
-- When this parameter is changed from 0 to 1,
-- make sure to uncomment the coregen commands
-- in ise_flow.bat or create_ise.bat files in
-- par folder.
CLK_PERIOD : integer := 5000;
-- Core/Memory clock period (in ps).
DLL_FREQ_MODE : string := "HIGH";
-- DCM Frequency range.
CLK_TYPE : string := "SINGLE_ENDED";
-- # = "DIFFERENTIAL " ->; Differential input clocks ,
-- # = "SINGLE_ENDED" -> Single ended input clocks.
NOCLK200 : boolean := FALSE;
-- clk200 enable and disable
RST_ACT_LOW : integer := 1
-- =1 for active low reset, =0 for active high.
);
port(
ddr2_dq : inout std_logic_vector((DQ_WIDTH-1) downto 0);
ddr2_a : out std_logic_vector((ROW_WIDTH-1) downto 0);
ddr2_ba : out std_logic_vector((BANK_WIDTH-1) downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_cs_n : out std_logic_vector((CS_WIDTH-1) downto 0);
ddr2_odt : out std_logic_vector((ODT_WIDTH-1) downto 0);
ddr2_cke : out std_logic_vector((CKE_WIDTH-1) downto 0);
ddr2_dm : out std_logic_vector((DM_WIDTH-1) downto 0);
sys_clk : in std_logic;
idly_clk_200 : in std_logic;
sys_rst_n : in std_logic;
phy_init_done : out std_logic;
rst0_tb : out std_logic;
clk0_tb : out std_logic;
app_wdf_afull : out std_logic;
app_af_afull : out std_logic;
rd_data_valid : out std_logic;
app_wdf_wren : in std_logic;
app_af_wren : in std_logic;
app_af_addr : in std_logic_vector(30 downto 0);
app_af_cmd : in std_logic_vector(2 downto 0);
rd_data_fifo_out : out std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_data : in std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_mask_data : in std_logic_vector((APPDATA_WIDTH/8-1) downto 0);
ddr2_dqs : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_dqs_n : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0)
);
end component ;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml50x.all;
entity ahb2mig_ml50x is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml50x is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(63 downto 0) & rdata(127 downto 64);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "01" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "10" => va.hrdata(31 downto 0) := rdata(127 downto 96);
when others => va.hrdata(31 downto 0) := rdata(95 downto 64);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
migi.app_addr <= "00000" & ra.acc.haddr(28 downto 5) & "00";
ddr_ctrl : process(rst_ddr, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask(15 downto 0) := ra.write(2) & ra.write(3) & ra.write(0) & ra.write(1);
app_wdf_data := (others => '0');
app_wdf_data(127 downto 0) := ra.hwdata(2) & ra.hwdata(3) & ra.hwdata(0) & ra.hwdata(1);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if (startsd = '1') and (migo.app_af_afull = '0') then
if ra.acc.hwrite = '0' then
v.dstate := dread; app_en := '1';
elsif migo.app_wdf_afull = '0' then
v.dstate := dwrite; app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 0) := migo.app_rd_data(127 downto 0);
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(255 downto 128) := migo.app_rd_data(127 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
app_wdf_mask(15 downto 0) := ra.write(6) & ra.write(7) & ra.write(4) & ra.write(5);
app_wdf_data(127 downto 0) := ra.hwdata(6) & ra.hwdata(7) & ra.hwdata(4) & ra.hwdata(5);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
gpl-2.0
|
c3aa093c25afa96e8c0486ad5345fc06
| 0.524903 | 3.594807 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/admout.vhd
| 3 | 4,183 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
library altera;
use altera.all;
entity admout is
port(
clk : in std_logic; -- clk0
dm_h : in std_logic;
dm_l : in std_logic;
dm_pad : out std_logic -- DQ pad
);
end;
architecture rtl of admout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic--;
--dfflo : out std_logic;
--dffhi : out std_logic;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dm_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DM output register --------------------------------------------------------------
dm_reg0 : stratixiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "true",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => dm_l,
datainhi => dm_h,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dm_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DM) ------------------------------------------------------------------
dm_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dm_reg,
--oe => vcc,
--dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dm_pad,
obar => open
);
end;
|
gpl-2.0
|
145d07834a505f5d07830167f48f91e1
| 0.398996 | 4.361835 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/memctrl/srctrl.vhd
| 1 | 16,152 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: srctrl
-- File: srctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Marko Isomaki - Gaisler Research
-- Description: 32-bit SRAM memory controller with read-modify-write
-- Supports also 64-bit AHB read/write accesses
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity srctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0; -- read-modify-write enable
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of srctrl is
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SRCTRL, 0, VERSION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ramaddr, '1', '1', rammask),
6 => ahb_membar(ioaddr, '0', '0', iomask),
others => zero32);
type srcycletype is (idle, read1, read2, write1, write2, write3, rmw1, rmw2, rmw3);
type prom8cycletype is (idle, read1, read2);
function byteswap (rdata, wdata : std_logic_vector(31 downto 0); addr, size : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
variable a : std_logic_vector(1 downto 0);
begin
tmp := rdata; a := addr(1 downto 0);
if size(0) = '0' then
case a is
when "00" => tmp(31 downto 24) := wdata(31 downto 24);
when "01" => tmp(23 downto 16) := wdata(23 downto 16);
when "10" => tmp(15 downto 8) := wdata(15 downto 8);
when others => tmp(7 downto 0) := wdata(7 downto 0);
end case;
else
if addr(1) = '0' then tmp(31 downto 16) := wdata(31 downto 16);
else tmp(15 downto 0) := wdata(15 downto 0); end if;
end if;
return(tmp);
end;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 2);
bdrive : std_ulogic;
nbdrive : std_ulogic;
srstate : srcycletype;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(63 downto 0);
hwdata : std_logic_vector(63 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
read : std_ulogic;
oen : std_ulogic;
ramsn : std_ulogic;
romsn : std_ulogic;
vramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
vromsn : std_logic_vector(1 downto 0);
writen : std_ulogic;
wen : std_logic_vector(3 downto 0);
mben : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
iosn : std_ulogic;
-- 8-bit prom access
pr8state : prom8cycletype;
data8 : std_logic_vector(23 downto 0);
ready8 : std_ulogic;
bwidth : std_logic_vector(1 downto 0);
end record;
signal r, ri : reg_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sri, rbdrive)
variable v : reg_type; -- local variables for registers
variable dqm : std_logic_vector(3 downto 0);
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable roms : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hrdata : std_logic_vector(63 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable vramws, vromws, viows : std_logic_vector(3 downto 0);
-- 8-bit prom access
variable romsn : std_ulogic;
variable bdrive : std_ulogic;
variable oen : std_ulogic;
variable writen : std_ulogic;
variable hready : std_ulogic;
variable ws : std_logic_vector(3 downto 0);
variable prom8sel : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable sbdrive : std_ulogic;
begin
-- Variable default settings to avoid latches
v := r; v.hresp := HRESP_OKAY; v.hrdata(31 downto 0) := sri.data;
hrdata := r.hrdata;
vramws := conv_std_logic_vector(ramws, 4); vbdrive := rbdrive;
vromws := conv_std_logic_vector(romws, 4);
viows := conv_std_logic_vector(iows, 4);
v.bwidth := sri.bwidth;
if (prom8en = 1) and (r.bwidth = "00") then prom8sel := '1';
else prom8sel := '0'; end if;
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans; v.hburst := ahbsi.hburst;
v.hsel := '1'; v.hmbsel := ahbsi.hmbsel(0 to 2);
v.haddr := ahbsi.haddr; v.hready := '0';
else
v.hsel := '0';
end if;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
end if;
-- chip-select decoding
adec := haddr(banksz+14 downto banksz+13);
rams := '0' & decode(adec);
case srbanks is
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others => null;
end case;
roms := haddr(romasel) & not haddr(romasel);
-- generate write strobes
if rmw = 1 then dqm := "0000"; else
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "1110";
when "01" => dqm := "1101";
when "10" => dqm := "1011";
when others => dqm := "0111";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "1100"; else dqm := "0011"; end if;
when others => dqm := "0000";
end case;
end if;
-- main FSM
case r.srstate is
when idle =>
if (v.hsel = '1') and not
(((v.ramsn or r.romsn) = '0') or ((v.romsn or r.ramsn) = '0')) and not
((v.hmbsel(0) and not hwrite and prom8sel) = '1' and prom8en = 1)
then
v.hready := '0';
v.ramsn := not v.hmbsel(1); v.romsn := not v.hmbsel(0);
v.iosn := not v.hmbsel(2);
v.read := not hwrite;
if hwrite = '1' then
if (rmw = 1) and (hsize(1) = '0') and (v.hmbsel(1) = '1') then
v.srstate := rmw1; v.read := '1';
else v.srstate := write1; end if;
elsif ahbsi.htrans = "10" then v.srstate := read1;
else v.srstate := read2; end if;
v.oen := not v.read;
else
v.ramsn := '1'; v.romsn := '1'; v.bdrive := '1'; v.oen := '1';
v.iosn := '1';
end if;
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
when read1 =>
v.srstate := read2;
v.hrdata(63 downto 32) := r.hrdata(31 downto 0);
when read2 =>
v.ws := r.ws -1; v.oen := '0';
if r.ws = "0000" then
if (r.size /= "11") or (r.haddr(2) = '1') or (AHBDW = 32) then
v.srstate := idle; v.hready := '1'; v.haddr := ahbsi.haddr;
v.ramsn := not (ahbsi.hmbsel(1) and ahbsi.htrans(1));
v.romsn := not (ahbsi.hmbsel(0) and ahbsi.htrans(1));
v.oen := not (ahbsi.hsel(hindex) and ahbsi.htrans(1) and not ahbsi.hwrite);
else
v.srstate := read1; v.haddr(2) := '1';
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
end if;
end if;
when write1 =>
if r.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
v.hwdata(31 downto 0) := ahbsi.hwdata(31 downto 0);
if not ((r.size = "11") and (r.haddr(2) = '1')) then
v.hwdata(63 downto 32) := ahbsi.hwdata(63 mod AHBDW downto 32 mod AHBDW);
end if;
when write2 =>
if r.ws = "0000" then
if (r.size /= "11") or (r.haddr(2) = '1') or (AHBDW = 32) then
v.srstate := idle; v.bdrive := '1'; v.hready := '1';
else
v.srstate := write3;
end if;
v.wen := "1111"; v.writen := '1';
end if;
v.ws := r.ws -1;
when write3 =>
v.haddr(2) := '1'; v.hwdata(63 downto 32) := r.hwdata(31 downto 0);
v.srstate := write1;
when rmw1 =>
if (rmw = 1) then v.oen := '0';
v.srstate := rmw2;
v.hwdata(31 downto 0) := ahbsi.hwdata(31 downto 0);
v.hwdata(63 downto 32) := ahbsi.hwdata(63 mod AHBDW downto 32 mod AHBDW);
end if;
when rmw2 =>
if (rmw = 1) then
v.ws := r.ws -1;
if r.ws = "0000" then v.oen := '1'; v.srstate := rmw3; end if;
end if;
when rmw3 =>
if (rmw = 1) then
v.hwdata(63 downto 32) := byteswap(r.hrdata(31 downto 0), r.hwdata(63 downto 32), r.haddr, r.size);
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
end if;
if r.romsn = '0' then v.ws := vromws; else v.ws := vramws; end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- 8-bit PROM access FSM
if prom8en = 1 then
hready := '0'; ws := v.ws; v.ready8 := '0';
bdrive := '1'; oen := '1'; writen := '1'; romsn := '1';
if r.ready8 = '1' then
v.data8 := r.data8(15 downto 0) & r.hrdata(31 downto 24);
case r.size is
when "00" => hrdata(31 downto 0) := r.hrdata(31 downto 24) &
r.hrdata(31 downto 24) & r.hrdata(31 downto 24) & r.hrdata(31 downto 24);
when "01" => hrdata(31 downto 0) := r.data8(7 downto 0) & r.hrdata(31 downto 24) &
r.data8(7 downto 0) & r.hrdata(31 downto 24);
when others => hrdata(31 downto 0) := r.data8 & r.hrdata(31 downto 24);
end case;
end if;
case r.pr8state is
when idle =>
if ( (v.hsel and v.hmbsel(0) and not hwrite and prom8sel) = '1')
then
romsn := '0'; v.pr8state := read1; oen := '0';
end if;
when read1 =>
oen := '0'; romsn := '0'; v.pr8state := read2; ws := vromws;
when read2 =>
oen := '0'; ws := r.ws - 1; romsn := '0';
if r.ws = "0000" then
v.haddr(1 downto 0) := r.haddr(1 downto 0) + 1;
if (r.size = "00") or ((r.size = "01") and (r.haddr(0) = '1'))
or r.haddr(1 downto 0) = "11"
then
hready := '1'; v.pr8state := idle; oen := '1';
else
v.pr8state := read1;
end if;
v.ready8 := '1';
end if;
when others =>
v.pr8state := idle;
end case;
v.romsn := v.romsn and romsn; v.bdrive := v.bdrive and bdrive;
v.oen := v.oen and oen; v.writen := v.writen and writen;
v.hready := v.hready or hready; v.ws := ws;
end if;
if (v.oen or v.ramsn) = '0' then v.ramoen := not rams;
else v.ramoen := (others => '1'); end if;
if v.romsn = '0' then v.vromsn := not roms;
else v.vromsn := (others => '1'); end if;
if v.ramsn = '0' then v.vramsn := not rams;
else v.vramsn := (others => '1'); end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wen; end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then sbdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else sbdrive := r.bdrive; vbdrive := (others => v.bdrive); end if;
if (r.size /= "11") or (AHBDW = 32) then hrdata(63 downto 32) := hrdata(31 downto 0); end if;
-- reset
if rst = '0' then
v.srstate := idle; v.hsel := '0'; v.writen := '1';
v.wen := (others => '1'); v.hready := '1'; v.read := '1';
v.ws := (others => '0');
if prom8en = 1 then v.pr8state := idle; end if;
end if;
ribdrive <= vbdrive;
ri <= v;
sro.address <= r.haddr;
sro.bdrive <= (others => sbdrive);
sro.vbdrive <= rbdrive;
sro.ramsn <= "111" & r.vramsn;
sro.ramoen <= "111" & r.ramoen;
sro.romsn <= "111111" & r.vromsn;
sro.iosn <= r.iosn;
sro.wrn <= r.wen;
sro.oen <= r.oen;
sro.read <= r.read;
sro.data <= r.hwdata(63 downto 32);
sro.writen <= r.writen;
sro.ramn <= r.ramsn;
sro.romn <= r.romsn;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
end process;
sdo.sdcsn <= "11"; sdo.sdcke <= "11"; sdo.sdwen <= '1'; sdo.rasn <= '1';
sdo.casn <= '1'; sdo.dqm <= (others => '1'); sdo.address <= (others => '0');
sdo.data <= (others => '0'); sdo.conf <= (others => '0'); sdo.odt <= (others => '0');
sdo.cal_pll <= (others => '0'); sdo.cal_inc <= (others => '0');
sdo.cal_en <= (others => '0'); sdo.sdck <= (others => '0');
sdo.ba <= (others => '0'); sdo.cb <= (others => '0');
sdo.vbdrive <= (others => '0'); sdo.qdrive <= '0'; sdo.bdrive <= '0';
sdo.oct <= '0';
sdo.ce <= '0'; sdo.moben <= '0'; sdo.cal_rst <= '0';
sdo.xsdcsn <= (others => '0'); sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0'); sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0'); sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0'); sdo.regwrite <= (others => '0');
sro.mben <= r.mben;
sro.sdram_en <= '0';
sro.rs_edac_en <= '0';
sro.ce <= '0';
sro.sddata <= (others => '0');
sro.svbdrive <= (others => '0');
sro.sa <= (others => '0');
sro.cb <= (others => '0');
sro.scb <= (others => '0');
sro.vcdrive <= (others => '0');
sro.svcdrive <= (others => '0');
sro.scb <= (others => '0');
regs : process(clk,rst)
begin
if rising_edge(clk) then r <= ri; rbdrive <= ribdrive; end if;
if rst = '0' then
r.ramsn <= '1';
r.romsn <= '1'; r.oen <= '1';
r.bdrive <= '1'; r.nbdrive <= '0';
r.vramsn <= (others => '1'); r.vromsn <= (others => '1');
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("srctrl" & tost(hindex) &
": 32-bit PROM/SRAM controller rev " & tost(VERSION));
-- pragma translate_on
end;
|
gpl-2.0
|
16171c4864ee71fd669e08401e2ada7a
| 0.558754 | 3.070139 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-115/leon3mp.vhd
| 1 | 16,967 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n: inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.15",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
gpl-2.0
|
153c0873a9dd9698b26a4fd5af649e60
| 0.533329 | 3.765424 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml403/testbench.vhd
| 1 | 9,832 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(20 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 3);
signal vid_g : std_logic_vector(7 downto 3);
signal vid_b : std_logic_vector(7 downto 3);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
gpio <= (others => 'L');
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, plb_error, opb_error, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n, sram_flash_we_n,
flash_ce, sram_clk, sram_clk_fb, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
ddr0 : ddrram
generic map(width => 32, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
|
gpl-2.0
|
a5e3c7d42374342addb3fb1e92701079
| 0.609642 | 3.00489 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-3s1500/leon3mp.vhd
| 1 | 30,423 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design for AVNET Spartan3 Evaluation Board
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.can.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
mezz : integer := CFG_ADS_DAU_MEZZ
);
port (
clk_66mhz : in std_logic;
clk_socket : in std_logic;
leds : out std_logic_vector(7 downto 0);
switches : in std_logic_vector(5 downto 0);
sram_a : out std_logic_vector(24 downto 0);
sram_ben_l : out std_logic_vector(0 to 3);
sram_cs_l : out std_logic_vector(1 downto 0);
sram_oe_l : out std_logic;
sram_we_l : out std_logic;
sram_dq : inout std_logic_vector(31 downto 0);
flash_cs_l : out std_logic;
flash_rst_l : out std_logic;
iosn : out std_logic;
sdclk : out std_logic;
rasn : out std_logic;
casn : out std_logic;
sdcke : out std_logic;
sdcsn : out std_logic;
tx : out std_logic;
rx : in std_logic;
can_txd : out std_logic;
can_rxd : in std_logic;
phy_txck : in std_logic;
phy_rxck : in std_logic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxdv : in std_logic;
phy_rxer : in std_logic;
phy_col : in std_logic;
phy_crs : in std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txen : out std_logic;
phy_txer : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic; -- ethernet PHY interface
phy_reset_l : inout std_logic;
video_clk : in std_logic;
comp_sync : out std_logic;
horiz_sync : out std_logic;
vert_sync : out std_logic;
blank : out std_logic;
video_out : out std_logic_vector(23 downto 0);
msclk : inout std_logic;
msdata : inout std_logic;
kbclk : inout std_logic;
kbdata : inout std_logic;
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant mahbmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+
CFG_SVGA_ENABLE + CFG_GRETH+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(23 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal abus : std_logic_vector(17 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clk, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_logic;
signal pllref, errorn, pci_rst : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal dac_clk, clk25, clk_66mhzl, pci_lclk : std_logic;
signal can_ltx, can_lrx : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk : signal is true;
attribute syn_preserve of clk : signal is true;
attribute keep of clk : signal is true;
signal switchesl : std_logic_vector(5 downto 0);
constant padlevel : integer := 0;
constant IOAEN : integer := CFG_CAN+CFG_GRPCI2_MASTER;
constant BOARD_FREQ : integer := 66667; -- input frequency in KHz
constant CPU_FREQ : integer := (BOARD_FREQ * CFG_CLKMUL) / CFG_CLKDIV;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
---------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0'); pllref <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= pllref;
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET, CFG_PCIDLL, CFG_PCISYSCLK, 66000)
port map (clk_66mhzl, pci_lclk, clk, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 8)
port map (sdclk, sdclkl);
clk_pad : clkpad generic map (tech => padtech, level => padlevel)
port map (clk_66mhz, clk_66mhzl);
clk2_pad : clkpad generic map (tech => padtech, level => padlevel)
port map (clk_socket, open);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
rst0 : rstgen generic map (acthigh => 1)
port map (switchesl(4), clk, cgo.clklock, rstn, rstraw);
flash_rst_l_pad : outpad generic map (level => padlevel, tech => padtech)
port map (flash_rst_l, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
nahbm => mahbmax, nahbs => 8, ioen => IOAEN)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
dsui.break <= switchesl(5);
dsui.enable <= '1';
dsuact_pad : outpad generic map (tech => padtech, level => padlevel)
port map (leds(1), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
dcompads : if CFG_AHB_UART = 1 generate
dsurx_pad : inpad generic map (tech => padtech, level => padlevel)
port map (rx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => padlevel)
port map (tx, duo.txd);
u1i.rxd <= '1';
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : entity work.mctrl_avnet generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
pageburst => CFG_MCTRL_PAGE, avnetmezz => mezz)
port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- no SDRAM controller
-- sdwen_pad : outpad generic map (tech => padtech)
-- port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (rasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (casn, sdo.casn);
-- sddqm_pad : outpadv generic map (width =>4, tech => padtech)
-- port map (sddqm, sdo.dqm);
end generate;
sdcke_pad : outpad generic map (tech => padtech)
port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdcsn, sdo.sdcsn(0));
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
port map (sram_cs_l, vcc(1 downto 0));
end generate;
mgpads : if CFG_MCTRL_LEON2 /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (level => padlevel, width => 25, tech => padtech)
port map (sram_a, memo.address(24 downto 0));
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
port map (sram_cs_l, memo.ramsn(1 downto 0));
flash_pad : outpad generic map (level => padlevel, tech => padtech)
port map (flash_cs_l, memo.romsn(0));
oen_pad : outpad generic map (level => padlevel, tech => padtech)
port map (sram_oe_l, memo.oen);
iosn_pad : outpad generic map (level => padlevel, tech => padtech)
port map (iosn, memo.iosn);
wri_pad : outpad generic map (level => padlevel, tech => padtech)
port map (sram_we_l, memo.writen);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (level => padlevel, tech => padtech, width => 8)
port map (sram_dq(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
ben_pad : outpadv generic map (level => padlevel, width => 4, tech => padtech)
port map (sram_ben_l, memo.mben);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clk, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clk, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua1pads : if CFG_AHB_UART = 0 generate
rx_pad : inpad generic map (tech => padtech, level => padlevel)
port map (rx, u1i.rxd);
tx_pad : outpad generic map (tech => padtech, level => padlevel)
port map (tx, u1o.txd);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clk, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clk, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clk, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (kbclk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (kbdata, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (msclk,mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (msdata, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clk, clk25, apbi, apbo(6), vgao);
vgaclk0 : entity techmap.clkmul_virtex2 generic map (3, 8) -- 25 MHz video clock
port map (rstn, clk, dac_clk, open);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 39722, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 5)
port map(rstn, clk, clk25, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
clk25 <= not dac_clk;
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
video_clk_pad : inpad generic map (tech => padtech)
port map (video_clk, dac_clk);
blank_pad : outpad generic map (tech => padtech)
port map (blank, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (comp_sync, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vert_sync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (horiz_sync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(23 downto 16), vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(15 downto 8), vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(7 downto 0), vgao.video_out_b);
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
grpci2xt : if (CFG_GRPCI2_TARGET) /= 0 and (CFG_GRPCI2_MASTER+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 9, paddr => 9, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clk, pciclk, pci_dirq, pcii, pcio, apbi, apbo(9), ahbsi, open, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbmi,
open, open, open, open, open);
end generate;
grpci2xmt : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) > 1 and (CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 9, paddr => 9, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clk, pciclk, pci_dirq, pcii, pcio, apbi, apbo(9), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 9, paddr => 9, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clk, pciclk, pci_dirq, pcii, pcio, apbi, apbo(9), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1),
open, open, open, open);
end generate;
end generate;
pcipads0 : pcipads
generic map (padtech => padtech, noreset => 1, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clk, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 0) generate -- no eth
etho <= eth_out_none;
end generate;
emdio_pad : iopad generic map (tech => padtech, level => padlevel)
port map (phy_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
port map (phy_txck, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
port map (phy_rxck, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => padlevel, width => 4)
port map (phy_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_rxer, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, level => padlevel, width => 4)
port map (phy_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => padlevel)
port map ( phy_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel)
port map (phy_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel)
port map (phy_mdc, etho.mdc);
phy_reset_pad : iodpad generic map (tech => padtech, level => padlevel)
port map (phy_reset_l, rstn, pci_rst);
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clk, ahbsi, ahbso(6), can_lrx, can_ltx );
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clk, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Misc ----------------------------------------------------------
-----------------------------------------------------------------------
errorn <= not dbgo(0).error;
led0_pad : outpad generic map (level => padlevel, tech => padtech)
port map (leds(0), errorn);
led2_7_pad : outpadv generic map (level => padlevel, width => 6, tech => padtech)
port map (leds(7 downto 2), gnd(5 downto 0));
disp_seg1_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
port map (disp_seg1, gnd(7 downto 0));
disp_seg2_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
port map (disp_seg2, gnd(7 downto 0));
switche_pad : inpadv generic map (tech => padtech, level => padlevel, width => 6)
port map (switches, switchesl);
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG-1+CFG_SVGA_ENABLE) <= ahbm_none;
-- end generate;
nap0 : for i in 12 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet Spartan3-1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
c395fe142f1fff1ec41409c64ff51cb7
| 0.572725 | 3.439959 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/grgates.vhd
| 1 | 6,916 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Various
-- File: grgates.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Various gates with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.allclkgen.all;
entity grmux2 is generic( tech : integer := inferred; imp : integer := 0);
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end;
architecture rtl of grmux2 is
component ut130hbd_mux2
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component mux2_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component mux2_rhs65
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
constant has_mux2 : tech_ability_type :=
( rhlib18t => 1, ut130 => 1, ut90 => 1, rhs65 => 1, others => 0);
begin
y0 : if has_mux2(tech) = 1 generate
rhlib : if tech = rhlib18t generate
x0 : clkmux_rhlib18t port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
ut13 : if tech = ut130 generate
x0 : ut130hbd_mux2 port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
ut90n : if tech = ut90 generate
x0 : mux2_ut90nhbd port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
rhs65n: if tech=rhs65 generate
x0 : mux2_rhs65 port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
end generate;
y1 : if has_mux2(tech) = 0 generate
op <= ip0 when sel = '0' else ip1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grmux2v is generic( tech : integer := inferred;
bits : integer := 2; imp : integer := 0);
port( ip0, ip1 : in std_logic_vector(bits-1 downto 0);
sel : in std_logic;
op : out std_logic_vector(bits-1 downto 0));
end;
architecture rtl of grmux2v is
begin
x0 : for i in bits-1 downto 0 generate
y0 : grmux2 generic map (tech, imp) port map (ip0(i), ip1(i), sel, op(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grdff is generic( tech : integer := inferred; imp : integer := 0);
port( clk, d : in std_ulogic; q : out std_ulogic); end;
architecture rtl of grdff is
component ut130hbd_dff
port(
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic);
end component;
component dff_ut90nhbd
port(
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic);
end component;
constant has_dff : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_dff(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_dff port map (clk => clk, d => d, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : dff_ut90nhbd port map (clk => clk, d => d, q => q);
end generate;
end generate;
y1 : if has_dff(tech) = 0 generate
x0 : process(clk)
begin if rising_edge(clk) then q <= d; end if; end process;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity gror2 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end;
architecture rtl of gror2 is
component ut130hbd_or2
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
q : out std_ulogic);
end component;
component or2_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
o : out std_ulogic);
end component;
constant has_or2 : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_or2(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_or2 port map (i0 => i0, i1 => i1, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : or2_ut90nhbd port map (i0 => i0, i1 => i1, o => q);
end generate;
end generate;
y1 : if has_or2(tech) = 0 generate
q <= i0 or i1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grand12 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end;
architecture rtl of grand12 is
component ut130hbd_and12
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
q : out std_ulogic);
end component;
component and12_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
o : out std_ulogic);
end component;
constant has_and12 : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_and12(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_and12 port map (i0 => i0, i1 => i1, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : and12_ut90nhbd port map (i0 => i0, i1 => i1, o => q);
end generate;
end generate;
y1 : if has_and12(tech) = 0 generate
q <= i0 and not i1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grnand2 is
generic (
tech: integer := 0;
imp: integer := 0
);
port (
i0: in std_ulogic;
i1: in std_ulogic;
q : out std_ulogic
);
end;
architecture rtl of grnand2 is
constant has_nand2: tech_ability_type := (others => 0);
begin
y0: if has_nand2(tech)=1 generate
end generate;
y1: if has_nand2(tech)=0 generate
q <= not (i0 and i1);
end generate;
end;
|
gpl-2.0
|
15edad183a4167b1090f0feb13ea2018
| 0.602227 | 3.101345 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spi.vhd
| 1 | 8,130 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Pacakge: spi
-- File: spi.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SPI interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package spi is
type spi_in_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
astart : std_ulogic;
cstart : std_ulogic;
ignore : std_ulogic;
end record;
type spi_in_vector is array (natural range <>) of spi_in_type;
constant spi_in_none : spi_in_type := ('0', '0', '0', '0', '0', '0', '0');
type spi_out_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
ssn : std_logic_vector(7 downto 0); -- used by GE/OC SPI core
enable : std_ulogic;
astart : std_ulogic;
aready : std_ulogic;
end record;
type spi_out_vector is array (natural range <>) of spi_out_type;
constant spi_out_none : spi_out_type := ('0', '0', '0', '0', '0', '0',
(others => '0'), '0', '0', '0');
-- SPI master/slave controller
component spictrl
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
netlist : integer := 0;
syncram : integer range 0 to 1 := 1;
memtech : integer := 0;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0;
ignore : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end component;
-- SPI to AHB bridge
type spi2ahb_in_type is record
haddr : std_logic_vector(31 downto 0);
hmask : std_logic_vector(31 downto 0);
en : std_ulogic;
end record;
type spi2ahb_out_type is record
dma : std_ulogic;
wr : std_ulogic;
prot : std_ulogic;
end record;
component spi2ahb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end component;
component spi2ahb_apb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end component;
component spi2ahbx
generic (
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end component;
type spimctrl_in_type is record
miso : std_ulogic;
mosi : std_ulogic;
cd : std_ulogic;
end record;
type spimctrl_out_type is record
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
csn : std_ulogic;
cdcsnoen : std_ulogic;
-- errorn : std_ulogic;
ready : std_ulogic;
initialized : std_ulogic;
end record;
constant spimctrl_out_none : spimctrl_out_type :=
('0', '1', '0', '1', '1', '0', '0');
component spimctrl
generic (
hindex : integer := 0;
hirq : integer := 0;
faddr : integer := 16#000#;
fmask : integer := 16#fff#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
spliten : integer := 0;
oepol : integer := 0;
sdcard : integer range 0 to 1 := 0;
readcmd : integer range 0 to 255 := 16#0B#;
dummybyte : integer range 0 to 1 := 1;
dualoutput : integer range 0 to 1 := 0;
scaler : integer range 1 to 512 := 1;
altscaler : integer range 1 to 512 := 1;
pwrupcnt : integer := 0;
maxahbaccsz : integer range 0 to 256 := AHBDW;
offset : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
spii : in spimctrl_in_type;
spio : out spimctrl_out_type
);
end component;
end;
|
gpl-2.0
|
074d2f7bdce44f2cb1bf37784ede8f6d
| 0.508487 | 3.748271 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/allmem.vhd
| 1 | 54,211 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allmem
-- File: allmem.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: All tech specific memories
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package allmem is
-- AX & RTAX family
component axcel_syncram
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component axcel_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer:= 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
-- Proasic + Proasicplus family
component proasic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
-- Proasic3 family
component proasic3_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic3_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component proasic3_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component proasic3e_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic3e_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component proasic3e_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component proasic3l_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic3l_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component saed32_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component rhs65_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic;
scanen : in std_ulogic;
bypass : in std_ulogic;
mbtdi : in std_ulogic;
mbtdo : out std_ulogic;
mbshft : in std_ulogic;
mbcapt : in std_ulogic;
mbupd : in std_ulogic;
mbclk : in std_ulogic;
mbrstn : in std_ulogic;
mbcgate : in std_ulogic;
mbpres : out std_ulogic;
mbmuxo : out std_logic_vector(5 downto 0)
);
end component;
component dare_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component rhumc_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component proasic3l_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component proasic3_from
generic (
TimingChecksOn: boolean := True;
InstancePath: string := "*";
Xon: boolean := False;
MsgOn: boolean := True;
DATA_X: integer := 1;
MEMORYFILE: string := "";
ACT_PROGFILE: string := "");
port(
CLK : in std_logic := 'U';
DO0 : out std_logic;
DO1 : out std_logic;
DO2 : out std_logic;
DO3 : out std_logic;
DO4 : out std_logic;
DO5 : out std_logic;
DO6 : out std_logic;
DO7 : out std_logic;
ADDR0 : in std_logic := 'U';
ADDR1 : in std_logic := 'U';
ADDR2 : in std_logic := 'U';
ADDR3 : in std_logic := 'U';
ADDR4 : in std_logic := 'U';
ADDR5 : in std_logic := 'U';
ADDR6 : in std_logic := 'U');
end component;
component proasic3e_from
generic (
TimingChecksOn: boolean := True;
InstancePath: string := "*";
Xon: boolean := False;
MsgOn: boolean := True;
DATA_X: integer := 1;
MEMORYFILE: string := "";
ACT_PROGFILE: string := "");
port(
CLK : in std_logic := 'U';
DO0 : out std_logic;
DO1 : out std_logic;
DO2 : out std_logic;
DO3 : out std_logic;
DO4 : out std_logic;
DO5 : out std_logic;
DO6 : out std_logic;
DO7 : out std_logic;
ADDR0 : in std_logic := 'U';
ADDR1 : in std_logic := 'U';
ADDR2 : in std_logic := 'U';
ADDR3 : in std_logic := 'U';
ADDR4 : in std_logic := 'U';
ADDR5 : in std_logic := 'U';
ADDR6 : in std_logic := 'U');
end component;
component proasic3l_from
generic (
TimingChecksOn: boolean := True;
InstancePath: string := "*";
Xon: boolean := False;
MsgOn: boolean := True;
DATA_X: integer := 1;
MEMORYFILE: string := "";
ACT_PROGFILE: string := "");
port(
CLK : in std_logic := 'U';
DO0 : out std_logic;
DO1 : out std_logic;
DO2 : out std_logic;
DO3 : out std_logic;
DO4 : out std_logic;
DO5 : out std_logic;
DO6 : out std_logic;
DO7 : out std_logic;
ADDR0 : in std_logic := 'U';
ADDR1 : in std_logic := 'U';
ADDR2 : in std_logic := 'U';
ADDR3 : in std_logic := 'U';
ADDR4 : in std_logic := 'U';
ADDR5 : in std_logic := 'U';
ADDR6 : in std_logic := 'U');
end component;
component from is
generic (
tech: integer := 0;
timingcheckson: boolean := True;
instancepath: string := "*";
xon: boolean := False;
msgon: boolean := True;
data_x: integer := 1;
memoryfile: string := "";
progfile: string := "");
port (
clk: in std_ulogic;
addr: in std_logic_vector(6 downto 0);
data: out std_logic_vector(7 downto 0));
end component;
-- IGLOO2
component igloo2_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component igloo2_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component igloo2_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
write : in std_ulogic);
end component;
-- Fusion family
component fusion_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component fusion_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component fusion_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component fusion_from
generic (
TimingChecksOn: boolean := True;
InstancePath: string := "*";
Xon: boolean := False;
MsgOn: boolean := True;
DATA_X: integer := 1;
MEMORYFILE: string := "";
ACT_PROGFILE: string := "");
port(
CLK : in std_logic := 'U';
DO0 : out std_logic;
DO1 : out std_logic;
DO2 : out std_logic;
DO3 : out std_logic;
DO4 : out std_logic;
DO5 : out std_logic;
DO6 : out std_logic;
DO7 : out std_logic;
ADDR0 : in std_logic := 'U';
ADDR1 : in std_logic := 'U';
ADDR2 : in std_logic := 'U';
ADDR3 : in std_logic := 'U';
ADDR4 : in std_logic := 'U';
ADDR5 : in std_logic := 'U';
ADDR6 : in std_logic := 'U');
end component;
component altera_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component altera_fifo_dp is
generic (tech : integer := 0; abits : integer := 4; dbits : integer := 32);
port (
rdclk : in std_logic;
rdreq : in std_logic;
rdfull : out std_logic;
rdempty : out std_logic;
rdusedw : out std_logic_vector(abits-1 downto 0);
q : out std_logic_vector(dbits-1 downto 0);
wrclk : in std_logic;
wrreq : in std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
wrusedw : out std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
aclr : in std_logic := '0');
end component;
component generic_syncram
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
component generic_syncram_reg
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end component;
component generic_syncram_2p_reg
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component generic_regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40;
delout: integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
pre1 : out std_ulogic;
pre2 : out std_ulogic;
prdata1 : out std_logic_vector((dbits -1) downto 0);
prdata2 : out std_logic_vector((dbits -1) downto 0)
);
end component;
component generic_fifo
generic (tech : integer := 0; abits : integer := 10; dbits : integer := 32;
sepclk : integer := 1; pfull : integer := 100; pempty : integer := 10; fwft : integer := 0);
port (
rclk : in std_logic;
rrstn : in std_logic;
wrstn : in std_logic;
renable : in std_logic;
rfull : out std_logic;
rempty : out std_logic;
aempty : out std_logic;
rusedw : out std_logic_vector(abits-1 downto 0);
dataout : out std_logic_vector(dbits-1 downto 0);
wclk : in std_logic;
write : in std_logic;
wfull : out std_logic;
afull : out std_logic;
wempty : out std_logic;
wusedw : out std_logic_vector(abits-1 downto 0);
datain : in std_logic_vector(dbits-1 downto 0));
end component;
component ihp25_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_logic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end component;
component ec_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component ec_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component rh_lib18t_syncram_2p
generic (abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
diagin : in std_logic_vector(3 downto 0));
end component;
component rh_lib18t_syncram is
generic (abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
diagin : in std_logic_vector(1 downto 0) := "00");
end component;
component umc_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component rhumc_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component saed32_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component saed32_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component rhs65_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic;
scanen : in std_ulogic;
bypass : in std_ulogic;
mbtdi : in std_ulogic;
mbtdo : out std_ulogic;
mbshft : in std_ulogic;
mbcapt : in std_ulogic;
mbupd : in std_ulogic;
mbclk : in std_ulogic;
mbrstn : in std_ulogic;
mbcgate : in std_ulogic;
mbpres : out std_ulogic;
mbmuxo : out std_logic_vector(5 downto 0)
);
end component;
component rhs65_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component dare_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component dare_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component virage_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component virage_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end component;
component virage90_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component virtex_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component virtex_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component unisim_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component unisim_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component virage90_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component ut025crh_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component ut025crh_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component ut130hbd_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component ut130hbd_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32; words : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component peregrine_regfile_3p
generic (abits : integer := 6; dbits : integer := 32);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0));
end component;
component eclipse_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component nextreme_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component custom1_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component artisan_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component smic13_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component ihp25rh_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_logic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic);
end component;
component peregrine_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component artisan_syncram
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component smic13_syncram
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component custom1_syncram
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component nextreme_syncram
generic (abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component virage_syncram_2p
generic (abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component atc18rha_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(3 downto 0));
end component;
component atc18rha_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(3 downto 0));
end component;
component atc18rha_syncram_2p
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0));
end component;
component artisan_syncram_dp
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component smic13_syncram_dp
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component tm65gplus_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component tm65gplus_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component tm65gplus_syncram_2p
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component generic_regfile_4p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; g0addr: integer := 0;
delout: integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
raddr3 : in std_logic_vector((abits -1) downto 0);
re3 : in std_ulogic;
rdata3 : out std_logic_vector((dbits -1) downto 0);
pre1 : out std_ulogic;
pre2 : out std_ulogic;
pre3 : out std_ulogic;
prdata1 : out std_logic_vector((dbits -1) downto 0);
prdata2 : out std_logic_vector((dbits -1) downto 0);
prdata3 : out std_logic_vector((dbits -1) downto 0)
);
end component;
component cmos9sf_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component cmos9sf_syncram_2p
generic ( abits : integer := 6; dbits : integer := 8);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
-- eASIC Nextreme2
component n2x_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component n2x_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8; sepclk : integer := 0 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component n2x_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component n2x_syncram_we -- syncram with 32-bit write strobes
generic (
abits : integer := 6;
dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
enable : in std_logic_vector((dbits/32)-1 downto 0);
write : in std_logic_vector((dbits/32)-1 downto 0));
end component;
component n2x_syncram_be -- syncram with 8-bit write strobes
generic (
abits : integer := 6;
dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
enable : in std_logic_vector((dbits/8)-1 downto 0);
write : in std_logic_vector((dbits/8)-1 downto 0)
);
end component;
component n2x_syncram_dp_be
generic (
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 1
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits-1) downto 0);
datain1 : in std_logic_vector((dbits-1) downto 0);
dataout1 : out std_logic_vector((dbits-1) downto 0);
enable1 : in std_logic_vector((dbits/8-1) downto 0);
write1 : in std_logic_vector((dbits/8-1) downto 0);
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits-1) downto 0);
datain2 : in std_logic_vector((dbits-1) downto 0);
dataout2 : out std_logic_vector((dbits-1) downto 0);
enable2 : in std_logic_vector((dbits/8-1) downto 0);
write2 : in std_logic_vector((dbits/8-1) downto 0));
end component;
component n2x_syncram_2p_be
generic (
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0));
end component;
component ut90nhbd_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
tdbn : in std_ulogic
);
end component;
component ut90nhbd_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
tdbn : in std_ulogic);
end component;
component ut90nhbd_syncram_dp
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
tdbn : in std_ulogic
);
end component;
component rh_lib13t_syncram_2p
generic (abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
diagin : in std_logic_vector(3 downto 0));
end component;
component rh_lib13t_syncram is
generic (abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
diagin : in std_logic_vector(1 downto 0) := "00");
end component;
end;
|
gpl-2.0
|
8798be1c336d4556e395e8e43d24ee1e
| 0.589696 | 3.375109 | false | false | false | false |
joaocarlos/udlx-verilog
|
fpga/syn/clk_40.vhd
| 1 | 16,279 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_40.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY clk_40 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END clk_40;
ARCHITECTURE SYN OF clk_40 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "3000",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=clk_40",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "3.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_40.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "3000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
lgpl-3.0
|
d459e5ac49b0f793891ce8bb32573985
| 0.700166 | 3.328358 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2c2ahb_apb.vhd
| 1 | 7,385 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb
-- File: i2c2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from I2C.
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity i2c2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb_apb;
architecture rtl of i2c2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
constant SLVA_OFF : std_logic_vector(4 downto 2) := "100";
constant SLVC_OFF : std_logic_vector(4 downto 2) := "101";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2C2AHB, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
i2c2ahbi : i2c2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal i2c2ahbo : i2c2ahb_out_type;
begin
bridge : i2c2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
i2ci => i2ci, i2co => i2co, i2c2ahbi => r.i2c2ahbi,
i2c2ahbo => i2c2ahbo);
comb: process (r, rstn, apbi, i2c2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := i2c2ahbo.prot; v.dmax := i2c2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.i2c2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.i2c2ahbi.haddr;
when MASK_OFF => apbout := r.i2c2ahbi.hmask;
when SLVA_OFF => apbout(6 downto 0) := r.i2c2ahbi.slvaddr;
when SLVC_OFF => apbout(6 downto 0) := r.i2c2ahbi.cfgaddr;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.i2c2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.i2c2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.i2c2ahbi.hmask := apbi.pwdata;
when SLVA_OFF => v.i2c2ahbi.slvaddr := apbi.pwdata(6 downto 0);
when SLVC_OFF => v.i2c2ahbi.cfgaddr := apbi.pwdata(6 downto 0);
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((i2c2ahbo.dma and not r.dmax) or
(i2c2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or i2c2ahbo.prot; v.wr := i2c2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.i2c2ahbi.en := conv_std_logic(resen = 1);
v.i2c2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.i2c2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.i2c2ahbi.slvaddr := conv_std_logic_vector(i2cslvaddr, 7);
v.i2c2ahbi.cfgaddr := conv_std_logic_vector(i2ccfgaddr, 7);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in i2c2ahbx...
end architecture rtl;
|
gpl-2.0
|
cfd0b11f1073ffd63ebf9d6700f5af81
| 0.548951 | 3.536877 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/adapters/word_aligner.vhd
| 1 | 5,399 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: word_aligner
-- File: word_aligner.vhd
-- Author: Pascal Trotta
-- Description: generic SGMII comma detector and word aligner for serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity word_aligner is
generic(
comma : std_logic_vector(9 downto 3) := "0011111");
port(
clk : in std_logic; -- rx clock
rstn : in std_logic; -- asynchronous reset
rx_in : in std_logic_vector(9 downto 0); -- Data in
val_in : in std_logic; -- Data in valid
rx_out : out std_logic_vector(9 downto 0); -- Data out
val_out : out std_logic; -- Data out valid
aligned : out std_logic); -- Data aligned
end entity;
architecture word_arch of word_aligner is
type state_type is (idle, fill_second, find_align, fix_align);
type mux_sel is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
type reg is record
val : std_logic;
state : state_type;
alignment_sel : mux_sel;
q0 : std_logic_vector(9 downto 0);
q1 : std_logic_vector(9 downto 0);
end record;
type out_sig is record
rx_out : std_logic_vector(9 downto 0);
val_out : std_logic;
aligned : std_logic;
end record;
signal regs, regin : reg;
begin
combp: process(regs, rx_in, val_in)
variable regv : reg;
variable outv : out_sig;
variable q1q0 : std_logic_vector(19 downto 0);
begin
regv := regs;
outv.aligned := '0';
outv.rx_out := rx_in;--(9 downto 0);
q1q0 := regv.q1 & regv.q0;
case regv.state is
when idle =>
if val_in = '1' then
regv.state := fill_second; --when first data valid wait another clock cycle to fill the second register q1
end if;
when fill_second =>
regv.state := find_align;
when find_align =>
regv.state := fix_align;
if q1q0(18 downto 12) = comma then
regv.alignment_sel:=S0;
elsif q1q0(17 downto 11) = comma then
regv.alignment_sel:=S1;
elsif q1q0(16 downto 10) = comma then
regv.alignment_sel:=S2;
elsif q1q0(15 downto 9) = comma then
regv.alignment_sel:=S3;
elsif q1q0(14 downto 8) = comma then
regv.alignment_sel:=S4;
elsif q1q0(13 downto 7) = comma then
regv.alignment_sel:=S5;
elsif q1q0(12 downto 6) = comma then
regv.alignment_sel:=S6;
elsif q1q0(11 downto 5) = comma then
regv.alignment_sel:=S7;
elsif q1q0(10 downto 4) = comma then
regv.alignment_sel:=S8;
elsif q1q0(9 downto 3) = comma then
regv.alignment_sel:=S9;
else
regv.state := find_align; -- comma not found and still not aligned
end if;
when fix_align => -- fix the alignment until rstn
regv.state := fix_align;
outv.aligned := '1';
case regv.alignment_sel is
when S0 =>
outv.rx_out := q1q0(18 downto 9);
when S1 =>
outv.rx_out := q1q0(17 downto 8);
when S2 =>
outv.rx_out := q1q0(16 downto 7);
when S3 =>
outv.rx_out := q1q0(15 downto 6);
when S4 =>
outv.rx_out := q1q0(14 downto 5);
when S5 =>
outv.rx_out := q1q0(13 downto 4);
when S6 =>
outv.rx_out := q1q0(12 downto 3);
when S7 =>
outv.rx_out := q1q0(11 downto 2);
when S8 =>
outv.rx_out := q1q0(10 downto 1);
when S9 =>
outv.rx_out := q1q0(9 downto 0);
end case;
end case;
outv.val_out := outv.aligned and regv.val;
regv.val := val_in;
regv.q1 := regv.q0;
regv.q0 := rx_in;
-- internal registers and outputs assignments
regin <= regv;
aligned <= outv.aligned;
val_out <= outv.val_out;
rx_out <= outv.rx_out;
end process;
regp: process(clk, rstn)
begin
if rstn = '0' then
regs.val <= '0';
regs.state <= idle;
regs.alignment_sel <= S0;
regs.q0 <= (others =>'0');
regs.q1 <= (others =>'0');
elsif rising_edge(clk) then
regs <= regin;
end if;
end process;
end architecture;
|
gpl-2.0
|
2a69b1658f540a4929e175705811a0d9
| 0.556399 | 3.606546 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/mmu_dcache.vhd
| 1 | 66,950 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_dcache
-- File: mmu_dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libmmu.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 1 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_ulogic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic;
ahbso : in ahb_slv_out_vector
);
end;
architecture rtl of mmu_dcache is
constant M_EN : boolean := (mmuen = 1);
constant DSNOOP2 : integer := dsnoop mod 4;
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant M_TLB_TYPE : integer range 0 to 1 := -- either split or combined
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(1, 2));
constant M_TLB_FASTWRITE : integer range 0 to 3 := -- fast writebuffer
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(2, 2));
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(dlramstart, 8);
constant ILRAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(ilramstart, 8);
constant DIR_BITS : integer := log2x(DSETS);
constant bend : std_logic_vector(4 downto 2) := "101";
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory,
sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_ulogic;
lock : std_ulogic;
lock2 : std_ulogic;
smask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag, dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_ulogic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, rburst, holdn, nomds, stpend : std_ulogic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
efaddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- error flush address
dstate : dstatetype; -- FSM vector
hit, valid : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
mexc : std_ulogic; -- latched mexc
bmexc : std_ulogic; -- latched mexc from burst read
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_ulogic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_ulogic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_ulogic;
lramrd : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
flushl2 : std_ulogic;
tadj, dadj, sadj : std_logic_vector(1 downto 0);
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
dlock : std_logic;
su : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
reqst : std_logic;
set : integer range 0 to DSETS-1;
noflush : std_logic;
cmiss : std_ulogic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_ulogic; -- snoop access to tags
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag address
mask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
snhit : std_logic_vector(0 to MAXSETS-1);
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0);
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else
xset(0) := xlru(0);
end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset: std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
constant write_buffer_none : write_buffer_type := (
addr => (others => '0'),
data1 => (others => '0'),
data2 => (others => '0'),
size => (others => '0'),
asi => (others => '0'),
read => '0',
lock => '0',
lock2 => '0',
smask => (others => '0')
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : dcache_control_type := (
read => '0',
size => (others => '0'),
req => '0',
burst => '0',
rburst => '0',
holdn => '1',
nomds => '0',
stpend => '0',
xaddress => (others => '0'),
paddress => (others => '0'),
faddr => (others => '0'),
efaddr => (others => '0'),
dstate => idle,
hit => '0',
valid => '0',
flush => '0',
flush2 => '1',
mexc => '0',
bmexc => '0',
wb => write_buffer_none,
asi => (others => '0'),
icenable => '0',
rndcnt => (others => '0'),
setrepl => (others => '0'),
lrr => '0',
dsuset => (others => '0'),
lock => '0',
lramrd => '0',
ilramen => '0',
cctrl => cctrl_none,
cctrlwr => '0',
flushl2 => '0',
tadj => (others => '0'),
dadj => (others => '0'),
sadj => (others => '0'),
mmctrl1 => mmctrl_type1_none,
mmctrl1wr => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
vaddr => (others => '0'),
ready => '0',
wbinit => '0',
cache => '0',
dlock => '0',
su => '0',
trans_op => '0',
flush_op => '0',
diag_op => '0',
reqst => '0',
set => 0,
noflush => '0',
cmiss => '0'
);
constant SRES : snoop_reg_type := (
snoop => '0',
addr => (others => '0'),
mask => (others => '0'),
snhit => (others => '0')
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
begin
dctrl : process(rst, r, rs, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco, ahbso)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_ulogic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_ulogic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_ulogic;
variable mexc : std_ulogic;
variable hit, valid, forcemiss : std_ulogic;
variable flush : std_ulogic;
variable iflush : std_ulogic;
variable v : dcache_control_type;
variable eholdn : std_ulogic; -- external hold
variable snoopwe : std_ulogic;
variable hcache : std_ulogic;
variable lramcs, lramen, lramrd, lramwr, ilramen : std_ulogic;
variable snoopaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable flushaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set, eset : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validraw : std_logic_vector(0 to DSETS-1);
variable validv, hitv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe, snhit : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable lrusetval: std_logic_vector(SETBITS-1 downto 0);
variable wlrr : std_logic_vector(0 to 3);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable laddr : std_logic_vector(31 downto 0); -- local ram addr
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable rlramrd : std_ulogic;
variable cache : std_ulogic;
variable ctx : ctxdatatype;
variable flushl : std_ulogic;
variable flushlv : std_logic_vector(0 to MAXSETS-1);
variable miscdata : std_logic_vector(31 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable su : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
variable pagesize : integer range 0 to 3;
variable mhold : std_logic; -- MMU hold
variable wbhold : std_logic; -- write-buffer hold
begin
-- init local variables
v := r; vs := rs; dcramov := dcramo; vl := rl;
vl.write := '0'; lramen := '0'; lramrd := '0'; lramwr := '0';
lramcs := '0'; laddr := (others => '0'); v.cctrlwr := '0';
ilramen := '0'; v.flush2 := r.flush;
snhit := (others => '0'); v.cmiss := '0'; mhold := '0'; wbhold := '0';
pagesize := MMU_getpagesize(mmupgsz,r.mmctrl1);
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
v.mmctrl1wr := '0';
tagclear := '0'; paddress := r.paddress;
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
paddress := r.xaddress;
end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0;
vs.snoop := '0'; snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
flushaddr := r.xaddress(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
validv := (others => '0'); hitv := (others => '0'); cache := '0';
if (dlram = 1) then rlramrd := r.lramrd; else rlramrd := '0'; end if;
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
ctx := (others => (others => '0'));
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
v.flushl2 := dci.flushl and not r.flush;
newptag := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => '0'); -- scanen no longer handled here
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if dsetlock = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if (DSNOOP2 /= 0) then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and (not mcdo.bg or r.mmctrl1.e)) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
if (r.mmctrl1.e = '1') and (mcdo.bg = '1') then vs.mask := r.wb.smask;
else vs.mask := (others => '1'); end if;
end if;
if DSNOOP /= 0 then
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
end if;
for i in DSETS-1 downto 0 loop
if ((rs.snoop and not (r.flush or r.flush2)) = '1') then
if (DSNOOP2 /= 0) and (rs.mask(i) = '1') and
((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW))
)
then
if DSNOOPSEP then flushaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
else snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW); end if;
snoopwe := '1'; snoopset := i; snhit(i) := '1';
end if;
end if;
end loop;
end if;
vs.snhit := snhit; -- not needed, debug only
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0);
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read and not r.dlock;
else
maddress := dci.maddress(31 downto 0);
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read and not dci.lock;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
if (dsnoop = 6) and (r.cctrl.dsnoop = '0') then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
senable := enable;
end if;
lrusetval := lru_set(rl.lru(conv_integer(maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
-- generate cache hit and valid bits
if (r.mmctrl1.e = '0') then hcache := ahb_slv_dec_cache(dci.maddress, ahbso, cached);
else hcache := '1'; end if;
forcemiss := (not dci.asi(3)) or dci.lock;
if (dci.asi(4 downto 0) = ASI_MMU_BP) or (r.cctrl.dcs(0) = '0') or
((r.flush or r.flush2) = '1')
then hcache := '0'; end if;
hit := '0'; set := 0;
for i in DSETS-1 downto 0 loop
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := '1'; end if;
validv(i) := hcache and hitv(i) and (not r.flush) and (not r.flush2) and dcramov.tag(i)(dlinesize-1);
validraw(i) := dcramov.tag(i)(dlinesize-1);
end loop;
if drepl = dir then
hit := hitv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1))) and not r.flush and (not r.flush2);
valid := validv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1)));
else
hit := orv(hitv) and not r.flush and (not r.flush2);
valid := orv(validv);
end if;
-- force cache miss if mmu-enabled but off or BYPASS, or on flush
if (dci.asi(4 downto 0) = ASI_MMU_BP) or (r.cctrl.dcs(0) = '0') or ((r.flush or r.flush2) = '1')
then hit := '0'; end if;
if DSETS > 1 then
if drepl = dir then
set := conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1));
else
for i in DSETS-1 downto 0 loop
if (hitv(i) = '1') then set := i; end if;
end loop;
end if;
if rlramrd = '1' then set := 1; end if;
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
v.su := dci.msu; v.set := set;
v.valid := valid; v.dlock := dci.lock;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(LINE_HIGH downto 2) := r.wb.addr(LINE_HIGH downto 2) + 1;
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
if (mcdo.grant and r.req) = '1' then v.wb.lock2 := r.wb.lock; end if;
if (dlram = 1) then
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
laddr := r.xaddress;
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then
laddr := dci.maddress;
else laddr := dci.eaddress; end if;
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)
then lramen := '1'; end if;
if ((laddr(31 downto 24) = LOCAL_RAM_START)) or ((dci.dsuen = '1') and (dci.asi(4 downto 1) = "0101"))
then lramcs := '1'; end if;
end if;
if (ilram = 1) then
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = ILRAM_START) then ilramen := '1'; end if;
end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if (r.cctrlwr and not dci.nullify) = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.noflush := dci.maddress(30);
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
if (memtech = rhlib18t) and (r.xaddress(7 downto 2) = "000001") and (dci.read = '0') then
v.tadj := dci.maddress(5 downto 4);
v.sadj := dci.maddress(3 downto 2);
v.dadj := dci.maddress(1 downto 0);
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
v.nomds := r.nomds and not eholdn; v.bmexc := '0';
if ((r.reqst = '0') and (r.stpend = '0')) or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock and not dci.nullify and ico.hold;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and
((M_TLB_FASTWRITE /= 0) or ((dci.enaddr and eholdn and dci.lock and not dci.read) = '1')))
then
if (dci.enaddr and eholdn and dci.lock and not dci.read) = '1' then -- skip address translation on store in LDST
v.wb.addr := r.wb.addr(31 downto 8) & dci.maddress(7 downto 0);
newptag := r.wb.addr(TAG_HIGH downto TAG_LOW);
else
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (dci.read and hcache and andv(r.cctrl.dcs)) = '1' then v.wb.addr(LINE_HIGH downto 0) := (others => '0'); end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => if M_EN then rdatasel := dctx; end if;
when ASI_MMUREGS | ASI_MMUREGS_V8 => if M_EN then rdatasel := misc; end if;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
v.cctrlwr := not dci.read and not (dci.dsuen and not dci.eenaddr);
when ASI_MMUREGS | ASI_MMUREGS_V8 =>
if M_EN then
if (dsu = 0) or dci.dsuen = '0' then
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
end if;
end if;
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; end if;
when ASI_UINST | ASI_SINST =>
if (ilram = 1) then v.dstate := asi_idtag; v.ilramen := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') then -- No access on flush
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if DSNOOPSEP then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if dci.read = '0' then iflush := '1'; end if;
if M_EN then
if dci.read = '0' then
flush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE | ASI_MMUFLUSHPROBE_V8 =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
v.rburst := hcache and (andv(r.cctrl.dcs) or andv(dci.size)); -- and not forcemiss;
if (dlram = 1) and (lramen = '1') then
lramrd := '1';
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if not ((hit and valid and not forcemiss) = '1') then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cmiss := hcache;
v.cache := hcache and andv(r.cctrl.dcs);
if (not M_EN) or ((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
-- cache disabled if mmu-enabled but off or BYPASS
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1')) then
v.req := '1'; v.burst := v.rburst;
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.wbinit := '1'; -- wb init in idle
v.burst := v.rburst;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
cache := '1';
end if;
end if;
else -- write access
if (dlram = 1) and (lramen = '1') then
lramwr := '1';
if (dci.size = "11") then -- double store
v.dstate := dblwrite; v.xaddress(2) := '1';
end if;
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1'))
then -- wait for store queue
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0'; v.wb.read := r.wb.read;
end if;
else
-- ## mmu case > false and
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and
(((mmudco.wbtransdata.accexc = '0') and (M_TLB_FASTWRITE /= 0)) or (dci.lock = '1'))
then
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
-- ## < mmu case
end if;
end if;
if (hit and valid) = '1' then -- write hit
dwrite := '1';
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end if;
eset := set;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (andv(validraw) = '0') and (drepl /= dir) and false then
for i in DSETS-1 downto 0 loop
if validraw(i) = '0' then eset := i; end if;
end loop;
v.setrepl := conv_std_logic_vector(eset, SETBITS);
elsif ((not hit) and (not r.flush)) = '1' then
case drepl is
when rnd =>
if dsetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := dci.maddress(OFFSET_HIGH+log2x(DSETS) downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lrusetval;
when lrr =>
v.setrepl := (others => '0');
if dsetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (dsetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
v.rburst := r.rburst and v.cache;
if r.wbinit = '1' then
v.wb.addr := v.paddress; --mmudco.transdata.data;
v.req := '1';
v.burst := v.rburst;
if v.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
end if;
end if;
end if;
mhold := '1';
end if;
when wread => -- read miss, wait for memory data
if drepl=lru and mcdo.ready='0' and r.hit='0' then
v.setrepl := lrusetval;
end if;
taddr := r.wb.addr(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 3 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if (r.rburst) = '1' then
if (mcdo.grant = '1') and ((r.cctrl.dcs = "01") or
((r.wb.addr(LINE_HIGH downto LINE_LOW) >= bend(LINE_HIGH downto LINE_LOW)) and not
((r.wb.addr(LINE_HIGH downto LINE_LOW) = bend(LINE_HIGH downto LINE_LOW)) and (mcdo.ready = '0')))) then
v.burst := '0';
else v.burst := r.burst; end if;
end if;
if mcdo.ready = '1' then
if (r.cache or r.hit) = '0' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
else
if r.wb.addr(LINE_HIGH downto LINE_LOW) = r.xaddress(LINE_HIGH downto LINE_LOW) then
mds := '0';
end if;
end if;
dwrite := r.cache; rdatasel := memory;
mexc := mcdo.mexc;
v.bmexc := r.bmexc or mcdo.mexc or dci.flushl;
if r.req = '0' then
twrite := r.cache; tagclear := v.bmexc;
if (((dci.enaddr and not mds) = '1') or (dci.flushl = '1') or ((dci.enaddr and twrite) = '1'))
and ((r.cctrl.dcs(0) = '1') or (dlram = 1))
then v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; v.holdn := '1'; end if;
else v.nomds := not r.cache; end if;
tpwrite := twrite;
end if;
v.mexc := mcdo.mexc and not r.rburst; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.wb.addr := paddress;
v.wb.size := r.size;
v.burst := r.rburst;
if r.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
wbhold := '1';
end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) then
laddr := dci.maddress;
if laddr(31 downto 24) = LOCAL_RAM_START then lramcs := '1'; end if;
end if;
if (r.flushl2 and dci.enaddr) = '1' then
v.holdn := '0';
else
v.dstate := idle;
end if;
when dblwrite => -- second part of double store cycle
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) and (rlramrd = '1') then
laddr := r.xaddress; lramwr := '1';
else
if r.hit = '1' then dwrite := r.valid; end if;
v.wb.data2 := dci.edata;
end if;
if (dci.flushl and ico.hold) = '1' then
v.dstate := loadpend; v.holdn := '0';
elsif ico.hold = '0' then v.reqst := '0';
else v.dstate := idle; end if;
when asi_idtag => -- icache diag and inst local ram access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; v.ilramen := '0';
if (dsu = 0) or ((dsu = 1) and (dci.dsuen = '0')) then
mds := not r.read;
end if;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
if (dci.nullify = '0')
then
v.req := '1'; v.stpend := '1';
else v.reqst := '1'; end if;
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
if (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := r.valid;
end if;
end if;
end if;
end if;
end if;
mhold := '1';
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (
(dci.lock = '1')) and (dci.nullify = '1') then
v.dstate := idle; v.wb.lock := '0';
elsif ((v.ready or (mcdo.ready and not r.req)) = '1') or (
(dci.lock = '1')) then -- store queue emptied
if (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := r.valid;
end if;
v.dstate := idle;
v.burst := r.size(1) and r.size(0);
if (dci.nullify = '0') then v.reqst := '1'; end if;
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
v.wb.smask := (others => '1');
if r.hit = '1' then v.wb.smask(r.set) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
wbhold := '1';
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
v.req := v.req or v.reqst; v.stpend := v.stpend or v.reqst; v.reqst := '0';
if (dlram = 1) then v.lramrd := lramcs; end if; -- read local ram data
-- select data to return on read access
-- align if byte/half word read from cache or memory.
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if DSNOOPSEP then snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
tdiagwrite := dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag; senable := (others => '1');
when ASI_DDATA =>
if M_EN then
ddiagwrite := dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
end if;
when ASI_UDATA | ASI_SDATA =>
lramwr := not dci.eenaddr and dci.enaddr and dci.write;
when ASI_MMUREGS | ASI_MMUREGS_V8 =>
rdatasel := misc;
when others =>
end case;
end if;
-- read
if M_EN then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0001";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(MMCTRL_TLBSEP) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
miscdata(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D) := conv_std_logic_vector(pagesize,2); -- r.mmctrl1.pagesize;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
end if;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
if M_EN then set := 0; rdatav(0) := miscdata; end if;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0;
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" =>
rdatav(0)(30) := r.noflush;
rdatav(0)(23) := r.cctrl.dsnoop;
if dsnoop > 4 then rdatav(0)(17) := '1'; end if;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "01" =>
rdatav(0)(7 downto 0) := "00" & r.tadj & r.sadj & r.dadj;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, dlram, dlramsize, dlramstart, mmuen);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0;
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
if r.wb.read = '0' then
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
else
v.burst := ((r.rburst) and not andv(r.wb.addr(LINE_HIGH downto LINE_LOW))) or
(not r.rburst and r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2));
end if;
v.wb.lock := r.wb.lock2;
end if;
-- Generate new valid bits
if r.flush = '1' then twrite := '0'; dwrite := '0'; end if;
vmask := (others => (others => '1'));
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
if (DSETS>1) and (drepl = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (drepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if r.mmctrl1wr = '1' then
case r.xaddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
v.mmctrl1.e := dci.maddress(MMCTRL_E);
v.mmctrl1.nf := dci.maddress(MMCTRL_NF);
v.mmctrl1.pso := dci.maddress(MMCTRL_PSO);
v.mmctrl1.tlbdis := dci.maddress(MMCTRL_TLBDIS);
v.mmctrl1.pagesize := dci.maddress(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := dci.maddress(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := dci.maddress(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
if ((dci.flush or dci.flushl or flush) = '1') and (dcen /= 0) then
v.flush := not r.noflush; v.faddr := (others => '0');
if (dci.flushl = '1') then v.flush := '1'; v.faddr := r.efaddr; end if;
end if;
if eholdn = '1' then v.efaddr := v.xaddress(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') and (dcen /= 0) then
twrite := '1'; vmask := (others => (others => '0'));
v.faddr := r.faddr +1; newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag := (others => '0');
if DSNOOPSEP then flushaddr := r.faddr; end if;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0');
if ((r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) or r.flushl2) = '1' then
v.flush := '0';
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop
ddatainv(i) := mcdo.data;
end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if DSNOOPSEP then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if DSNOOPSEP then
ctpwrite := (others => '1');
end if;
end if;
csnoopwe := (others => '0'); flushl := '0';
flushlv := (others => r.flush);
if (snoopwe = '1') then csnoopwe := snhit; end if;
if DSNOOPSEP then
csnoopwe := csnoopwe or ctwrite;
flushlv := flushlv or snhit; -- flush tag on snoop hit
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0'); v.flush2 := '1';
v.lrr := '0'; v.lock := '0'; v.ilramen := '0';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.tadj := (others => '0'); v.dadj := (others => '0');
v.sadj := (others => '0');
--if M_EN then
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.pagesize := (others => '0');
--end if;
v.mmctrl1.bar := (others => '0');
v.faddr := (others => '0');
v.reqst := '0';
v.cache := '0'; v.wb.lock := '0'; v.wb.lock2 := '0';
v.wb.data1 := (others => '0'); v.wb.data2 := (others => '0');
v.noflush := '0'; v.mexc := '0';
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
if not M_EN then v.mmctrl1 := mmctrl_type1_none; end if; -- kill MMU regs if not enabled
-- Drive signals
c <= v; cs <= vs; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag; -- virtual tag
dcrami.ptag <= ptag; -- physical tag
dcrami.ctx <= ctx; -- context
dcrami.tenable <= enable; -- virtual tag ram enable
dcrami.twrite <= ctwrite; -- virtual tag ram write (port 1)
dcrami.tpwrite <= ctpwrite; -- virtual tag ram write (port 2)
dcrami.flush <= flushlv;
dcrami.senable <= senable; -- physical tag ram enable
dcrami.swrite <= csnoopwe; -- physical tag ram write
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.faddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.faddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= flushaddr;
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
dcrami.ldramin.address(23 downto 2) <= laddr(23 downto 2);
dcrami.ldramin.enable <= (lramcs or lramwr);
dcrami.ldramin.read <= rlramrd;
dcrami.ldramin.write <= lramwr;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= r.cache;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.ilramen <= r.ilramen;
dco.icdiag.cctrl <= r.cctrl;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.cache <= cache;
dco.hit <= r.hit;
if r.dstate = idle then dco.idle <= not r.stpend;
else dco.idle <= '0'; end if;
dco.cstat.cmiss <= r.cmiss;
dco.cstat.chold <= not r.holdn;
dco.cstat.tmiss <= mmudco.tlbmiss;
dco.cstat.mhold <= mhold;
dco.wbhold <= wbhold;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
end process;
-- Local registers
reg1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin
if rising_edge(sclk) then
rs <= cs;
if RESET_ALL and (rst = '0') then rs <= SRES; end if;
end if;
end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.addr <= (others => '0');
rs.snhit <= (others => '0'); rs.mask <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (drepl = lru) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then rl <= LRES; end if;
end if;
end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (drepl = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 ways"
severity failure;
assert not ((DSETS = 3) and (drepl = dir)) report
"Wrong data cache configuration detected: Direct replacement requires 2 or 4 ways"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
gpl-2.0
|
78292ae8efdd869460d0dff4ecd0cacc
| 0.5246 | 3.456733 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/ptf/pt_pci_arb.vhd
| 1 | 4,042 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_arb
-- File: pt_pci_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
entity pt_pci_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pt_pci_arb;
architecture tb of pt_pci_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
|
gpl-2.0
|
29fc08fe5ccdc96e556beb28467e36d7
| 0.555171 | 3.49654 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/sim/ddr3ram.vhd
| 1 | 30,855 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr3ram
-- File: ddr3ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR3 SDRAM (JESD79-3)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr3ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
colbits: integer range 9 to 12 := 10;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0-1:800E-D, 2-4:1066G-E 5-8:1333J-F 9-12:1600K-G
speedbin: integer range 0 to 12 := 0;
density: integer range 2 to 6 := 3; -- 2:512M 3:1G 4:2G 5:4G 6:8G bits/chip
pagesize: integer range 1 to 2 := 1; -- 1K/2K page size (controls tRRD)
changeendian: integer range 0 to 32 := 0
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(2 downto 0);
a: in std_logic_vector(abits-1 downto 0);
resetn: in std_ulogic;
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr3ram is
type moderegs is record
-- Mode register (0)
ppd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
rbt: std_ulogic;
caslat: std_logic_vector(3 downto 0);
blen: std_logic_vector(1 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
tdqsen: std_ulogic;
level: std_ulogic;
al: std_logic_vector(1 downto 0);
rtt_nom: std_logic_vector(2 downto 0);
dic: std_logic_vector(1 downto 0);
dlldis: std_ulogic;
-- Extended mode register 2
rtt_wr: std_logic_vector(1 downto 0);
srt: std_ulogic;
asr: std_ulogic;
cwl: std_logic_vector(2 downto 0);
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
mpr: std_ulogic;
mprloc: std_logic_vector(1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en, dqscal_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 4;
constant tRTP_ck: integer := 4;
constant tRTP_t: time := 7.5 ns;
function tRTP(tper: time) return time is
begin
if tRTP_ck*tper > tRTP_t then return tRTP_ck*tper; else return tRTP_t; end if;
end tRTP;
constant tMOD_ck: integer := 12;
constant tMOD_t: time := 15 ns;
type timetab is array (0 to 12) of time;
-- 800E 800D 1066G 1066H 1066E 1333J 1333H 1333G 1333F 1600K 1600J 1600H 1600G
constant tRAS : timetab :=
(37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 36 ns, 36 ns, 36 ns, 36 ns, 35 ns, 35 ns, 35 ns, 35 ns);
constant tRP : timetab :=
(15 ns, 12.5 ns, 15 ns, 13.125 ns, 11.25 ns, 15 ns, 13.5 ns, 12 ns, 10.5 ns, 13.75 ns, 12.5 ns, 11.25 ns, 10 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(2 to 6) of time;
constant tRFC: timetab2 := (90 ns, 110 ns, 160 ns, 300 ns, 350 ns);
function tRRD(tper: time; speedbin: integer range 0 to 12) return time is
variable t: time;
begin
case speedbin is
when 0 to 1 => t:=10 ns;
when 2 to 4 => if pagesize<2 then t:=7.5 ns; else t:=10 ns; end if;
when 5 to 12 => if pagesize<2 then t:=6 ns; else t:=7.5 ns; end if;
end case;
if t < 4*tper then t:=4*tper; end if;
return t;
end tRRD;
function pick(t,f: integer; b: boolean) return integer is
begin
if b then return t; else return f; end if;
end pick;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(2 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="---" or cba=ba) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t,t2: time;
variable i: integer;
begin
initdone <= false;
-- Allow resetn to be X or U for a while during sim start
if resetn /= '0' then
wait until resetn='0' for 1 us;
end if;
assert resetn='0' report "RESETn not asserted on power-up" severity warning;
wait until resetn/='0' for 200 us;
assert resetn='0' report "RESETn raised with less than 200 us init delay" severity warning;
l0: loop
initdone <= false;
wait until resetn/='0';
assert cke='0' report "CKE not low when RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') for 500 us;
if resetn='0' then next; end if;
assert cke='0' report "CKE raised with less than 500 us delay after RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') and rising_edge(ck);
if resetn='0' then next; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
t2 := t+tRFC(density)+(10 ns);
i := 0;
while i<5 and now<t2 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
i := i+1;
end loop;
-- EMRS EMR2
checkcmd('0','0','0',"010","----------------");
if resetn='0' then next; end if;
-- EMRS EMR3
checkcmd('0','0','0',"011","----------------");
if resetn='0' then next; end if;
-- EMRS EMR1 enable DLL
checkcmd('0','0','0',"001","---------------0");
if resetn='0' then next; end if;
-- EMRS EMR0 reset DLL
checkcmd('0','0','0',"000","-------1--------");
if resetn='0' then next; end if;
-- ZQCL
checkcmd('1','1','0',"---","-----1----------");
if resetn='0' then next; end if;
for x in 1 to 512 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
end loop;
initdone <= true;
wait until resetn='0';
end loop;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
-- Data split by bank to avoid exceeding 4G
constant b0size: integer := (2**(colbits+rowbits)) * ((width+15)/16);
constant b1size: integer := pick(b0size, 1, implbanks>1);
constant b2size: integer := pick(b0size, 1, implbanks>2);
constant b3size: integer := pick(b0size, 1, implbanks>3);
constant b4size: integer := pick(b0size, 1, implbanks>4);
constant b5size: integer := pick(b0size, 1, implbanks>5);
constant b6size: integer := pick(b0size, 1, implbanks>6);
constant b7size: integer := pick(b0size, 1, implbanks>7);
subtype coldata is std_logic_vector(width-1 downto 0);
subtype idata is integer range 0 to (2**20)-1; -- 16 data bits + 2x2 X/U state
type idata_arr is array(natural range <>) of idata;
variable memdata0: idata_arr(0 to b0size-1);
variable memdata1: idata_arr(0 to b1size-1);
variable memdata2: idata_arr(0 to b2size-1);
variable memdata3: idata_arr(0 to b3size-1);
variable memdata4: idata_arr(0 to b4size-1);
variable memdata5: idata_arr(0 to b5size-1);
variable memdata6: idata_arr(0 to b6size-1);
variable memdata7: idata_arr(0 to b7size-1);
function reversedata(data : std_logic_vector; step : integer)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/step-1) loop
rdata(i*step+step-1 downto i*step) := data(data'length-i*step-1 downto data'length-i*step-step);
end loop;
return rdata;
end function reversedata;
impure function memdata_get(bank,idx: integer) return coldata is
variable r: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
case bank is
when 0 => x := memdata0(iidx+q);
when 1 => x := memdata1(iidx+q);
when 2 => x := memdata2(iidx+q);
when 3 => x := memdata3(iidx+q);
when 4 => x := memdata4(iidx+q);
when 5 => x := memdata5(iidx+q);
when 6 => x := memdata6(iidx+q);
when others => x := memdata7(iidx+q);
end case;
p := std_logic_vector(to_unsigned(x,20));
if p(18)='0' then p(15 downto 8) := "UUUUUUUU";
elsif p(19)='1' then p(15 downto 8) := "XXXXXXXX"; end if;
if p(16)='0' then p(7 downto 0) := "UUUUUUUU";
elsif p(17)='1' then p(7 downto 0) := "XXXXXXXX"; end if;
if width < 16 then
r := p(7 downto 0);
else
r(width-16*q-1 downto width-16*q-16) := p(15 downto 0);
end if;
end loop;
if changeendian /= 0 then
r := reversedata(r, changeendian);
end if;
return r;
end memdata_get;
procedure memdata_set(bank,idx: integer; v: coldata) is
variable n: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
-- assert false
-- report ("memdata_set: bank " & tost(bank) & " idx " & tost(idx) & " data " & tost(v))
-- severity note;
n := v;
if changeendian /= 0 then
n := reversedata(n, changeendian);
end if;
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
p := "0101" & x"0000";
if width < 16 then
p(7 downto 0) := n;
else
p(15 downto 0) := n(width-16*q-1 downto width-16*q-16);
end if;
if p(15 downto 8)="UUUUUUUU" then p(18):='0'; p(15 downto 8):=x"00";
elsif is_x(p(15 downto 8)) then p(19):='1'; p(15 downto 8):=x"00"; end if;
if p(7 downto 0)="UUUUUUUU" then p(16):='0'; p(7 downto 0):=x"00";
elsif is_x(p(7 downto 0)) then p(17):='1'; p(7 downto 0):=x"00"; end if;
x := to_integer(unsigned(p));
case bank is
when 0 => memdata0(iidx+q) := x;
when 1 => memdata1(iidx+q) := x;
when 2 => memdata2(iidx+q) := x;
when 3 => memdata3(iidx+q) := x;
when 4 => memdata4(iidx+q) := x;
when 5 => memdata5(iidx+q) := x;
when 6 => memdata6(iidx+q) := x;
when others => memdata7(iidx+q) := x;
end case;
end loop;
end memdata_set;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable idx, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if width < 16 then
idx := to_integer(unsigned(recaddr(rowbits+colbits-1 downto 0)));
while len > 1 loop
memdata0(idx) := 16#10000# + to_integer(unsigned(recdata(0 to 7)));
idx := idx+1;
len := len-1;
recdata(0 to recdata'length-8-1) := recdata(8 to recdata'length-1);
end loop;
else
assert recaddr(0)='0'; -- Assume 16-bit alignment on SREC entry
idx := to_integer(unsigned(recaddr(rowbits+colbits+log2(width/16) downto 1)));
while len > 1 loop
memdata0(idx) := 16#50000# + to_integer(unsigned(recdata(0 to 15)));
idx := idx+1;
len := len-2;
recdata(0 to recdata'length-16-1) := recdata(16 to recdata'length-1);
end loop;
if len > 0 then
memdata0(idx) := 16#40000# + to_integer(unsigned(recdata(0 to 15)));
end if;
end if;
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
first,wchop: boolean;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 25);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-2 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen, wblen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, cwl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 100;
variable mrstime: time;
variable loaded: boolean := false;
variable cold: coldata;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) and resetn='1' then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false; accpipe(0).first:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat(3 downto 1)))+4; end if;
if cl<5 or cl>11 then cl:=0; end if;
case vmr.al is
when "00" => al:=0;
when "01" => al:=cl-1;
when "10" => al:=cl-2;
when others => al:=-1;
end case;
if is_x(vmr.cwl) then cwl:=0; else cwl:=to_integer(unsigned(vmr.cwl))+5; end if;
if cwl>8 then cwl:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=to_integer(unsigned(vmr.wr))+4; end if;
if wrap<5 or wrap>12 then wrap:=0; end if;
-- Checks for all-bank commands
mrscount := mrscount+1;
assert (mrscount >= tMRD_ck) or (cke='1' and (csn='1' or cmd="111"))
report "tMRD violation!" severity warning;
assert (mrscount > tMOD_ck and now > mrstime+tMOD_t-deltat) or
(cke='1' and (csn='1' or cmd="111" or cmd="000"))
report "tMOD violation!" severity warning;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
if vmr.mpr='1' then
assert cke='0' or csn='1' or cmd="111" or cmd="101"
report "Command other than read in MPR mode!" severity warning;
for x in 7 downto 0 loop
assert banks(x).openrow<0
report "Row opened in MPR mode!" severity warning;
end loop;
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(re-prev_re, speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0 or vmr.mpr='1'
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 13) & a(11) & a(9 downto 0)));
wblen := 8;
case vmr.blen is
when "00" => blen := 8;
when "01" => if a(12)='1' then blen:=8; else blen:=4; end if;
when "11" => blen := 4; wblen:=4;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
if cmd(0)='0' then
alow(1 downto 0) := "00";
if blen=8 then alow(2):='0'; end if;
end if;
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.rbt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
accpipe(3-x/2).wchop := (blen<wblen);
end loop;
accpipe(3).first := true;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+tRTP_ck;
else
banks(bank).autopch := al+cwl+wblen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- ZQInit
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
for x in 3+cl+al downto 0 loop
assert not accpipe(x).r severity warning;
end loop;
for x in 4+cwl+al downto 0 loop
assert not accpipe(x).w severity warning;
end loop;
-- Currently does not check TZQCoper/TZQCs
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 6+cwl+al downto 0 loop
assert ( (not ((accpipe(x).r and x<=3+al) or accpipe(x).w)) or
(a(10)='0' and accpipe(x).bank/=bank) )
report "Precharging bank with access in progress" severity warning;
end loop;
for x in 0 to 7 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,3)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.ppd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4) & a(2);
vmr.rbt := a(3);
vmr.blen := a(1 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.tdqsen := a(11);
vmr.level := a(7);
vmr.al := a(4 downto 3);
vmr.rtt_nom := a(9) & a(6) & a(2);
vmr.dic := a(5) & a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.rtt_wr := a(10 downto 9);
vmr.srt := a(7);
vmr.asr := a(6);
vmr.cwl := a(5 downto 3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.mpr := a(2);
vmr.mprloc := a(1 downto 0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := 0;
mrstime := now;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and
((now-banks(x).readtime-deltat) < tRTP_t or
(now-banks(x).opentime-deltat) < tRAS(speedbin)) then
-- Auto delay auto-precharge to satisfy tRTP_t
-- NOTE: According to Micron's datasheets, their DDR3 memories
-- automatically hold off the auto precharge so that also tRAS is satisfied,
-- and the MIG controller seems to depend on this. It is not clear in the
-- JEDEC standard (rev F) whether this is guaranteed behavior for all DDR3
-- RAMs, but we emulate that behavior here.
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP(re-prev_re), true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
if vmr.mpr='1' then
assert vmr.mprloc="00" report "Read from undefined MPR!" severity warning;
read_data <= (others => '0');
for x in width/8-1 downto 0 loop
read_data(x*8) <= '1';
end loop;
else
read_data <= memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(0)) &
memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(1));
end if;
else
read_en <= false;
end if;
if accpipe(3+al).r and accpipe(3+al).first then
banks(accpipe(3+al).bank).readtime := now;
end if;
write_en <= accpipe(2+cwl+al).w or accpipe(3+cwl+al).w;
if accpipe(4+cwl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
cold := memdata_get(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x));
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
cold(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
memdata_set(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x), cold);
end loop;
banks(accpipe(4+cwl+al).bank).writetime := now;
end if;
if accpipe(6+cwl+al).w and accpipe(6+cwl+al).wchop then
banks(accpipe(6+cwl+al).bank).writetime := now;
end if;
dqscal_en <= (vmr.level='1');
elsif resetn='0' then
for x in banks'range loop
banks(x).openrow := -1;
end loop;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en or dqscal_en;
assert not (read_en and write_en);
if dqscal_en then
while dqscal_en loop
prevdqs := dqs;
wait on dqs,dqscal_en;
for x in dqs'range loop
if dqs(x)='1' and prevdqs(x)='0' then
dq(8*x+7 downto 8*x) <= "0000000" & ck;
end if;
end loop;
end loop;
elsif read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
gpl-2.0
|
642ce52f2a1697c5cf681ddb205ad46e
| 0.533917 | 3.594478 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml605/config.vhd
| 1 | 6,141 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex6;
constant CFG_MEMTECH : integer := virtex6;
constant CFG_PADTECH : integer := virtex6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020789#;
constant CFG_ETH_ENL : integer := 16#000123#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
-- Xilinx MIG DDR2 controller
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_CLK4 : integer := 16;
end;
|
gpl-2.0
|
7b54a65f82ea31ba32125566f5966e5a
| 0.646149 | 3.587033 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/saed32/pads_saed32.vhd
| 1 | 12,073 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: saed32pads
-- File: pads_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: SAED32 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package saed32pads is
-- input pad
component I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic;DOUT : out std_logic); end component;
-- input pad with pull-up and pull-down
component B4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT: out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
-- schmitt input pad
component ISH1025_EW port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
-- output pads
component D4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D12I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D16I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
-- bidirectional pads (and tri-state output pads)
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.I1025_NS;
use saed32.B4I1025_NS;
use saed32.ISH1025_EW;
-- pragma translate_on
entity saed32_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of saed32_inpad is
component I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
component B4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT: out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component ISH1025_EW port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
signal localout,localpad : std_logic;
begin
norm : if filter = 0 generate
ip : I1025_NS port map (PADIO => localpad, DOUT => localout, VSS => OPEN, R_EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pu : if filter = pullup generate
ip : B4I1025_NS port map (PADIO => localpad, PULL_UP => '1', PULL_DOWN => '0', DOUT => localout, DIN => '0', VSS => OPEN, R_EN => '1', EN => '0', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pd : if filter = pulldown generate
ip : B4I1025_NS port map (PADIO => localpad, PULL_UP => '0', PULL_DOWN => '1', DOUT => localout, DIN => '0', VSS => OPEN, R_EN => '1', EN => '0', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
sch : if filter = schmitt generate
ip : ISH1025_EW port map (PADIO => localpad, DOUT => localout, VSS => OPEN, R_EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
o <= localout;
localpad <= pad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.B4ISH1025_NS;
use saed32.B12ISH1025_NS;
use saed32.B16ISH1025_NS;
-- pragma translate_on
entity saed32_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of saed32_iopad is
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
signal localen : std_logic;
signal localout,localpad : std_logic;
begin
localen <= not en;
f4 : if (strength <= 4) generate
op : B4ISH1025_NS port map (DIN => i,PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : B12ISH1025_NS port map (DIN => i, PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f16 : if (strength > 12) generate
op : B16ISH1025_NS port map (DIN => i, PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.D4I1025_NS;
use saed32.D12I1025_NS;
use saed32.D16I1025_NS;
-- pragma translate_on
entity saed32_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of saed32_outpad is
component D4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D12I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D16I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
signal localout,localpad : std_logic;
begin
f4 : if (strength <= 4) generate
op : D4I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : D12I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
f16 : if (strength > 12) generate
op : D16I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pad <= localpad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.B4ISH1025_NS;
use saed32.B12ISH1025_NS;
use saed32.B16ISH1025_NS;
-- pragma translate_on
entity saed32_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of saed32_toutpad is
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
signal localpad : std_logic;
begin
f4 : if (strength <= 4) generate
op : B4ISH1025_NS port map (DIN => i,PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : B12ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f16 : if (strength > 12) generate
op : B16ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
pad <= localpad;
end;
|
gpl-2.0
|
105e9a9494f943574309e8773aa19af7
| 0.656092 | 3.236729 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/virage/simprims/virage_simprims.vhd
| 1 | 18,571 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
|
gpl-2.0
|
79ae2a8e043c562dede2897ed9f2ff4e
| 0.634215 | 3.168031 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/core/eth_edcl_ahb_mst.vhd
| 1 | 4,706 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_edcl_ahb_mst
-- File: eth_edcl_ahb_mst.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Ethernet EDCL MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of eth_edcl_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable tretry : std_ulogic;
variable tready : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable hsize : std_logic_vector(2 downto 0);
begin
v := r; htrans := HTRANS_IDLE; tready := '0'; tretry := '0';
terror := '0'; tgrant := '0';
hsize := HSIZE_WORD;
hwdata := tmsti.data;
hbusreq := tmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1' then
tgrant := '1';
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
tmsto.grant <= tgrant;
ahbmo.htrans <= htrans;
ahbmo.hsize <= hsize;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
|
gpl-2.0
|
94986f23f2ff9f304b7304adbbd19c13
| 0.569273 | 3.628373 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica00_EncendidoLEDsCPLD/p1.vhd
| 1 | 886 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Demo0 is
port(
LED0: out std_logic ;
LED1: out std_logic ;
LED2: out std_logic ;
LED3: out std_logic ;
LED4: out std_logic ;
LED5: out std_logic ;
LED6: out std_logic ;
LED7: out std_logic );
-- LOC: LOCATION
attribute loc:string;
attribute loc of LED0: signal is "p58";
attribute loc of LED1: signal is "p59";
attribute loc of LED2: signal is "p60";
attribute loc of LED3: signal is "p61";
attribute loc of LED4: signal is "p62";
attribute loc of LED5: signal is "p63";
attribute loc of LED6: signal is "p70";
attribute loc of LED7: signal is "p71";
end;
architecture ADemo0 of Demo0 is
begin
LED0 <= '0';
LED1 <= '0';
LED2 <= '0';
LED3 <= '0';
LED4 <= '0';
LED5 <= '0';
LED6 <= '0';
LED7 <= '0';
end ADemo0;
|
apache-2.0
|
fb600697e1f4930dd84e30bc23b0e215
| 0.636569 | 2.553314 | false | false | false | false |
aortiz49/MIPS-Processor
|
Hardware/alu_control.vhd
| 1 | 2,130 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.MIPS_lib.all;
entity alu_control is
port(
ALUop : in std_logic_vector(2 downto 0);
funct : in std_logic_vector(5 downto 0);
shamt_in : in std_logic_vector(4 downto 0);
shamt_out : out std_logic_vector(4 downto 0);
control : out std_logic_vector(3 downto 0);
shdir : out std_logic
);
end alu_control ;
architecture bhv of alu_control is
begin
process(shamt_in,ALUop, funct)
begin
shdir <= '0'; -- shift left for lui (default))
shamt_out <= shamt_in;
case ALUop is
when ADD => -- Add for load/store/addi/addiu
control <= F_SUM;
when BEQ => -- sub for branching
control <= F_SUB;
when ANDI => -- and imm
control <= F_AND;
when ORI => -- or immediate
control <= F_OR;
when LUI => -- lui
shamt_out <= "10000";
control <= F_SHFT;
when SLTI => -- set if less than imm
control <= F_SLT;
when SLTIU => -- set if less than imm unsigned
control <= F_SLTU;
when R_TYPE => -- R-type instructions
shdir <= funct(1); -- for sll this bit is '0', for slr it's '1'
case funct IS
when CTRL_ADD =>
control <= F_SUM;
when CTRL_ADDU =>
control <= F_SUM;
when CTRL_SUB =>
control <= F_SUB;
when CTRL_SUBU =>
control <= F_SUB;
when CTRL_AND =>
control <= F_AND;
when CTRL_OR =>
control <= F_OR;
when CTRL_NOR =>
control <= F_NOR;
when CTRL_SLT =>
control <= F_SLT;
when CTRL_SLTU =>
control <= F_SLTU;
when CTRL_SLL =>
control <= F_SHFT;
when CTRL_SRL =>
control <= F_SHFT;
when others =>
control <= (others => '0');
end case;
when others =>
control <= (others => '0');
end case;
end process;
end bhv;
|
mit
|
8d17bba34642d43b4ff97caf5c1ba20a
| 0.486385 | 3.021277 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/topgeneric00.vhd
| 1 | 8,580 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packagegeneric00.all;
entity topgeneric00 is
port(
clk0: in std_logic ;
--SL0: in std_logic;
enable0: in std_logic;
oscdis0: in std_logic;
tmrrst0: in std_logic;
oscout0: out std_logic;
outdiv0: inout std_logic;
--LED0: out std_logic;
cdiv0: in std_logic_vector ( 3 downto 0 );
codop0: in std_logic_vector ( 3 downto 0 );
portA0: in std_logic_vector ( 7 downto 0 );
portB0: in std_logic_vector ( 7 downto 0 );
AC0: inout std_logic_vector ( 7 downto 0 );
outFlag0: inout std_logic);
attribute loc: string;
-- Entradas
attribute loc of portA0: signal is "p125, p124, p123, p122, p121, p120, p117, p110";
attribute loc of portB0: signal is "p116, p115, p114, p113, p112, p111, p105, p104";
attribute loc of codop0: signal is "p103, p102, p101, p100";
attribute loc of cdiv0: signal is "p84, p83, p81, p80";
attribute loc of enable0: signal is "p79";
attribute loc of tmrrst0: signal is "p78";
attribute loc of oscdis0: signal is "p77";
attribute loc of clk0: signal is "p76";
--attribute loc of SL0: signal is "";
-- Salidas
attribute loc of AC0: signal is "p4, p5, p6, p7, p8, p9, p11, p12"; --Acumulador
attribute loc of outFlag0: signal is "p22";
attribute loc of outdiv0: signal is "p23";
attribute loc of oscout0: signal is "p24";
--attribute loc of LED0: signal is "";
end;
architecture topgeneric0 of topgeneric00 is
signal sinuc0: std_logic_vector(7 downto 0);
signal senable0: std_logic;
signal sclk0: std_logic; -- Variable comentada por defecto
signal S1intFlag0, sFlagucBuf, S2intFlag0: std_logic;
signal soutFlag0: std_logic; --, sinucFlag0
--signal soutdiv0, sSL, sLED: std_logic;
signal sAC0, sucBuff, S2inuc0: std_logic_vector(7 downto 0); --sAi, sBi, sSo,
signal S1portA0, S1portB0, S2portA0, S2portB0: std_logic_vector(7 downto 0);
signal scdiv0, S1codop0, S2codop0: std_logic_vector(3 downto 0);
begin
sclk0 <= clk0;
S1portA0 <= portA0;
S1portB0 <= portB0;
S2portA0 <= portA0;
S2portB0 <= portB0;
--inuc0 <= sinuc0;
S1codop0 <= codop0;
S2codop0 <= codop0;
--outdiv0 <= soutdiv0;
scdiv0 <= cdiv0;
AC0 <= sAC0;
outFlag0 <= soutFlag0;
senable0 <= enable0;
G00: toposc00 port map(indivosc => scdiv0, -- Opcode para el divisor implementado en clase
soscdis => oscdis0, -- Enable/Disable oscilador interno
stmrrst => tmrrst0, -- Timer reset
oscout => oscout0, -- Salida del oscilador interno (su frecuencia no cambia)
outdivosc => outdiv0); -- Salida del timer (oscilador con divisor de frecuencia interno) + divisor implementado en clase
-- Checar si es válido reemplazar sclk0 por outdiv0 para que todo se realice en función de la frecuencia de salida con el timer implementado en clase,
-- de lo contrario todo parecerá estático ya que sclk solo cambia de valor mediante una entrada externa
G01: and00 port map(clka => sclk0, --sclk0
codopa => S1codop0,
portAa => S1portA0,
portBa => S1portB0,
inFlaga => soutFlag0,
outa => sinuc0,
outFlaga => S1intFlag0);
G02: xor00 port map(clkx => sclk0,
codopx => S2codop0,
portAx => S2portA0,
portBx => S2portB0,
inFlagx => soutFlag0,
outx => S2inuc0,
outFlagx => S2intFlag0);
G03: uc00 port map(clkuc => sclk0,
inFlaguc => S1intFlag0,
inFlaguc2 => S2intFlag0,
enable => senable0,
inuc => sinuc0,
outuc => sucBuff,
outFlaguc => sFlagucBuf);
G04: or00 port map(clko => sclk0,
codopo => S1codop0,
portAo => S1portA0,
portBo => S1portB0,
inFlago => soutFlag0,
outo => sinuc0,
outFlago => S1intFlag0);
G05: not00 port map(clkn => sclk0,
codopn => S1codop0,
portAn => S1portA0,
inFlagn => soutFlag0,
outn => sinuc0,
outFlagn => S1intFlag0);
G06: nand00 port map(clknd => sclk0,
codopnd => S1codop0,
portAnd => S1portA0,
portBnd => S1portB0,
inFlagnd => soutFlag0,
outnd => sinuc0,
outFlagnd => S1intFlag0);
--G07: topadder00 port map(clkadd => sclk0,
-- codopadd => S2codop0,
-- inFlagadd => soutFlag0,
-- portAaddin => S2portA0,
-- portBaddin => S2portB0,
-- SLaddin => SL0,
-- LEDaddin => sLED,
-- portAaddout => sAi,
-- portBaddout => sBi,
-- SLaddout => sSL,
-- LEDaddout => LED0,
-- outFlagadd => S2intFlag0,
-- Soaddin => sSo,
-- Soaddout => S2inuc0);
--G08: adder8bita00 port map(Ai => sAi,
-- Bi => sBi,
-- SL => sSL,
-- LED => sLED,
-- So => sSo);
G09: buffer00 port map(clkb => sclk0,
enableb => senable0,
inFlagb => sFlagucBuf,
inFlagb2 => S2intFlag0,
inucb => sucBuff,
inucb2 => S2inuc0,
outucb =>sAC0,
outFlagb => soutFlag0);
G10: nor00 port map(clknr => sclk0,
codopnr => S1codop0,
portAnr => S1portA0,
portBnr => S1portB0,
inFlagnr => soutFlag0,
outnr => sinuc0,
outFlagnr => S1intFlag0);
G11: xnor00 port map(clkxnr => sclk0,
codopxnr => S1codop0,
portAxnr => S1portA0,
portBxnr => S1portB0,
inFlagxnr => soutFlag0,
outxnr => sinuc0,
outFlagxnr => S1intFlag0);
G12: comp200 port map(clkcmp2 => sclk0,
codopcmp2 => S1codop0,
portAcmp2 => S1portA0,
inFlagcmp2 => soutFlag0,
outcmp2 => sinuc0,
outFlagcmp2 => S1intFlag0);
G13: shiftl00 port map(clkcshl => sclk0,
codopcshl => S1codop0,
portAcshl => S1portA0,
inFlagcshl => soutFlag0,
outcshl => sinuc0,
outFlagcshl => S1intFlag0);
G14: shiftr00 port map(clkcshr => sclk0,
codopcshr => S1codop0,
portAcshr => S1portA0,
inFlagcshr => soutFlag0,
outcshr => sinuc0,
outFlagcshr => S1intFlag0);
G15: rotl00 port map(clkrotl => sclk0,
codoprotl => S1codop0,
portArotl => S1portA0,
inFlagrotl => soutFlag0,
outrotl => sinuc0,
outFlagrotl => S1intFlag0);
G16: rotr00 port map(clkrotr => sclk0,
codoprotr => S1codop0,
portArotr => S1portA0,
inFlagrotr => soutFlag0,
outrotr => sinuc0,
outFlagrotr => S1intFlag0);
G17: comp00 port map(clkcmp => sclk0,
codopcmp => S1codop0,
portAcmp => S1portA0,
portBcmp => S2portB0,
inFlagcmp => soutFlag0,
outcmp => sinuc0,
outFlagcmp => S1intFlag0);
end topgeneric0;
|
apache-2.0
|
d1d9aea9975696d7a614673f96982c58
| 0.477845 | 4.077984 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/fmf/fifo/idt7202.vhd
| 3 | 31,912 |
--pragma translate_off
--------------------------------------------------------------------------------
-- File Name: idt7202.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Munden 01 Feb 10 Initial release
-- V1.1 D. Rambaud 01 OCT 24 fixed problem with RDPoint
-- V1.2 S. Habinc 06 Apr 18 fixed problem with RDPoint
--
--------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library: FIFO
-- Technology: CMOS
-- Part: IDT7202
--
-- Description: Async FIFO 1,024 x 9
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF; USE FMF.gen_utils.ALL;
USE FMF.conversions.ALL;
--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt7202 IS
GENERIC (
-- tipd delays: interconnect path delays
tipd_D0 : VitalDelayType01 := VitalZeroDelay01;
tipd_D1 : VitalDelayType01 := VitalZeroDelay01;
tipd_D2 : VitalDelayType01 := VitalZeroDelay01;
tipd_D3 : VitalDelayType01 := VitalZeroDelay01;
tipd_D4 : VitalDelayType01 := VitalZeroDelay01;
tipd_D5 : VitalDelayType01 := VitalZeroDelay01;
tipd_D6 : VitalDelayType01 := VitalZeroDelay01;
tipd_D7 : VitalDelayType01 := VitalZeroDelay01;
tipd_D8 : VitalDelayType01 := VitalZeroDelay01;
tipd_FLNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_RNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_RSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_XINeg : VitalDelayType01 := VitalZeroDelay01;
-- tpd delays
tpd_FLNeg_EFNeg : VitalDelayType01 := UnitDelay01;
tpd_RNeg_Q0 : VitalDelayType01Z := UnitDelay01Z;
tpd_RNeg_EFNeg : VitalDelayType01 := UnitDelay01;
tpd_RNeg_FFNeg : VitalDelayType01 := UnitDelay01;
tpd_RNeg_XONeg : VitalDelayType01 := UnitDelay01;
tpd_RSNeg_EFNeg : VitalDelayType01 := UnitDelay01;
tpd_RSNeg_FFNeg : VitalDelayType01 := UnitDelay01;
tpd_RSNeg_XONeg : VitalDelayType01 := UnitDelay01;
tpd_WNeg_Q0 : VitalDelayType01Z := UnitDelay01Z;
tpd_WNeg_EFNeg : VitalDelayType01 := UnitDelay01;
tpd_WNeg_FFNeg : VitalDelayType01 := UnitDelay01;
tpd_WNeg_XONeg : VitalDelayType01 := UnitDelay01;
-- tpw values: pulse widths
tpw_RNeg_negedge : VitalDelayType := UnitDelay;
tpw_RNeg_posedge : VitalDelayType := UnitDelay;
tpw_WNeg_negedge : VitalDelayType := UnitDelay;
tpw_WNeg_posedge : VitalDelayType := UnitDelay;
tpw_RSNeg_negedge : VitalDelayType := UnitDelay;
tpw_FLNeg_negedge : VitalDelayType := UnitDelay;
tpw_FLNeg_posedge : VitalDelayType := UnitDelay;
tpw_XINeg_negedge : VitalDelayType := UnitDelay;
tpw_XINeg_posedge : VitalDelayType := UnitDelay;
-- tperiod_min: minimum clock period = 1/max freq
tperiod_RNeg : VitalDelayType := UnitDelay;
tperiod_WNeg : VitalDelayType := UnitDelay;
-- tsetup values: setup times
tsetup_D0_WNeg : VitalDelayType := UnitDelay;
tsetup_RNeg_RSNeg : VitalDelayType := UnitDelay;
tsetup_RNeg_FLNeg : VitalDelayType := UnitDelay;
tsetup_XINeg_RNeg : VitalDelayType := UnitDelay;
-- thold values: hold times
thold_D0_WNeg : VitalDelayType := UnitDelay;
thold_RNeg_RSNeg : VitalDelayType := UnitDelay;
thold_RNeg_FLNeg : VitalDelayType := UnitDelay;
-- generic control parameters
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
-- For FMF SDF technology file usage
TimingModel : STRING := DefaultTimingModel
);
PORT (
D0 : IN std_ulogic := 'U';
D1 : IN std_ulogic := 'U';
D2 : IN std_ulogic := 'U';
D3 : IN std_ulogic := 'U';
D4 : IN std_ulogic := 'U';
D5 : IN std_ulogic := 'U';
D6 : IN std_ulogic := 'U';
D7 : IN std_ulogic := 'U';
D8 : IN std_ulogic := 'U';
Q0 : OUT std_ulogic := 'U';
Q1 : OUT std_ulogic := 'U';
Q2 : OUT std_ulogic := 'U';
Q3 : OUT std_ulogic := 'U';
Q4 : OUT std_ulogic := 'U';
Q5 : OUT std_ulogic := 'U';
Q6 : OUT std_ulogic := 'U';
Q7 : OUT std_ulogic := 'U';
Q8 : OUT std_ulogic := 'U';
EFNeg : OUT std_ulogic := 'U';
FFNeg : OUT std_ulogic := 'U';
FLNeg : IN std_ulogic := 'U';
RNeg : IN std_ulogic := 'U';
RSNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
XINeg : IN std_ulogic := 'U';
XONeg : OUT std_ulogic := 'U'
);
ATTRIBUTE VITAL_LEVEL0 of idt7202 : ENTITY IS TRUE;
END idt7202;
--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt7202 IS
ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;
CONSTANT partID : STRING := "IDT7202";
CONSTANT MaxData : NATURAL := 511;
CONSTANT TotalLOC : NATURAL := 1023;
CONSTANT Half : NATURAL := TotalLOC/2;
CONSTANT DataWidth : NATURAL := 9;
CONSTANT HiDbit : NATURAL := 8;
SIGNAL D0_ipd : std_ulogic := 'U';
SIGNAL D1_ipd : std_ulogic := 'U';
SIGNAL D2_ipd : std_ulogic := 'U';
SIGNAL D3_ipd : std_ulogic := 'U';
SIGNAL D4_ipd : std_ulogic := 'U';
SIGNAL D5_ipd : std_ulogic := 'U';
SIGNAL D6_ipd : std_ulogic := 'U';
SIGNAL D7_ipd : std_ulogic := 'U';
SIGNAL D8_ipd : std_ulogic := 'U';
SIGNAL FLNeg_ipd : std_ulogic := 'U';
SIGNAL RNeg_ipd : std_ulogic := 'U';
SIGNAL RSNeg_ipd : std_ulogic := 'U';
SIGNAL WNeg_ipd : std_ulogic := 'U';
SIGNAL XINeg_ipd : std_ulogic := 'U';
BEGIN
----------------------------------------------------------------------------
-- Wire Delays
----------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN
w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0);
w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1);
w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2);
w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3);
w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4);
w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5);
w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6);
w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7);
w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8);
w_21 : VitalWireDelay (FLNeg_ipd, FLNeg, tipd_FLNeg);
w_22 : VitalWireDelay (RNeg_ipd, RNeg, tipd_RNeg);
w_23 : VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg);
w_24 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
w_25 : VitalWireDelay (XINeg_ipd, XINeg, tipd_XINeg);
END BLOCK;
----------------------------------------------------------------------------
-- Main Behavior Block
----------------------------------------------------------------------------
Behavior: BLOCK
PORT (
DIn : IN std_logic_vector(HiDbit downto 0);
QOut : OUT std_logic_vector(HiDbit downto 0);
FLNegIn : IN std_Ulogic := 'U';
RNegIn : IN std_Ulogic := 'U';
RSNegIn : IN std_Ulogic := 'U';
WNegIn : IN std_Ulogic := 'U';
XINegIn : IN std_Ulogic := 'U';
EFNegOut : OUT std_Ulogic := 'U';
FFNegOut : OUT std_Ulogic := 'U';
XONegOut : OUT std_Ulogic := 'U'
);
PORT MAP (
DIn(0) => D0_ipd,
DIn(1) => D1_ipd,
DIn(2) => D2_ipd,
DIn(3) => D3_ipd,
DIn(4) => D4_ipd,
DIn(5) => D5_ipd,
DIn(6) => D6_ipd,
DIn(7) => D7_ipd,
DIn(8) => D8_ipd,
QOut(0) => Q0,
QOut(1) => Q1,
QOut(2) => Q2,
QOut(3) => Q3,
QOut(4) => Q4,
QOut(5) => Q5,
QOut(6) => Q6,
QOut(7) => Q7,
QOut(8) => Q8,
FLNegIn => FLNeg_ipd,
RSNegIn => RSNeg_ipd,
XINegIn => XINeg_ipd,
RNegIn => RNeg_ipd,
WNegIn => WNeg_ipd,
EFNegOut => EFNeg,
FFNegOut => FFNeg,
XONegOut => XONeg
);
SIGNAL Q_zd : std_logic_vector(HiDbit downto 0) := (others => 'Z');
SIGNAL EF_pulse : std_ulogic := '0';
SIGNAL FF_pulse : std_ulogic := '0';
BEGIN
------------------------------------------------------------------------
-- Behavior Process
------------------------------------------------------------------------
Fifo : PROCESS (DIn, FLNegIn, RSNegIn, XINegIn, RNegIn, WNegIn,
EF_pulse, FF_pulse)
-- Timing Check Variables
VARIABLE Tviol_D0_WNeg : X01 := '0';
VARIABLE TD_D0_WNeg : VitalTimingDataType;
VARIABLE Tviol_RNeg_RSNeg : X01 := '0';
VARIABLE TD_RNeg_RSNeg : VitalTimingDataType;
VARIABLE Tviol_RNeg_FLNeg : X01 := '0';
VARIABLE TD_RNeg_FLNeg : VitalTimingDataType;
VARIABLE Tviol_XINeg_RNeg : X01 := '0';
VARIABLE TD_XINeg_RNeg : VitalTimingDataType;
VARIABLE Tviol_XINeg_WNeg : X01 := '0';
VARIABLE TD_XINeg_WNeg : VitalTimingDataType;
VARIABLE Pviol_RNeg : X01 := '0';
VARIABLE TD_RNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_WNeg : X01 := '0';
VARIABLE TD_WNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_RSNeg : X01 := '0';
VARIABLE TD_RSNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_FLNeg : X01 := '0';
VARIABLE TD_FLNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_XINeg : X01 := '0';
VARIABLE TD_XINeg : VitalPeriodDataType := VitalPeriodDataInit;
-- Memory array declaration
TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
RANGE -2 TO MaxData;
-- Functionality Results Variables
VARIABLE Violation : X01 := '0';
TYPE mode_type IS (unk, single, first_exp, other_exp);
TYPE stat_type IS (inact, act);
VARIABLE mode : mode_type;
VARIABLE rd_stat : stat_type;
VARIABLE wr_stat : stat_type;
VARIABLE EFNeg_zd : std_ulogic;
VARIABLE FFNeg_zd : std_ulogic;
VARIABLE XONeg_zd : std_ulogic;
VARIABLE EF_pzd : std_ulogic;
VARIABLE FF_pzd : std_ulogic;
VARIABLE RDPoint : INTEGER RANGE 0 TO TotalLoc := 0;
VARIABLE WRPoint : INTEGER RANGE 0 TO TotalLoc := 0;
VARIABLE Count : INTEGER RANGE 0 TO TotalLoc := 0;
VARIABLE MemData : MemStore;
VARIABLE DataDrive : std_logic_vector(HiDbit DOWNTO 0)
:= (OTHERS => 'Z');
-- Output Glitch Detection Variables
VARIABLE FFNeg_GlitchData : VitalGlitchDataType;
VARIABLE EFNeg_GlitchData : VitalGlitchDataType;
VARIABLE XONeg_GlitchData : VitalGlitchDataType;
VARIABLE EFp_GlitchData : VitalGlitchDataType;
VARIABLE FFp_GlitchData : VitalGlitchDataType;
-- No Weak Values Variables
VARIABLE FLNeg_nwv : UX01 := 'U';
VARIABLE WNeg_nwv : UX01 := 'U';
VARIABLE RNeg_nwv : UX01 := 'U';
VARIABLE RSNeg_nwv : UX01 := 'U';
VARIABLE XINeg_nwv : UX01 := 'U';
BEGIN
FLNeg_nwv := To_UX01 (s => FLNegIn);
WNeg_nwv := To_UX01 (s => WNegIn);
RNeg_nwv := To_UX01 (s => RNegIn);
RSNeg_nwv := To_UX01 (s => RSNegIn);
XINeg_nwv := To_UX01 (s => XINegIn);
--------------------------------------------------------------------
-- Timing Check Section
--------------------------------------------------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => DIn,
TestSignalName => "D",
RefSignal => WNegIn,
RefSignalName => "WNeg",
SetupHigh => tsetup_D0_WNeg,
SetupLow => tsetup_D0_WNeg,
HoldHigh => thold_D0_WNeg,
HoldLow => thold_D0_WNeg,
CheckEnabled => (WNeg_nwv ='0'),
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_D0_WNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D0_WNeg );
VitalSetupHoldCheck (
TestSignal => RNegIn,
TestSignalName => "RNeg",
RefSignal => RSNegIn,
RefSignalName => "RSNeg",
SetupHigh => tsetup_RNeg_RSNeg,
SetupLow => tsetup_RNeg_RSNeg,
HoldHigh => thold_RNeg_RSNeg,
HoldLow => thold_RNeg_RSNeg,
CheckEnabled => (RSNeg_nwv ='0'),
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_RNeg_RSNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_RNeg_RSNeg );
VitalSetupHoldCheck (
TestSignal => RNegIn,
TestSignalName => "RNeg",
RefSignal => FLNegIn,
RefSignalName => "FLNeg",
SetupHigh => tsetup_RNeg_FLNeg,
SetupLow => tsetup_RNeg_FLNeg,
HoldHigh => thold_RNeg_FLNeg,
HoldLow => thold_RNeg_FLNeg,
CheckEnabled => (FLNeg_nwv ='0'),
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_RNeg_FLNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_RNeg_FLNeg );
VitalSetupHoldCheck (
TestSignal => XINegIn,
TestSignalName => "XINeg",
RefSignal => RNegIn,
RefSignalName => "RNeg",
SetupHigh => tsetup_XINeg_RNeg,
SetupLow => tsetup_XINeg_RNeg,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_XINeg_RNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_XINeg_RNeg );
VitalSetupHoldCheck (
TestSignal => XINegIn,
TestSignalName => "XINeg",
RefSignal => WNegIn,
RefSignalName => "WNeg",
SetupHigh => tsetup_XINeg_RNeg,
SetupLow => tsetup_XINeg_RNeg,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_XINeg_WNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_XINeg_WNeg );
VitalPeriodPulseCheck (
TestSignal => RNegIn,
TestSignalName => "RNeg",
Period => tperiod_RNeg,
PulseWidthLow => tpw_RNeg_negedge,
PulseWidthHigh => tpw_RNeg_posedge,
PeriodData => TD_RNeg,
XOn => XOn,
MsgOn => MsgOn,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE,
Violation => Pviol_RNeg );
VitalPeriodPulseCheck (
TestSignal => WNegIn,
TestSignalName => "WNeg",
Period => tperiod_WNeg,
PulseWidthLow => tpw_WNeg_negedge,
PulseWidthHigh => tpw_WNeg_posedge,
PeriodData => TD_WNeg,
XOn => XOn,
MsgOn => MsgOn,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE,
Violation => Pviol_WNeg );
VitalPeriodPulseCheck (
TestSignal => XINegIn,
TestSignalName => "XINeg",
PulseWidthLow => tpw_XINeg_negedge,
PeriodData => TD_XINeg,
XOn => XOn,
MsgOn => MsgOn,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE,
Violation => Pviol_XINeg );
VitalPeriodPulseCheck (
TestSignal => FLNegIn,
TestSignalName => "FLNeg",
PulseWidthLow => tpw_FLNeg_negedge,
PulseWidthHigh => tpw_FLNeg_posedge,
PeriodData => TD_FLNeg,
XOn => XOn,
MsgOn => MsgOn,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE,
Violation => Pviol_FLNeg );
END IF; -- Timing Check Section
--------------------------------------------------------------------
-- Functional Section
--------------------------------------------------------------------
Violation := Tviol_D0_WNeg OR Tviol_RNeg_RSNeg OR Tviol_RNeg_FLNeg
OR Tviol_XINeg_RNeg OR Tviol_XINeg_WNeg OR Pviol_RNeg
OR Pviol_WNeg OR Pviol_RSNeg OR Pviol_FLNeg OR
Pviol_XINeg;
IF (Violation = 'X') THEN
DataDrive := (OTHERS => 'X');
FFNeg_zd := 'X';
EFNeg_zd := 'X';
XONeg_zd := 'X';
ELSIF falling_edge(RSNegIn) THEN
RDPoint := 0;
WRPoint := 0;
Count := 0;
ELSIF rising_edge(RSNegIn) THEN
FFNeg_zd := '1';
XONeg_zd := '1';
EFNeg_zd := '0';
IF XINeg_nwv = '0' THEN
mode := single;
rd_stat := act;
wr_stat := act;
ELSIF FLNeg_nwv = '0' THEN
mode := first_exp;
rd_stat := act;
wr_stat := act;
ELSE
mode := other_exp;
rd_stat := inact;
wr_stat := inact;
END IF;
END IF;
IF rising_edge(WNegIn) THEN
IF wr_stat = act AND FFNeg_zd = '1' THEN
IF Violation = '0' THEN
MemData(WRPoint) := To_Nat(DIn);
ELSE
MemData(WRPoint) := -1;
END IF;
Count := Count + 1;
IF WRPoint = TotalLoc THEN
WRPoint := 0;
ELSE
WRPoint := WRPoint + 1;
END IF;
IF Count > Half AND mode = single THEN
XONeg_zd := '0';
ELSE
XONeg_zd := '1';
END IF;
IF Count = TotalLoc THEN
FFNeg_zd := '0';
ELSE
FFNeg_zd := '1';
END IF;
IF EFNeg_zd = '0' AND RNeg_nwv = '0' THEN
DataDrive := To_X01(DIn);
EF_pzd := '1';
Count := Count - 1;
RDPoint := RDPoint + 1;
END IF;
EFNeg_zd := '1';
ELSE
IF mode /= single THEN
XONeg_zd := '1';
END IF;
END IF;
ELSIF falling_edge(WNegIn) AND mode /= single AND Count = TotalLoc THEN
XONeg_zd := '0';
wr_stat := inact;
END IF;
IF falling_edge(RNegIn) AND EFNeg_zd = '1' AND rd_stat = act THEN
IF Violation = '0' THEN
IF MemData(RDPoint) >= 0 THEN
DataDrive := To_slv(MemData(RDPoint), DataWidth);
ELSE
DataDrive := (OTHERS => 'X');
END IF;
ELSE
MemData(WRPoint) := -1;
END IF;
Count := Count - 1;
IF Count > Half AND mode = single THEN
XONeg_zd := '0';
ELSE
XONeg_zd := '1';
END IF;
IF Count = 0 THEN
EFNeg_zd := '0';
IF mode = other_exp THEN
XONeg_zd := '0';
END IF;
ELSE
EFNeg_zd := '1';
END IF;
if (RDPoint = WRPoint-1) or -- We must increment RDPoint if it
(WRPoint=0 and RDPoint=TotalLoc) then -- is the last element because...
IF RDPoint = TotalLoc THEN
RDPoint := 0;
ELSE
RDPoint := RDPoint + 1;
END IF;
end if;
ELSIF rising_edge(RNegIn) THEN
IF EFNeg_zd = '1' AND rd_stat = act THEN
IF FFNeg_zd = '0' AND WNeg_nwv = '0' THEN
FF_pzd := '1';
END IF;
FFNeg_zd := '1';
IF RDPoint = TotalLoc THEN
RDPoint := 0;
ELSE
RDPoint := RDPoint + 1;
END if;
END IF;
IF mode = other_exp AND Count = 0 THEN
XONeg_zd := '1';
rd_stat := inact;
END IF;
END IF;
IF falling_edge(FLNegIn) AND XINeg_nwv = '0' THEN
RDPoint := 0;
Count := WRPoint;
IF Count > Half THEN
XONeg_zd := '0';
ELSE
XONeg_zd := '1';
END IF;
IF Count = 0 THEN
EFNeg_zd := '0';
ELSE
EFNeg_zd := '1';
END IF;
IF Count = TotalLoc THEN
FFNeg_zd := '0';
ELSE
FFNeg_zd := '1';
END IF;
ELSIF falling_edge(XINegIn) AND mode = other_exp THEN
IF wr_stat = inact THEN
wr_stat := act;
ELSE
rd_stat := act;
END IF;
END IF;
IF rising_edge(EF_pulse) THEN
EFNeg_zd := '0';
EF_pulse <= '0';
ELSIF rising_edge(FF_pulse) THEN
FFNeg_zd := '0';
FF_pulse <= '0';
END IF;
IF rising_edge(RNegIn) THEN
DataDrive := (others => 'Z');
END IF;
Q_zd <= DataDrive;
--------------------------------------------------------------------
-- Path Delay Section
--------------------------------------------------------------------
VitalPathDelay01 (
OutSignal => EF_pulse,
OutSignalName => "EF_pulse",
OutTemp => EF_pzd,
GlitchData => EFp_GlitchData,
XOn => false,
MsgOn => false,
Paths => (
0 => (InputChangeTime => WNeg'LAST_EVENT,
PathDelay => tpd_RNeg_EFNeg,
PathCondition => true)
)
);
VitalPathDelay01 (
OutSignal => FF_pulse,
OutSignalName => "FF_pulse",
OutTemp => FF_pzd,
GlitchData => FFp_GlitchData,
XOn => false,
MsgOn => false,
Paths => (
0 => (InputChangeTime => RNeg'LAST_EVENT,
PathDelay => tpd_WNeg_FFNeg,
PathCondition => true)
)
);
VitalPathDelay01 (
OutSignal => EFNegOut,
OutSignalName => "EFNeg",
OutTemp => EFNeg_zd,
GlitchData => EFNeg_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => FLNeg'LAST_EVENT,
PathDelay => tpd_FLNeg_EFNeg,
PathCondition => FLNeg_nwv = '0'),
1 => (InputChangeTime => RNeg'LAST_EVENT,
PathDelay => tpd_RNeg_EFNeg,
PathCondition => true),
2 => (InputChangeTime => WNeg'LAST_EVENT,
PathDelay => tpd_WNeg_EFNeg,
PathCondition => true),
3 => (InputChangeTime => RSNeg'LAST_EVENT,
PathDelay => tpd_RSNeg_EFNeg,
PathCondition => true),
4 => (InputChangeTime => EF_pulse'LAST_EVENT,
PathDelay => tpd_RNeg_EFNeg,
PathCondition => true)
)
);
VitalPathDelay01 (
OutSignal => FFNegOut,
OutSignalName => "FFNeg",
OutTemp => FFNeg_zd,
GlitchData => FFNeg_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => FLNeg'LAST_EVENT,
PathDelay => tpd_FLNeg_EFNeg,
PathCondition => FLNeg_nwv = '0'),
1 => (InputChangeTime => RNeg'LAST_EVENT,
PathDelay => tpd_RNeg_FFNeg,
PathCondition => true),
2 => (InputChangeTime => WNeg'LAST_EVENT,
PathDelay => tpd_WNeg_FFNeg,
PathCondition => true),
3 => (InputChangeTime => RSNeg'LAST_EVENT,
PathDelay => tpd_RSNeg_FFNeg,
PathCondition => true),
4 => (InputChangeTime => FF_pulse'LAST_EVENT,
PathDelay => tpd_WNeg_EFNeg,
PathCondition => true)
)
);
VitalPathDelay01 (
OutSignal => XONegOut,
OutSignalName => "XONeg",
OutTemp => XONeg_zd,
GlitchData => XONeg_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => FLNeg'LAST_EVENT,
PathDelay => tpd_FLNeg_EFNeg,
PathCondition => FLNeg_nwv = '0'),
1 => (InputChangeTime => RNeg'LAST_EVENT,
PathDelay => tpd_RNeg_XONeg,
PathCondition => true),
2 => (InputChangeTime => WNeg'LAST_EVENT,
PathDelay => tpd_WNeg_XONeg,
PathCondition => true),
3 => (InputChangeTime => RSNeg'LAST_EVENT,
PathDelay => tpd_RSNeg_XONeg,
PathCondition => true)
)
);
END PROCESS Fifo;
------------------------------------------------------------------------
-- Path Delay Processes generated as a function of data width
------------------------------------------------------------------------
DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE
DataOut_Delay : PROCESS (Q_zd(i))
VARIABLE Q_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
BEGIN
VitalPathDelay01Z (
OutSignal => QOut(i),
OutSignalName => "Q",
OutTemp => Q_zd(i),
Mode => VitalTransport,
GlitchData => Q_GlitchData(i),
Paths => (
0 => (InputChangeTime => RNegIn'LAST_EVENT,
PathDelay => tpd_RNeg_Q0,
PathCondition => TRUE),
1 => (InputChangeTime => WNegIn'LAST_EVENT,
PathDelay => tpd_WNeg_Q0,
PathCondition => TRUE)
)
);
END PROCESS;
END GENERATE;
END BLOCK;
END vhdl_behavioral;
--pragma translate_on
|
gpl-2.0
|
1d0c1f9c1d1ba338d2773256dd2d4701
| 0.408028 | 5.07345 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/unisim/ddr_unisim.vhd
| 1 | 12,176 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: unisim_iddr_reg
-- File: unisim_iddr_reg.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: Xilinx DDR input register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.iddr;
--pragma translate_on
entity unisim_iddr_reg is
generic (tech : integer := virtex4;arch : integer := 0);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of unisim_iddr_reg is
attribute BOX_TYPE : string;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
attribute BOX_TYPE of IDDR : component is "PRIMITIVE";
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preQ1, preQ2 : std_ulogic;
signal D_delay : std_ulogic;
begin
V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "SAME_EDGE")
Port map( Q1 => Q1, Q2 => Q2, C => C1, CE => CE,
D => D, R => R, S => S);
end generate;
V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = zynq7000) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE")
Port map( Q1 => Q1, Q2 => preQ2, C => C1, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
S6 : if (tech = spartan6) generate
noalign : if arch = 0 generate
U0 : IDDR2 generic map( DDR_ALIGNMENT => "NONE")
Port map( Q0 => Q1, Q1 => preQ2, C0 => C1, C1 => C2, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1)
begin
if C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
align : if arch /= 0 generate
U0 : IDDR2 generic map( DDR_ALIGNMENT => "C0")
Port map( Q0 => preQ1, Q1 => Q2, C0 => C1, C1 => C2, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1)
begin
if C1'event and C1='1' then --Clock event - posedge
Q1 <= preQ1;
end if;
end process;
end generate;
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
-- CE and S inputs inactive for virtex 2
q1reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
Q1 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q1 <= D;
end if;
end process;
q2reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
preQ2 <= '0';
elsif C1'event and C1='0' then --Clock event - negedge
preQ2 <= D;
end if;
end process;
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
-- S6 : if tech = spartan6 generate
--
-- x0 : IFDDRRSE port map (
-- Q0 => Q1, Q1 => Q2, C0 => C1, C1 => C2, CE => CE,
-- D => D, R => R, S => S);
--
-- end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.oddr;
use unisim.oddr2;
--use unisim.FDDRRSE;
--pragma translate_on
entity unisim_oddr_reg is
generic (tech : integer := virtex4; arch : integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of unisim_oddr_reg is
attribute BOX_TYPE : string;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR : component is "PRIMITIVE";
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "ASYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR2 : component is "PRIMITIVE";
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
FDDRRSE : component is "PRIMITIVE";
signal preD2 : std_ulogic;
begin
V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate
U0 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE")
port map(
Q => Q, C => C1, CE => CE, D1 => D1,
D2 => D2, R => R, S => S);
end generate;
V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = zynq7000) generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
U0 : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE" -- ,INIT => '0'
, SRTYPE => "ASYNC")
port map(
Q => Q,
C => C1,
CE => CE,
D1 => D1,
D2 => preD2,
R => R,
S => S);
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
c_dm : component FDDRRSE
-- generic map( INIT => '0')
port map(
Q => Q,
D0 => D1,
D1 => preD2,
C0 => C1,
C1 => C2,
CE => CE,
R => R,
S => S);
end generate;
s6 : if tech = spartan6 generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
c_dm : component ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC")
port map (
Q => Q,
C0 => C1,
C1 => C2,
CE => CE,
D0 => D1,
D1 => D2,
R => R,
S => S);
end generate;
end ;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
--use unisim.FDDRRSE;
--pragma translate_on
entity oddrv2 is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrv2 is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDDRRSE
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : FDDRRSE port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
use unisim.oddr2;
--pragma translate_on
entity oddrc3e is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrc3e is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : ODDR2 port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
|
gpl-2.0
|
319f9e7cc4327f9c3a659045863f12e3
| 0.521025 | 3.40397 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/serdes.vhd
| 1 | 6,690 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes
-- File: serdes.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII Gigabit Ethernet PMA Physical Media Attachment
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
entity serdes is
generic (
fabtech : integer;
transtech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in_p : in std_logic; -- SER IN
rx_in_n : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out_p : out std_logic; -- SER OUT
tx_out_n : out std_logic; -- SER OUT
bitslip : in std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
serdes_ready: out std_logic);
end;
architecture rtl of serdes is
component serdes_stratixiii is
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end component;
component igloo2_serdes is
port(
apb_in : in apb_in_serdes;
apb_out : out apb_out_serdes;
insig : in sigin_serdes_type;
outsig : out sigout_serdes_type;
padin : in pad_in_serdes;
padout : out pad_out_serdes);
end component;
component serdes_unisim is
generic (
transtech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in_p : in std_logic; -- SER IN
rx_in_n : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out_p : out std_logic; -- SER OUT
tx_out_n : out std_logic; -- SER OUT
bitslip : in std_logic
);
end component;
signal rst_125n, rx_clk_serdes, rx_rstn_serdes, rx_val_serdes, tx_rstn_serdes, tx_clk_lock_serdes, rx_idle : std_logic;
signal tx_out_p_int : std_logic;
begin
str : if (fabtech = stratix3) or (fabtech = stratix4) generate
str0 : serdes_stratixiii
port map (clk_125, rst_125, rx_in_p, rx_out, rx_clk, rx_rstn, rx_pll_clk, rx_pll_rstn, tx_pll_clk, tx_pll_rstn, tx_in, tx_out_p_int, bitslip);
apbout <= apb_out_serdes_none; m2gl_padout <= pad_out_serdes_none; serdes_clk125 <= '0'; serdes_ready <= '1'; -- not used
tx_out_n <= not tx_out_p_int; -- not used
end generate;
xilinx : if (fabtech = virtex5) or (fabtech = virtex6) generate
xil0 : serdes_unisim
generic map (transtech)
port map (clk_125, rst_125, rx_in_p, rx_in_n, rx_out, rx_clk, rx_rstn, rx_pll_clk, rx_pll_rstn, tx_pll_clk, tx_pll_rstn, tx_in, tx_out_p, tx_out_n, bitslip);
apbout <= apb_out_serdes_none; m2gl_padout <= pad_out_serdes_none; serdes_clk125 <= '0'; serdes_ready <= '1'; -- not used
end generate;
igl2 : if (fabtech = igloo2) generate
rst_125n <= not(rst_125); -- used as SERDES macro reset
rx_clk <= rx_clk_serdes;
rx_pll_clk <= rx_clk_serdes;
rx_rstn <= rx_rstn_serdes and rx_val_serdes;
rx_pll_rstn <= rx_rstn_serdes and rx_val_serdes;
tx_pll_rstn <= tx_rstn_serdes and tx_clk_lock_serdes;
tx_out_p <= '0'; -- not used
tx_out_n <= '0'; -- not used
igl20 : igloo2_serdes
port map (
apb_in => apbin,
apb_out => apbout,
padin => m2gl_padin,
padout => m2gl_padout,
insig.rstn => rst_125n,
insig.tx_data => tx_in,
outsig.ready => serdes_ready,
outsig.rx_clk => rx_clk_serdes,
outsig.rx_data => rx_out,
outsig.rx_idle => rx_idle,
outsig.rx_rstn => rx_rstn_serdes,
outsig.rx_val => rx_val_serdes,
outsig.tx_clk => tx_pll_clk,
outsig.tx_clk_lock => tx_clk_lock_serdes,
outsig.tx_rstn => tx_rstn_serdes,
outsig.refclk => serdes_clk125);
end generate;
-- pragma translate_off
nofifo : if (has_transceivers(fabtech) = 0) generate
x : process
begin
assert false report "serdes: technology " & tech_table(fabtech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "serdes: (" & tech_table(fabtech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
gpl-2.0
|
0a81f5f860383de6b9a5129dfb4333ae
| 0.579073 | 3.365191 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/arith/arith.vhd
| 1 | 4,810 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: arith
-- File: arith.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Declaration of mul/div components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package arith is
type div32_in_type is record
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
op1 : std_logic_vector(32 downto 0); -- operand 1 (LSB divident)
op2 : std_logic_vector(32 downto 0); -- operand 2 (divisor)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul32_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector(39 downto 0);
--y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
--asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
component div32
generic (scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
divi : in div32_in_type;
divo : out div32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end component;
component mul32
generic (
tech : integer := 0;
multype : integer := 0;
pipe : integer := 0;
mac : integer := 0;
arch : integer range 0 to 3 := 0;
scantest: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end component;
function smult ( a, b : in std_logic_vector) return std_logic_vector;
function umult ( a, b : in std_logic_vector) return std_logic_vector;
end;
package body arith is
function smult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : signed (a'length-1 downto 0);
variable sb : signed (b'length-1 downto 0);
variable sc : signed ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := signed(a); sb := signed(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
function umult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : unsigned (a'length-1 downto 0);
variable sb : unsigned (b'length-1 downto 0);
variable sc : unsigned ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := unsigned(a); sb := unsigned(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
end;
|
gpl-2.0
|
5e3f637dc4bd097c9799562b3744d3e2
| 0.5842 | 3.505831 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-nuhorizons-3s1500/smc_mctrl.vhd
| 4 | 33,528 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity smc_mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_logic; -- for smsc eth
eth_readn : out std_logic; -- for smsc eth
eth_writen: out std_logic; -- for smsc eth
eth_nbe : out std_logic_vector(3 downto 0);
eth_din : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of smc_mctrl is
constant REVISION : integer := 0;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
eth_aen : std_logic; -- for smsc eth
eth_readn : std_logic; -- for smsc eth
eth_writen : std_logic; -- for smsc eth
eth_nbe : std_logic_vector(3 downto 0);-- for smsc eth
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rsbdrive, risbdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive, rsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
if r.iosn(0) = '0' then v.data := eth_din; else v.data := memi.data; end if;
v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1') or (((sdmo.aload and r.hsel) = '1') and SDRAMEN))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbreadword(ahbsi.hwdata, r.address(4 downto 2));
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then v.writedata := writedata;
else
v.writedata(31 downto 16) := writedata(31 downto 16);
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or (r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 19) := sdmo.prdata(31 downto 19);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
v.hresp := sdmo.hresp;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- for smc lan chip ********************************************
if (r.iosn(0) = '1' and v.iosn(0) = '0') then
v.eth_aen := '0';
v.eth_nbe := v.wrn and not (r.read&r.read&r.read&r.read);
elsif (r.iosn(0) = '1' and r.eth_aen = '0') then
v.eth_aen := '1';
v.eth_nbe := v.wrn;
end if;
if (r.eth_aen = '0' and v.iosn(0) = '0' and r.read = '1') then
v.eth_readn := '0';
else
v.eth_readn := '1';
end if;
if (r.eth_aen = '0' and v.iosn(0) = '0' and r.writen = '0') then
v.eth_writen := '0';
else
v.eth_writen := '1';
end if;
-- *************************************************************
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
v.eth_aen := '1'; -- for smsc eth
v.eth_readn := '1'; -- for smsc eth
v.eth_writen := '1'; -- for smsc eth
v.eth_nbe := (others => '1'); -- for smsc eth
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.address;
memo.sa <= r.sa;
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.bdrive <= bdrive;
memo.data <= r.writedata;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
memo.mben <= r.mben;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rsbdrive;
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
-- for smsc eth
eth_aen <= r.eth_aen;
eth_readn <= r.eth_readn;
eth_writen <= r.eth_writen;
eth_nbe <= r.eth_nbe;
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (rst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => sdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
--sdmo <= ((others => '0'), '0', '0', '0', '1', '0', "11");
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
end generate;
end;
|
gpl-2.0
|
44d6787df05547ba36c6318d4fa26b68
| 0.542054 | 3.170796 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/umc18/memory_umc18.vhd
| 1 | 9,463 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_umc_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for UMC rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library umc18;
use umc18.SRAM_2048wx32b;
use umc18.SRAM_1024wx32b;
use umc18.SRAM_512wx32b;
use umc18.SRAM_256wx32b;
use umc18.SRAM_128wx32b;
use umc18.SRAM_64wx32b;
use umc18.SRAM_32wx32b;
use umc18.SRAM_2048wx40b;
use umc18.SRAM_1024wx40b;
use umc18.SRAM_512wx40b;
use umc18.SRAM_256wx40b;
use umc18.SRAM_128wx40b;
use umc18.SRAM_64wx40b;
use umc18.SRAM_32wx40b;
-- pragma translate_on
entity umc_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of umc_syncram is
component SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(41 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc, csn, wen : std_ulogic;
constant synopsys_bug : std_logic_vector(41 downto 0) := (others => '0');
begin
csn <= not enable; wen <= not write;
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(41 downto dbits) <= synopsys_bug(41 downto dbits);
dataout <= q(dbits -1 downto 0);
-- q(41 downto dbits) <= synopsys_bug(41 downto dbits);
d32 : if (dbits <= 32) generate
a5d32 : if (abits <= 5) generate
id0 : SRAM_32wx32b port map (a(4 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a6d32 : if (abits = 6) generate
id0 : SRAM_64wx32b port map (a(5 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a7d32 : if (abits = 7) generate
id0 : SRAM_128wx32b port map (a(6 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a8d32 : if (abits = 8) generate
id0 : SRAM_256wx32b port map (a(7 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a9d32 : if (abits = 9) generate
id0 : SRAM_512wx32b port map (a(8 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a10d32 : if (abits = 10) generate
id0 : SRAM_1024wx32b port map (a(9 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a11d32 : if (abits = 11) generate
id0 : SRAM_2048wx32b port map (a(10 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
end generate;
d40 : if (dbits > 32) and (dbits <= 40) generate
a5d40 : if (abits <= 5) generate
id0 : SRAM_32wx40b port map (a(4 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a6d40 : if (abits = 6) generate
id0 : SRAM_64wx40b port map (a(5 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a7d40 : if (abits = 7) generate
id0 : SRAM_128wx40b port map (a(6 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a8d40 : if (abits = 8) generate
id0 : SRAM_256wx40b port map (a(7 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a9d40 : if (abits = 9) generate
id0 : SRAM_512wx40b port map (a(8 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a10d40 : if (abits = 10) generate
id0 : SRAM_1024wx40b port map (a(9 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a11d40 : if (abits = 11) generate
id0 : SRAM_2048wx40b port map (a(10 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
end generate;
-- pragma translate_off
a_to_high : if (abits > 11) or (dbits > 40) generate
x : process
begin
assert false
report "Unsupported memory size (umc18)"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
gpl-2.0
|
c341acec4cb2c9937f2022eee73d7763
| 0.606679 | 2.911692 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2s60-ddr/config.vhd
| 1 | 5,607 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
2e7d868c7bb6ad4309fedb7615b8201d
| 0.643303 | 3.650391 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/pcitrace/pcitrace.vhd
| 1 | 7,755 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitrace
-- File: pcitrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI trace buffer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
entity pcitrace is
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of pcitrace is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCITRACE, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
sample : std_ulogic;
armed : std_ulogic;
busy : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
admask : std_logic_vector(31 downto 0);
adpattern : std_logic_vector(31 downto 0);
sigmask : std_logic_vector(15 downto 0);
sigpattern : std_logic_vector(15 downto 0);
count : std_logic_vector(7 downto 0);
end record;
type pci_reg_type is record
sample : std_ulogic;
armed : std_ulogic;
sync : std_ulogic;
start : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
baddr : std_logic_vector(depth-1 downto 0);
count : std_logic_vector(7 downto 0);
end record;
signal r, rin : reg_type;
signal csad, csctrl : std_ulogic;
signal pr, prin : pci_reg_type;
signal bufout : std_logic_vector(47 downto 0);
signal pciad : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal pcictrlin, pcictrl : std_logic_vector(15 downto 0);
begin
vcc <= '1';
comb: process(pcii, apbi, rst, r, pr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable paddr : std_logic_vector(3 downto 0);
variable vcsad, vcssig : std_ulogic;
begin
v := r; vcsad := '0'; vcssig := '0'; rdata := (others => '0');
v.sample := r.armed and not pr.armed; v.busy := pr.sample;
if (r.sample and pr.armed) = '1' then v.armed := '0'; end if;
--registers
paddr := apbi.paddr(15) & apbi.paddr(4 downto 2);
if apbi.penable = '1' then
if (apbi.pwrite and apbi.psel(pindex)) = '1' then
case paddr is
when "0000" => v.admask := apbi.pwdata;
when "0001" => v.sigmask := apbi.pwdata(15 downto 0);
when "0010" => v.adpattern := apbi.pwdata;
when "0011" => v.sigpattern := apbi.pwdata(15 downto 0);
when "0100" => v.timeout := apbi.pwdata(depth-1 downto 0);
when "0101" => v.armed := '1';
when "0111" => v.count := apbi.pwdata(7 downto 0);
when others =>
if apbi.paddr(15 downto 14) = "10" then vcsad := '1';
elsif apbi.paddr(15 downto 14) = "11" then vcssig := '1'; end if;
end case;
end if;
case paddr is
when "0000" => rdata := r.admask;
when "0001" => rdata(15 downto 0) := r.sigmask;
when "0010" => rdata := r.adpattern;
when "0011" => rdata(15 downto 0) := r.sigpattern;
when "0100" => rdata(depth-1 downto 0) := r.timeout;
when "0101" => rdata(0) := r.busy;
when "0110" => rdata(3 downto 0) := conv_std_logic_vector(depth, 4);
when "0111" =>
rdata(depth-1+16 downto 16) := pr.baddr;
rdata(15 downto 0) := pr.count & r.count;
when others =>
if apbi.paddr(15 downto 14) = "10" then
vcsad := '1'; rdata := bufout(31 downto 0);
elsif apbi.paddr(15 downto 14) = "11" then
vcssig := '1'; rdata(15 downto 0) := bufout(47 downto 32);
end if;
end case;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.admask := (others => '0');
v.sigmask := (others => '0'); v.adpattern := (others => '0');
v.sigpattern := (others => '0'); v.timeout := (others => '0');
end if;
csad <= vcsad; csctrl <= vcssig; apbo.prdata <= rdata; rin <= v;
end process;
comb2 : process(r, pr, pciclk, pcii, pcictrl, rst)
variable v : pci_reg_type;
constant z : std_logic_vector(47 downto 0) := (others => '0');
begin
v := pr; v.sync := (r.sample and not pr.armed);
if (pr.sample = '1') then
v.baddr := pr.baddr + 1;
if ((((pcii.ad & pcictrl) xor (r.adpattern & r.sigpattern)) and (r.admask & r.sigmask)) = z) then
if pr.count = "00000000" then v.start := '0';
else v.count := pr.count -1; end if;
end if;
if (pr.start = '0') then
v.timeout := pr.timeout - 1;
if (v.timeout(depth-1) and not pr.timeout(depth-1)) = '1' then
v.sample := '0'; v.armed := '0';
end if;
end if;
end if;
if pr.sync = '1' then
v.start := '1'; v.sample := '1'; v.armed := '1';
v.timeout := r.timeout; v.count := r.count;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.start := '0';
v.timeout := (others => '0'); v.baddr := (others => '0');
v.count := (others => '0');
end if;
prin <= v;
end process ;
pcictrlin <= pcii.rst & pcii.idsel & pcii.frame & pcii.trdy & pcii.irdy &
pcii.devsel & pcii.gnt & pcii.stop & pcii.lock & pcii.perr &
pcii.serr & pcii.par & pcii.cbe;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
seq: process (clk)
begin
if clk'event and clk = '1' then r <= rin; end if;
end process seq;
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then pr <= prin; end if;
end process ;
ir : if iregs = 1 generate
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then
pcictrl <= pcictrlin; pciad <= pcii.ad;
end if;
end process ;
end generate;
noir : if iregs = 0 generate
pcictrl <= pcictrlin; pciad <= pcii.ad;
end generate;
admem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 32, sepclk => 1)
port map (clk, csad, apbi.paddr(depth+1 downto 2), bufout(31 downto 0),
pciclk, pr.sample, pr.baddr, pciad);
ctrlmem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 16, sepclk => 1)
port map (clk, csctrl, apbi.paddr(depth+1 downto 2), bufout(47 downto 32),
pciclk, pr.sample, pr.baddr, pcictrl);
end;
|
gpl-2.0
|
f840f49d6925c752bf80bf025009e101
| 0.578337 | 3.336919 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/uart/apbuart.vhd
| 1 | 20,625 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: uart.vhd
-- Authors: Jiri Gaisler - Gaisler Research
-- Marko Isomaki - Gaisler Research
-- Description: Asynchronous UART. Implements 8-bit data frame with one stop-bit.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbuart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of apbuart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity);
type fifo is array (0 to fifosize - 1) of std_logic_vector(7 downto 0);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
debug : std_ulogic; -- debug mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
tsemptyirqen : std_ulogic; -- generate irq when tx shift register is empty
break : std_ulogic; -- break detected
breakirqen : std_ulogic; -- generate irq when break has been received
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
ctsn : std_logic_vector(1 downto 0); -- clear to send
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : fifo;
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(9 downto 0);
thold : fifo;
irq : std_ulogic; -- tx/rx interrupt (internal)
irqpend : std_ulogic; -- pending irq for delayed rx irq
delayirqen : std_ulogic; -- enable delayed rx irq
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(sbits-1 downto 0);
brate : std_logic_vector(sbits-1 downto 0);
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
rfifoirqen : std_ulogic; -- receiver fifo interrupt enable
tfifoirqen : std_ulogic; -- transmitter fifo interrupt enable
irqcnt : std_logic_vector(5 downto 0); -- delay counter for rx irq
--fifo counters
rwaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rraddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
traddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
twaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rcnt : std_logic_vector(log2x(fifosize) downto 0);
tcnt : std_logic_vector(log2x(fifosize) downto 0);
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant addrzero : std_logic_vector(log2x(fifosize)-1 downto 0) := (others => '0');
constant sbitszero : std_logic_vector(sbits-1 downto 0) := (others => '0');
constant fifozero : fifo := (others => (others => '0'));
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs :=
(rxen => '0', txen => '0', rirqen => '0', tirqen => '0', parsel => '0',
paren => '0', flow => '0', loopb => '0', debug => '0', rsempty => '1',
tsempty => '1', tsemptyirqen => '0', break => '0', breakirqen => '0',
ovf => '0', parerr => '0', frame => '0', ctsn => (others => '0'),
rtsn => '1', extclken => '0', extclk => '0', rhold => fifozero,
rshift => (others => '0'), tshift => (others => '1'), thold => fifozero,
irq => '0', irqpend => '0', delayirqen => '0', tpar => '0', txstate => idle,
txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), dpar => '0',rxtick => '0',
tick => '0', scaler => sbitszero, brate => sbitszero, rxf => (others => '0'),
txd => '1', rfifoirqen => '0', tfifoirqen => '0', irqcnt => (others => '0'),
rwaddr => addrzero, rraddr => addrzero, traddr => addrzero, twaddr => addrzero,
rcnt => rcntzero, tcnt => rcntzero);
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(sbits-1 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : uartregs;
variable thalffull : std_ulogic;
variable rhalffull : std_ulogic;
variable rfull : std_ulogic;
variable tfull : std_ulogic;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
dready := '0'; thempty := '1'; thalffull := '1'; rhalffull := '0';
v.ctsn := r.ctsn(0) & uarti.ctsn;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if fifosize = 1 then
dready := r.rcnt(0); rfull := dready; tfull := r.tcnt(0);
thempty := not tfull;
else
tfull := r.tcnt(log2x(fifosize)); rfull := r.rcnt(log2x(fifosize));
if (r.rcnt(log2x(fifosize)) or r.rcnt(log2x(fifosize) - 1)) = '1' then
rhalffull := '1';
end if;
if ((r.tcnt(log2x(fifosize)) or r.tcnt(log2x(fifosize) - 1))) = '1' then
thalffull := '0';
end if;
if r.rcnt /= rcntzero then dready := '1'; end if;
if r.tcnt /= rcntzero then thempty := '0'; end if;
end if;
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(sbits-1) and not r.scaler(sbits-1);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold(conv_integer(r.rraddr));
if fifosize = 1 then v.rcnt(0) := '0';
else
if r.rcnt /= rcntzero then
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "000001" =>
if fifosize /= 1 then
rdata (26 + log2x(fifosize) downto 26) := r.rcnt;
rdata (20 + log2x(fifosize) downto 20) := r.tcnt;
rdata (10 downto 7) := rfull & tfull & rhalffull & thalffull;
end if;
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & thempty & r.tsempty & dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
if fifosize > 1 then
rdata(31) := '1';
end if;
rdata(14) := r.tsemptyirqen;
rdata(13) := r.delayirqen;
rdata(12) := r.breakirqen;
rdata(11) := r.debug;
if fifosize /= 1 then
rdata(10 downto 9) := r.rfifoirqen & r.tfifoirqen;
end if;
rdata(8 downto 0) := r.extclken & r.loopb &
r.flow & r.paren & r.parsel & r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
rdata(sbits-1 downto 0) := r.brate;
when "000100" =>
-- Read TX FIFO.
if r.debug = '1' and r.tcnt /= rcntzero then
rdata(7 downto 0) := r.thold(conv_integer(r.traddr));
if fifosize = 1 then
v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
when "000001" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "000010" =>
v.tsemptyirqen := apbi.pwdata(14);
v.delayirqen := apbi.pwdata(13);
v.breakirqen := apbi.pwdata(12);
v.debug := apbi.pwdata(11);
if fifosize /= 1 then
v.rfifoirqen := apbi.pwdata(10);
v.tfifoirqen := apbi.pwdata(9);
end if;
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
v.brate := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "000100" =>
-- Write RX fifo and generate irq
if flow /= 0 then
v.rhold(conv_integer(r.rwaddr)) := apbi.pwdata(7 downto 0);
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
if r.debug = '1' then
v.irq := v.irq or r.rirqen;
end if;
end if;
when others =>
null;
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
if (r.rxtick and r.delayirqen) = '1' then
v.irqcnt := v.irqcnt + 1;
end if;
if r.irqcnt(5 downto 4) = "11" then
v.irq := v.irq or (r.delayirqen and r.irqpend); -- make sure no tx irqs are lost !
v.irqpend := '0';
end if;
-- filter rx data
-- v.rxf := r.rxf(6 downto 0) & uarti.rxd;
-- if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
-- r.rxf(7)) = r.rxf(6 downto 0))
-- then v.rxdb(0) := r.rxf(7); end if;
v.rxf(1 downto 0) := r.rxf(0) & uarti.rxd; -- meta-stability filter
if r.tick = '1' then
v.rxf(4 downto 2) := r.rxf(3 downto 1);
end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := dready and not r.rsempty;
elsif (flow = 1) then ctsn := r.ctsn(1); else ctsn := '0'; end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle and stopbit state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((not r.debug and r.txen and (not thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.txstate := data;
v.tpar := r.parsel; v.tsempty := '0';
v.txclk := "00" & r.tick; v.txtick := '0';
v.tshift := '0' & r.thold(conv_integer(r.traddr)) & '0';
if fifosize = 1 then
v.irq := r.irq or r.tirqen; v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(9 downto 1);
if r.tshift(9 downto 1) = "111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := idle;
end if;
end if;
end if;
when cparity => -- transmit parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(9 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(4 downto 2) is
when "000" =>
if fifosize = 1 then
v.thold(0) := apbi.pwdata(7 downto 0); v.tcnt(0) := '1';
else
v.thold(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
if not (tfull = '1') then
v.twaddr := r.twaddr + 1; v.tcnt := v.tcnt + 1;
end if;
end if;
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((r.rsempty = '0') and not (rfull = '1')) then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if r.delayirqen = '0' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
end if;
if rxd = '1' then
if r.delayirqen = '1' then
v.irqpend := r.rirqen; v.irqcnt := (others => '0');
end if;
v.parerr := r.parerr or r.dpar; v.rsempty := r.dpar;
if not (rfull = '1') and (r.dpar = '0') then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
else
if r.rshift = "00000000" then
v.break := '1';
v.irq := v.irq or r.breakirqen;
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (rfull and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb or r.debug;
if fifosize /= 1 then
if thempty = '0' and v.tcnt = rcntzero then
v.irq := v.irq or r.tirqen;
end if;
v.irq := v.irq or (r.tfifoirqen and r.txen and thalffull);
v.irq := v.irq or (r.rfifoirqen and r.rxen and rhalffull);
if (r.rfifoirqen and r.rxen and rhalffull) = '1' then
v.irqpend := '0';
end if;
end if;
v.irq := v.irq or (r.tsemptyirqen and v.tsempty and not r.tsempty);
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.parerr := RES.parerr; v.ovf := RES.ovf; v.break := RES.break;
v.tsempty := RES.tsempty; v.txen := RES.txen; v.rxen := RES.rxen;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.extclken := RES.extclken; v.rtsn := RES.rtsn; v.flow := RES.flow;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
v.rcnt := RES.rcnt; v.tcnt := RES.tcnt;
v.rwaddr := RES.rwaddr; v.twaddr := RES.twaddr;
v.rraddr := RES.rraddr; v.traddr := RES.traddr;
v.irqcnt := RES.irqcnt; v.irqpend := RES.irqpend;
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
uarto.scaler <= (others => '0');
uarto.scaler(sbits-1 downto 0) <= r.scaler;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
uarto.txen <= r.txen; uarto.rxen <= r.rxen;
uarto.flow <= '0';
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.ctsn <= rin.ctsn;
r.rxf <= rin.rxf;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
", irq " & tost(pirq) & ", scaler bits " & tost(sbits));
-- pragma translate_on
end;
|
gpl-2.0
|
0ed1e4782276cc07099ed8d671318351
| 0.543758 | 3.333064 | false | false | false | false |
lunod/lt24_ctrl
|
demo/top.vhd
| 1 | 5,092 |
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity top is
port (
clock_50 : in std_logic;
key : in std_logic_vector(1 downto 0);
lt24_reset_n : out std_logic;
lt24_cs_n : out std_logic;
lt24_rs : out std_logic;
lt24_rd_n : out std_logic;
lt24_wr_n : out std_logic;
lt24_d : out std_logic_vector(15 downto 0);
lt24_lcd_on : out std_logic);
-- attribute useioff : boolean;
-- attribute useioff of lt24_reset_n : signal is true;
-- attribute useioff of lt24_cs_n : signal is true;
-- attribute useioff of lt24_rs : signal is true;
-- --attribute useioff of lt24_rd_n : signal is true;
-- attribute useioff of lt24_wr_n : signal is true;
-- attribute useioff of lt24_d : signal is true;
-- --attribute useioff of lt24_lcd_on : signal is true;
--
end entity top;
---------------------------------------------------------------------------
architecture inst of top is
signal x : std_logic_vector(7 downto 0); -- 0 .. 319 => 9 bits
signal y : std_logic_vector(8 downto 0); -- 0 .. 239 => 8 bits
signal c, c_rom, c_rom_reg, c_pat: std_logic_vector(15 downto 0); -- 16 bits colors
signal clk, resetn_pad, resetn_pad_reg1, resetn_sync : std_logic;
signal xy_to_address : std_logic_vector(17 downto 0);
-- Registers key(1) to exclude key(1) from critical path
signal selected_input : std_logic;
begin
--------------------------------------------------------------------
-- Synchronize reset (synchronous reset_sync assertion, but synchronous
-- reset_sync removal)
resetn_pad <= key(0);
clk <= clock_50;
sync_reset:process(resetn_pad, clk)
variable resetn_pad_reg0 : std_logic;
begin
if resetn_pad = '0' then
resetn_pad_reg0 := '0';
resetn_pad_reg1 <= '0';
elsif rising_edge(clk) then
resetn_pad_reg1 <= resetn_pad_reg0;
resetn_pad_reg0 := '1';
end if;
end process;
resetn_sync <= resetn_pad_reg1;
--------------------------------------------------------------------
-- registers used to split some critical paths
update_regs: process(resetn_sync, clk)
begin
if (resetn_sync = '0') then
selected_input <= '0';
c_rom_reg <= (others => '0');
xy_to_address<= (others => '0');
elsif rising_edge(clk) then
selected_input <= key(1);
c_rom_reg <= c_rom;
xy_to_address <= std_logic_vector(unsigned(x) +
unsigned(y)*to_unsigned(240,9)
-- -1 -- to compensate c_reg delay
);
end if;
end process;
--------------------------------------------------------------------
-- LT24 controller
-- Remark : LT24_RD_N and LR24_LCD_ON are always set.
lt24ctrl_0:entity work.lt24ctrl
generic map (
system_frequency => 50_000_000.0,
tmin_cycles => 1)
port map (
clk => clock_50,
resetn => resetn_sync,
x => x,
y => y,
c => c,
lt24_reset_n => lt24_reset_n,
lt24_cs_n => lt24_cs_n,
lt24_rs => lt24_rs,
lt24_rd_n => lt24_rd_n,
lt24_wr_n => lt24_wr_n,
lt24_d => lt24_d,
lt24_lcd_on => lt24_lcd_on);
--------------------------------------------------------------------
-- Select LCD screen input depending on key(1)
c <= c_rom_reg when selected_input = '1' else
c_pat;
-- Input 1 : static picture stored into a ROM
rom_img: entity work.rom_img
port map(
addr => xy_to_address(16 downto 0),
q => c_rom,
clk => clk);
-- Input 2 : pattern generator
genpix0: entity work.genpix
port map(
x => x,
y => y,
c => c_pat,
resetn => resetn_sync,
clk => clock_50);
end architecture inst;
---------------------------------------------------------------------------
|
lgpl-3.0
|
9ffcebd1d35f03bd033c650e39a3e407
| 0.508641 | 3.817091 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2s60-sdr/leon3mp.vhd
| 1 | 20,764 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
wpn : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
wpn <= '1'; byten <= '0';
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
memb_pad : outpadv generic map (width => 4, tech => padtech)
port map (mben, memo.mben);
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
24dd7652ac11cc3366a88213551a8c3e
| 0.53848 | 3.753435 | false | false | false | false |
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