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elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-cpci-xc2v6000/testbench.vhd
| 1 | 19,189 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic := 'L';
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART1 tx data
rxd2 : in std_logic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to 1);
can_rxd : in std_logic_vector(0 to 1);
can_stb : out std_logic_vector(0 to 1);
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal gtx_clk : std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal led_cfg: std_logic_vector(2 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to 1);
signal can_rxd : std_logic_vector(0 to 1);
signal can_stb : std_logic_vector(0 to 1);
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= (others => '1');
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_rxd, spw_rxdn, spw_rxs, spw_rxsn,
spw_txd, spw_txdn, spw_txs, spw_txsn);
-- optional sdram
sd0 : if (CFG_SDEN = 1) and (CFG_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN = 1) and (CFG_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 = 1) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
49cc88912db77d419985cd2406cfed43
| 0.569232 | 3.039119 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml510/testbench.vhd
| 1 | 19,647 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2008 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal clk_125_p : std_ulogic := '0';
signal clk_125_n : std_ulogic := '1';
constant slips : integer := 11;
signal rst_125 : std_ulogic;
signal sysace_fpga_clk : std_ulogic := '0';
signal flash_we_b : std_ulogic;
signal flash_wait : std_ulogic;
signal flash_reset_b : std_ulogic;
signal flash_oe_b : std_ulogic;
signal flash_d : std_logic_vector(15 downto 0);
signal flash_clk : std_ulogic;
signal flash_ce_b : std_ulogic;
signal flash_adv_b : std_logic;
signal flash_a : std_logic_vector(21 downto 0);
signal sram_bw : std_ulogic;
signal sim_d : std_logic_vector(15 downto 0);
signal iosn : std_ulogic;
signal dimm1_ddr2_we_b : std_ulogic;
signal dimm1_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm1_ddr2_ras_b : std_ulogic;
signal dimm1_ddr2_pll_clkin_p : std_ulogic;
signal dimm1_ddr2_pll_clkin_n : std_ulogic;
signal dimm1_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm1_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm1_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm1_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm1_ddr2_cas_b : std_ulogic;
signal dimm1_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm1_ddr2_a : std_logic_vector(13 downto 0);
signal dimm0_ddr2_we_b : std_ulogic;
signal dimm0_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm0_ddr2_ras_b : std_ulogic;
signal dimm0_ddr2_pll_clkin_p : std_ulogic;
signal dimm0_ddr2_pll_clkin_n : std_ulogic;
signal dimm0_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm0_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm0_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm0_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm0_ddr2_cas_b : std_ulogic;
signal dimm0_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm0_ddr2_a : std_logic_vector(13 downto 0);
signal phy0_txer : std_ulogic;
signal phy0_txd : std_logic_vector(3 downto 0);
signal phy0_txctl_txen : std_ulogic;
signal phy0_txclk : std_ulogic;
signal phy0_rxer : std_ulogic;
signal phy0_rxd : std_logic_vector(3 downto 0);
signal phy0_rxctl_rxdv : std_ulogic;
signal phy0_rxclk : std_ulogic;
signal phy0_reset : std_ulogic;
signal phy0_mdio : std_logic;
signal phy0_mdc : std_ulogic;
signal phy1_reset : std_logic;
signal phy1_mdio : std_logic;
signal phy1_mdc : std_logic;
signal phy1_sgmii_tx_p : std_logic;
signal phy1_sgmii_tx_n : std_logic;
signal phy1_sgmii_rx_p : std_logic;
signal phy1_sgmii_rx_n : std_logic;
signal phy1_sgmii_rx_p_d : std_logic;
signal phy1_sgmii_rx_n_d : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_mpd : std_logic_vector(15 downto 0);
signal dbg_led : std_logic_vector(3 downto 0);
signal opb_bus_error : std_ulogic;
signal plb_bus_error : std_ulogic;
signal dvi_xclk_p : std_ulogic;
signal dvi_xclk_n : std_ulogic;
signal dvi_v : std_ulogic;
signal dvi_reset_b : std_ulogic;
signal dvi_h : std_ulogic;
signal dvi_gpio1 : std_logic;
signal dvi_de : std_ulogic;
signal dvi_d : std_logic_vector(11 downto 0);
signal pci_p_trdy_b : std_logic;
signal pci_p_stop_b : std_logic;
signal pci_p_serr_b : std_logic;
signal pci_p_rst_b : std_logic;
signal pci_p_req_b : std_logic_vector(0 to 4);
signal pci_p_perr_b : std_logic;
signal pci_p_par : std_logic;
signal pci_p_lock_b : std_logic;
signal pci_p_irdy_b : std_logic;
signal pci_p_intd_b : std_logic;
signal pci_p_intc_b : std_logic;
signal pci_p_intb_b : std_logic;
signal pci_p_inta_b : std_logic;
signal pci_p_gnt_b : std_logic_vector(0 to 4);
signal pci_p_frame_b : std_logic;
signal pci_p_devsel_b : std_logic;
signal pci_p_clk5_r : std_ulogic;
signal pci_p_clk5 : std_ulogic;
signal pci_p_clk4_r : std_ulogic;
signal pci_p_clk3_r : std_ulogic;
signal pci_p_clk1_r : std_ulogic;
signal pci_p_clk0_r : std_ulogic;
signal pci_p_cbe_b : std_logic_vector(3 downto 0);
signal pci_p_ad : std_logic_vector(31 downto 0);
--signal pci_fpga_idsel : std_ulogic;
signal sbr_pwg_rsm_rstj : std_logic;
signal sbr_nmi_r : std_ulogic;
signal sbr_intr_r : std_ulogic;
signal sbr_ide_rst_b : std_logic;
signal iic_sda_dvi : std_logic;
signal iic_scl_dvi : std_logic;
signal fpga_sda : std_logic;
signal fpga_scl : std_logic;
signal iic_therm_b : std_ulogic;
signal iic_reset_b : std_ulogic;
signal iic_irq_b : std_ulogic;
signal iic_alert_b : std_ulogic;
signal spi_data_out : std_logic;
signal spi_data_in : std_logic;
signal spi_data_cs_b : std_ulogic;
signal spi_clk : std_ulogic;
signal uart1_txd : std_ulogic;
signal uart1_rxd : std_ulogic;
signal uart1_rts_b : std_ulogic;
signal uart1_cts_b : std_ulogic;
signal uart0_txd : std_ulogic;
signal uart0_rxd : std_ulogic;
signal uart0_rts_b : std_ulogic;
--signal uart0_cts_b : std_ulogic;
--signal test_mon_vrefp : std_ulogic;
signal test_mon_vp0_p : std_ulogic;
signal test_mon_vn0_n : std_ulogic;
--signal test_mon_avdd : std_ulogic;
signal data : std_logic_vector(31 downto 0);
signal phy0_rxdl : std_logic_vector(7 downto 0);
signal phy0_txdl : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_fpga_clk <= not sysace_fpga_clk after 15 ns;
pci_p_clk5 <= pci_p_clk5_r;
clk_125_p <= not clk_125_p after 4 ns;
clk_125_n <= not clk_125_n after 4 ns;
flash_wait <= 'L';
phy0_txdl <= "0000" & phy0_txd; phy0_rxd <= phy0_rxdl(3 downto 0);
sysace_mpd <= (others => 'H'); sysace_mpirq <= 'L';
dbg_led <= (others => 'H');
dvi_gpio1 <= 'H';
pci_p_trdy_b <= 'H'; pci_p_stop_b <= 'H';
pci_p_serr_b <= 'H'; pci_p_rst_b <= 'H';
pci_p_req_b <= (others => 'H'); pci_p_perr_b <= 'H';
pci_p_par <= 'H'; pci_p_lock_b <= 'H';
pci_p_irdy_b <= 'H'; pci_p_intd_b <= 'H';
pci_p_intc_b <= 'H'; pci_p_intb_b <= 'H';
pci_p_inta_b <= 'H'; pci_p_gnt_b <= (others => 'H');
pci_p_frame_b <= 'H'; pci_p_devsel_b <= 'H';
pci_p_cbe_b <= (others => 'H'); pci_p_ad <= (others => 'H');
-- pci_fpga_idsel <= 'H';
sbr_pwg_rsm_rstj <= 'H'; sbr_nmi_r <= 'H';
sbr_intr_r <= 'L'; sbr_ide_rst_b <= 'H';
iic_sda_dvi <= 'H'; iic_scl_dvi <= 'H';
fpga_sda <= 'H'; fpga_scl <= 'H';
iic_therm_b <= 'L'; iic_irq_b <= 'L'; iic_alert_b <= 'L';
spi_data_out <= 'H';
uart1_rxd <= 'H'; uart1_cts_b <= uart1_rts_b;
uart0_rxd <= 'H'; --uart0_cts_b <= uart0_rts_b;
test_mon_vp0_p <= 'H'; test_mon_vn0_n <= 'H';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, transtech, ncpu, disas, dbguart, pclow )
port map (sys_rst_in, sys_clk, sysace_fpga_clk,
-- Flash
flash_we_b, flash_wait, flash_reset_b, flash_oe_b,
flash_d, flash_clk, flash_ce_b, flash_adv_b, flash_a,
sram_bw, sim_d, iosn,
-- DDR2 slot 1
dimm1_ddr2_we_b, dimm1_ddr2_s_b, dimm1_ddr2_ras_b,
dimm1_ddr2_pll_clkin_p, dimm1_ddr2_pll_clkin_n,
dimm1_ddr2_odt, dimm1_ddr2_dqs_p, dimm1_ddr2_dqs_n,
dimm1_ddr2_dqm, dimm1_ddr2_dq, dimm1_ddr2_cke,
dimm1_ddr2_cas_b, dimm1_ddr2_ba, dimm1_ddr2_a,
-- DDR2 slot 0
dimm0_ddr2_we_b, dimm0_ddr2_s_b, dimm0_ddr2_ras_b,
dimm0_ddr2_pll_clkin_p, dimm0_ddr2_pll_clkin_n,
dimm0_ddr2_odt, dimm0_ddr2_dqs_p, dimm0_ddr2_dqs_n,
dimm0_ddr2_dqm, dimm0_ddr2_dq, dimm0_ddr2_cke,
dimm0_ddr2_cas_b, dimm0_ddr2_ba, dimm0_ddr2_a,
open,
-- Ethernet PHY0
phy0_txer, phy0_txd, phy0_txctl_txen, phy0_txclk,
phy0_rxer, phy0_rxd, phy0_rxctl_rxdv, phy0_rxclk,
phy0_reset, phy0_mdio, phy0_mdc,
-- Ethernet PHY1
clk_125_p, clk_125_n,
phy1_reset, phy1_mdio, phy1_mdc, open,
phy1_sgmii_tx_p, phy1_sgmii_tx_n, phy1_sgmii_rx_p, phy1_sgmii_rx_n,
-- System ACE MPU
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_mpd,
-- GPIO/Green LEDs
dbg_led,
-- Red/Green LEDs
opb_bus_error, plb_bus_error,
-- LCD
-- fpga_lcd_rw, fpga_lcd_rs, fpga_lcd_e, fpga_lcd_db,
-- DVI
dvi_xclk_p, dvi_xclk_n, dvi_v, dvi_reset_b, dvi_h,
dvi_gpio1, dvi_de, dvi_d,
-- PCI
pci_p_trdy_b, pci_p_stop_b, pci_p_serr_b, pci_p_rst_b,
pci_p_req_b, pci_p_perr_b, pci_p_par, pci_p_lock_b,
pci_p_irdy_b, pci_p_intd_b, pci_p_intc_b, pci_p_intb_b,
pci_p_inta_b, pci_p_gnt_b, pci_p_frame_b, pci_p_devsel_b,
pci_p_clk5_r, pci_p_clk5, pci_p_clk4_r, pci_p_clk3_r,
pci_p_clk1_r, pci_p_clk0_r, pci_p_cbe_b, pci_p_ad,
-- pci_fpga_idsel,
sbr_pwg_rsm_rstj, sbr_nmi_r, sbr_intr_r, sbr_ide_rst_b,
-- IIC/SMBus and sideband signals
iic_sda_dvi, iic_scl_dvi, fpga_sda, fpga_scl, iic_therm_b,
iic_reset_b, iic_irq_b, iic_alert_b,
-- SPI
spi_data_out, spi_data_in, spi_data_cs_b, spi_clk,
-- UARTs
uart1_txd, uart1_rxd, uart1_rts_b, uart1_cts_b,
uart0_txd, uart0_rxd, uart0_rts_b--, --uart0_cts_b
-- System monitor
-- test_mon_vp0_p, test_mon_vn0_n
);
-- ddr2mem0: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
-- fname => sdramfile, fdelay => 0)
-- port map (DQ => dimm0_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQS => dimm0_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQSB => dimm0_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQS => dimm0_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQSB => dimm0_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDM => dimm0_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- WEB => dimm0_ddr2_we_b, CASB => dimm0_ddr2_cas_b,
-- RASB => dimm0_ddr2_ras_b, CSB => dimm0_ddr2_s_b(0),
-- BA => dimm0_ddr2_ba(1 downto 0), ADDR => dimm0_ddr2_a(12 downto 0),
-- CKE => dimm0_ddr2_cke(0), CLK => dimm0_ddr2_pll_clkin_p,
-- CLKB => dimm0_ddr2_pll_clkin_n,
-- UDM => dimm0_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
-- end generate;
ddr2mem0 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 14, babits => 3, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => dimm0_ddr2_pll_clkin_p, ckn => dimm0_ddr2_pll_clkin_n,
cke => dimm0_ddr2_cke(0), csn => dimm0_ddr2_s_b(0),
odt => gnd, rasn => dimm0_ddr2_ras_b,
casn => dimm0_ddr2_cas_b, wen => dimm0_ddr2_we_b,
dm => dimm0_ddr2_dqm(7 downto 8-CFG_DDR2SP_DATAWIDTH/8), ba => dimm0_ddr2_ba,
a => dimm0_ddr2_a, dq => dimm0_ddr2_dq2(63 downto 64-CFG_DDR2SP_DATAWIDTH),
dqs => dimm0_ddr2_dqs_p(7 downto 8-CFG_DDR2SP_DATAWIDTH/8),
dqsn =>dimm0_ddr2_dqs_n(7 downto 8-CFG_DDR2SP_DATAWIDTH/8));
-- ddr2mem1: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
-- fname => sdramfile, fdelay => 0)
-- port map (DQ => dimm1_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQS => dimm1_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQSB => dimm1_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQS => dimm1_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQSB => dimm1_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDM => dimm1_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- WEB => dimm1_ddr2_we_b, CASB => dimm1_ddr2_cas_b,
-- RASB => dimm1_ddr2_ras_b, CSB => dimm1_ddr2_s_b(0),
-- BA => dimm1_ddr2_ba(1 downto 0), ADDR => dimm1_ddr2_a(12 downto 0),
-- CKE => dimm1_ddr2_cke(0), CLK => dimm1_ddr2_pll_clkin_p,
-- CLKB => dimm1_ddr2_pll_clkin_n,
-- UDM => dimm1_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
-- end generate;
ddr2mem1 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => dimm1_ddr2_pll_clkin_p, ckn => dimm1_ddr2_pll_clkin_n,
cke => dimm1_ddr2_cke(0), csn => dimm1_ddr2_s_b(0),
odt => gnd, rasn => dimm1_ddr2_ras_b,
casn => dimm1_ddr2_cas_b, wen => dimm1_ddr2_we_b,
dm => dimm1_ddr2_dqm(CFG_DDR2SP_DATAWIDTH/8-1 downto 0), ba => dimm1_ddr2_ba(1 downto 0),
a => dimm1_ddr2_a(12 downto 0), dq => dimm1_ddr2_dq2(CFG_DDR2SP_DATAWIDTH-1 downto 0),
dqs => dimm1_ddr2_dqs_p(CFG_DDR2SP_DATAWIDTH/8-1 downto 0),
dqsn =>dimm1_ddr2_dqs_n(CFG_DDR2SP_DATAWIDTH/8-1 downto 0));
ddr2delay0 : delay_wire
generic map(data_width => dimm0_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => dimm0_ddr2_dq, b => dimm0_ddr2_dq2);
ddr2delay1 : delay_wire
generic map(data_width => dimm1_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => dimm1_ddr2_dq, b => dimm1_ddr2_dq2);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (flash_a(romdepth-1 downto 0), flash_d(15 downto 0),
gnd, gnd, flash_ce_b, flash_we_b, flash_oe_b);
phy0_mdio <= 'H';
p0: phy
generic map (address => 7)
port map(phy0_reset, phy0_mdio, phy0_txclk, phy0_rxclk, phy0_rxdl,
phy0_rxctl_rxdv, phy0_rxer, open, open, phy0_txdl,
phy0_txctl_txen, phy0_txer, phy0_mdc, '0');
rst_125 <= not phy1_reset;
phy1_sgmii_rx_p <= transport phy1_sgmii_rx_p_d after 0.8 ns * slips;
phy1_sgmii_rx_n <= transport phy1_sgmii_rx_n_d after 0.8 ns * slips;
sp0: ser_phy
generic map(
address => 7,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
transtech => CFG_TRANSTECH
)
port map(
rstn => phy1_reset,
clk_125 => clk_125_p,
rst_125 => rst_125,
eth_rx_p => phy1_sgmii_rx_p_d,
eth_rx_n => phy1_sgmii_rx_n_d,
eth_tx_p => phy1_sgmii_tx_p,
eth_tx_n => phy1_sgmii_tx_n,
mdio => phy1_mdio,
mdc => phy1_mdc
);
i0: i2c_slave_model
port map (iic_scl_dvi, iic_sda_dvi);
i1: i2c_slave_model
port map (fpga_scl, fpga_sda);
iuerr : process
begin
wait for 5000 ns;
if to_x01(opb_bus_error) = '0' then wait on opb_bus_error; end if;
assert (to_x01(opb_bus_error) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= flash_d & sim_d;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, opb_bus_error, flash_a(20 downto 1), data,
iosn, flash_oe_b, sram_bw, open);
flash_d <= buskeep(flash_d), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
|
gpl-2.0
|
c7c3e92614094ea37468b976412668fb
| 0.575101 | 2.84863 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep1c20/config.vhd
| 1 | 5,735 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := altera;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
45fb76e3cca6200708076a40b36bfd06
| 0.645161 | 3.662197 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de4/leon3mp.vhd
| 1 | 42,379 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- LEON3 Demonstration design
-- Copyright (C) 2014 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
use gaisler.l2cache.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- clocks
OSC_50_BANK2 : in std_logic;
OSC_50_BANK3 : in std_logic;
OSC_50_BANK4 : in std_logic;
OSC_50_BANK5 : in std_logic;
OSC_50_BANK6 : in std_logic;
OSC_50_BANK7 : in std_logic;
PLL_CLKIN_p : in std_logic;
SMA_CLKIN_p : in std_logic;
-- SMA_GXBCLK_p : in std_logic;
GCLKIN : in std_logic;
-- GCLKOUT_FPGA : out std_logic;
-- SMA_CLKOUT_p : out std_logic;
-- cpu reset
CPU_RESET_n : in std_ulogic;
-- max i/o
-- MAX_CONF_D : inout std_logic_vector(3 downto 0);
-- MAX_I2C_SCLK : out std_logic;
-- MAX_I2C_SDAT : inout std_logic;
-- LEDs
LED : out std_logic_vector(7 downto 0);
-- buttons
BUTTON : in std_logic_vector(3 downto 0);
-- switches
SW : in std_logic_vector(3 downto 0);
-- slide switches
SLIDE_SW : in std_logic_vector(3 downto 0);
-- temperature
-- TEMP_SMCLK : out std_logic;
-- TEMP_SMDAT : inout std_logic;
-- TEMP_INT_n : in std_logic;
-- current
CSENSE_ADC_FO : out std_logic;
CSENSE_SCK : inout std_logic;
CSENSE_SDI : out std_logic;
CSENSE_SDO : in std_logic;
CSENSE_CS_n : out std_logic_vector(1 downto 0);
-- fan
FAN_CTRL : out std_logic;
-- eeprom
EEP_SCL : out std_logic;
EEP_SDA : inout std_logic;
-- sdcard
-- SD_CLK : out std_logic;
-- SD_CMD : inout std_logic;
-- SD_DAT : inout std_logic_vector(3 downto 0);
-- SD_WP_n : in std_logic;
-- Ethernet interfaces
ETH_INT_n : in std_logic_vector(3 downto 0);
ETH_MDC : out std_logic_vector(3 downto 0);
ETH_MDIO : inout std_logic_vector(3 downto 0);
ETH_RST_n : out std_ulogic;
ETH_RX_p : in std_logic_vector(3 downto 0);
ETH_TX_p : out std_logic_vector(3 downto 0);
-- PCIe interfaces
-- PCIE_PREST_n : in std_ulogic;
-- PCIE_REFCLK_p : in std_ulogic;
-- PCIE_RX_p : in std_logic_vector(7 downto 0);
-- PCIE_SMBCLK : in std_logic;
-- PCIE_SMBDAT : inout std_logic;
-- PCIE_TX_p : out std_logic_vector(7 downto 0);
-- PCIE_WAKE_n : out std_logic;
-- Flash and SRAM, shared signals
FSM_A : out std_logic_vector(25 downto 1);
FSM_D : inout std_logic_vector(15 downto 0);
-- Flash control
FLASH_ADV_n : out std_ulogic;
FLASH_CE_n : out std_ulogic;
FLASH_CLK : out std_ulogic;
FLASH_OE_n : out std_ulogic;
FLASH_RESET_n : out std_ulogic;
FLASH_RYBY_n : in std_ulogic;
FLASH_WE_n : out std_ulogic;
-- SSRAM control
SSRAM_ADV : out std_ulogic;
SSRAM_BWA_n : out std_ulogic;
SSRAM_BWB_n : out std_ulogic;
SSRAM_CE_n : out std_ulogic;
SSRAM_CKE_n : out std_ulogic;
SSRAM_CLK : out std_ulogic;
SSRAM_OE_n : out std_ulogic;
SSRAM_WE_n : out std_ulogic;
-- USB OTG
-- OTG_A : out std_logic_vector(17 downto 1);
-- OTG_CS_n : out std_ulogic;
-- OTG_D : inout std_logic_vector(31 downto 0);
-- OTG_DC_DACK : out std_ulogic;
-- OTG_DC_DREQ : in std_ulogic;
-- OTG_DC_IRQ : in std_ulogic;
-- OTG_HC_DACK : out std_ulogic;
-- OTG_HC_DREQ : in std_ulogic;
-- OTG_HC_IRQ : in std_ulogic;
-- OTG_OE_n : out std_ulogic;
-- OTG_RESET_n : out std_ulogic;
-- OTG_WE_n : out std_ulogic;
-- SATA
-- SATA_REFCLK_p : in std_logic;
-- SATA_HOST_RX_p : in std_logic_vector(1 downto 0);
-- SATA_HOST_TX_p : out std_logic_vector(1 downto 0);
-- SATA_DEVICE_RX_p : in std_logic_vector(1 downto 0);
-- SATA_DEVICE_TX_p : out std_logic_vector(1 downto 0);
-- DDR2 SODIMM
M1_DDR2_addr : out std_logic_vector(15 downto 0);
M1_DDR2_ba : out std_logic_vector(2 downto 0);
M1_DDR2_cas_n : out std_logic;
M1_DDR2_cke : out std_logic_vector(1 downto 0);
M1_DDR2_clk : out std_logic_vector(1 downto 0);
M1_DDR2_clk_n : out std_logic_vector(1 downto 0);
M1_DDR2_cs_n : out std_logic_vector(1 downto 0);
M1_DDR2_dm : out std_logic_vector(7 downto 0);
M1_DDR2_dq : inout std_logic_vector(63 downto 0);
M1_DDR2_dqs : inout std_logic_vector(7 downto 0);
M1_DDR2_dqsn : inout std_logic_vector(7 downto 0);
M1_DDR2_odt : out std_logic_vector(1 downto 0);
M1_DDR2_ras_n : out std_logic;
-- M1_DDR2_SA : out std_logic_vector(1 downto 0);
-- M1_DDR2_SCL : out std_logic;
-- M1_DDR2_SDA : inout std_logic;
M1_DDR2_we_n : out std_logic;
M1_DDR2_oct_rdn : in std_logic;
M1_DDR2_oct_rup : in std_logic;
-- DDR2 SODIMM
-- M2_DDR2_addr : out std_logic_vector(15 downto 0);
-- M2_DDR2_ba : out std_logic_vector(2 downto 0);
-- M2_DDR2_cas_n : out std_logic;
-- M2_DDR2_cke : out std_logic_vector(1 downto 0);
-- M2_DDR2_clk : out std_logic_vector(1 downto 0);
-- M2_DDR2_clk_n : out std_logic_vector(1 downto 0);
-- M2_DDR2_cs_n : out std_logic_vector(1 downto 0);
-- M2_DDR2_dm : out std_logic_vector(7 downto 0);
-- M2_DDR2_dq : inout std_logic_vector(63 downto 0);
-- M2_DDR2_dqs : inout std_logic_vector(7 downto 0);
-- M2_DDR2_dqsn : inout std_logic_vector(7 downto 0);
-- M2_DDR2_odt : out std_logic_vector(1 downto 0);
-- M2_DDR2_ras_n : out std_logic;
-- M2_DDR2_SA : out std_logic_vector(1 downto 0);
-- M2_DDR2_SCL : out std_logic;
-- M2_DDR2_SDA : inout std_logic;
-- M2_DDR2_we_n : out std_logic;
-- GPIO
GPIO0_D : inout std_logic_vector(35 downto 0);
-- GPIO1_D : inout std_logic_vector(35 downto 0);
-- Ext I/O
-- EXT_IO : inout std_logic;
-- HSMC A
-- HSMA_CLKIN_n1 : in std_logic;
-- HSMA_CLKIN_n2 : in std_logic;
-- HSMA_CLKIN_p1 : in std_logic;
-- HSMA_CLKIN_p2 : in std_logic;
-- HSMA_CLKIN0 : in std_logic;
HSMA_CLKOUT_n2 : out std_logic;
HSMA_CLKOUT_p2 : out std_logic;
-- HSMA_D : inout std_logic_vector(3 downto 0);
-- HSMA_GXB_RX_p : in std_logic_vector(3 downto 0);
-- HSMA_GXB_TX_p : out std_logic_vector(3 downto 0);
-- HSMA_OUT_n1 : inout std_logic;
-- HSMA_OUT_p1 : inout std_logic;
-- HSMA_OUT0 : inout std_logic;
-- HSMA_REFCLK_p : in std_logic;
-- HSMA_RX_n : inout std_logic_vector(16 downto 0);
-- HSMA_RX_p : inout std_logic_vector(16 downto 0);
-- HSMA_TX_n : inout std_logic_vector(16 downto 0);
-- HSMA_TX_p : inout std_logic_vector(16 downto 0);
-- HSMC_B
-- HSMB_CLKIN_n1 : in std_logic;
-- HSMB_CLKIN_n2 : in std_logic;
-- HSMB_CLKIN_p1 : in std_logic;
-- HSMB_CLKIN_p2 : in std_logic;
-- HSMB_CLKIN0 : in std_logic;
-- HSMB_CLKOUT_n2 : out std_logic;
-- HSMB_CLKOUT_p2 : out std_logic;
-- HSMB_D : inout std_logic_vector(3 downto 0);
-- HSMB_GXB_RX_p : in std_logic_vector(3 downto 0);
-- HSMB_GXB_TX_p : out std_logic_vector(3 downto 0);
-- HSMB_OUT_n1 : inout std_logic;
-- HSMB_OUT_p1 : inout std_logic;
-- HSMB_OUT0 : inout std_logic;
-- HSMB_REFCLK_p : in std_logic;
-- HSMB_RX_n : inout std_logic_vector(16 downto 0);
-- HSMB_RX_p : inout std_logic_vector(16 downto 0);
-- HSMB_TX_n : inout std_logic_vector(16 downto 0);
-- HSMB_TX_p : inout std_logic_vector(16 downto 0);
-- HSMC i2c
-- HSMC_SCL : out std_logic;
-- HSMC_SDA : inout std_logic;
-- Display
-- SEG0_D : out std_logic_vector(6 downto 0);
-- SEG1_D : out std_logic_vector(6 downto 0);
-- SEG0_DP : out std_ulogic;
-- SEG1_DP : out std_ulogic;
-- UART
UART_CTS : out std_ulogic;
UART_RTS : in std_ulogic;
UART_RXD : in std_ulogic;
UART_TXD : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant burstlen : integer := 16; -- burst length in 32-bit words
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal del_addr : std_logic_vector(25 downto 1);
signal del_ce, del_we: std_logic;
signal del_bwa_n, del_bwb_n: std_logic_vector(1 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal edcl_ahbmi : ahb_mst_in_type;
signal edcl_ahbmo : ahb_mst_out_vector_type(1 downto 0);
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw : std_logic;
signal cgi, cgi_125 : clkgen_in_type;
signal cgo, cgo_125 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal spii, spislvi : spi_in_type;
signal spio, spislvo : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal dsubren : std_logic;
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal nolock : ahb2ahb_ctrl_type;
signal noifctrl : ahb2ahb_ifctrl_type;
signal e0_reset, e1_reset : std_logic;
signal e0_mdio_o, e1_mdio_o : std_logic;
signal e0_mdio_oe, e1_mdio_oe : std_logic;
signal e0_mdio_i, e1_mdio_i : std_logic;
signal e0_mdc, e1_mdc : std_logic;
signal e0_mdint, e1_mdint : std_logic;
signal ref_clk, ref_rstn, ref_rst: std_logic;
signal led_crs1, led_link1, led_col1, led_an1, led_char_err1, led_disp_err1 : std_logic;
signal led_crs2, led_link2, led_col2, led_an2, led_char_err2, led_disp_err2 : std_logic;
signal led1_int, led2_int, led3_int, led4_int, led5_int, led6_int, led7_int : std_logic;
constant BOARD_FREQ : integer := 100000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 0;
constant OEPOL : integer := padoen_polarity(padtech);
constant DEBUG_BUS : integer := CFG_L2_EN;
constant EDCL_SEP_AHB : integer := CFG_L2_EN;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_clk_fb : std_ulogic;
signal clkm125 : std_logic;
signal clklock, lock, clkml : std_logic;
signal gprego : std_logic_vector(15 downto 0);
signal slide_switch: std_logic_vector(3 downto 0);
signal counter1 : std_logic_vector(26 downto 0);
signal counter2 : std_logic_vector(3 downto 0);
signal bitslip_int : std_logic;
signal tx_rstn0, tx_rstn1, rx_rstn0, rx_rstn1 : std_logic;
begin
nolock <= ahb2ahb_ctrl_none;
noifctrl <= ahb2ahb_ifctrl_none;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1');
gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 0,
noclkfb => CFG_CLK_NOFB, freq => BOARD_FREQ)
port map (clkin => PLL_CLKIN_p, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
-- clk125_pad : clkpad generic map (tech => padtech) port map (clk125, lclk125);
-- clkm125 <= clk125;
rst0 : rstgen -- reset generator
port map (CPU_RESET_n, clkm, clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, fpnpen => CFG_FPNPEN,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+
DEBUG_BUS+CFG_GRETH+CFG_GRETH2,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (LED(0), dbgo(0).error);
----------------------------------------------------------------------
--- Debug -----------------------------------------
----------------------------------------------------------------------
-- Debug DSU and debug links can be connected to the system on two
-- ways:
--
-- a) Directly to the main AHB bus
-- b) Connected via a dedicated debug AHB bus that is connected to
-- the main AHB bus via a AHB/AHB bridge.
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (BUTTON(0), dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (LED(1), dsuo.active);
dui.rxd <= uart_rxd when slide_sw(0) = '0' else '1';
nodbgbus : if DEBUG_BUS /= 1 generate
-- DSU and debug links directly connected to main bus
edcl_ahbmi <= ahbmi;
-- EDCL ahbmo interfaces are not used in this configuration
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#E00#, hmask => 16#FC0#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
end generate;
dbgbus : if DEBUG_BUS = 1 generate
-- DSU and debug links connected via AHB/AHB bridge to process
dbgsubsys : block
constant DBG_AHBIO : integer := 16#EFF#;
signal dbg_ahbsi : ahb_slv_in_type;
signal dbg_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal dbg_ahbmi : ahb_mst_in_type;
signal dbg_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
begin
edcl_ahbmi <= dbg_ahbmi;
dbg_ahbmo(CFG_AHB_UART+CFG_AHB_JTAG) <= edcl_ahbmo(0);
dbg_ahbmo(CFG_AHB_UART+CFG_AHB_JTAG+1) <= edcl_ahbmo(1);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3_mb -- LEON3 Debug Support Unit
generic map (hindex => 0, haddr => 16#E00#, hmask => 16#FC0#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, dbg_ahbsi, dbg_ahbso(0), ahbsi, dbgo, dbgi, dsui, dsuo);
end generate;
nodsu : if CFG_DSU = 0 generate
dbg_ahbso(0) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
membustrc : if true generate
ahbtrace0: ahbtrace_mb
generic map (
hindex => 2,
ioaddr => 16#000#,
iomask => 16#E00#,
tech => memtech,
irq => 0,
kbytes => 8,
ahbfilt => 2)
port map(
rst => rstn,
clk => clkm,
ahbsi => dbg_ahbsi,
ahbso => dbg_ahbso(2),
tahbmi => mem_ahbmi,
tahbsi => mem_ahbsi);
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => 0, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), dbg_ahbmi, dbg_ahbmo(0));
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, dbg_ahbmi, dbg_ahbmo(CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => 0, fpnpen => CFG_FPNPEN,
rrobin => CFG_RROBIN, ioaddr => DBG_AHBIO,
ioen => 1,
nahbm => CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRETH2,
nahbs => 3)
port map (rstn, clkm, dbg_ahbmi, dbg_ahbmo, dbg_ahbsi, dbg_ahbso);
-- Bridge connecting debug bus -> processor bus
-- Configuration:
-- Prefetching with a maximum burst length of 8 words
-- No interrupt synchronisation
-- Debug cores cannot make locked accesses => lckdac = 0
-- Slave maximum access size: 32
-- Master maximum access size: 128
-- Read and write combining
-- No special handling for instruction bursts
debug_bridge: ahb2ahb
generic map (
memtech => 0,
hsindex => 1,
hmindex => CFG_NCPU+CFG_GRETH+CFG_GRETH2,
slv => 0,
dir => 1,
ffact => 1,
pfen => 1,
wburst => burstlen,
iburst => 8,
rburst => burstlen,
irqsync => 0,
bar0 => ahb2ahb_membar(16#000#, '1', '1', 16#800#),
bar1 => ahb2ahb_membar(16#800#, '0', '0', 16#C00#),
bar2 => ahb2ahb_membar(16#C00#, '0', '0', 16#E00#),
bar3 => ahb2ahb_membar(16#F00#, '0', '0', 16#F00#),
sbus => 2,
mbus => 0,
ioarea => 16#FFF#,
ibrsten => 0,
lckdac => 0,
slvmaccsz => 32,
mstmaccsz => 32,
rdcomb => 0,
wrcomb => 0,
combmask => 0,
allbrst => 0,
ifctrlen => 0,
fcfs => 0,
fcfsmtech => 0,
scantest => 0,
split => 0,
pipe => 0)
port map (
rstn => rstn,
hclkm => clkm,
hclks => clkm,
ahbsi => dbg_ahbsi,
ahbso => dbg_ahbso(1),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_GRETH+CFG_GRETH2),
ahbso2 => ahbso,
lcki => nolock,
lcko => open,
ifctrl => noifctrl);
end block dbgsubsys;
end generate;
----------------------------------------------------------------------
--- Memory subsystem ----------------------------------------------
----------------------------------------------------------------------
data_pad : iopadvv generic map (tech => padtech, width => 16, oepol => OEPOL)
port map (FSM_D, memo.data(31 downto 16), memo.vbdrive(31 downto 16), memi.data(31 downto 16));
FSM_A <= memo.address(25 downto 1);
FLASH_CLK <= clkm;
FLASH_RESET_n <= rstn;
FLASH_CE_n <= memo.romsn(0);
FLASH_OE_n <= memo.oen;
FLASH_WE_n <= memo.writen;
FLASH_ADV_n <= '0';
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= (others => '1');
memi.bwidth <= "01";
memi.sd <= (others => '0');
memi.cb <= (others => '0');
memi.scb <= (others => '0');
memi.edac <= '0';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
romaddr => 16#000#, rommask => 16#fc0#,
ioaddr => 0, iomask => 0,
ramaddr => 0, rammask => 0,
ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open);
end generate;
nomctrl0: if CFG_MCTRL_LEON2 = 0 generate
ahbso(0) <= ahbs_none;
apbo(0) <= apb_none;
memo <= memory_out_none;
end generate;
-----------------------------------------------------------------------------
-- DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
l2cdis : if CFG_L2_EN = 0 generate
ddr2if0: entity work.ddr2if
generic map(
hindex => 3,
haddr => 16#400#,
hmask => 16#C00#,
burstlen => burstlen
)
port map (
pll_ref_clk => OSC_50_BANK4,
global_reset_n => CPU_RESET_n,
mem_a => M1_DDR2_addr(13 downto 0),
mem_ba => M1_DDR2_ba,
mem_ck => M1_DDR2_clk,
mem_ck_n => M1_DDR2_clk_n,
mem_cke => M1_DDR2_cke(0),
mem_cs_n => M1_DDR2_cs_n(0),
mem_dm => M1_DDR2_dm,
mem_ras_n => M1_DDR2_ras_n,
mem_cas_n => M1_DDR2_cas_n,
mem_we_n => M1_DDR2_we_n,
mem_dq => M1_DDR2_dq,
mem_dqs => M1_DDR2_dqs,
mem_dqs_n => M1_DDR2_dqsn,
mem_odt => M1_DDR2_odt(0),
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(3),
oct_rdn => M1_DDR2_oct_rdn,
oct_rup => M1_DDR2_oct_rup
);
end generate;
-----------------------------------------------------------------------------
-- L2 cache covering DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
memorysubsys : block
constant MEM_AHBIO : integer := 16#FFE#;
begin
l2c0 : l2c
generic map(hslvidx => 3, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => MEM_AHBIO, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(3),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso);
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => MEM_AHBIO,
ioen => IOAEN, nahbm => 1, nahbs => 1)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
ddr2if0: entity work.ddr2if
generic map(
hindex => 0,
haddr => 16#400#,
hmask => 16#C00#,
burstlen => burstlen
)
port map (
pll_ref_clk => OSC_50_BANK4,
global_reset_n => CPU_RESET_n,
mem_a => M1_DDR2_addr(13 downto 0),
mem_ba => M1_DDR2_ba,
mem_ck => M1_DDR2_clk,
mem_ck_n => M1_DDR2_clk_n,
mem_cke => M1_DDR2_cke(0),
mem_cs_n => M1_DDR2_cs_n(0),
mem_dm => M1_DDR2_dm,
mem_ras_n => M1_DDR2_ras_n,
mem_cas_n => M1_DDR2_cas_n,
mem_we_n => M1_DDR2_we_n,
mem_dq => M1_DDR2_dq,
mem_dqs => M1_DDR2_dqs,
mem_dqs_n => M1_DDR2_dqsn,
mem_odt => M1_DDR2_odt(0),
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => mem_ahbsi,
ahbso => mem_ahbso(0),
oct_rdn => M1_DDR2_oct_rdn,
oct_rup => M1_DDR2_oct_rup
);
end block memorysubsys;
end generate;
lock <= '1';
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= '1' when slide_sw(0) = '0' else uart_rxd;
u1i.ctsn <= uart_rts; u1i.extclk <= '0';
end generate;
uart_txd <= u1o.txd when slide_sw(0) = '1' else duo.txd;
uart_cts <= u1o.rtsn;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (GPIO0_D(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
unused_pio_pads : for i in (CFG_GRGPIO_WIDTH*CFG_GRGPIO_ENABLE) to 35 generate
GPIO0_D(i) <= '0';
end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (CSENSE_SDO, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (CSENSE_SDI, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (CSENSE_SCK, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (CSENSE_CS_n(0), slvsel(0));
slvseladc_pad : outpad generic map (tech => padtech)
port map (CSENSE_ADC_FO, slvsel(1));
end generate spic;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat
generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
fan_pad : outpad generic map (tech => padtech) port map (FAN_CTRL, vcc(0));
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
-- 125 MHz Gigabit ethernet clock generator from 50 MHz input
sgmii_pll0 : clkgen
generic map (
tech => CFG_CLKTECH,
clk_mul => 5,
clk_div => 2,
sdramen => 0,
freq => 50000
)
port map (
clkin => OSC_50_BANK3,
pciclkin => gnd(0),
clk => ref_clk,
clkn => open,
clk2x => open,
sdclk => open,
pciclk => open,
cgi => cgi_125,
cgo => cgo_125
);
-- 125 MHz clock reset synchronizer
rst2 : rstgen
generic map (acthigh => 0)
port map (e0_reset, ref_clk, cgo_125.clklock, ref_rstn, open);
ref_rst <= not ref_rstn;
e0 : greths_mb -- Gaisler Ethernet MAC 0
generic map (
hindex => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS),
ehindex => CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11,
paddr => 11,
pirq => 6,
fabtech => fabtech,
memtech => memtech,
mdcscaler => CPU_FREQ/1000,
enable_mdio => 1,
nsync => 2,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
burstlength => burstlen,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 0,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
edclsepahbg => EDCL_SEP_AHB,
giga => CFG_GRETH1G,
sim => 1
)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)),
ahbmi2 => edcl_ahbmi,
ahbmo2 => edcl_ahbmo(0),
apbi => apbi,
apbo => apbo(11),
-- High-speed Serial Interface
clk_125 => ref_clk,
rst_125 => ref_rst,
eth_rx_p => ETH_RX_p(0),
eth_tx_p => ETH_TX_p(0),
-- MDIO interface
reset => e0_reset,
mdio_o => e0_mdio_o,
mdio_oe => e0_mdio_oe,
mdio_i => e0_mdio_i,
mdc => e0_mdc,
mdint => e0_mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0001",
edclsepahb => '1',
edcldisable => slide_switch(1),
debug_pcs_mdio => gprego(0)
);
ethrst_pad : outpad generic map (tech => padtech)
port map (ETH_RST_n, e0_reset);
emdio0_pad : iopad generic map (tech => padtech)
port map (ETH_MDIO(0), e0_mdio_o, e0_mdio_oe, e0_mdio_i);
emdc0_pad : outpad generic map (tech => padtech)
port map (ETH_MDC(0), e0_mdc);
eint0_pad : inpad generic map (tech => padtech)
port map (ETH_INT_n(0), e0_mdint);
grgpreg0 : grgpreg
generic map (
pindex => 8,
paddr => 4,
rstval => 0
)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(8),
gprego => gprego
);
-- LEDs
led2_pad : outpad generic map (tech => padtech) port map (LED(2), vcc(0));
led3_pad : outpad generic map (tech => padtech) port map (LED(3), vcc(0));
led4_pad : outpad generic map (tech => padtech) port map (LED(4), vcc(0));
led5_pad : outpad generic map (tech => padtech) port map (LED(5), vcc(0));
led6_pad : outpad generic map (tech => padtech) port map (LED(6), vcc(0));
led7_pad : outpad generic map (tech => padtech) port map (LED(7), vcc(0));
end generate;
noeth0 : if CFG_GRETH = 0 generate
edcl_ahbmo(0) <= ahbm_none;
end generate;
eth1: if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC
e1 : greths_mb -- Gaisler Ethernet MAC 1
generic map (
hindex => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+CFG_GRETH,
ehindex => CFG_AHB_UART+CFG_AHB_JTAG+1,
pindex => 12,
paddr => 12,
pirq => 7,
fabtech => fabtech,
memtech => memtech,
mdcscaler => CPU_FREQ/1000,
enable_mdio => 1,
nsync => 2,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
burstlength => burstlen,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 1,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
edclsepahbg => EDCL_SEP_AHB,
giga => CFG_GRETH21G,
sim => 1
)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+CFG_GRETH),
ahbmi2 => edcl_ahbmi,
ahbmo2 => edcl_ahbmo(1),
apbi => apbi,
apbo => apbo(12),
-- High-speed Serial Interface
clk_125 => ref_clk,
rst_125 => ref_rst,
eth_rx_p => ETH_RX_p(1),
eth_tx_p => ETH_TX_p(1),
-- MDIO interface
reset => e1_reset,
mdio_o => e1_mdio_o,
mdio_oe => e1_mdio_oe,
mdio_i => e1_mdio_i,
mdc => e1_mdc,
mdint => e1_mdint,
-- Control signals
phyrstaddr => "00001",
edcladdr => "0010",
edclsepahb => '1',
edcldisable => slide_switch(1)
);
-- MDIO interface setup
emdio1_pad : iopad generic map (tech => padtech)
port map (ETH_MDIO(1), e1_mdio_o, e1_mdio_oe, e1_mdio_i);
emdc1_pad : outpad generic map (tech => padtech)
port map (ETH_MDC(1), e1_mdc);
eint1_pad : inpad generic map (tech => padtech)
port map (ETH_INT_n(1), e1_mdint);
end generate;
noeth2 : if CFG_GRETH2 = 0 generate
edcl_ahbmo(1) <= ahbm_none;
end generate;
edcl_pad : inpad
generic map (tech => padtech)
port map (SLIDE_SW(1), slide_switch(1));
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(5) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRETH2) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
--ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto 6) <= (others => ahbs_none);
--apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(ALTERA_DE4),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
daf3442f8aa47f09fbf4eaa906a55f14
| 0.512919 | 3.481679 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-jopdesign-ep1c12/leon3mp.vhd
| 1 | 29,594 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant BOARD_FREQ : integer := 20000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_SDCTRL_INVCLK + CFG_MCTRL_INVCLK;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*20000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, 0, 0, 0)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm);
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(8) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 8)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
-- pp : if CFG_PCI /= 0 generate
-- pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
-- pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
-- apb_en => CFG_PCI_ARBAPB)
-- port map ( clk => pciclk, rst_n => pcii.rst,
-- req_n => pci_arb_req_n, frame_n => pcii.frame,
-- gnt_n => pci_arb_gnt_n, pclk => clkm,
-- prst_n => rstn, apbi => apbi, apbo => apbo(10)
-- );
-- pgnt_pad : outpadv generic map (tech => padtech, width => 4)
-- port map (pci_arb_gnt, pci_arb_gnt_n);
-- preq_pad : inpadv generic map (tech => padtech, width => 4)
-- port map (pci_arb_req, pci_arb_req_n);
-- end generate;
--
-- pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
-- port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
-- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
-- pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
--
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, rmapbufs => CFG_SPW_RMAPBUF,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, ports => 1, dmachan => CFG_SPW_DMACHAN,
spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
757cec256aa6dbc34a50a8cbea4e63ed
| 0.553322 | 3.477147 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys3/testbench.vhd
| 1 | 8,160 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCS : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
signal FlashCS : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(7 downto 0);
signal brdyn : std_ulogic;
signal sw : std_logic_vector(7 downto 0):= (others =>'0');
signal btn : std_logic_vector(4 downto 0):= (others =>'0');
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
clk => clk,
-- PROM
address => address(25 downto 0),
data => data(31 downto 16),
MemOE => oen,
MemWR => writen,
RamCS => RamCS,
--FlashRp => FlashRP
FlashCS => FlashCS,
-- AHB Uart
RsRx => dsurx,
RsTx => dsutx,
-- PHY
PhyTxClk => etx_clk,
PhyRxClk => erx_clk,
PhyRxd => erxdt(3 downto 0),
PhyRxDv => erx_dv,
PhyRxEr => erx_er,
PhyCol => erx_col,
PhyCrs => erx_crs,
PhyTxd => etxdt(3 downto 0),
PhyTxEn => etx_en,
PhyTxEr => etx_er,
PhyMdc => emdc,
PhyMdio => emdio,
-- Output signals for LEDs
led => led,
sw => sw,
btn => btn
);
btn(0) <= rst;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => 4+i, abits => romdepth, fname => promfile)--index => i
port map (address(romdepth-1 downto 0), data(31-i*8 downto 24-i*8), FlashCS,
writen, oen);
end generate;
sram0 : sram
generic map (index => 4, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(31 downto 24), RamCS, writen, oen);
sram1 : sram
generic map (index => 5, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(23 downto 16), RamCS, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
gpl-2.0
|
789166ad828557180f0e2f15a5ceb413
| 0.563848 | 3.526361 | false | false | false | false |
rhexsel/cmips
|
cMIPS/vhdl/incomplete/memoriavideo.vhd
| 1 | 6,382 |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: memoriavideo.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 177 11/07/2012 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY memoriavideo IS
PORT
(
address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END memoriavideo;
ARCHITECTURE SYN OF memoriavideo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(11 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "DHW.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 32768,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 15,
width_a => 12,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "DHW.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
-- Retrieval info: PRIVATE: WidthData NUMERIC "12"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "DHW.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
-- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL memoriavideo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memoriavideo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memoriavideo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memoriavideo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memoriavideo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
0448f26ca44f856fe3ef1d10efb6c451
| 0.65481 | 3.565363 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/alt/adqsout.vhd
| 3 | 5,194 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf, dqs_oe_n : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and DQS ------------------------------------------------------------
-- ****** ????????? invert dqs_oe also ??????
dqs_oe_n <= not dqs_oe;
dqs_oe_reg0 : cycloneiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
-- Out buffer (DQS) -----------------------------------------------------------------
dqs_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dqs_reg,
oe => dqs_oe_reg_n,
--devoe => vcc,
o => dqs_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
gpl-2.0
|
849089ab638915f43b0160e774768dc3
| 0.38506 | 4.148562 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica02_Semisumador4Bits/top_sumadormedio.vhd
| 1 | 903 |
library ieee;
use ieee.std_logic_1164.all;
use pack_sum_medio.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eTopSumMedio is
port(
entrada1_tsm: in std_logic;
entrada2_tsm: in std_logic;
resultado_tsm: out std_logic;
acarreo_tsm: out std_logic);
attribute loc: string;
attribute loc of entrada1_tsm: signal is "p125";
attribute loc of entrada2_tsm: signal is "p124";
attribute loc of resultado_tsm: signal is "p4";
attribute loc of acarreo_tsm: signal is "p5";
end;
-- Arquitectura
architecture aTopSumMedio of eTopSumMedio is
begin
U1: eAnd port map(
entrada1_and => entrada1_tsm,
entrada2_and => entrada2_tsm,
salida_and => acarreo_tsm);
U2: eXor port map(
entrada1_xor => entrada1_tsm,
entrada2_xor => entrada2_tsm,
salida_xor => resultado_tsm);
end aTopSumMedio;
|
apache-2.0
|
552321120f2d5148a4ccc267fad21934
| 0.6866 | 3.236559 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/core/grethc.vhd
| 1 | 84,566 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethc
-- File: grethc.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of grethc is
procedure sel_op_mode(
capbil : in std_logic_vector(4 downto 0);
speed : out std_ulogic;
duplex : out std_ulogic) is
variable vspeed : std_ulogic;
variable vduplex : std_ulogic;
begin
vspeed := '0'; vduplex := '0';
vspeed := orv(capbil(4 downto 2));
vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1));
speed := vspeed;
duplex := vduplex;
end procedure;
--host constants
constant fabits : integer := log2(fifosize);
constant burstlength : integer := setburstlength(fifosize);
constant burstbits : integer := log2(burstlength);
constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808";
constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF";
-- constant maxsizetx : integer := 1514;
constant index : integer := log2(edclbufsz);
constant receiveOK : std_logic_vector(3 downto 0) := "0000";
constant frameCheckError : std_logic_vector(3 downto 0) := "0100";
constant alignmentError : std_logic_vector(3 downto 0) := "0001";
constant frameTooLong : std_logic_vector(3 downto 0) := "0010";
constant overrun : std_logic_vector(3 downto 0) := "1000";
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
--mdio constants
constant divisor : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(mdcscaler, 8);
--receiver constants
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--tranceiver constants
constant maxsizetx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8);
constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64);
constant macaddrt : std_logic_vector(47 downto 0) :=
conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24);
constant bpbits : integer := blbits(log2(edclbufsz));
constant wsz : integer := winsz(log2(edclbufsz));
constant bselbits : integer := log2(wsz);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1');
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant txfifosizev : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(txfifosize, txfabits+1);
constant rxburstlen : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(burstlength, fabits+1);
constant txburstlen : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(burstlength, txfabits+1);
type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata,
oplength, arp, iplength, ipcrc, arpop, udp, spill);
type duplexstate_type is (start, waitop, nextop, selmode, done);
--host types
type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo,
check_result, write_result, readhdr, start, wrbus1,
etdone, getlen, ahberror, fill_fifo2, wrbus2);
type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo,
discard, write_status, write_status2);
--mdio types
type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr,
ta, ta2, ta3, data, dataend);
type ctrl_reg_type is record
txen : std_ulogic;
rxen : std_ulogic;
tx_irqen : std_ulogic;
rx_irqen : std_ulogic;
full_duplex : std_ulogic;
prom : std_ulogic;
reset : std_ulogic;
speed : std_ulogic;
pstatirqen : std_ulogic;
mcasten : std_ulogic;
ramdebugen : std_ulogic;
edcldis : std_ulogic;
end record;
type status_reg_type is record
tx_int : std_ulogic;
rx_int : std_ulogic;
rx_err : std_ulogic;
tx_err : std_ulogic;
txahberr : std_ulogic;
rxahberr : std_ulogic;
toosmall : std_ulogic;
invaddr : std_ulogic;
phystat : std_ulogic;
end record;
type mdio_ctrl_reg_type is record
phyadr : std_logic_vector(4 downto 0);
regadr : std_logic_vector(4 downto 0);
write : std_ulogic;
read : std_ulogic;
data : std_logic_vector(15 downto 0);
busy : std_ulogic;
linkfail : std_ulogic;
end record;
subtype mac_addr_reg_type is std_logic_vector(47 downto 0);
type fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(fabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(fabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(txfabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(txfabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type edcl_ram_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(eabits-1 downto 0);
writem : std_ulogic;
writel : std_ulogic;
waddressm : std_logic_vector(eabits-1 downto 0);
waddressl : std_logic_vector(eabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type edcl_ram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type reg_type is record
--user registers
ctrl : ctrl_reg_type;
status : status_reg_type;
mdio_ctrl : mdio_ctrl_reg_type;
mac_addr : mac_addr_reg_type;
hash : std_logic_vector(63 downto 0);
txdesc : std_logic_vector(31 downto 10);
rxdesc : std_logic_vector(31 downto 10);
edclip : std_logic_vector(31 downto 0);
--master tx interface
txdsel : std_logic_vector(9 downto 3);
tmsto : eth_tx_ahb_in_type;
tmsto2 : eth_tx_ahb_in_type;
txdstate : txd_state_type;
txwrap : std_ulogic;
txden : std_ulogic;
txirq : std_ulogic;
txaddr : std_logic_vector(31 downto 2);
txlength : std_logic_vector(10 downto 0);
txburstcnt : std_logic_vector(burstbits downto 0);
tfwpnt : std_logic_vector(txfabits-1 downto 0);
tfrpnt : std_logic_vector(txfabits-1 downto 0);
tfcnt : std_logic_vector(txfabits downto 0);
txcnt : std_logic_vector(10 downto 0);
txstart : std_ulogic;
txirqgen : std_ulogic;
txstatus : std_logic_vector(1 downto 0);
txvalid : std_ulogic;
txdata : std_logic_vector(31 downto 0);
writeok : std_ulogic;
txread : std_logic_vector(nsync-1 downto 0);
txrestart : std_logic_vector(nsync downto 0);
txdone : std_logic_vector(nsync downto 0);
txstart_sync : std_ulogic;
txreadack : std_ulogic;
txdataav : std_ulogic;
txburstav : std_ulogic;
--master rx interface
rxrenable : std_ulogic;
rxdsel : std_logic_vector(9 downto 3);
rmsto : eth_rx_ahb_in_type;
rxdstate : rxd_state_type;
rxstatus : std_logic_vector(4 downto 0);
rxaddr : std_logic_vector(31 downto 2);
rxlength : std_logic_vector(10 downto 0);
rxbytecount : std_logic_vector(10 downto 0);
rxwrap : std_ulogic;
rxirq : std_ulogic;
rfwpnt : std_logic_vector(fabits-1 downto 0);
rfrpnt : std_logic_vector(fabits-1 downto 0);
rfcnt : std_logic_vector(fabits downto 0);
rxcnt : std_logic_vector(10 downto 0);
rxdoneold : std_ulogic;
rxdoneack : std_ulogic;
rxdone : std_logic_vector(nsync-1 downto 0);
rxstart : std_logic_vector(nsync downto 0);
rxwrite : std_logic_vector(nsync-1 downto 0);
rxwriteack : std_ulogic;
rxburstcnt : std_logic_vector(burstbits downto 0);
addrok : std_ulogic;
addrdone : std_ulogic;
ctrlpkt : std_ulogic;
check : std_ulogic;
checkdata : std_logic_vector(31 downto 0);
usesizefield : std_ulogic;
rxden : std_ulogic;
gotframe : std_ulogic;
bcast : std_ulogic;
msbgood : std_ulogic;
rxburstav : std_ulogic;
hashlookup : std_ulogic;
mcast : std_ulogic;
mcastacc : std_ulogic;
--mdio
mdccnt : std_logic_vector(7 downto 0);
mdioclk : std_ulogic;
mdioclkold : std_logic_vector(mdiohold-1 downto 0);
mdio_state : mdio_state_type;
mdioo : std_ulogic;
mdioi : std_ulogic;
mdioen : std_ulogic;
cnt : std_logic_vector(4 downto 0);
duplexstate : duplexstate_type;
disableduplex : std_ulogic;
init_busy : std_ulogic;
ext : std_ulogic;
extcap : std_ulogic;
regaddr : std_logic_vector(4 downto 0);
phywr : std_ulogic;
rstphy : std_ulogic;
capbil : std_logic_vector(4 downto 0);
rstaneg : std_ulogic;
mdint_sync : std_logic_vector(2 downto 0);
--edcl
erenable : std_ulogic;
edclrstate : edclrstate_type;
edclactive : std_ulogic;
nak : std_ulogic;
ewr : std_ulogic;
write : std_logic_vector(wsz-1 downto 0);
seq : std_logic_vector(13 downto 0);
abufs : std_logic_vector(bselbits downto 0);
tpnt : std_logic_vector(bselbits-1 downto 0);
rpnt : std_logic_vector(bselbits-1 downto 0);
tcnt : std_logic_vector(bpbits-1 downto 0);
rcntm : std_logic_vector(bpbits-1 downto 0);
rcntl : std_logic_vector(bpbits-1 downto 0);
ipcrc : std_logic_vector(17 downto 0);
applength : std_logic_vector(15 downto 0);
oplen : std_logic_vector(9 downto 0);
udpsrc : std_logic_vector(15 downto 0);
ecnt : std_logic_vector(3 downto 0);
tarp : std_ulogic;
tnak : std_ulogic;
tedcl : std_ulogic;
edclbcast : std_ulogic;
etxidle : std_ulogic;
erxidle : std_ulogic;
emacaddr : std_logic_vector(47 downto 0);
edclsepahb : std_ulogic;
end record;
--host signals
signal arst : std_ulogic;
signal irst : std_ulogic;
signal vcc : std_ulogic;
signal tmsto : eth_tx_ahb_in_type;
signal tmsti : eth_tx_ahb_out_type;
signal tmsto2 : eth_tx_ahb_in_type;
signal tmsti2 : eth_tx_ahb_out_type;
signal rmsto : eth_rx_ahb_in_type;
signal rmsti : eth_rx_ahb_out_type;
signal ahbmi : ahbc_mst_in_type;
signal ahbmo : ahbc_mst_out_type;
signal ahbmi2 : ahbc_mst_in_type;
signal ahbmo2 : ahbc_mst_out_type;
signal txi : host_tx_type;
signal txo : tx_host_type;
signal rxi : host_rx_type;
signal rxo : rx_host_type;
signal r, rin : reg_type;
attribute sync_set_reset of irst : signal is "true";
attribute async_set_reset of arst : signal is "true";
begin
--reset generators for transmitter and receiver
vcc <= '1';
arst <= testrst when (scanen = 1) and (testen = '1')
else rst and not r.ctrl.reset;
irst <= rst and not r.ctrl.reset;
comb : process(rst, irst, r, rmsti, tmsti, txo, rxo, psel, paddr, penable,
erdata, pwrite, pwdata, rxrdata, txrdata, mdio_i, phyrstaddr,
testen, testrst, edcladdr, mdint, tmsti2, edcldisable,
edclsepahb) is
variable v : reg_type;
variable vpirq : std_ulogic;
variable vprdata : std_logic_vector(31 downto 0);
variable txvalid : std_ulogic;
variable vtxfi : tx_fifo_access_in_type;
variable vrxfi : fifo_access_in_type;
variable lengthav : std_ulogic;
variable txdone : std_ulogic;
variable txread : std_ulogic;
variable txrestart : std_ulogic;
variable rxstart : std_ulogic;
variable rxdone : std_ulogic;
variable vrxwrite : std_ulogic;
variable ovrunstop : std_ulogic;
variable edcldbgread : std_ulogic;
--mdio
variable mdioindex : integer range 0 to 31;
variable mclk : std_ulogic; --rising mdio clk edge
variable nmclk : std_ulogic; --falling mdio clk edge
variable mclkvec : std_logic_vector(mdiohold downto 0);
--edcl
variable veri : edcl_ram_in_type;
variable swap : std_ulogic;
variable setmz : std_ulogic;
variable ipcrctmp : std_logic_vector(15 downto 0);
variable ipcrctmp2 : std_logic_vector(17 downto 0);
variable vrxenable : std_ulogic;
variable crctmp : std_ulogic;
variable vecnt : integer;
begin
v := r; vprdata := (others => '0'); vpirq := '0';
v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield;
ovrunstop := '0'; vrxfi.raddress := v.rfrpnt;
if edcl /= 0 then
veri.renable := r.erenable;
veri.datain := rxo.dataout;
veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
end if;
vtxfi.renable := '0';
vtxfi.datain := tmsti.data;
vtxfi.raddress := r.tfrpnt; vtxfi.write := '0';
vtxfi.waddress := r.tfwpnt;
vrxfi.datain := rxo.dataout;
vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt;
vrxfi.renable := r.rxrenable; vrxenable := r.ctrl.rxen;
--synchronization
v.txdone(0) := txo.done;
v.txread(0) := txo.read;
v.txrestart(0) := txo.restart;
v.rxstart(0) := rxo.start;
v.rxdone(0) := rxo.done;
v.rxwrite(0) := rxo.write;
if nsync = 2 then
v.txdone(1) := r.txdone(0);
v.txread(1) := r.txread(0);
v.txrestart(1) := r.txrestart(0);
v.rxstart(1) := r.rxstart(0);
v.rxdone(1) := r.rxdone(0);
v.rxwrite(1) := r.rxwrite(0);
end if;
if enable_mdint = 1 then
v.mdint_sync(0) := mdint;
v.mdint_sync(1) := r.mdint_sync(0);
v.mdint_sync(2) := r.mdint_sync(1);
end if;
txdone := r.txdone(nsync) xor r.txdone(nsync-1);
txread := r.txreadack xor r.txread(nsync-1);
txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1);
rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1);
rxdone := r.rxdoneack xor r.rxdone(nsync-1);
vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1);
if txdone = '1' then
v.txstatus := txo.status;
end if;
-------------------------------------------------------------------------------
-- HOST INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--SLAVE INTERFACE
if ramdebug = 2 then
edcldbgread := '0';
end if;
--write
if (psel and penable and pwrite) = '1' then
if (ramdebug = 0) or (paddr(17 downto 16) = "00") then
case paddr(5 downto 2) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
v.ctrl.ramdebugen := pwdata(13);
end if;
if edcl /= 0 then
v.ctrl.edcldis := pwdata(14);
v.disableduplex := pwdata(12);
end if;
if multicast = 1 then
v.ctrl.mcasten := pwdata(11);
end if;
if enable_mdint = 1 then
v.ctrl.pstatirqen := pwdata(10);
end if;
if rmii = 1 then
v.ctrl.speed := pwdata(7);
end if;
v.ctrl.reset := pwdata(6);
v.ctrl.prom := pwdata(5);
v.ctrl.full_duplex := pwdata(4);
v.ctrl.rx_irqen := pwdata(3);
v.ctrl.tx_irqen := pwdata(2);
v.ctrl.rxen := pwdata(1);
v.ctrl.txen := pwdata(0);
when "0001" => --status/int source reg
if enable_mdint = 1 then
if pwdata(8) = '1' then v.status.phystat := '0'; end if;
end if;
if pwdata(7) = '1' then v.status.invaddr := '0'; end if;
if pwdata(6) = '1' then v.status.toosmall := '0'; end if;
if pwdata(5) = '1' then v.status.txahberr := '0'; end if;
if pwdata(4) = '1' then v.status.rxahberr := '0'; end if;
if pwdata(3) = '1' then v.status.tx_int := '0'; end if;
if pwdata(2) = '1' then v.status.rx_int := '0'; end if;
if pwdata(1) = '1' then v.status.tx_err := '0'; end if;
if pwdata(0) = '1' then v.status.rx_err := '0'; end if;
when "0010" => --mac addr msb
v.mac_addr(47 downto 32) := pwdata(15 downto 0);
when "0011" => --mac addr lsb
v.mac_addr(31 downto 0) := pwdata(31 downto 0);
when "0100" => --mdio ctrl/status
if enable_mdio = 1 then
if r.mdio_ctrl.busy = '0' then
v.mdio_ctrl.data := pwdata(31 downto 16);
v.mdio_ctrl.phyadr := pwdata(15 downto 11);
v.mdio_ctrl.regadr := pwdata(10 downto 6);
v.mdio_ctrl.read := pwdata(1);
v.mdio_ctrl.write := pwdata(0);
v.mdio_ctrl.busy := pwdata(1) or pwdata(0);
end if;
end if;
when "0101" => --tx descriptor
v.txdesc := pwdata(31 downto 10);
v.txdsel := pwdata(9 downto 3);
when "0110" => --rx descriptor
v.rxdesc := pwdata(31 downto 10);
v.rxdsel := pwdata(9 downto 3);
when "0111" => --edcl ip
if (edcl /= 0) then
v.edclip := pwdata;
end if;
when "1000" => --hash msb
if multicast = 1 then
v.hash(63 downto 32) := pwdata;
end if;
when "1001" => --hash lsb
if multicast = 1 then
v.hash(31 downto 0) := pwdata;
end if;
when "1010" =>
if edcl /= 0 then
v.emacaddr(47 downto 32) := pwdata(15 downto 0);
end if;
when "1011" =>
if edcl /= 0 then
v.emacaddr(31 downto 0) := pwdata;
end if;
when others => null;
end case;
elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "01")) then
if r.ctrl.ramdebugen = '1' then
vtxfi.write := '1';
vtxfi.waddress := paddr(txfabits+1 downto 2);
vtxfi.datain := pwdata;
end if;
elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "10")) then
if r.ctrl.ramdebugen = '1' then
vrxfi.write := '1';
vrxfi.waddress := paddr(fabits+1 downto 2);
vrxfi.datain := pwdata;
end if;
elsif ((ramdebug = 2) and (edcl /= 0) and (paddr(17 downto 16) = "11")) then
if r.ctrl.ramdebugen = '1' then
veri.datain := pwdata;
veri.waddressm := paddr(eabits+1 downto 2);
veri.waddressl := paddr(eabits+1 downto 2);
veri.writem := '1';
veri.writel := '1';
end if;
end if;
end if;
--read
if (ramdebug = 0) or (paddr(17 downto 16) = "00") then
case paddr(5 downto 2) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
vprdata(13) := r.ctrl.ramdebugen;
end if;
if (edcl /= 0) then
vprdata(31) := '1';
vprdata(30 downto 28) := bufsize;
vprdata(14) := r.ctrl.edcldis;
vprdata(12) := r.disableduplex;
end if;
if enable_mdint = 1 then
vprdata(26) := '1';
vprdata(10) := r.ctrl.pstatirqen;
end if;
if multicast = 1 then
vprdata(25) := '1';
vprdata(11) := r.ctrl.mcasten;
end if;
if rmii = 1 then
vprdata(7) := r.ctrl.speed;
end if;
vprdata(6) := r.ctrl.reset;
vprdata(5) := r.ctrl.prom;
vprdata(4) := r.ctrl.full_duplex;
vprdata(3) := r.ctrl.rx_irqen;
vprdata(2) := r.ctrl.tx_irqen;
vprdata(1) := r.ctrl.rxen;
vprdata(0) := r.ctrl.txen;
when "0001" => --status/int source reg
vprdata(9) := not (r.etxidle or r.erxidle);
if enable_mdint = 1 then
vprdata(8) := r.status.phystat;
end if;
vprdata(7) := r.status.invaddr;
vprdata(6) := r.status.toosmall;
vprdata(5) := r.status.txahberr;
vprdata(4) := r.status.rxahberr;
vprdata(3) := r.status.tx_int;
vprdata(2) := r.status.rx_int;
vprdata(1) := r.status.tx_err;
vprdata(0) := r.status.rx_err;
when "0010" => --mac addr msb/mdio address
vprdata(15 downto 0) := r.mac_addr(47 downto 32);
when "0011" => --mac addr lsb
vprdata := r.mac_addr(31 downto 0);
when "0100" => --mdio ctrl/status
vprdata(31 downto 16) := r.mdio_ctrl.data;
vprdata(15 downto 11) := r.mdio_ctrl.phyadr;
vprdata(10 downto 6) := r.mdio_ctrl.regadr;
vprdata(3) := r.mdio_ctrl.busy;
vprdata(2) := r.mdio_ctrl.linkfail;
vprdata(1) := r.mdio_ctrl.read;
vprdata(0) := r.mdio_ctrl.write;
when "0101" => --tx descriptor
vprdata(31 downto 10) := r.txdesc;
vprdata(9 downto 3) := r.txdsel;
when "0110" => --rx descriptor
vprdata(31 downto 10) := r.rxdesc;
vprdata(9 downto 3) := r.rxdsel;
when "0111" => --edcl ip
if (edcl /= 0) then
vprdata := r.edclip;
end if;
when "1000" =>
if multicast = 1 then
vprdata := r.hash(63 downto 32);
end if;
when "1001" =>
if multicast = 1 then
vprdata := r.hash(31 downto 0);
end if;
when "1010" =>
if edcl /= 0 then
vprdata(15 downto 0) := r.emacaddr(47 downto 32);
end if;
when "1011" =>
if edcl /= 0 then
vprdata := r.emacaddr(31 downto 0);
end if;
when others => null;
end case;
elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "01")) then
if r.ctrl.ramdebugen = '1' then
vtxfi.renable := '1';
vtxfi.raddress := paddr(txfabits+1 downto 2);
vprdata := txrdata;
end if;
elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "10")) then
if r.ctrl.ramdebugen = '1' then
vrxfi.renable := '1';
vrxfi.raddress := paddr(fabits+1 downto 2);
vprdata := rxrdata;
end if;
elsif ((ramdebug = 2) and (edcl /= 0) and (paddr(17 downto 16) = "11")) then
if r.ctrl.ramdebugen = '1' then
edcldbgread := '1';
veri.renable := '1';
veri.raddress := paddr(eabits+1 downto 2);
vprdata := erdata;
end if;
end if;
--PHY STATUS DETECTION
if enable_mdint = 1 then
if mdint_pol = 0 then
if (r.mdint_sync(2) and not r.mdint_sync(1)) = '1' then
v.status.phystat := '1';
if r.ctrl.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
else
if (r.mdint_sync(1) and not r.mdint_sync(2)) = '1' then
v.status.phystat := '1';
if r.ctrl.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
end if;
end if;
--MASTER INTERFACE
v.txburstav := '0';
if (txfifosizev - r.tfcnt) >= txburstlen then
v.txburstav := '1';
end if;
if (conv_integer(r.abufs) /= 0) then
v.etxidle := '0';
else
v.etxidle := '1';
end if;
--tx dma fsm
case r.txdstate is
when idle =>
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
if (edcl /= 0) then
v.tedcl := '0'; v.erenable := '0';
end if;
if (edcl /= 0) and (conv_integer(r.abufs) /= 0) and
(r.ctrl.edcldis = '0') then
v.erenable := '1'; v.etxidle := '0';
if r.erenable = '1' then
v.txdstate := getlen;
end if;
v.tcnt := conv_std_logic_vector(10, bpbits);
elsif r.ctrl.txen = '1' then
v.txdstate := read_desc; v.tmsto.write := '0';
v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.req := '1';
end if;
if r.txirqgen = '1' then
vpirq := '1'; v.txirqgen := '0';
end if;
if txrestart = '1' then
v.txrestart(nsync) := r.txrestart(nsync-1);
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
end if;
when read_desc =>
v.tmsto.write := '0'; v.txstatus := (others => '0');
v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfcnt := (others => '0');
if tmsti.grant = '1' then
v.txburstcnt := r.txburstcnt + 1; v.tmsto.addr := r.tmsto.addr + 4;
if r.txburstcnt(0) = '1' then
v.tmsto.req := '0';
end if;
end if;
if tmsti.ready = '1' then
v.txcnt := r.txcnt + 1;
case r.txcnt(1 downto 0) is
when "00" =>
v.txlength := tmsti.data(10 downto 0);
v.txden := tmsti.data(11);
v.txwrap := tmsti.data(12);
v.txirq := tmsti.data(13);
v.ctrl.txen := tmsti.data(11);
when "01" =>
v.txaddr := tmsti.data(31 downto 2);
v.txdstate := check_desc;
when others => null;
end case;
end if;
when check_desc =>
v.txstart := '0';
v.txburstcnt := (others => '0');
if r.txden = '1' then
if (unsigned(r.txlength) > unsigned(maxsizetx)) or
(conv_integer(r.txlength) = 0) then
v.txdstate := write_result; v.tmsto.req := '1';
v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000";
v.tmsto.data := (others => '0');
else
v.txdstate := req;
v.tmsto.addr := r.txaddr & "00"; v.txcnt(10 downto 0) := r.txlength;
end if;
else
v.txdstate := idle;
end if;
when req =>
if txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := idle;
end if;
elsif txdone = '1' then
v.txdstate := check_result;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone;
end if;
elsif conv_integer(r.txcnt) = 0 then
v.txdstate := check_result;
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone; v.txstart_sync := not r.txstart_sync;
end if;
elsif (r.txburstav = '1') or (r.tedcl = '1') then
if (edclsepahbg = 0) or (edcl = 0) or
(r.edclsepahb = '0') or (r.tedcl = '0') then
v.tmsto.req := '1'; v.txdstate := fill_fifo;
else
v.tmsto2.req := '1'; v.txdstate := fill_fifo2;
end if;
end if;
v.txburstcnt := (others => '0');
when fill_fifo =>
v.txburstav := '0';
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then
v.tmsto.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
when fill_fifo2 =>
if edclsepahbg = 1 then
v.txburstav := '0';
vtxfi.datain := tmsti2.data;
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) then
v.tmsto2.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti2.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto2.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
end if;
when check_result =>
if txdone = '1' then
v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0';
v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000";
v.tmsto.data(31 downto 16) := (others => '0');
v.tmsto.data(15 downto 14) := v.txstatus;
v.tmsto.data(13 downto 0) := (others => '0');
v.txdone(nsync) := r.txdone(nsync-1);
elsif txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
end if;
when write_result =>
if tmsti.grant = '1' then
v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txdstate := idle;
v.txirqgen := r.ctrl.tx_irqen and r.txirq;
if r.txwrap = '0' then v.txdsel := r.txdsel + 1;
else v.txdsel := (others => '0'); end if;
if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1';
else v.status.tx_err := '1'; end if;
end if;
when ahberror =>
v.tfcnt := (others => '0'); v.tfwpnt := (others => '0');
v.tfrpnt := (others => '0');
v.status.txahberr := '1'; v.ctrl.txen := '0';
if not ((edcl /= 0) and (r.tedcl = '1')) then
if r.txstart = '1' then
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
end if;
else
v.txdstate := idle;
end if;
else
v.txdstate := idle;
v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1;
end if;
when others =>
null;
end case;
--tx fifo read
v.txdataav := '0';
if conv_integer(r.tfcnt) /= 0 then
v.txdataav := '1';
end if;
if txread = '1' then
v.txreadack := not r.txreadack;
if r.txdataav = '1' then
if conv_integer(r.tfcnt) < 2 then
v.txdataav := '0';
end if;
v.txvalid := '1';
v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1;
else
v.txvalid := '0';
end if;
v.txdata := txrdata;
end if;
v.rxburstav := '0';
if r.rfcnt >= rxburstlen then
v.rxburstav := '1';
end if;
if ramdebug = 0 then
vtxfi.renable := v.txdataav;
else
vtxfi.renable := vtxfi.renable or v.txdataav;
end if;
--rx dma fsm
case r.rxdstate is
when idle =>
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
if r.ctrl.rxen = '1' then
v.rxdstate := read_desc; v.rmsto.req := '1';
v.rmsto.addr := r.rxdesc & r.rxdsel & "000";
elsif rxstart = '1' then
v.rxstart(nsync) := r.rxstart(nsync-1);
v.rxdstate := discard;
end if;
when read_desc =>
v.rxstatus := (others => '0');
if rmsti.grant = '1' then
v.rxburstcnt := r.rxburstcnt + 1; v.rmsto.addr := r.rmsto.addr + 4;
if r.rxburstcnt(0) = '1' then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rxcnt := r.rxcnt + 1;
case r.rxcnt(1 downto 0) is
when "00" =>
v.ctrl.rxen := rmsti.data(11);
v.rxden := rmsti.data(11);
v.rxwrap := rmsti.data(12);
v.rxirq := rmsti.data(13);
when "01" =>
v.rxaddr := rmsti.data(31 downto 2);
v.rxdstate := check_desc;
v.rxrenable := '1';
when others =>
null;
end case;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when check_desc =>
v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1';
if r.rxden = '1' then
if rxstart = '1' then
v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1);
end if;
else
v.rxdstate := idle;
end if;
v.rmsto.addr := r.rxaddr & "00";
when read_req =>
if r.edclactive = '1' then
v.rxdstate := discard;
elsif (r.rxdoneold and r.rxstatus(3)) = '1' then
v.rxdstate := write_status;
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
elsif ((r.addrdone and not r.addrok) or r.ctrlpkt) = '1' then
v.rxdstate := discard; v.status.invaddr := '1';
elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then
if r.gotframe = '1' then
v.rxdstate := write_status;
else
v.rxdstate := discard; v.status.toosmall := '1';
end if;
elsif (r.rxburstav or r.rxdoneold) = '1' then
v.rmsto.req := '1'; v.rxdstate := read_fifo;
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
end if;
v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata;
when read_fifo =>
v.rxburstav := '0';
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
if (lengthav = '1') then
if ((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or
((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then
v.rmsto.req := '0';
end if;
end if;
v.rxburstcnt := r.rxburstcnt + 1;
if (conv_integer(r.rxburstcnt) = burstlength-1) then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rmsto.data := rxrdata;
v.rxcnt := r.rxcnt + 4;
if r.rmsto.req = '0' then
v.rxdstate := read_req;
else
v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1;
end if;
v.check := '1'; v.checkdata := r.rmsto.data;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := discard;
v.rxcnt := r.rxcnt + 4;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when write_status =>
v.rmsto.req := '1'; v.rmsto.addr := r.rxdesc & r.rxdsel & "000";
v.rxdstate := write_status2;
if multicast = 1 then
v.rmsto.data := "00000" & r.mcastacc & "0000000" &
r.rxstatus & "000" & r.rxlength;
else
v.rmsto.data := "0000000000000" &
r.rxstatus & "000" & r.rxlength;
end if;
when write_status2 =>
if rmsti.grant = '1' then
v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then
v.rxdstate := discard;
else
v.rxdstate := idle;
end if;
if (r.ctrl.rx_irqen and r.rxirq) = '1' then
vpirq := '1';
end if;
if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1';
else v.status.rx_err := '1'; end if;
if r.rxwrap = '1' then
v.rxdsel := (others => '0');
else
v.rxdsel := r.rxdsel + 1;
end if;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when discard =>
if (r.rxdoneold = '0') then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
if r.rxstatus(3) = '1' then
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.rxdstate := idle;
elsif (conv_integer(r.rxcnt) < conv_integer(r.rxbytecount)) then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
v.rxdstate := idle; v.ctrlpkt := '0';
end if;
end if;
when others =>
null;
end case;
--rx address/type check
if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then
case r.rxcnt(4 downto 2) is
when "001" =>
if r.ctrl.prom = '1' then
v.addrok := '1';
end if;
v.mcast := r.checkdata(24);
if r.checkdata = broadcast(47 downto 16) then
v.bcast := '1';
end if;
if r.checkdata = r.mac_addr(47 downto 16) then
v.msbgood := '1';
end if;
when "010" =>
if r.checkdata(31 downto 16) = broadcast(15 downto 0) then
if r.bcast = '1' then
v.addrok := '1';
end if;
else
v.bcast := '0';
end if;
if r.checkdata(31 downto 16) = r.mac_addr(15 downto 0) then
if r.msbgood = '1' then
v.addrok := '1';
end if;
end if;
if multicast = 1 then
v.hashlookup := r.hash(conv_integer(rxo.mcasthash));
end if;
when "011" =>
if multicast = 1 then
if (r.hashlookup and r.ctrl.mcasten and r.mcast) = '1' then
v.addrok := '1';
if r.bcast = '0' then
v.mcastacc := '1';
end if;
end if;
end if;
when "100" =>
if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if;
v.addrdone := '1';
when others =>
null;
end case;
end if;
--rx packet done
if (rxdone and not rxstart) = '1' then
v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count;
v.rxstatus(3 downto 0) := rxo.status;
if (unsigned(rxo.lentype) > maxsizerx) or (rxo.status /= "0000") then
v.rxlength := rxo.byte_count;
else
v.rxlength := rxo.lentype(10 downto 0);
if (rxo.lentype(10 downto 0) > minpload) and
(rxo.lentype(10 downto 0) /= rxo.byte_count) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
elsif (rxo.lentype(10 downto 0) <= minpload) and
(rxo.byte_count /= minpload) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
end if;
end if;
v.rxdoneold := '1';
v.rxdoneack := not r.rxdoneack;
end if;
--rx fifo write
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
if (not r.rfcnt(fabits)) = '1' then
v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1';
vrxfi.write := '1';
else
v.writeok := '0';
end if;
end if;
--must be placed here because it uses variable
if (ramdebug = 0) or (r.ctrl.ramdebugen = '0') then
vrxfi.raddress := v.rfrpnt;
end if;
-------------------------------------------------------------------------------
-- MDIO INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--mdio commands
if enable_mdio = 1 then
mclkvec := r.mdioclkold & r.mdioclk;
mclk := mclkvec(mdiohold-1) and not mclkvec(mdiohold);
nmclk := mclkvec(1) and not mclkvec(0);
v.mdioclkold := mclkvec(mdiohold-1 downto 0);
if r.mdccnt = "00000000" then
v.mdccnt := divisor;
v.mdioclk := not r.mdioclk;
else
v.mdccnt := r.mdccnt - 1;
end if;
mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i;
case r.mdio_state is
when idle =>
if (enable_mdio = 1) and (edcl = 0) and (r.ctrl.reset = '1') then
v.mdio_state := idle; v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.mdio_ctrl.busy := '0';
v.mdio_ctrl.data := (others => '0');
v.mdio_ctrl.regadr := (others => '0');
v.ctrl.reset := '0';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
if mclk = '1' then
v.cnt := (others => '0');
if r.mdio_ctrl.busy = '1' then
v.mdio_ctrl.linkfail := '0';
if r.mdio_ctrl.read = '1' then
v.mdio_ctrl.write := '0';
end if;
v.mdio_state := preamble; v.mdioo := '1';
if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if;
end if;
end if;
when preamble =>
if mclk = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "11111" then
v.mdioo := '0'; v.mdio_state := startst;
end if;
end if;
when startst =>
if mclk = '1' then
v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0');
end if;
when op =>
if mclk = '1' then
v.mdio_state := op2;
if r.mdio_ctrl.read = '1' then v.mdioo := '1';
else v.mdioo := '0'; end if;
end if;
when op2 =>
if mclk = '1' then
v.mdioo := not r.mdioo; v.mdio_state := phyadr;
v.cnt := (others => '0');
end if;
when phyadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.mdio_ctrl.phyadr(4);
when 1 => v.mdioo := r.mdio_ctrl.phyadr(3);
when 2 => v.mdioo := r.mdio_ctrl.phyadr(2);
when 3 => v.mdioo := r.mdio_ctrl.phyadr(1);
when 4 => v.mdioo := r.mdio_ctrl.phyadr(0);
v.mdio_state := regadr; v.cnt := (others => '0');
when others => null;
end case;
end if;
when regadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.mdio_ctrl.regadr(4);
when 1 => v.mdioo := r.mdio_ctrl.regadr(3);
when 2 => v.mdioo := r.mdio_ctrl.regadr(2);
when 3 => v.mdioo := r.mdio_ctrl.regadr(1);
when 4 => v.mdioo := r.mdio_ctrl.regadr(0);
v.mdio_state := ta; v.cnt := (others => '0');
when others => null;
end case;
end if;
when ta =>
if mclk = '1' then
v.mdio_state := ta2;
if r.mdio_ctrl.read = '1' then
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
else v.mdioo := '1'; end if;
end if;
when ta2 =>
if mclk = '1' then
v.cnt := "01111"; v.mdio_state := ta3;
if r.mdio_ctrl.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if;
end if;
when ta3 =>
if mclk = '1' then
v.mdio_state := data;
end if;
if nmclk = '1' then
if r.mdioi /= '0' then
v.mdio_ctrl.linkfail := '1';
end if;
end if;
when data =>
if mclk = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "00000" then
v.mdio_state := dataend;
end if;
if r.mdio_ctrl.read = '0' then
v.mdioo := r.mdio_ctrl.data(mdioindex);
end if;
end if;
if nmclk = '1' then
if r.mdio_ctrl.read = '1' then
v.mdio_ctrl.data(mdioindex) := r.mdioi;
end if;
end if;
when dataend =>
if mclk = '1' then
if (rmii = 1) or (edcl /= 0) then
v.init_busy := '0';
if (r.duplexstate = done or r.ctrl.edcldis = '1' or r.disableduplex = '1') then
v.mdio_ctrl.busy := '0';
end if;
else
v.mdio_ctrl.busy := '0';
end if;
v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
when others =>
null;
end case;
end if;
-------------------------------------------------------------------------------
-- EDCL -----------------------------------------------------------------------
-------------------------------------------------------------------------------
if (edcl /= 0) then
if (ramdebug /= 2) or (r.ctrl.ramdebugen = '0') then
veri.renable := r.erenable; veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
vrxenable := '1';
end if;
swap := '0'; vecnt := conv_integer(r.ecnt); setmz := '0';
if vrxwrite = '1' then
if r.ctrl.edcldis = '0' then
v.rxwriteack := not r.rxwriteack;
end if;
end if;
--edcl receiver
case r.edclrstate is
when idle =>
v.edclbcast := '0'; v.erxidle := '1';
if (ramdebug /= 2) or (r.ctrl.ramdebugen = '0') then
if (rxstart and not r.ctrl.edcldis) = '1' then
v.edclrstate := wrda; v.edclactive := '0'; v.erxidle := '0';
v.rcntm := conv_std_logic_vector(2, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
end if;
end if;
when wrda =>
if vrxwrite = '1' then
v.edclrstate := wrdsa;
veri.writem := '1'; veri.writel := '1';
swap := '1';
v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1;
if (r.emacaddr(47 downto 16) /= rxo.dataout) and
(X"FFFFFFFF" /= rxo.dataout) then
v.edclrstate := spill;
elsif (X"FFFFFFFF" = rxo.dataout) then
v.edclbcast := '1';
end if;
if conv_integer(r.abufs) = wsz then
v.edclrstate := spill;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrdsa =>
if vrxwrite = '1' then
v.edclrstate := wrsa; swap := '1';
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2;
if (r.emacaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and
(X"FFFF" /= rxo.dataout(31 downto 16)) then
v.edclrstate := spill;
elsif (X"FFFF" = rxo.dataout(31 downto 16)) then
v.edclbcast := r.edclbcast;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrsa =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.edclrstate := wrtype; swap := '1';
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrtype =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then
v.edclrstate := ip;
elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then
v.edclrstate := arp;
else
v.edclrstate := spill;
end if;
end if;
v.ecnt := (others => '0'); v.ipcrc := (others => '0');
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ip =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 1 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2;
when 2 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1;
when 3 =>
v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2;
when 4 =>
v.udpsrc := rxo.dataout(15 downto 0);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1;
when 5 =>
setmz := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 6 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 7 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if (rxo.dataout(31 downto 18) = r.seq) then
v.nak := '0';
else
v.nak := '1';
veri.datain(31 downto 18) := r.seq;
end if;
veri.datain(17) := v.nak; v.ewr := rxo.dataout(17);
if (rxo.dataout(17) or v.nak) = '1' then
veri.datain(16 downto 7) := (others => '0');
end if;
v.oplen := rxo.dataout(16 downto 7);
v.applength := "000000" & veri.datain(16 downto 7);
v.ipcrc :=
crcadder(v.applength + 38, r.ipcrc);
v.write(conv_integer(r.rpnt)) := rxo.dataout(17);
when 8 =>
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc :=
crcadder(ipcrctmp, ipcrctmp2);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
v.edclrstate := ipdata;
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ipdata =>
if (vrxwrite and r.ewr and not r.nak) = '1' and
(r.rcntm /= ebufmax) then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
end if;
if rxdone = '1' then
v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits);
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc := crcadder(ipcrctmp, ipcrctmp2);
if conv_integer(v.rxstatus(3 downto 0)) /= 0 then
v.edclrstate := idle;
end if;
end if;
when ipcrc =>
veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0);
v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits);
v.rcntl := conv_std_logic_vector(9, bpbits);
when udp =>
veri.writem := '1'; veri.writel := '1';
v.edclrstate := iplength;
veri.datain(31 downto 16) := r.udpsrc;
veri.datain(15 downto 0) := r.applength + 18;
v.rcntm := conv_std_logic_vector(4, bpbits);
when iplength =>
veri.writem := '1';
veri.datain(31 downto 16) := r.applength + 38;
v.edclrstate := oplength;
v.rcntm := conv_std_logic_vector(10, bpbits);
v.rcntl := conv_std_logic_vector(10, bpbits);
when oplength =>
if rxstart = '0' then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
veri.writel := '1'; veri.writem := '1';
end if;
if r.nak = '0' then
v.seq := r.seq + 1;
end if;
v.edclrstate := idle;
veri.datain(31 downto 0) := (others => '0');
veri.datain(15 downto 0) := "00000" & r.nak & r.oplen;
when arp =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.rcntm := r.rcntm + 4;
when 1 =>
swap := '1'; veri.writel := '0';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4;
when 2 =>
swap := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 3 =>
swap := '1';
v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4;
when 4 =>
veri.datain := r.emacaddr(31 downto 16) & r.emacaddr(47 downto 32);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 5 =>
v.rcntl := r.rcntl + 1;
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := r.emacaddr(15 downto 0);
if rxo.dataout(15 downto 0) /= r.edclip(31 downto 16) then
v.edclrstate := spill;
end if;
when 6 =>
swap := '1'; veri.writem := '0';
v.rcntm := conv_std_logic_vector(5, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
if rxo.dataout(31 downto 16) /= r.edclip(15 downto 0) then
v.edclrstate := spill;
else
v.edclactive := '1';
end if;
when 7 =>
veri.writem := '0';
veri.datain(15 downto 0) := r.emacaddr(47 downto 32);
v.rcntl := r.rcntl + 1;
v.rcntm := conv_std_logic_vector(2, bpbits);
when 8 =>
v.edclrstate := arpop;
veri.datain := r.emacaddr(31 downto 0);
v.rcntm := conv_std_logic_vector(5, bpbits);
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when arpop =>
veri.writem := '1'; veri.datain(31 downto 16) := X"0002";
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
end if;
end if;
when spill =>
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
end case;
--edcl transmitter
case r.txdstate is
when getlen =>
v.tcnt := r.tcnt + 1;
if conv_integer(r.tcnt) = 10 then
v.txlength := '0' & erdata(9 downto 0);
v.tnak := erdata(10);
v.txcnt := v.txlength;
if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then
v.txlength := (others => '0');
end if;
end if;
if conv_integer(r.tcnt) = 11 then
v.txdstate := readhdr;
v.tcnt := (others => '0');
end if;
when readhdr =>
v.tcnt := r.tcnt + 1; vtxfi.write := '1';
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1;
vtxfi.datain := erdata;
if conv_integer(r.tcnt) = 12 then
v.txaddr := erdata(31 downto 2);
end if;
if conv_integer(r.tcnt) = 3 then
if erdata(31 downto 16) = X"0806" then
v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11);
else
v.tarp := '0'; v.txlength := r.txlength + 52;
end if;
end if;
if r.tarp = '0' then
if conv_integer(r.tcnt) = 12 then
v.txdstate := start;
end if;
else
if conv_integer(r.tcnt) = 10 then
v.txdstate := start;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when start =>
v.tmsto.addr := r.txaddr & "00";
v.tmsto.write := r.write(conv_integer(r.tpnt));
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.addr := r.txaddr & "00";
v.tmsto2.write := r.write(conv_integer(r.tpnt));
end if;
if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then
v.txdstate := etdone;
v.txstart_sync := not r.txstart_sync;
v.tmsto.req := '0';
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.req := '0';
end if;
elsif r.write(conv_integer(r.tpnt)) = '0' then
v.txdstate := req; v.tedcl := '1';
else
v.txstart_sync := not r.txstart_sync;
v.tedcl := '1';
v.tcnt := r.tcnt + 1;
if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') then
v.tmsto.req := '1'; v.tmsto.data := erdata;
v.txdstate := wrbus1;
else
v.tmsto2.req := '1'; v.tmsto2.data := erdata;
v.txdstate := wrbus2;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when wrbus1 =>
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready or tmsti.error) = '1' then
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti.retry = '1' then
v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1';
end if;
when wrbus2 =>
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready or tmsti2.error) = '1' then
v.tmsto2.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto2.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti2.retry = '1' then
v.tmsto2.addr := r.tmsto2.addr - 4; v.tmsto2.req := '1';
end if;
when etdone =>
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
elsif txrestart = '1' then
v.txdstate := idle;
end if;
when others =>
null;
end case;
if swap = '1' then
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := rxo.dataout(31 downto 16);
end if;
if setmz = '1' then
veri.datain(31 downto 16) := (others => '0');
end if;
if (ramdebug /= 2) or (edcl = 0) or (edcldbgread = '0') then
veri.raddress := r.tpnt & v.tcnt;
end if;
end if;
--edcl duplex mode read
if (rmii = 1) or (edcl /= 0) then
--edcl, gbit link mode check
case r.duplexstate is
when start =>
if (r.ctrl.edcldis = '0' and r.disableduplex = '0') then
v.mdio_ctrl.regadr := r.regaddr; v.init_busy := '1';
v.mdio_ctrl.busy := '1'; v.duplexstate := waitop;
if (r.phywr or r.rstphy) = '1' then
v.mdio_ctrl.write := '1';
else
v.mdio_ctrl.read := '1';
end if;
if r.rstphy = '1' then
v.mdio_ctrl.data := X"9000";
end if;
end if;
when waitop =>
if r.init_busy = '0' then
if r.mdio_ctrl.linkfail = '1' then
v.duplexstate := start;
elsif r.rstphy = '1' then
v.duplexstate := start; v.rstphy := '0';
else
v.duplexstate := nextop;
end if;
end if;
when nextop =>
case r.regaddr is
when "00000" =>
if r.mdio_ctrl.data(15) = '1' then --rst not finished
v.duplexstate := start;
elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD
v.duplexstate := selmode;
elsif r.mdio_ctrl.data(12) = '0' then --no auto neg
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := (others => '0');
else
v.duplexstate := start; v.regaddr := "00001";
end if;
if r.rstaneg = '1' then
v.phywr := '0';
end if;
if r.disableduplex = '1' then
v.duplexstate := done; v.mdio_ctrl.busy := '0';
end if;
when "00001" =>
v.ext := r.mdio_ctrl.data(8); --extended status register
v.extcap := r.mdio_ctrl.data(1); --extended register capabilities
v.duplexstate := start;
if r.mdio_ctrl.data(0) = '0' then
--no extended register capabilites, unable to read aneg config
--forcing 10 Mbit
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := (others => '0');
v.regaddr := (others => '0');
elsif (r.mdio_ctrl.data(8) and not r.rstaneg) = '1' then
--phy gbit capable, disable gbit
v.regaddr := "01001";
elsif r.mdio_ctrl.data(5) = '1' then --auto neg completed
v.regaddr := "00100";
end if;
if r.disableduplex = '1' then
v.duplexstate := done; v.mdio_ctrl.busy := '0';
end if;
when "00100" =>
v.duplexstate := start; v.regaddr := "00101";
v.capbil(4 downto 0) := r.mdio_ctrl.data(9 downto 5);
when "00101" =>
v.duplexstate := selmode;
v.capbil(4 downto 0) :=
r.capbil(4 downto 0) and r.mdio_ctrl.data(9 downto 5);
when "01001" =>
if r.phywr = '0' then
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data(9 downto 8) := (others => '0');
else
v.regaddr := "00000";
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := X"3300"; v.rstaneg := '1';
end if;
when others =>
null;
end case;
when selmode =>
v.duplexstate := done; v.mdio_ctrl.busy := '0';
if r.phywr = '1' then
v.ctrl.full_duplex := '0'; v.ctrl.speed := '0';
else
sel_op_mode(r.capbil, v.ctrl.speed, v.ctrl.full_duplex);
end if;
when done =>
null;
end case;
-- MDIO Disable
if r.ctrl.edcldis = '1' or r.disableduplex = '1' then
if v.duplexstate /= start then
v.duplexstate := start;
v.mdio_ctrl.regadr := (others => '0');
v.mdio_ctrl.busy := '0';
v.init_busy := '0';
v.mdio_ctrl.write := '0';
v.mdio_ctrl.read := '0';
v.mdio_ctrl.data := X"0000";
end if;
end if;
end if;
--transmitter retry
if tmsti.retry = '1' then
v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto.req := '0'; v.txdstate := ahberror;
end if;
if (edclsepahbg /= 0) and (edcl /= 0) then
--transmitter retry
if tmsti2.retry = '1' then
v.tmsto2.req := '1'; v.tmsto2.addr := r.tmsto2.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti2.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto2.req := '0'; v.txdstate := ahberror;
end if;
end if;
--receiver retry
if rmsti.retry = '1' then
v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4;
v.rxburstcnt := r.rxburstcnt - 1;
end if;
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if irst = '0' then
v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0');
v.tmsto.req := '0'; v.tmsto2.req := '0'; v.rfwpnt := (others => '0');
v.rfcnt := (others => '0');
v.ctrl.txen := '0';
v.txirqgen := '0'; v.ctrl.rxen := '0';
v.txdsel := (others => '0'); v.txstart_sync := '0';
v.txread := (others => '0'); v.txrestart := (others => '0');
v.txdone := (others => '0'); v.txreadack := '0';
v.rxdsel := (others => '0'); v.rxdone := (others => '0');
v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0';
v.rxstart := (others => '0'); v.rxwrite := (others => '0');
v.status.invaddr := '0'; v.status.toosmall := '0';
v.ctrl.full_duplex := '0'; v.writeok := '1';
if (enable_mdio = 0) or (edcl /= 0) then
v.ctrl.reset := '0';
end if;
if enable_mdint = 1 then
v.status.phystat := '0'; v.ctrl.pstatirqen := '0';
end if;
if (edcl /= 0) then
v.tpnt := (others => '0'); v.rpnt := (others => '0');
v.tcnt := (others => '0'); v.edclactive := '0';
v.tarp := '0'; v.abufs := (others => '0');
v.edclrstate := idle;
v.emacaddr := macaddrt;
end if;
if (rmii = 1) then
v.ctrl.speed := '1';
end if;
v.ctrl.tx_irqen := '0';
v.ctrl.rx_irqen := '0';
v.ctrl.prom := '0';
if multicast = 1 then
v.ctrl.mcasten := '0';
end if;
if ramdebug /= 0 then
v.ctrl.ramdebugen := '0';
end if;
end if;
if edcl = 0 then
v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0';
v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0');
v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0');
v.applength := (others => '0'); v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0';
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
end if;
--some parts of edcl are only affected by hw reset
if rst = '0' then
v.edclip := conv_std_logic_vector(ipaddrh, 16) &
conv_std_logic_vector(ipaddrl, 16);
if edcl > 1 then
v.edclip(3 downto 0) := edcladdr;
v.emacaddr(3 downto 0) := edcladdr;
end if;
v.duplexstate := start; v.regaddr := (others => '0');
v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0';
if phyrstadr /= 32 then
v.mdio_ctrl.phyadr := conv_std_logic_vector(phyrstadr, 5);
else
v.mdio_ctrl.phyadr := phyrstaddr;
end if;
v.seq := (others => '0');
if (enable_mdio = 1) then
v.mdccnt := divisor; v.mdioclk := '0';
end if;
if edcl /= 0 then
v.disableduplex := '0';
end if;
if edcl = 3 then
v.ctrl.edcldis := edcldisable;
elsif edcl /= 0 then
v.ctrl.edcldis := '0';
end if;
v.ctrl.reset := '0';
if (enable_mdio = 1) then
v.mdio_state := idle; v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.mdio_ctrl.busy := '0';
v.mdio_ctrl.data := (others => '0');
v.mdio_ctrl.regadr := (others => '0');
v.ctrl.reset := '0'; v.mdio_ctrl.linkfail := '1';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
v.cnt := (others => '0');
end if;
if edclsepahbg /= 0 then
v.edclsepahb := edclsepahb;
end if;
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
v.tedcl := '0'; v.erenable := '0';
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
v.gotframe := '0';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.txburstav := '0'; v.txdataav := '0';
v.txstatus := (others => '0'); v.txstart := '0';
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0'); v.txaddr := (others => '0');
v.cnt := (others => '0');
v.rxaddr := (others => '0');
v.rxstatus := (others => '0');
v.rxwrap := '0'; v.rxden := '0';
v.rmsto.addr := (others => '0');
v.tmsto.addr := (others => '0');
v.nak := '0'; v.ewr := '0';
v.write := (others => '0');
v.applength := (others => '0');
v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0');
end if;
-------------------------------------------------------------------------------
-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
-------------------------------------------------------------------------------
rin <= v;
prdata <= vprdata;
irq <= vpirq;
--rx ahb fifo
rxrenable <= vrxfi.renable;
rxraddress(10 downto fabits) <= (others => '0');
rxraddress(fabits-1 downto 0) <= vrxfi.raddress;
rxwrite <= vrxfi.write;
rxwdata <= vrxfi.datain;
rxwaddress(10 downto fabits) <= (others => '0');
rxwaddress(fabits-1 downto 0) <= vrxfi.waddress;
--tx ahb fifo
txrenable <= vtxfi.renable;
txraddress(10 downto txfabits) <= (others => '0');
txraddress(txfabits-1 downto 0) <= vtxfi.raddress;
txwrite <= vtxfi.write;
txwdata <= vtxfi.datain;
txwaddress(10 downto txfabits) <= (others => '0');
txwaddress(txfabits-1 downto 0) <= vtxfi.waddress;
--edcl buf
erenable <= veri.renable;
eraddress(15 downto eabits) <= (others => '0');
eraddress(eabits-1 downto 0) <= veri.raddress;
ewritem <= veri.writem;
ewritel <= veri.writel;
ewaddressm(15 downto eabits) <= (others => '0');
ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0);
ewaddressl(15 downto eabits) <= (others => '0');
ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0);
ewdata <= veri.datain;
rxi.enable <= vrxenable;
end process;
rxi.writeack <= r.rxwriteack;
rxi.doneack <= r.rxdoneack;
rxi.speed <= r.ctrl.speed;
rxi.writeok <= r.writeok;
rxi.rxd <= rxd;
rxi.rx_dv <= rx_dv;
rxi.rx_crs <= rx_crs;
rxi.rx_er <= rx_er;
rxi.rx_en <= rx_en;
txi.rx_col <= rx_col;
txi.rx_crs <= rx_crs;
txi.full_duplex <= r.ctrl.full_duplex;
txi.start <= r.txstart_sync;
txi.readack <= r.txreadack;
txi.speed <= r.ctrl.speed;
txi.data <= r.txdata;
txi.valid <= r.txvalid;
txi.len <= r.txlength;
txi.datavalid <= tx_dv;
mdc <= r.mdioclk;
mdio_o <= r.mdioo;
mdio_oe <= testoen when (scanen/=0 and testen/='0') else r.mdioen;
tmsto <= r.tmsto;
rmsto <= r.rmsto;
tmsto2 <= r.tmsto2;
txd <= txo.txd;
tx_en <= txo.tx_en;
tx_er <= txo.tx_er;
ahbmi.hgrant <= hgrant;
ahbmi.hready <= hready;
ahbmi.hresp <= hresp;
ahbmi.hrdata <= hrdata;
hbusreq <= ahbmo.hbusreq;
hlock <= ahbmo.hlock;
htrans <= ahbmo.htrans;
haddr <= ahbmo.haddr;
hwrite <= ahbmo.hwrite;
hsize <= ahbmo.hsize;
hburst <= ahbmo.hburst;
hprot <= ahbmo.hprot;
hwdata <= ahbmo.hwdata;
ahbmi2.hgrant <= ehgrant;
ahbmi2.hready <= ehready;
ahbmi2.hresp <= ehresp;
ahbmi2.hrdata <= ehrdata;
ehbusreq <= ahbmo2.hbusreq;
ehlock <= ahbmo2.hlock;
ehtrans <= ahbmo2.htrans;
ehaddr <= ahbmo2.haddr;
ehwrite <= ahbmo2.hwrite;
ehsize <= ahbmo2.hsize;
ehburst <= ahbmo2.hburst;
ehprot <= ahbmo2.hprot;
ehwdata <= ahbmo2.hwdata;
speed <= r.ctrl.speed;
reset <= irst;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-------------------------------------------------------------------------------
-- TRANSMITTER-----------------------------------------------------------------
-------------------------------------------------------------------------------
tx_rmii0 : if rmii = 0 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => tx_clk,
txi => txi,
txo => txo);
end generate;
tx_rmii1 : if rmii = 1 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rmii_clk,
txi => txi,
txo => txo);
end generate;
-------------------------------------------------------------------------------
-- RECEIVER -------------------------------------------------------------------
-------------------------------------------------------------------------------
rx_rmii0 : if rmii = 0 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rx_clk,
rxi => rxi,
rxo => rxo);
end generate;
rx_rmii1 : if rmii = 1 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode)
port map(
rst => arst,
clk => rmii_clk,
rxi => rxi,
rxo => rxo);
end generate;
-------------------------------------------------------------------------------
-- AHB MST INTERFACE ----------------------------------------------------------
-------------------------------------------------------------------------------
ahb0 : eth_ahb_mst
port map(rst, clk, ahbmi, ahbmo, tmsto, tmsti, rmsto, rmsti);
edclmst : if edclsepahbg = 1 generate
ahb1 : eth_edcl_ahb_mst
port map(rst, clk, ahbmi2, ahbmo2, tmsto2, tmsti2);
end generate;
end architecture;
|
gpl-2.0
|
fff48bef02cf0581a142d50345893f77
| 0.487324 | 3.562924 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/amba/defmst.vhd
| 1 | 1,959 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: defmst
-- File: defmst.vhd
-- Author: Edvin Catovic, Gaisler Research
-- Description: Default AHB master
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
entity ahbdefmst is
generic ( hindex : integer range 0 to NAHBMST-1 := 0);
port ( ahbmo : out ahb_mst_out_type);
end;
architecture rtl of ahbdefmst is
begin
ahbmo.hbusreq <= '0';
ahbmo.hlock <= '0';
ahbmo.htrans <= HTRANS_IDLE;
ahbmo.haddr <= (others => '0');
ahbmo.hwrite <= '0';
ahbmo.hsize <= (others => '0');
ahbmo.hburst <= (others => '0');
ahbmo.hprot <= (others => '0');
ahbmo.hwdata <= (others => '0');
ahbmo.hirq <= (others => '0');
ahbmo.hconfig <= (others => (others => '0'));
ahbmo.hindex <= hindex;
end;
|
gpl-2.0
|
cf09a585ee83082bcd8377a5b5cfe8d2
| 0.587545 | 4.030864 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ahb2mig_7series_ddr2.vhd
| 1 | 25,561 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_7series_ddr2_dq16_ad13_ba3
-- File: ahb2mig_7series_ddr2.vhd
-- Author: Pascal Trotta
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG. (adapted from
-- ahb2mig_7series to work with 16-bit ddr2 memories)
-- Notes: - works only with 32-bit bus
-- - does not replicate output data
-- - does not support MIG interface model
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_7series_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_7series_ddr2_dq16_ad13_ba3 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_reset_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_7series_ddr2_dq16_ad13_ba3 is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant maxburst : integer := 8;
constant maxmigcmds : integer := 3;
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(128*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(16*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(128*maxmigcmds-1 downto 0);
rd_buffer : unsigned(128*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(127 downto 0);
wdf_mask_buffer : std_logic_vector(15 downto 0);
migcommands : integer;
nxt : std_logic;
maxrburst : integer;
end record;
type mig_in_type is record
app_addr : std_logic_vector(26 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(127 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(15 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(127 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
component mig is
port (
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-5 downto 4)) & "000"),startaddress'length);
-- Adjust offset in memory buffer
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 4))&"0000");
step_offset := resize(unsigned(haddr_offset(5 downto 4)&"00"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds16(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep16(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(127 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(255 downto 128) := unsigned(migout.app_rd_data);
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit output
v.hrdata := ahbselectdatanoreplicaoutput16(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,false);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Set maximum read burst depending on the starting address offset
case r.haddr_start(3 downto 2) is
when "01" => v.maxrburst := 7;
when "10" => v.maxrburst := 6;
when "11" => v.maxrburst := 5;
when others => v.maxrburst := 8;
end case;
-- Check if this was the last transaction
if (r.wr_count >= v.maxrburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= v.maxrburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0'; v.maxrburst := maxburst;
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00";
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(26 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(15 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(127 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
elsif (r.wr_count = 1) then --to support 3 migcmds
r.wdf_mask_buffer <= not r.mask_burst(47 downto 32);
r.wdf_data_buffer <= r.hwdata_burst(383 downto 256);
else
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
MCB_inst : mig
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
sys_clk_i => sys_clk_i,
clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end;
|
gpl-2.0
|
7f42d048c5072ff7fdca6f96ed1177ae
| 0.522202 | 3.448597 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml50x/leon3mp.vhd
| 1 | 43,628 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
use work.pcie.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
use unisim.IBUFDS;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
clk_33 : in std_ulogic; -- 33 MHz
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqsp : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(12 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
sgmii_rx_n : in std_ulogic;
sgmii_rx_p : in std_ulogic;
sgmii_tx_n : out std_ulogic;
sgmii_tx_p : out std_ulogic;
sgmiiclk_qo_n : in std_ulogic;
sgmiiclk_qo_p : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
iic_scl_video : inout std_logic;
iic_sda_video : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(15 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_PCIEXP;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal sgmii_refclk, sgmii_rst : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal mdio_reset, mdio_o, mdio_oe, mdio_i, mdc, mdint : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of clk_33_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
clk_33_pad : clkpad generic map (tech => padtech)
port map (clk_33, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
-- D1 => vcc(0), D2 => gnd(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => CFG_BOARD_SELECTION,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
bus_error(0) <= not dbgo(0).error;
bus_error(1) <= rstn;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
txd2 <= '0'; -- Second UART is unused
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr_ad(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr_ba(1 downto 0), ddr2_ras_n => ddr_rasb,
ddr2_cas_n => ddr_casb, ddr2_we_n => ddr_web,
ddr2_cs_n => ddr_csb(CS_NUM-1 downto 0), ddr2_odt => ddr_odt(0 downto 0),
ddr2_cke => ddr_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr_dqsp(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr_dqsn(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr_clk((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr_clkb((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
ddr_ad(13) <= '0';
ddr_odt(1) <= '0';
ddr_csb(1) <= '0';
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt);
led(5) <= '0';
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; led(5) <= '0'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_d, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(
memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_video, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_video, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 13)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio, gpioo.dout(12 downto 0), gpioo.oen(12 downto 0),
gpioi.din(12 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
gmii_eth: if CFG_GRETH_SGMII_MODE = 0 generate
e1 : grethm
generic map(
hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1
)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho
);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
sgmii_eth: if CFG_GRETH_SGMII_MODE /= 0 generate
sgmii_rst <= not rst;
refclk_bufds : IBUFDS
port map (
I => sgmiiclk_qo_p,
IB => sgmiiclk_qo_n,
O => sgmii_refclk
);
e1 : greths
generic map(
hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 7,
fabtech => fabtech,
memtech => memtech,
transtech => transtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1
)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi,
apbo => apbo(11),
-- High-speed Serial Interface
clk_125 => sgmii_refclk,
rst_125 => sgmii_rst,
eth_rx_p => sgmii_rx_p,
eth_rx_n => sgmii_rx_n,
eth_tx_p => sgmii_tx_p,
eth_tx_n => sgmii_tx_n,
-- MDIO interface
reset => mdio_reset,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
mdio_i => mdio_i,
mdc => mdc,
mdint => mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0000",
edclsepahb => '0',
edcldisable => '0'
);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, mdio_o, mdio_oe, mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, mdio_reset);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, mdint);
end generate;
end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hslvndx => 6,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 10,
paddr => 10,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE)
);
end generate;
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
dapbndx => 13, dapbaddr => 13,dapbirq => 13, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 6, apbndx => 10, apbaddr => 10, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(13),
dahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(6)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 6, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 10, paddr => 10,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10)
);
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(CFG_BOARD_SELECTION),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
9a0a745273c5f2f9ac0bbe62528e29bc
| 0.549441 | 3.448036 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/inferred/fifo_inferred.vhd
| 1 | 9,254 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: fifo_inferred.vhd
-- Author: Cobham Gaisler AB
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.">";
use ieee.std_logic_unsigned."<";
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity generic_fifo is
generic (
tech : integer := 0; -- target technology
abits : integer := 10; -- fifo address bits (actual fifo depth = 2**abits)
dbits : integer := 32; -- fifo data width
sepclk : integer := 1; -- 1 = asynchrounous read/write clocks, 0 = synchronous read/write clocks
pfull : integer := 100; -- almost full threshold (max 2**abits - 3)
pempty : integer := 10; -- almost empty threshold (min 2)
fwft : integer := 0 -- 1 = first word fall trough mode, 0 = standard mode
);
port (
rclk : in std_logic; -- read clock
rrstn : in std_logic; -- read clock domain synchronous reset
wrstn : in std_logic; -- write clock domain synchronous reset
renable : in std_logic; -- read enable
rfull : out std_logic; -- fifo full (synchronized in read clock domain)
rempty : out std_logic; -- fifo empty
aempty : out std_logic; -- fifo almost empty (depending on pempty threshold)
rusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in read clock domain)
dataout : out std_logic_vector(dbits-1 downto 0); -- fifo data output
wclk : in std_logic; -- write clock
write : in std_logic; -- write enable
wfull : out std_logic; -- fifo full
afull : out std_logic; -- fifo almost full (depending on pfull threshold)
wempty : out std_logic; -- fifo empty (synchronized in write clock domain)
wusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in write clock domain)
datain : in std_logic_vector(dbits-1 downto 0)); -- fifo data input
end;
architecture rtl_fifo of generic_fifo is
procedure gray_encoder(variable idata : in std_logic_vector; variable odata : out std_logic_vector) is
begin
for i in 0 to (idata'left)-1 loop
odata(i) := idata(i) xor idata(i+1);
end loop;
odata(odata'left) := idata(idata'left);
end gray_encoder;
procedure gray_decoder(signal idata : in std_logic_vector; constant size : integer; variable odata : out std_logic_vector) is
variable vdata : std_logic_vector(size downto 0);
begin
vdata(vdata'left) := idata(idata'left);
for i in (idata'left)-1 downto 0 loop
vdata(i) := idata(i) xor vdata(i+1);
end loop;
odata := vdata;
end gray_decoder;
type wfifo_type is record
waddr : std_logic_vector(abits downto 0);
waddr_gray : std_logic_vector(abits downto 0);
full : std_logic;
end record;
type rfifo_type is record
raddr : std_logic_vector(abits downto 0);
raddr_gray : std_logic_vector(abits downto 0);
empty : std_logic;
end record;
signal wregs, wregsin : wfifo_type;
signal rregs, rregsin : rfifo_type;
signal raddr_sync_encoded, waddr_sync_encoded : std_logic_vector(abits downto 0);
signal empty_sync, full_sync : std_logic;
begin
---------------------
-- write clock domain
---------------------
wdomain_comb: process(wregs, write, raddr_sync_encoded, wrstn)
variable vwregs : wfifo_type;
variable vwusedw : std_logic_vector(abits-1 downto 0);
variable raddr_sync_decoded : std_logic_vector(abits downto 0);
begin
-- initialize fifo signals on write side
vwregs := wregs;
vwregs.full := '0';
afull <= '0';
-- fifo full generation and compute wusedw
gray_decoder(raddr_sync_encoded,abits,raddr_sync_decoded); -- decode read address coming from read clock domain
if (vwregs.waddr(abits)=raddr_sync_decoded(abits)) then
vwusedw := vwregs.waddr(abits-1 downto 0)-raddr_sync_decoded(abits-1 downto 0);
if (vwusedw > (2**abits-2)) then
vwregs.full := '1';
end if;
else
vwusedw := raddr_sync_decoded(abits-1 downto 0)-vwregs.waddr(abits-1 downto 0);
if (vwusedw < 2) then
vwregs.full := '1';
end if;
vwusedw := 2**abits - vwusedw;
end if;
-- write fifo
if write = '1' then
vwregs.waddr := vwregs.waddr + 1;
end if;
gray_encoder(vwregs.waddr,vwregs.waddr_gray);
-- assign wusedw and almost full fifo output
wusedw <= vwusedw;
if vwusedw>pfull then
afull <= '1';
end if;
-- synchronous reset
if wrstn = '0' then
vwregs.waddr := (others =>'0');
vwregs.waddr_gray := (others =>'0');
vwregs.full := '0';
end if;
-- update fifo signals
wregsin <= vwregs;
end process;
wdomain_regs: process(wclk)
begin
if rising_edge(wclk) then
wregs <= wregsin;
end if;
end process;
------------
-- sync regs
------------
-- transfer write address (encoded) in read clock domain
-- transfer read address (encoded) in write clock domain
-- transfer empty in write clock domain
-- transfer full in read block domain
-- Note: input d is already registered in the source clock domain
syn_gen0: for i in 0 to abits generate -- fifo addresses
syncreg_inst0: syncreg generic map (tech => tech, stages => 2)
port map(clk => rclk, d => wregs.waddr_gray(i), q => waddr_sync_encoded(i));
syncreg_inst1: syncreg generic map (tech => tech, stages => 2)
port map(clk => wclk, d => rregs.raddr_gray(i), q => raddr_sync_encoded(i));
end generate;
syncreg_inst2: syncreg generic map (tech => tech, stages => 2)
port map(clk => wclk, d => rregs.empty, q => empty_sync);
syncreg_inst3: syncreg generic map (tech => tech, stages => 2)
port map(clk => rclk, d => wregs.full, q => full_sync);
-- Assign synchronized empty/full to fifo outputs
wempty <= empty_sync;
rfull <= full_sync;
wfull <= wregsin.full;
rempty <= rregsin.empty;
--------------------
-- read clock domain
--------------------
rdomain_comb: process(rregs, renable, waddr_sync_encoded, rrstn)
variable vrregs : rfifo_type;
variable vrusedw : std_logic_vector(abits-1 downto 0);
variable waddr_sync_decoded : std_logic_vector(abits downto 0);
begin
-- initialize fifo signals on read side
vrregs := rregs;
vrregs.empty := '0';
aempty <= '0';
-- fifo empty generation
gray_encoder(vrregs.raddr,vrregs.raddr_gray);
if (vrregs.raddr_gray=waddr_sync_encoded) then
vrregs.empty := '1';
end if;
-- compute and assign rusedw fifo output
gray_decoder(waddr_sync_encoded,abits,waddr_sync_decoded);
if (vrregs.raddr(abits)=waddr_sync_decoded(abits)) then
vrusedw := waddr_sync_decoded(abits-1 downto 0)-vrregs.raddr(abits-1 downto 0);
else
vrusedw := (2**abits) - (vrregs.raddr(abits-1 downto 0)-waddr_sync_decoded(abits-1 downto 0));
end if;
rusedw <= vrusedw;
-- assign almost empty
if vrusedw<pempty then
aempty <= '1';
end if;
-- read fifo
if renable = '1' then
vrregs.raddr := vrregs.raddr + 1;
end if;
-- synchronous reset
if rrstn = '0' then
vrregs.raddr := (others =>'0');
vrregs.raddr_gray := (others =>'0');
vrregs.empty := '1';
end if;
-- update fifo signals
rregsin <= vrregs;
end process;
rdomain_regs: process(rclk)
begin
if rising_edge(rclk) then
rregs <= rregsin;
end if;
end process;
-- memory instantiation
nofwft_gen: if fwft = 0 generate
ram0 : syncram_2p generic map ( tech => tech, abits => abits, dbits => dbits, sepclk => sepclk)
port map (rclk, renable, rregsin.raddr(abits-1 downto 0), dataout, wclk, write, wregsin.waddr(abits-1 downto 0), datain);
end generate;
fwft_gen: if fwft = 1 generate
ram0 : syncram_2p generic map ( tech => tech, abits => abits, dbits => dbits, sepclk => sepclk)
port map (rclk, '1', rregsin.raddr(abits-1 downto 0), dataout, wclk, write, wregs.waddr(abits-1 downto 0), datain);
end generate;
end;
|
gpl-2.0
|
3562a4d18340288c5e8a31896f3f379d
| 0.63097 | 3.728445 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/grgpio.vhd
| 1 | 15,812 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpio
-- File: grgpio.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Scalable general-purpose I/O port
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpio is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0; -- Only synchronous reset
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0;
iflagreg : integer range 0 to 1 := 0;
bpmode : integer range 0 to 1 := 0;
inpen : integer range 0 to 1 := 0;
doutresv : integer := 0;
dirresv : integer := 0;
bpresv : integer := 0;
inpresv : integer := 0;
pulse : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end;
architecture rtl of grgpio is
constant REVISION : integer := 3;
constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
constant DOUT_RESVAL : std_logic_vector(31 downto 0) := conv_std_logic_vector(doutresv, 32);
constant DIR_RESVAL : std_logic_vector(31 downto 0) := conv_std_logic_vector(dirresv, 32);
constant BP_RESVAL : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpresv, 32);
constant INPEN_RESVAL : std_logic_vector(31 downto 0) := conv_std_logic_vector(inpresv, 32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPIO, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- Prevent tools from issuing index errors for unused code
function calc_nirqmux return integer is
begin
if irqgen = 0 then return 1; end if;
return irqgen;
end;
constant NIRQMUX : integer := calc_nirqmux;
subtype irqmap_type is std_logic_vector(log2x(NIRQMUX)-1 downto 0);
type irqmap_array_type is array (natural range <>) of irqmap_type;
type registers is record
din1 : std_logic_vector(nbits-1 downto 0);
din2 : std_logic_vector(nbits-1 downto 0);
dout : std_logic_vector(nbits-1 downto 0);
imask : std_logic_vector(nbits-1 downto 0);
level : std_logic_vector(nbits-1 downto 0);
edge : std_logic_vector(nbits-1 downto 0);
ilat : std_logic_vector(nbits-1 downto 0);
dir : std_logic_vector(nbits-1 downto 0);
bypass : std_logic_vector(nbits-1 downto 0);
irqmap : irqmap_array_type(nbits-1 downto 0);
iflag : std_logic_vector(nbits-1 downto 0);
inpen : std_logic_vector(nbits-1 downto 0);
pulse : std_logic_vector(nbits-1 downto 0);
end record;
constant nbitszero : std_logic_vector(nbits-1 downto 0) := (others => '0');
constant irqmapzero : irqmap_array_type(nbits-1 downto 0) := (others => (others => '0'));
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : registers := (
din1 => nbitszero, din2 => nbitszero, -- Sync. regs, not reset
dout => DOUT_RESVAL(nbits-1 downto 0), imask => nbitszero, level => nbitszero, edge => nbitszero,
ilat => nbitszero, dir => DIR_RESVAL(nbits-1 downto 0), bypass => BP_RESVAL(nbits-1 downto 0), irqmap => irqmapzero,
iflag => nbitszero, inpen => INPEN_RESVAL(nbits-1 downto 0),
pulse => nbitszero);
signal r, rin : registers;
signal arst : std_ulogic;
begin
arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
comb : process(rst, r, apbi, gpioi)
variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
variable v : registers;
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
din := (others => '0');
din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
if inpen /= 0 then
din(nbits-1 downto 0) := din(nbits-1 downto 0) and r.inpen;
end if;
v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
if (syncrst = 1) and (rst = '0') then
dir(nbits-1 downto 0) := DIR_RESVAL(nbits-1 downto 0);
end if;
dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(nbits-1 downto 0) := r.din2;
when "00001" | "10101" | "11001" | "11101" =>
readdata(nbits-1 downto 0) := r.dout;
when "00010" | "10110" | "11010" | "11110" =>
readdata(nbits-1 downto 0) := r.dir;
when "00011" | "10111" | "11011" | "11111"=>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00100" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00101" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00110" =>
if (bypass /= 0) then
readdata(nbits-1 downto 0) :=
r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "00111" =>
readdata(18) := conv_std_logic(pulse /= 0);
readdata(17) := conv_std_logic(inpen /= 0);
readdata(16) := conv_std_logic(iflagreg /= 0);
readdata(12 downto 8) := conv_std_logic_vector(irqgen, 5);
readdata(4 downto 0) := conv_std_logic_vector(nbits-1, 5);
when "10000" =>
if (iflagreg /= 0) then
readdata(nbits-1 downto 0) := PIMASK(nbits-1 downto 0);
end if;
when "10001" =>
if (iflagreg) /= 0 then
readdata(nbits-1 downto 0) := r.iflag and PIMASK(nbits-1 downto 0);
end if;
when "10010" | "10100" | "11000" | "11100" =>
if (inpen /= 0) then
readdata(nbits-1 downto 0) := r.inpen;
end if;
when "10011" =>
if (pulse /= 0) then
readdata(nbits-1 downto 0) := r.pulse;
end if;
when others => --when "01000" to "01111" =>
if (irqgen > 1) then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
readdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8)) := r.irqmap(i*4+j);
end loop;
end if;
end loop;
end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => null;
when "00001" => v.dout := apbi.pwdata(nbits-1 downto 0);
when "00010" => v.dir := apbi.pwdata(nbits-1 downto 0);
when "00011" =>
if (imask /= 0) then
v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00100" =>
if (imask /= 0) then
v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00101" =>
if (imask /= 0) then
v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00110" =>
if (bypass /= 0) then
v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "00111" =>
null;
when "10000" =>
null;
when "10001" =>
if (iflagreg /= 0) then
v.iflag := (r.iflag and not apbi.pwdata(nbits-1 downto 0)) and PIMASK(nbits-1 downto 0);
end if;
when "10010" =>
if (inpen /= 0) then
v.inpen := apbi.pwdata(nbits-1 downto 0);
end if;
when "10011" =>
if (pulse /= 0) then
v.pulse := apbi.pwdata(nbits-1 downto 0);
end if;
when "10100" =>
if (inpen /= 0) then
v.inpen := r.inpen or apbi.pwdata(nbits-1 downto 0);
end if;
when "10101" => v.dout := r.dout or apbi.pwdata(nbits-1 downto 0);
when "10110" => v.dir := r.dir or apbi.pwdata(nbits-1 downto 0);
when "10111" =>
if (imask /= 0) then
v.imask := (r.imask or apbi.pwdata(nbits-1 downto 0)) and PIMASK(nbits-1 downto 0);
end if;
when "11000" =>
if (inpen /= 0) then
v.inpen := r.inpen and apbi.pwdata(nbits-1 downto 0);
end if;
when "11001" => v.dout := r.dout and apbi.pwdata(nbits-1 downto 0);
when "11010" => v.dir := r.dir and apbi.pwdata(nbits-1 downto 0);
when "11011" =>
if (imask /= 0) then
v.imask := (r.imask and apbi.pwdata(nbits-1 downto 0)) and PIMASK(nbits-1 downto 0);
end if;
when "11100" =>
if (inpen /= 0) then
v.inpen := r.inpen xor apbi.pwdata(nbits-1 downto 0);
end if;
when "11101" => v.dout := r.dout xor apbi.pwdata(nbits-1 downto 0);
when "11110" => v.dir := r.dir xor apbi.pwdata(nbits-1 downto 0);
when "11111" =>
if (imask /= 0) then
v.imask := (r.imask xor apbi.pwdata(nbits-1 downto 0)) and PIMASK(nbits-1 downto 0);
end if;
when others => --when "01000" to "01111" =>
if (irqgen > 1) then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
v.irqmap(i*4+j) := apbi.pwdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8));
end loop;
end if;
end loop;
end if;
end case;
end if;
-- interrupt filtering and routing
xirq := (others => '0'); tmp2 := (others => '0');
if (imask /= 0) then
tmp2(nbits-1 downto 0) := r.din2;
for i in 0 to nbits-1 loop
if (PIMASK(i) and r.imask(i)) = '1' then
if r.edge(i) = '1' then
if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
else tmp2(i) := r.din2(i) xor not r.level(i); end if;
else
tmp2(i) := '0';
end if;
end loop;
for i in 0 to nbits-1 loop
if irqgen = 0 then
-- IRQ for line i = i + pirq
if (i+pirq) > NAHBIRQ-1 then
exit;
end if;
xirq(i+pirq) := tmp2(i);
else
-- IRQ for line i determined by irq select register i
for j in 0 to NIRQMUX-1 loop
if (j+pirq) > NAHBIRQ-1 then
exit;
end if;
if (irqgen = 1) or (j = conv_integer(r.irqmap(i))) then
xirq(j+pirq) := xirq(j+pirq) or tmp2(i);
end if;
end loop;
end if;
end loop;
if iflagreg /= 0 then
v.iflag := tmp2(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
end if;
-- toggle dout based on gpioi.sig_in pulse
if pulse /= 0 then
for i in 0 to nbits-1 loop
if r.pulse(i) = '1' and gpioi.sig_in(i) = '1' then
v.dout(i) := not r.dout(i);
end if;
end loop;
end if;
-- drive filtered inputs on the output record
pval := (others => '0');
pval(nbits-1 downto 0) := r.din2;
-- Drive output with gpioi.sig_in for bypassed registers
if bypass /= 0 then
for i in 0 to nbits-1 loop
if r.bypass(i) = '1' then
dout(i) := gpioi.sig_in(i);
end if;
end loop;
end if;
-- Drive output with gpioi.sig_in for bypassed registers
if bpdir /= 0 then
for i in 0 to nbits-1 loop
if ((BPDIRM(i) = '1') and
((gpioi.sig_en(i) = '1' and bpmode = 0) or
(r.bypass(i) = '1' and bpmode = 1))) then
dout(i) := gpioi.sig_in(i);
if bpmode = 0 then
dir(i) := '1';
else
dir(i) := gpioi.sig_en(i);
end if;
end if;
end loop;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.imask := RES.imask; v.bypass := RES.bypass;
v.dir := RES.dir; v.dout := RES.dout;
v.irqmap := RES.irqmap;
if iflagreg /= 0 then
v.iflag := RES.iflag;
end if;
if inpen /= 0 then
v.inpen := RES.inpen;
end if;
if pulse /= 0 then
v.pulse := RES.pulse;
end if;
end if;
if irqgen < 2 then v.irqmap := (others => (others => '0')); end if;
if iflagreg = 0 then v.iflag := (others => '0'); end if;
if inpen = 0 then v.inpen := (others => '0'); end if;
if pulse = 0 then v.pulse := (others => '0'); end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
if (scantest = 1) and (apbi.testen = '1') then
dir := (others => apbi.testoen);
if oepol = 0 then dir := not dir; end if;
elsif (syncrst = 1 ) and (rst = '0') then
dir := (others => '0');
end if;
gpioo.dout <= dout;
gpioo.oen <= dir;
if oepol = 0 then gpioo.oen <= not dir; end if;
gpioo.val <= pval;
-- non filtered input
gpioo.sig_out <= din;
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk, arst)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers din1 and din2 not reset
r.din1 <= rin.din1;
r.din2 <= rin.din2;
end if;
end if;
if (syncrst = 0 ) and (arst = '0') then
r.dir <= DIR_RESVAL(nbits-1 downto 0);
r.dout <= DOUT_RESVAL(nbits-1 downto 0);
if bypass /= 0 then
r.bypass <= BP_RESVAL(nbits-1 downto 0);
end if;
if inpen /= 0 then
r.inpen <= INPEN_RESVAL(nbits-1 downto 0);
end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpio" & tost(pindex) &
": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
-- pragma translate_on
end;
|
gpl-2.0
|
564209a5320d7a3296d240fa0f325c5d
| 0.559512 | 3.303113 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de4/ddr2sim.vhd
| 1 | 10,064 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end ddr2ctrl;
architecture sim of ddr2ctrl is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
-- 200 MHz clock
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 2.5 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 256;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
|
gpl-2.0
|
e9b20a7245bc22dd58b336b286392e32
| 0.461248 | 3.737096 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/outpad_ds.vhd
| 1 | 3,772 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ds
-- File: outpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential output pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad_ds is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0; slew : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of outpad_ds is
signal gnd, oen : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 generate
padp <= i
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
u0 : unisim_outpad_ds generic map (level, slew, voltage) port map (padp, padn, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
igl2 : if (tech = igloo2) generate
u0 : igloo2_outpad_ds port map (padp, padn, i);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_outpad_ds port map (padp, padn, i, oen);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity outpad_dsv is
generic (tech : integer := 0; level : integer := x33v;
voltage : integer := lvds; width : integer := 1;
oepol : integer := 0; slew : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end;
architecture rtl of outpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : outpad_ds generic map (tech, level, voltage, oepol, slew)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
|
gpl-2.0
|
854147977ea41823e628b1e5afcdd7f9
| 0.637328 | 3.495829 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml510/svga2ch7301c.vhd
| 3 | 10,231 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
|
gpl-2.0
|
468b89e98c4566230c4880c7be7473d9
| 0.55498 | 3.566051 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/grfpwxsh.vhd
| 1 | 9,963 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwxsh
-- File: grfpwxsh.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwxsh is
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of grfpwxsh is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
component grfpwsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0);
start : out std_logic;
nonstd : out std_logic;
flop : out std_logic_vector(8 downto 0);
op1 : out std_logic_vector(63 downto 0);
op2 : out std_logic_vector(63 downto 0);
opid : out std_logic_vector(7 downto 0);
flush : out std_logic;
flushid : out std_logic_vector(5 downto 0);
rndmode : out std_logic_vector(1 downto 0);
req : out std_logic_vector(2 downto 0);
res : in std_logic_vector(63 downto 0);
exc : in std_logic_vector(5 downto 0);
allow : in std_logic_vector(2 downto 0);
rdy : in std_logic;
cc : in std_logic_vector(1 downto 0);
idout : in std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpwsh generic map (tech, pclow, dsu, disas,
id)
port map (rst,
clk,
holdn,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2 ,
fpui.start ,
fpui.nonstd ,
fpui.flop ,
fpui.op1 ,
fpui.op2 ,
fpui.opid ,
fpui.flush ,
fpui.flushid ,
fpui.rndmode ,
fpui.req ,
fpuo.res ,
fpuo.exc ,
fpuo.allow ,
fpuo.rdy ,
fpuo.cc ,
fpuo.idout
);
rf1 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2,
testin
);
rf2 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2,
testin
);
end;
|
gpl-2.0
|
cfae2acd5aea9e71294b1389f0928cd3
| 0.478771 | 3.559486 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/jtag/jtagcom.vhd
| 1 | 7,857 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Modified: J. Gaisler, K. Glembo, J. Andersson - Aeroflex Gaisler
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
reread : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tck : in std_ulogic;
trst : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb, nxt_shft);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tcktog: std_logic_vector(nsync-1 downto 0);
tcktog2: std_ulogic;
tdishft: std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
upd : std_logic_vector(nsync-1 downto 0);
upd2 : std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
seq : std_ulogic;
holdn : std_ulogic;
end record;
type tckreg_type is record
tcktog: std_ulogic;
tdi: std_ulogic;
tdor: std_ulogic;
end record;
signal nexttdo: std_ulogic;
signal r, rin : reg_type;
signal tr: tckreg_type;
begin
comb : process (rst, r, tapo, dmao, tr)
variable v : reg_type;
variable redge0 : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
variable vnexttdo: std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
vtapi.en := asel or dsel;
vnexttdo := '0';
if asel='1' then
if tapo.shift='1' then
vnexttdo := r.addr(1);
else
vnexttdo := r.addr(0);
end if;
else
if tapo.shift='1' then
vnexttdo := r.data(1);
else
vnexttdo := r.data(0);
end if;
if reread /= 0 then vnexttdo := vnexttdo and r.holdn; end if;
end if;
nexttdo <= vnexttdo;
vtapi.tdo := tr.tdor;
write := r.addr(34); seq := r.seq;
v.tcktog(0) := r.tcktog(nsync-1); v.tcktog(nsync-1) := tr.tcktog;
v.tcktog2 := r.tcktog(0); v.shift2 := r.shift(0);
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tr.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.upd(0) := r.upd(nsync-1); v.upd(nsync-1) := tapo.upd;
v.upd2 := r.upd(0);
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
redge0 := r.tcktog2 xor r.tcktog(0);
v.tdishft := '0';
vdmai.address := r.addr(31 downto 0); vdmai.wdata := ahbdrivedata(r.data(31 downto 0));
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := '0' & r.addr(33 downto 32);
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge0 = '1' then
if r.asel(0) = '1' then v.addr(33 downto 0) := r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data(31 downto 0) := r.data(32 downto 1); end if;
v.tdishft := '1'; -- Shift in TDI next AHB cycle
end if;
elsif r.upd2 = '1' then
if reread /= 0 then
v.data(32) := '0'; -- Transfer not done
end if;
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
if r.tdishft='1' then
if r.asel(0)='1' then v.addr(34):=r.tdi(0); end if;
if r.dsel(0)='1' then v.data(32):=r.tdi(0); v.seq:=r.tdi(0); end if;
end if;
if reread /= 0 then v.holdn := '1'; end if;
vdmai.size := "000";
when ahb =>
if reread /= 0 and r.shift2 = '1' then v.holdn := '0'; end if;
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := ahbreadword(dmao.rdata);
v.state := nxt_shft;
if reread /= 0 then
v.data(32) := '1'; -- Transfer done
end if;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
when nxt_shft =>
if reread /= 0 then
v.holdn := (r.holdn or r.upd2) and not r.shift2;
if r.upd2 = '0' and r.shift2 = '0' and r.holdn = '1' then v.state := shft; end if;
else
if r.upd2 = '0' then v.state := shft; end if;
end if;
when others =>
v.state := shft; v.addr := (others => '0'); v.seq := '0';
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr := (others => '0'); v.seq := '0';
end if;
if reread = 0 then v.holdn := '0'; end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
tckreg: process (tck,trst)
begin
if rising_edge(tck) then
tr.tcktog <= not tr.tcktog;
tr.tdi <= tapo.tdi;
tr.tdor <= nexttdo;
end if;
if trst='0' then
tr.tcktog <= '0';
tr.tdi <= '0';
tr.tdor <= '0';
end if;
end process;
end;
|
gpl-2.0
|
48922fbeb8f18991571dbe85e28500eb
| 0.546264 | 3.283326 | false | false | false | false |
ECE492W2014G4/G4Capstone
|
vhdl_simulation/fifo_buffer_tb.vhd
| 1 | 2,018 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY fifo_buffer_tb IS
END fifo_buffer_tb;
ARCHITECTURE behavior OF fifo_buffer_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component fifo_buffer
Generic (
constant data_width : positive := 8;
constant fifo_depth : positive := 16
);
port (
clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector(7 downto 0);
write_en : in std_logic;
read_en : in std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal read_en : std_logic := '0';
signal write_en : std_logic := '0';
--Outputs
signal data_out : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fifo_buffer
PORT MAP (
clk => clk,
reset => reset,
data_in => data_in,
write_en => write_en,
read_en => read_en,
data_out => data_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Reset process
reset_proc : process
begin
wait for clk_period * 5;
reset <= '1';
wait for clk_period;
reset <= '0';
wait;
end process;
-- Write process
wr_proc : process
variable counter : unsigned (7 downto 0) := (others => '0');
begin
wait for clk_period * 20;
for i in 1 to 32 loop
counter := counter + 1;
data_in <= std_logic_vector(counter);
wait for clk_period * 1;
write_en <= '1';
end loop;
wait for clk_period * 20;
wait;
end process;
-- Read process
rd_proc : process
begin
wait for clk_period * 30;
read_en <= '1';
wait for clk_period * 5;
read_en <= '0';
wait for clk_period * 5;
read_en <= '1';
wait;
end process;
END;
|
gpl-3.0
|
24e20c56cbf7fbc7f6f51f2e221485db
| 0.613974 | 2.783448 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/usb/grusb.vhd
| 1 | 24,356 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: grusb
-- File: grusb.vhd
-- Author: Marko Isomaki, Jonas Ekergarn
-- Description: Package for GRUSBHC, GRUSBDC, and GRUSB_DCL
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package grusb is
-----------------------------------------------------------------------------
-- USB in/out types
-----------------------------------------------------------------------------
type grusb_in_type is record
datain : std_logic_vector(15 downto 0);
rxactive : std_ulogic;
rxvalid : std_ulogic;
rxvalidh : std_ulogic;
rxerror : std_ulogic;
txready : std_ulogic;
linestate : std_logic_vector(1 downto 0);
nxt : std_ulogic;
dir : std_ulogic;
vbusvalid : std_ulogic;
hostdisconnect : std_ulogic;
functesten : std_ulogic;
urstdrive : std_ulogic;
end record;
constant grusb_in_none : grusb_in_type :=
((others => '0'), '0', '0', '0', '0', '0', (others => '0'),
'0', '0', '0', '0', '0', '0');
type grusb_out_type is record
dataout : std_logic_vector(15 downto 0);
txvalid : std_ulogic;
txvalidh : std_ulogic;
opmode : std_logic_vector(1 downto 0);
xcvrselect : std_logic_vector(1 downto 0);
termselect : std_ulogic;
suspendm : std_ulogic;
reset : std_ulogic;
stp : std_ulogic;
oen : std_ulogic;
databus16_8 : std_ulogic;
dppulldown : std_ulogic;
dmpulldown : std_ulogic;
idpullup : std_ulogic;
drvvbus : std_ulogic;
dischrgvbus : std_ulogic;
chrgvbus : std_ulogic;
txbitstuffenable : std_ulogic;
txbitstuffenableh : std_ulogic;
fslsserialmode : std_ulogic;
tx_enable_n : std_ulogic;
tx_dat : std_ulogic;
tx_se0 : std_ulogic;
end record;
constant grusb_out_none : grusb_out_type :=
((others => '0'), '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0');
type grusb_in_vector is array (natural range <>) of grusb_in_type;
type grusb_out_vector is array (natural range <>) of grusb_out_type;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component grusbhc is
generic (
ehchindex : integer range 0 to NAHBMST-1 := 0;
ehcpindex : integer range 0 to NAPBSLV-1 := 0;
ehcpaddr : integer range 0 to 16#FFF# := 0;
ehcpirq : integer range 0 to NAHBIRQ-1 := 0;
ehcpmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchindex : integer range 0 to NAHBMST-1 := 0;
uhchsindex : integer range 0 to NAHBSLV-1 := 0;
uhchaddr : integer range 0 to 16#FFF# := 0;
uhchmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchirq : integer range 0 to NAHBIRQ-1 := 0;
tech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
apbi : in apb_slv_in_type;
ehc_apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ehc_ahbmo : out ahb_mst_out_type;
uhc_ahbmo : out ahb_mst_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso : out ahb_slv_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
o : out grusb_out_vector((nports-1) downto 0);
i : in grusb_in_vector((nports-1) downto 0));
end component;
component grusbdc is
generic (
hsindex : integer range 0 to NAHBSLV-1 := 0;
hirq : integer range 0 to NAHBIRQ-1 := 0;
haddr : integer := 0;
hmask : integer := 16#FFF#;
hmindex : integer range 0 to NAHBMST-1 := 0;
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
irqi : integer range 0 to NAHBIRQ-1 := 1;
irqo : integer range 0 to NAHBIRQ-1 := 2;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component grusb_dcl is
generic (
hindex : integer := 0;
memtech : integer := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
burstlength: integer range 1 to 512 := 8;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1
);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component grusb_dcl;
component grusbhc_gen is
generic (
tech : integer := 0;
memtech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC APB slave input signals
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC APB slave output signals
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_irq : out std_ulogic;
-- EHC/UHC(s) AHB master input signals
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC(s) AHB slave input signals
uhc_ahbsi_hsel : in std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC AHB master output signals
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC(s) AHB master output signals
uhc_ahbmo_hbusreq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hlock : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_htrans : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbmo_haddr : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbmo_hwrite : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hsize : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hburst : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hprot : out std_logic_vector(((n_cc*4)-1)*uhcgen downto 0);
uhc_ahbmo_hwdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
-- UHC(s) AHB slave output signals
uhc_ahbso_hready : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbso_hresp : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbso_hrdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbso_hsplit : out std_logic_vector(((n_cc*NAHBMST)-1)*uhcgen downto 0);
uhc_irq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
-- ULPI/UTMI+ output signals
xcvrselect : out std_logic_vector(((nports*2)-1) downto 0);
termselect : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataout : out std_logic_vector(((nports*16)-1) downto 0);
txvalidh : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
reset : out std_logic_vector((nports-1) downto 0);
oen : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- ULPI/UTMI+ input signals
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datain : in std_logic_vector(((nports*16)-1) downto 0);
rxvalidh : in std_logic_vector((nports-1) downto 0);
hostdisconnect : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component grusbdc_gen is
generic (
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
-- usb clock
uclk : in std_ulogic;
--usb in signals
datain : in std_logic_vector(15 downto 0);
rxactive : in std_ulogic;
rxvalid : in std_ulogic;
rxvalidh : in std_ulogic;
rxerror : in std_ulogic;
txready : in std_ulogic;
linestate : in std_logic_vector(1 downto 0);
nxt : in std_ulogic;
dir : in std_ulogic;
vbusvalid : in std_ulogic;
urstdrive : in std_ulogic;
--usb out signals
dataout : out std_logic_vector(15 downto 0);
txvalid : out std_ulogic;
txvalidh : out std_ulogic;
opmode : out std_logic_vector(1 downto 0);
xcvrselect : out std_logic_vector(1 downto 0);
termselect : out std_ulogic;
suspendm : out std_ulogic;
reset : out std_ulogic;
stp : out std_ulogic;
oen : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
drvvbus : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- amba clock/rst
hclk : in std_ulogic;
hrst : in std_ulogic;
--ahb master in signals
ahbmi_hgrant : in std_ulogic;
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
--ahb master out signals
ahbmo_hbusreq : out std_ulogic;
ahbmo_hlock : out std_ulogic;
ahbmo_htrans : out std_logic_vector(1 downto 0);
ahbmo_haddr : out std_logic_vector(31 downto 0);
ahbmo_hwrite : out std_ulogic;
ahbmo_hsize : out std_logic_vector(2 downto 0);
ahbmo_hburst : out std_logic_vector(2 downto 0);
ahbmo_hprot : out std_logic_vector(3 downto 0);
ahbmo_hwdata : out std_logic_vector(31 downto 0);
--ahb slave in signals
ahbsi_hsel : in std_ulogic;
ahbsi_haddr : in std_logic_vector(31 downto 0);
ahbsi_hwrite : in std_ulogic;
ahbsi_htrans : in std_logic_vector(1 downto 0);
ahbsi_hsize : in std_logic_vector(2 downto 0);
ahbsi_hburst : in std_logic_vector(2 downto 0);
ahbsi_hwdata : in std_logic_vector(31 downto 0);
ahbsi_hprot : in std_logic_vector(3 downto 0);
ahbsi_hready : in std_ulogic;
ahbsi_hmaster : in std_logic_vector(3 downto 0);
ahbsi_hmastlock : in std_ulogic;
--ahb slave out signals
ahbso_hready : out std_ulogic;
ahbso_hresp : out std_logic_vector(1 downto 0);
ahbso_hrdata : out std_logic_vector(31 downto 0);
ahbso_hsplit : out std_logic_vector(NAHBMST-1 downto 0);
-- misc
irq : out std_logic_vector(2*sepirq downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
end grusb;
|
gpl-2.0
|
96cf2d4f3b79bffb55e840e587a50b8d
| 0.495607 | 3.828356 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/adqout.vhd
| 3 | 7,097 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
library altera;
use altera.all;
entity adqout is
port(
clk : in std_logic; -- clk0
clk_oct : in std_logic; -- clk90
dq_h : in std_logic;
dq_l : in std_logic;
dq_oe : in std_logic;
dq_oct : in std_logic; -- gnd = disable
dq_pad : out std_logic -- DQ pad
);
end;
architecture rtl of adqout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic--;
--dfflo : out std_logic;
--dffhi : out std_logic;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
component DFF is
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dq_reg : std_logic;
signal dq_oe_reg, dq_oe_reg_n, dq_oct_reg : std_logic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dq_oe_reg : signal is true;
attribute syn_preserve of dq_oe_reg : signal is true;
attribute syn_keep of dq_oe_reg_n : signal is true;
attribute syn_preserve of dq_oe_reg_n : signal is true;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQ output register --------------------------------------------------------------
dq_reg0 : stratixiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "true",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => dq_l,
datainhi => dq_h,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dq_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and oct for DQ -----------------------------------------------------
-- dq_oe_reg0 : stratixiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "stratixiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oe,
-- clk => clk,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oe_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- dq_oe_reg0 : dff
-- port map(
-- d => dq_oe,
-- clk => clk,
-- clrn => vcc,
-- prn => vcc,
-- q => dq_oe_reg
-- );
dq_oe_reg0 : process(clk)
begin if rising_edge(clk) then dq_oe_reg <= dq_oe; end if; end process;
dq_oe_reg_n <= not dq_oe_reg;
-- dq_oct_reg0 : stratixiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "stratixiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oct,
-- clk => clk_oct,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oct_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- Out buffer (DQ) ------------------------------------------------------------------
dq_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dq_reg,
oe => dq_oe_reg_n,
dynamicterminationcontrol => dq_oct,--dq_oct_reg, --gnd(0),--dq_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dq_pad,
obar => open
);
end;
|
gpl-2.0
|
df8dc51c1bd615e3c949f364d9b41ce9
| 0.40806 | 3.82794 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-pci-xc2v3000/leon3mp.vhd
| 1 | 27,089 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
spw_rxd : in std_logic_vector(0 to 1);
spw_rxs : in std_logic_vector(0 to 1);
spw_txd : out std_logic_vector(0 to 1);
spw_txs : out std_logic_vector(0 to 1)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal resetnl, clk2x, spw_clkl : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant IOAEN : integer := 0;
constant sysfreq : integer := (CFG_CLKMUL*40000/CFG_CLKDIV);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, sysfreq)
port map (lclk, pci_lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, resetnl);
rst0 : rstgen -- reset generator
port map (resetnl, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(8) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 8)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, irq => 4,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, irq => 4)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => sysfreq/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw_clkl <= clk2x;
spw : if CFG_SPW_EN > 0 generate
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT,
netlist => CFG_SPW_NETLIST, ports => 1, dmachan => CFG_SPW_DMACHAN,
spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(2*sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad generic map (padtech)
port map (spw_rxd(i), dtmp(i));
spw_rxs_pad : inpad generic map (padtech)
port map (spw_rxs(i), stmp(i));
spw_txd_pad : outpad generic map (padtech)
port map (spw_txd(i), spwo(i).d(0));
spw_txs_pad : outpad generic map (padtech)
port map (spw_txs(i), spwo(i).s(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC2V3000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
09d6a39d62300b58eb4ad409858a35cd
| 0.5572 | 3.481877 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-vc707/leon3mp.vhd
| 1 | 47,477 |
-----------------------------------------------------------------------------
-- LEON3 Xilinx VC707 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.grusb.all;
use gaisler.can.all;
use gaisler.l2cache.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false;
autonegotiation : integer := 1
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(4 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
usb_refclk_opt : in std_logic;
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
txp : out std_logic;
txn : out std_logic;
rxp : in std_logic;
rxn : in std_logic;
emdio : inout std_logic;
emdc : out std_ulogic;
eint : in std_ulogic;
erst : out std_ulogic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic
);
end;
architecture rtl of leon3mp is
component sgmii_vc707
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
abits : integer := 8;
autonegotiation : integer := 1;
pirq : integer := 0;
debugmem : integer := 0;
tech : integer := 0
);
port(
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
reset : in std_logic; -- Asynchronous reset for entire core.
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component ahb2mig_7series
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
-- pragma translate_off
component ahbram_sim
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component ;
-- pragma translate_on
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRUSBHC+CFG_GRUSBDC+CFG_GRUSB_DCL;
constant maxahbm : integer := 16;
--constant maxahbs : integer := 1+CFG_DSU+CFG_MCTRL_LEON2+CFG_AHBROMEN+CFG_AHBRAMEN+2+CFG_GRUSBDC;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT+CFG_GRUSBHC+CFG_GRUSBDC+CFG_PRC;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal ui_clk : std_ulogic;
signal clkm : std_ulogic := '0';
signal rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgiu : clkgen_in_type;
signal cgo, cgo2, cgou : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal sgmiii : eth_sgmii_in_type;
signal sgmiio : eth_sgmii_out_type;
signal sgmiirst : std_logic;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal egtx_clk :std_ulogic;
signal negtx_clk :std_ulogic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, uclk ,ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal usbi : grusb_in_vector(0 downto 0);
signal usbo : grusb_out_vector(0 downto 0);
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal clkref : std_logic;
signal migrstn : std_logic;
attribute keep : boolean;
attribute syn_keep : string;
attribute keep of clkm : signal is true;
attribute keep of uclk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen : if (CFG_MIG_7SERIES = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 0)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, lock, migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE, CFG_BP,
CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (button(3), dsui.break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(4), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1),
open, open, open, open, open, open, open, gnd(0));
end generate;
nojtag : if CFG_AHB_JTAG = 0 generate apbo(CFG_NCPU+1) <= apb_none; end generate;
----------------------------------------------------------------------
--- Memory controller ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 26, tech => padtech, level => cmos, voltage => x18v)
port map (address(25 downto 0), memo.address(26 downto 1));
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (oen, memo.oen);
adv_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (adv, '0');
wri_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16, level => cmos, voltage => x18v)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (romsn, vcc(0)); --ahbso(0) <= ahbso_none;
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
l2cdis : if CFG_L2_EN = 0 generate
mig_gen : if (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 4,
haddr => 16#400#,
hmask => 16#C00#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4)
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 5.0 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model; end generate;
no_mig_gen : if (CFG_MIG_7SERIES = 0) generate
ahbram0 : ahbram
generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 128)
port map ( rstn, clkm, ahbsi, ahbso(4));
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate no_mig_gen;
end generate l2cdis;
-----------------------------------------------------------------------------
-- L2 cache covering DDR3 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2c0 : l2c
generic map(hslvidx => 4, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#F00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(4),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 1)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
--mig_gen : if (CFG_MIG_7SERIES = 1) generate
-- gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series
generic map(hindex => 0, haddr => 16#400#, hmask => 16#F00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n, ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n, ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt,
ahbsi => mem_ahbsi, ahbso => mem_ahbso(0), apbi => apbi, apbo => apbo(4),
calib_done => calib_done, rst_n_syn => migrstn, rst_n_async => rstraw,
clk_amba => clkm, sys_clk_p => clk200p, sys_clk_n => clk200n, clk_ref_i => clkref,
ui_clk => clkm, ui_clk_sync_rst => open);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
-- end generate gen_mig;
--end generate mig_gen;
end generate l2cen;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (led(3), lock);
led4_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (led(4), ahbso(4).hready);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 5, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 0, gmiimode => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
sgmiirst <= not rstraw;
sgmii0 : sgmii_vc707
generic map(
pindex => 11,
paddr => 16#010#,
pmask => 16#ff0#,
abits => 8,
autonegotiation => autonegotiation,
pirq => 11,
debugmem => 1,
tech => fabtech
)
port map(
sgmiii => sgmiii,
sgmiio => sgmiio,
gmiii => gmiii,
gmiio => gmiio,
reset => sgmiirst,
apb_clk => clkm,
apb_rstn => rstn,
apbi => apbi,
apbo => apbo(11)
);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (emdio, sgmiio.mdio_o, sgmiio.mdio_oe, sgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (emdc, sgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (eint, sgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (erst, sgmiio.reset);
sgmiii.clkp <= gtrefclk_p;
sgmiii.clkn <= gtrefclk_n;
txp <= sgmiio.txp;
txn <= sgmiio.txn;
sgmiii.rxp <= rxp;
sgmiii.rxn <= rxn;
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc
generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-------------------------------------------------------------------------------
-- USB ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that more than one USB component can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
-- arch 2 = through BUFG or similiar.
--usb_clkout_pad : clkpad
--generic map (tech => padtech, arch => 3)
--port map (usb_clkout, uclk, cgo.clklock, ulock);
usb_clkout_pad : clkpad generic map (tech => padtech, arch => 2) port map (usb_clkout,uclk);
usb_d_pad: iopadv
generic map(tech => padtech, width => 8)
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
usbi(0).datain(7 downto 0));
usb_nxt_pad : inpad generic map (tech => padtech)
port map (usb_nxt, usbi(0).nxt);
usb_dir_pad : inpad generic map (tech => padtech)
port map (usb_dir, usbi(0).dir);
usb_resetn_pad : outpad generic map (tech => padtech)
port map (usb_resetn, usbo(0).reset);
usb_stp_pad : outpad generic map (tech => padtech)
port map (usb_stp, usbo(0).stp);
end generate usbpads;
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
--ulock <= '1';
usb_resetn_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_resetn, '0');
usb_stp_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_stp, '0');
end generate nousb;
-----------------------------------------------------------------------------
-- USB 2.0 Host Controller
-----------------------------------------------------------------------------
usbhc0: if CFG_GRUSBHC = 1 generate
usbhc0 : grusbhc
generic map (
ehchindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 3, ehcpmask => 16#fff#,
uhchindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 4, tech => fabtech,
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
port map (
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1
downto
CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1),
ahbso(8 downto 8),
usbo,usbi);
end generate usbhc0;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 8, hirq => 6, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech, keepclk => 1)
port map(
uclk => uclk,
usbi => usbi(0),
usbo => usbo(0),
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
memtech => memtech, keepclk => 1, uiface => 1)
port map (
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH));
end generate usb_dcl0;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 10, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, hmask => 16#F00#, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 3 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 4 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-4), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
serrx_pad : outpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (led(5), rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (led(6), txd1);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(12), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (level => cmos, voltage => x18v,tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- DYNAMIC PARTIAL RECONFIGURATION ---------------------------------
-----------------------------------------------------------------------
prc : if CFG_PRC = 1 generate
p1 : dprc generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH, pindex => 5, paddr => 5, cfg_clkmul => 4, cfg_clkdiv => 8, raw_freq => BOARD_FREQ, clk_sel => 0,
technology => CFG_FABTECH, crc_en => CFG_CRC_EN, words_block => CFG_WORDS_BLOCK, fifo_dcm_inst => CFG_DCM_FIFO, fifo_depth => CFG_DPR_FIFO)
port map( rstn => rstn, clkm => clkm, clkraw => clkm, clk100 => '0', ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH), apbi => apbi, apbo => apbo(5), rm_reset => open);
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
-- pragma translate_on
test1_gen : if (testahb = false) generate
ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(3));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRUSBDC+CFG_GRUSBHC*2+CFG_GRUSB_DCL+CFG_PRC) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx VC707 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
5d0c84f804e99cbd1e340215bbc85621
| 0.522801 | 3.548621 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/leon3mp.vhd
| 1 | 28,150 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.net.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic; -- Driven const low by MAXV CPLD?
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : inout std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- This has been commented out as some pins have been placed in
-- violation with the Altera diff pad keep-out rules.
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic; -- changed due to placement rule
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic; -- in due to placement rule
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant USE_AHBREP: integer := 0
--pragma translate_off
+1
--pragma translate_on
;
-- Bus indexes
constant hmi_cpu : integer := 0;
constant hmi_greth1 : integer := hmi_cpu + CFG_NCPU;
constant hmi_greth2 : integer := hmi_greth1 + CFG_GRETH;
constant hmi_ahbuart : integer := hmi_greth2 + CFG_GRETH2;
constant hmi_ahbjtag : integer := hmi_ahbuart + CFG_AHB_UART;
constant nahbm : integer := hmi_ahbjtag + CFG_AHB_JTAG;
constant hsi_ssrctrl : integer := 0;
constant hsi_apbctrl : integer := hsi_ssrctrl + (CFG_SSCTRL + CFG_AHBROMEN + 1)/2;
constant hsi_dsu : integer := hsi_apbctrl + 1;
constant hsi_ddr3 : integer := hsi_dsu + CFG_DSU;
constant hsi_lpddr2 : integer := hsi_ddr3 + 1;
constant hsi_ahbrep : integer := hsi_lpddr2 + 1;
constant nahbs : integer := hsi_ahbrep + USE_AHBREP;
constant pi_irqmp : integer := 0;
constant pi_apbuart : integer := pi_irqmp + CFG_IRQ3_ENABLE;
constant pi_gpt : integer := pi_apbuart + CFG_UART1_ENABLE;
constant pi_ahbuart : integer := pi_gpt + CFG_GPT_ENABLE;
constant pi_ssrctrl : integer := pi_ahbuart + CFG_AHB_UART;
constant pi_greth1 : integer := pi_ssrctrl + CFG_SSCTRL;
constant pi_greth2 : integer := pi_greth1 + CFG_GRETH;
constant pi_i2cmst : integer := pi_greth2 + CFG_GRETH2;
constant napbs : integer := pi_i2cmst + CFG_I2C_ENABLE;
constant CPU_FREQ : integer := 75000;
signal clklock: std_ulogic;
signal clkm: std_ulogic;
signal ssclk: std_ulogic;
signal rstn: std_ulogic;
signal ahbmi: ahb_mst_in_type;
signal ahbmo: ahb_mst_out_vector;
signal ahbsi: ahb_slv_in_type;
signal ahbso: ahb_slv_out_vector;
signal apbi: apb_slv_in_type;
signal apbo: apb_slv_out_vector;
signal irqi: irq_in_vector(CFG_NCPU-1 downto 0);
signal irqo: irq_out_vector(CFG_NCPU-1 downto 0);
signal dbgi: l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo: l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui: dsu_in_type;
signal dsuo: dsu_out_type;
signal gpti: gptimer_in_type;
signal sri: memory_in_type;
signal sro: memory_out_type;
signal del_addr: std_logic_vector(26 downto 1);
signal del_ce: std_logic;
signal del_bwe, del_bwa, del_bwb: std_logic_vector(1 downto 0);
signal ui_serial, ui_usb, ui, dui: uart_in_type;
signal uo_serial, uo_usb, uo, duo: uart_out_type;
signal ethi1,ethi2: eth_in_type;
signal etho1,etho2: eth_out_type;
signal i2ci: i2c_in_type;
signal i2co: i2c_out_type;
signal vcc, gnd: std_ulogic;
-- signal logsig: std_logic_vector(31 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- Clocking and reset
-----------------------------------------------------------------------------
user_led(0) <= not clklock;
clkgen0: entity work.clkgen_c5ekit
port map (clkin_50_fpga_right, clkm, open, clklock);
rstgen0: rstgen
generic map (syncrst => CFG_NOASYNC)
port map (cpu_resetn, clkm, clklock, rstn);
-----------------------------------------------------------------------------
-- AMBA bus fabric
-----------------------------------------------------------------------------
ahbctrl0: ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN,ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
enbusmon => CFG_AHB_MON, assertwarn => CFG_AHB_MONWAR,
asserterr => CFG_AHB_MONERR, ahbtrace => CFG_AHB_DTRACE,
nahbm => nahbm, nahbs => nahbs)
port map (rstn,clkm,ahbmi,ahbmo,ahbsi,ahbso);
apbctrl0: apbctrl
generic map (hindex => hsi_apbctrl, haddr => CFG_APBADDR, nslaves => napbs)
port map (rstn,clkm,ahbsi,ahbso(hsi_apbctrl),apbi,apbo);
ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto nahbs) <= (others => ahbs_none);
apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------------
-- LEON3 Processor(s), DSU, timer and IRQ controller
-----------------------------------------------------------------------------
errorn_pad : outpad generic map (tech => padtech) port map (user_led(3), dbgo(0).error);
dsubre_pad : inpad generic map (tech => padtech) port map (user_pb(3), dsui.break);
user_led(2) <= not dsuo.active;
dsui.enable <= '1';
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => hsi_dsu, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(hsi_dsu), dbgo, dbgi, dsui, dsuo);
end generate;
end generate;
noleon: if CFG_LEON3 = 0 generate
irqo <= (others => ('0',"0000",'0','0','0'));
dbgo <= (others => dbgo_none);
end generate;
nodsu : if CFG_DSU = 0 or CFG_LEON3 = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; dsuo.pwd <= (others => '0');
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => pi_irqmp, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(pi_irqmp), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
irqi(i).rst <= '1';
irqi(i).run <= '1';
irqi(i).rstvec <= (others => '0');
irqi(i).iact <= '0';
irqi(i).index <= (others => '0');
irqi(i).hrdrst <= '1';
end generate;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => pi_gpt, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(pi_gpt), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; gpti.wdogen <= '0';
end generate;
-----------------------------------------------------------------------------
-- Debug links
-----------------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => hmi_ahbuart, pindex => pi_ahbuart, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(pi_ahbuart), ahbmi, ahbmo(hmi_ahbuart));
end generate;
nouah : if CFG_AHB_UART = 0 generate
duo.rtsn <= '0'; duo.txd <= '0';
duo.scaler <= (others => '0'); duo.txen <= '0';
duo.flow <= '0'; duo.rxen <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => hmi_ahbjtag, nsync => 2)
port map(rstn, clkm, gnd, gnd, gnd, open, ahbmi, ahbmo(hmi_ahbjtag),
open, open, open, open, open, open, open, gnd);
end generate;
-- EDCL included in Ethernet below
-----------------------------------------------------------------------------
-- Memory controllers
-----------------------------------------------------------------------------
fm_a <= del_addr; -- sro.address(26 downto 1);
-- fm_d_pad: iopadvv
-- generic map (tech => padtech, width => 16)
-- port map (pad => fm_d, i => sro.data(31 downto 16),
-- en => sro.vbdrive(31 downto 16), o => sri.data(31 downto 16));
sri.data(31 downto 16) <= fm_d;
flash_clk <= '0';
flash_resetn <= '1';
flash_cen <= '0'; -- sro.romsn(0);
flash_advn <= '0';
flash_wen <= sro.writen or sro.romsn(0);
flash_oen <= sro.oen or sro.romsn(0);
ssram_clk <= clkm;
ssram_oen <= sro.oen;
sram_cen <= del_ce; -- sro.ramsn(0);
ssram_bwen <= del_bwe(1); -- sro.writen;
ssram_bwan <= del_bwa(1); -- sro.wrn(0);
ssram_bwbn <= del_bwb(1); -- sro.wrn(1);
ssram_adscn <= '1';
ssram_adspn <= '0';
ssram_zzn <= '0';
ssram_advn <= '1';
sri.data(15 downto 0) <= sri.data(31 downto 16);
sri.brdyn <= '1';
sri.bexcn <= '1';
sri.writen <= '1';
sri.wrn <= (others => '1');
sri.bwidth <= "01";
sri.sd <= (others => '0');
sri.cb <= (others => '0');
sri.scb <= (others => '0');
sri.edac <= '0';
delproc: process(clkm)
begin
if rising_edge(clkm) then
del_addr <= sro.address(26 downto 1);
del_ce <= sro.ramsn(0);
del_bwe <= del_bwe(0) & sro.writen;
del_bwa <= del_bwa(0) & sro.wrn(0);
del_bwb <= del_bwb(0) & sro.wrn(1);
end if;
end process;
ssrctrl: if CFG_SSCTRL = 1 generate
ssrctrl0: gaisler.memctrl.ssrctrl
generic map (hindex => hsi_ssrctrl, pindex => pi_ssrctrl,
romaddr => 16#000#, rommask => 16#fc0#,
ioaddr => 0, iomask => 0,
ramaddr => 0, rammask => 0,
bus16 => CFG_SSCTRLP16
)
port map (rstn, clkm, ahbsi, ahbso(hsi_ssrctrl), apbi, apbo(pi_ssrctrl), sri, sro);
end generate;
nossrctrl: if CFG_SSCTRL = 0 generate
sro <= memory_out_none;
end generate;
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SSCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => hsi_ssrctrl, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(hsi_ssrctrl));
end generate;
ddr3if0: entity work.ddr3if
generic map (
hindex => hsi_ddr3,
haddr => 16#400#, hmask => 16#E00#
) port map (
pll_ref_clk => diff_clkin_top_125_p,
global_reset_n => cpu_resetn,
mem_a => ddr3_a,
mem_ba => ddr3_ba,
mem_ck => ddr3_ck_p,
mem_ck_n => ddr3_ck_n,
mem_cke => ddr3_cke,
mem_reset_n => ddr3_rstn,
mem_cs_n => ddr3_csn,
mem_dm => ddr3_dm,
mem_ras_n => ddr3_rasn,
mem_cas_n => ddr3_casn,
mem_we_n => ddr3_wen,
mem_dq => ddr3_dq,
mem_dqs => ddr3_dqs_p,
mem_dqs_n => ddr3_dqs_n,
mem_odt => ddr3_odt,
oct_rzqin => ddr3_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ddr3)
);
lpddr2if0: entity work.lpddr2if
generic map (
hindex => hsi_lpddr2,
haddr => 16#600#, hmask => 16#F00#
) port map (
pll_ref_clk => diff_clkin_bot_125_p,
global_reset_n => cpu_resetn,
mem_ca => lpddr2_a,
mem_ck => lpddr2_ck_p,
mem_ck_n => lpddr2_ck_n,
mem_cke => lpddr2_cke,
mem_cs_n => lpddr2_csn,
mem_dm => lpddr2_dm,
mem_dq => lpddr2_dq,
mem_dqs => lpddr2_dqs_p,
mem_dqs_n => lpddr2_dqs_n,
oct_rzqin => lpddr2_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_lpddr2)
);
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
srx_pad : inpad generic map (tech => padtech) port map (uart_rxd, ui_serial.rxd);
srts_pad : inpad generic map (tech => padtech) port map (uart_rts, ui_serial.ctsn);
stx_pad : outpad generic map (tech => padtech) port map (uart_txd, uo_serial.txd);
scts_pad : outpad generic map (tech => padtech) port map (uart_cts, uo_serial.rtsn);
urx_pad : inpad generic map (tech => padtech) port map (usb_uart_rxd, ui_usb.rxd);
urts_pad : inpad generic map (tech => padtech) port map (usb_uart_rts, ui_usb.ctsn);
utx_pad : outpad generic map (tech => padtech) port map (usb_uart_txd, uo_usb.txd);
ucts_pad : outpad generic map (tech => padtech) port map (usb_uart_cts, uo_usb.rtsn);
usb_uart_dtr <= '0';
ui_serial.extclk <= '0'; ui_usb.extclk <= '0';
-- UART switch
ui <= ui_serial when user_dipsw(0)='0' else ui_usb;
dui <= ui_usb when user_dipsw(0)='0' else ui_serial;
uo_serial <= uo when user_dipsw(0)='0' else duo;
uo_usb <= duo when user_dipsw(0)='0' else uo;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => pi_apbuart, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(pi_apbuart), ui, uo);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate
uo.rtsn <= '0'; uo.txd <= '0'; uo.scaler <= (others => '0');
uo.txen <= '0'; uo.flow <= '0'; uo.rxen <= '0';
end generate;
-- AHBUART, see under Debug links above
-----------------------------------------------------------------------------
-- Ethernet
-----------------------------------------------------------------------------
emdio_pad : iopad generic map (tech => padtech)
port map (eneta_mdio, etho1.mdio_o, etho1.mdio_oe, ethi1.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_tx_clk, ethi1.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_rx_clk, ethi1.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (eneta_rx_d, ethi1.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (eneta_rx_dv, ethi1.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (eneta_rx_er, ethi1.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eneta_rx_col, ethi1.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eneta_rx_crs, ethi1.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (eneta_intn, ethi1.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (eneta_tx_d, etho1.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (eneta_tx_en, etho1.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (eneta_tx_er, etho1.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (eneta_mdc, etho1.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eneta_resetn, rstn);
ethi1.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi1.gtx_clk <= '0'; ethi1.rmii_clk <= '0';
emdio_pad2 : iopad generic map (tech => padtech)
port map (enetb_mdio, etho2.mdio_o, etho2.mdio_oe, ethi2.mdio_i);
etxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_tx_clk, ethi2.tx_clk);
erxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_rx_clk, ethi2.rx_clk);
erxd_pad2 : inpadv generic map (tech => padtech, width => 4)
port map (enetb_rx_d, ethi2.rxd(3 downto 0));
erxdv_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_dv, ethi2.rx_dv);
erxer_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_er, ethi2.rx_er);
erxco_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_col, ethi2.rx_col);
erxcr_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_crs, ethi2.rx_crs);
emdint_pad2 : inpad generic map (tech => padtech)
port map (enetb_intn, ethi2.mdint);
etxd_pad2 : outpadv generic map (tech => padtech, width => 4)
port map (enetb_tx_d, etho2.txd(3 downto 0));
etxen_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_en, etho2.tx_en);
etxer_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_er, etho2.tx_er);
emdc_pad2 : outpad generic map (tech => padtech)
port map (enetb_mdc, etho2.mdc);
erst_pad2 : outpad generic map (tech => padtech)
port map (enetb_resetn, rstn);
ethi2.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi2.gtx_clk <= '0'; ethi2.rmii_clk <= '0';
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => hmi_greth1,
pindex => pi_greth1, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 0,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth1),
apbi => apbi, apbo => apbo(pi_greth1), ethi => ethi1, etho => etho1);
end generate;
noeth1 : if CFG_GRETH = 0 generate
etho1 <= eth_out_none;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Secondary ethernet MAC
e2 : grethm generic map(hindex => hmi_greth2,
pindex => pi_greth2, paddr => 12, pirq => 13, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth2),
apbi => apbi, apbo => apbo(pi_greth2), ethi => ethi2, etho => etho2);
end generate;
noeth2 : if CFG_GRETH2 = 0 generate
etho2 <= eth_out_none;
end generate;
-----------------------------------------------------------------------------
-- GPIO
-----------------------------------------------------------------------------
-- TO DO
-----------------------------------------------------------------------------
-- Other
-----------------------------------------------------------------------------
max5_csn <= '1';
sclpad: iopad generic map (tech => padtech) port map (eeprom_scl, i2co.scl, i2co.scloen, i2ci.scl);
sdapad: iopad generic map (tech => padtech) port map (eeprom_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
i2c: if CFG_I2C_ENABLE=1 generate
i2cmst0: i2cmst
generic map (pindex => pi_i2cmst, paddr => 4, pmask => 16#FFF#, pirq => 4)
port map (rstn,clkm,apbi,apbo(pi_i2cmst),i2ci,i2co);
end generate;
noi2c: if CFG_I2C_ENABLE=0 generate
i2co <= (others => '1');
end generate;
-- logan0: logan
-- generic map (pindex => napbs-1, paddr => 16#100#, memtech => memtech)
-- port map (rstn, clkm, clkm, apbi, apbo(napbs-1), logsig);
--
-- logsig(31 downto 6) <= (others => '0');
-- logsig(5 downto 0) <= i2co.scl & i2co.scloen & i2ci.scl & i2co.sda & i2co.sdaoen & i2ci.sda;
-- pragma translate_off
rep: if USE_AHBREP/=0 generate
ahbrep0: ahbrep
generic map (hindex => hsi_ahbrep, haddr => 16#200#)
port map (rstn,clkm,ahbsi,ahbso(hsi_ahbrep));
end generate;
x : report_version
generic map (
msg1 => "LEON3 Altera CycloneV E Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
bb5a1b8cd4004ddc8583e2eafa7882d6
| 0.571972 | 3.328604 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/inpad_ds.vhd
| 1 | 3,865 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ds
-- File: inpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (tech = virtex2) or (tech = spartan3) generate
u0 : unisim_inpad_ds generic map (level, voltage, term) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) or (tech = spartan6)
or (tech = virtex6) or (tech = virtex7) or (tech = kintex7) or (tech =artix7) or (tech =zynq7000) generate
u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
igl2 : if (tech = igloo2) generate
u0 : igloo2_inpad_ds port map (padp, padn, o);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpad_dsv is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; term : integer := 0);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpad_dsv is
begin
v : for i in width-1 downto 0 generate
u0 : inpad_ds generic map (tech, level, voltage, term) port map (padp(i), padn(i), o(i));
end generate;
end;
|
gpl-2.0
|
3d8d9acec92852fc6282fb72f3eeabda
| 0.635188 | 3.463262 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/grlfpwx.vhd
| 1 | 4,548 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpwx
-- File: grlfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
entity grlfpwx is
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0;
index : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of grlfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
begin
x1 : if true generate
grlfpw0 : grlfpw_net generic map (tech, pclow, dsu, disas, pipe)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2,
testin
);
rf2 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2,
testin
);
end;
|
gpl-2.0
|
88c64ecd11831c85f90e01d4676b99e5
| 0.494063 | 3.471756 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/lvds_combo.vhd
| 1 | 3,917 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: lvds_combo.vhd
-- File: lvds_combo.vhd.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential input/output pads with IREF/OREF logic wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1) := (others => '0');
powerdownrx : in std_logic_vector(0 to width-1) := (others => '0');
lvdsref : in std_logic := '1';
lvdsrefo : out std_logic
);
end ;
architecture rtl of lvds_combo is
signal gnd : std_ulogic;
signal oen : std_logic_vector(0 to width-1);
constant level : integer := lvds;
begin
gnd <= '0';
gen0 : if has_ds_combo(tech) = 0 generate
swloop : for i in 0 to width-1 generate
od0 : outpad_ds generic map (tech, level, voltage, oepol) port map (odpadp(i), odpadn(i), odval(i), en(i));
os0 : outpad_ds generic map (tech, level, voltage, oepol) port map (ospadp(i), ospadn(i), osval(i), en(i));
id0 : inpad_ds generic map (tech, level, voltage) port map (idpadp(i), idpadn(i), idval(i));
is0 : inpad_ds generic map (tech, level, voltage) port map (ispadp(i), ispadn(i), isval(i));
end generate;
end generate;
combo : if has_ds_combo(tech) /= 0 generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
ut025 : if tech = ut25 generate
u0: ut025crh_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval);
end generate;
ut13 : if tech = ut130 generate
u0: ut130hbd_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo);
end generate;
um : if tech = umc generate
u0: umc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref);
end generate;
rhu : if tech = rhumc generate
u0: rhumc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo);
end generate;
end generate;
end;
|
gpl-2.0
|
76fccc001668bcf7e7f37022b3b380fe
| 0.634159 | 3.698772 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/xnor00.vhd
| 1 | 1,399 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity xnor00 is
port(
clkxnr: in std_logic ;
codopxnr: in std_logic_vector ( 3 downto 0 );
portAxnr: in std_logic_vector ( 7 downto 0 );
portBxnr: in std_logic_vector ( 7 downto 0 );
inFlagxnr: in std_logic;
outxnr: out std_logic_vector ( 7 downto 0 );
outFlagxnr: out std_logic );
end;
architecture xnor0 of xnor00 is
begin
pxnor: process(codopxnr, portAxnr, portBxnr)
begin
if(codopxnr = "0110") then
outxnr <= portAxnr xnor portBxnr;
outFlagxnr <= '1';
else
outxnr <= (others => 'Z');
outFlagxnr <= 'Z';
end if;
end process pxnor;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end xnor0;
|
apache-2.0
|
d7a1414ae400d4aa13c5462a6c400843
| 0.50965 | 3.074725 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/system_monitor.vhd
| 1 | 13,179 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: system_monitor
-- File: system_monitor.vhd
-- Author: Jan Andersson, Jiri Gaisler - Gaisler Research
-- Description: System monitor wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity system_monitor is
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end system_monitor;
architecture struct of system_monitor is
component sysmon_virtex5
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component sysmon
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_DEVICE : string := "VIRTEX5";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
begin -- struct
gen: if not ((tech = virtex5) or (tech = virtex6) or (tech = virtex7) or (tech = kintex7)) generate
alm <= (others => '0');
busy <= '0';
channel <= (others => '0');
do <= (others => '0');
drdy <= '0';
eoc <= '0';
eos <= '0';
jtagbusy <= '0';
jtaglocked <= '0';
jtagmodified <= '0';
ot <= '0';
end generate gen;
v5: if tech = virtex5 generate
v50 : sysmon_virtex5
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v5;
v6: if tech = virtex6 generate
v60 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v6;
v7: if tech = virtex7 generate
v70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v7;
k7: if tech = kintex7 generate
k70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "KINTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate k7;
end struct;
|
gpl-2.0
|
6986db99345d3c2dd0ac1ba074d06812
| 0.504591 | 3.499469 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/iodpad.vhd
| 1 | 5,253 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_iopad port map (pad, gnd, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (strength) port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
|
gpl-2.0
|
dab435735b03fc9367ba853b2b767fca
| 0.628212 | 3.490365 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/core/greth_tx.vhd
| 1 | 17,540 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
--attribute sync_set_reset : string;
attribute sync_set_reset of txrst : signal is "true";
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
gmiimode0 : if gmiimode = 0 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
if (txi.datavalid = '1' or txrst = '0') then r <= rin; end if;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
if txi.datavalid = '1' then
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end if;
end process;
end generate;
end architecture;
|
gpl-2.0
|
0fe99b28b109516157f833ca032c38f4
| 0.517161 | 3.204238 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-kc705/leon3mp.vhd
| 1 | 44,294 |
-----------------------------------------------------------------------------
-- LEON3 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.l2cache.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ahb2mig_7series
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
-- pragma translate_off
component ahbram_sim
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component ;
-- pragma translate_on
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
----- component STARTUPE2 -----
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := 16;
--constant maxahbs : integer := 1+CFG_DSU+CFG_MCTRL_LEON2+CFG_AHBROMEN+CFG_AHBRAMEN+2;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal ui_clk : std_ulogic;
signal clkm : std_ulogic := '0';
signal rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal sgmiii : eth_sgmii_in_type;
signal sgmiio : eth_sgmii_out_type;
signal sgmiirst : std_logic;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal clkref : std_logic;
signal migrstn : std_logic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen0 : if (CFG_MIG_7SERIES = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(1), dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (button(0), dsui.break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(3), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 and CFG_SPIMCTRL = 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 26, tech => padtech, level => cmos, voltage => x25v)
port map (address(25 downto 0), memo.address(26 downto 1));
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (oen, memo.oen);
adv_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (adv, '0');
wri_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPIMCTRL = 1 and CFG_MCTRL_LEON2 = 0 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 0, hirq => 1, faddr => 16#100#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (data(1), spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (data(0), spmo.mosi);
slvsel0_pad : odpad generic map (tech => padtech)
port map (romsn, spmo.csn);
-- To output SPI clock use Xilinx STARTUPE2 primitive
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE",
SIM_CCLK_FREQ => 10.0
)
port map (
CFGCLK => open ,
CFGMCLK => open ,
EOS => open ,
PREQ => open ,
CLK => '0',
GSR => '0',
GTS => '0',
KEYCLEARB => '0',
PACK => '0',
USRCCLKO => spmo.sck,
USRCCLKTS => '0',
USRDONEO => '1',
USRDONETS => '1'
);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
nomctrl : if CFG_MCTRL_LEON2 = 0 and CFG_SPIMCTRL = 0 generate
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
mctrl_error_gen : if CFG_MCTRL_LEON2 /= 0 and CFG_SPIMCTRL = 1 generate
x : process
begin
assert false
report "Xilins KC705 Ref design do not support Quad SPI Flash Memory and Linear BPI flash memory at the same time"
severity failure;
wait;
end process;
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
l2cdis : if CFG_L2_EN = 0 generate
mig_gen : if (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series generic map(
hindex => 4, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 4,
haddr => 16#400#,
hmask => 16#C00#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4)
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 5.0 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model; end generate;
no_mig_gen : if (CFG_MIG_7SERIES = 0) generate
ahbram0 : ahbram
generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 128)
port map ( rstn, clkm, ahbsi, ahbso(4));
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate no_mig_gen;
end generate l2cdis;
-----------------------------------------------------------------------------
-- L2 cache covering DDR3 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2c0 : l2c
generic map(hslvidx => 4, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(4),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 1)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
--mig_gen : if (CFG_MIG_7SERIES = 1) generate
-- gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series
generic map(hindex => 0, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n, ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n, ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt,
ahbsi => mem_ahbsi, ahbso => mem_ahbso(0), apbi => apbi, apbo => apbo(4),
calib_done => calib_done, rst_n_syn => migrstn, rst_n_async => rstraw,
clk_amba => clkm, sys_clk_p => clk200p, sys_clk_n => clk200n, clk_ref_i => clkref,
ui_clk => clkm, ui_clk_sync_rst => open);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
-- end generate gen_mig;
--end generate mig_gen;
end generate l2cen;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(3), lock);
led4_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (led(4), ahbso(4).hready);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 3, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 0, gmiimode => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => io_ref,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (rst, io_ref, lock, rstgtxn, OPEN);
process (io_ref,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(io_ref) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 1,
pirq => 11, use90degtxclk => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_gtxclk, rgmiio.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_int, rgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rgmiio.reset);
-- GTX Clock
rgmiii.gtx_clk <= gtx_clk;
-- 125MHz input clock
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => gtrefclk_p,
IB => gtrefclk_n,
CEB => '0',
O => gtx_clk_nobuf,
ODIV2 => open
);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_gtrefclk : clkgen
generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000)
port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, rgmiii.tx_clk_90, io_ref, open, open, cgi2, cgo2, open, open, open);
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 4, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 2 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 3 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (button(i-2), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
serrx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(5), rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(6), txd1);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
-- pragma translate_on
test1_gen : if (testahb = false) generate
ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(3));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx KC705 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
57d201ebb60a5428d0065ff60edb9760
| 0.52068 | 3.59092 | false | false | false | false |
ECE492W2014G4/G4Capstone
|
distortion_component.vhd
| 1 | 4,165 |
-- Design unit: distortion_component
-- Authors : Aaron Arnason, Byron Maroney, Edrick De Guzman
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity distort is
port(
clk : in std_logic;
reset : in std_logic;
dist_en : in std_logic; -- 1-bit distortion enable signal
ready : in std_logic;
done : out std_logic;
data_in : in std_logic_vector(15 downto 0); -- 16-bit data stream input
clipping_write : in std_logic;
clipping_read : in std_logic;
clipping_value: in std_logic_vector(15 downto 0); -- 16-bit input clipping threshold
clipping_readdata: out std_logic_vector(15 downto 0);
data_out: out std_logic_vector(15 downto 0) -- 16-bit data stream output (either clipped or not)
);
end entity distort;
architecture behavior of distort is
constant clipping_default : std_logic_vector(15 downto 0) := "0000101110111000"; -- constant value of 3000 in decimal
constant clipping_high : std_logic_vector(15 downto 0) := "0000000001100100"; -- constant value of 1000 in decimal
constant clipping_low : std_logic_vector(15 downto 0) := "0000001111101000"; -- constant value of 5000 in decimal
constant clipping_inc : std_logic_vector(15 downto 0) := X"01F4";
signal gain_constant : std_logic_vector(2 downto 0) := "001"; -- constant gain: default at 1
signal clip_threshold,clip_sample : std_logic_vector(15 downto 0);
signal completed : std_logic :='0';
signal counter: unsigned(15 downto 0);
begin
clipping_readdata <= clip_threshold;
done <= completed;
c1: process(clk,clipping_write)
begin
if rising_edge(clk) then
if dist_en = '1' then
if clipping_write = '0' then -- Active Low
clip_sample <= clipping_value;
else
case clip_sample is
when X"0001" =>
clip_threshold <= X"0BB8"; -- Level: 1 - 3000
gain_constant <= "001"; -- Gain: 1
when X"0002" =>
clip_threshold <= X"076C"; -- Level: 2 - 1900
gain_constant <= "010"; -- Gain: 2
when X"0003" =>
clip_threshold <= X"0514"; -- Level: 3 - 1300
gain_constant <= "010"; -- Gain: 2
when X"0004" =>
clip_threshold <= X"02BC"; -- Level: 4 - 700
gain_constant <= "011"; -- Gain: 3
when X"0005" =>
clip_threshold <= X"012C"; -- Level: 5 - 300
gain_constant <= "111"; -- Gain: 5
when others =>
clip_threshold <= X"012C"; -- Level: X - 300
gain_constant <= "111";
end case;
end if;
end if;
end if;
end process;
g0:process(clk,reset,dist_en,ready)
variable mult_result : std_logic_vector(18 downto 0);
begin
if reset = '0' then
data_out <= X"0000";
elsif (rising_edge(clk)) then
if(ready = '1') then
-- End Clipping Configurations
if dist_en = '1' then -- Check if Distortion is Enabled
if data_in(15) = '1' then -- Check sign of sample (If negative...)
if (not data_in(14 downto 0)) >= clip_threshold(14 downto 0) then -- compare data to clip_threshold (without sign bits)
mult_result := gain_constant * clip_threshold;
data_out <= '1' & (not mult_result(14 downto 0));
--data_out <= '1' & (not clip_threshold(14 downto 0)); -- if data is greater than threshold, data_out = clip_threshold, concatenate '1' to complement
else
mult_result := gain_constant * data_in;
data_out <= mult_result(15 downto 0);
--data_out <= data_in;
end if;
elsif data_in(15) = '0' then -- Check sign of sample (If positive...)
if data_in(14 downto 0) >= clip_threshold(14 downto 0) then
mult_result := gain_constant * clip_threshold;
data_out <= '0' & mult_result(14 downto 0);
--data_out <= '0' & clip_threshold(14 downto 0);
else
mult_result := gain_constant * data_in;
data_out <= mult_result(15 downto 0);
--data_out <= data_in;
end if;
end if;
else
data_out <= data_in;
end if;
completed <= '1';
else
completed <= '0';
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
ea657c13a7b982d295c1833318d2746b
| 0.608884 | 3.251366 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/mul_61x61.vhd
| 1 | 4,220 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul_61x61
-- File: mul_61x61.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity mul_61x61 is
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of mul_61x61 is
component dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component axcel_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex4_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex6_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component kintex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
begin
gen0 : if multech = 0 generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
dw0 : if multech = 1 generate
mul0 : dw_mul_61x61 port map (A, B, CLK, PRODUCT);
end generate;
tech0 : if multech = 3 generate
axd0 : if fabtech = axdsp generate
mul0 : axcel_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc5v : if fabtech = virtex5 generate
mul0 : virtex4_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc6v : if fabtech = virtex6 generate
mul0 : virtex6_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
gen0 : if not ((fabtech = axdsp) or (fabtech = virtex5) or (fabtech = virtex6)) generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
end generate;
end;
|
gpl-2.0
|
da78241be96c9490b54e0a29f5178fdb
| 0.611137 | 3.467543 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/adapters/rgmii.vhd
| 1 | 31,492 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rgmii
-- File: rgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to RGMII interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library eth;
use eth.grethpkg.all;
entity rgmii is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
tech : integer := 0;
gmii : integer := 0;
debugmem : integer := 0;
abits : integer := 8;
no_clk_mux : integer := 0;
pirq : integer := 0;
use90degtxclk : integer := 0
);
port (
rstn : in std_ulogic;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
rgmiii : in eth_in_type;
rgmiio : out eth_out_type;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end ;
architecture rtl of rgmii is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_RGMII, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type status_vector_type is array(1 downto 0) of std_logic_vector(15 downto 0);
type rgmiiregs is record
clk25_wrap : unsigned(5 downto 0);
clk25_first_edge : unsigned(5 downto 0);
clk25_second_edge : unsigned(5 downto 0);
clk2_5_wrap : unsigned(5 downto 0);
clk2_5_first_edge : unsigned(5 downto 0);
clk2_5_second_edge : unsigned(5 downto 0);
irq : std_logic_vector(15 downto 0); -- interrupt
mask : std_logic_vector(15 downto 0); -- interrupt enable
clkedge : std_logic_vector(23 downto 0);
rxctrl_q1_delay : std_logic_vector(1 downto 0);
rxctrl_q2_delay : std_logic_vector(1 downto 0);
rxctrl_q1_sel : std_logic;
rxctrl_delay : std_logic;
rxctrl_c_delay : std_logic;
status_vector : status_vector_type;
end record;
-- Global signal
signal vcc, gnd : std_ulogic;
signal tx_en, tx_ctl : std_ulogic;
signal txd : std_logic_vector(7 downto 0);
signal rxd, rxd_pre, rxd_int, rxd_int0, rxd_int1, rxd_int2,rxd_q1,rxd_q2 : std_logic_vector(7 downto 0);
signal rx_clk, nrx_clk : std_ulogic;
signal rx_dv, rx_dv_pre, rx_dv_int, rx_dv0 , rx_ctl, rx_ctl_pre, rx_ctl_int, rx_ctl0, rx_error : std_logic;
signal rx_dv_int0, rx_dv_int1, rx_dv_int2 : std_logic;
signal rx_ctl_int0, rx_ctl_int1, rx_ctl_int2 : std_logic;
signal clk25i, clk25ni, clk2_5i, clk2_5ni : std_ulogic;
signal txp, txn, txp_sync, txn_sync, tx_clk_ddr, tx_clk, tx_clki, ntx_clk : std_ulogic;
signal cnt2_5, cnt25 : unsigned(5 downto 0);
signal rsttxclkn,rsttxclk,rsttxclk90n,rsttxclk90 : std_logic;
-- RGMII Inband status signals
signal inbandopt,inbandreq : std_logic;
signal link_status : std_logic;
signal clock_speed : std_logic_vector(1 downto 0);
signal duplex_status : std_logic;
signal false_carrier_ind : std_logic;
signal carrier_ext : std_logic;
signal carrier_ext_error : std_logic;
signal carrier_sense : std_logic;
-- Status signals and Clock domain crossing
signal line_status_vector : std_logic_vector(3 downto 0);
signal status_vector : std_logic_vector(15 downto 0);
signal status_vector_sync : std_logic_vector(15 downto 0);
-- APB and RGMII control register
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
-- notech default settings
constant RES : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '0', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Kintex7 settings for KC705 Dev Board
constant RES_kintex7 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Spartan6 settings for GR-XC6 Dev Board
constant RES_spartan6 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => "01", rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Artix7 settings for AC701 Dev Board
constant RES_artix7 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '1', status_vector => (others => (others => '0')) );
signal r, rin : rgmiiregs;
signal clk_tx_90_n : std_logic;
signal sync_gbit : std_logic;
signal sync_speed : std_logic;
signal cnt2_5_en, cnt25_en : std_logic;
signal clkedge_sync : std_logic_vector(23 downto 0);
signal sync_rxctrl_q1_delay : std_logic_vector(1 downto 0);
signal sync_rxctrl_q2_delay : std_logic_vector(1 downto 0);
signal sync_rxctrl_q1_sel : std_logic;
signal sync_rxctrl_delay : std_logic;
signal sync_rxctrl_c_delay : std_logic;
signal cnt_en : std_logic;
signal clk10_100 : std_logic;
signal clk25_wrap_sync : unsigned(5 downto 0);
signal clk25_first_edge_sync : unsigned(5 downto 0);
signal clk25_second_edge_sync : unsigned(5 downto 0);
signal clk2_5_wrap_sync : unsigned(5 downto 0);
signal clk2_5_first_edge_sync : unsigned(5 downto 0);
signal clk2_5_second_edge_sync : unsigned(5 downto 0);
-- debug signal
signal WMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioWrEn : std_logic;
signal WMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiWrEn : std_logic;
signal RMemRgmiiiRead : std_logic;
signal RMemRgmiioRead : std_logic;
begin -- rtl
vcc <= '1'; gnd <= '0';
---------------------------------------------------------------------------------------
-- MDIO path
---------------------------------------------------------------------------------------
gmiii.mdint <= rgmiii.mdint;
gmiii.mdio_i <= rgmiii.mdio_i;
rgmiio.mdio_o <= gmiio.mdio_o;
rgmiio.mdio_oe <= gmiio.mdio_oe;
rgmiio.mdc <= gmiio.mdc;
---------------------------------------------------------------------------------------
-- TX path
---------------------------------------------------------------------------------------
useclkmux0 : if no_clk_mux = 0 generate
process (apb_clk)
begin -- process
if rising_edge(apb_clk) then
clk25i <= not clk25i;
if cnt2_5 = "001001" then cnt2_5 <= "000000"; clk2_5i <= not clk2_5i;
else cnt2_5 <= cnt2_5 + 1; end if;
if apb_rstn = '0' then clk25i <= '0'; clk2_5i <= '0'; cnt2_5 <= "000000"; end if;
end if;
end process;
notecclkmux : if (has_clkmux(tech) = 0) generate
tx_clki <= rgmiii.gtx_clk when ((gmii = 1) and (gmiio.gbit = '1')) else
clk25i when gmiio.speed = '1' else clk2_5i;
end generate;
tecclkmux : if (has_clkmux(tech) = 1) generate
-- Select 2.5 or 25 Mhz clockL
clkmux10_100 : clkmux generic map (tech => tech) port map (clk2_5i,clk25i,gmiio.speed,clk10_100);
clkmux1000 : clkmux generic map (tech => tech) port map (clk10_100,rgmiii.gtx_clk,gmiio.gbit,tx_clki);
end generate;
clkbuf0: techbuf generic map (buftype => 2, tech => tech)
port map (i => tx_clki, o => tx_clk);
end generate;
noclkmux0 : if no_clk_mux = 1 generate
-- Generate transmit clocks.
tx_clk <= rgmiii.gtx_clk;
-- CDC
syncreg7 : syncreg port map (tx_clk, gmiio.gbit , sync_gbit );
syncreg8 : syncreg port map (tx_clk, gmiio.speed, sync_speed );
syncreg_clkedge : for i in 0 to r.clkedge'length-1 generate
syncreg9 : syncreg port map (tx_clk, r.clkedge(i), clkedge_sync(i));
end generate;
syncreg_clk25_wrap_sync : for i in 0 to r.clk25_wrap'length-1 generate
syncreg_clk25_wrap_sync : syncreg port map (tx_clk, r.clk25_wrap(i), clk25_wrap_sync(i));
end generate;
syncreg_clk25_first_edge : for i in 0 to r.clk25_first_edge'length-1 generate
syncreg_clk25_first_edge : syncreg port map (tx_clk, r.clk25_first_edge(i), clk25_first_edge_sync(i));
end generate;
syncreg_clk25_second_edge : for i in 0 to r.clk25_second_edge'length-1 generate
syncreg_clk25_second_edge : syncreg port map (tx_clk, r.clk25_second_edge(i), clk25_second_edge_sync(i));
end generate;
syncreg_clk2_5_wrap_sync : for i in 0 to r.clk2_5_wrap'length-1 generate
syncreg_clk2_5_wrap_sync : syncreg port map (tx_clk, r.clk2_5_wrap(i), clk2_5_wrap_sync(i));
end generate;
syncreg_clk2_5_first_edge : for i in 0 to r.clk2_5_first_edge'length-1 generate
syncreg_clk2_5_first_edge : syncreg port map (tx_clk, r.clk2_5_first_edge(i), clk2_5_first_edge_sync(i));
end generate;
syncreg_clk2_5_second_edge : for i in 0 to r.clk2_5_second_edge'length-1 generate
syncreg_clk2_5_second_edge : syncreg port map (tx_clk, r.clk2_5_second_edge(i), clk2_5_second_edge_sync(i));
end generate;
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
if cnt25 >= clk25_wrap_sync then
cnt25 <= to_unsigned(0,cnt25'length);
cnt25_en <= '1';
else
cnt25_en <= '0';
cnt25 <= cnt25 + 1;
end if;
if (cnt25 >= clk25_wrap_sync) then
clk25ni <= clkedge_sync(0);
clk25i <= clkedge_sync(1);
elsif (cnt25 = clk25_first_edge_sync) then
clk25ni <= clkedge_sync(2);
clk25i <= clkedge_sync(3);
elsif (cnt25 = clk25_second_edge_sync) then
clk25ni <= clkedge_sync(4);
clk25i <= clkedge_sync(5);
end if;
if cnt2_5 >= clk2_5_wrap_sync then
cnt2_5 <= to_unsigned(0,cnt2_5'length);
cnt2_5_en <= '1';
else
cnt2_5 <= cnt2_5 + 1;
cnt2_5_en <= '0';
end if;
if (cnt2_5 >= clk2_5_wrap_sync) then
clk2_5ni <= clkedge_sync(8);
clk2_5i <= clkedge_sync(9);
elsif (cnt25 = clk2_5_first_edge_sync) then
clk2_5ni <= clkedge_sync(10);
clk2_5i <= clkedge_sync(11);
elsif (cnt2_5 = clk2_5_second_edge_sync) then
clk2_5ni <= clkedge_sync(12);
clk2_5i <= clkedge_sync(13);
end if;
if rsttxclkn = '0' then
cnt2_5_en <= '0'; cnt25_en <= '0'; clk25i <= '0'; clk25ni <= '0';
clk2_5i <= '0'; clk2_5ni <= '0'; cnt2_5 <= to_unsigned(0,cnt2_5'length);
cnt25 <= to_unsigned(0,cnt25'length);
end if;
end if;
end process;
end generate;
ntx_clk <= not tx_clk;
gmiii.gtx_clk <= tx_clk;
gmiii.tx_clk <= tx_clk;
noclkmux1 : if no_clk_mux = 1 generate
cnt_en <= '1' when ((gmii = 1) and (sync_gbit = '1')) else
cnt25_en when sync_speed = '1' else cnt2_5_en;
end generate;
useclkmux1 : if no_clk_mux = 0 generate
cnt_en <= '1';
end generate;
gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1';
-- Generate RGMII control signal and check data rate
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
if (gmii = 1) and (sync_gbit = '1') then
txd(7 downto 0) <= gmiio.txd(7 downto 0);
else
txd(3 downto 0) <= gmiio.txd(3 downto 0);
txd(7 downto 4) <= gmiio.txd(3 downto 0);
end if;
tx_en <= gmiio.tx_en;
tx_ctl <= gmiio.tx_en xor gmiio.tx_er;
end if;
if (gmii = 1) and (sync_gbit = '1') then
txp <= clkedge_sync(17);
txn <= clkedge_sync(16);
else
if sync_speed = '1' then
txp <= clk25ni;
txn <= clk25i;
else
txp <= clk2_5ni;
txn <= clk2_5i;
end if;
end if;
end process;
clk_tx_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(rstn, tx_clk, vcc, rsttxclkn, open);
rsttxclk <= not rsttxclkn;
-- DDR outputs
rgmii_txd : for i in 0 to 3 generate
ddr_oreg0 : ddr_oreg generic map (tech, arch => 1)
port map (q => rgmiio.txd(i), c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => txd(i), d2 => txd(i+4), r => rsttxclk, s => gnd);
end generate;
rgmii_tx_ctl : ddr_oreg generic map (tech, arch => 1)
port map (q => rgmiio.tx_en, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => tx_en, d2 => tx_ctl, r => rsttxclk, s => gnd);
no_clk_mux1 : if no_clk_mux = 1 generate
use90degtxclk1 : if use90degtxclk = 1 generate
clk_tx90_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(rstn, rgmiii.tx_clk_90, vcc, rsttxclk90n, open);
rsttxclk90 <= not rsttxclk90n;
clk_tx_90_n <= not rgmiii.tx_clk_90;
syncreg_txp : syncreg port map (rgmiii.tx_clk_90, txp, txp_sync);
syncreg_txn : syncreg port map (rgmiii.tx_clk_90, txn, txn_sync);
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => rgmiii.tx_clk_90, c2 => clk_tx_90_n, ce => vcc,
d1 => txp_sync, d2 => txn_sync, r => rsttxclk90, s => gnd);
end generate;
use90degtxclk0 : if use90degtxclk = 0 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => txp, d2 => txn, r => rsttxclk, s => gnd);
end generate;
end generate;
no_clk_mux0 : if no_clk_mux = 0 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => '1', d2 => '0', r => rsttxclk, s => gnd);
end generate;
rgmiio.tx_er <= '0';
rgmiio.tx_clk <= tx_clk_ddr;
rgmiio.reset <= rstn;
rgmiio.gbit <= gmiio.gbit;
rgmiio.speed <= gmiio.speed when (gmii = 1) else '0';
-- Not used in RGMII mode
rgmiio.txd(7 downto 4) <= (others => '0');
---------------------------------------------------------------------------------------
-- RX path
---------------------------------------------------------------------------------------
-- CDC (RX Control signal)
syncreg_q1_delay : for i in 0 to r.rxctrl_q1_delay'length-1 generate
syncreg0 : syncreg port map (rx_clk, r.rxctrl_q1_delay(i), sync_rxctrl_q1_delay(i));
end generate;
syncreg_q2_delay : for i in 0 to r.rxctrl_q2_delay'length-1 generate
syncreg1 : syncreg port map (rx_clk, r.rxctrl_q2_delay(i) , sync_rxctrl_q2_delay(i));
end generate;
syncreg_q1_sel : syncreg port map (rx_clk, r.rxctrl_q1_sel, sync_rxctrl_q1_sel);
syncreg_delay_sel : syncreg port map (rx_clk, r.rxctrl_delay, sync_rxctrl_delay);
syncreg_delay_c_sel : syncreg port map (rx_clk, r.rxctrl_c_delay, sync_rxctrl_c_delay);
-- Rx Clocks
rx_clk <= rgmiii.rx_clk;
nrx_clk <= not rgmiii.rx_clk;
-- DDR inputs
rgmii_rxd : for i in 0 to 3 generate
ddr_ireg0 : ddr_ireg generic map (tech, arch => 1)
port map (q1 => rxd_pre(i), q2 => rxd_pre(i+4), c1 => rx_clk, c2 => nrx_clk,
ce => vcc, d => rgmiii.rxd(i), r => gnd, s => gnd);
process (rx_clk)
begin
if rising_edge(rx_clk) then
rxd_int <= rxd_pre;
rxd_int0(i) <= rxd_int(i);
rxd_int0(i+4) <= rxd_int(i+4);
rxd_int1(i) <= rxd_int0(i);
rxd_int1(i+4) <= rxd_int0(i+4);
rxd_int2(i) <= rxd_int1(i);
rxd_int2(i+4) <= rxd_int1(i+4);
end if;
end process;
end generate;
rgmii_rxd0 : for i in 0 to 3 generate
process (rx_clk)
begin
if (sync_rxctrl_q1_delay = "00") then
if (sync_rxctrl_delay = '1') then
rxd_q1(i) <= rxd_int(i+4);
else
rxd_q1(i) <= rxd_int(i);
end if;
elsif (sync_rxctrl_q1_delay = "01") then
rxd_q1(i) <= rxd_int0(i);
elsif (sync_rxctrl_q1_delay = "10") then
rxd_q1(i) <= rxd_int1(i);
else
rxd_q1(i) <= rxd_int2(i);
end if;
end process;
end generate;
rgmii_rxd1 : for i in 4 to 7 generate
process (rx_clk)
begin
if (sync_rxctrl_q2_delay = "00") then
if (sync_rxctrl_delay = '1') then
rxd_q2(i) <= rxd_int0(i-4);
else
rxd_q2(i) <= rxd_int(i);
end if;
elsif (sync_rxctrl_q2_delay = "01") then
rxd_q2(i) <= rxd_int0(i);
elsif (sync_rxctrl_q2_delay = "10") then
rxd_q2(i) <= rxd_int1(i);
else
rxd_q2(i) <= rxd_int2(i);
end if;
end process;
end generate;
rxd(3 downto 0) <= rxd_q1(3 downto 0) when (sync_rxctrl_q1_sel = '0') else rxd_q2(7 downto 4);
rxd(7 downto 4) <= rxd_q2(7 downto 4) when (sync_rxctrl_q1_sel = '0') else rxd_q1(3 downto 0);
ddr_dv0 : ddr_ireg generic map (tech, arch => 1)
port map (q1 => rx_dv_pre, q2 => rx_ctl_pre, c1 => rx_clk, c2 => nrx_clk,
ce => vcc, d => rgmiii.rx_dv, r => gnd, s => gnd);
process (rx_clk)
begin
if rising_edge(rx_clk) then
rx_ctl_int <= rx_ctl_pre;
rx_dv_int <= rx_dv_pre;
rx_ctl_int0 <= rx_ctl_int;
rx_ctl_int1 <= rx_ctl_int0;
rx_ctl_int2 <= rx_ctl_int1;
rx_dv_int0 <= rx_dv_int;
rx_dv_int1 <= rx_dv_int0;
rx_dv_int2 <= rx_dv_int2;
end if;
end process;
process (rx_clk)
begin
if (sync_rxctrl_q1_delay = "00") then
--rx_dv0 <= rx_dv_int;
if (sync_rxctrl_c_delay = '1') then
rx_dv0 <= rx_ctl_int;
else
rx_dv0 <= rx_dv_int;
end if;
elsif (sync_rxctrl_q1_delay = "01") then
rx_dv0 <= rx_dv_int0;
elsif (sync_rxctrl_q1_delay = "10") then
rx_dv0 <= rx_dv_int1;
else
rx_dv0 <= rx_dv_int2;
end if;
if (sync_rxctrl_q2_delay = "00") then
--rx_ctl0 <= rx_ctl_int;
if (sync_rxctrl_c_delay = '1') then
rx_ctl0 <= rx_dv_int0;
else
rx_ctl0 <= rx_ctl_int;
end if;
elsif (sync_rxctrl_q2_delay = "01") then
rx_ctl0 <= rx_ctl_int0;
elsif (sync_rxctrl_q2_delay = "10") then
rx_ctl0 <= rx_ctl_int1;
else
rx_ctl0 <= rx_ctl_int2;
end if;
end process;
rx_dv <= rx_dv0 when (sync_rxctrl_q1_sel = '0') else rx_ctl0;
rx_ctl <= rx_ctl0 when (sync_rxctrl_q1_sel = '0') else rx_dv0;
-- Decode GMII error signal
rx_error <= rx_dv xor rx_ctl;
-- Enable inband status registers during Interframe Gap
inbandopt <= not ( rx_dv or rx_error );
inbandreq <= rx_error and not rx_dv;
-- Sample RGMII inband information
process (rx_clk)
begin
if rising_edge(rx_clk) then
if (inbandopt = '1') then
link_status <= rxd(0);
clock_speed <= rxd(2 downto 1);
duplex_status <= rxd(3);
end if;
if (inbandreq = '1') then
if (rxd = x"0E") then false_carrier_ind <= '1'; else false_carrier_ind <= '0'; end if;
if (rxd = x"0F") then carrier_ext <= '1'; else carrier_ext <= '0'; end if;
if (rxd = x"1F") then carrier_ext_error <= '1'; else carrier_ext_error <= '0'; end if;
if (rxd = x"FF") then carrier_sense <= '1'; else carrier_sense <= '0'; end if;
end if;
end if;
end process;
-- GMII output
gmiii.rxd <= rxd;
gmiii.rx_dv <= rx_dv;
gmiii.rx_er <= rx_error;
gmiii.rx_clk <= rx_clk;
gmiii.rx_col <= '0';
gmiii.rx_crs <= rx_dv;
gmiii.rmii_clk <= '0';
gmiii.rx_en <= '1';
-- GMII output controlled via generics
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
---------------------------------------------------------------------------------------
-- APB Section
---------------------------------------------------------------------------------------
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- Status Register
status_vector_sync(15) <= '1' when (no_clk_mux = 1) else '0';
status_vector_sync(14) <= '1' when (debugmem = 1 ) else '0';
status_vector_sync(13) <= '1' when (gmii = 1 ) else '0';
status_vector_sync(12 downto 10) <= (others => '0');
status_vector_sync(9) <= gmiio.gbit;
status_vector_sync(8) <= gmiio.speed;
status_vector_sync(7) <= carrier_sense;
status_vector_sync(6) <= carrier_ext_error;
status_vector_sync(5) <= carrier_ext;
status_vector_sync(4) <= false_carrier_ind;
status_vector_sync(3) <= duplex_status;
status_vector_sync(2) <= clock_speed(1);
status_vector_sync(1) <= clock_speed(0);
status_vector_sync(0) <= link_status;
-- CDC clock domain crossing
syncreg_status : for i in 0 to status_vector'length-1 generate
syncreg3 : syncreg port map (tx_clk, status_vector_sync(i), status_vector(i));
end generate;
rgmiiapb : process(apb_rstn, r, apbi, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead, status_vector )
variable rdata : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : rgmiiregs;
begin
v := r;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
rdata := (others => '0');
v.status_vector(1) := r.status_vector(0);
v.status_vector(0) := status_vector;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(15 downto 0) := r.status_vector(0);
when "000001" =>
rdata(15 downto 0) := r.irq;
v.irq := (others => '0'); -- Interrupt is clear on read
when "000010" =>
rdata(15 downto 0) := r.mask;
when "000011" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_wrap);
when "000100" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_first_edge);
when "000101" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_second_edge);
when "000110" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_wrap);
when "000111" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_first_edge);
when "001000" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_second_edge);
when "001001" =>
rdata(23 downto 0) := r.clkedge;
when "001010" =>
rdata(1 downto 0) := v.rxctrl_q2_delay;
when "001011" =>
rdata(1 downto 0) := v.rxctrl_q1_delay;
when "001100" =>
rdata(0) := v.rxctrl_q1_sel;
when "001101" =>
rdata(0) := v.rxctrl_delay;
when "001110" =>
rdata(0) := v.rxctrl_c_delay;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
null;
when "000001" =>
null;
when "000010" =>
v.mask := apbi.pwdata(15 downto 0);
when "000011" =>
v.clk25_wrap := unsigned(apbi.pwdata(5 downto 0));
when "000100" =>
v.clk25_first_edge := unsigned(apbi.pwdata(5 downto 0));
when "000101" =>
v.clk25_second_edge := unsigned(apbi.pwdata(5 downto 0));
when "000110" =>
v.clk2_5_wrap := unsigned(apbi.pwdata(5 downto 0));
when "000111" =>
v.clk2_5_first_edge := unsigned(apbi.pwdata(5 downto 0));
when "001000" =>
v.clk2_5_second_edge := unsigned(apbi.pwdata(5 downto 0));
when "001001" =>
v.clkedge := apbi.pwdata(23 downto 0);
when "001010" =>
v.rxctrl_q2_delay := apbi.pwdata(1 downto 0);
when "001011" =>
v.rxctrl_q1_delay := apbi.pwdata(1 downto 0);
when "001100" =>
v.rxctrl_q1_sel := apbi.pwdata(0);
when "001101" =>
v.rxctrl_delay := apbi.pwdata(0);
when "001110" =>
v.rxctrl_c_delay := apbi.pwdata(0);
when others =>
null;
end case;
end if;
-- Check interrupts
for i in 0 to r.status_vector'length-1 loop
if ((r.status_vector(0)(i) xor r.status_vector(1)(i)) and r.mask(i)) = '1' then
v.irq(i) := '1';
end if;
end loop;
-- reset operation
if (not RESET_ALL) and (apb_rstn = '0') then
if (tech = kintex7) then
v := RES_kintex7;
elsif (tech = spartan6) then
v := RES_spartan6;
elsif (tech = artix7) then
v := RES_artix7;
else
v := RES;
end if;
end if;
-- update registers
rin <= v;
-- drive outputs
if apbi.psel(pindex) = '0' then
apbo.prdata <= (others => '0');
elsif RMemRgmiiiRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiiiData;
elsif RMemRgmiioRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiioData;
else
apbo.prdata <= rdata;
end if;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= orv(v.irq);
end process;
regs : process(apb_clk)
begin
if rising_edge(apb_clk) then
r <= rin;
if RESET_ALL and apb_rstn = '0' then
if (tech = kintex7) then
r <= RES_kintex7;
elsif (tech = spartan6) then
r <= RES_spartan6;
else
r <= RES;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- Debug Mem
---------------------------------------------------------------------------------------
debugmem1 : if (debugmem /= 0) generate
-- Write GMII IN data
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
WMemRgmiioData(15 downto 0) <= "000" & tx_en & "000" & tx_ctl & txd;
if (tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then
WMemRgmiioAddr <= WMemRgmiioAddr + 1;
WMemRgmiioWrEn <= '1';
else
if (tx_en = '0') then
WMemRgmiioAddr <= (others => '1');
else
WMemRgmiioAddr <= WMemRgmiioAddr;
end if;
WMemRgmiioWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex);
RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2);
gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData,
tx_clk, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData);
-- Write GMII IN data
process (rx_clk)
begin -- process
if rising_edge(rx_clk) then
WMemRgmiiiData(15 downto 0) <= "000" & rx_dv & "000" & rx_ctl & rxd(7 downto 4) & rxd(3 downto 0);
if ((rx_dv = '1') or (rx_ctl = '1')) and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then
WMemRgmiiiAddr <= WMemRgmiiiAddr + 1;
WMemRgmiiiWrEn <= '1';
else
if (rx_dv = '0') then
WMemRgmiiiAddr <= (others => '1');
else
WMemRgmiiiAddr <= WMemRgmiiiAddr;
end if;
WMemRgmiiiWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex);
RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2);
rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData,
rx_clk, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("rgmii" & tost(pindex) &
": RGMII rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end rtl;
|
gpl-2.0
|
741bfaac43e60a5d770c8e17b5e69848
| 0.550584 | 3.260379 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-115/testbench.vhd
| 1 | 7,513 |
-------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_zio : std_logic;
signal mcb3_dram_dqs : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n : std_logic_vector(1 downto 0);
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(2 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic_vector(1 downto 0);
signal mcb3_dram_udm : std_logic;
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.417 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_dqs(1),
mcb3_dram_udqs_n => mcb3_dram_dqs_n(1),
mcb3_dram_dqs => mcb3_dram_dqs(0),
mcb3_dram_dqs_n => mcb3_dram_dqs_n(0),
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm(0),
mcb3_dram_udm => mcb3_dram_dm(1),
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr0 : ddr2ram
generic map(width => 16, abits => 13, babits => 3, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>9, density => 2,
lddelay => 115 us)
port map (ck => mcb3_dram_ck, ckn => mcb3_dram_ck_n, cke => mcb3_dram_cke, csn => csb,
odt => '0', rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n,
dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a(12 downto 0),
dq => mcb3_dram_dq, dqs => mcb3_dram_dqs, dqsn => mcb3_dram_dqs_n);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
gpl-2.0
|
289589d48371fa58f809c6d9f5ccc60d
| 0.545188 | 3.331707 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml50x/config.vhd
| 1 | 7,763 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.devices.all;
package config is
-- Board selection
constant CFG_BOARD_SELECTION : system_device_type := XILINX_ML505;
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000505#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (190);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
343f6320460e220ef0dae113fa172d9e
| 0.652454 | 3.541515 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-cpci-xc2v6000/config.vhd
| 1 | 7,680 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000004#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 1;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN + CFG_SDCTRL;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK + CFG_SDCTRL_INVCLK;
constant CFG_SEPBUS : integer := CFG_MCTRL_SEPBUS + CFG_SDCTRL;
constant CFG_SD64 : integer := CFG_MCTRL_SD64 + CFG_SDCTRL_SD64;
end;
|
gpl-2.0
|
cad1dc45888080fda0af80600a4490cd
| 0.650391 | 3.593823 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/rotl00.vhd
| 1 | 1,397 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rotl00 is
port(
clkrotl: in std_logic ;
codoprotl: in std_logic_vector ( 3 downto 0 );
portArotl: in std_logic_vector ( 7 downto 0 );
inFlagrotl: in std_logic;
outrotl: out std_logic_vector ( 7 downto 0 );
outFlagrotl: out std_logic );
end;
architecture rotl0 of rotl00 is
begin
rotl: process(codoprotl, portArotl)
begin
if(codoprotl = "1101") then
outrotl(0) <= portArotl(7);
outrotl(7 downto 1) <= portArotl(6 downto 0);
outFlagrotl <= '1';
else
outrotl <= (others => 'Z');
outFlagrotl <= 'Z';
end if;
end process rotl;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end rotl0;
|
apache-2.0
|
3000326d459f2ae1f8be498fa7bf65a6
| 0.506084 | 3.077093 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd
| 1 | 7,960 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of cyclone3_pll is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY"
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
-- Must use operation_mode other than "ZERO_DELAY_BUFFER" due to
-- tool issues with ZERO_DELAY_BUFFER and non-existent output clock
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 5,
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_cycloneiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_cycloneiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component cyclone3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : cyclone3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_cycloneiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
gpl-2.0
|
6a9e2eae6c4101bfcc53cfbb13d59bd7
| 0.587437 | 3.51901 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/amba/dma2ahb_pkg.vhd
| 1 | 6,039 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_Package (package declaration)
--
-- File name : dma2ahb_pkg.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : gaisler
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.7 SH 6 Dec 2007 Added syncrst generic
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package DMA2AHB_Package is
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface Types
-----------------------------------------------------------------------------
type DMA_In_Type is record
Reset: Std_Logic;
Address: Std_Logic_Vector(32-1 downto 0);
Data: Std_Logic_Vector(32-1 downto 0);
Request: Std_Logic; -- access requested
Burst: Std_Logic; -- burst requested
Beat: Std_Logic_Vector(1 downto 0); -- incrementing beat
Size: Std_Logic_Vector(1 downto 0); -- size
Store: Std_Logic; -- data write requested
Lock: Std_Logic; -- locked Transfer
end record;
type DMA_Out_Type is record
Grant: Std_Logic; -- access accepted
OKAY: Std_Logic; -- write access ready
Ready: Std_Logic; -- read data ready
Retry: Std_Logic; -- retry
Fault: Std_Logic; -- error occured
Data: Std_Logic_Vector(32-1 downto 0);
end record;
-- constants for HBURST definition (used with dma_in_type.Beat)
constant HINCR: Std_Logic_Vector(1 downto 0) := "00";
constant HINCR4: Std_Logic_Vector(1 downto 0) := "01";
constant HINCR8: Std_Logic_Vector(1 downto 0) := "10";
constant HINCR16: Std_Logic_Vector(1 downto 0) := "11";
-- constants for HSIZE definition (used with dma_in_type.Size)
constant HSIZE8: Std_Logic_Vector(1 downto 0) := "00";
constant HSIZE16: Std_Logic_Vector(1 downto 0) := "01";
constant HSIZE32: Std_Logic_Vector(1 downto 0) := "10";
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface
-----------------------------------------------------------------------------
component DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic;
HRESETn: in Std_ULogic;
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end component DMA2AHB;
end package DMA2AHB_Package; --===============================================--
|
gpl-2.0
|
806c63f60b815875573a00a826d4ceeb
| 0.503063 | 4.706937 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-minimal/leon3mp.vhd
| 1 | 10,498 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
clk : in std_ulogic; -- FPGA main clock input
-- Buttons & LEDs
btnCpuResetn : in std_ulogic; -- Reset button
Led : out std_logic_vector(15 downto 0);
-- Onboard Cellular RAM
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
-- Memory controler signals
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
-- AMBA bus signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to 0);
signal irqo : irq_out_vector(0 to 0);
signal dbgi : l3_debug_in_vector(0 to 0);
signal dbgo : l3_debug_out_vector(0 to 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal gpti : gptimer_in_type;
signal clkm, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart (unconnected)
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant clock_mult : integer := 10; -- Clock multiplier
constant clock_div : integer := 20; -- Clock divider
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * clock_mult / clock_div; -- CPU freq in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 0)
port map (btnCpuResetn, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, clock_mult, clock_div, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (ioen => 1, nahbm => 4, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
u0 : leon3s
generic map (hindex=>0, fabtech=>fabtech, memtech=>memtech, dsu=>1, fpu=>0, v8=>2,
mac=>0, isetsize=>8, dsetsize=>8,icen=>1, dcen=>1,tbuf=>2)
port map (clkm, rstn, ahbmi, ahbmo(0), ahbsi, ahbso, irqi(0), irqo(0), dbgi(0), dbgo(0));
-- LEON3 Debug Support Unit
dsu0 : dsu3
generic map (hindex => 2, ncpu => 1, tech => memtech, irq => 0, kbytes => 2)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- Debug UART
dcom0 : ahbuart
generic map (hindex => 1, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(1));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => 3)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(3),
open, open, open, open, open, open, open, gnd);
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => 0, ram16 => 1,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01"; -- Sets data bus width for PROM accesses.
-- Bidirectional data bus
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
-- Out signals to memory
addr_pad : outpadv generic map (tech => padtech, width => 23) -- Address bus
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech) -- Output Enable
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech) -- SRAM Chip select
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech) -- Write enable
port map (RamWE, memo.writen);
RamCRE <= '0'; -- Special SRAM signals specific
RamClk <= '0'; -- to Nexys4 board
RamAdv <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- APB Bridge
generic map (hindex => 1, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
irqctrl0 : irqmp -- Interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => 1)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
timer0 : gptimer -- Time Unit
generic map (pindex => 3, paddr => 3, pirq => 8,
sepirq => 1, ntimers => 2)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => 1)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
gpl-2.0
|
c19c269c0f46544b64d43cd44f5a8c2a
| 0.51505 | 4.048592 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/ec/orca/orca_ecmem.vhd
| 4 | 61,799 |
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
GENERIC (
DATA_WIDTH_A : Integer := 18;
DATA_WIDTH_B : Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dp8ka";
-- input SIGNAL delays
tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
-- setup and hold constraints
-- pulse width constraints
tperiod_clka : VitalDelayType := 0.001 ns;
tpw_clka_posedge : VitalDelayType := 0.001 ns;
tpw_clka_negedge : VitalDelayType := 0.001 ns;
tperiod_clkb : VitalDelayType := 0.001 ns;
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
END dp8ka ;
-- ARCHITECTURE body --
ARCHITECTURE V OF dp8ka IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
--SIGNAL DECLARATIONS----
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL clka_ipd : std_logic := '0';
SIGNAL cea_ipd : std_logic := '0';
SIGNAL wrea_ipd : std_logic := '0';
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rsta_ipd : std_logic := '0';
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
SIGNAL clkb_ipd : std_logic := '0';
SIGNAL ceb_ipd : std_logic := '0';
SIGNAL wreb_ipd : std_logic := '0';
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rstb_ipd : std_logic := '0';
SIGNAL csa_en : std_logic := '0';
SIGNAL csb_en : std_logic := '0';
SIGNAL g_reset : std_logic := '0';
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL rsta_int : std_logic := '0';
SIGNAL rstb_int : std_logic := '0';
SIGNAL rsta_reg : std_logic := '0';
SIGNAL rstb_reg : std_logic := '0';
SIGNAL reseta : std_logic := '0';
SIGNAL resetb : std_logic := '0';
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL wrena_reg : std_logic := '0';
SIGNAL clka_valid : std_logic := '0';
SIGNAL clkb_valid : std_logic := '0';
SIGNAL clka_valid1 : std_logic := '0';
SIGNAL clkb_valid1 : std_logic := '0';
SIGNAL wrenb_reg : std_logic := '0';
SIGNAL rena_reg : std_logic := '0';
SIGNAL renb_reg : std_logic := '0';
SIGNAL rsta_sig : std_logic := '0';
SIGNAL rstb_sig : std_logic := '0';
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
CONSTANT initval : string(2560 downto 1) := (
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
SIGNAL j : integer := 0;
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
VitalWireDelay(clka_ipd, clka, tipd_clka);
VitalWireDelay(wrea_ipd, wea, tipd_wea);
VitalWireDelay(cea_ipd, cea, tipd_cea);
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
VitalWireDelay(wreb_ipd, web, tipd_web);
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
END BLOCK;
GLOBALRESET : PROCESS (purnet, gsrnet)
BEGIN
IF (GSR = "DISABLED") THEN
g_reset <= purnet;
ELSE
g_reset <= purnet AND gsrnet;
END IF;
END PROCESS;
rsta_sig <= rsta_ipd or (not g_reset);
rstb_sig <= rstb_ipd or (not g_reset);
-- set_reset <= g_reset and (not reset_ipd);
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
-- chip select A decode
P1 : PROCESS(csa_ipd)
BEGIN
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
csa_en <= '1';
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
csa_en <= '1';
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
csa_en <= '1';
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
csa_en <= '1';
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
csa_en <= '1';
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
csa_en <= '1';
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
csa_en <= '1';
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
csa_en <= '1';
ELSE
csa_en <= '0';
END IF;
END PROCESS;
P2 : PROCESS(csb_ipd)
BEGIN
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
csb_en <= '1';
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
csb_en <= '1';
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
csb_en <= '1';
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
csb_en <= '1';
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
csb_en <= '1';
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
csb_en <= '1';
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
csb_en <= '1';
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
csb_en <= '1';
ELSE
csb_en <= '0';
END IF;
END PROCESS;
P3 : PROCESS(dia_ipd)
BEGIN
CASE DATA_WIDTH_A IS
WHEN 1 =>
dia_node <= dia_ipd(11 downto 11);
WHEN 2 =>
dia_node <= (dia_ipd(1), dia_ipd(11));
WHEN 4 =>
dia_node <= dia_ipd(3 downto 0);
WHEN 9 =>
dia_node <= dia_ipd(8 downto 0);
WHEN 18 =>
dia_node <= dia_ipd;
WHEN 36 =>
dia_node <= dia_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
P4 : PROCESS(dib_ipd)
BEGIN
CASE DATA_WIDTH_B IS
WHEN 1 =>
dib_node <= dib_ipd(11 downto 11);
WHEN 2 =>
dib_node <= (dib_ipd(1), dib_ipd(11));
WHEN 4 =>
dib_node <= dib_ipd(3 downto 0);
WHEN 9 =>
dib_node <= dib_ipd(8 downto 0);
WHEN 18 =>
dib_node <= dib_ipd;
WHEN 36 =>
dib_node <= dib_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
diab_node <= (dib_ipd & dia_ipd);
P107 : PROCESS(clka_ipd)
BEGIN
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
clka_valid <= '0';
ELSE
IF (cea_ipd = '1') THEN
IF (csa_en = '1') THEN
clka_valid <= '1', '0' after 0.01 ns;
ELSE
clka_valid <= '0';
END IF;
ELSE
clka_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
P108 : PROCESS(clkb_ipd)
BEGIN
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
clkb_valid <= '0';
ELSE
IF (ceb_ipd = '1') THEN
IF (csb_en = '1') THEN
clkb_valid <= '1', '0' after 0.01 ns;
ELSE
clkb_valid <= '0';
END IF;
ELSE
clkb_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
clka_valid1 <= clka_valid;
clkb_valid1 <= clkb_valid;
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
END IF;
END PROCESS;
-- Warning for collision
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
renb_reg)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE ADDR_A : integer := 0;
VARIABLE ADDR_B : integer := 0;
VARIABLE DN_ADDR_A : integer := 0;
VARIABLE UP_ADDR_A : integer := 0;
VARIABLE DN_ADDR_B : integer := 0;
VARIABLE UP_ADDR_B : integer := 0;
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
ADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
ADDR_B := conv_integer(adb_reg);
END IF;
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity error;
END IF;
END IF;
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
END PROCESS;
-- Writing to the memory
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
wrenb_reg, clka_valid, clkb_valid)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE WADDR_A : integer := 0;
VARIABLE WADDR_B : integer := 0;
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
WADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
WADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_A = 36) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
END LOOP;
doa_node_rbr <= dout_node_rbr(17 downto 0);
dob_node_rbr <= dout_node_rbr(35 downto 18);
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
END LOOP;
END IF;
ELSE
IF (DATA_WIDTH_A = 18) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_A = 9) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
END IF;
ELSE
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
END LOOP;
END IF;
END IF;
IF (DATA_WIDTH_B = 18) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_B = 9) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
END IF;
ELSE
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
VARIABLE RADDR_A_VALID : boolean := TRUE;
VARIABLE RADDR_B_VALID : boolean := TRUE;
VARIABLE RADDR_A : integer := 0;
VARIABLE RADDR_B : integer := 0;
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
BEGIN
RADDR_A_VALID := Valid_Address (ada_reg);
RADDR_B_VALID := Valid_Address (adb_reg);
IF (RADDR_A_VALID = TRUE) THEN
RADDR_A := conv_integer(ada_reg);
END IF;
IF (RADDR_B_VALID = TRUE) THEN
RADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_B = 36) THEN
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_tr(17 downto 0);
dob_node <= dout_node_tr(35 downto 18);
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_wt(17 downto 0);
dob_node <= dout_node_wt(35 downto 18);
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
ELSE
IF (rsta_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clka_ipd = '1') THEN
doa_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
END IF;
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
IF (rena_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (rena_reg = '0') THEN
IF (WRITEMODE_A = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
END IF;
END IF;
END IF;
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
doa_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
doa_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (rsta_ipd = '0') THEN
doa_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (rstb_ipd = '0') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
BEGIN
IF (REGMODE_A = "OUTREG") THEN
IF (DATA_WIDTH_B = 36) THEN
doa_int <= doab_reg;
ELSE
doa_int <= doa_reg;
END IF;
ELSE
doa_int <= doa_node;
END IF;
IF (REGMODE_B = "OUTREG") THEN
dob_int <= dob_reg;
ELSE
dob_int <= dob_node;
END IF;
END PROCESS;
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
END V;
--
-----cell sp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY sp8ka IS
GENERIC (
DATA_WIDTH : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
END sp8ka ;
architecture V of sp8ka is
signal lo: std_logic := '0';
signal hi: std_logic := '1';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
WRITEMODE_A : in String;
WRITEMODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH,
DATA_WIDTH_B => DATA_WIDTH,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE,
CSDECODE_B => CSDECODE,
WRITEMODE_A => WRITEMODE,
WRITEMODE_B => WRITEMODE,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
dib16 => lo, dib17 => lo,
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
doa16 => do16, doa17 => do17);
end V;
--
-----cell pdp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY pdp8ka IS
GENERIC (
DATA_WIDTH_W : Integer := 18;
DATA_WIDTH_R : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
END pdp8ka ;
architecture V of pdp8ka is
signal lo: std_logic := '0';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
DATA_WIDTH_B => DATA_WIDTH_R,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE_W,
CSDECODE_B => CSDECODE_R,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
dib16 => di34, dib17 => di35,
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
doa16 => do34, doa17 => do35);
end V;
|
gpl-2.0
|
6f89195e980abdbcdf1f041f1f6aa517
| 0.574184 | 3.584421 | false | false | false | false |
aortiz49/MIPS-Processor
|
Testbenches/alu32control_tb.vhd
| 1 | 1,128 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.MIPS_lib.all;
entity alu32control_tb is
end alu32control_tb;
architecture TB of alu32control_tb is
component alu32control
port(
ALUop : in std_logic_vector (2 downto 0);
funct : in std_logic_vector (5 downto 0);
control : out std_logic_vector (3 downto 0)
);
end component;
signal ALUop : std_logic_vector (2 downto 0);
signal funct : std_logic_vector (5 downto 0);
signal control : std_logic_vector(3 downto 0);
begin -- TB
UUT: entity work.alu32control
port map(
ALUop => ALUop,
funct => funct,
control => control
);
process
begin
ALUop <= LW_SW;
wait for 20 ns;
ALUop <= BEQ;
wait for 20 ns;
ALUop <= R_TYPE;
funct <= CTRL_ADD;
wait for 20 ns;
funct <= CTRL_SUB;
wait for 20 ns;
funct <= CTRL_AND;
wait for 20 ns;
funct <= CTRL_OR;
wait for 20 ns;
funct <= CTRL_NOR;
wait for 20 ns;
funct <= CTRL_SLT;
wait for 20 ns;
funct <= CTRL_SLTU;
wait for 380 ns;
wait;
end process;
end TB;
|
mit
|
a166deb7ec8f7e6576ce83de16a4c28d
| 0.632092 | 2.907216 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/wrapper/greth_gen.vhd
| 1 | 13,902 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gen
-- File: greth_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end entity;
architecture rtl of greth_gen is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl = 1) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ehgrant,
ehready => ehready,
ehresp => ehresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ehbusreq,
ehlock => ehlock,
ehtrans => ehtrans,
ehaddr => ehaddr,
ehwrite => ehwrite,
ehsize => ehsize,
ehburst => ehburst,
ehprot => ehprot,
ehwdata => ehwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => rmii_clk,
tx_clk => tx_clk,
tx_dv => tx_dv,
rx_clk => rx_clk,
rxd => rxd(3 downto 0),
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_en => rx_en,
rx_crs => rx_crs,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
mdint => mdint,
--ethernet output signals
reset => reset,
txd => txd(3 downto 0),
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen,
testoen => testoen,
edcladdr => edcladdr,
edclsepahb => edclsepahb,
edcldisable => edcldisable,
speed => speed);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
end architecture;
|
gpl-2.0
|
2f7c41e37cbe2928c8fb533335fc9848
| 0.51453 | 4.138732 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaFinal/uc01.vhd
| 1 | 787 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uc01 is
port(
clkuc: in std_logic ;
inACuc: in std_logic_vector ( 7 downto 0 );
FlagInstuc: inout std_logic ;
outACuc: out std_logic_vector ( 7 downto 0 );
FlagReadyuc: out std_logic );
end;
architecture uc0 of uc01 is
signal sinACuc: std_logic_vector(7 downto 0);
begin
puc: process(clkuc, inACuc, FlagInstuc)
begin
if (clkuc'event and clkuc = '1') then
if (FlagInstuc = '1') then
sinACuc <= inACuc;
outACuc <= sinACuc;
FlagReadyuc <= '1';
elsif (FlagInstuc = '0') then
FlagReadyuc <= '0';
end if;
end if;
end process puc;
end uc0;
|
apache-2.0
|
a71cbed55de4e1ed43f39241354d5224
| 0.589581 | 3.148 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp605/svga2ch7301c.vhd
| 2 | 6,828 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
vgao : in apbvga_out_type;
vgaclk : in std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
signal nvgaclk : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nvgaclk <= not vgaclk;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
end rtl;
|
gpl-2.0
|
16dbbbc07e73cb6b2f2b507fd5e377af
| 0.553896 | 3.696806 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/memctrl/memctrl.vhd
| 1 | 20,513 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.log2;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
edac : std_logic;
end record;
constant memory_in_none : memory_in_type :=
((others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
vcdrive : std_logic_vector(15 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(15 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
sdram_en : std_ulogic; -- SDRAM enabled
rs_edac_en : std_ulogic; -- Reed-Solomon enabled
end record;
constant memory_out_none : memory_out_type :=
((others => '0'), (others => '0'), (others => '0'), (others => '1'),
(others => '1'), '1', '1', (others => '1'), '1', (others => '1'),
'1', '1', (others => '1'), (others => '1'), (others => '1'),
(others => '1'), '0', (others => '0'), (others => '1'), (others => '1'),
(others => '1'), (others => '1'), '0', '0', '0');
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(63 downto 0);
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in
datavalid : std_logic; -- Data-valid signal
end record;
constant sdctrl_in_none : sdctrl_in_type :=
('0', (others => '0'), (others => '0'), (others => '0'), '0');
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
xsdcsn : std_logic_vector ( 7 downto 0); -- ext. chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
nbdrive : std_ulogic; -- bdrive 1 cycle early
vbdrive : std_logic_vector(63 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(63 downto 0);
ce : std_ulogic;
ba : std_logic_vector (2 downto 0); -- bank address
sdck : std_logic_vector(2 downto 0);
moben : std_logic; -- Mobile support
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0); -- In Die Termination
conf : std_logic_vector(63 downto 0);
oct : std_logic; -- On Chip Termination
vcbdrive : std_logic_vector(31 downto 0); -- cb vector bus drive
dqs_gate : std_logic;
cbdqm : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy delays)
-- PHY-specific register interface
regwdata : std_logic_vector(63 downto 0);
regwrite : std_logic_vector(1 downto 0);
end record;
constant sdctrl_out_none : sdctrl_out_type :=
((others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), "00000000",
(others => '0'), "00");
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
type zbtssram_out_type is record
cen : std_ulogic;
oen : std_ulogic;
wen : std_ulogic;
advld : std_ulogic;
addr : std_logic_vector(22 downto 0);
bwn : std_logic_vector(15 downto 0);
data : std_logic_vector(127 downto 0);
dqoen : std_logic_vector(127 downto 0);
zz : std_ulogic;
shutdown : std_ulogic;
end record;
constant zbtssram_out_none : zbtssram_out_type := (
'1','1','1','1',(others => '0'),(others => '1'),(others => '0'),(others => '1'),'0','0');
type zbtssram_in_type is record
data : std_logic_vector(127 downto 0);
mbe : std_logic_vector(7 downto 0);
end record;
constant zbtssram_in_none : zbtssram_in_type := ( data => (others => '0'), mbe => (others => '0') );
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component sdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
merror : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0;
tech : integer := 0;
rahold : integer := 0;
wsshift : integer := 0;
brdynto : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component p8ctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 0;
iomask : integer := 16#ff0#;
ioaddr : integer := 0;
rammask : integer := 16#ff0#;
romws : integer := 15;
ramws : integer := 15;
prom8en : integer := 0;
rmw : integer := 0;
oepol : integer := 0;
romasel : integer range 0 to 28 := 23
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
end;
|
gpl-2.0
|
b6362a3e68b641aa2795440bac38c18b
| 0.516697 | 3.470897 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/snps/dw02/comp/DW02_components.vhd
| 6 | 1,601 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end DW02_components;
-- pragma translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity DW02_mult_2_stage is
generic( A_width: POSITIVE;
B_width: POSITIVE);
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end;
architecture behav of DW02_mult_2_stage is
signal P_i : std_logic_vector(A_width+B_width-1 downto 0);
begin
comb : process(A, B, TC)
begin
if notx(A) and notx(B) then
if TC = '1' then
P_i <= signed(A) * signed(B);
else
P_i <= unsigned(A) * unsigned(B);
end if;
else
P_i <= (others => 'X');
end if;
end process;
reg : process(CLK)
begin
if rising_edge(CLK) then
PRODUCT <= P_i;
end if;
end process;
end;
-- pragma translate_on
|
gpl-2.0
|
8b08ee4856467a4d9618b9b76ba6cd7d
| 0.603373 | 3.126953 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/ec/orca/orcacomp.vhd
| 5 | 74,888 |
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCACOMP.vhd,v 1.1 2005/12/06 13:00:22 tame Exp $
--
---
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE components IS
function str2std(L: string) return std_logic_vector;
function Str2int( L : string) return integer;
function Str2real( L : string) return REAL;
-----functions for Multipliers (for ECP)----------
function INT2VEC(INT: INTEGER; BWIDTH: INTEGER) RETURN STD_LOGIC_VECTOR;
function VEC2INT(v: std_logic_vector) return integer;
function ADDVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function SUBVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function TSCOMP(VECT: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function BITX (VECT: std_logic) return boolean;
function VECX (VECT: std_logic_vector) return boolean;
--
COMPONENT ageb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
ge: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT aleb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
le: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT aneb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
ne: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cd2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cu2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cb2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
con: IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fadd2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
cout0, cout1 : OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fsub2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
bi: IN std_logic := 'X';
bout0, bout1 : OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fadsu2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
bci: IN std_logic := 'X';
con: IN std_logic := 'X';
bco: OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1a
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3az
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3iy
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3jy
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1a
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT gsr
PORT(
gsr: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT inv
PORT(
a: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux21
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sd: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT l6mux21
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sd: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux41
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux81
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux161
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
d8: IN std_logic := 'X';
d9: IN std_logic := 'X';
d10: IN std_logic := 'X';
d11: IN std_logic := 'X';
d12: IN std_logic := 'X';
d13: IN std_logic := 'X';
d14: IN std_logic := 'X';
d15: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
sd4: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux321
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
d8: IN std_logic := 'X';
d9: IN std_logic := 'X';
d10: IN std_logic := 'X';
d11: IN std_logic := 'X';
d12: IN std_logic := 'X';
d13: IN std_logic := 'X';
d14: IN std_logic := 'X';
d15: IN std_logic := 'X';
d16: IN std_logic := 'X';
d17: IN std_logic := 'X';
d18: IN std_logic := 'X';
d19: IN std_logic := 'X';
d20: IN std_logic := 'X';
d21: IN std_logic := 'X';
d22: IN std_logic := 'X';
d23: IN std_logic := 'X';
d24: IN std_logic := 'X';
d25: IN std_logic := 'X';
d26: IN std_logic := 'X';
d27: IN std_logic := 'X';
d28: IN std_logic := 'X';
d29: IN std_logic := 'X';
d30: IN std_logic := 'X';
d31: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
sd4: IN std_logic := 'X';
sd5: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pfumx
PORT(
alut: IN std_logic := 'X';
blut: IN std_logic := 'X';
c0 : IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pur
PORT(
pur: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom32x1
GENERIC(
initval : string := "0x00000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4: IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom16x1
GENERIC(
initval : string := "0x0000"
);
PORT(
ad0, ad1, ad2, ad3: IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom64x1
GENERIC(
initval : string := "0x0000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom128x1
GENERIC(
initval : string := "0x00000000000000000000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5, ad6 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom256x1
GENERIC(
initval : string := "0x0000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT strtup
PORT(
uclk : IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT tsall
PORT(
tsall: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT vhi
PORT(
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT vlo
PORT(
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor11
PORT(
a, b, c, d, e, f, g, h, i, j, k: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor21
PORT(
a, b, c, d, e, f, g, h, i, j, k: IN std_logic := 'X';
l, m, n, o, p, q, r, s, t, u: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT bufba
PORT(
a: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pdp8ka
GENERIC(
DATA_WIDTH_W : in Integer := 18;
DATA_WIDTH_R : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT bbw
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obw
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ilvds
PORT(
a : IN std_logic := 'X';
an: IN std_logic := 'X';
z : OUT std_logic
);
END COMPONENT;
--
COMPONENT olvds
PORT(
a : IN std_logic := 'X';
z : OUT std_logic ;
zn : OUT std_logic
);
END COMPONENT;
--
COMPONENT bb
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT bbpd
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT bbpu
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ib
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ibpd
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ibpu
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ob
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obz
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obzpd
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obzpu
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT dcs
GENERIC(
DCSMODE : String := "POS");
PORT(
clk0 : IN std_logic;
clk1 : IN std_logic;
sel : IN std_logic;
dcsout : OUT std_logic);
END COMPONENT;
--
component EPLLB
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "8";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
WAKE_ON_LOCK : string := "off");
port(
CLKI : in STD_ULOGIC;
RST : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
LOCK : out STD_ULOGIC
);
end component;
--
component EHXPLLB
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "1";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
CLKOK_DIV : string := "2";
WAKE_ON_LOCK : string := "off";
DELAY_CNTL : string := "STATIC";
PHASEADJ : string := "0";
DUTY : string := "4");
port(
CLKI : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
RST : in STD_ULOGIC := '0';
DDAMODE : in STD_ULOGIC;
DDAIZR : in STD_ULOGIC;
DDAILAG : in STD_ULOGIC;
DDAIDEL0 : in STD_ULOGIC;
DDAIDEL1 : in STD_ULOGIC;
DDAIDEL2 : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
CLKOS : out STD_ULOGIC;
CLKOK : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
DDAOZR : out STD_ULOGIC;
DDAOLAG : out STD_ULOGIC;
DDAODEL0 : out STD_ULOGIC;
DDAODEL1 : out STD_ULOGIC;
DDAODEL2 : out STD_ULOGIC
);
end component;
--
------Component ORCALUT4------
component ORCALUT4
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT5------
component ORCALUT5
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT6------
component ORCALUT6
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT7------
component ORCALUT7
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
G : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT8------
component ORCALUT8
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
G : in STD_ULOGIC;
H : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
--
component MULT2
port(
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
B2 : in STD_ULOGIC;
B3 : in STD_ULOGIC;
CI : in STD_ULOGIC;
P0 : out STD_ULOGIC;
P1 : out STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
--
component IDDRXB
generic( REGSET : string := "RESET");
port(
D : in STD_LOGIC;
ECLK : in STD_LOGIC;
SCLK : in STD_LOGIC;
LSR : in STD_LOGIC;
CE : in STD_LOGIC;
DDRCLKPOL : in STD_LOGIC;
QA : out STD_LOGIC;
QB : out STD_LOGIC
);
end component;
--
component ODDRXB
generic( REGSET : string := "RESET");
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
--
component CCU2
generic (
inject1_0 : string := "YES";
inject1_1 : string := "YES";
init0: string := "0x0000";
init1: string := "0x0000"
);
port (
A0,A1 : in std_ulogic;
B0,B1 : in std_ulogic;
C0,C1 : in std_ulogic;
D0,D1 : in std_ulogic;
CIN : in std_ulogic;
S0,S1 : out std_ulogic;
COUT0,COUT1 : out std_ulogic
);
end component;
--
component DQSBUFB
generic(DEL_ADJ : string := "PLUS";
DEL_VAL : string := "0");
port(
DQSI : in STD_LOGIC;
CLK : in STD_LOGIC;
READ : in STD_LOGIC;
DQSDEL : in STD_LOGIC;
DQSO : out STD_LOGIC;
DDRCLKPOL : out STD_LOGIC;
DQSC : out STD_LOGIC;
PRMBDET : out STD_LOGIC
);
end component;
--
component DQSDLL
generic(DEL_ADJ : string := "PLUS";
DEL_VAL : string := "0";
LOCK_SENSITIVITY : string := "LOW");
port(
CLK : in STD_ULOGIC;
RST : in STD_ULOGIC;
UDDCNTL : in STD_ULOGIC;
LOCK : out STD_ULOGIC;
DQSDEL : out STD_ULOGIC
);
end component;
--
-- 18x18 MULT for ECP
component MULT18X18
generic(
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
REG_SIGNEDAB_0_CLK : string := "NONE";
REG_SIGNEDAB_0_CE : string := "CE0";
REG_SIGNEDAB_0_RST : string := "RST0";
REG_SIGNEDAB_1_CLK : string := "NONE";
REG_SIGNEDAB_1_CE : string := "CE0";
REG_SIGNEDAB_1_RST : string := "RST0";
SHIFT_IN_A : string := "FALSE";
SHIFT_IN_B : string := "FALSE";
GSR : string := "ENABLED");
port (
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
A5 : in STD_ULOGIC;
A6 : in STD_ULOGIC;
A7 : in STD_ULOGIC;
A8 : in STD_ULOGIC;
A9 : in STD_ULOGIC;
A10 : in STD_ULOGIC;
A11 : in STD_ULOGIC;
A12 : in STD_ULOGIC;
A13 : in STD_ULOGIC;
A14 : in STD_ULOGIC;
A15 : in STD_ULOGIC;
A16 : in STD_ULOGIC;
A17 : in STD_ULOGIC;
SRIA0 : in STD_ULOGIC;
SRIA1 : in STD_ULOGIC;
SRIA2 : in STD_ULOGIC;
SRIA3 : in STD_ULOGIC;
SRIA4 : in STD_ULOGIC;
SRIA5 : in STD_ULOGIC;
SRIA6 : in STD_ULOGIC;
SRIA7 : in STD_ULOGIC;
SRIA8 : in STD_ULOGIC;
SRIA9 : in STD_ULOGIC;
SRIA10 : in STD_ULOGIC;
SRIA11 : in STD_ULOGIC;
SRIA12 : in STD_ULOGIC;
SRIA13 : in STD_ULOGIC;
SRIA14 : in STD_ULOGIC;
SRIA15 : in STD_ULOGIC;
SRIA16 : in STD_ULOGIC;
SRIA17 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
B2 : in STD_ULOGIC;
B3 : in STD_ULOGIC;
B4 : in STD_ULOGIC;
B5 : in STD_ULOGIC;
B6 : in STD_ULOGIC;
B7 : in STD_ULOGIC;
B8 : in STD_ULOGIC;
B9 : in STD_ULOGIC;
B10 : in STD_ULOGIC;
B11 : in STD_ULOGIC;
B12 : in STD_ULOGIC;
B13 : in STD_ULOGIC;
B14 : in STD_ULOGIC;
B15 : in STD_ULOGIC;
B16 : in STD_ULOGIC;
B17 : in STD_ULOGIC;
SRIB0 : in STD_ULOGIC;
SRIB1 : in STD_ULOGIC;
SRIB2 : in STD_ULOGIC;
SRIB3 : in STD_ULOGIC;
SRIB4 : in STD_ULOGIC;
SRIB5 : in STD_ULOGIC;
SRIB6 : in STD_ULOGIC;
SRIB7 : in STD_ULOGIC;
SRIB8 : in STD_ULOGIC;
SRIB9 : in STD_ULOGIC;
SRIB10 : in STD_ULOGIC;
SRIB11 : in STD_ULOGIC;
SRIB12 : in STD_ULOGIC;
SRIB13 : in STD_ULOGIC;
SRIB14 : in STD_ULOGIC;
SRIB15 : in STD_ULOGIC;
SRIB16 : in STD_ULOGIC;
SRIB17 : in STD_ULOGIC;
SIGNEDAB : in STD_ULOGIC;
CE0 : in STD_ULOGIC;
CE1 : in STD_ULOGIC;
CE2 : in STD_ULOGIC;
CE3 : in STD_ULOGIC;
CLK0 : in STD_ULOGIC;
CLK1 : in STD_ULOGIC;
CLK2 : in STD_ULOGIC;
CLK3 : in STD_ULOGIC;
RST0 : in STD_ULOGIC;
RST1 : in STD_ULOGIC;
RST2 : in STD_ULOGIC;
RST3 : in STD_ULOGIC;
SROA0 : out STD_ULOGIC;
SROA1 : out STD_ULOGIC;
SROA2 : out STD_ULOGIC;
SROA3 : out STD_ULOGIC;
SROA4 : out STD_ULOGIC;
SROA5 : out STD_ULOGIC;
SROA6 : out STD_ULOGIC;
SROA7 : out STD_ULOGIC;
SROA8 : out STD_ULOGIC;
SROA9 : out STD_ULOGIC;
SROA10 : out STD_ULOGIC;
SROA11 : out STD_ULOGIC;
SROA12 : out STD_ULOGIC;
SROA13 : out STD_ULOGIC;
SROA14 : out STD_ULOGIC;
SROA15 : out STD_ULOGIC;
SROA16 : out STD_ULOGIC;
SROA17 : out STD_ULOGIC;
SROB0 : out STD_ULOGIC;
SROB1 : out STD_ULOGIC;
SROB2 : out STD_ULOGIC;
SROB3 : out STD_ULOGIC;
SROB4 : out STD_ULOGIC;
SROB5 : out STD_ULOGIC;
SROB6 : out STD_ULOGIC;
SROB7 : out STD_ULOGIC;
SROB8 : out STD_ULOGIC;
SROB9 : out STD_ULOGIC;
SROB10 : out STD_ULOGIC;
SROB11 : out STD_ULOGIC;
SROB12 : out STD_ULOGIC;
SROB13 : out STD_ULOGIC;
SROB14 : out STD_ULOGIC;
SROB15 : out STD_ULOGIC;
SROB16 : out STD_ULOGIC;
SROB17 : out STD_ULOGIC;
P0 : out STD_ULOGIC;
P1 : out STD_ULOGIC;
P2 : out STD_ULOGIC;
P3 : out STD_ULOGIC;
P4 : out STD_ULOGIC;
P5 : out STD_ULOGIC;
P6 : out STD_ULOGIC;
P7 : out STD_ULOGIC;
P8 : out STD_ULOGIC;
P9 : out STD_ULOGIC;
P10 : out STD_ULOGIC;
P11 : out STD_ULOGIC;
P12 : out STD_ULOGIC;
P13 : out STD_ULOGIC;
P14 : out STD_ULOGIC;
P15 : out STD_ULOGIC;
P16 : out STD_ULOGIC;
P17 : out STD_ULOGIC;
P18 : out STD_ULOGIC;
P19 : out STD_ULOGIC;
P20 : out STD_ULOGIC;
P21 : out STD_ULOGIC;
P22 : out STD_ULOGIC;
P23 : out STD_ULOGIC;
P24 : out STD_ULOGIC;
P25 : out STD_ULOGIC;
P26 : out STD_ULOGIC;
P27 : out STD_ULOGIC;
P28 : out STD_ULOGIC;
P29 : out STD_ULOGIC;
P30 : out STD_ULOGIC;
P31 : out STD_ULOGIC;
P32 : out STD_ULOGIC;
P33 : out STD_ULOGIC;
P34 : out STD_ULOGIC;
P35 : out STD_ULOGIC
);
end component;
end Components;
package body Components is
function str2std(L: string) return std_logic_vector is
variable vpos : integer := 0; -- Index of last valid bit in val.
variable lpos : integer; -- Index of next unused char in L.
variable val : std_logic_vector(1 to L'right); -- lenth of the vector.
begin
lpos := L'left;
while lpos <= L'right and vpos < VAL'length loop
if L(lpos) = '0' then
vpos := vpos + 1;
val(vpos) := '0';
elsif L(lpos) = '1' then
vpos := vpos + 1;
val(vpos) := '1';
else
exit; -- Bit values must be '0' or '1'.
end if;
lpos := lpos + 1;
end loop;
return val;
end str2std;
function str2int( L : string) return integer is
variable ok: boolean;
variable pos: integer:=1;
variable sign: integer := 1;
variable rval: integer := 0;
variable value: integer := 0;
begin
ok := FALSE;
if pos < L'right and (L(pos) = '-' or L(pos) = '+') then
if L(pos) = '-' then
sign := -1;
end if;
pos := pos + 1;
end if;
-- Once the optional leading sign is removed, an integer can
-- contain only the digits '0' through '9' and the '_'
-- (underscore) character. VHDL disallows two successive
-- underscores, and leading or trailing underscores.
if pos <= L'right and L(pos) >= '0' and L(pos) <= '9' then
while pos <= L'right loop
if L(pos) >= '0' and L(pos) <= '9' then
rval := rval * 10
+ character'pos(L(pos)) - character'pos('0');
ok := TRUE;
elsif L(pos) = '_' then
if pos = L'right
or L(pos + 1) < '0'
or L(pos + 1) > '9' then
ok := FALSE;
exit;
end if;
else
exit;
end if;
pos := pos + 1;
end loop;
end if;
value := sign * rval;
RETURN(value);
end str2int;
function str2real( L: string) return real is
variable pos: integer;
variable value: real;
variable ok: boolean;
variable sign: real := 1.0;
variable rval: real := 0.0;
variable powerten: real := 0.1;
begin
pos := L'left;
if (pos <= L'right) and (L(pos) = '-') then
sign := -1.0;
pos := pos + 1;
end if;
ok := FALSE;
rval := 0.0;
if pos <= L'right and L(pos) >= '0' and L(pos) <= '9' then
while pos <= L'right and L(pos) /= '.' and L(pos) /= ' ' and L(pos) /= HT
loop
if L(pos) >= '0' and L(pos) <= '9' then
rval := rval*10.0 + real(character'pos(L(pos)) - character'pos('0'));
pos := pos+1;
ok := true;
else
ok := false;
exit;
end if;
end loop;
end if;
if ok and pos <= L'right and L(pos) = '.' then
pos := pos + 1;
end if;
if pos <= L'right then
while pos <= L'right and ((L(pos) >= '0' and L(pos) <= '9') or L(pos) = '_') loop
rval := rval + (real(character'pos(L(pos))-character'pos('0'))*powerten);
powerten := powerten*0.1;
pos := pos+1;
ok := true;
end loop;
end if;
if ok then
value := rval * sign;
end if;
return (value);
end str2real;
function INT2VEC(INT: INTEGER; BWIDTH: INTEGER) RETURN STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (BWIDTH-1 downto 0);
variable tmp : integer := INT;
begin
tmp := INT;
for i in 0 to BWIDTH-1 loop
if (tmp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if tmp > 0 then
tmp := tmp /2 ;
elsif (tmp > integer'low) then
tmp := (tmp-1) / 2;
else
tmp := tmp / 2;
end if;
end loop;
return result;
end;
function VEC2INT(v: std_logic_vector) return integer is
variable result: integer := 0;
variable addition: integer := 1;
begin
for b in v'reverse_range loop
if v(b) = '1' then
result := result + addition;
end if;
addition := addition * 2;
end loop;
return result;
end VEC2INT;
function VECX (VECT: std_logic_vector) return boolean is
begin
for b in VECT'range loop
if bitX (VECT (b)) then
return true;
end if;
end loop;
return false;
end VECX;
function TSCOMP(VECT: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (VECT'left downto 0);
variable is1 : std_ulogic := '0';
begin
for i in 0 to VECT'left loop
if (is1 = '0') then
result(i) := VECT(i);
if (VECT(i) = '1' ) then
is1 := '1';
end if;
else
result(i) := NOT VECT(i);
end if;
end loop;
return result;
end;
function ADDVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable cout: STD_ULOGIC;
variable BVect, result: STD_LOGIC_VECTOR(A'left downto 0);
begin
for i in 0 to A'left loop
if (A(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
for i in 0 to B'left loop
if (B(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
cout := '0';
BVEct := B;
for i in 0 to A'left loop
result(i) := A(i) xor BVect(i) xor cout;
cout := (A(i) and BVect(i)) or
(A(i) and cout) or
(cout and BVect(i));
end loop;
return result;
end;
function SUBVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable cout: STD_ULOGIC;
variable result: STD_LOGIC_VECTOR(A'left downto 0);
begin
for i in 0 to A'left loop
if (A(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
for i in 0 to B'left loop
if (B(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
cout := '1';
for i in 0 to A'left loop
result(i) := A(i) xor not B(i) xor cout;
cout := (A(i) and not B(i)) or
(A(i) and cout) or
(cout and not B(i));
end loop;
return result;
end;
function BITX (VECT: std_logic) return boolean is
begin
case VECT is
when 'X' => return true;
when others => return false;
end case;
end BITX;
END components;
|
gpl-2.0
|
5f20051d82adab54b2ff3b2409c20d4b
| 0.52485 | 3.342767 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-atlys/ahbrom.vhd
| 3 | 13,745 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 976;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"821020C0";
when 16#00001# => romdata <= X"81884000";
when 16#00002# => romdata <= X"01000000";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"01000000";
when 16#00006# => romdata <= X"01000000";
when 16#00007# => romdata <= X"81980000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"01000000";
when 16#0000A# => romdata <= X"C0A00040";
when 16#0000B# => romdata <= X"01000000";
when 16#0000C# => romdata <= X"01000000";
when 16#0000D# => romdata <= X"11200000";
when 16#0000E# => romdata <= X"90122100";
when 16#0000F# => romdata <= X"821020A2";
when 16#00010# => romdata <= X"C222200C";
when 16#00011# => romdata <= X"82102003";
when 16#00012# => romdata <= X"C2222008";
when 16#00013# => romdata <= X"11000000";
when 16#00014# => romdata <= X"90122344";
when 16#00015# => romdata <= X"40000091";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"113FFC00";
when 16#00018# => romdata <= X"90122200";
when 16#00019# => romdata <= X"82102018";
when 16#0001A# => romdata <= X"C2222004";
when 16#0001B# => romdata <= X"9010202E";
when 16#0001C# => romdata <= X"40000080";
when 16#0001D# => romdata <= X"01000000";
when 16#0001E# => romdata <= X"113FFC00";
when 16#0001F# => romdata <= X"90122200";
when 16#00020# => romdata <= X"C2022008";
when 16#00021# => romdata <= X"80886004";
when 16#00022# => romdata <= X"02BFFFFC";
when 16#00023# => romdata <= X"01000000";
when 16#00024# => romdata <= X"9010202E";
when 16#00025# => romdata <= X"40000077";
when 16#00026# => romdata <= X"01000000";
when 16#00027# => romdata <= X"113FFC00";
when 16#00028# => romdata <= X"90122100";
when 16#00029# => romdata <= X"13208821";
when 16#0002A# => romdata <= X"92126091";
when 16#0002B# => romdata <= X"D2220000";
when 16#0002C# => romdata <= X"1300B140";
when 16#0002D# => romdata <= X"D2222008";
when 16#0002E# => romdata <= X"92102100";
when 16#0002F# => romdata <= X"D222200C";
when 16#00030# => romdata <= X"130011C0";
when 16#00031# => romdata <= X"92126004";
when 16#00032# => romdata <= X"D2222010";
when 16#00033# => romdata <= X"13208821";
when 16#00034# => romdata <= X"92126091";
when 16#00035# => romdata <= X"03000040";
when 16#00036# => romdata <= X"92124001";
when 16#00037# => romdata <= X"D2220000";
when 16#00038# => romdata <= X"9010202E";
when 16#00039# => romdata <= X"40000063";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"40000051";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"40000081";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"9010202E";
when 16#00040# => romdata <= X"4000005C";
when 16#00041# => romdata <= X"01000000";
when 16#00042# => romdata <= X"40000070";
when 16#00043# => romdata <= X"01000000";
when 16#00044# => romdata <= X"9010202E";
when 16#00045# => romdata <= X"40000057";
when 16#00046# => romdata <= X"01000000";
when 16#00047# => romdata <= X"A2100000";
when 16#00048# => romdata <= X"A4100000";
when 16#00049# => romdata <= X"A6103FFF";
when 16#0004A# => romdata <= X"40000074";
when 16#0004B# => romdata <= X"01000000";
when 16#0004C# => romdata <= X"80A460A0";
when 16#0004D# => romdata <= X"22800002";
when 16#0004E# => romdata <= X"90100000";
when 16#0004F# => romdata <= X"80A22000";
when 16#00050# => romdata <= X"1280000B";
when 16#00051# => romdata <= X"A404A001";
when 16#00052# => romdata <= X"80A4A010";
when 16#00053# => romdata <= X"24800008";
when 16#00054# => romdata <= X"A4100000";
when 16#00055# => romdata <= X"80A4FFFF";
when 16#00056# => romdata <= X"32800005";
when 16#00057# => romdata <= X"A4100000";
when 16#00058# => romdata <= X"A534A001";
when 16#00059# => romdata <= X"A6244012";
when 16#0005A# => romdata <= X"A4100000";
when 16#0005B# => romdata <= X"4000003D";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"80A460A0";
when 16#0005E# => romdata <= X"A2046001";
when 16#0005F# => romdata <= X"12BFFFEB";
when 16#00060# => romdata <= X"01000000";
when 16#00061# => romdata <= X"80A4FFFF";
when 16#00062# => romdata <= X"02800022";
when 16#00063# => romdata <= X"01000000";
when 16#00064# => romdata <= X"11000000";
when 16#00065# => romdata <= X"9012234F";
when 16#00066# => romdata <= X"40000040";
when 16#00067# => romdata <= X"01000000";
when 16#00068# => romdata <= X"9134E004";
when 16#00069# => romdata <= X"40000033";
when 16#0006A# => romdata <= X"90022030";
when 16#0006B# => romdata <= X"900CE00F";
when 16#0006C# => romdata <= X"80A2200A";
when 16#0006D# => romdata <= X"90022030";
when 16#0006E# => romdata <= X"36800002";
when 16#0006F# => romdata <= X"90022027";
when 16#00070# => romdata <= X"4000002C";
when 16#00071# => romdata <= X"01000000";
when 16#00072# => romdata <= X"4000001A";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"4000004A";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"80A4E000";
when 16#00077# => romdata <= X"02800006";
when 16#00078# => romdata <= X"01000000";
when 16#00079# => romdata <= X"4000001F";
when 16#0007A# => romdata <= X"01000000";
when 16#0007B# => romdata <= X"10BFFFF9";
when 16#0007C# => romdata <= X"A624E001";
when 16#0007D# => romdata <= X"11000000";
when 16#0007E# => romdata <= X"90122360";
when 16#0007F# => romdata <= X"40000027";
when 16#00080# => romdata <= X"01000000";
when 16#00081# => romdata <= X"03380800";
when 16#00082# => romdata <= X"81C04000";
when 16#00083# => romdata <= X"01000000";
when 16#00084# => romdata <= X"11000000";
when 16#00085# => romdata <= X"90122368";
when 16#00086# => romdata <= X"40000020";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"40000004";
when 16#00089# => romdata <= X"01000000";
when 16#0008A# => romdata <= X"10BFFFF7";
when 16#0008B# => romdata <= X"01000000";
when 16#0008C# => romdata <= X"03200000";
when 16#0008D# => romdata <= X"113FFC00";
when 16#0008E# => romdata <= X"90122100";
when 16#0008F# => romdata <= X"1300B140";
when 16#00090# => romdata <= X"92124001";
when 16#00091# => romdata <= X"D2222008";
when 16#00092# => romdata <= X"82102014";
when 16#00093# => romdata <= X"82A06001";
when 16#00094# => romdata <= X"12BFFFFF";
when 16#00095# => romdata <= X"01000000";
when 16#00096# => romdata <= X"81C3E008";
when 16#00097# => romdata <= X"01000000";
when 16#00098# => romdata <= X"0300003F";
when 16#00099# => romdata <= X"821063FF";
when 16#0009A# => romdata <= X"10BFFFF3";
when 16#0009B# => romdata <= X"01000000";
when 16#0009C# => romdata <= X"03200000";
when 16#0009D# => romdata <= X"82106100";
when 16#0009E# => romdata <= X"C2006004";
when 16#0009F# => romdata <= X"80886004";
when 16#000A0# => romdata <= X"02BFFFFC";
when 16#000A1# => romdata <= X"03200000";
when 16#000A2# => romdata <= X"82106100";
when 16#000A3# => romdata <= X"D0204000";
when 16#000A4# => romdata <= X"81C3E008";
when 16#000A5# => romdata <= X"01000000";
when 16#000A6# => romdata <= X"9A10000F";
when 16#000A7# => romdata <= X"92100008";
when 16#000A8# => romdata <= X"D00A4000";
when 16#000A9# => romdata <= X"80A20000";
when 16#000AA# => romdata <= X"02800006";
when 16#000AB# => romdata <= X"92026001";
when 16#000AC# => romdata <= X"7FFFFFF0";
when 16#000AD# => romdata <= X"01000000";
when 16#000AE# => romdata <= X"10BFFFFA";
when 16#000AF# => romdata <= X"01000000";
when 16#000B0# => romdata <= X"81C36008";
when 16#000B1# => romdata <= X"01000000";
when 16#000B2# => romdata <= X"11100000";
when 16#000B3# => romdata <= X"13000000";
when 16#000B4# => romdata <= X"92126374";
when 16#000B5# => romdata <= X"94102010";
when 16#000B6# => romdata <= X"C2024000";
when 16#000B7# => romdata <= X"92026004";
when 16#000B8# => romdata <= X"C2220000";
when 16#000B9# => romdata <= X"94A2A001";
when 16#000BA# => romdata <= X"12BFFFFC";
when 16#000BB# => romdata <= X"90022004";
when 16#000BC# => romdata <= X"81C3E008";
when 16#000BD# => romdata <= X"01000000";
when 16#000BE# => romdata <= X"11100000";
when 16#000BF# => romdata <= X"13000000";
when 16#000C0# => romdata <= X"92126374";
when 16#000C1# => romdata <= X"D41A0000";
when 16#000C2# => romdata <= X"90022008";
when 16#000C3# => romdata <= X"C2024000";
when 16#000C4# => romdata <= X"80A0400A";
when 16#000C5# => romdata <= X"1280000A";
when 16#000C6# => romdata <= X"C2026004";
when 16#000C7# => romdata <= X"80A0400B";
when 16#000C8# => romdata <= X"12800007";
when 16#000C9# => romdata <= X"92026008";
when 16#000CA# => romdata <= X"808A2040";
when 16#000CB# => romdata <= X"02BFFFF6";
when 16#000CC# => romdata <= X"01000000";
when 16#000CD# => romdata <= X"81C3E008";
when 16#000CE# => romdata <= X"90102001";
when 16#000CF# => romdata <= X"81C3E008";
when 16#000D0# => romdata <= X"90102000";
when 16#000D1# => romdata <= X"0D0A4148";
when 16#000D2# => romdata <= X"42524F4D";
when 16#000D3# => romdata <= X"3A200020";
when 16#000D4# => romdata <= X"64647232";
when 16#000D5# => romdata <= X"5F64656C";
when 16#000D6# => romdata <= X"6179203D";
when 16#000D7# => romdata <= X"20307800";
when 16#000D8# => romdata <= X"2C204F4B";
when 16#000D9# => romdata <= X"2E0D0A00";
when 16#000DA# => romdata <= X"4641494C";
when 16#000DB# => romdata <= X"45440D0A";
when 16#000DC# => romdata <= X"00000000";
when 16#000DD# => romdata <= X"12345678";
when 16#000DE# => romdata <= X"F0C3A596";
when 16#000DF# => romdata <= X"6789ABCD";
when 16#000E0# => romdata <= X"A6F1590E";
when 16#000E1# => romdata <= X"EDCBA987";
when 16#000E2# => romdata <= X"0F3C5A69";
when 16#000E3# => romdata <= X"98765432";
when 16#000E4# => romdata <= X"590EA6F1";
when 16#000E5# => romdata <= X"FFFF0000";
when 16#000E6# => romdata <= X"0000FFFF";
when 16#000E7# => romdata <= X"5AC3FFFF";
when 16#000E8# => romdata <= X"0000A53C";
when 16#000E9# => romdata <= X"01510882";
when 16#000EA# => romdata <= X"F4D908FD";
when 16#000EB# => romdata <= X"9B6F7A46";
when 16#000EC# => romdata <= X"C721271D";
when 16#000ED# => romdata <= X"00000000";
when 16#000EE# => romdata <= X"00000000";
when 16#000EF# => romdata <= X"00000000";
when 16#000F0# => romdata <= X"00000000";
when 16#000F1# => romdata <= X"00000000";
when 16#000F2# => romdata <= X"00000000";
when 16#000F3# => romdata <= X"00000000";
when 16#000F4# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
50ae8b81e8fe47a1e1a80c90496c4950
| 0.582976 | 3.088764 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/unisim/ddr_phy_unisim.vhd
| 1 | 118,383 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: ddr_phy_unisim.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Virtex-2 and Virtex-4
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex4 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex4_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0)
);
end;
architecture rtl of virtex4_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute keep of rclk90b : signal is true;
attribute syn_keep : boolean;
attribute syn_keep of rclk90b : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of rclk90b : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddrclkfbl);
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dllfb <= clk_0r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR port map ( Q => ddr_clk_fb_outr, C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclkdiffio : if phyiconf = 0 generate
ddrclocks0 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad_ds generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkb(i), ddr_clkl(i), '1');
end generate;
end generate;
ddrclknodiffio : if phyiconf = 1 generate
ddrclocks1 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk1_pad : outpad generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclk1b_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), -- 1-bit output for negative edge of clock
C => rclk90b, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
--use unisim.BUFG;
--use unisim.DCM;
--use unisim.FDDRRSE;
--use unisim.IFDDRRSE;
--use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrv2;
------------------------------------------------------------------
-- Virtex2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex2_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex2_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component oddrv2
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of FDDRRSE : component is true;
attribute syn_noprune of IFDDRRSE : component is true;
attribute syn_noprune of oddrv2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : FDDRRSE port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : FDDRRSE port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : FDDRRSE port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2 port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IFDDRRSE
port map ( Q0 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q1 => dqin(i), -- 1-bit output for negative edge of clock
C0 => rclk90b, -- clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C1 => rclk270b, -- clk90r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dq(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
-- dinq1 : FD port map ( Q => dqin(i+dbits), C => clk90r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrv2
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => open); -- o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR2;
use unisim.IDDR2;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrc3e;
------------------------------------------------------------------
-- Spartan3E DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity spartan3e_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of spartan3e_ddr_phy is
component oddrc3e
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
attribute syn_noprune of oddrc3e : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r;
-- clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR2 port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2 port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2 port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
clkread <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map ( Q0 => dqinl(i), Q1 => dqin(i), C0 => rclk90b, C1 => rclk270b,
CE => vcc, D => ddr_dqin(i), R => gnd, S => gnd );
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrc3e
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDELAY;
use unisim.IDELAYE2;
use unisim.PLLE2_ADV;
use unisim.ISERDES;
use unisim.BUFIO;
use unisim.IDELAYCTRL;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex5 DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity virtex5_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0; ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := virtex5; odten : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0; abits: integer := 14; nclk: integer := 3;
ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of virtex5_ddr2_phy_wo_pads is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component OBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port (
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component IDELAYE2
generic (
CINVCTRL_SEL : string := "FALSE";
DELAY_SRC : string := "IDATAIN";
HIGH_PERFORMANCE_MODE : string := "FALSE";
IDELAY_TYPE : string := "FIXED";
IDELAY_VALUE : integer := 0;
PIPE_SEL : string := "FALSE";
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
LD : in std_ulogic;
LDPIPEEN : in std_ulogic;
REGRST : in std_ulogic
);
end component;
signal dllfbout, dllfbin, refdllfbout, refdllfbin, ddrdllfbout, ddrdllfbin : std_logic;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal cbdqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_rasnr2, ddr_casnr2, ddr_wenr2 : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(nclk-1 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(ncs-1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin, ddr_dqin_nodel, ddr_dqintemp : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_cbdqin, ddr_cbdqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqout : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqoen : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_adr : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_adr2 : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar2 : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr data mask
signal ddr_cbdmr : std_logic_vector (dbits/8-1 downto 0); -- ddr checkbit mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_cbdqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk, dqsclkn : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
signal clk200, clk200_0, clk200fb, clk200fx, lock200 : std_logic;
signal odtl : std_logic_vector(ncs-1 downto 0);
signal refclk_rdy : std_logic_vector(numidelctrl-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
type ddelay_type is array (0 to 11) of integer;
constant ddelay : ddelay_type := (ddelayb0, ddelayb1, ddelayb2,
ddelayb3, ddelayb4, ddelayb5,
ddelayb6, ddelayb7, ddelayb8,
ddelayb9, ddelayb10, ddelayb11);
attribute syn_noprune : boolean;
attribute syn_noprune of IDELAYCTRL : component is true;
attribute syn_keep : boolean;
attribute syn_keep of dqsclk : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of dqsclk : signal is true;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
attribute keep : boolean;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
signal clk_180temp : std_logic;
begin
-- Generate 200 MHz ref clock if not supplied
refclkx : if norefclk = 0 generate
buf_clk200 : BUFG port map( I => clkref200, O => clk200);
lock200 <= '1';
end generate;
norefclkx : if norefclk /= 0 generate
bufg0 : BUFG port map (I => clk200fx, O => clk200);
HMODE_dll200 : if (tech = virtex4 and MHz >= 210) or (tech = virtex5) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
LMODE_dll200 : if not ((tech = virtex4 and MHz >= 210) or (tech = virtex5) or
tech = virtex7 or tech = kintex7 or tech = artix7 or tech = zynq7000) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
V7_refdll : if (tech = virtex7 or tech = kintex7 or tech = artix7 or tech = zynq7000) generate
bufg0_fb : BUFG port map (I => refdllfbout, O => refdllfbin);
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 1200/MHz, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000.0/real(MHz),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 6,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk200fx,
CLKOUT1 => open, -- actually is only 20 degrees (see CLKOUT1_PHASE)
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => refdllfbout,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => lock200,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => dll0rst(0),
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => refdllfbin
);
end generate;
end generate;
-- Delay control
idelctrl : for i in 0 to numidelctrl-1 generate
u : IDELAYCTRL port map (rst => dllrst(0), refclk => clk200, rdy => refclk_rdy(i));
end generate;
oe <= not oen;
vcc <= '1';
gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
--dll0rst <= dllrst;
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
HMODE_dllm : if (tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
LMODE_dllm : if not ((tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120))) or
tech = virtex7 or tech = kintex7 or tech = artix7 or tech = zynq7000) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
V7_ddrdll : if (tech = virtex7 or tech = kintex7 or tech = artix7 or tech = zynq7000) generate
bufg1_fb : BUFG port map (I => ddrdllfbout, O => ddrdllfbin);
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000.0/real(MHz),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => mclkfx,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => ddrdllfbout,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => mlock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => dll0rst(0),
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => ddrdllfbin
);
end generate;
end generate;
-- DDR clock generation
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
clkout <= mclk;
dllfb <= clk90r;
HMODE_dll : if (tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120)) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk180r <= not mclk;
end generate;
LMODE_dll : if not ((tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120))
or tech = virtex7 or tech = kintex7 or tech = artix7 or tech = zynq7000) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk180r <= not mclk;
end generate;
V7_dll : if (tech = virtex7 or tech = kintex7 or tech = artix7 or tech = zynq7000) generate
bufg2 : BUFG port map (I => dllfbout, O => dllfbin);
bufg3 : BUFG port map (I => clk_180temp, O => clk180r);
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 9, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000.0/real(MHz*clk_mul/clk_div),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 1,
CLKOUT1_DIVIDE => 9,
CLKOUT2_DIVIDE => 9,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 180.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => open,
CLKOUT1 => clk_90ro,
CLKOUT2 => clk_180temp,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => dllfbout,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => lockl,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => mclk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => dllrst(0),
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => dllfbin
);
end generate;
rstdel : process (mclk, rst, mlock, lock200)
begin
if rst = '0' or mlock = '0' or lock200 = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
--rcnt : process (clk_0r)
rcnt : process (clkoutret)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
--if rising_edge(clk_0r) then
if rising_edge(clkoutret) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked and orv(refclk_rdy);
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR port map ( Q => ddr_clk(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddr_clkb(i) <= '0'; -- unused
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
odtl(i) <= locked and orv(refclk_rdy) and odt(i);
ddr_odt(i) <= odtl(i);
end generate;
ddrbanks : for i in 0 to ncs-1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk180r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
ddr_csb(i) <= ddr_csnr(i);
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk180r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
ddr_cke(i) <= ddr_ckenr(i);
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk180r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
ddr_rasb <= ddr_rasnr;
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk180r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
ddr_casb <= ddr_casnr;
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk180r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
ddr_web <= ddr_wenr;
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clkoutret, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
end generate;
ddr_dm <= ddr_dmr;
bagen : for i in 0 to 1+eightbanks generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk180r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
end generate;
ddr_ba <= ddr_bar;
dagen : for i in 0 to abits-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk180r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
end generate;
ddr_ad <= ddr_adr;
-- DQS generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
--D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
D1 => dqsn(i), D2 => gnd, R => gnd, S => gnd);
doen_reg : FD port map ( Q => ddr_dqsoen_reg(i), C => clk180r, D => dqsoen);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk90r, D => ddr_dqsoen_reg(i));
end generate;
ddr_dqs_out <= ddr_dqsin;
ddr_dqs_oen <= ddr_dqsoen;
ddr_dqsoutl <= ddr_dqs_in;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
idelay_v4: if (tech = virtex4 or tech = virtex5 or tech = virtex6) generate
del_dq0 : IDELAY generic map(IOBDELAY_TYPE => "VARIABLE", IOBDELAY_VALUE => ddelay(i/8))
port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clkoutret, CE => cal_en(i/8),
INC => cal_inc(i/8), RST => cal_rst);
end generate;
idelay_v7: if (tech = virtex7 or tech = kintex7 or tech = artix7 or tech = zynq7000) generate
del_dq0 : IDELAYE2 generic map(CINVCTRL_SEL => "FALSE", DELAY_SRC => "IDATAIN",
HIGH_PERFORMANCE_MODE => "TRUE", IDELAY_TYPE => "VARIABLE", IDELAY_VALUE => ddelay(i/8),
PIPE_SEL => "FALSE", REFCLK_FREQUENCY => 200.0, SIGNAL_PATTERN => "DATA")
port map(
CNTVALUEOUT => open, DATAOUT => ddr_dqintemp(i), C => clkoutret, CE => cal_en(i/8), CINVCTRL => '0',
CNTVALUEIN => "00000", DATAIN => '0', IDATAIN => ddr_dqin_nodel(i), INC => cal_inc(i/8), LD => cal_rst,
LDPIPEEN => '0', REGRST => '0');
del_dq1 : IDELAYE2 generic map(CINVCTRL_SEL => "FALSE", DELAY_SRC => "DATAIN",
HIGH_PERFORMANCE_MODE => "TRUE", IDELAY_TYPE => "VARIABLE", IDELAY_VALUE => ddelay(i/8),
PIPE_SEL => "FALSE", REFCLK_FREQUENCY => 200.0, SIGNAL_PATTERN => "DATA")
port map(
CNTVALUEOUT => open, DATAOUT => ddr_dqin(i), C => clkoutret, CE => cal_en(i/8), CINVCTRL => '0',
CNTVALUEIN => "00000", DATAIN => ddr_dqintemp(i), IDATAIN => '0', INC => cal_inc(i/8), LD => cal_rst,
LDPIPEEN => '0', REGRST => '0');
end generate;
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), --dqin(i), -- 1-bit output for negative edge of clock
C => clk180r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => clkoutret, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clkoutret, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD
generic map (INIT => '1')
port map ( Q => ddr_dqoen(i), C => clkoutret, D => oen);
end generate;
ddr_dq_out <= ddr_dqout;
ddr_dq_oen <= ddr_dqoen;
ddr_dqin_nodel <= ddr_dq_in;
end;
------------------------------------------------------------------
-- Spartan 3A DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.BUFIO;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan3a_ddr2_phy is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan3;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of spartan3a_ddr2_phy is
component DCM
generic (CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false);
port ( CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal ddr_clk_fbl, ddr_clk_fb_outl : std_ulogic;
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal rclk0b, rclk90b, rclk180b, rclk270b : std_ulogic;
signal rclk0, rclk90, rclk180, rclk270 : std_ulogic;
signal rclk0b_high, rclk90b_high, rclk270b_high : std_ulogic;
signal rclk0_high, rclk90_high, rclk270_high : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr row address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr bank address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqinl : std_logic_vector (dbits*2-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_ulogic;
signal dll1rst : std_ulogic;
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal odtl : std_logic_vector(1 downto 0);
--signals needed for alignment with DQS
signal dm_delay : std_logic_vector (dbits/8-1 downto 0);
signal dqout_delay : std_logic_vector (dbits-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= '1';
elsif rising_edge(clk) then
dll0rst <= '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM
generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64)
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
rstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2
port map (Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2
port map (Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
-- Generate the DDR clock to be fed back for DQ synchronization
dclkfb0r : ODDR2
port map (Q => ddr_clk_fb_outl, C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclkfb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outl);
-- The above clock fed back for DQ synchronization
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddr_clk_fbl);
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and odt(i);
ddr_odt_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_odt(i), odtl(i));
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to 1 generate
csn0gen : FD
port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD
port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : FD
port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD
port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_casb, ddr_casnr);
wengen : FD
port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_web, ddr_wenr);
bagen : for i in 0 to 1+eightbanks generate
ba0 : FD
port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
addrgen : for i in 0 to 13 generate
addr0 : FD
port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dq_delay : FD
port map ( Q => dm_delay(i), C => clk0r, D => dm(i));
dm0 : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dmr(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm_delay(i), R => gnd, S => gnd);
ddr_bm_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR2
port map ( Q => ddr_dqsin(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd);
doen : FD
port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad_ds
generic map (tech => virtex5, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i => ddr_dqsin(i),
en => ddr_dqsoen(i), o => ddr_dqsoutl(i));
end generate;
-- Phase shift the feedback clock and use it to latch DQ
rstphase : process (ddr_clk_fbl, rst, lockl)
begin
if rst = '0' or lockl = '0' then
dll1rst <= '1';
elsif rising_edge(ddr_clk_fbl) then
dll1rst <= '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg8 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
bufg9 : BUFG port map (I => rclk180, O => rclk180b);
read_dll : DCM
generic map (clkin_period => 8.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "VARIABLE", PHASE_SHIFT => rskew)
port map ( CLKIN => ddr_clk_fbl, CLKFB => rclk90b, DSSEN => gnd, PSCLK => mclk,
PSEN => cal_pll(0), PSINCDEC => cal_pll(1), RST => dll1rst, CLK0 => rclk90,
CLK90 => rclk180); --, CLK180 => rclk270);
-- Data bus
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map (Q0 => dqinl(i+dbits), -- 1-bit output for positive edge of C0
Q1 => dqinl(i), -- 1-bit output for negative edge of C1
C0 => rclk90b, -- 1-bit clock input
C1 => rclk270b, -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd); -- 1-bit set
dinq0 : FD
port map ( Q => dqin(i+dbits), C => rclk180b, D => dqinl(i));
dinq1 : FD
port map ( Q => dqin(i), C => rclk180b, D => dqinl(i+dbits));
dq_delay : FD
port map ( Q => dqout_delay(i), C => clk0r, D => dqout(i));
dout : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dqout(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout_delay(i), R => gnd, S => gnd);
doen : FD
port map (Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad
generic map (tech => virtex4, level => sstl18_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
------------------------------------------------------------------
-- Spartan 6 DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM_SP;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.IODELAY2;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan6_ddr2_phy_wo_pads is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan6;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3; ncs : integer := 2 );
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0));
end;
architecture rtl of spartan6_ddr2_phy_wo_pads is
component DCM_SP is
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false );
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK2X180 : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
CLKFX : out std_ulogic;
CLKFX180 : out std_ulogic;
LOCKED : out std_ulogic;
PSDONE : out std_ulogic;
STATUS : out std_logic_vector(7 downto 0);
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
DSSEN : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
RST : in std_ulogic );
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component IODELAY2 is
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75 );
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic );
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal dqsoen_reg : std_logic_vector(dbits/8-1 downto 0);
signal ddr_dq_indel : std_logic_vector(dbits-1 downto 0);
signal ckel : std_logic_vector(ncs-1 downto 0);
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal delay_cal : std_ulogic;
signal dcal_started : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mclk <= clk;
-- mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
-- Extend DCM reset signal.
dll0rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & "0";
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM_SP
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "1X", CLKIN_PERIOD => 1000.0/real(MHz) )
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM_SP
generic map ( CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64 )
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
-- Extend DCM reset signal.
dllrstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & "0";
end if;
end process;
-- Delay lock signal.
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR2
port map ( Q => ddr_clk(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd );
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to ncs-1 generate
ddr_odt(i) <= locked and odt(i);
csn0gen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_csb(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => csn(i), D1 => csn(i), R => gnd, S => gnd );
ckel(i) <= cke(i) and locked;
ckegen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_cke(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ckel(i), D1 => ckel(i), R => gnd, S => gnd );
end generate;
rasgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_rasb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => rasn, D1 => rasn, R => gnd, S => gnd );
casgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_casb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => casn, D1 => casn, R => gnd, S => gnd );
wengen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_web, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => wen, D1 => wen, R => gnd, S => gnd );
bagen : for i in 0 to 1+eightbanks generate
ba0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ba(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ba(i), D1 => ba(i), R => gnd, S => gnd );
end generate;
addrgen : for i in 0 to abits-1 generate
addr0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ad(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => addr(i), D1 => addr(i), R => gnd, S => gnd );
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dmgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dm(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm(i), R => gnd, S => gnd );
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dqsreg : FD
port map ( Q => dqsn(i), C => clk180r, D => oe );
dqsgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_out(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd );
doenreg : FD
port map ( Q => dqsoen_reg(i), C => clk180r, D => dqsoen );
doen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_oen(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsoen_reg(i), D1 => dqsoen_reg(i), R => gnd, S => gnd );
end generate;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
dqdelay : IODELAY2
generic map ( DATA_RATE => "DDR", DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO" )
port map ( BUSY => open, CAL => delay_cal, CE => cal_en(i/8), CLK => clk0r,
DATAOUT => ddr_dq_indel(i), DATAOUT2 => open, DOUT => open,
IDATAIN => ddr_dq_in(i), INC => cal_inc(i/8),
IOCLK0 => clk0r, IOCLK1 => clk180r,
ODATAIN => gnd, RST => cal_rst, T => vcc, TOUT => open );
din : IDDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( D => ddr_dq_indel(i), C0 => clk0r, C1 => clk180r, CE => vcc,
R => gnd, S => gnd, Q0 => dqin(i), Q1 => dqin(i+dbits) );
dout : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_out(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout(i), R => gnd, S => gnd );
doen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_oen(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => oen, D1 => oen, R => gnd, S => gnd );
end generate;
-- Generate IODELAY calibration command after core reset.
calcmd : process (mclk, rst)
begin
if rst = '0' then
dcal_started <= '0';
delay_cal <= '0';
elsif rising_edge(mclk) then
if mlock = '1' then
dcal_started <= '1';
delay_cal <= not dcal_started;
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
78b36e7d8c8925874f402db7c124079f
| 0.541209 | 3.384305 | false | false | false | false |
rhexsel/cmips
|
cMIPS/vhdl/ram.vhd
| 1 | 14,316 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- To simplify (and accelerate) internal address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address that is larger the RAM capacity. Otherwise, the
-- base must be subtracted from the address on every reference,
-- which means having an adder in the critical path. Bad idea.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous RAM for synthesis; NON-initialized, byte-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity RAM is
generic (LOAD_FILE_NAME : string := "data.bin";
DUMP_FILE_NAME : string := "dump.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
wr : in std_logic; -- active in '0'
strobe : in std_logic; -- active in '1'
addr : in reg32;
data_inp : in reg32;
data_out : out reg32;
byte_sel : in reg4;
dump_ram : in std_logic); -- dump RAM contents
-- simulation version
constant DATA_ADDRS_BITS : natural := log2_ceil(DATA_MEM_SZ);
-- FPGA version
constant N_WORDS : natural := 8192;
constant ADDRS_BITS : natural := log2_ceil(N_WORDS);
subtype ram_address is integer range 0 to N_WORDS-1;
subtype ram_addr_bits is std_logic_vector(ADDRS_BITS-1 downto 0);
end entity RAM;
architecture rtl of RAM is
component mf_ram1port
generic (N_WORDS : integer; ADDRS_BITS : integer);
port (address : in std_logic_vector (ADDRS_BITS-1 downto 0);
clken : in std_logic;
clock : in std_logic;
data : in std_logic_vector (7 downto 0);
wren : in std_logic;
q : out std_logic_vector (7 downto 0));
end component mf_ram1port;
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
signal we0,we1,we2,we3 : std_logic := '0';
signal di,do : reg32;
signal r_addr : ram_address := 0;
signal r_address : ram_addr_bits;
signal waiting, enable : std_logic;
begin -- rtl
U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
enable <= not(sel);
-- CPU acesses are word-addressed; RAM is byte-addressed, 4-bytes wide
r_addr <= to_integer( unsigned(addr( (ADDRS_BITS-1+2) downto 2 ) ) );
r_address <= addr( ADDRS_BITS-1+2 downto 2 );
U_ram0: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(7 downto 0), we0, do(7 downto 0));
U_ram1: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(15 downto 8), we1, do(15 downto 8));
U_ram2: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(23 downto 16), we2, do(23 downto 16));
U_ram3: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(31 downto 24), we3, do(31 downto 24));
accessRAM: process(sel, strobe, wr, r_addr, byte_sel, data_inp, do)
begin
if sel = '0' then
if wr = '0' then -- WRITE to MEM
assert (r_addr >= 0) and (r_addr < (DATA_MEM_SZ/4))
report "ramWR index out of bounds: " & natural'image(r_addr)
severity failure;
case byte_sel is -- partial word stores
when b"1111" => -- SW
we3 <= '1';
we2 <= '1';
we1 <= '1';
we0 <= '1';
di <= data_inp;
when b"1100" => -- SH, upper
we3 <= '1';
we2 <= '1';
we1 <= '0';
we0 <= '0';
di(31 downto 16) <= data_inp(15 downto 0);
di(15 downto 0) <= (others => 'X');
when b"0011" => -- SH. lower
we3 <= '0';
we2 <= '0';
we1 <= '1';
we0 <= '1';
di(15 downto 0) <= data_inp(15 downto 0);
di(31 downto 16) <= (others => 'X');
when b"0001" => -- SB
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '1';
di(7 downto 0) <= data_inp(7 downto 0);
di(31 downto 8) <= (others => 'X');
when b"0010" =>
we3 <= '0';
we2 <= '0';
we1 <= '1';
we0 <= '0';
di(31 downto 16) <= (others => 'X');
di(15 downto 8) <= data_inp(7 downto 0);
di(7 downto 0) <= (others => 'X');
when b"0100" =>
we3 <= '0';
we2 <= '1';
we1 <= '0';
we0 <= '0';
di(31 downto 24) <= (others => 'X');
di(23 downto 16) <= data_inp(7 downto 0);
di(15 downto 0) <= (others => 'X');
when b"1000" =>
we3 <= '1';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di(31 downto 24) <= data_inp(7 downto 0);
di(23 downto 0) <= (others => 'X');
when others =>
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
end case;
assert TRUE report "ramWR["& natural'image(r_addr) &"] "
& SLV32HEX(data_inp) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
data_out <= (others => 'X');
else -- READ from MEM, wr /= 0
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
assert (r_addr >= 0) and (r_addr < (DATA_MEM_SZ/4))
report "ramRD index out of bounds: " & natural'image(r_addr)
severity failure;
-- byte/half selection done at CPU
data_out(31 downto 24) <= do(31 downto 24);
data_out(23 downto 16) <= do(23 downto 16);
data_out(15 downto 8) <= do(15 downto 8);
data_out(7 downto 0) <= do(7 downto 0);
assert TRUE report "ramRD["& natural'image(r_addr) &"] "
& SLV32HEX(do) &" bySel="& SLV2STR(byte_sel); -- DEBUG
end if; -- wr
else -- sel /= 0
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
data_out <= (others => 'X');
end if;
end process accessRAM;
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous RAM; initialization Data loaded at CPU reset, byte-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simulation of RAM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
constant WAIT_COUNT : max_wait_states := NUM_MAX_W_STS - RAM_WAIT_STATES;
signal wait_counter, ram_current : integer;
subtype t_address is unsigned((DATA_ADDRS_BITS - 1) downto 0);
subtype word is std_logic_vector(7 downto 0);
type storage_array is
array (natural range 0 to (DATA_MEM_SZ - 1)) of word;
signal storage : storage_array;
signal enable, waiting, do_wait : std_logic;
begin -- simulation
U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
enable <= not(sel); -- and not(waiting);
accessRAM: process(strobe,enable, wr,rst, addr,byte_sel, data_inp,dump_ram)
variable u_addr : t_address;
variable index, latched : natural;
type binary_file is file of integer;
file load_file: binary_file open read_mode is LOAD_FILE_NAME;
variable datum: integer;
variable s_datum: unsigned(31 downto 0);
file dump_file: binary_file open write_mode is DUMP_FILE_NAME;
variable d : reg32 := (others => 'X');
variable val, i : integer;
begin
if rst = '0' then -- reset, read-in binary initialized data
index := 0; -- byte indexed
for i in 0 to (DATA_MEM_SZ - 1) loop
if not endfile(load_file) then
read(load_file, datum);
s_datum := to_unsigned(datum, 32);
assert TRUE report "ramINIT["& natural'image(index*4)&"]= " &
SLV32HEX(std_logic_vector(s_datum)); -- DEBUG
storage(index+3) <= std_logic_vector(s_datum(31 downto 24));
storage(index+2) <= std_logic_vector(s_datum(23 downto 16));
storage(index+1) <= std_logic_vector(s_datum(15 downto 8));
storage(index+0) <= std_logic_vector(s_datum(7 downto 0));
index := index + 4;
end if;
end loop;
data_out <= (others=>'X');
else -- (rst = '1'), normal operation
if sel = '0' and wr = '0' and rising_edge(strobe) then
-- only access RAM if address is valid (sel = '0')
u_addr := unsigned(addr( (DATA_ADDRS_BITS-1) downto 0 ) );
index := to_integer(u_addr);
assert (index >= 0) and (index < DATA_MEM_SZ)
report "ramWR index out of bounds: " & natural'image(index)
severity failure;
case byte_sel is
when b"1111" => -- SW
storage(index+3) <= data_inp(31 downto 24);
storage(index+2) <= data_inp(23 downto 16);
storage(index+1) <= data_inp(15 downto 8);
storage(index+0) <= data_inp(7 downto 0);
when b"1100" | b"0011" => -- SH
storage(index+1) <= data_inp(15 downto 8);
storage(index+0) <= data_inp(7 downto 0);
when b"0001" | b"0010" | b"0100" | b"1000" => -- SB
storage(index+0) <= data_inp(7 downto 0);
when others => null;
end case;
assert TRUE report "ramWR["& natural'image(index) &"] "
& SLV32HEX(data_inp) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
end if; -- is write?
if sel = '0' and wr = '1' then
-- only access RAM if address is valid (sel = '0')
u_addr := unsigned(addr( (DATA_ADDRS_BITS-1) downto 0 ) );
index := to_integer(u_addr);
assert (index >= 0) and (index < DATA_MEM_SZ)
report "ramRD index out of bounds: " & natural'image(index)
severity failure;
case byte_sel is
when b"1111" => -- LW
d(31 downto 24) := storage(index+3);
d(23 downto 16) := storage(index+2);
d(15 downto 8) := storage(index+1);
d(7 downto 0) := storage(index+0);
when b"1100" => -- LH top-half
d(31 downto 24) := storage(index+1);
d(23 downto 16) := storage(index+0);
d(15 downto 0) := (others => 'X');
when b"0011" => -- LH bottom-half
d(31 downto 16) := (others => 'X');
d(15 downto 8) := storage(index+1);
d(7 downto 0) := storage(index+0);
when b"0001" => -- LB top byte
d(31 downto 8) := (others => 'X');
d(7 downto 0) := storage(index+0);
when b"0010" => -- LB mid-top byte
d(31 downto 16) := (others => 'X');
d(15 downto 8) := storage(index+0);
d(7 downto 0) := (others => 'X');
when b"0100" => -- LB mid-bot byte
d(31 downto 24) := (others => 'X');
d(23 downto 16) := storage(index+0);
d(15 downto 0) := (others => 'X');
when b"1000" => -- LB bottom byte
d(31 downto 24) := storage(index+0);
d(23 downto 0) := (others => 'X');
when others => d := (others => 'X');
end case;
assert TRUE report "ramRD["& natural'image(index) &"] "
& SLV32HEX(d) &" bySel="& SLV2STR(byte_sel); -- DEBUG
elsif rising_edge(dump_ram) then
i := 0;
while i < DATA_MEM_SZ-4 loop
d(31 downto 24) := storage(i+3);
d(23 downto 16) := storage(i+2);
d(15 downto 8) := storage(i+1);
d(7 downto 0) := storage(i+0);
write( dump_file, to_integer(signed(d)) );
i := i+4;
end loop; -- i
else
d := (others=>'X');
end if; -- is read?
data_out <= d;
end if; -- is reset?
end process accessRAM; -- ---------------------------------------------
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
9068464238031e552caea69110ee5d83
| 0.485401 | 3.645531 | false | false | false | false |
rhexsel/cmips
|
cMIPS/vhdl/core.vhd
| 1 | 125,833 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- CPU core
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
use work.p_exception.all;
entity core is
port (
rst : in std_logic;
clk : in std_logic;
phi1 : in std_logic;
phi2 : in std_logic;
phi3 : in std_logic;
i_aVal : out std_logic;
i_wait : in std_logic;
i_addr : out reg32;
instr : in reg32;
d_aVal : out std_logic;
d_wait : in std_logic;
d_addr : out reg32;
data_inp : in reg32;
data_out : out reg32;
wr : out std_logic;
b_sel : out reg4;
busFree : out std_logic;
nmi : in std_logic;
irq : in reg6;
i_busErr : in std_logic;
d_busErr : in std_logic);
end core;
architecture rtl of core is
-- control pipeline registers ------------
component reg_excp_IF_RF is
port(clk, rst, ld: in std_logic;
IF_excp_type: in exception_type;
RF_excp_type: out exception_type;
PC_abort: in boolean;
RF_PC_abort: out boolean;
IF_PC: in std_logic_vector;
RF_PC: out std_logic_vector);
end component reg_excp_IF_RF;
component reg_excp_RF_EX is
port(clk, rst, ld: in std_logic;
RF_cop0_reg: in reg5;
EX_cop0_reg: out reg5;
RF_cop0_sel: in reg3;
EX_cop0_sel: out reg3;
RF_can_trap: in std_logic_vector;
EX_can_trap: out std_logic_vector;
RF_exception: in exception_type;
EX_exception: out exception_type;
RF_is_delayslot: in std_logic;
EX_is_delayslot: out std_logic;
RF_PC_abort: in boolean;
EX_PC_abort: out boolean;
RF_PC: in std_logic_vector;
EX_PC: out std_logic_vector;
RF_trap_taken: in boolean;
EX_trapped: out boolean);
end component reg_excp_RF_EX;
component reg_excp_EX_MM is
port(clk, rst, ld: in std_logic;
EX_cop0_reg: in reg5;
MM_cop0_reg: out reg5;
EX_cop0_sel: in reg3;
MM_cop0_sel: out reg3;
EX_PC: in std_logic_vector;
MM_PC: out std_logic_vector;
EX_v_addr: in std_logic_vector;
MM_v_addr: out std_logic_vector;
EX_nullify: in boolean;
MM_nullify: out boolean;
EX_addrError: in boolean;
MM_addrError: out boolean;
EX_addrErr_stage_mm: in boolean;
MM_addrErr_stage_mm: out boolean;
EX_is_delayslot: in std_logic;
MM_is_delayslot: out std_logic;
EX_trapped: in boolean;
MM_trapped: out boolean;
EX_ll_sc_abort: in boolean;
MM_ll_sc_abort: out boolean;
EX_tlb_exception: in boolean;
MM_tlb_exception: out boolean;
EX_tlb_stage_MM: in boolean;
MM_tlb_stage_MM: out boolean;
EX_int_req: in reg6;
MM_int_req: out reg6;
EX_is_SC: in boolean;
MM_is_SC: out boolean;
EX_is_MFC0: in boolean;
MM_is_MFC0: out boolean;
EX_is_exception: in exception_type;
MM_is_exception: out exception_type);
end component reg_excp_EX_MM;
component reg_excp_MM_WB is
port(clk, rst, ld: in std_logic;
MM_PC: in std_logic_vector;
WB_PC: out std_logic_vector;
MM_cop0_LLbit: in std_logic;
WB_cop0_LLbit: out std_logic;
MM_is_delayslot: in std_logic;
WB_is_delayslot: out std_logic;
MM_cop0_val: in std_logic_vector;
WB_cop0_val: out std_logic_vector);
end component reg_excp_MM_WB;
signal nullify_MM_pre, nullify_MM_int :std_logic;
signal annul_1, annul_2, annul_twice : std_logic;
signal interrupt, exception_stall : std_logic;
signal dly_i0, dly_i1, dly_i2, dly_interr: std_logic;
signal exception_taken, interrupt_taken, tlb_excp_taken : std_logic;
signal nullify_fetch, nullify, MM_nullify : boolean;
signal addrError, MM_addrError, abort_ref, MM_ll_sc_abort : boolean;
signal PC_abort, RF_PC_abort, EX_PC_abort : boolean;
signal IF_excp_type,RF_excp_type : exception_type;
signal mem_excp_type, tlb_excp_type : exception_type;
signal trap_instr: instr_type;
signal RF_PC,EX_PC,MM_PC,WB_PC, LLaddr: reg32;
signal ll_sc_bit, MM_LLbit,WB_LLbit: std_logic;
signal LL_update, LL_SC_abort, LL_SC_differ: std_logic;
signal EX_trapped, MM_trapped, EX_ovfl, trap_taken: boolean;
signal int_req, MM_int_req: reg6;
signal can_trap,EX_can_trap : reg2;
signal is_trap, tr_signed, tr_stall: std_logic;
signal tr_is_equal, tr_less_than: std_logic;
signal tr_fwd_A, tr_fwd_B, tr_result : reg32;
signal excp_IF_RF_ld,excp_RF_EX_ld,excp_EX_MM_ld,excp_MM_WB_ld: std_logic;
signal update, not_stalled: std_logic;
signal update_reg : reg5;
signal status_update,epc_update,compare_update: std_logic;
signal disable_count, compare_set, compare_clr: std_logic;
signal STATUSinp, STATUS, CAUSE, EPCinp,EPC : reg32;
signal COUNT, COMPARE : reg32;
signal count_eq_compare,count_update,count_enable : std_logic;
signal exception,EX_exception, MM_exception : exception_type;
signal is_exception, EX_is_exception : exception_type;
signal ExcCode : reg5 := cop0code_NULL;
signal exception_dec,TLB_excp_num,trap_dec: integer; -- debugging
signal RF_is_delayslot,EX_is_delayslot,MM_is_delayslot,WB_is_delayslot,is_delayslot : std_logic;
signal cop0_sel, EX_cop0_sel, MM_cop0_sel, epc_source : reg3;
signal cop0_reg,EX_cop0_reg,MM_cop0_reg : reg5;
signal cop0_inp, RF_cop0_val,MM_cop0_val,WB_cop0_val : reg32;
signal BadVAddr, BadVAddr_inp : reg32;
signal BadVAddr_update : std_logic;
signal is_SC, MM_is_SC, is_MFC0, MM_is_MFC0 : boolean;
signal is_busError, is_nmi, is_interr, is_ovfl : boolean;
signal busError_type : exception_type;
-- MMU signals --
signal INDEX, index_inp, RANDOM, WIRED, wired_inp : reg32;
signal index_update, wired_update : std_logic;
signal EntryLo0, EntryLo1, EntryLo0_inp, EntryLo1_inp : reg32;
signal EntryHi, EntryHi_inp, v_addr, MM_v_addr : reg32;
signal Context, PageMask, PageMask_inp : reg32;
signal entryLo0_update, entryLo1_update, entryHi_update : std_logic;
signal context_upd_pte, context_upd_bad, tlb_read, tlb_ex_2 : std_logic;
signal tlb_entrylo0_mm, tlb_entrylo1_mm, tlb_entryhi : reg32;
signal tlb_tag0_updt, tlb_tag1_updt, tlb_tag2_updt, tlb_tag3_updt : std_logic;
signal tlb_tag4_updt, tlb_tag5_updt, tlb_tag6_updt, tlb_tag7_updt : std_logic;
signal tlb_dat0_updt, tlb_dat1_updt, tlb_dat2_updt, tlb_dat3_updt : std_logic;
signal tlb_dat4_updt, tlb_dat5_updt, tlb_dat6_updt, tlb_dat7_updt : std_logic;
signal hit0_pc, hit1_pc, hit2_pc, hit3_pc, hit_pc : boolean;
signal hit4_pc, hit5_pc, hit6_pc, hit7_pc : boolean;
signal hit0_mm, hit1_mm, hit2_mm, hit3_mm, hit_mm : boolean;
signal hit4_mm, hit5_mm, hit6_mm, hit7_mm: boolean;
signal tlb_exception,MM_tlb_exception,tlb_stage_mm,MM_tlb_stage_mm : boolean;
signal addrErr_stage_mm, MM_addrErr_stage_mm : boolean;
signal hit_mm_v, hit_mm_d, hit_pc_v : std_logic;
signal tlb_adr_mm : MMU_idx_bits;
signal tlb_probe, probe_hit, hit_mm_bit : std_logic;
signal mm, tlb_excp_VA : std_logic_vector(VA_HI_BIT downto VA_LO_BIT);
signal tlb_adr,tlb_a0_pc,tlb_a1_pc,tlb_a2_pc : natural range 0 to (MMU_CAPACITY-1);
signal hit_pc_adr, hit_mm_adr : natural range 0 to (MMU_CAPACITY-1);
signal tlb_a0_mm,tlb_a1_mm,tlb_a2_mm : natural range 0 to (MMU_CAPACITY-1);
signal tlb_ppn_pc0,tlb_ppn_pc1 : mmu_dat_reg;
signal tlb_ppn_mm0,tlb_ppn_mm1 : mmu_dat_reg;
signal tlb_ppn_mm, tlb_ppn_pc : std_logic_vector(PPN_BITS - 1 downto 0);
signal tlb_tag0, tlb_tag1, tlb_tag2, tlb_tag3, tlb_tag_inp : reg32;
signal tlb_tag4, tlb_tag5, tlb_tag6, tlb_tag7, e_hi, e_hi_inp : reg32;
signal tlb_dat0_inp, tlb_dat1_inp, e_lo0, e_lo1 : mmu_dat_reg;
signal tlb_dat0_0, tlb_dat1_0, tlb_dat2_0, tlb_dat3_0 : mmu_dat_reg;
signal tlb_dat0_1, tlb_dat1_1, tlb_dat2_1, tlb_dat3_1 : mmu_dat_reg;
signal tlb_dat4_0, tlb_dat5_0, tlb_dat6_0, tlb_dat7_0 : mmu_dat_reg;
signal tlb_dat4_1, tlb_dat5_1, tlb_dat6_1, tlb_dat7_1 : mmu_dat_reg;
signal tlb_entryLo0, tlb_entryLo1, phy_i_addr, phy_d_addr : reg32;
-- other components ------------
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component adder32 is
port(A, B : in std_logic_vector;
C : out std_logic_vector);
end component adder32;
component mf_alt_add_4 IS
port(datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) );
end component mf_alt_add_4;
component mf_alt_adder IS
port(dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component mf_alt_adder;
component subtr32 IS
port(A,B : in std_logic_vector (31 downto 0);
C : out std_logic_vector (31 downto 0);
sgnd : in std_logic;
ovfl,lt : out std_logic);
end component subtr32;
component reg_bank is
port(wrclk, rdclk, wren: in std_logic;
a_rs, a_rt, a_rd: in std_logic_vector;
C: in std_logic_vector;
A, B: out std_logic_vector);
end component reg_bank;
component register32 is
generic (INITIAL_VALUE: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component register32;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component counter32 is
generic (INITIAL_VALUE: std_logic_vector);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component counter32;
component alu is
port(clk, rst: in std_logic;
A, B: in std_logic_vector;
C: out std_logic_vector;
LO: out std_logic_vector;
HI: out std_logic_vector;
wr_hilo: in std_logic;
move_ok: out std_logic;
fun: in t_alu_fun;
postn: in std_logic_vector;
shamt: in std_logic_vector;
ovfl: out std_logic);
end component alu;
signal PC,PC_aligned : reg32;
signal PCinp,PCinp_noExcp, PCincd : reg32;
signal instr_fetched : reg32;
signal PCload, IF_RF_ld : std_logic;
signal PCsel : reg2;
signal excp_PCsel : reg3;
signal rom_stall, iaVal, if_stalled, mem_stall, pipe_stall : std_logic;
signal ram_stall, daVal, mm_stalled : std_logic;
signal br_target, br_addend, br_tgt_pl4, br_tgt_displ, j_target : reg32;
signal RF_PCincd, RF_instruction : reg32;
signal eq_fwd_A,eq_fwd_B : reg32;
signal dbg_jr_stall: integer; -- debugging only
-- register fetch/read and instruction decode --
component reg_IF_RF is
port(clk, rst, ld: in std_logic;
PCincd_d: in std_logic_vector;
PCincd_q: out std_logic_vector;
instr: in std_logic_vector;
RF_instr: out std_logic_vector);
end component reg_IF_RF;
signal opcode, func: reg6;
signal ctrl_word: t_control_type;
signal funct_word: t_function_type;
signal rimm_word: t_rimm_type;
signal syscall_n : reg20;
signal displ16: reg16;
signal br_operand: reg32;
signal br_opr: reg2;
signal br_equal,br_negative,br_eq_zero: boolean;
signal flush_RF_EX: boolean := FALSE;
signal is_branch: std_logic;
signal c_sel : reg2;
-- execution and beyond --
signal RF_EX_ld, EX_MM_ld, MM_WB_ld: std_logic;
signal a_rs,EX_a_rs, a_rt,EX_a_rt,MM_a_rt, a_rd: reg5;
signal a_c,EX_a_c,MM_a_c,WB_a_c: reg5;
signal move,EX_move,MM_move : std_logic;
signal is_load,EX_is_load,MM_is_load : boolean;
signal muxC,EX_muxC,MM_muxC,WB_muxC: reg3;
signal wreg,EX_wreg_pre,EX_wreg,MM_wreg_cond,MM_wreg,WB_wreg: std_logic;
signal aVal,EX_aVal,EX_aVal_cond,MM_aVal: std_logic;
signal wrmem,EX_wrmem,EX_wrmem_cond,MM_wrmem, m_sign_ext: std_logic;
signal mem_t, EX_mem_t,MM_mem_t: reg4;
signal WB_mem_t : reg2;
signal alu_inp_A,alu_fwd_B,alu_inp_B : reg32;
signal alu_move_ok, MM_alu_move_ok, ovfl : std_logic;
signal selB,EX_selB: std_logic;
signal oper,EX_oper: t_alu_fun;
signal EX_postn, shamt,EX_shamt: reg5;
signal regs_A,EX_A,MM_A,WB_A, regs_B,EX_B,MM_B: reg32;
signal displ32,EX_displ32: reg32;
signal result,MM_result,WB_result,WB_C, EX_addr,MM_addr: reg32;
signal pc_p8,EX_pc_p8,MM_pc_p8,WB_pc_p8 : reg32;
signal HI,MM_HI,WB_HI, LO,MM_LO,WB_LO : reg32;
-- data memory --
signal rd_data_raw, rd_data, WB_rd_data, WB_mem_data: reg32;
signal MM_B_data, WB_B_data: reg32;
signal jr_stall, br_stall, sw_stall, lw_stall : std_logic;
signal fwd_lwlr : boolean;
signal fwd_mem, WB_addr2: reg2;
component reg_RF_EX is
port(clk, rst, ld: in std_logic;
selB: in std_logic;
EX_selB: out std_logic;
oper: in t_alu_fun;
EX_oper: out t_alu_fun;
a_rs: in std_logic_vector;
EX_a_rs: out std_logic_vector;
a_rt: in std_logic_vector;
EX_a_rt: out std_logic_vector;
a_c: in std_logic_vector;
EX_a_c: out std_logic_vector;
wreg: in std_logic;
EX_wreg: out std_logic;
muxC: in std_logic_vector;
EX_muxC: out std_logic_vector;
move: in std_logic;
EX_move: out std_logic;
postn: in std_logic_vector;
EX_postn: out std_logic_vector;
shamt: in std_logic_vector;
EX_shamt: out std_logic_vector;
aVal: in std_logic;
EX_aVal: out std_logic;
wrmem: in std_logic;
EX_wrmem: out std_logic;
mem_t: in std_logic_vector;
EX_mem_t: out std_logic_vector;
is_load: in boolean;
EX_is_load: out boolean;
A: in std_logic_vector;
EX_A: out std_logic_vector;
B: in std_logic_vector;
EX_B: out std_logic_vector;
displ32: in std_logic_vector;
EX_displ32: out std_logic_vector;
pc_p8: in std_logic_vector;
EX_pc_p8: out std_logic_vector);
end component reg_RF_EX;
component reg_EX_MM is
port(clk, rst, ld: in std_logic;
EX_a_rt: in std_logic_vector;
MM_a_rt: out std_logic_vector;
EX_a_c: in std_logic_vector;
MM_a_c: out std_logic_vector;
EX_wreg: in std_logic;
MM_wreg: out std_logic;
EX_muxC: in std_logic_vector;
MM_muxC: out std_logic_vector;
EX_aVal: in std_logic;
MM_aVal: out std_logic;
EX_wrmem: in std_logic;
MM_wrmem: out std_logic;
EX_mem_t: in std_logic_vector;
MM_mem_t: out std_logic_vector;
EX_is_load: in boolean;
MM_is_load: out boolean;
EX_A: in std_logic_vector;
MM_A: out std_logic_vector;
EX_B: in std_logic_vector;
MM_B: out std_logic_vector;
EX_result: in std_logic_vector;
MM_result: out std_logic_vector;
EX_addr: in std_logic_vector;
MM_addr: out std_logic_vector;
HI: in std_logic_vector;
MM_HI: out std_logic_vector;
LO: in std_logic_vector;
MM_LO: out std_logic_vector;
EX_alu_move_ok: in std_logic;
MM_alu_move_ok: out std_logic;
EX_move: in std_logic;
MM_move: out std_logic;
EX_pc_p8: in std_logic_vector;
MM_pc_p8: out std_logic_vector);
end component reg_EX_MM;
component reg_MM_WB is
port(clk, rst, ld: in std_logic;
MM_a_c: in std_logic_vector;
WB_a_c: out std_logic_vector;
MM_wreg: in std_logic;
WB_wreg: out std_logic;
MM_muxC: in std_logic_vector;
WB_muxC: out std_logic_vector;
MM_A: in std_logic_vector;
WB_A: out std_logic_vector;
MM_result: in std_logic_vector;
WB_result: out std_logic_vector;
MM_HI: in std_logic_vector;
WB_HI: out std_logic_vector;
MM_LO: in std_logic_vector;
WB_LO: out std_logic_vector;
rd_data: in std_logic_vector;
WB_rd_data: out std_logic_vector;
MM_B_data: in std_logic_vector;
WB_B_data: out std_logic_vector;
MM_addr2: in std_logic_vector;
WB_addr2: out std_logic_vector;
MM_oper: in std_logic_vector;
WB_oper: out std_logic_vector;
MM_pc_p8: in std_logic_vector;
WB_pc_p8: out std_logic_vector);
end component reg_MM_WB;
-- fields of the control table
-- aVal: std_logic; -- addressValid, enable data-mem=0
-- wmem: std_logic; -- READ=1/WRITE=0 in/to memory
-- i: instr_type; -- instruction
-- wreg: std_logic; -- register write=0
-- selB: std_logic; -- B ALU input, reg=0 ext=1
-- fun: std_logic; -- check function_field=1
-- oper: t_alu_fun; -- ALU operation
-- muxC: reg3; -- select result mem=0 ula=1 jr=2 pc+8=3
-- c_sel: reg2; -- select destination reg RD=0 RT=1 31=2
-- extS: std_logic; -- sign-extend=1, zero-ext=0
-- PCsel: reg2; -- PCmux 0=PC+4 1=beq 2=j 3=jr
-- br_t: t_comparison; -- branch: 0=no 1=beq 2=bne
-- excp: reg2 -- stage with exception 0=no,1=rf,2=ex,3=mm
constant ctrl_table : t_control_mem := (
--aVal wmem ins wreg selB fun oper muxC csel extS PCsel br_t excp
('1','1',iALU, '1','0','1',opNOP,"001","00", '0', "00",cNOP,"00"),--ALU=0
('1','1',RIMM, '1','0','0',opNOP,"001","00", '1', "00",cOTH,"00"),--BR=1
('1','1',J, '1','0','0',opNOP,"001","00", '0', "10",cNOP,"00"),--j=2
('1','1',JAL, '0','0','0',opNOP,"011","10", '0', "10",cNOP,"00"),--jal=3
('1','1',BEQ, '1','0','0',opNOP,"001","00", '1', "01",cEQU,"00"),--beq=4
('1','1',BNE, '1','0','0',opNOP,"001","00", '1', "01",cNEQ,"00"),--bne=5
('1','1',BLEZ, '1','0','0',opNOP,"001","00", '1', "01",cLEZ,"00"),--blez=6
('1','1',BGTZ, '1','0','0',opNOP,"001","00", '1', "01",cGTZ,"00"),--bgtz=7
('1','1',ADDI, '0','1','0',opADD,"001","01", '1', "00",cNOP,"10"),--addi=8
('1','1',ADDIU,'0','1','0',opADD,"001","01", '1', "00",cNOP,"00"),--addiu=9
('1','1',SLTI, '0','1','0',opSLT,"001","01", '1', "00",cNOP,"10"),--slti=10
('1','1',SLTIU,'0','1','0',opSLTU,"001","01",'1', "00",cNOP,"00"),--sltiu11
('1','1',ANDI, '0','1','0',opAND,"001","01", '0', "00",cNOP,"00"),--andi=12
('1','1',ORI, '0','1','0',opOR, "001","01", '0', "00",cNOP,"00"),--ori=13
('1','1',XORI, '0','1','0',opXOR,"001","01", '0', "00",cNOP,"00"),--xori=14
('1','1',LUI, '0','1','0',opLUI,"001","01", '0', "00",cNOP,"00"),--lui=15
('1','1',COP0, '1','0','1',opNOP,"110","01", '0', "00",cNOP,"00"),--COP0=16
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--17
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--18
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--19
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--beql=20
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--bnel=21
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--blzel=22
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--bgtzl=23
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--24
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--25
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--26
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--27
('1','1',SPEC2,'0','0','0',opSPC,"001","00", '0', "00",cNOP,"00"),--28
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--29
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--30
('1','1',SPEC3,'0','0','0',opSPC,"001","00", '0', "00",cNOP,"00"),--special3
('0','1',LB, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lb=32
('0','1',LH, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lh=33
('0','1',LWL, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lwl=34
('0','1',LW, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lw=35
('0','1',LBU, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lbu=36
('0','1',LHU, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lhu=37
('0','1',LWR, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lwr=38
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--39
('0','0',SB, '1','1','0',opADD,"001","00", '1', "00",cNOP,"11"),--sb=40
('0','0',SH, '1','1','0',opADD,"001","00", '1', "00",cNOP,"11"),--sh=41
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--swl=42
('0','0',SW, '1','1','0',opADD,"001","00", '1', "00",cNOP,"11"),--sw=43
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--44
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--45
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--swr=46
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--cache=47
('0','1',LL, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--ll=48
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--lwc1=49
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--lwc2=50
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--pref=51
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--52
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--ldc1=53
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--ldc2=54
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--55
('0','0',SC, '0','1','0',opADD,"111","01", '1', "00",cNOP,"11"),--sc=56
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--swc1=57
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--swc2=58
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--59
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--60
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--sdc1=61
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--sdc2=62
('1','1',NOP, '1','0','0',opNOP,"000","00", '0', "00",cNOP,"00") --63
);
-- fields of the function table (opcode=0)
-- i: instr_type; -- instruction
-- wreg: std_logic; -- register write=0
-- selB: std_logic; -- B ALU input, reg=0 ext=1
-- oper: t_alu_fun; -- ALU operation
-- muxC: reg3; -- select result mem=0 ula=1 jr=2 pc+8=3
-- trap: std_logic; -- trap on compare
-- move: std_logic; -- conditional move
-- sync: std_logic; -- synch the memory hierarchy
-- PCsel: reg2; -- PCmux 0=PC+4 1=beq 2=j 3=jr
-- excp: reg2 -- stage with exception 0=no,1=rf,2=ex,3=mm
constant func_table : t_function_mem := (
-- i wreg selB oper muxC trap mov syn PCsel excp
(iSLL, '0','0',opSLL, "001",'0','0','0',"00","00"), --sll=0, EHB
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --1, FlPoint
(iSRL, '0','0',opSRL, "001",'0','0','0',"00","00"), --srl=2
(iSRA, '0','0',opSRA, "001",'0','0','0',"00","00"), --sra=3
(SLLV, '0','0',opSLLV, "001",'0','0','0',"00","00"), --sllv=4
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --5
(SRLV, '0','0',opSRLV, "001",'0','0','0',"00","00"), --srlv=6
(SRAV, '0','0',opSRAV, "001",'0','0','0',"00","00"), --srav=7
(JR, '1','0',opNOP, "001",'0','0','0',"11","00"), --jr=8
(JALR, '0','0',opNOP, "011",'0','0','0',"11","00"), --jalr=9
(MOVZ, '0','0',opMOVZ, "001",'0','1','0',"00","00"), --movz=10
(MOVN, '0','0',opMOVN, "001",'0','1','0',"00","00"), --movn=11
(SYSCALL,'1','0',trNOP,"001",'1','0','0',"00","00"), --syscall=12
(BREAK,'1','0',trNOP, "001",'1','0','0',"00","00"), --break=13
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --14
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --15
(MFHI, '0','0',opMFHI, "100",'0','0','0',"00","00"), --mfhi=16
(MTHI, '1','0',opMTHI, "001",'0','0','0',"00","00"), --mthi=17
(MFLO, '0','0',opMFLO, "101",'0','0','0',"00","00"), --mflo=18
(MTLO, '1','0',opMTLO, "001",'0','0','0',"00","00"), --mtlo=19
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --20
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --21
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --22
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --23
(MULT, '1','0',opMULT, "001",'0','0','0',"00","00"), --mult=24
(MULTU,'1','0',opMULTU,"001",'0','0','0',"00","00"), --multu=25
(DIV, '1','0',opDIV, "001",'0','0','0',"00","00"), --div=26
(DIVU, '1','0',opDIVU, "001",'0','0','0',"00","00"), --divu=27
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --28
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --29
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --30
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --31
(ADD, '0','0',opADD, "001",'0','0','0',"00","10"), --add=32
(ADDU, '0','0',opADDU, "001",'0','0','0',"00","00"), --addu=33
(SUB, '0','0',opSUB, "001",'0','0','0',"00","10"), --sub=34
(SUBU, '0','0',opSUBU, "001",'0','0','0',"00","00"), --subu=35
(iAND, '0','0',opAND, "001",'0','0','0',"00","00"), --and=36
(iOR, '0','0',opOR, "001",'0','0','0',"00","00"), --or=37
(iXOR, '0','0',opXOR, "001",'0','0','0',"00","00"), --xor=38
(iNOR, '0','0',opNOR, "001",'0','0','0',"00","00"), --nor=39
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --40
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --41
(SLT, '0','0',opSLT, "001",'0','0','0',"00","10"), --slt=42
(SLTU, '0','0',opSLTU, "001",'0','0','0',"00","00"), --sltu=43
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --44
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --45
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --46
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --47
(TGE, '1','0',trGEQ, "001",'1','0','0',"00","10"), --tge=48
(TGEU, '1','0',trGEU, "001",'1','0','0',"00","10"), --tgeu=49
(TLT, '1','0',trLTH, "001",'1','0','0',"00","10"), --tlt=50
(TLTU, '1','0',trLTU, "001",'1','0','0',"00","10"), --tltu=51
(TEQ, '1','0',trEQU, "001",'1','0','0',"00","10"), --teq=52
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --53
(TNE, '1','0',trNEQ, "001",'1','0','0',"00","10"), --tne=54
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --55
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --56
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --57
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --58
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --59
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --60
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --61
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --62
(NOP, '1','0',opNOP, "001",'0','0','0',"00","00") --63
);
-- fields of the register-immediate control table (opcode=1)
-- i: instr_type; -- instruction
-- wreg: std_logic; -- register write=0
-- selB: std_logic; -- B ALU input, reg=0 ext=1
-- br_t: t_comparison; -- comparison type: ltz,gez
-- muxC: reg3; -- select result mem=0 ula=1 jr=2 *al(pc+8)=3
-- c_sel: reg2 -- select destination reg rd=0 rt=1 31=2
-- trap: std_logic; -- trap on compare
-- PCsel: reg2; -- PCmux 0=PC+4 1=beq 2=j 3=jr
-- excp: reg2 -- stage with exception 0=no,1=rf,2=ex,3=mm
constant rimm_table : t_rimm_mem := (
-- i wreg selB br_t muxC csel trap PCsel excp
(BLTZ, '1','0',cLTZ, "001","00",'0',"01","00"), --0bltz
(BGEZ, '1','0',cGEZ, "001","00",'0',"01","00"), --1bgez
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --2
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --3
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --4
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --5
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --6
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --7
(TGEI, '1','1',tGEQ, "001","00",'1',"00","10"), --8tgei
(TGEIU,'1','1',tGEU, "001","00",'1',"00","10"), --9tgeiu
(TLTI, '1','1',tLTH, "001","00",'1',"00","10"), --10tlti
(TLTIU,'1','1',tLTU, "001","00",'1',"00","10"), --11tltiu
(TEQI, '1','1',tEQU, "001","00",'1',"00","10"), --12teqi
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --13
(TNEI, '1','1',tNEQ, "001","00",'1',"00","10"), --14tnei
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --15
(BLTZAL,'0','0',cLTZ,"011","10",'0',"01","00"), --16bltzal
(BGEZAL,'0','0',cGEZ,"011","10",'0',"01","00"), --17bgezal
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --18
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --19
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --20
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --21
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --22
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --23
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --24
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --25
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --26
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --27
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --28
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --29
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --30
(NOP, '1','0',cNOP, "001","00",'0',"00","00") --31
);
-- Table 8-30 Config Register Field Descriptions, pg 101
constant CONFIG0 : reg32 := (
'1'& -- M, Config1 implemented = 1
b"000"& -- K23, with MMU, kseg2,kseg3 coherency algorithm
b"000"& -- KU, with MMU, kuseg coherency algorithm
b"000000000"& -- Impl, implementation dependent = 0
'0'& -- BE, little endian = 0
b"00"& -- AT, MIPS32 = 0
b"001"& -- AR, Release 2 = 1
b"001"& -- MT, MMU type = 1, standard
b"000"& -- nil, always zero = 0
'1'& -- VI, Instruction Cache is virtual = 1
b"000" -- K0, Kseg0 coherency algorithm
);
-- Table 8-31 Config1 Register Field Descriptions, pg 103
constant CONFIG1 : reg32 := (
'0'& -- M, Config2 not implemented = 0
MMU_SIZE & -- MMUsz, MMU entries minus 1
IC_SETS_PER_WAY & -- ICS, IC sets per way
IC_LINE_SIZE & -- ICL, IC line size
IC_ASSOCIATIVITY & -- ICA, IC associativity
DC_SETS_PER_WAY & -- DCS, DC sets per way
DC_LINE_SIZE & -- DCL, DC line size = 3 16 bytes/line
DC_ASSOCIATIVITY & -- DCA, DC associativity = 0 direct mapped
'0'& -- C2, No coprocessor 2 implemented = 0
'0'& -- MD, No MDMX ASE implemented = 0
'0'& -- PC, No performance counters implemented = 0
'0'& -- WR, No watch registers implemented = 0
'0'& -- CA, No code compression implemented = 0
'0'& -- EP, No EJTAG implemented = 0
'0' -- FP, No FPU implemented = 0
);
-- pipeline ============================================================
begin
-- INSTR_FETCH_STATE_MACHINE: instruction-bus control
U_ifetch_stalled: FFD port map (clk => phi2, rst => rst, set => '1',
D => mem_stall, Q => if_stalled);
-- iaVal <= '1' when ((phi0 = '1' and if_stalled = '0')) else '0';
i_aVal <= '0'; -- interface signal/port, always fetches a new instruction
iaVal <= '0'; -- internal signal
rom_stall <= not(iaVal) and not(i_wait);
mem_stall <= ram_stall or rom_stall;
not_stalled <= not(mem_stall);
-- end INSTR_FETCH_STATE_MACHINE --------------------------
-- PROGRAM COUNTER AND INSTRUCTION FETCH ------------------
pipe_stall <= rom_stall or ram_stall or jr_stall or br_stall or
sw_stall or lw_stall or tr_stall or exception_stall;
PCload <= '1' when pipe_stall = '1' else '0';
IF_RF_ld <= '1' when pipe_stall = '1' else '0';
RF_EX_ld <= mem_stall; -- or exception_stall;
EX_MM_ld <= mem_stall;
MM_WB_ld <= mem_stall;
excp_IF_RF_ld <= '1' when pipe_stall = '1' else '0';
excp_RF_EX_ld <= mem_stall; -- or exception_stall;
excp_EX_MM_ld <= mem_stall;
excp_MM_WB_ld <= mem_stall;
with PCsel select
PCinp_noExcp <= PCincd when b"00", -- next instruction
br_target when b"01", -- taken branch
j_target when b"10", -- jump
eq_fwd_A when b"11", -- jump register regs_A
(others => 'X') when others;
with excp_PCsel select
PCinp <= PCinp_noExcp when PCsel_EXC_none, -- no exception
EPC when PCsel_EXC_EPC, -- ERET
x_EXCEPTION_0000 when PCsel_EXC_0000, -- TLBrefill entry point
x_EXCEPTION_0180 when PCsel_EXC_0180, -- general exception handler
x_EXCEPTION_0200 when PCsel_EXC_0200, -- separate interrupt handler
x_EXCEPTION_BFC0 when PCsel_EXC_BFC0, -- NMI or soft-reset handler
(others => 'X') when others;
-- x_EXCEPTION_0100 when PCsel_EXC_0100, -- Cache Error
PC_abort <= PC(1 downto 0) /= b"00";
IF_excp_type <= IFaddressError when PC_abort else exNOP;
PIPESTAGE_PC: register32 generic map (x_INST_BASE_ADDR)
port map (clk, rst, PCload, PCinp, PC);
PC_aligned <= PC(31 downto 2) & b"00";
-- PCincd <= std_logic_vector( 4 + signed(PC_aligned) );
U_INCPC: mf_alt_add_4 PORT MAP( datab => PC_aligned, result => PCincd );
-- uncomment this when NOT making use of the TLB
-- i_addr <= PC_aligned; -- fetch instruction from aligned address
-- uncomment this when making use of the TLB
i_addr <= phy_i_addr;
nullify_fetch <= (MM_tlb_exception and not(MM_tlb_stage_mm));
instr_fetched(25 downto 0) <= instr(25 downto 0);
instr_fetched(31 downto 26) <= instr(31 downto 26)
when not(nullify_fetch or PC_abort
or MM_addrError)
else NULL_INSTRUCTION(31 downto 26); -- x"fc";
PIPESTAGE_IF_RF: reg_IF_RF
port map (clk,rst, IF_RF_ld, PCincd, RF_PCincd,
instr_fetched, RF_instruction);
-- INSTRUCTION DECODE AND REGISTER FETCH -----------------
annul_1 <= BOOL2SL(nullify or MM_addrError);
U_NULLIFY_TWICE: FFD port map (clk, rst, '1', annul_1, annul_2);
annul_twice <= annul_1 or annul_2;
opcode <= RF_instruction(31 downto 26) when annul_twice = '0' else
NULL_INSTRUCTION (31 downto 26);
a_rs <= RF_instruction(25 downto 21);
a_rt <= RF_instruction(20 downto 16);
a_rd <= RF_instruction(15 downto 11);
shamt <= RF_instruction(10 downto 6);
func <= RF_instruction( 5 downto 0);
displ16 <= RF_instruction(15 downto 0);
syscall_n <= RF_instruction(25 downto 6);
ctrl_word <= ctrl_table( to_integer(unsigned(opcode)) );
funct_word <=
func_table( to_integer(unsigned(func)) ) when opcode = b"000000" else
func_table( 63 ); -- null instruction (sigs inactive)
rimm_word <=
rimm_table( to_integer(unsigned(a_rt)) ) when opcode = b"000001" else
rimm_table( 31 ); -- null instruction (sigs inactive)
is_branch <= '1' when ((ctrl_word.br_t /= cNOP)
or((rimm_word.br_t /= cNOP)and(rimm_word.trap='0')))
else '0';
is_trap <= '1' when ((funct_word.trap = '1')or(rimm_word.trap = '1'))
else '0';
RF_is_delayslot <= '1' when ((ctrl_word.PCsel /= "00") or
(funct_word.PCsel /= "00") or
(rimm_word.PCsel /= "00"))
else '0';
RF_STOP_SIMULATION: process (rst, phi2, opcode, func,
ctrl_word, funct_word, rimm_word,
RF_PC, exception, syscall_n)
begin
if rst = '1' and phi2 = '1' then
-- normal end of simulation, instruction "wait 0"
assert not(exception = exWAIT and syscall_n = x"80000")
report LF & "cMIPS BREAKPOINT at PC="& SLV32HEX(RF_PC) &
" opc="& SLV2STR(opcode) & " fun=" & SLV2STR(func) &
" brk=" & SLV2STR(syscall_n) &
LF & "SIMULATION ENDED (correctly?) AT exit();"
severity failure;
-- simulation aborted by instruction "wait N"
assert not(exception = exWAIT and syscall_n /= x"80000")
report LF & " PC="& SLV32HEX(PC) &
" EPC="& SLV32HEX(EPC) &
" bad="& SLV32HEX(BadVAddr) &
" opc="& SLV2STR(opcode) & " wait=" & SLV2STR(syscall_n(7 downto 0)) &
" instr=" & SLV32HEX(RF_instruction) &
LF & "SIMULATION ABORTED AT EXCEPTION HANDLER;"
severity failure;
-- abort on invalid/unimplemented opcodes
if opcode = b"000000" and funct_word.i = NIL then
assert (1=0)
report LF & "INVALID OPCODE at PC="& SLV32HEX(RF_PC) &
" opc="& SLV2STR(opcode) & " instr=" & SLV32HEX(RF_instruction) &
LF & "SIMULATION ABORTED"
severity failure;
elsif opcode = b"000001" and rimm_word.i = NIL then
assert (1=0)
report LF & "INVALID OPCODE at PC="& SLV32HEX(RF_PC) &
" opc="& SLV2STR(opcode) & " instr=" & SLV32HEX(RF_instruction) &
LF & "SIMULATION ABORTED"
severity failure;
elsif ctrl_word.i = NIL then
assert (1=0)
report LF & "INVALID OPCODE at PC="& SLV32HEX(RF_PC) &
" opc="& SLV2STR(opcode) & " instr=" & SLV32HEX(RF_instruction) &
LF & "SIMULATION ABORTED"
severity failure;
end if;
end if;
end process RF_STOP_SIMULATION;
move <= funct_word.move when opcode = b"000000" else '0';
U_regs: reg_bank -- phi1=read_early, clk=write_late
port map (clk, phi1, WB_wreg, a_rs,a_rt, WB_a_c,WB_C, regs_A,regs_B);
-- U_PC_plus_8: adder32 port map (x"00000004", RF_PCincd, pc_p8); -- (PC+4)+4
-- pc_p8 <= std_logic_vector( 4 + signed(RF_PCincd) ); -- (PC+4)+4
U_PC_plus_8: mf_alt_add_4 PORT MAP( datab => RF_PCincd, result => pc_p8 );
displ32 <= x"FFFF" & displ16 when
(displ16(15) = '1' and ctrl_word.extS = '1') else
x"0000" & displ16;
j_target <= RF_PCincd(31 downto 28) & RF_instruction(25 downto 0) & b"00";
RF_JR_STALL: process (funct_word,a_rs,EX_a_c,MM_a_c,EX_wreg,MM_wreg,
MM_is_load)
variable i_dbg_jr_stall : integer := 0; -- debug only
begin
if ( (funct_word.PCsel = b"11")and -- load-delay slot
(EX_a_c /= a_rs)and(EX_wreg = '0')and
(MM_a_c = a_rs)and(MM_wreg = '0')and(MM_a_c /= b"00000") ) then
jr_stall <= '1';
i_dbg_jr_stall := 1;
elsif ( (funct_word.PCsel = b"11")and -- ALU hazard
(EX_a_c = a_rs)and(EX_wreg = '0')and(EX_a_c /= b"00000") ) then
jr_stall <= '1';
i_dbg_jr_stall := 2;
elsif ( (funct_word.PCsel = b"11")and -- 2nd load-delay slot
MM_is_load and
(MM_a_c = a_rs)and(MM_wreg = '0')and(MM_a_c /= b"00000") ) then
jr_stall <= '1';
i_dbg_jr_stall := 3;
else
jr_stall <= '0';
i_dbg_jr_stall := 0;
end if;
dbg_jr_stall <= i_dbg_jr_stall;
end process RF_JR_STALL;
RF_LD_DELAY_SLOT: process (a_rs,a_rt,EX_a_c,EX_wreg,EX_is_load)
begin
if ( EX_is_load and
(EX_wreg = '0') and (EX_a_c /= b"00000") and
( (EX_a_c = a_rs)or(EX_a_c = a_rt) ) ) then
lw_stall <= '1';
else
lw_stall <= '0';
end if;
end process RF_LD_DELAY_SLOT;
RF_SW_STALL: process (ctrl_word,a_rs,EX_a_c,EX_wreg,EX_is_load)
variable is_store : boolean := false;
begin
case ctrl_word.i is
when LB | LH | LWL | LW | LBU | LHU | LWR =>
is_load <= TRUE;
is_store := FALSE;
when SB | SH | SW =>
is_store := TRUE;
is_load <= FALSE;
when others =>
is_load <= FALSE;
is_store := FALSE;
end case;
if ( is_store and EX_is_load and
(EX_a_c = a_rs)and(EX_wreg = '0')and(EX_a_c /= b"00000") ) then
sw_stall <= '1';
else
sw_stall <= '0';
end if;
end process RF_SW_STALL;
RF_FORWARDING_BRANCH: process (a_rs,a_rt,EX_wreg,EX_a_c,MM_wreg,MM_a_c,
MM_aVal,MM_result,MM_cop0_val,MM_is_MFC0,
regs_A,regs_B,is_branch,
is_SC, LL_SC_abort)
variable rs_stall, rt_stall : boolean;
begin
if ( (is_branch = '1') and -- forward_A
(EX_wreg = '0') and (EX_a_c = a_rs) and (EX_a_c /= b"00000") ) then
if is_SC then
eq_fwd_A <= x"0000000" & b"000" & not(LL_SC_abort);
rs_stall := FALSE;
else
eq_fwd_A <= regs_A;
rs_stall := TRUE;
end if;
elsif ( (MM_wreg = '0') and (MM_a_c = a_rs) and (MM_a_c /= b"00000") ) then
if ( (MM_aVal = '0') and (is_branch = '1') ) then -- LW load-delay slot
eq_fwd_A <= regs_A;
rs_stall := TRUE;
elsif MM_is_MFC0 then -- non-LW
eq_fwd_A <= MM_cop0_val;
rs_stall := FALSE;
elsif MM_is_SC then
eq_fwd_A <= x"00000000";
rs_stall := FALSE;
else
eq_fwd_A <= MM_result;
rs_stall := FALSE;
end if;
else
eq_fwd_A <= regs_A;
rs_stall := FALSE;
end if;
if ( (is_branch = '1') and -- forward_B
(EX_wreg = '0') and (EX_a_c = a_rt) and (EX_a_c /= b"00000") ) then
if is_SC then
eq_fwd_B <= x"0000000" & b"000" & not(LL_SC_abort);
rt_stall := FALSE;
else
eq_fwd_B <= regs_B;
rt_stall := TRUE;
end if;
elsif ( (MM_wreg = '0') and (MM_a_c = a_rt) and (MM_a_c /= b"00000") ) then
if ( (MM_aVal = '0') and (is_branch = '1') ) then -- LW load-delay slot
eq_fwd_B <= regs_B;
rt_stall := TRUE;
elsif MM_is_MFC0 then -- non-LW
eq_fwd_B <= MM_cop0_val;
rt_stall := FALSE;
elsif MM_is_SC then
eq_fwd_B <= x"00000000";
rt_stall := FALSE;
else
eq_fwd_B <= MM_result;
rt_stall := FALSE;
end if;
else
eq_fwd_B <= regs_B;
rt_stall := FALSE;
end if;
br_stall <= BOOL2SL(rs_stall or rt_stall);
end process RF_FORWARDING_BRANCH;
br_equal <= (eq_fwd_A = eq_fwd_B);
br_negative <= (eq_fwd_A(31) = '1');
br_eq_zero <= (eq_fwd_A = x"00000000");
RF_BR_tgt_select: process (br_equal,br_negative,br_eq_zero,
ctrl_word,rimm_word)
variable branch_type, regimm_br_type : t_comparison;
variable i_br_opr : reg2;
begin
branch_type := ctrl_word.br_t;
regimm_br_type := rimm_word.br_t;
i_br_opr := b"01"; -- assume not taken, PC+4 + 4 (delay slot)
case branch_type is
when cNOP => -- no branch, PC+4
i_br_opr := b"00";
when cEQU => -- beq
if br_equal then i_br_opr := b"10"; -- br_target;
end if;
when cNEQ => -- bne
if not(br_equal) then i_br_opr := b"10"; -- br_target;
end if;
when cLEZ =>
if (br_negative or br_eq_zero) then i_br_opr := b"10"; -- br_target;
end if;
when cGTZ =>
if not(br_negative or br_eq_zero) then i_br_opr := b"10"; -- br_target;
end if;
when cOTH => -- bltz,blez,bgtz,bgez
case regimm_br_type is
when cLTZ =>
if br_negative then i_br_opr := b"10"; -- br_target;
end if;
when cGEZ =>
if not(br_negative) then i_br_opr := b"10"; -- br_target;
end if;
when others =>
i_br_opr := b"00"; -- x"00000000";
end case;
when others =>
i_br_opr := b"00"; -- x"00000000";
end case;
br_opr <= i_br_opr;
-- assert false report
-- "branch_add32 A="& SLV32HEX(RF_PCincd) &" B="& SLV32HEX(br_operand) &
-- " A+B="& SLV32HEX(br_target); -- DEBUG
end process RF_BR_tgt_select;
-- U_BR_ADDER: adder32 port map (RF_PCincd, br_operand, br_target);
-- br_target <= std_logic_vector( signed(RF_PCincd) + signed(br_operand) );
-- branch target computation is in the citical path; add early, select late
br_addend <= displ32(29 downto 0) & b"00";
U_BR_tgt_pl_4: mf_alt_add_4 port map (RF_PCincd, br_tgt_pl4);
U_BR_tgt_pl_displ: mf_alt_adder port map (RF_PCincd, br_addend, br_tgt_displ);
with br_opr select
br_target <= br_tgt_pl4 when b"01",
br_tgt_displ when b"10",
RF_PCincd when others;
RF_DECODE_FUNCT: process (opcode,IF_RF_ld,ctrl_word,funct_word,rimm_word,
func,shamt, a_rs,a_rd, STATUS,
RF_excp_type,RF_instruction)
variable i_wreg : std_logic;
variable i_csel : reg2;
variable i_oper : t_alu_fun := opNOP;
variable i_exception : exception_type;
variable i_trap : instr_type;
variable i_cop0_reg : reg5;
variable i_cop0_sel : reg3;
begin
i_wreg := '1';
i_exception := exNOP;
i_oper := opNOP;
i_csel := "00";
i_trap := NOP;
i_cop0_reg := b"00000";
i_cop0_sel := b"000";
case opcode is
when b"000000" => -- ALU
i_wreg := funct_word.wreg;
selB <= funct_word.selB;
i_oper := funct_word.oper;
muxC <= funct_word.muxC;
i_csel := ctrl_word.c_sel;
PCsel <= funct_word.PCsel;
i_trap := funct_word.i;
if (funct_word.trap = '1') then -- traps
case funct_word.i is
when SYSCALL => i_exception := exSYSCALL;
when BREAK => i_exception := exBREAK;
when iSLL =>
if RF_instruction = x"000000c0" then
i_exception := exEHB;
end if;
when others => i_exception := exNOP;
end case;
end if;
when b"000001" => -- register immediate
i_wreg := rimm_word.wreg;
selB <= rimm_word.selB;
muxC <= rimm_word.muxC;
i_csel := rimm_word.c_sel;
PCsel <= rimm_word.PCsel;
i_trap := rimm_word.i;
i_oper := opNOP; -- no ALU operation
if (rimm_word.trap = '1') then -- traps
i_exception := exNOP;
end if;
when b"010000" => -- COP-0
i_cop0_reg := a_rd;
i_cop0_sel := func(2 downto 0);
case a_rs is
when b"00100" => -- MTC0
i_exception := exMTC0;
when b"00000" => -- MFC0
i_exception := exMFC0;
i_wreg := '0';
when b"10000" => -- ERET
case func is
when b"000001" => i_exception := exTLBR;
when b"000010" => i_exception := exTLBWI;
when b"000110" => i_exception := exTLBWR;
when b"001000" => i_exception := exTLBP;
when b"011000" => i_exception := exERET;
when b"011111" => i_exception := exDERET;
when b"100000" => i_exception := exWAIT;
when others => i_exception := exRESV_INSTR;
end case;
when b"01011" => -- EI and DI
case func is
when b"100000" => -- EI;
i_exception := exEI;
i_wreg := '0';
when b"000000" => -- DI;
i_exception := exDI;
i_wreg := '0';
when others => i_exception := exRESV_INSTR;
end case;
when others => i_exception := exRESV_INSTR;
end case;
selB <= '0';
i_oper := opNOP;
muxC <= ctrl_word.muxC;
i_csel := ctrl_word.c_sel;
PCsel <= ctrl_word.PCsel;
when b"011100" => -- special2
i_wreg := ctrl_word.wreg;
selB <= ctrl_word.selB;
muxC <= ctrl_word.muxC;
i_csel := ctrl_word.c_sel;
PCsel <= ctrl_word.PCsel;
case func is
when b"000010" => -- MUL R[rd] <= R[rs]*R[rt]
i_oper := opMUL;
when others =>
i_oper := opNOP;
i_exception := exRESV_INSTR;
end case;
when b"011111" => -- special3
case func is
when b"100000" => -- BSHFL
i_csel := ctrl_word.c_sel;
case shamt is
when b"00010" => -- word swap bytes within halfwords
i_oper := opSWAP;
when b"10000" => -- sign-extend byte
i_oper := opSEB;
when b"11000" => -- sign-extend halfword
i_oper := opSEH;
when others =>
i_oper := opNOP;
end case;
when b"000000" => -- extract bit field
i_csel := b"01"; -- dest = rt
i_oper := opEXT;
when b"000100" => -- insert bit field
i_csel := b"01"; -- dest = rt
i_oper := opINS;
when others => i_exception := exRESV_INSTR;
end case;
i_wreg := ctrl_word.wreg;
selB <= ctrl_word.selB;
muxC <= ctrl_word.muxC;
PCsel <= ctrl_word.PCsel;
when others =>
case opcode is
when b"110000" => i_exception := exLL; -- not REALLY exceptions
when b"111000" => i_exception := exSC;
when others => null; -- i_exception := exRESV_INSTR;
end case;
i_wreg := ctrl_word.wreg;
selB <= ctrl_word.selB;
i_oper := ctrl_word.oper;
muxC <= ctrl_word.muxC;
i_csel := ctrl_word.c_sel;
PCsel <= ctrl_word.PCsel;
end case;
oper <= i_oper;
c_sel <= i_csel;
trap_instr <= i_trap;
cop0_reg <= i_cop0_reg;
cop0_sel <= i_cop0_sel;
if IF_RF_ld = '1' then -- bubble (OR flush_RF_EX)
wreg <= '1';
aVal <= '1';
wrmem <= '1';
exception <= exNOP;
else
wreg <= i_wreg;
aVal <= ctrl_word.aVal;
wrmem <= ctrl_word.wmem;
exception <= i_exception;
end if;
end process RF_DECODE_FUNCT;
-- exception_dec <= exception_type'pos(exception); -- debugging only
can_trap <= ctrl_word.excp or funct_word.excp or rimm_word.excp;
RF_DECODE_MEM_REF: process (ctrl_word)
variable i_type : reg4;
-- bit3: LWL,LWR=1, bit2: signed=1, bits10:xx,byte,half,word
begin
case ctrl_word.i is
when LB => i_type := b"0101"; -- signed, byte (sign extend)
when LH => i_type := b"0110"; -- signed, half-word
when LW | LL => i_type := b"0011"; -- word
when LBU => i_type := b"0001"; -- unsigned, byte (zero extend)
when LHU => i_type := b"0010"; -- unsigned, half-word
when SB => i_type := b"0001";
when SH => i_type := b"0010";
when SW | SC => i_type := b"0011";
when LWL => i_type := b"1011"; -- unaligned LOADS
when LWR => i_type := b"1111"; -- unaligned LOADS
when others => i_type := b"0000";
end case;
mem_t <= i_type;
end process RF_DECODE_MEM_REF;
with c_sel select -- select destination register
a_c <= a_rd when b"00", -- type-R
a_rt when b"01", -- type-I
b"11111" when b"10", -- jal
b"00000" when others;
PIPESTAGE_RF_EX: reg_RF_EX
port map (clk,rst, RF_EX_ld, selB,EX_selB, oper,EX_oper,
a_rs,EX_a_rs, a_rt,EX_a_rt, a_c,EX_a_c,
wreg,EX_wreg_pre, muxC,EX_muxC, move,EX_move,
a_rd,EX_postn, shamt,EX_shamt, aVal,EX_aVal,
wrmem,EX_wrmem, mem_t,EX_mem_t, is_load,EX_is_load,
regs_A,EX_A, regs_B,EX_B, displ32,EX_displ32,
pc_p8,EX_pc_p8);
-- EXECUTION ---------------------------------------------
EX_FORWARDING_ALU: process (EX_a_rs,EX_a_rt,EX_a_c, EX_A,EX_B,
MM_ll_sc_abort, MM_is_SC,
MM_a_c,MM_wreg,WB_a_c,WB_wreg,
MM_is_MFC0,MM_cop0_val, MM_result,WB_C)
variable i_A,i_B : reg32;
begin
FORWARD_A:
if ((MM_wreg = '0')and(MM_a_c /= b"00000")and(MM_a_c = EX_a_rs)) then
if MM_is_MFC0 then
i_A := MM_cop0_val;
elsif MM_is_SC then
i_A := x"0000000" & b"000" & not( BOOL2SL(MM_ll_sc_abort) );
else
i_A := MM_result;
end if;
elsif ((WB_wreg = '0')and(WB_a_c /= b"00000")and(WB_a_c = EX_a_rs)) then
i_A := WB_C;
else
i_A := EX_A;
end if;
alu_inp_A <= i_A;
assert TRUE report -- DEBUG
"FWD_A: alu_A="&SLV32HEX(alu_inp_A)&" alu_B="&SLV32HEX(alu_fwd_B);
FORWARD_B:
if ((MM_wreg = '0')and(MM_a_c /= b"00000")and(MM_a_c = EX_a_rt)) then
if MM_is_MFC0 then
i_B := MM_cop0_val;
elsif MM_is_SC then
i_B := x"0000000" & b"000" & not( BOOL2SL(MM_ll_sc_abort) );
else
i_B := MM_result;
end if;
elsif ((WB_wreg = '0')and(WB_a_c /= b"00000")and(WB_a_c = EX_a_rt)) then
i_B := WB_C;
else
i_B := EX_B;
end if;
alu_fwd_B <= i_B;
assert TRUE report -- DEBUG
"FWD_B: alu_A="&SLV32HEX(alu_inp_A)&" alu_B="&SLV32HEX(alu_fwd_B);
end process EX_FORWARDING_ALU;
alu_inp_B <= alu_fwd_B when (EX_selB = '0') else EX_displ32;
U_ALU: alu port map(clk,rst,
alu_inp_A, alu_inp_B, result, LO, HI, annul_twice,
alu_move_ok, EX_oper,EX_postn,EX_shamt, ovfl);
-- this adder performs address calculation so the TLB can be checked during
-- EX and thus signal an exception as early as possible
U_VIR_ADDR_ADD: mf_alt_adder port map (alu_inp_A, EX_displ32, v_addr);
U_EX_ADDR_ERR_EXCP: process(EX_mem_t,EX_aVal,EX_wrmem, v_addr)
variable i_stage_mm, i_addrError : boolean;
variable i_excp_type : exception_type;
begin
case EX_mem_t(1 downto 0) is -- xx,by,hf,wd
when b"11" =>
if ( EX_mem_t(3) = '0' and -- normal LOAD, not LWL,LWR
EX_aVal = '0' and v_addr(1 downto 0) /= b"00" ) then
if EX_wrmem = '1' then
i_excp_type := MMaddressErrorLD;
else
i_excp_type := MMaddressErrorST;
end if;
i_addrError := TRUE;
i_stage_mm := TRUE;
else
i_excp_type := exNOP;
i_addrError := FALSE;
i_stage_mm := FALSE;
end if;
when b"10" => -- LH*, SH
if EX_aVal = '0' and v_addr(0) /= '0' then
if EX_wrmem = '1' then
i_excp_type := MMaddressErrorLD;
else
i_excp_type := MMaddressErrorST;
end if;
i_addrError := TRUE;
i_stage_mm := TRUE;
else
i_excp_type := exNOP;
i_addrError := FALSE;
i_stage_mm := FALSE;
end if;
when others => -- LB*, SB
i_excp_type := exNOP;
i_addrError := FALSE;
i_stage_mm := FALSE;
end case;
mem_excp_type <= i_excp_type;
addrErr_stage_mm <= i_stage_mm;
addrError <= i_addrError;
-- assert mem_excp_type = exNOP -- DEBUG
-- report LF & "SIMULATION ERROR -- data addressing error: " &
-- integer'image(exception_type'pos(mem_excp_type)) &
-- " at address: " & SLV32HEX(v_addr)
-- severity error;
end process U_EX_ADDR_ERR_EXCP; ----------------------------------
-- uncomment this when making use of the TLB CHANGE
EX_addr <= phy_d_addr; -- with TLB
-- uncomment this when NOT making use of the TLB
-- EX_addr <= v_addr; -- without TLB
-- assert ( (phy_d_addr = v_addr) and (EX_aVal = '0') ) -- DEBUG
-- report LF&"mapping mismatch V:P "&SLV32HEX(v_addr)&":"&SLV32HEX(phy_d_addr);
EX_wreg <= EX_wreg_pre -- movz,movn, move/DO_NOT move
-- abort wr if previous exception in EX
or ( BOOL2SL(nullify) and not(MM_is_delayslot) )
-- abort wr if TLB exception in EX (nullify=1 on next cycle)
or ( BOOL2SL( tlb_exception and tlb_stage_mm ) );
EX_wrmem_cond <= EX_wrmem
or BOOL2SL(abort_ref) -- abort write if exception in MEM
or LL_SC_abort -- SC is to be killed
-- abort memWrite if exception in EX, but not in IF
or ( BOOL2SL(nullify) and
(MM_is_delayslot and not BOOL2SL(nullify_fetch)) )
or ( BOOL2SL(nullify) and not BOOL2SL(nullify_fetch) );
-- check_this
EX_aVal_cond <= EX_aVal
or BOOL2SL(abort_ref) -- abort ref if exception in MEM
or LL_SC_abort -- SC is to be killed
-- abort memWrite if exception in EX, but not in IF
or ( BOOL2SL(nullify) and
(MM_is_delayslot and not BOOL2SL(nullify_fetch)) )
or ( BOOL2SL(nullify) and not BOOL2SL(nullify_fetch) );
-- check_this
abort_ref <= (addrError or (tlb_exception and tlb_stage_mm));
busFree <= EX_aVal_cond;
-- ----------------------------------------------------------------------
PIPESTAGE_EX_MM: reg_EX_MM
port map (clk,rst, EX_MM_ld,
EX_a_rt,MM_a_rt, EX_a_c,MM_a_c, EX_wreg,MM_wreg,
EX_muxC,MM_muxC, EX_aVal_cond,MM_aVal, EX_wrmem_cond,MM_wrmem,
EX_mem_t,MM_mem_t, EX_is_load,MM_is_load,
EX_A,MM_A, alu_fwd_B,MM_B,
result,MM_result, EX_addr,MM_addr,
HI,MM_HI, LO,MM_LO,
alu_move_ok,MM_alu_move_ok, EX_move,MM_move,
EX_pc_p8,MM_pc_p8);
-- MEMORY ---------------------------------------------------------------
-- DATA_BUS_STATE_MACHINE: data-bus control
U_dmem_stalled: FFD port map (clk => phi2, rst => rst, set => '1',
D => mem_stall, Q => mm_stalled);
d_aVal <= MM_aVal; -- interface signal/port
daVal <= MM_aVal; -- internal signal
ram_stall <= not(daVal) and not(d_wait);
-- end DATA_BUS_STATE_MACHINE -------------------------------------
wr <= MM_wrmem; -- abort write if SC fails
rd_data_raw <= data_inp when (MM_wrmem = '1' and MM_aVal = '0') else
(others => 'X');
MM_MEM_CTRL_INTERFACE: process(MM_mem_t, MM_addr)
variable i_d_addr : reg2;
variable i_byte_sel : reg4;
begin
case MM_mem_t(1 downto 0) is -- xx,by,hf,wd
when b"11" =>
i_byte_sel := b"1111"; -- LW, SW, LWL, LWR
i_d_addr := b"00"; -- align reference
when b"10" =>
i_d_addr := MM_addr(1) & '0'; -- align reference
if MM_addr(1) = '0' then -- LH*, SH
i_byte_sel := b"0011";
else
i_byte_sel := b"1100";
end if;
when b"01" => -- LB*, SB
i_d_addr := MM_addr(1 downto 0);
case MM_addr(1 downto 0) is
when b"00" => i_byte_sel := b"0001";
when b"01" => i_byte_sel := b"0010";
when b"10" => i_byte_sel := b"0100";
when others => i_byte_sel := b"1000";
end case;
when others =>
i_d_addr := (others => 'X'); -- MM_addr;
i_byte_sel := b"0000";
end case;
d_addr <= MM_addr(31 downto 2) & i_d_addr;
b_sel <= i_byte_sel;
end process MM_MEM_CTRL_INTERFACE; ---------------------------------
MM_MEM_DATA_INTERFACE: process(MM_mem_t, MM_addr, rd_data_raw)
variable bytes_read : reg32;
variable i_byte : reg8;
variable i_half : reg16;
constant c_24_ones : reg24 := b"111111111111111111111111";
constant c_24_zeros : reg24 := b"000000000000000000000000";
constant c_16_ones : reg16 := b"1111111111111111";
constant c_16_zeros : reg16 := b"0000000000000000";
begin
case MM_mem_t(1 downto 0) is -- 10:xx,by,hf,wd
when b"11" =>
bytes_read := rd_data_raw;
when b"10" =>
if MM_addr(1) = '0' then -- LH*, SH
i_half := rd_data_raw(15 downto 0);
else
i_half := rd_data_raw(31 downto 16);
end if;
if MM_mem_t(2) = '1' and i_half(15) = '1' then -- mem_t(2):signed=1
bytes_read := c_16_ones & i_half;
else
bytes_read := c_16_zeros & i_half;
end if;
when b"01" => -- LB*, SB
case MM_addr(1 downto 0) is
when b"00" => i_byte := rd_data_raw(7 downto 0);
when b"01" => i_byte := rd_data_raw(15 downto 8);
when b"10" => i_byte := rd_data_raw(23 downto 16);
when others => i_byte := rd_data_raw(31 downto 24);
end case;
if MM_mem_t(2) = '1' and i_byte(7) = '1' then -- mem_t(2):signed=1
bytes_read := c_24_ones & i_byte;
else
bytes_read := c_24_zeros & i_byte;
end if;
when others =>
bytes_read := (others => 'X');
end case;
rd_data <= bytes_read;
end process MM_MEM_DATA_INTERFACE; ---------------------------------
-- forwarding for LW -> SW
MM_FORWARDING_MEM: process (MM_aVal,MM_wrmem,MM_a_rt,WB_a_c,WB_wreg,WB_C,MM_B)
variable f_m: reg2;
variable i_data : reg32;
begin
f_m := "XX";
if ( (MM_wrmem = '0') and (MM_aVal = '0') ) then
if ( (MM_a_rt = WB_a_c) and (WB_wreg = '0') and (WB_a_c /= b"00000")) then
f_m := "01"; -- forward from WB
i_data := WB_C;
else
f_m := "00"; -- not forwarding
i_data := MM_B;
end if;
else
f_m := "11"; -- not a write, (others=>'Z')
i_data := (others => 'X');
end if;
fwd_mem <= f_m; -- for debugging
data_out <= i_data;
end process MM_FORWARDING_MEM; -------------------------------
-- forwarding for LWL, LWR
MM_FWD_LWLR: process (MM_aVal,MM_wreg,MM_a_rt,WB_a_c,WB_wreg,WB_C,MM_B)
variable f_m: boolean;
variable i_data : reg32;
begin
if ( (MM_wreg = '0') and (MM_aVal = '0') and
(MM_a_rt = WB_a_c) and (WB_wreg = '0') and
(WB_a_c /= b"00000") ) then
f_m := TRUE; -- forward from WB
i_data := WB_C;
else
f_m := FALSE; -- not forwarding
i_data := MM_B;
end if;
fwd_lwlr <= f_m; -- for debugging
MM_B_data <= i_data;
end process MM_FWD_LWLR;
-- if interrupt is in J/BR delaySlot, and JR was stalled, kill instr in MM
U_NULLIFY_THRICE:
FFD port map (clk, rst, '1', nullify_MM_pre, nullify_MM_int);
MM_wreg_cond <= '1' when ( (ram_stall = '1')
or MM_addrError -- abort regWrite if excptn in MEM
or (MM_move = '1' and MM_alu_move_ok = '0')
or (nullify_MM_int = '1')
)
else MM_wreg;
-- ----------------------------------------------------------------------
PIPESTAGE_MM_WB: reg_MM_WB
port map (clk,rst, MM_WB_ld,
MM_a_c,WB_a_c, MM_wreg_cond,WB_wreg, MM_muxC,WB_muxC,
MM_A,WB_A, MM_result,WB_result, MM_HI,WB_HI,MM_LO,WB_LO,
rd_data,WB_rd_data, MM_B_data,WB_B_data,
MM_addr(1 downto 0),WB_addr2, MM_mem_t(3 downto 2),WB_mem_t,
MM_pc_p8,WB_pc_p8);
-- WRITE BACK -----------------------------------------------------------
-- merge unaligned loads LWL,LWR
mergeLOAD: process (WB_rd_data, WB_B_data, WB_addr2, WB_mem_t)
variable mem, reg, res : reg32;
begin
mem := WB_rd_data;
reg := WB_B_data;
case WB_mem_t is
when "10" => -- LWL
case WB_addr2 is
when "00" =>
res := mem( 7 downto 0) & reg(23 downto 0);
when "01" =>
res := mem(15 downto 0) & reg(15 downto 0);
when "10" =>
res := mem(23 downto 0) & reg( 7 downto 0);
when others =>
res := mem;
end case;
when "11" => -- LWR
case WB_addr2 is
when "01" =>
res := reg(31 downto 24) & mem(31 downto 8);
when "10" =>
res := reg(31 downto 16) & mem(31 downto 16);
when "11" =>
res := reg(31 downto 8) & mem(31 downto 24);
when others =>
res := mem;
end case;
when others => -- normal LOAD
res := mem;
end case;
WB_mem_data <= res;
end process mergeLOAD;
with WB_muxC select WB_C <=
WB_mem_data when b"000", -- from memory
WB_result when b"001", -- from ALU
WB_A when b"010", -- A, for jr
WB_pc_p8 when b"011", -- PC+8 for jal
WB_HI when b"100", -- MFHI
WB_LO when b"101", -- MFLO
WB_cop0_val when b"110", -- from COP0 registers
(x"0000000" & b"000" & WB_LLbit) when b"111", -- from LLbit
(others => 'X') when others; -- invalid selection
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- end of data pipeline
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- control pipeline
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- IF instruction fetch ---------------------------------------------
PIPESTAGE_EXCP_IF_RF: reg_excp_IF_RF
port map (clk, rst, excp_IF_RF_ld,
IF_excp_type,RF_excp_type, PC_abort,RF_PC_abort, PC,RF_PC);
-- RF decode & register fetch ---------------------------------------------
RF_FORWARDING_TRAPS: process (a_rs,a_rt,rimm_word,displ32,
EX_wreg,EX_a_c,MM_wreg,MM_a_c,
MM_aVal,MM_result,regs_A,regs_B,is_trap)
begin
tr_stall <= '0';
if ( (is_trap = '1') and -- forward_A:
(EX_wreg = '0') and (EX_a_c = a_rs) and (EX_a_c /= b"00000") ) then
tr_stall <= '1';
tr_fwd_A <= regs_A;
elsif ((MM_wreg = '0') and (MM_a_c = a_rs) and (MM_a_c /= b"00000")) then
if (MM_aVal = '0') then -- LW load-delay slot
if (is_trap = '1') then
tr_stall <= '1';
end if;
tr_fwd_A <= regs_A;
else -- non-LW
tr_fwd_A <= MM_result;
end if;
else
tr_fwd_A <= regs_A;
end if;
if ( (is_trap = '1') and (rimm_word.selB = '1') ) then -- from immediate
tr_fwd_B <= displ32;
elsif ( (is_trap = '1') and -- forward_B:
(EX_wreg = '0') and (EX_a_c = a_rt) and (EX_a_c /= b"00000") ) then
tr_stall <= '1';
tr_fwd_B <= regs_B;
elsif ((MM_wreg = '0') and (MM_a_c = a_rt) and (MM_a_c /= b"00000")) then
if (MM_aVal = '0') then -- LW load-delay slot
if (is_trap = '1') then
tr_stall <= '1';
end if;
tr_fwd_B <= regs_B;
else -- non-LW
tr_fwd_B <= MM_result;
end if;
else
tr_fwd_B <= regs_B;
end if;
end process RF_FORWARDING_TRAPS;
tr_signed <= '0' when ((funct_word.trap = '1' and
((funct_word.oper = trGEU)or(funct_word.oper = trLTU)))
or
(rimm_word.trap = '1' and
((rimm_word.br_t = tGEU)or(rimm_word.br_t = tLTU))))
else '1';
tr_is_equal <= '1' when (tr_fwd_A = tr_fwd_B) else '0';
U_COMP_TRAP: subtr32
port map (tr_fwd_A, tr_fwd_B, tr_result, tr_signed, open, tr_less_than);
trap_dec <= instr_type'pos(trap_instr); -- debugging only
RF_EVALUATE_TRAPS: process (trap_instr, tr_is_equal, tr_less_than)
variable i_take_trap : boolean;
begin
case trap_instr is
when TEQ | TEQI =>
i_take_trap := tr_is_equal = '1';
when TNE | TNEI =>
i_take_trap := tr_is_equal = '0';
when TLT | TLTI | TLTU | TLTIU =>
i_take_trap := tr_less_than = '1';
when TGE | TGEI | TGEU | TGEIU =>
i_take_trap := tr_less_than = '0';
when others =>
i_take_trap := FALSE;
end case;
trap_taken <= i_take_trap;
end process RF_EVALUATE_TRAPS;
-- ----------------------------------------------------------------------
PIPESTAGE_EXCP_RF_EX: reg_excp_RF_EX
port map (clk, rst, excp_RF_EX_ld,
cop0_reg,EX_cop0_reg, cop0_sel,EX_cop0_sel,
can_trap,EX_can_trap,
exception,EX_exception,
RF_is_delayslot,EX_is_delayslot,
RF_PC_abort,EX_PC_abort, RF_PC,EX_PC,
trap_taken,EX_trapped);
is_nmi <= ( (nmi = '1') and (STATUS(STATUS_ERL) = '0') );
int_req(5) <= (irq(5) or count_eq_compare);
int_req(4) <= irq(4);
int_req(3) <= irq(3);
int_req(2) <= irq(2);
int_req(1) <= irq(1);
int_req(0) <= irq(0);
interrupt <= int_req(5) or int_req(4) or int_req(3) or int_req(2) or
int_req(1) or int_req(0) or
CAUSE(CAUSE_IP1) or CAUSE(CAUSE_IP0);
is_interr <= ( (interrupt = '1') and
(STATUS(STATUS_EXL) = '0') and
(STATUS(STATUS_ERL) = '0') and
(STATUS(STATUS_IE) = '1') and
(dly_interr = '0') and
(interrupt_taken = '0') ); -- single cycle exception req
-- While returning from an exception (especially another interrupt),
-- delay the IRQ to make sure the interrupted instruction completes;
-- This is needed to ensure forward-progress: at least one instruction
-- must complete before another interrupt may be taken.
-- Also, delay the interrupt requests to avoid hazards while
-- the interrupt-enable bit is changed in the STATUS register.
-- dly_i0 <= '1' when ( (EX_exception = exERET) or -- forward progress
-- (EX_exception = exEI) or -- interrupt hazard
-- (EX_exception = exDI) or -- interrupt hazard
-- (EX_exception = exEHB) or -- interrupt hazard
-- (EX_exception = exMTC0 -- interrupt hazard
-- and EX_cop0_reg = cop0reg_STATUS) or
-- (EX_exception = exMFC0 -- interrupt hazard
-- and EX_cop0_reg = cop0reg_STATUS) ) else
-- '0';
dly_i0 <= '1' when ( EX_exception /= exNOP ) else '0';
U_DLY_INT1: FFD port map (clk, rst, '1',dly_i0, dly_i1);
U_DLY_INT2: FFD port map (clk, rst, '1',dly_i1, dly_i2);
dly_interr <= dly_i0 or dly_i1 or dly_i2;
-- check for overflow in EX, send it to MM for later processing
is_ovfl <= (EX_can_trap = b"10" and ovfl = '1');
is_SC <= (EX_exception = exSC); -- is StoreConditional? (alu_fwd)
is_mfc0 <= (EX_exception = exMFC0); -- is MFC0? (alu_fwd)
-- priority is always given to events later in the pipeline
busError_type <= exDBE when d_busErr = '0' else
exIBE when i_busErr = '0' else
exNOP;
is_busError <= (i_busErr = '0') or (d_busErr = '0');
EX_is_exception <= busError_type when is_busError else
TLB_excp_type when tlb_exception else
mem_excp_type when addrError else
IFaddressError when EX_PC_abort else
exTrap when EX_trapped else
exOvfl when is_ovfl else
exNMI when is_nmi else
exInterr when is_interr else
EX_exception;
exception_dec <= exception_type'pos(EX_is_exception); -- debugging only
-- ----------------------------------------------------------------------
PIPESTAGE_EXCP_EX_MM: reg_excp_EX_MM
port map (clk, rst, excp_EX_MM_ld,
EX_cop0_reg, MM_cop0_reg, EX_cop0_sel, MM_cop0_sel,
EX_PC,MM_PC, v_addr,MM_v_addr, nullify,MM_nullify,
addrError,MM_addrError,
addrErr_stage_mm,MM_addrErr_stage_mm,
EX_is_delayslot,MM_is_delayslot,
EX_trapped,MM_trapped,
SL2BOOL(LL_SC_abort), MM_ll_sc_abort,
tlb_exception,MM_tlb_exception,
tlb_stage_mm,MM_tlb_stage_mm,
int_req,MM_int_req,
is_SC, MM_is_SC, is_MFC0, MM_is_MFC0,
EX_is_exception, is_exception);
-- exception_dec <= exception_type'pos(is_exception); -- debugging only
-- STATUS -- pg 79 -- cop0_12 --------------------
COP0_DECODE_EXCEPTION_AND_UPDATE_STATUS:
process (MM_a_rt, is_exception, cop0_inp,
MM_cop0_reg, MM_cop0_sel,
RF_is_delayslot, EX_is_delayslot, MM_is_delayslot, WB_is_delayslot,
rom_stall,ram_stall, STATUS)
variable newSTATUS : reg32;
variable i_update,i_epc_update,i_stall : std_logic;
variable i_nullify: boolean;
variable i_update_r : reg5;
variable i_epc_source : reg3;
begin
newSTATUS := STATUS;
i_epc_update := '1';
i_epc_source := EPC_src_PC;
i_update := '0';
i_update_r := b"00000";
i_stall := '0';
i_nullify := FALSE;
exception_taken <= '0';
interrupt_taken <= '0';
ExcCode <= cop0code_NULL;
is_delayslot <= '0';
nullify_MM_pre <= '0';
newSTATUS := STATUS; -- preserve as needed
newSTATUS(STATUS_BEV) := '0'; -- interrupts at offset 0x200, not boot
newSTATUS(STATUS_CU3) := '0'; -- COP-3 absent (always)
newSTATUS(STATUS_CU2) := '0'; -- COP-2 absent (always)
newSTATUS(STATUS_CU1) := '0'; -- COP-1 absent (always)
newSTATUS(STATUS_CU0) := '1'; -- COP-0 present=1 (always)
newSTATUS(STATUS_RP) := '0'; -- reduced power (always)
case is_exception is
when exMTC0 => -- move to COP-0
i_update_r := MM_cop0_reg;
case MM_cop0_reg is
when cop0reg_STATUS =>
newSTATUS := cop0_inp;
i_update := '1';
i_stall := '0';
when cop0reg_COUNT | cop0reg_COMPARE | cop0reg_CAUSE |
cop0reg_EntryLo0 | cop0reg_EntryLo1 | cop0reg_EntryHi |
cop0reg_Index | cop0reg_Context | cop0reg_Wired =>
i_update := '1';
i_stall := '0';
when cop0reg_EPC =>
i_epc_update := '0';
i_epc_source := EPC_src_B;
i_stall := '0';
when others =>
i_stall := '0';
i_update := '0';
end case;
when exEI => -- enable interrupts
newSTATUS(STATUS_IE) := '1';
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
when exDI => -- disable interrupts
newSTATUS(STATUS_IE) := '0';
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
when exMFC0 => -- move from COP-0
i_stall := '0'; -- register selection below
when exERET => -- EXCEPTION RETURN
newSTATUS(STATUS_EXL) := '0'; -- leave exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0'; -- do not stall
i_nullify := TRUE; -- nullify instructions in IF,RF
-- when processor goes into exception-level, IRQs are ignored,
-- hence disabled
when exSYSCALL | exBREAK => -- SYSCALL, BREAK
i_stall := '0';
if is_exception = exSYSCALL then
ExcCode <= cop0code_Sys;
else
ExcCode <= cop0code_Bp;
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
newSTATUS(STATUS_UM) := '0'; -- enter kernel mode
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0'; -- do not stall
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF
exception_taken <= '1';
if MM_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM;
is_delayslot <= MM_is_delayslot;
end if;
when exTRAP =>
ExcCode <= cop0code_Tr;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
newSTATUS(STATUS_UM) := '0'; -- enter kernel mode
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
exception_taken <= '1';
if MM_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- WB_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- MM_PC
is_delayslot <= MM_is_delayslot;
end if;
when exLL => -- load linked (not a real exception)
i_update := '1';
i_update_r := cop0reg_LLaddr;
-- when exSC => null; if treated here, SC might delay an interrupt
when exRESV_INSTR => -- reserved instruction ABORT SIMULATION
assert FALSE -- invalid opcode
report LF & "invalid opcode (resv instr) at PC="& SLV32HEX(EX_PC)
severity failure;
when exOvfl => -- OVERFLOW happened one cycle earlier
newSTATUS(STATUS_EXL) := '1'; -- at exception level
exception_taken <= '1';
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
ExcCode <= cop0code_Ov;
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
if WB_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- WB_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- offending instr PC is in MM_PC
is_delayslot <= MM_is_delayslot;
end if;
when IFaddressError => -- fetch from UNALIGNED ADDRESS
newSTATUS(STATUS_EXL) := '1'; -- at exception level
exception_taken <= '1';
i_update := '1';
i_update_r := cop0reg_STATUS;
ExcCode <= cop0code_AdEL;
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
i_epc_source := EPC_src_MM; -- bad address is in EXCP_MM_PC
i_epc_update := '0';
is_delayslot <= MM_is_delayslot;
when MMaddressErrorLD | MMaddressErrorST =>
-- load/store from/to UNALIGNED ADDRESS
newSTATUS(STATUS_EXL) := '1'; -- at exception level
exception_taken <= '1';
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
if is_exception = MMaddressErrorST then
ExcCode <= cop0code_AdES;
else
ExcCode <= cop0code_AdEL;
end if;
if WB_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- WB_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- offending instr PC is in MM_PC
is_delayslot <= MM_is_delayslot;
end if;
when exEHB => -- stall processor to clear hazards
i_stall := '1';
when exTLBP | exTLBR | exTLBWI | exTLBWR => -- TLB access
i_stall := '0'; -- do not stall the processor
when exTLBrefillIF =>
ExcCode <= cop0code_TLBL;
if RF_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_EX; -- EX_PC, re-execute branch/jump
is_delayslot <= RF_is_delayslot;
elsif EX_is_delayslot = '1' then
i_epc_source := EPC_src_MM; -- MM_PC check_this
is_delayslot <= '0';
else
i_epc_source := EPC_src_RF; -- RF_PC check_this
is_delayslot <= '0';
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
exception_taken <= '1';
when exTLBrefillRD | exTLBrefillWR =>
case is_exception is
when exTLBrefillRD =>
ExcCode <= cop0code_TLBL;
when exTLBrefillWR =>
ExcCode <= cop0code_TLBS;
when others => null;
end case;
if WB_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- MM_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- EX_PC
is_delayslot <= MM_is_delayslot;
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
exception_taken <= '1';
when exTLBdblFaultIF | exTLBinvalIF =>
ExcCode <= cop0code_TLBL;
if RF_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_RF; -- RF_PC, re-execute branch/jump
is_delayslot <= RF_is_delayslot;
else
i_epc_source := EPC_src_PC; -- PC
is_delayslot <= '0';
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
when exTLBdblFaultRD | exTLBdblFaultWR |
exTLBinvalRD | exTLBinvalWR | exTLBmod =>
case is_exception is
when exTLBinvalRD | exTLBdblFaultRD =>
ExcCode <= cop0code_TLBL;
when exTLBinvalWR | exTLBdblFaultWR =>
ExcCode <= cop0code_TLBS;
when exTLBmod =>
ExcCode <= cop0code_Mod;
when others => null;
end case;
if WB_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- MM_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- EX_PC
is_delayslot <= MM_is_delayslot;
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
when exIBE | exDBE => -- BUS ERROR
if is_exception = exIBE then
ExcCode <= cop0code_IBE;
else
ExcCode <= cop0code_DBE;
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
exception_taken <= '1';
when exInterr => -- normal interrupt
if (rom_stall = '0') and (ram_stall = '0') then
assert TRUE report "interrupt PC="&SLV32HEX(PC) severity note;
interrupt_taken <= '1';
newSTATUS(STATUS_UM) := '0'; -- enter kernel mode
newSTATUS(STATUS_EXL) := '1'; -- at exception level
ExcCode <= cop0code_Int;
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
if MM_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_MM; -- re-execute branch/jump
is_delayslot <= MM_is_delayslot;
nullify_MM_pre <= '1'; -- if stalled, kill instrn in MM
else
i_epc_source := EPC_src_EX;
is_delayslot <= EX_is_delayslot;
nullify_MM_pre <= '0';
end if;
end if;
when exNMI => -- non maskable interrupt
-- assert false report "NMinterrupt PC="&SLV32HEX(PC) severity note;
exception_taken <= '1';
newSTATUS(STATUS_BEV) := '1'; -- locationVector at bootstrap
newSTATUS(STATUS_TS) := '0'; -- not TLBmatchesSeveral
newSTATUS(STATUS_SR) := '0'; -- not softReset
newSTATUS(STATUS_NMI) := '1'; -- non maskable interrupt
newSTATUS(STATUS_ERL) := '1'; -- at error level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
if MM_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_MM; -- re-execute branch/jump
is_delayslot <= MM_is_delayslot;
nullify_MM_pre <= '1'; -- if stalled, kill instrn in MM
else
i_epc_source := EPC_src_EX;
is_delayslot <= EX_is_delayslot;
nullify_MM_pre <= '0';
end if;
when others => null;
end case;
STATUSinp <= newSTATUS;
update <= i_update;
update_reg <= i_update_r;
if is_exception = exMTC0 and MM_cop0_reg = cop0reg_EPC then
epc_update <= i_epc_update;
else
epc_update <= i_epc_update OR STATUS(STATUS_EXL);
end if;
epc_source <= i_epc_source;
exception_stall <= i_stall;
nullify <= i_nullify;
end process COP0_DECODE_EXCEPTION_AND_UPDATE_STATUS;
-- Select value to be read by instruction MFC0 --------------------
COP0_READ: process (is_exception, MM_cop0_reg, MM_cop0_sel,
INDEX, RANDOM, EntryLo0, EntryLo1,
CONTEXT, PAGEMASK, WIRED, EntryHi,
COUNT, COMPARE, STATUS, CAUSE, EPC, BadVAddr)
variable i_COP0_rd : reg32;
begin
case is_exception is
when exEI | exDI => -- enable/disable interrupts
i_COP0_rd := STATUS;
when exMFC0 => -- move from COP-0
case MM_cop0_reg is
when cop0reg_Index => i_COP0_rd := INDEX;
when cop0reg_Random => i_COP0_rd := RANDOM;
when cop0reg_EntryLo0 => i_COP0_rd := EntryLo0;
when cop0reg_EntryLo1 => i_COP0_rd := EntryLo1;
when cop0reg_Context => i_COP0_rd := CONTEXT;
when cop0reg_PageMask => i_COP0_rd := PAGEMASK;
when cop0reg_Wired => i_COP0_rd := WIRED;
when cop0reg_EntryHi => i_COP0_rd := EntryHi;
when cop0reg_COUNT => i_COP0_rd := COUNT;
when cop0reg_COMPARE => i_COP0_rd := COMPARE;
when cop0reg_STATUS => i_COP0_rd := STATUS;
when cop0reg_CAUSE => i_COP0_rd := CAUSE;
when cop0reg_EPC => i_COP0_rd := EPC;
when cop0reg_BadVAddr => i_COP0_rd := BadVAddr;
when cop0reg_CONFIG =>
if MM_cop0_sel = b"000" then
i_COP0_rd := CONFIG0; -- constant
else
i_COP0_rd := CONFIG1; -- constant
end if;
when others =>
i_COP0_rd := STATUS;
end case;
when others =>
i_COP0_rd := STATUS;
end case;
MM_cop0_val <= i_COP0_rd;
end process COP0_READ;
-- Select input to PC on an exception --------------------
COP0_SEL_EPC: process (is_exception, STATUS, CAUSE, MM_trapped)
variable i_excp_PCsel : reg3;
begin
case is_exception is
when exERET => -- exception return
i_excp_PCsel := PCsel_EXC_EPC; -- PC <= EPC
when exSYSCALL | exBREAK | exRESV_INSTR | exOvfl
| IFaddressError | MMaddressErrorLD | MMaddressErrorST
| exTLBdblFaultIF | exTLBdblFaultRD | exTLBdblFaultWR
| exTLBinvalIF | exTLBinvalRD | exTLBinvalWR | exTLBmod
| exIBE | exDBE =>
i_excp_PCsel := PCsel_EXC_0180; -- PC <= exception_180
when exTRAP =>
if MM_trapped then
i_excp_PCsel := PCsel_EXC_0180; -- PC <= exception_180
else
i_excp_PCsel := PCsel_EXC_none;
end if;
when exTLBrefillIF | exTLBrefillRD | exTLBrefillWR =>
i_excp_PCsel := PCsel_EXC_0000; -- PC <= exception_0000
when exNMI => -- non maskable interrupt
i_excp_PCsel := PCsel_EXC_BFC0; -- PC <= 0xBFC0.0000
when exInterr => -- normal interrupt
if CAUSE(CAUSE_IV) = '1' then
i_excp_PCsel := PCsel_EXC_0200; -- PC <= exception_0200
else
i_excp_PCsel := PCsel_EXC_0180; -- PC <= exception_0180
end if;
-- when exNOP =>
-- i_excp_PCsel := PCsel_EXC_none; -- no exception, do nothing to PC
when others => -- should never get here
i_excp_PCsel := PCsel_EXC_none;
end case;
excp_PCsel <= i_excp_PCsel;
end process COP0_SEL_EPC;
COP0_FORWARDING: process (WB_a_c,WB_wreg,MM_a_rt,WB_C,MM_B)
variable i_B : reg32;
begin
if ((WB_wreg = '0')and(WB_a_c /= b"00000")and(WB_a_c = MM_a_rt)) then
i_B := WB_C;
else
i_B := MM_B;
end if;
cop0_inp <= i_B;
end process COP0_FORWARDING;
-- STATUS -- pg 79 -- cop0_12 --------------------
status_update <= '0' when (update = '1' and update_reg = cop0reg_STATUS and
not_stalled = '1')
else '1';
COP0_STATUS: register32 generic map (RESET_STATUS)
port map (clk, rst, status_update, STATUSinp, STATUS);
U_DLY_TLB_EXCP: FFD
port map (clk, rst, '1', BOOL2SL(tlb_exception), tlb_excp_taken);
-- CAUSE -- pg 92-- cop0_13 --------------------------
COP0_COMPUTE_CAUSE: process(rst, clk)
-- update, update_reg,
-- MM_int_req, ExcCode, cop0_inp, is_delayslot,
-- count_eq_compare,
-- interrupt_taken, exception_taken,
-- STATUS)
variable branch_delay : std_logic;
variable excp_code : reg5;
begin
if (STATUS(STATUS_EXL) = '1') then
branch_delay := CAUSE(CAUSE_BD); -- do NOT update
else
branch_delay := is_delayslot; -- may update
end if;
if ( (interrupt_taken = '1') or (exception_taken = '1') or
(tlb_excp_taken = '1') )
then
excp_code := ExcCode; -- record new exception
elsif ( (is_exception = exMFC0) and (MM_cop0_reg = cop0reg_CAUSE) ) then
excp_code := cop0code_NULL; -- clear code when sw reads CAUSE
else
excp_code := CAUSE(CAUSE_ExcCodeHi downto CAUSE_ExcCodeLo); -- hold
end if;
if rst = '0' then
CAUSE <= RESET_CAUSE;
elsif rising_edge(clk) then
if (update = '1' and update_reg = cop0reg_CAUSE) then
CAUSE <= branch_delay & -- b31, CAUSE_BD
count_eq_compare & -- b30, CAUSE_TI timer interrupt
b"00" & -- b29,28, CAUSE_CE1,CAUSE_CE0
cop0_inp(CAUSE_DC) & -- b27, disable COUNT register
'0' & -- b26, CAUSE_PCI
b"00" & -- b25,b24, nil
cop0_inp(CAUSE_IV) & -- b23, separate interrupr vector
cop0_inp(CAUSE_WP) & -- b22, watch exception
b"000000" & -- b21..b16, nil
MM_int_req(5 downto 0) & -- b15..b10, update HW IRQs
cop0_inp(CAUSE_IP1 downto CAUSE_IP0) & -- b10,b9, SW IRQs
'0' & -- b7, nil
excp_code & -- b6..b2, ExcCode
b"00"; -- b1,b0, nil
else
CAUSE <= branch_delay & -- b31, CAUSE_BD
count_eq_compare & -- b30, CAUSE_TI timer interrupt
b"00" & -- b29,b28, CAUSE_CE1,CAUSE_CE0
CAUSE(CAUSE_DC) & -- b27, disable COUNT register
'0' & -- b26, CAUSE(CAUSE_PCI)
b"00" & -- b25,b24, nil
CAUSE(CAUSE_IV) & -- b23, separate interrupr vector
CAUSE(CAUSE_WP) & -- b22, watch exception
b"000000" & -- b21..b16, nil
MM_int_req(5 downto 0) & -- b15..b10, update HW IRQs
CAUSE(CAUSE_IP1 downto CAUSE_IP0) & -- b10,b9, SW IRQs
'0' & -- b7, nil
excp_code & -- b6..b2, ExcCode
b"00"; -- b1,b0, nil
end if;
end if;
end process COP0_COMPUTE_CAUSE;
-- EPC -- pg 97 -- cop0_14 -------------------
with epc_source select EPCinp <=
PC when EPC_src_PC, -- instr fetch exception
RF_PC when EPC_src_RF, -- invalid instr exception
EX_PC when EPC_src_EX, -- interrupt, eret, overflow
MM_PC when EPC_src_MM, -- data memory exception
WB_PC when EPC_src_WB, -- overflow in a branch delay slot
MM_B when EPC_src_B, -- mtc0
(others => 'X') when others; -- invalid selection
COP0_EPC: register32 generic map (x"00000000")
port map (clk, rst, epc_update, EPCinp, EPC);
-- COUNT & COMPARE -- pg 75, 78 -----------------
compare_update <= '0' when (update = '1' and update_reg = cop0reg_COMPARE)
else '1';
COP0_COMPARE: register32 generic map(x"00000000")
port map (clk, rst, compare_update, cop0_inp, COMPARE);
count_update <= '0' when (update = '1' and update_reg = cop0reg_COUNT)
else '1';
COP0_COUNT: counter32 generic map (x"00000001")
port map (clk, rst, count_update, count_enable, cop0_inp, COUNT);
-- port map (clk, rst, count_update, PCload, cop0_inp, COUNT); -- DEBUG
compare_set <= (count_eq_compare or BOOL2SL(COUNT = COMPARE))
when compare_update = '1'
else '0';
COP0_COUNT_INTERRUPT: FFD
port map (clk, rst, '1', compare_set, count_eq_compare);
disable_count <= CAUSE(CAUSE_DC) when (CAUSE(CAUSE_DC) /= count_enable)
else count_enable; -- load new CAUSE(CAUSE_DC)
COP0_DISABLE_COUNT: FFD port map (clk,'1',rst, disable_count, count_enable);
-- BadVAddr -- pg 74 ---------------------------
U_BadVAddr_UPDATE: process(is_exception, RF_is_delayslot, RF_PC, EX_PC,
MM_v_addr)
variable i_update : std_logic;
begin
case is_exception is
when IFaddressError | exTLBrefillIF | exTLBdblFaultIF | exTLBinvalIF =>
if RF_is_delayslot = '1' then -- instr is in delay slot
BadVAddr_inp <= EX_PC;
else
BadVAddr_inp <= RF_PC;
end if;
i_update := '0';
when MMaddressErrorLD | MMaddressErrorST | exTLBrefillRD | exTLBrefillWR
| exTLBdblFaultRD | exTLBdblFaultWR | exTLBinvalRD | exTLBinvalWR
| exTLBmod =>
BadVAddr_inp <= MM_v_addr;
i_update := '0';
when others =>
BadVAddr_inp <= (others => 'X');
i_update := '1';
end case;
BadVAddr_update <= i_update;
end process U_BadVAddr_UPDATE;
COP0_BadVAddr: register32 generic map(x"00000000")
port map (clk, rst, BadVAddr_update, BadVAddr_inp, BadVAddr);
-- LLaddr & LLbit --------------------------------------------------
-- check address of SC at stage EX, in time to kill memory reference
LL_update <= '0' when (update = '1' and update_reg = cop0reg_LLAddr)
else '1';
COP0_LLaddr: register32 generic map(x"00000000") -- update at MM
port map (clk, rst, LL_update, MM_v_addr, LLaddr);
LL_SC_differ <= '0' when (v_addr = LLaddr) else '1'; -- check at EX
LL_SC_abort <= (LL_SC_differ or not(ll_sc_bit))
when (EX_exception = exSC) -- and pipe_stall = '0')
else '0';
COP0_LLbit: process(rst,clk)
begin
if rst = '0' then
ll_sc_bit <= '0';
elsif rising_edge(clk) then
case is_exception is
when exERET =>
ll_sc_bit <= '0'; -- break SC -> LL
when exLL =>
ll_sc_bit <= not LL_update; -- update only if instr is an LL
when others =>
null;
end case;
end if;
end process COP0_LLbit;
MM_llbit <= ll_sc_bit and not(BOOL2SL(MM_ll_sc_abort));
-- MMU-TLB ===============================================================
-- assert false -- true -- DEBUG
-- report "pgSz " & integer'image(PAGE_SZ_BITS) &
-- " va-1 "& integer'image(VABITS-1) &
-- " pg+1 "& integer'image(PAGE_SZ_BITS+1) &
-- " add " & integer'image(VABITS-1 - PAGE_SZ_BITS+1) &
-- " lef "&integer'image( PC(VABITS-1 downto PAGE_SZ_BITS+1)'left)&
-- " rig "&integer'image(PC(VABITS-1 downto PAGE_SZ_BITS+1)'right);
-- MMU Index -- cop0_0 -------------------------
index_update <= '0' when (update = '1' and update_reg = cop0reg_Index)
else not(tlb_probe);
hit_mm_bit <= '0' when (hit_mm = TRUE) else '1';
with hit_mm_adr select tlb_adr_mm <= "000" when 0,
"001" when 1,
"010" when 2,
"011" when 3,
"100" when 4,
"101" when 5,
"110" when 6,
"111" when 7,
"XXX" when others;
index_inp <= hit_mm_bit & MMU_IDX_0s & tlb_adr_mm when tlb_probe = '1' else
hit_mm_bit & MMU_IDX_0s & cop0_inp(MMU_CAPACITY_BITS-1 downto 0);
MMU_Index: register32 generic map(x"00000000")
port map (clk, rst, index_update, index_inp, INDEX);
-- MMU Wired -- pg 72 -- cop0_6 ----------------
wired_update <= '0' when (update = '1' and update_reg = cop0reg_Wired)
else '1';
wired_inp <= '0' & MMU_IDX_0s & cop0_inp(MMU_CAPACITY_BITS-1 downto 0);
MMU_Wired: register32 generic map(MMU_WIRED_INIT)
port map (clk, rst, wired_update, wired_inp, WIRED);
-- MMU Random -- cop0_1 ------------------------
MMU_Random: process(clk, rst, WIRED, wired_update)
variable count : integer range -1 to MMU_CAPACITY-1 := MMU_CAPACITY-1;
begin
if rst = '0' then
count := MMU_CAPACITY - 1;
elsif rising_edge(clk) then
count := count - 1;
if count = to_integer(unsigned(WIRED))-1 or wired_update = '0' then
count := MMU_CAPACITY - 1;
end if;
end if;
RANDOM <= std_logic_vector(to_signed(count, 32));
end process MMU_Random;
-- MMU EntryLo0 -- pg 63 -- cop0_2 ------------
entryLo0_update <= '0' when (update = '1' and update_reg = cop0reg_EntryLo0)
else not(tlb_read);
entryLo0_inp <= cop0_inp when tlb_read = '0' else tlb_entryLo0;
MMU_EntryLo0: register32 generic map(x"00000000")
port map (clk, rst, entryLo0_update, entryLo0_inp, EntryLo0);
-- MMU EntryLo1 -- pg 63 -- cop0_3 ------------
entryLo1_update <= '0' when (update = '1' and update_reg = cop0reg_EntryLo1)
else not(tlb_read);
entryLo1_inp <= cop0_inp when tlb_read = '0' else tlb_entryLo1;
MMU_EntryLo1: register32 generic map(x"00000000")
port map (clk, rst, entryLo1_update, entryLo1_inp, EntryLo1);
-- MMU Context -- pg 67 -- cop0_4 ------------
context_upd_pte <= '0' when (update = '1' and update_reg = cop0reg_Context)
else '1';
--
-- these registers are non-compliant so the Page Table can be set
-- at low addresses
--
-- MMU_ContextPTE: registerN generic map(9, ContextPTE_init)
-- port map (clk, rst, context_upd_pte,
-- cop0_inp(31 downto 23), Context(31 downto 23));
MMU_ContextPTE: registerN generic map(16, b"0000000000000000")
port map (clk, rst, context_upd_pte,
cop0_inp(31 downto 16), Context(31 downto 16));
context_upd_bad <= '0' when MM_tlb_exception else '1';
-- MMU_ContextBAD: registerN generic map(19, b"0000000000000000000")
-- port map (clk, rst, context_upd_bad, tlb_context_inp, Context(22 downto 4));
MMU_ContextBAD: registerN generic map(12, b"000000000000")
port map (clk, rst, context_upd_bad,
tlb_excp_VA(VA_HI_BIT-7 downto VA_LO_BIT), Context(15 downto 4));
Context(3 downto 0) <= b"0000";
-- MMU Pagemask -- pg 68 -- cop0_5 -----------
-- page size is fixed = 4k, thus PageMask is not register
-- pageMask_update <= '0' when (update='1' and update_reg=cop0reg_PageMask)
-- else '1';
-- pageMask_inp <= cop0_inp when tlb_read = '0' else tlb_pageMask_mm;
-- MMU_PageMask: register32 generic map(x"00000000")
-- port map (clk, rst, pageMask_update, pageMask_inp, PageMask);
PageMask <= mmu_PageMask;
-- MMU EntryHi -- pg 76 -- cop0_10 -----------
-- EntryHi holds the ASID of the current process, to check for a match
entryHi_update <= '0' when ( (update = '1' and update_reg = cop0reg_EntryHi)
or ( MM_tlb_exception ) )
else not(tlb_read);
entryHi_inp <= tlb_excp_VA & EHI_ZEROS & EntryHi(EHI_G_BIT) & EntryHi(EHI_ASIDHI_BIT downto EHI_ASIDLO_BIT) when MM_tlb_exception else
cop0_inp when tlb_read = '0' else
tlb_entryhi;
MMU_EntryHi: register32 generic map(x"00000000")
port map (clk, rst, entryHi_update, entryHi_inp, EntryHi);
-- == MMU ===============================================================
-- -- pg 41 ----------------------------------
MMU_exceptions: process(iaVal, EX_wrmem, EX_aVal, hit_mm, hit_pc,
hit_mm_v, hit_mm_d, hit_pc_v, STATUS, tlb_ex_2)
variable i_stage_mm, i_exception, i_miss_mm, i_miss_pc : boolean;
variable i_excp_type : exception_type;
begin
i_miss_pc := not(hit_pc) and (iAval = '0');
i_miss_mm := not(hit_mm) and (EX_aval = '0');
-- check first for events later in the pipeline: LOADS and STORES
if i_miss_mm then
if EX_wrmem = '0' then
if STATUS(STATUS_EXL) = '1' then
i_excp_type := exTLBdblFaultWR;
else
i_excp_type := exTLBrefillWR;
end if;
else
if STATUS(STATUS_EXL) = '1' then
i_excp_type := exTLBdblFaultRD;
else
i_excp_type := exTLBrefillRD;
end if;
end if;
i_stage_mm := TRUE;
i_exception := TRUE;
elsif i_miss_pc then
if STATUS(STATUS_EXL) = '1' then
i_excp_type := exTLBdblFaultIF;
else
i_excp_type := exTLBrefillIF;
end if;
i_exception := TRUE;
i_stage_mm := FALSE;
elsif hit_mm and EX_aVal = '0' then
if hit_mm_v = '0' then -- check for TLBinvalid
if EX_wrmem = '0' then
i_excp_type := exTLBinvalWR;
else
i_excp_type := exTLBinvalRD;
end if;
i_exception := TRUE;
elsif (EX_wrmem = '0' and hit_mm_d = '0') then -- check for TLBmodified
i_excp_type := exTLBmod;
i_exception := TRUE;
else
i_excp_type := exNOP;
i_exception := FALSE;
end if;
i_stage_mm := TRUE;
elsif (hit_pc and hit_pc_v = '0' and iaVal = '0') then -- TLBinvalid IF?
i_excp_type := exTLBinvalIF;
i_stage_mm := FALSE;
i_exception := TRUE;
else
i_excp_type := exNOP;
i_stage_mm := FALSE;
i_exception := FALSE;
end if;
-- uncomment when making use of the TLB
TLB_excp_type <= i_excp_type;
tlb_stage_MM <= i_stage_mm;
tlb_exception <= i_exception and not(SL2BOOL(tlb_ex_2));
-- uncomment when NOT making use of the TLB
-- TLB_excp_type <= exNOP;
-- tlb_stage_MM <= FALSE;
-- tlb_exception <= FALSE;
end process MMU_exceptions; -- -----------------------------------------
-- catch only first exception, if there are two in consecutive cycles
U_TLB_EXCP_ONCE: FFD port map (clk, rst, '1',
BOOL2SL(tlb_exception), tlb_ex_2);
TLB_excp_num <= exception_type'pos(TLB_excp_type); -- for debugging only
-- MMU TLB TAG-DATA array -- pg 17 ------------------------------------
-- TLB_tag: 31..13 = VPN, 12..9 = 0, 8 = G, 7..0 = ASID
-- TLB_dat: 29..6 = PPN, 5..3 = C, 2 = D, 1 = V, 0 = G
MMU_CONTROL: process(is_exception, INDEX, RANDOM)
variable i_tlb_adr : integer range MMU_CAPACITY-1 downto 0;
begin
tlb_tag0_updt <= '1';
tlb_tag1_updt <= '1';
tlb_tag2_updt <= '1';
tlb_tag3_updt <= '1';
tlb_tag4_updt <= '1';
tlb_tag5_updt <= '1';
tlb_tag6_updt <= '1';
tlb_tag7_updt <= '1';
tlb_dat0_updt <= '1';
tlb_dat1_updt <= '1';
tlb_dat2_updt <= '1';
tlb_dat3_updt <= '1';
tlb_dat4_updt <= '1';
tlb_dat5_updt <= '1';
tlb_dat6_updt <= '1';
tlb_dat7_updt <= '1';
case is_exception is
when exTLBP =>
tlb_probe <= '1';
tlb_read <= '0';
i_tlb_adr := 0;
when exTLBR =>
tlb_probe <= '0';
tlb_read <= '1';
i_tlb_adr := to_integer(unsigned(INDEX(MMU_CAPACITY-1 downto 0)));
when exTLBWI | exTLBWR =>
tlb_probe <= '0';
tlb_read <= '0';
if is_exception = exTLBWI then
i_tlb_adr := to_integer(unsigned(INDEX(MMU_CAPACITY-1 downto 0)));
else
i_tlb_adr := to_integer(unsigned(RANDOM));
end if;
case i_tlb_adr is
when 0 => tlb_tag0_updt <= '0'; tlb_dat0_updt <= '0';
when 1 => tlb_tag1_updt <= '0'; tlb_dat1_updt <= '0';
when 2 => tlb_tag2_updt <= '0'; tlb_dat2_updt <= '0';
when 3 => tlb_tag3_updt <= '0'; tlb_dat3_updt <= '0';
when 4 => tlb_tag4_updt <= '0'; tlb_dat4_updt <= '0';
when 5 => tlb_tag5_updt <= '0'; tlb_dat5_updt <= '0';
when 6 => tlb_tag6_updt <= '0'; tlb_dat6_updt <= '0';
when 7 => tlb_tag7_updt <= '0'; tlb_dat7_updt <= '0';
when others => null;
end case;
when others =>
tlb_probe <= '0';
tlb_read <= '0';
i_tlb_adr := 0;
end case;
tlb_adr <= i_tlb_adr;
end process MMU_CONTROL; ------------------------------------------------
with tlb_adr select
e_hi <= tlb_tag0 when 0,
tlb_tag1 when 1,
tlb_tag2 when 2,
tlb_tag3 when 3,
tlb_tag4 when 4,
tlb_tag5 when 5,
tlb_tag6 when 6,
tlb_tag7 when others;
with tlb_adr select
e_lo0 <= tlb_dat0_0 when 0,
tlb_dat1_0 when 1,
tlb_dat2_0 when 2,
tlb_dat3_0 when 3,
tlb_dat4_0 when 4,
tlb_dat5_0 when 5,
tlb_dat6_0 when 6,
tlb_dat7_0 when others;
with tlb_adr select
e_lo1 <= tlb_dat0_1 when 0,
tlb_dat1_1 when 1,
tlb_dat2_1 when 2,
tlb_dat3_1 when 3,
tlb_dat4_1 when 4,
tlb_dat5_1 when 5,
tlb_dat6_1 when 6,
tlb_dat7_1 when others;
-- assert false
-- report "e_hi="&SLV32HEX(e_hi)&" adr="&natural'image(tlb_adr);--DEBUG
-- tlb_entryhi(EHI_AHI_BIT downto EHI_ALO_BIT)
tlb_entryhi(31 downto PAGE_SZ_BITS + 1)
<= e_hi(TAG_AHI_BIT downto TAG_ALO_BIT);
tlb_entryhi(PAGE_SZ_BITS downto EHI_ASIDHI_BIT+1) <= (others => '0');
tlb_entryhi(EHI_ASIDHI_BIT downto EHI_ASIDLO_BIT)
<= e_hi(TAG_ASIDHI_BIT downto TAG_ASIDLO_BIT);
tlb_entryLo0(31 downto ELO_AHI_BIT+1) <= (others => '0');
tlb_entryLo0(ELO_AHI_BIT downto ELO_ALO_BIT)
<= e_lo0(DAT_AHI_BIT downto DAT_ALO_BIT);
tlb_entryLo0(ELO_CHI_BIT downto ELO_CLO_BIT)
<= e_lo0(DAT_CHI_BIT downto DAT_CLO_BIT);
tlb_entryLo0(ELO_D_BIT) <= e_lo0(DAT_D_BIT);
tlb_entryLo0(ELO_V_BIT) <= e_lo0(DAT_V_BIT);
tlb_entryLo0(ELO_G_BIT) <= e_lo0(DAT_G_BIT);
tlb_entryLo1(31 downto ELO_AHI_BIT+1) <= (others => '0');
tlb_entryLo1(ELO_AHI_BIT downto ELO_ALO_BIT)
<= e_lo1(DAT_AHI_BIT downto DAT_ALO_BIT);
tlb_entryLo1(ELO_CHI_BIT downto ELO_CLO_BIT)
<= e_lo1(DAT_CHI_BIT downto DAT_CLO_BIT);
tlb_entryLo1(ELO_D_BIT) <= e_lo1(DAT_D_BIT);
tlb_entryLo1(ELO_V_BIT) <= e_lo1(DAT_V_BIT);
tlb_entryLo1(ELO_G_BIT) <= e_lo1(DAT_G_BIT);
e_hi_inp <= EntryHi(EHI_AHI_BIT downto EHI_ALO_BIT) & EHI_ZEROS &
(EntryLo0(ELO_G_BIT) and EntryLo1(ELO_G_BIT)) &
EntryHi(EHI_ASIDHI_BIT downto EHI_ASIDLO_BIT); -- pg64
tlb_tag_inp <= e_hi_inp;
tlb_dat0_inp <= EntryLo0(ELO_AHI_BIT downto ELO_G_BIT);
tlb_dat1_inp <= EntryLo1(ELO_AHI_BIT downto ELO_G_BIT);
-- MMU TLB TAG+DATA array -------------------------
mm <= entryHi(EHI_AHI_BIT downto EHI_ALO_BIT) when tlb_probe = '1' else
v_addr(VA_HI_BIT downto VA_LO_BIT);
tlb_excp_VA <= MM_v_addr(VA_HI_BIT downto VA_LO_BIT) when MM_tlb_stage_mm else
PC(VA_HI_BIT downto VA_LO_BIT);
-- TLB entry 0 -- initialized to 1st,2nd pages of ROM
-- this mapping must be pinned down at all times (Wired >= 2, see next entry)
MMU_TAG0: register32 generic map(MMU_ini_tag_ROM0)
port map (clk, rst, tlb_tag0_updt, tlb_tag_inp, tlb_tag0);
MMU_DAT0_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM0)
port map (clk, rst, tlb_dat0_updt, tlb_dat0_inp, tlb_dat0_0); -- d=1,v=1,g=1
MMU_DAT0_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM1)
port map (clk, rst, tlb_dat0_updt, tlb_dat1_inp, tlb_dat0_1); -- d=1,v=1,g=1
hit0_pc <= TRUE when (tlb_tag0(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag0(TAG_G_BIT) = '1') OR
tlb_tag0(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit0_mm <= TRUE when (tlb_tag0(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag0(TAG_G_BIT) = '1') OR
tlb_tag0(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 1 -- initialized to page with I/O devices
-- this mapping must be pinned down at all times (Wired >= 2)
MMU_TAG1: register32 generic map(MMU_ini_tag_IO)
port map (clk, rst, tlb_tag1_updt, tlb_tag_inp, tlb_tag1);
MMU_DAT1_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_IO0) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat1_updt, tlb_dat0_inp, tlb_dat1_0);
MMU_DAT1_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_IO1) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat1_updt, tlb_dat1_inp, tlb_dat1_1);
hit1_pc <= TRUE when (tlb_tag1(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag1(TAG_G_BIT) = '1') OR
tlb_tag1(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit1_mm <= TRUE when (tlb_tag1(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag1(TAG_G_BIT) = '1') OR
tlb_tag1(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 2 -- initialized to 3rd,4th pages of ROM
MMU_TAG2: register32 generic map(MMU_ini_tag_ROM2)
port map (clk, rst, tlb_tag2_updt, tlb_tag_inp, tlb_tag2);
MMU_DAT2_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM2) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat2_updt, tlb_dat0_inp, tlb_dat2_0);
MMU_DAT2_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM3) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat2_updt, tlb_dat1_inp, tlb_dat2_1);
hit2_pc <= TRUE when (tlb_tag2(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag2(TAG_G_BIT) = '1') OR
tlb_tag2(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit2_mm <= TRUE when (tlb_tag2(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag2(TAG_G_BIT) = '1') OR
tlb_tag2(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 3 -- initialized to 5th,6th pages of ROM
MMU_TAG3: register32 generic map(MMU_ini_tag_ROM4)
port map (clk, rst, tlb_tag3_updt, tlb_tag_inp, tlb_tag3);
MMU_DAT3_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM5) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat3_updt, tlb_dat0_inp, tlb_dat3_0);
MMU_DAT3_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM6) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat3_updt, tlb_dat1_inp, tlb_dat3_1);
hit3_pc <= TRUE when (tlb_tag3(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag3(TAG_G_BIT) = '1') OR
tlb_tag3(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit3_mm <= TRUE when (tlb_tag3(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag3(TAG_G_BIT) = '1') OR
tlb_tag3(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 4 -- initialized to 1st,2nd pages of RAM
MMU_TAG4: register32 generic map(MMU_ini_tag_RAM0)
port map (clk, rst, tlb_tag4_updt, tlb_tag_inp, tlb_tag4);
MMU_DAT4_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM0) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat4_updt, tlb_dat0_inp, tlb_dat4_0);
MMU_DAT4_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM1) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat4_updt, tlb_dat1_inp, tlb_dat4_1);
hit4_pc <= TRUE when (tlb_tag4(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag4(TAG_G_BIT) = '1') OR
tlb_tag4(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit4_mm <= TRUE when (tlb_tag4(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag4(TAG_G_BIT) = '1') OR
tlb_tag4(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 5 -- initialized to 3rd,4th pages of RAM
MMU_TAG5: register32 generic map(MMU_ini_tag_RAM2)
port map (clk, rst, tlb_tag5_updt, tlb_tag_inp, tlb_tag5);
MMU_DAT5_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM2) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat5_updt, tlb_dat0_inp, tlb_dat5_0);
MMU_DAT5_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM3) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat5_updt, tlb_dat1_inp, tlb_dat5_1);
hit5_pc <= TRUE when (tlb_tag5(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag5(TAG_G_BIT) = '1') OR
tlb_tag5(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit5_mm <= TRUE when (tlb_tag5(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag5(TAG_G_BIT) = '1') OR
tlb_tag5(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 6 -- initialized to RAM 5th, 6th (1st,2nd pages of SDRAM)
MMU_TAG6: register32 generic map(MMU_ini_tag_RAM4)
port map (clk, rst, tlb_tag6_updt, tlb_tag_inp, tlb_tag6);
MMU_DAT6_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM4) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat6_updt, tlb_dat0_inp, tlb_dat6_0);
MMU_DAT6_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM5) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat6_updt, tlb_dat1_inp, tlb_dat6_1);
hit6_pc <= TRUE when (tlb_tag6(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag6(TAG_G_BIT) = '1') OR
tlb_tag6(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit6_mm <= TRUE when (tlb_tag6(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag6(TAG_G_BIT) = '1') OR
tlb_tag6(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 7 -- initialized to 7th,8th pages of RAM = stack
MMU_TAG7: register32 generic map(MMU_ini_tag_RAM6)
port map (clk, rst, tlb_tag7_updt, tlb_tag_inp, tlb_tag7);
MMU_DAT7_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM6) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat7_updt, tlb_dat0_inp, tlb_dat7_0);
MMU_DAT7_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM7) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat7_updt, tlb_dat1_inp, tlb_dat7_1);
hit7_pc <= TRUE when (tlb_tag7(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag7(TAG_G_BIT) = '1') OR
tlb_tag7(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit7_mm <= TRUE when (tlb_tag7(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag7(TAG_G_BIT) = '1') OR
tlb_tag7(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- end of TLB TAG+DATA ARRAY ----------------------------------------
-- select mapping for IF --------------------------------------------
tlb_a2_pc <= 4 when (hit4_pc or hit5_pc or hit6_pc or hit7_pc) else 0;
tlb_a1_pc <= 2 when (hit2_pc or hit3_pc or hit6_pc or hit7_pc) else 0;
tlb_a0_pc <= 1 when (hit1_pc or hit3_pc or hit5_pc or hit7_pc) else 0;
hit_pc <= hit0_pc or hit1_pc or hit2_pc or hit3_pc or
hit4_pc or hit5_pc or hit6_pc or hit7_pc;
hit_pc_adr <= (tlb_a2_pc + tlb_a1_pc + tlb_a0_pc);
with hit_pc_adr select
tlb_ppn_pc0 <= tlb_dat0_0 when 0,
tlb_dat1_0 when 1,
tlb_dat2_0 when 2,
tlb_dat3_0 when 3,
tlb_dat4_0 when 4,
tlb_dat5_0 when 5,
tlb_dat6_0 when 6,
tlb_dat7_0 when others;
with hit_pc_adr select
tlb_ppn_pc1 <= tlb_dat0_1 when 0,
tlb_dat1_1 when 1,
tlb_dat2_1 when 2,
tlb_dat3_1 when 3,
tlb_dat4_1 when 4,
tlb_dat5_1 when 5,
tlb_dat6_1 when 6,
tlb_dat7_1 when others;
tlb_ppn_pc <= tlb_ppn_pc0(DAT_AHI_BIT downto DAT_ALO_BIT)
when PC(PAGE_SZ_BITS) = '0'
else tlb_ppn_pc1(DAT_AHI_BIT downto DAT_ALO_BIT);
hit_pc_v <= tlb_ppn_pc0(DAT_V_BIT) when PC(PAGE_SZ_BITS) = '0' else
tlb_ppn_pc1(DAT_V_BIT);
phy_i_addr <= tlb_ppn_pc(PPN_BITS-1 downto 0) & PC(PAGE_SZ_BITS-1 downto 0);
-- select mapping for MM --------------------------------------------
tlb_a2_mm <= 4 when (hit4_mm or hit5_mm or hit6_mm or hit7_mm) else 0;
tlb_a1_mm <= 2 when (hit2_mm or hit3_mm or hit6_mm or hit7_mm) else 0;
tlb_a0_mm <= 1 when (hit1_mm or hit3_mm or hit5_mm or hit7_mm) else 0;
hit_mm <= (hit0_mm or hit1_mm or hit2_mm or hit3_mm or
hit4_mm or hit5_mm or hit6_mm or hit7_mm);
-- and EX_mem_t /= b"0000"; -- hit AND is load or store
hit_mm_adr <= (tlb_a2_mm + tlb_a1_mm + tlb_a0_mm);
with hit_mm_adr select
tlb_ppn_mm0 <= tlb_dat0_0 when 0,
tlb_dat1_0 when 1,
tlb_dat2_0 when 2,
tlb_dat3_0 when 3,
tlb_dat4_0 when 4,
tlb_dat5_0 when 5,
tlb_dat6_0 when 6,
tlb_dat7_0 when others;
with hit_mm_adr select
tlb_ppn_mm1 <= tlb_dat0_1 when 0,
tlb_dat1_1 when 1,
tlb_dat2_1 when 2,
tlb_dat3_1 when 3,
tlb_dat4_1 when 4,
tlb_dat5_1 when 5,
tlb_dat6_1 when 6,
tlb_dat7_1 when others;
tlb_ppn_mm <= tlb_ppn_mm0(DAT_AHI_BIT downto DAT_ALO_BIT) when v_addr(PAGE_SZ_BITS) = '0' else
tlb_ppn_mm1(DAT_AHI_BIT downto DAT_ALO_BIT);
hit_mm_v <= tlb_ppn_mm0(DAT_V_BIT) when v_addr(PAGE_SZ_BITS) = '0' else
tlb_ppn_mm1(DAT_V_BIT);
hit_mm_d <= tlb_ppn_mm0(DAT_D_BIT) when v_addr(PAGE_SZ_BITS) = '0' else
tlb_ppn_mm1(DAT_D_BIT);
phy_d_addr <= tlb_ppn_mm(PPN_BITS-1 downto 0) & v_addr(PAGE_SZ_BITS-1 downto 0);
-- MMU-TLB == end =======================================================
-- ----------------------------------------------------------------------
PIPESTAGE_EXCP_MM_WB: reg_excp_MM_WB
port map (clk, rst, excp_MM_WB_ld,
MM_PC,WB_PC, MM_LLbit,WB_LLbit,
MM_is_delayslot,WB_is_delayslot,
MM_cop0_val,WB_cop0_val);
-- WB is shared with datapath -------------------------------------------
-- nothing to do here
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- end of control pipeline
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
end rtl;
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
965969baf40974bb7ee22b44e45fa9db
| 0.505177 | 3.127063 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc3s1600e/config.vhd
| 1 | 6,199 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3e;
constant CFG_MEMTECH : integer := spartan3e;
constant CFG_PADTECH : integer := spartan3e;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3e;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000018#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (10);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (40);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
1890ae85a1d448c0a48c323eb23dc6cc
| 0.644297 | 3.610367 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp605/config.vhd
| 1 | 7,707 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (3);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020605#;
constant CFG_ETH_ENL : integer := 16#000987#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
75233045c480cf1294a42c2e551b019d
| 0.653562 | 3.635377 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/aclkout.vhd
| 3 | 5,376 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic --;
-- dfflo : out std_logic;
-- dffhi : out std_logic_vector(1 downto 0) -- changed in quartus 9.0
-- dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg : std_logic;
signal clk_buf, clk_bufn : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : stratixiii_ddio_out
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "true",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => vcc,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => clk_reg
-- dfflo => open --,
-- dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => clk_reg,
o => clk_buf,
obar => clk_bufn
);
out_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => clk_buf,
oe => vcc,
dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => ddr_clk,
obar => open
);
out_bufn0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => clk_bufn,
oe => vcc,
dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => ddr_clkn,
obar => open
);
end;
|
gpl-2.0
|
c7417e20161d5cb5f8c65153aa7b3a0b
| 0.395461 | 4.540541 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ac701/config.vhd
| 1 | 7,783 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 1;
constant CFG_L2_SIZE : integer := 64;
constant CFG_L2_WAYS : integer := 1;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := 1;
constant CFG_MIG_7SERIES_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (7);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (8);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
89050411394cd5ee8af72637f600bfda
| 0.649749 | 3.568547 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/sim/sram16.vhd
| 1 | 2,402 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname, clear)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname, clear)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
|
gpl-2.0
|
6d34bc6418511582eb1f60a936fc913a
| 0.60741 | 3.724031 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-arrow-bemicro-sdk/testbench.vhd
| 1 | 7,304 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- LEON3 BeMicro SDK design testbench
-- Copyright (C) 2011 - 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal cpu_rst_n : std_ulogic := '0';
signal clk_fpga_50m : std_ulogic := '0';
-- DDR SDRAM
signal ram_a : std_logic_vector (13 downto 0); -- ddr address
signal ram_ck_p : std_logic;
signal ram_ck_n : std_logic;
signal ram_cke : std_logic;
signal ram_cs_n : std_logic;
signal ram_ws_n : std_ulogic; -- ddr write enable
signal ram_ras_n : std_ulogic; -- ddr ras
signal ram_cas_n : std_ulogic; -- ddr cas
signal ram_dm : std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
signal ram_dqs : std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
signal ram_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ram_d : std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
signal txd : std_logic_vector(3 downto 0);
signal rxd : std_logic_vector(3 downto 0);
signal tx_clk : std_logic;
signal rx_clk : std_logic;
signal tx_en : std_logic;
signal rx_dv : std_logic;
signal eth_crs : std_logic;
signal rx_er : std_logic;
signal eth_col : std_logic;
signal mdio : std_logic;
signal mdc : std_logic;
signal eth_reset_n : std_logic;
-- Temperature sensor
signal temp_sc : std_logic;
signal temp_cs_n : std_logic;
signal temp_sio : std_logic;
-- LEDs
signal f_led : std_logic_vector(7 downto 0);
-- User push-button
signal pbsw_n : std_logic;
-- Reconfig SW1 and SW2
signal reconfig_sw : std_logic_vector(2 downto 1);
-- SD card interface
signal sd_dat0 : std_logic;
signal sd_dat1 : std_logic;
signal sd_dat2 : std_logic;
signal sd_dat3 : std_logic;
signal sd_cmd : std_logic;
signal sd_clk : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal txdt : std_logic_vector(7 downto 0) := (others => '0');
signal rxdt : std_logic_vector(7 downto 0) := (others => '0');
-- EPCS
signal epcs_data : std_ulogic;
signal epcs_dclk : std_ulogic;
signal epcs_csn : std_logic;
signal epcs_asdi : std_logic;
begin
-- clock and reset
clk_fpga_50m <= not clk_fpga_50m after ct * 1 ns;
cpu_rst_n <= '0', '1' after 200 ns;
-- Push button, connected to DSU break, kept high
pbsw_n <= 'H';
reconfig_sw <= (others => 'H');
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, ncpu, disas, dbguart, pclow)
port map (
cpu_rst_n, clk_fpga_50m,
-- DDR SDRAM
ram_a, ram_ck_p, ram_ck_n, ram_cke, ram_cs_n, ram_ws_n,
ram_ras_n, ram_cas_n, ram_dm, ram_dqs, ram_ba, ram_d,
-- Ethernet PHY
txd, rxd, tx_clk, rx_clk, tx_en, rx_dv, eth_crs, rx_er,
eth_col, mdio, mdc, eth_reset_n,
-- Temperature sensor
temp_sc, temp_cs_n, temp_sio,
-- LEDs
f_led,
-- User push-button
pbsw_n,
-- Reconfig SW1 and SW2
reconfig_sw,
-- SD card interface
sd_dat0, sd_dat1, sd_dat2, sd_dat3, sd_cmd, sd_clk,
-- EPCS
epcs_data, epcs_dclk, epcs_csn, epcs_asdi
);
-- SD card signals
spiflashmod0 : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => sd_clk, di => sd_cmd, do => sd_dat0, csn => sd_dat3);
sd_dat0 <= 'Z'; sd_cmd <= 'Z';
-- EPCS
spi0: spi_flash
generic map (
ftype => 4, debug => 0, fname => promfile, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (sck => epcs_dclk, di => epcs_asdi, do => epcs_data,
csn => epcs_csn, sd_cmd_timeout => open,
sd_data_timeout => open);
-- On the BeMicro the temp_* signals are connected to a temperature sensor
temp_sc <= 'H'; temp_sio <= 'H';
-- DDR memory
ddr0 : ddrram
generic map(width => 16, abits => 14, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ram_ck_p, cke => ram_cke, csn => ram_cs_n,
rasn => ram_ras_n, casn => ram_cas_n, wen => ram_ws_n,
dm => ram_dm, ba => ram_ba, a => ram_a, dq => ram_d,
dqs => ram_dqs);
-- Ethernet PHY
mdio <= 'H'; phy_tx_er <= '0'; phy_gtx_clk <= '0';
txdt(3 downto 0) <= txd; rxd <= rxdt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(eth_reset_n, mdio, tx_clk, rx_clk, rxdt, rx_dv,
rx_er, eth_col, eth_crs, txdt, tx_en, phy_tx_er, mdc,
phy_gtx_clk);
-- LEDs
f_led <= (others => 'H');
-- Processor error mode indicator is connected to led(6).
iuerr : process
begin
wait for 2500 ns;
if to_x01(f_led(6)) = '1' then wait on f_led(6); end if;
assert (to_x01(f_led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
gpl-2.0
|
2cdac24efe1ef5e9cfa460332e221804
| 0.5727 | 3.421077 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml605/testbench.vhd
| 1 | 12,388 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
use work.ml605.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal ddr3_dm : std_logic_vector(DM_WIDTH-1 downto 0);
signal ddr3_addr : std_logic_vector(ROW_WIDTH-1 downto 0);
signal ddr3_ba : std_logic_vector(BANK_WIDTH-1 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_cs_n : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_odt : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_cke : std_logic_vector(CKE_WIDTH-1 downto 0);
signal ddr3_dqs_p : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_dqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_tdqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_ck_p : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_ck_n : std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_logic;
signal egtx_clk : std_logic;
signal gmiiclk_p : std_logic := '1';
signal gmiiclk_n : std_logic := '0';
-- Output signals for LEDs
signal led : std_logic_vector(6 downto 0);
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_dvi, iic_sda_dvi : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal clk_33 : std_ulogic := '0';
signal brdyn : std_ulogic;
---------------------pcie----------------------------------------------
signal cor_sys_reset_n : std_logic := '1';
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
signal rp_sys_clk : std_logic;
signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
---------------------pcie end---------------------------------------------
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
gmiiclk_p <= not gmiiclk_p after 4 ns;
gmiiclk_n <= not gmiiclk_n after 4 ns;
clk_33 <= not clk_33 after 15 ns;
rst <= '1', '0' after 200 us;
rstn1 <= not rst;
dsubre <= '0';
urxd <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, disas, dbguart, pclow,
SIM_BYPASS_INIT_CAL)
port map (
reset => rst,
errorn => error,
clk_ref_p => clk200p,
clk_ref_n => clk200n,
-- PROM
address => address(24 downto 1),
data => data(15 downto 0),
romsn => romsn,
oen => oen,
writen => writen,
-- DDR3
ddr3_dq => ddr3_dq,
ddr3_dm => ddr3_dm,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
gmiiclk_p => gmiiclk_p,
gmiiclk_n => gmiiclk_n,
egtx_clk => egtx_clk,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
emdint => emdint,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- Output signals for LEDs
iic_scl_main => iic_scl_main,
iic_sda_main => iic_sda_main,
dvi_iic_scl => iic_scl_dvi,
dvi_iic_sda => iic_sda_dvi,
tft_lcd_data => tft_lcd_data,
tft_lcd_clk_p => tft_lcd_clk_p,
tft_lcd_clk_n => tft_lcd_clk_n,
tft_lcd_hsync => tft_lcd_hsync,
tft_lcd_vsync => tft_lcd_vsync,
tft_lcd_de => tft_lcd_de,
tft_lcd_reset_b => tft_lcd_reset_b,
clk_33 => clk_33,
sysace_mpa => sysace_mpa,
sysace_mpce => sysace_mpce,
sysace_mpirq => sysace_mpirq,
sysace_mpoe => sysace_mpoe,
sysace_mpwe => sysace_mpwe,
sysace_d => sysace_d,
pci_exp_txp=> cor_pci_exp_txp,
pci_exp_txn=> cor_pci_exp_txn,
pci_exp_rxp=> cor_pci_exp_rxp,
pci_exp_rxn=> cor_pci_exp_rxn,
sys_clk_p=> ep_sys_clk_p,
sys_clk_n=> ep_sys_clk_n,
sys_reset_n=> cor_sys_reset_n,
led => led
);
u1 : ddr3ram
generic map (
width => 64,
abits => 13,
colbits => 10,
rowbits => 13,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 32)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
address(0) <= '0';
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 7)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, egtx_clk);
end generate;
-- spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
-- end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
gpl-2.0
|
d6f53d1e375a157491f486040ca2b645
| 0.551824 | 3.221009 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/testgrouppolito/pr/dprc_pkg.vhd
| 1 | 22,419 |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: dprc_pkg
-- File: dprc_pkg.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc package including types definitions, procedures and components declarations
-- Last revision: 29/09/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library techmap;
use techmap.gencomp.all;
package dprc_pkg is
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
-- ICAP I/O signals
type icap_in_type is record
idata : std_logic_vector(31 downto 0);
wen : std_ulogic;
cen : std_ulogic;
end record;
type icap_out_type is record
odata : std_logic_vector(31 downto 0);
busy : std_ulogic;
end record;
-- read-only APB registers
type dprc_apbregout_type is record
status : std_logic_vector(31 downto 0);
timer : std_logic_vector(31 downto 0);
end record;
-- control signals for APB registers
type dprc_apbcontrol_type is record
status_value : std_logic_vector(31 downto 0);
control_clr : std_ulogic;
status_en : std_ulogic;
status_clr : std_ulogic;
timer_en : std_ulogic;
timer_clear : std_ulogic;
end record;
-- write/read APB registers
type dprc_apbregin_type is record
control : std_logic_vector(31 downto 0);
address : std_logic_vector(31 downto 0);
rm_reset : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- Functions & Procedures
-------------------------------------------------------------------------------
procedure icapbyteswap(signal idata : in std_logic_vector(31 downto 0); signal odata : out std_logic_vector(31 downto 0));
procedure crc(signal idata : in std_logic_vector(31 downto 0); signal q : in std_logic_vector(31 downto 0); variable d : out std_logic_vector(31 downto 0));
procedure gray_encoder(variable idata : in std_logic_vector; variable odata : out std_logic_vector);
procedure gray_decoder(signal idata : in std_logic_vector; constant size : integer; variable odata : out std_logic_vector);
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component dprc is
generic (
cfg_clkmul : integer := 2; -- clkraw multiplier
cfg_clkdiv : integer := 1; -- clkraw divisor
raw_freq : integer := 50000; -- Board frequency in KHz
clk_sel : integer := 0; -- Select between clkraw and clk100 for ICAP domain clk when configured in async or d2prc mode
hindex : integer := 2; -- AMBA AHB master index
vendorid : integer := VENDOR_CONTRIB; -- Vendor ID
deviceid : integer := CONTRIB_CORE1; -- Device ID
version : integer := 1; -- Device version
pindex : integer := 13; -- AMBA APB slave index
paddr : integer := 13; -- Address for APB I/O BAR
pmask : integer := 16#fff#; -- Mask for APB I/O BAR
technology : integer := virtex4; -- FPGA target technology
crc_en : integer := 0; -- Bitstream verification enable (d2prc mode)
words_block : integer := 10; -- Number of 32-bit words in a CRC-block
fifo_dcm_inst : integer := 1; -- Instantiate clock generator and fifo (async/sync mode)
fifo_depth : integer := 9); -- Number of addressing bits for the FIFO (true FIFO depth = 2**fifo_depth)
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clkraw : in std_ulogic; -- Raw Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
ahbmi : in ahb_mst_in_type; -- AHB master input
ahbmo : out ahb_mst_out_type; -- AHB master output
apbi : in apb_slv_in_type; -- APB slave input
apbo : out apb_slv_out_type; -- APB slave output
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition)
end component;
component d2prc is
generic (
technology : integer := virtex4; -- FPGA target technology
fifo_depth : integer := 9; -- true FIFO depth = 2**fifo_depth
crc_block : integer := 10); -- Number of 32-bit words in a CRC-block
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition));
end component;
component async_dprc is
generic (
technology : integer := virtex4; -- Target technology
fifo_depth : integer := 9); -- true FIFO depth = 2**fifo_depth
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition));
end component;
component sync_dprc is
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition));
end component;
end package;
package body dprc_pkg is
procedure icapbyteswap(signal idata : in std_logic_vector(31 downto 0); signal odata : out std_logic_vector(31 downto 0)) is
begin
for i in 0 to 3 loop
for j in 0+i*8 to 7+i*8 loop
odata(j)<=idata(7+i*8-(j-i*8));
end loop;
end loop;
end icapbyteswap;
procedure crc(signal idata : in std_logic_vector(31 downto 0); signal q : in std_logic_vector(31 downto 0); variable d : out std_logic_vector(31 downto 0)) is
-------------------------------------------------------------------------------
-- Copyright (C) 2009 OutputLogic.com
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-------------------------------------------------------------------------------
variable dv : std_logic_vector(31 downto 0);
begin
d(0) := q(0) xor q(3) xor q(6) xor q(9) xor q(12) xor q(14) xor q(15) xor q(20) xor q(21) xor q(26) xor q(27) xor q(28) xor q(29) xor q(31) xor idata(0) xor idata(3) xor idata(6) xor idata(9) xor idata(12) xor idata(14) xor idata(15) xor idata(20) xor idata(21) xor idata(26) xor idata(27) xor idata(28) xor idata(29) xor idata(31);
d(1) := q(1) xor q(4) xor q(7) xor q(10) xor q(13) xor q(15) xor q(16) xor q(21) xor q(22) xor q(27) xor q(28) xor q(29) xor q(30) xor idata(1) xor idata(4) xor idata(7) xor idata(10) xor idata(13) xor idata(15) xor idata(16) xor idata(21) xor idata(22) xor idata(27) xor idata(28) xor idata(29) xor idata(30);
d(2) := q(2) xor q(5) xor q(8) xor q(11) xor q(14) xor q(16) xor q(17) xor q(22) xor q(23) xor q(28) xor q(29) xor q(30) xor q(31) xor idata(2) xor idata(5) xor idata(8) xor idata(11) xor idata(14) xor idata(16) xor idata(17) xor idata(22) xor idata(23) xor idata(28) xor idata(29) xor idata(30) xor idata(31);
d(3) := q(0) xor q(14) xor q(17) xor q(18) xor q(20) xor q(21) xor q(23) xor q(24) xor q(26) xor q(27) xor q(28) xor q(30) xor idata(0) xor idata(14) xor idata(17) xor idata(18) xor idata(20) xor idata(21) xor idata(23) xor idata(24) xor idata(26) xor idata(27) xor idata(28) xor idata(30);
d(4) := q(1) xor q(15) xor q(18) xor q(19) xor q(21) xor q(22) xor q(24) xor q(25) xor q(27) xor q(28) xor q(29) xor q(31) xor idata(1) xor idata(15) xor idata(18) xor idata(19) xor idata(21) xor idata(22) xor idata(24) xor idata(25) xor idata(27) xor idata(28) xor idata(29) xor idata(31);
d(5) := q(2) xor q(16) xor q(19) xor q(20) xor q(22) xor q(23) xor q(25) xor q(26) xor q(28) xor q(29) xor q(30) xor idata(2) xor idata(16) xor idata(19) xor idata(20) xor idata(22) xor idata(23) xor idata(25) xor idata(26) xor idata(28) xor idata(29) xor idata(30);
d(6) := q(3) xor q(17) xor q(20) xor q(21) xor q(23) xor q(24) xor q(26) xor q(27) xor q(29) xor q(30) xor q(31) xor idata(3) xor idata(17) xor idata(20) xor idata(21) xor idata(23) xor idata(24) xor idata(26) xor idata(27) xor idata(29) xor idata(30) xor idata(31);
d(7) := q(4) xor q(18) xor q(21) xor q(22) xor q(24) xor q(25) xor q(27) xor q(28) xor q(30) xor q(31) xor idata(4) xor idata(18) xor idata(21) xor idata(22) xor idata(24) xor idata(25) xor idata(27) xor idata(28) xor idata(30) xor idata(31);
d(8) := q(5) xor q(19) xor q(22) xor q(23) xor q(25) xor q(26) xor q(28) xor q(29) xor q(31) xor idata(5) xor idata(19) xor idata(22) xor idata(23) xor idata(25) xor idata(26) xor idata(28) xor idata(29) xor idata(31);
d(9) := q(6) xor q(20) xor q(23) xor q(24) xor q(26) xor q(27) xor q(29) xor q(30) xor idata(6) xor idata(20) xor idata(23) xor idata(24) xor idata(26) xor idata(27) xor idata(29) xor idata(30);
d(10) := q(7) xor q(21) xor q(24) xor q(25) xor q(27) xor q(28) xor q(30) xor q(31) xor idata(7) xor idata(21) xor idata(24) xor idata(25) xor idata(27) xor idata(28) xor idata(30) xor idata(31);
d(11) := q(8) xor q(22) xor q(25) xor q(26) xor q(28) xor q(29) xor q(31) xor idata(8) xor idata(22) xor idata(25) xor idata(26) xor idata(28) xor idata(29) xor idata(31);
d(12) := q(9) xor q(23) xor q(26) xor q(27) xor q(29) xor q(30) xor idata(9) xor idata(23) xor idata(26) xor idata(27) xor idata(29) xor idata(30);
d(13) := q(10) xor q(24) xor q(27) xor q(28) xor q(30) xor q(31) xor idata(10) xor idata(24) xor idata(27) xor idata(28) xor idata(30) xor idata(31);
d(14) := q(0) xor q(3) xor q(6) xor q(9) xor q(11) xor q(12) xor q(14) xor q(15) xor q(20) xor q(21) xor q(25) xor q(26) xor q(27) xor idata(0) xor idata(3) xor idata(6) xor idata(9) xor idata(11) xor idata(12) xor idata(14) xor idata(15) xor idata(20) xor idata(21) xor idata(25) xor idata(26) xor idata(27);
d(15) := q(1) xor q(4) xor q(7) xor q(10) xor q(12) xor q(13) xor q(15) xor q(16) xor q(21) xor q(22) xor q(26) xor q(27) xor q(28) xor idata(1) xor idata(4) xor idata(7) xor idata(10) xor idata(12) xor idata(13) xor idata(15) xor idata(16) xor idata(21) xor idata(22) xor idata(26) xor idata(27) xor idata(28);
d(16) := q(2) xor q(5) xor q(8) xor q(11) xor q(13) xor q(14) xor q(16) xor q(17) xor q(22) xor q(23) xor q(27) xor q(28) xor q(29) xor idata(2) xor idata(5) xor idata(8) xor idata(11) xor idata(13) xor idata(14) xor idata(16) xor idata(17) xor idata(22) xor idata(23) xor idata(27) xor idata(28) xor idata(29);
d(17) := q(3) xor q(6) xor q(9) xor q(12) xor q(14) xor q(15) xor q(17) xor q(18) xor q(23) xor q(24) xor q(28) xor q(29) xor q(30) xor idata(3) xor idata(6) xor idata(9) xor idata(12) xor idata(14) xor idata(15) xor idata(17) xor idata(18) xor idata(23) xor idata(24) xor idata(28) xor idata(29) xor idata(30);
d(18) := q(0) xor q(3) xor q(4) xor q(6) xor q(7) xor q(9) xor q(10) xor q(12) xor q(13) xor q(14) xor q(16) xor q(18) xor q(19) xor q(20) xor q(21) xor q(24) xor q(25) xor q(26) xor q(27) xor q(28) xor q(30) xor idata(0) xor idata(3) xor idata(4) xor idata(6) xor idata(7) xor idata(9) xor idata(10) xor idata(12) xor idata(13) xor idata(14) xor idata(16) xor idata(18) xor idata(19) xor idata(20) xor idata(21) xor idata(24) xor idata(25) xor idata(26) xor idata(27) xor idata(28) xor idata(30);
d(19) := q(1) xor q(4) xor q(5) xor q(7) xor q(8) xor q(10) xor q(11) xor q(13) xor q(14) xor q(15) xor q(17) xor q(19) xor q(20) xor q(21) xor q(22) xor q(25) xor q(26) xor q(27) xor q(28) xor q(29) xor q(31) xor idata(1) xor idata(4) xor idata(5) xor idata(7) xor idata(8) xor idata(10) xor idata(11) xor idata(13) xor idata(14) xor idata(15) xor idata(17) xor idata(19) xor idata(20) xor idata(21) xor idata(22) xor idata(25) xor idata(26) xor idata(27) xor idata(28) xor idata(29) xor idata(31);
d(20) := q(2) xor q(5) xor q(6) xor q(8) xor q(9) xor q(11) xor q(12) xor q(14) xor q(15) xor q(16) xor q(18) xor q(20) xor q(21) xor q(22) xor q(23) xor q(26) xor q(27) xor q(28) xor q(29) xor q(30) xor idata(2) xor idata(5) xor idata(6) xor idata(8) xor idata(9) xor idata(11) xor idata(12) xor idata(14) xor idata(15) xor idata(16) xor idata(18) xor idata(20) xor idata(21) xor idata(22) xor idata(23) xor idata(26) xor idata(27) xor idata(28) xor idata(29) xor idata(30);
d(21) := q(3) xor q(6) xor q(7) xor q(9) xor q(10) xor q(12) xor q(13) xor q(15) xor q(16) xor q(17) xor q(19) xor q(21) xor q(22) xor q(23) xor q(24) xor q(27) xor q(28) xor q(29) xor q(30) xor q(31) xor idata(3) xor idata(6) xor idata(7) xor idata(9) xor idata(10) xor idata(12) xor idata(13) xor idata(15) xor idata(16) xor idata(17) xor idata(19) xor idata(21) xor idata(22) xor idata(23) xor idata(24) xor idata(27) xor idata(28) xor idata(29) xor idata(30) xor idata(31);
d(22) := q(4) xor q(7) xor q(8) xor q(10) xor q(11) xor q(13) xor q(14) xor q(16) xor q(17) xor q(18) xor q(20) xor q(22) xor q(23) xor q(24) xor q(25) xor q(28) xor q(29) xor q(30) xor q(31) xor idata(4) xor idata(7) xor idata(8) xor idata(10) xor idata(11) xor idata(13) xor idata(14) xor idata(16) xor idata(17) xor idata(18) xor idata(20) xor idata(22) xor idata(23) xor idata(24) xor idata(25) xor idata(28) xor idata(29) xor idata(30) xor idata(31);
d(23) := q(5) xor q(8) xor q(9) xor q(11) xor q(12) xor q(14) xor q(15) xor q(17) xor q(18) xor q(19) xor q(21) xor q(23) xor q(24) xor q(25) xor q(26) xor q(29) xor q(30) xor q(31) xor idata(5) xor idata(8) xor idata(9) xor idata(11) xor idata(12) xor idata(14) xor idata(15) xor idata(17) xor idata(18) xor idata(19) xor idata(21) xor idata(23) xor idata(24) xor idata(25) xor idata(26) xor idata(29) xor idata(30) xor idata(31);
d(24) := q(6) xor q(9) xor q(10) xor q(12) xor q(13) xor q(15) xor q(16) xor q(18) xor q(19) xor q(20) xor q(22) xor q(24) xor q(25) xor q(26) xor q(27) xor q(30) xor q(31) xor idata(6) xor idata(9) xor idata(10) xor idata(12) xor idata(13) xor idata(15) xor idata(16) xor idata(18) xor idata(19) xor idata(20) xor idata(22) xor idata(24) xor idata(25) xor idata(26) xor idata(27) xor idata(30) xor idata(31);
d(25) := q(7) xor q(10) xor q(11) xor q(13) xor q(14) xor q(16) xor q(17) xor q(19) xor q(20) xor q(21) xor q(23) xor q(25) xor q(26) xor q(27) xor q(28) xor q(31) xor idata(7) xor idata(10) xor idata(11) xor idata(13) xor idata(14) xor idata(16) xor idata(17) xor idata(19) xor idata(20) xor idata(21) xor idata(23) xor idata(25) xor idata(26) xor idata(27) xor idata(28) xor idata(31);
d(26) := q(8) xor q(11) xor q(12) xor q(14) xor q(15) xor q(17) xor q(18) xor q(20) xor q(21) xor q(22) xor q(24) xor q(26) xor q(27) xor q(28) xor q(29) xor idata(8) xor idata(11) xor idata(12) xor idata(14) xor idata(15) xor idata(17) xor idata(18) xor idata(20) xor idata(21) xor idata(22) xor idata(24) xor idata(26) xor idata(27) xor idata(28) xor idata(29);
d(27) := q(9) xor q(12) xor q(13) xor q(15) xor q(16) xor q(18) xor q(19) xor q(21) xor q(22) xor q(23) xor q(25) xor q(27) xor q(28) xor q(29) xor q(30) xor idata(9) xor idata(12) xor idata(13) xor idata(15) xor idata(16) xor idata(18) xor idata(19) xor idata(21) xor idata(22) xor idata(23) xor idata(25) xor idata(27) xor idata(28) xor idata(29) xor idata(30);
d(28) := q(10) xor q(13) xor q(14) xor q(16) xor q(17) xor q(19) xor q(20) xor q(22) xor q(23) xor q(24) xor q(26) xor q(28) xor q(29) xor q(30) xor q(31) xor idata(10) xor idata(13) xor idata(14) xor idata(16) xor idata(17) xor idata(19) xor idata(20) xor idata(22) xor idata(23) xor idata(24) xor idata(26) xor idata(28) xor idata(29) xor idata(30) xor idata(31);
d(29) := q(0) xor q(3) xor q(6) xor q(9) xor q(11) xor q(12) xor q(17) xor q(18) xor q(23) xor q(24) xor q(25) xor q(26) xor q(28) xor q(30) xor idata(0) xor idata(3) xor idata(6) xor idata(9) xor idata(11) xor idata(12) xor idata(17) xor idata(18) xor idata(23) xor idata(24) xor idata(25) xor idata(26) xor idata(28) xor idata(30);
d(30) := q(1) xor q(4) xor q(7) xor q(10) xor q(12) xor q(13) xor q(18) xor q(19) xor q(24) xor q(25) xor q(26) xor q(27) xor q(29) xor q(31) xor idata(1) xor idata(4) xor idata(7) xor idata(10) xor idata(12) xor idata(13) xor idata(18) xor idata(19) xor idata(24) xor idata(25) xor idata(26) xor idata(27) xor idata(29) xor idata(31);
d(31) := q(2) xor q(5) xor q(8) xor q(11) xor q(13) xor q(14) xor q(19) xor q(20) xor q(25) xor q(26) xor q(27) xor q(28) xor q(30) xor idata(2) xor idata(5) xor idata(8) xor idata(11) xor idata(13) xor idata(14) xor idata(19) xor idata(20) xor idata(25) xor idata(26) xor idata(27) xor idata(28) xor idata(30);
end crc;
procedure gray_encoder(variable idata : in std_logic_vector; variable odata : out std_logic_vector) is
begin
for i in 0 to (idata'left)-1 loop
odata(i) := idata(i) xor idata(i+1);
end loop;
odata(odata'left) := idata(idata'left);
end gray_encoder;
procedure gray_decoder(signal idata : in std_logic_vector; constant size : integer; variable odata : out std_logic_vector) is
variable vdata : std_logic_vector(size downto 0);
begin
vdata(vdata'left) := idata(idata'left);
for i in (idata'left)-1 downto 0 loop
vdata(i) := idata(i) xor vdata(i+1);
end loop;
odata := vdata;
end gray_decoder;
end package body;
|
gpl-2.0
|
78863066126606bb84a68eb00e7b129e
| 0.589991 | 3.212812 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25-eek/ahbrom.vhd
| 3 | 8,961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A803";
when 16#00069# => romdata <= X"8410A261";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
d7b1ee9ce4b4668dab5e3746639278a8
| 0.58085 | 3.28844 | false | false | false | false |
aortiz49/MIPS-Processor
|
Testbenches/extender_tb.vhd
| 1 | 835 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity extender_tb is
end extender_tb;
architecture TB of extender_tb is
component extender
port(
in0 : in std_logic_vector(15 downto 0);
Sel : in std_logic;
out0 : out std_logic_vector(31 downto 0));
end component;
signal in0 : std_logic_vector(15 downto 0);
signal Sel : std_logic;
signal out0 : std_logic_vector(31 downto 0);
begin -- TB
UUT: entity work.extender
port map(
in0 => in0,
Sel => Sel,
out0 => out0);
process
begin
in0 <= x"7FFF";
Sel <= '0';
wait for 20 ns;
in0 <= x"7FFF";
Sel <= '1';
wait for 20 ns;
in0 <= x"FFFF";
Sel <= '0';
wait for 20 ns;
in0 <= x"FFFF";
Sel <= '1';
wait for 20 ns;
report "SIMULATION FINISHED!";
wait;
end process;
end TB;
|
mit
|
0cc1bd037fa25a2663c7f093c79ea018
| 0.598802 | 2.625786 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/sparc/sparc.vhd
| 1 | 11,241 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: opcodes
-- File: opcodes.vhd
-- Author: Jiri Gaisler
-- Description: Instruction definitions according to the SPARC V8 manual.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sparc is
-- op decoding (inst(31 downto 30))
subtype op_type is std_logic_vector(1 downto 0);
constant FMT2 : op_type := "00";
constant CALL : op_type := "01";
constant FMT3 : op_type := "10";
constant LDST : op_type := "11";
-- op2 decoding (inst(24 downto 22))
subtype op2_type is std_logic_vector(2 downto 0);
constant UNIMP : op2_type := "000";
constant BICC : op2_type := "010";
constant SETHI : op2_type := "100";
constant FBFCC : op2_type := "110";
constant CBCCC : op2_type := "111";
-- op3 decoding (inst(24 downto 19))
subtype op3_type is std_logic_vector(5 downto 0);
constant IADD : op3_type := "000000";
constant IAND : op3_type := "000001";
constant IOR : op3_type := "000010";
constant IXOR : op3_type := "000011";
constant ISUB : op3_type := "000100";
constant ANDN : op3_type := "000101";
constant ORN : op3_type := "000110";
constant IXNOR : op3_type := "000111";
constant ADDX : op3_type := "001000";
constant UMUL : op3_type := "001010";
constant SMUL : op3_type := "001011";
constant SUBX : op3_type := "001100";
constant UDIV : op3_type := "001110";
constant SDIV : op3_type := "001111";
constant ADDCC : op3_type := "010000";
constant ANDCC : op3_type := "010001";
constant ORCC : op3_type := "010010";
constant XORCC : op3_type := "010011";
constant SUBCC : op3_type := "010100";
constant ANDNCC : op3_type := "010101";
constant ORNCC : op3_type := "010110";
constant XNORCC : op3_type := "010111";
constant ADDXCC : op3_type := "011000";
constant UMULCC : op3_type := "011010";
constant SMULCC : op3_type := "011011";
constant SUBXCC : op3_type := "011100";
constant UDIVCC : op3_type := "011110";
constant SDIVCC : op3_type := "011111";
constant TADDCC : op3_type := "100000";
constant TSUBCC : op3_type := "100001";
constant TADDCCTV : op3_type := "100010";
constant TSUBCCTV : op3_type := "100011";
constant MULSCC : op3_type := "100100";
constant ISLL : op3_type := "100101";
constant ISRL : op3_type := "100110";
constant ISRA : op3_type := "100111";
constant RDY : op3_type := "101000";
constant RDPSR : op3_type := "101001";
constant RDWIM : op3_type := "101010";
constant RDTBR : op3_type := "101011";
constant WRY : op3_type := "110000";
constant WRPSR : op3_type := "110001";
constant WRWIM : op3_type := "110010";
constant WRTBR : op3_type := "110011";
constant FPOP1 : op3_type := "110100";
constant FPOP2 : op3_type := "110101";
constant CPOP1 : op3_type := "110110";
constant CPOP2 : op3_type := "110111";
constant JMPL : op3_type := "111000";
constant TICC : op3_type := "111010";
constant FLUSH : op3_type := "111011";
constant RETT : op3_type := "111001";
constant SAVE : op3_type := "111100";
constant RESTORE : op3_type := "111101";
constant UMAC : op3_type := "111110";
constant SMAC : op3_type := "111111";
constant LD : op3_type := "000000";
constant LDUB : op3_type := "000001";
constant LDUH : op3_type := "000010";
constant LDD : op3_type := "000011";
constant LDSB : op3_type := "001001";
constant LDSH : op3_type := "001010";
constant LDSTUB : op3_type := "001101";
constant SWAP : op3_type := "001111";
constant LDA : op3_type := "010000";
constant LDUBA : op3_type := "010001";
constant LDUHA : op3_type := "010010";
constant LDDA : op3_type := "010011";
constant LDSBA : op3_type := "011001";
constant LDSHA : op3_type := "011010";
constant LDSTUBA : op3_type := "011101";
constant SWAPA : op3_type := "011111";
constant LDF : op3_type := "100000";
constant LDFSR : op3_type := "100001";
constant LDDF : op3_type := "100011";
constant LDC : op3_type := "110000";
constant LDCSR : op3_type := "110001";
constant LDDC : op3_type := "110011";
constant ST : op3_type := "000100";
constant STB : op3_type := "000101";
constant STH : op3_type := "000110";
constant ISTD : op3_type := "000111";
constant STA : op3_type := "010100";
constant STBA : op3_type := "010101";
constant STHA : op3_type := "010110";
constant STDA : op3_type := "010111";
constant STF : op3_type := "100100";
constant STFSR : op3_type := "100101";
constant STDFQ : op3_type := "100110";
constant STDF : op3_type := "100111";
constant STC : op3_type := "110100";
constant STCSR : op3_type := "110101";
constant STDCQ : op3_type := "110110";
constant STDC : op3_type := "110111";
constant CASA : op3_type := "111100";
-- bicc decoding (inst(27 downto 25))
constant BA : std_logic_vector(3 downto 0) := "1000";
-- fpop1 decoding
subtype fpop_type is std_logic_vector(8 downto 0);
constant FITOS : fpop_type := "011000100";
constant FITOD : fpop_type := "011001000";
constant FITOQ : fpop_type := "011001100";
constant FSTOI : fpop_type := "011010001";
constant FDTOI : fpop_type := "011010010";
constant FQTOI : fpop_type := "011010011";
constant FSTOD : fpop_type := "011001001";
constant FSTOQ : fpop_type := "011001101";
constant FDTOS : fpop_type := "011000110";
constant FDTOQ : fpop_type := "011001110";
constant FQTOS : fpop_type := "011000111";
constant FQTOD : fpop_type := "011001011";
constant FMOVS : fpop_type := "000000001";
constant FNEGS : fpop_type := "000000101";
constant FABSS : fpop_type := "000001001";
constant FSQRTS : fpop_type := "000101001";
constant FSQRTD : fpop_type := "000101010";
constant FSQRTQ : fpop_type := "000101011";
constant FADDS : fpop_type := "001000001";
constant FADDD : fpop_type := "001000010";
constant FADDQ : fpop_type := "001000011";
constant FSUBS : fpop_type := "001000101";
constant FSUBD : fpop_type := "001000110";
constant FSUBQ : fpop_type := "001000111";
constant FMULS : fpop_type := "001001001";
constant FMULD : fpop_type := "001001010";
constant FMULQ : fpop_type := "001001011";
constant FSMULD : fpop_type := "001101001";
constant FDMULQ : fpop_type := "001101110";
constant FDIVS : fpop_type := "001001101";
constant FDIVD : fpop_type := "001001110";
constant FDIVQ : fpop_type := "001001111";
-- fpop2 decoding
constant FCMPS : fpop_type := "001010001";
constant FCMPD : fpop_type := "001010010";
constant FCMPQ : fpop_type := "001010011";
constant FCMPES : fpop_type := "001010101";
constant FCMPED : fpop_type := "001010110";
constant FCMPEQ : fpop_type := "001010111";
-- trap type decoding
subtype trap_type is std_logic_vector(5 downto 0);
constant TT_IAEX : trap_type := "000001";
constant TT_IINST : trap_type := "000010";
constant TT_PRIV : trap_type := "000011";
constant TT_FPDIS : trap_type := "000100";
constant TT_WINOF : trap_type := "000101";
constant TT_WINUF : trap_type := "000110";
constant TT_UNALA : trap_type := "000111";
constant TT_FPEXC : trap_type := "001000";
constant TT_DAEX : trap_type := "001001";
constant TT_TAG : trap_type := "001010";
constant TT_WATCH : trap_type := "001011";
constant TT_DSU : trap_type := "010000";
constant TT_PWD : trap_type := "010001";
constant TT_RFERR : trap_type := "100000";
constant TT_IAERR : trap_type := "100001";
constant TT_CPDIS : trap_type := "100100";
constant TT_CPEXC : trap_type := "101000";
constant TT_DIV : trap_type := "101010";
constant TT_DSEX : trap_type := "101011";
constant TT_TICC : trap_type := "111111";
-- Alternate address space identifiers
subtype asi_type is std_logic_vector(4 downto 0);
constant ASI_SYSR : asi_type := "00010"; -- 0x02
constant ASI_UINST : asi_type := "01000"; -- 0x08
constant ASI_SINST : asi_type := "01001"; -- 0x09
constant ASI_UDATA : asi_type := "01010"; -- 0x0A
constant ASI_SDATA : asi_type := "01011"; -- 0x0B
constant ASI_ITAG : asi_type := "01100"; -- 0x0C
constant ASI_IDATA : asi_type := "01101"; -- 0x0D
constant ASI_DTAG : asi_type := "01110"; -- 0x0E
constant ASI_DDATA : asi_type := "01111"; -- 0x0F
constant ASI_IFLUSH : asi_type := "10000"; -- 0x10
constant ASI_DFLUSH : asi_type := "10001"; -- 0x11
constant ASI_FLUSH_PAGE : std_logic_vector(4 downto 0) := "10000"; -- 0x10 i/dcache flush page
constant ASI_FLUSH_CTX : std_logic_vector(4 downto 0) := "10011"; -- 0x13 i/dcache flush ctx
constant ASI_DCTX : std_logic_vector(4 downto 0) := "10100"; -- 0x14 dcache ctx
constant ASI_ICTX : std_logic_vector(4 downto 0) := "10101"; -- 0x15 icache ctx
-- ASIs traditionally used by LEON for SRMMU
constant ASI_MMUFLUSHPROBE : std_logic_vector(4 downto 0) := "11000"; -- 0x18 i/dtlb flush/(probe)
constant ASI_MMUREGS : std_logic_vector(4 downto 0) := "11001"; -- 0x19 mmu regs access
constant ASI_MMU_BP : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
constant ASI_MMU_DIAG : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
constant ASI_MMUSNOOP_DTAG : std_logic_vector(4 downto 0) := "11110"; -- 0x1e mmusnoop physical dtag
--constant ASI_MMU_DSU : std_logic_vector(4 downto 0) := "11111"; -- 0x1f mmu diagnostic
-- ASIs recommended in V8 specification, appendix I
constant ASI_MMUFLUSHPROBE_V8 : std_logic_vector(4 downto 0) := "00011"; -- 0x03 i/dtlb flush/(probe)
constant ASI_MMUREGS_V8 : std_logic_vector(4 downto 0) := "00100"; -- 0x04 mmu regs access
--constant ASI_MMU_BP_V8 : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
--constant ASI_MMU_DIAG_V8 : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
-- ftt decoding
subtype ftt_type is std_logic_vector(2 downto 0);
constant FPIEEE_ERR : ftt_type := "001";
constant FPUNIMP_ERR : ftt_type := "011";
constant FPSEQ_ERR : ftt_type := "100";
constant FPHW_ERR : ftt_type := "101";
end;
|
gpl-2.0
|
75f8eda37f6bc5feee314e86f46babed
| 0.628325 | 3.288765 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3sl150/config.vhd
| 1 | 6,714 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix3;
constant CFG_MEMTECH : integer := stratix3;
constant CFG_PADTECH : integer := stratix3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix3;
constant CFG_CLKMUL : integer := (30);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0058#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000012#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
67e4dcf9a2230dbf748eeac90c38f27c
| 0.64641 | 3.546751 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ambatest/ahbtbm.vhd
| 1 | 14,280 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbm
-- File: ahbtbm.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench master
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.ahbtbp.all;
entity ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end;
architecture rtl of ahbtbm is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
-- new /*
grant : std_logic;
grant2 : std_logic;
retry : std_logic_vector(1 downto 0);
read : std_logic; -- indicate
dbgl : integer;
use128 : integer;
hsize : std_logic_vector(2 downto 0);
ac : ahbtbm_access_array_type;
retryac : ahbtbm_access_type;
curac : ahbtbm_access_type;
haddr : std_logic_vector(31 downto 0); -- addr current access
hdata : std_logic_vector(31 downto 0); -- data currnet access
hdata128 : std_logic_vector(127 downto 0); -- data currnet access
hwrite : std_logic; -- write current access
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
dvalid : std_logic;
oldhtrans : std_logic_vector(1 downto 0);
-- new */
start : std_ulogic;
active : std_ulogic;
end record;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal r, rin : reg_type;
begin
ctrlo.rst <= rst;
ctrlo.clk <= clk;
comb : process(ahbmi, ctrli, rst, r)
-- new /*
variable v : reg_type;
variable update : std_logic;
variable hbusreq : std_ulogic; -- bus request
variable kblimit : std_logic; -- 1 kB limit indicator
-- new */
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- new /*
v := r; update := '0'; hbusreq := '0';--v.retry := '0';
v.dvalid := '0'; xhirq := (others => '0');
hprot := "1110";
--v.hrdata := ahbmi.hrdata;
--v.hrdata128 := ahbmi.hrdata128;
v.hrdata := ahbmi.hrdata(31 downto 0);
v.hrdata128 := ahbread4word(ahbmi.hrdata);
-- pragma translate_off
if ahbmi.hready = '1' and ahbmi.hresp = HRESP_ERROR then
v.hrdata := (others => 'X');
v.hrdata128 := (others => 'X');
end if;
-- pragma translate_on
v.status.err := '0';
--v.oldhtrans := r.ac(1).htrans;
kblimit := '0';
-- Sample grant when hready
if ahbmi.hready = '1' then
v.grant := ahbmi.hgrant(hindex);
v.grant2 := r.grant;
v.oldhtrans := r.ac(1).htrans;
end if;
-- 1k limit
if (r.ac(0).htrans = HTRANS_SEQ
and (r.ac(0).haddr(10) xor r.ac(1).haddr(10)) = '1')
or (r.retryac.htrans = HTRANS_SEQ
and (r.retryac.haddr(10) xor r.ac(1).haddr(10)) = '1' and r.retry = "10") then
kblimit := '1';
end if;
-- Read in new access
--if ((ahbmi.hready = '1' and ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = '0' then
--if ahbmi.hready = '1' and ((ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
if ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif ahbmi.hready = '1' and ( r.grant = '1'
or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
-- elsif ahbmi.hready = '1' and (( r.grant = '1' and
-- (ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR))
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
v.ac(1) := r.ac(0); v.ac(0) := ctrli.ac;
v.curac := r.ac(1);
v.hdata := r.ac(1).hdata; v.haddr := r.ac(1).haddr;
v.hwrite := r.ac(1).hwrite; v.dbgl := r.ac(1).ctrl.dbgl;
v.use128 := r.ac(1).ctrl.use128;
if v.use128 = 0 then
v.hdata128 := r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata;
else
v.hdata128 := r.ac(1).hdata128;
end if;
v.hsize := r.ac(1).hsize;
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
update := '1';
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
elsif ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif r.retry = "01" then
v.ac(1).htrans := HTRANS_NONSEQ;
v.ac(1).hburst := r.curac.hburst;
v.read := '0';
v.retry := "10";
elsif ahbmi.hready = '1' and r.grant = '1' and r.retry = "10" then
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
--if ahbmi.hresp = HRESP_OKAY then
--if ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
v.retry := "00";
--end if;
end if;
-- NONSEQ in retry
--if r.retry = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
-- NONSEQ if burst is interrupted
if r.grant = '0' and r.ac(1).htrans = HTRANS_SEQ then
v.ac(1).htrans := HTRANS_NONSEQ;
end if;
--if r.ac(1).htrans /= HTRANS_IDLE or r.ac(0).htrans /= HTRANS_IDLE then
-- hbusreq := '1';
--end if;
if r.ac(1).htrans = HTRANS_NONSEQ
or (r.ac(1).htrans = HTRANS_SEQ
and r.ac(0).htrans /= HTRANS_NONSEQ and kblimit = '0') then
hbusreq := '1';
end if;
--if r.grant = '0' then -- fix dvalid if grant deasserted *** ???
if r.grant = '0' and ahbmi.hready = '1' then
v.read := '0';
end if;
-- Check read data
if r.read = '1' and ahbmi.hresp = HRESP_OKAY and ahbmi.hready = '1' then
v.dvalid := '1';
if r.use128 = 0 then
--if r.hdata /= ahbmi.hrdata then
if r.hdata /= ahbmi.hrdata(31 downto 0) then
v.status.err := '1';
end if;
else
if r.hsize = "100" then
--if r.hdata128 /= ahbmi.hrdata128 then
if r.hdata128 /= ahbread4word(ahbmi.hrdata) then
v.status.err := '1';
end if;
else
--if r.hdata128(63 downto 0) /= ahbmi.hrdata128(63 downto 0) then
--if r.hdata128(63 downto 0) /= ahbmi.hrdata(63 downto 0) then
if r.hdata128(63 downto 0) /= ahbreaddword(ahbmi.hrdata) then
v.status.err := '1';
end if;
end if;
end if;
elsif r.read = '1' and ahbmi.hresp = HRESP_ERROR and ahbmi.hready = '1' then
v.status.err := '1';
end if;
-- new */
if rst = '0' then
v.ac(0).htrans := (others => '0');
v.ac(1).htrans := (others => '0');
v.retry := (others => '0');
v.read := '0';
v.ac(1).haddr := (others => '0');
v.ac(1).htrans := (others => '0');
v.ac(1).hwrite := '0';
v.ac(1).hsize := (others => '0');
v.ac(1).hburst := (others =>'0');
end if;
rin <= v;
ctrlo.update <= update;
ctrlo.status <= r.status;
ctrlo.hrdata <= r.hrdata;
ctrlo.hrdata128 <= r.hrdata128;
ctrlo.dvalid <= r.dvalid;
ahbmo.haddr <= r.ac(1).haddr;
ahbmo.htrans <= r.ac(1).htrans;
ahbmo.hbusreq <= hbusreq;
--ahbmo.hwdata <= r.hdata;
--ahbmo.hwdata128 <= r.hdata128;
ahbmo.hwdata <= ahbdrivedata(r.hdata128);
ahbmo.hconfig <= hconfig;
ahbmo.hlock <= '0';
ahbmo.hwrite <= r.ac(1).hwrite;
ahbmo.hsize <= r.ac(1).hsize;
ahbmo.hburst <= r.ac(1).hburst;
ahbmo.hprot <= r.ac(1).hprot;
ahbmo.hirq <= xhirq;
ahbmo.hindex <= hindex;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
-- pragma translate_off
if r.read = '1' and ahbmi.hready = '1' then --and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if rin.status.err = '0' then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0)));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))); end if;
end if;
end if;
else
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0))
& " != " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata)
& " != " & tost(r.hdata128));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))
& " != " & tost(r.hdata128(63 downto 0)));
end if;
end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [RETRY]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
print(ptime & "Read[" & tost(r.haddr) & "]: [ERROR]");
end if;
end if;
end if;
if r.hwrite = '1' and ahbmi.hready = '1' and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128));
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0))); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [RETRY]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [RETRY]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [RETRY]"); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [ERROR]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [ERROR]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [ERROR]"); end if;
end if;
end if;
end if;
end if;
-- pragma translate_on
end if;
end process;
end;
|
gpl-2.0
|
cdbca655c2aaa47414688287d3696d09
| 0.534244 | 3.301734 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/core/eth_ahb_mst.vhd
| 1 | 6,194 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_ahb_mst
-- File: eth_ahb_mst.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Ethernet MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of eth_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
bo : std_ulogic; --bus owner, 0=rx, 1=tx
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
error : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, rmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable nbo : std_ulogic;
variable tretry : std_ulogic;
variable rretry : std_ulogic;
variable rready : std_ulogic;
variable tready : std_ulogic;
variable rerror : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable rgrant : std_ulogic;
begin
v := r; htrans := HTRANS_IDLE; rready := '0'; tready := '0'; tretry := '0';
rretry := '0'; rerror := '0'; terror := '0'; tgrant := '0'; rgrant := '0';
if r.bo = '0' then hwdata := rmsti.data;
else hwdata := tmsti.data; end if;
hbusreq := tmsti.req or rmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
if r.retry = '0' then
nbo := tmsti.req and not (rmsti.req and not r.bo);
else
nbo := r.bo;
end if;
if nbo = '0' then
haddr := rmsti.addr; hwrite := rmsti.write;
if (rmsti.req and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (rmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then rgrant := '1'; end if;
else
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then tgrant := '1'; end if;
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.bo = '0' then
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => rready := '1';
when HRESP_SPLIT | HRESP_RETRY => rretry := '1';
when HRESP_ERROR => rerror := '1';
when others => null;
end case;
end if;
end if;
else
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if (r.ba = '1') and
(ahbmi.hresp = HRESP_ERROR)
then v.error := not ahbmi.hready; else v.error := '0'; end if;
if (r.retry or r.error) = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bo := nbo; v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bo := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
rmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
rmsto.error <= rerror;
rmsto.retry <= rretry;
rmsto.ready <= rready;
tmsto.grant <= tgrant;
rmsto.grant <= rgrant;
ahbmo.htrans <= htrans;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hsize <= HSIZE_WORD;
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
|
gpl-2.0
|
1df50f44908fc90448bf1ef4b7fa9799
| 0.558767 | 3.511338 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/altera_mf/clkgen_altera_mf.vhd
| 1 | 7,148 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity altera_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of altera_pll is
component altpll
generic (
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
extclk0_multiply_by : positive := 1;
extclk0_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
extclkena : in std_logic_vector(3 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal extclk : std_logic_vector (3 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 2) <= (others => '0');
noclk2xgen: if (clk2xen = 0) generate clkena(1 downto 0) <= "01"; end generate;
clk2xgen: if (clk2xen /= 0) generate clkena(1 downto 0) <= "11"; end generate;
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1); e0 <= extclk(0);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_altera_mf is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_altera_mf is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : altera_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_altera" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_altera" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
gpl-2.0
|
84d332f481f065c4be4ec13adec9e7b2
| 0.592473 | 3.476654 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddr2spax_ddr.vhd
| 1 | 52,372 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spax
-- File: ddr2spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR2 memory controller with asynch AHB interface
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
-- dqsgating : integer := 0;
nosync : integer := 0;
dqsgating : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr2spax_ddr;
architecture rtl of ddr2spax_ddr is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
function tosl(x: integer) return std_logic is
begin
if x /= 0 then return '1'; else return '0'; end if;
end tosl;
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(3 downto 0);
trcd : std_logic_vector(2 downto 0); -- tRCD : 2-9 clock cycles
trfc : std_logic_vector(7 downto 0);
trp : std_logic_vector(2 downto 0); -- precharge to activate: 2-9 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
cal_pll : std_logic_vector(1 downto 0); -- *** ??? pll_reconf
cal_rst : std_logic;
readdly : std_logic_vector(3 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
dqsctrl : std_logic_vector(7 downto 0);
eightbanks : std_ulogic;
caslat : std_logic_vector(1 downto 0); -- CAS latency 3-6
odten : std_logic_vector(1 downto 0);
tras : std_logic_vector(4 downto 0); -- RAS-to-Precharge minimum
trtp : std_ulogic;
regmem : std_ulogic; -- Registered memory (1 cycle extra latency)
strength : std_ulogic; -- Drive strength 1=reduced, 0=normal
end record;
constant ddr_burstlen: integer := (burstlen*32)/(2*ddrbits);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
type ddrstate is (dsidle,dsrascas,dscaslat,dsreaddly,dsdata,dsdone,dsagain,dsreg,dsrefresh,dspreall);
type ddrcmdstate is (dcrstdel,dcoff,dcinit1,dcinit2,dcinit3,dcinit4,dcinit5,dcinit6,dcinit7,dcinit8,dcon);
type ddr_reg_type is record
s : ddrstate;
cmds : ddrcmdstate;
response : ddr_response_type;
response1 : ddr_response_type;
response2 : ddr_response_type;
response_prev : ddr_response_type;
cfg : sdram_cfg_type;
rowsel : std_logic_vector(2 downto 0);
endaddr : std_logic_vector(l2blen-4 downto 2);
addrlo : std_logic_vector(l2ddrw-4 downto 0);
col : std_logic_vector(13 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(2 downto 0);
ctr : std_logic_vector(7 downto 0);
casctr : std_logic_vector(l2ddr_burstlen-1 downto 0);
datacas : std_logic;
prectr : std_logic_vector(5 downto 0);
rastimer : std_logic_vector(4 downto 0);
tras_met : std_logic;
pchpend : std_logic;
refctr : std_logic_vector(16 downto 0);
refpend : std_logic;
pastlast : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_wen : std_ulogic;
wen_prev : std_ulogic;
sdo_rasn : std_ulogic;
rasn_pre : std_ulogic;
sdo_casn : std_ulogic;
sdo_dqm : std_logic_vector(15 downto 0);
dqm_prev : std_logic_vector(15 downto 0);
twr_plus_cl : std_logic_vector(5 downto 0);
request_row : std_logic_vector(14 downto 0);
request_bank : std_logic_vector(2 downto 0);
request_cs : std_logic_vector(0 downto 0);
row : std_logic_vector(14 downto 0);
setrow : std_logic;
samerow : std_logic;
start_tog_prev: std_logic;
sdo_bdrive : std_ulogic;
sdo_qdrive : std_ulogic;
sdo_nbdrive : std_ulogic;
sdo_address : std_logic_vector(14 downto 0);
sdo_address_prev: std_logic_vector(14 downto 0);
sdo_ba : std_logic_vector(2 downto 0);
sdo_data : std_logic_vector(sdo.data'length-1 downto 0);
sdo_cb : std_logic_vector(sdo.cb'length-1 downto 0);
sdo_odt : std_logic;
sdo_oct : std_logic;
rbwrite : std_logic;
rbwdata : std_logic_vector(rbuf_wdbits-1 downto 0);
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
ramaddr_prev : std_logic_vector(rbuf_wabits-1 downto 0);
mr_twr : std_logic_vector(2 downto 0);
mr_tcl : std_logic_vector(2 downto 0);
read_pend : std_logic_vector(15 downto 0);
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
hwidth1 : std_logic;
hwidth : std_logic;
hwcas : std_logic;
hwctr : std_logic;
end record;
signal dr,ndr : ddr_reg_type;
signal muxsel2,muxsel1,muxsel0: std_ulogic;
signal muxin4: std_logic_vector(31 downto 0);
signal muxout4: std_logic_vector(3 downto 0);
signal start_tog_delta1,start_tog_delta2: std_logic;
signal arst: std_ulogic;
attribute syn_keep: boolean;
attribute syn_keep of muxsel2:signal is true;
attribute syn_keep of muxsel1:signal is true;
attribute syn_keep of muxsel0:signal is true;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
start_tog_delta1 <= start_tog;
start_tog_delta2 <= start_tog_delta1;
muxsel2 <= dr.rowsel(2);
muxsel1 <= dr.rowsel(1);
muxsel0 <= dr.rowsel(0);
muxproc : process(muxin4,muxsel2,muxsel1,muxsel0)
begin
muxout4(3) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(31 downto 24));
muxout4(2) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(23 downto 16));
muxout4(1) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(15 downto 8));
muxout4(0) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(7 downto 0));
end process;
ddrcomb : process(ddr_rst,sdi,request,frequest,start_tog_delta2,dr,wbrdata,muxout4,hwidth,reqsel,testen,testoen)
constant plmemwrite: boolean := false;
constant plmemread: boolean := false;
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable bdrive,qdrive: std_logic;
variable vreq,vreqf: ddr_request_type;
variable resp,resp2: ddr_response_type;
variable vstart: std_logic;
variable acsn: std_logic_vector(1 downto 0);
variable arow: std_logic_vector(14 downto 0);
variable acol: std_logic_vector(13 downto 0);
variable abank: std_logic_vector(2 downto 0);
variable aendaddr: std_logic_vector(l2blen-4 downto 2);
variable aloa: std_logic_vector(l2ddrw-4 downto 0);
variable rbw: std_logic;
variable rbwd: std_logic_vector(rbuf_wdbits-1 downto 0);
variable rbwa: std_logic_vector(rbuf_wabits-1 downto 0);
variable wbra: std_logic_vector(wbuf_rabits-1 downto 0);
variable regdata: std_logic_vector(31 downto 0);
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
variable regsd4 : std_logic_vector(31 downto 0); -- data from registers
variable regsd5 : std_logic_vector(31 downto 0); -- data from registers
variable mr : std_logic_vector(14 downto 0); -- DDR2 Mode register
variable mask: std_logic_vector(15 downto 0);
variable hio1: std_logic;
variable w5: std_logic;
variable precharge_next: std_logic;
variable precharge_notras: std_logic;
variable goto_caslat: std_logic;
variable block_precharge: std_logic;
variable regt0,regt1: std_logic_vector(ddrbits-1 downto 0);
variable addrtemp3,addrtemp2,addrtemp1,addrtemp0: std_logic_vector(7 downto 0);
variable expcsize: std_logic_vector(2 downto 0);
variable caslat_reg: std_logic_vector(2 downto 0);
variable addrlo32, endaddr32: std_logic_vector(3 downto 2);
variable endaddr43: std_logic_vector(4 downto 3);
variable endaddr42: std_logic_vector(4 downto 2);
variable inc_rctr: std_logic;
begin
dv := dr;
o := ddrctrl_out_none;
o.sdcke := (others => dr.cfg.cke);
o.sdcsn := dr.sdo_csn;
o.sdwen := dr.wen_prev;
o.rasn := dr.sdo_rasn and dr.rasn_pre;
o.casn := dr.sdo_casn and dr.datacas;
o.dqm := dr.dqm_prev;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
o.nbdrive := dr.sdo_nbdrive;
o.address := dr.sdo_address;
o.data := dr.sdo_data;
o.ba := dr.sdo_ba;
o.cal_en := dr.cfg.cal_en;
o.cal_inc := dr.cfg.cal_inc;
o.cal_pll := dr.cfg.cal_pll;
o.cal_rst := dr.cfg.cal_rst;
o.odt := (others => dr.sdo_odt);
o.oct := dr.sdo_oct;
o.cb := dr.sdo_cb;
o.cbcal_en := dr.cfg.cbcal_en;
o.cbcal_inc := dr.cfg.cbcal_inc;
resp := ddr_response_none;
resp2 := ddr_response_none;
rbw := dr.rbwrite;
rbwd := dr.rbwdata;
rbwa := (others => '0');
w5 := '0';
wbra := dr.response.done_tog & dr.ramaddr;
dv.ramaddr_prev := dr.ramaddr;
dv.dqm_prev := dr.sdo_dqm;
dv.wen_prev := dr.sdo_wen;
dv.response_prev := dr.response;
dv.sdo_address_prev := dr.sdo_address;
dv.cfg.cal_en := (others => '0');
dv.cfg.cal_inc := (others => '0');
dv.cfg.cal_pll := (others => '0');
dv.cfg.cal_rst := '0';
dv.cfg.cbcal_en := (others => '0');
dv.cfg.cbcal_inc := (others => '0');
dv.sdo_data := (others => '0');
dv.sdo_data(2*ddrbits-1 downto ddrbits) := wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_cb := (others => '0');
if chkbits > 0 then
dv.sdo_cb(2*chkbits-1 downto chkbits) := wbrdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+chkbits);
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
end if;
if hwidthen/=0 and dr.hwidth='1' and dr.hwctr='1' then
dv.sdo_data(ddrbits-1 downto 0) := dr.sdo_data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto chkbits);
end if;
end if;
if not (hwidthen/=0 and hasdqvalid/=0 and sdi.datavalid='0') then
dv.rbwdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := sdi.data(2*ddrbits-1 downto ddrbits);
dv.rbwdata(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
if chkbits > 0 then
dv.rbwdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+chkbits) := sdi.cb(2*chkbits-1 downto chkbits);
dv.rbwdata(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
end if;
-- Half-width input data muxing
if hwidthen/=0 and dr.hwidth='1' and dr.hwctr='1' then
dv.rbwdata(2*ddrbits+chkbits-1 downto 2*ddrbits+chkbits-ddrbits/2) :=
dr.rbwdata(2*ddrbits+chkbits-ddrbits/2-1 downto ddrbits+chkbits);
dv.rbwdata(2*ddrbits+chkbits-ddrbits/2-1 downto ddrbits+chkbits) :=
dr.rbwdata(ddrbits/2-1 downto 0);
dv.rbwdata(ddrbits-1 downto ddrbits/2) :=
sdi.data(ddrbits+ddrbits/2-1 downto ddrbits);
if chkbits > 0 then
dv.rbwdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+2*chkbits-chkbits/2) :=
dr.rbwdata(2*ddrbits+2*chkbits-chkbits/2-1 downto 2*ddrbits+chkbits);
dv.rbwdata(2*ddrbits+2*chkbits-chkbits/2-1 downto 2*ddrbits+chkbits) :=
dr.rbwdata(ddrbits+chkbits/2-1 downto ddrbits);
dv.rbwdata(ddrbits+chkbits-1 downto ddrbits+chkbits/2) :=
sdi.cb(chkbits+chkbits/2-1 downto chkbits);
end if;
end if;
end if;
-- hwidth input should be constant but sample it for robustness
-- then sample in one more stage to allow replication if necessary
dv.hwidth1 := hwidth;
dv.hwidth := dr.hwidth1;
if hwidthen=0 then dv.hwidth:='0'; end if;
-- Synchronize 1/2 stages
dv.req1 := request; dv.req2 := dr.req1;
dv.start1 := start_tog_delta2; dv.start2 := dr.start1;
vstart := dr.start2;
vreq := dr.req2;
vreqf := dr.req1;
if nosync /= 0 then vstart:=start_tog_delta2; vreq:=request; vreqf:=request; end if;
if nosync > 1 then vreqf:=frequest; end if;
dv.start_tog_prev := vstart;
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.ocd & dr.cfg.emr & dr.cfg.bsize(3) & dr.cfg.trcd(0) &
dr.cfg.bsize(2 downto 0) & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(25 downto 18) := std_logic_vector(to_unsigned(phytech,8));
if bigmem /= 0 then regsd2(17):='1'; end if;
if chkbits > 0 then regsd2(16):='1'; end if;
regsd2(15 downto 0) := "1" &
std_logic_vector(to_unsigned(log2(ddrbits/8),3)) &
std_logic_vector(to_unsigned(MHz,12));
if dr.hwidth='1' then
regsd2(14 downto 12) := std_logic_vector(to_unsigned(log2((ddrbits/2)/8),3));
end if;
regsd3 := (others => '0');
regsd3(17 downto 16) := dr.cfg.readdly(1 downto 0);
regsd3(22 downto 18) := dr.cfg.trfc(4 downto 0);
regsd3(27 downto 23) := dr.cfg.twr;
regsd3(28) := dr.cfg.trp(0);
regsd4 := (others => '0');
regsd4(23 downto 22) := dr.cfg.readdly(3 downto 2);
regsd4(21) := dr.cfg.regmem;
regsd4(13 downto 0) := dr.cfg.trtp & "00" & dr.cfg.caslat &
dr.cfg.eightbanks & dr.cfg.dqsctrl;
regsd5 := (others => '0');
regsd5(30 downto 28) := dr.cfg.trp;
regsd5(25 downto 18) := dr.cfg.trfc;
regsd5(17 downto 16) := dr.cfg.odten;
regsd5(15) := dr.cfg.strength;
regsd5(10 downto 8) := dr.cfg.trcd;
regsd5(4 downto 0) := dr.cfg.tras;
case ddrbits is
when 16 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(31 downto 0);
when 32 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(63 downto 32);
when 64 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(63 downto 32);
when others => o.regwdata := dr.sdo_data(2*ddrbits-7*32-1 downto 2*ddrbits-8*32) &
dr.sdo_data(2*ddrbits-6*32-1 downto 2*ddrbits-7*32);
end case;
if dr.cfg.regmem='1' then
caslat_reg := std_logic_vector(unsigned('0' & dr.cfg.caslat)+1);
else
caslat_reg := '0' & dr.cfg.caslat;
end if;
-- Mode register
dv.mr_twr := std_logic_vector(unsigned(dr.cfg.twr(2 downto 0))-3);
if dv.mr_twr="110" or dv.mr_twr="111" or dv.mr_twr="000" then
dv.mr_twr := "101";
end if;
dv.mr_tcl := std_logic_vector(unsigned('0' & dr.cfg.caslat)+3);
mr := (others => '0');
mr(12) := '0'; -- Power down exit time
mr(11 downto 9) := dr.mr_twr; -- WR-1
mr(8) := dr.cfg.dllrst; -- DLL Reset
mr(7) := '0'; -- Test mode
mr(6 downto 4) := dr.mr_tcl; -- CL
mr(3) := '0'; -- Burst type, 0=seq 1=interl
mr(2 downto 0) := "010"; -- Burst len 010=4, 011=8
-- Calculate address parts from a2ds.haddr and a2ds.startword
expcsize := dr.hwidth & dr.cfg.csize;
case expcsize is
when "011" => arow := vreqf.startaddr(l2ddrw+22 downto l2ddrw+8);
when "111" | "010" => arow := vreqf.startaddr(l2ddrw+21 downto l2ddrw+7);
when "110" | "001" => arow := vreqf.startaddr(l2ddrw+20 downto l2ddrw+6);
when "101" | "000" => arow := vreqf.startaddr(l2ddrw+19 downto l2ddrw+5);
when others => arow := vreqf.startaddr(l2ddrw+18 downto l2ddrw+4);
end case;
dv.rowsel := dr.cfg.bsize(2 downto 0);
if bigmem /= 0 and dr.cfg.bsize(3 downto 1)="000" then
dv.rowsel := "010";
end if;
if bigmem = 0 and dr.cfg.bsize(3)='1' then
dv.rowsel := "111";
end if;
addrtemp3 := vreqf.startaddr(30 downto 23); --CS
addrtemp2 := vreqf.startaddr(29 downto 22); --BA2/1
addrtemp1 := vreqf.startaddr(28 downto 21); --BA1/0
addrtemp0 := vreqf.startaddr(27 downto 20); --BA0/-
if bigmem=1 then
addrtemp3(1 downto 0) := "0" & vreqf.startaddr(31);
addrtemp2(1 downto 0) := vreqf.startaddr(31 downto 30);
addrtemp1(1 downto 0) := vreqf.startaddr(30 downto 29);
addrtemp0(1 downto 0) := vreqf.startaddr(29 downto 28);
end if;
muxin4 <= addrtemp3 & addrtemp2 & addrtemp1 & addrtemp0;
abank := muxout4(2 downto 0);
if dr.cfg.eightbanks='0' then
abank := '0' & abank(2) & abank(1);
end if;
acol := vreqf.startaddr(log2(ddrbits/8)+13 downto log2(ddrbits/8));
if ddrbits=16 then acol(0):='0'; end if; -- Always align to at least 32 bits
acsn(0) := muxout4(3);
acsn(1) := not acsn(0);
dv.setrow := '0';
if dr.setrow='1' then
dv.row := dr.sdo_address_prev;
end if;
dv.samerow := '0';
if abank=dr.sdo_ba and acsn=dr.sdo_csn and arow=dr.row then
dv.samerow := '1';
end if;
dv.request_row := arow;
dv.request_cs := acsn(0 downto 0);
dv.request_bank := abank;
hio1 := vreqf.hio;
if raspipe /= 0 then
vstart := dr.start_tog_prev;
arow := dr.request_row;
acsn := (not dr.request_cs) & dr.request_cs;
abank := dr.request_bank;
hio1 := vreq.hio;
end if;
aendaddr := vreq.endaddr(log2(4*burstlen)-1 downto 2);
if vreq.hsize(1 downto 0)="11" and vreq.hio='0' then
aendaddr(2):='1';
end if;
if ahbdw > 64 and vreqf.hsize(2)='1' then
aendaddr(3 downto 2) := "11";
if ahbdw > 128 and vreqf.hsize(0)='1' then
aendaddr(4) := '1';
end if;
end if;
aloa(l2ddrw-4 downto 0) := vreq.startaddr(l2ddrw-4 downto 0);
if ddrbits > 32 then addrlo32 := dr.addrlo(3 downto 2);
elsif ddrbits > 16 then addrlo32 := '0' & dr.addrlo(2);
else addrlo32 := "00";
end if;
endaddr32 := dr.endaddr(3 downto 2);
endaddr43 := dr.endaddr(4 downto 3);
endaddr42 := dr.endaddr(4 downto 2);
-- Calculate data mask
mask := (others => dr.pastlast);
-- Set mask bits for <word access
if dr.hsize="000" then
if dr.addrlo(0)='1' then
mask := mask or "1010101010101010";
else
mask := mask or "0101010101010101";
end if;
end if;
if dr.hsize(2 downto 1)="00" then
if dr.addrlo(1)='1' then
mask := mask or "1100110011001100";
else
mask := mask or "0011001100110011";
end if;
end if;
-- First access
-- (this could be written in generic code instead)
if dr.ctr=zerov(dr.ctr'length) then
case ddrbits is
when 16 =>
null;
when 32 =>
if dr.addrlo(2)='1' then
mask(7 downto 0) := mask(7 downto 0) or x"F0";
end if;
when 64 =>
case addrlo32 is
when "00" => null;
when "01" => mask := mask or x"F000";
when "10" => mask := mask or x"FF00";
when others => mask := mask or x"FFF0";
end case;
when others => null;
end case;
end if;
-- Last access
if dr.ramaddr = dr.endaddr(log2(4*burstlen)-1 downto log2(2*ddrbits/8)) then
if hwidthen=0 or dr.hwidth='0' or dr.hwctr='1' then
dv.pastlast := '1';
end if;
case ddrbits is
when 16 => null;
when 32 =>
if dr.endaddr(2)='0' then
mask(7 downto 0) := mask(7 downto 0) or x"0F";
end if;
when 64 =>
case endaddr32 is
when "00" => mask := mask or x"0FFF";
when "01" => mask := mask or x"00FF";
when "10" => mask := mask or x"000F";
when others => null;
end case;
when others => null;
end case;
end if;
-- Before first
if dr.col(1)='1' and dr.ctr(0)='1' and dr.ctr(dr.ctr'high downto 1)=zerov(dr.ctr'length-1) then
mask := mask or x"FFFF";
end if;
dv.sdo_rasn := '1'; dv.sdo_casn := '1'; dv.sdo_wen := '1';
dv.sdo_odt := '0'; dv.sdo_oct := '0';
dv.rbwrite := '0';
dv.ctr := std_logic_vector(unsigned(dr.ctr)+1);
if hwidthen/=0 and dr.hwidth='1' and dr.s=dsdata then
dv.hwctr := not dr.hwctr;
if dr.hwctr='0' then dv.ctr := dr.ctr; end if;
end if;
dv.rastimer := std_logic_vector(unsigned(dr.rastimer)+1);
if dr.rastimer=dr.cfg.tras then dv.tras_met := '1'; end if;
-- Calculate whether we would precharge the next cycle if Tras=0
precharge_notras := '0';
if dr.casctr=zerov(dr.casctr'length) and dr.prectr="000000" and dr.pchpend='1' then
precharge_notras := '1';
end if;
-- Calculate whether we should precharge the next cycle
precharge_next := precharge_notras and dr.tras_met;
block_precharge := '0';
inc_rctr := '0';
goto_caslat := '0';
case dr.s is
when dsidle =>
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_bdrive := not oepols;
dv.sdo_qdrive := not oepols;
dv.sdo_nbdrive := not oepols;
dv.col := acol;
dv.sdo_csn := (others => '1');
dv.rastimer := (others => '0');
dv.tras_met := '0';
dv.response.rctr_gray := "0000";
if dr.refpend='1' and dr.cfg.refon='1' then
-- Periodic refresh
dv.sdo_csn := (others => '0');
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.refpend := '0';
dv.s := dsrefresh;
elsif vstart /= dr.response.done_tog and (dr.cmds=dcon or (dr.cmds=dcoff and dr.cfg.renable='0')) then
-- R/W data
dv.sdo_rasn := '0' or hio1;
dv.sdo_csn := acsn;
dv.sdo_address := arow;
dv.sdo_ba := abank;
dv.s := dsrascas;
elsif dr.cfg.command /= "000" then
-- Command
dv.sdo_csn := (others => '0');
if dr.cfg.command(2 downto 1)="11" then
dv.sdo_wen:='0'; dv.sdo_casn:='0'; dv.sdo_rasn:='0';
dv.sdo_ba := "00" & dr.cfg.command(0);
if dr.cfg.command(0)='0' or dr.cfg.emr="00" then
dv.sdo_ba := "000";
dv.sdo_address := mr;
else
dv.sdo_ba := "0" & dr.cfg.emr;
if dr.cfg.emr="01" then
dv.sdo_address := "0000"&conv_std_logic(dqsse=1)&dr.cfg.ocd&dr.cfg.ocd&dr.cfg.ocd
& dr.cfg.odten(1)&"000"& dr.cfg.odten(0) & dr.cfg.strength & "0";
else
dv.sdo_address := (others => '0');
end if;
end if;
else
dv.sdo_wen := dr.cfg.command(2);
dv.sdo_casn := dr.cfg.command(1);
dv.sdo_rasn := dr.cfg.command(0);
dv.sdo_address(10) := '1';
-- print("X Command: " & tost(dr.cfg.command) & " -> casn:" & tost(dv.sdo_casn) & ",rasn:" & tost(dv.sdo_rasn) & ",wen:" & tost(dv.sdo_wen));
end if;
dv.cfg.command := "000";
if dr.cfg.command=CMD_REF then
dv.s := dsrefresh;
end if;
if dr.cfg.command=CMD_PRE then
dv.s := dspreall;
end if;
end if;
when dsrascas =>
if dr.ctr(2 downto 0)="000" then
-- pragma translate_off
assert dr.ctr="00000000" severity failure;
-- pragma translate_on
-- dv.row := dr.sdo_address;
dv.setrow := '1';
end if;
dv.hwrite := vreq.hwrite;
dv.hsize := vreq.hsize;
dv.endaddr := aendaddr;
dv.addrlo := aloa;
dv.sdo_address := dr.col(13 downto 10) & '0' & dr.col(9 downto 1) & '0';
if dr.hwidth='1' then
dv.sdo_address := dr.col(12 downto 9) & '0' & dr.col(8 downto 1) & "00";
end if;
if vreq.hio='1' and dr.ctr(0)='1' then
dv.s := dsreg;
dv.ctr := (others => '0');
dv.hwctr := '0';
elsif vreq.hio='0' and dr.ctr(2 downto 0)=dr.cfg.trcd then
goto_caslat := '1';
end if;
when dscaslat =>
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.pastlast := '0';
if dr.ctr(2 downto 0)=caslat_reg then
if dr.hwrite='1' then
dv.s := dsdata;
else
dv.s := dsreaddly;
end if;
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_qdrive := not (dr.hwrite xor oepols);
dv.sdo_nbdrive := not (dr.hwrite xor oepols);
end if;
when dsreaddly =>
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.pastlast := '0';
if dr.ctr(3 downto 0)=dr.cfg.readdly then
dv.s := dsdata;
dv.ctr := (others => '0');
dv.hwctr := '0';
end if;
when dsdata =>
inc_rctr := '0';
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.rbwrite := '1';
dv.sdo_dqm := mask;
dv.sdo_bdrive := not (dr.hwrite xor oepols);
dv.sdo_qdrive := not (dr.hwrite xor oepols);
dv.sdo_nbdrive := not (dr.hwrite xor oepols);
-- If-case to handle pausing for half-width mode
if hwidthen=0 or dr.hwidth='0' or dr.hwctr='1' then
inc_rctr := '1';
-- The first request may be on a 2-odd column to get the first data first
-- Make sure following requests are on even mult of 4xcolumns
if dr.ctr(0)='1' then
dv.col(1) := '0';
end if;
-- Make sure we don't advance read counter for the unwanted 3:rd/4:th
-- word in the burst in this case
if dr.ctr(0)='1' and dr.col(1)='1' then
inc_rctr := '0';
end if;
-- Toggle done and change state after completed burst
if dr.ctr(log2(ddr_burstlen)-1 downto 0)=(not zerov(l2ddr_burstlen)) then
dv.sdo_nbdrive := not oepols;
dv.s := dsdone;
dv.response.done_tog := not dr.response.done_tog;
end if;
end if;
-- Stall if not ready yet
if hasdqvalid/=0 and sdi.datavalid='0' and dr.hwrite='0' then
dv.ctr := dr.ctr;
dv.hwctr := dr.hwctr;
dv.response := dr.response;
dv.s := dsdata;
dv.col(1) := dr.col(1);
dv.rbwrite := '0';
inc_rctr := '0';
end if;
if inc_rctr='1' and dr.hwrite='0' then
dv.response.rctr_gray(l2ddr_burstlen-1 downto 0) :=
nextgray(dr.response.rctr_gray(l2ddr_burstlen-1 downto 0));
end if;
when dsdone =>
dv.response.rctr_gray := "0000";
dv.sdo_bdrive := not oepols;
if dr.ctr(0)='1' then
dv.sdo_qdrive := not oepols;
end if;
if dr.pchpend='0' and dr.prectr=zerov(dr.prectr'length) then
dv.s := dsidle;
end if;
-- Short circuit if request on same row and waiting for Tras to expire
if precharge_notras='1' and precharge_next='0' and
dr.start_tog_prev /= dr.response.done_tog and dr.samerow='1' and vreq.hio='0' then
dv.col := acol;
dv.endaddr := aendaddr;
dv.addrlo := aloa;
dv.hwrite := vreq.hwrite;
dv.hsize := vreq.hsize;
dv.s := dsagain;
dv.sdo_qdrive := not oepols;
end if;
when dsagain =>
block_precharge := '1';
dv.sdo_address := dr.col(13 downto 10) & '0' & dr.col(9 downto 1) & '0';
goto_caslat := '1';
when dsreg =>
-- This code assumes ddrbits>=16, needs to be changed slightly to support
-- smaller widths
dv.rbwrite := '1';
-- DDR2CFG1-5,PHYCFG read
regt0 := (others => '0'); regt1 := (others => '0');
case ddrbits is
when 16 =>
case endaddr42 is
when "000" => regt0 := regsd1(31 downto 16); regt1 := regsd1(15 downto 0);
when "001" => regt0 := regsd2(31 downto 16); regt1 := regsd2(15 downto 0);
when "010" => regt0 := regsd3(31 downto 16); regt1 := regsd3(15 downto 0);
when "011" => regt0 := regsd4(31 downto 16); regt1 := regsd4(15 downto 0);
when "100" | "101" => regt0 := regsd5(31 downto 16); regt1 := regsd5(15 downto 0);
when "110" => regt0 := sdi.regrdata(31 downto 16); regt1 := sdi.regrdata(15 downto 0);
when others => regt0 := sdi.regrdata(63 downto 48); regt1 := sdi.regrdata(47 downto 32);
end case;
when 32 =>
case endaddr43 is
when "00" => regt0 := regsd1; regt1 := regsd2;
when "01" => regt0 := regsd3; regt1 := regsd4;
when "10" => regt0 := regsd5; regt1 := regsd2;
when others => regt0 := sdi.regrdata(31 downto 0); regt1 := sdi.regrdata(63 downto 32);
end case;
when 64 =>
case dr.endaddr(4) is
when '0' => regt0 := regsd1 & regsd2; regt1 := regsd3 & regsd4;
when others => regt0 := regsd5 & regsd2; regt1 := sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
end case;
when 128 =>
regt0 := regsd1 & regsd2 & regsd3 & regsd4;
regt1 := regsd5 & regsd2 & sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
when others =>
regt0(ddrbits-1 downto ddrbits-255) := regsd1 & regsd2 & regsd3 & regsd4 &
regsd5 & x"00000000" & sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
end case;
dv.rbwdata(ddrbits*2+chkbits-1 downto ddrbits+chkbits) := regt0;
dv.rbwdata(ddrbits-1 downto 0) := regt1;
-- Note write data is two cycles behind
regt0 := dr.sdo_data(ddrbits*2-1 downto ddrbits);
regt1 := dr.sdo_data(ddrbits-1 downto 0);
if dr.hwrite='1' and dr.ctr(2 downto 0)="010" then
w5 := '0';
case ddrbits is
when 16 =>
case endaddr42 is
when "000" => regsd1 := regt0 & regt1;
when "001" => regsd2 := regt0 & regt1;
when "010" => regsd3 := regt0 & regt1;
when "011" => regsd4 := regt0 & regt1;
when "100" => regsd5 := regt0 & regt1;
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 32 =>
case endaddr42 is
when "000" => regsd1 := regt0;
when "001" => regsd2 := regt1;
when "010" => regsd3 := regt0;
when "011" => regsd4 := regt1;
when "100" => regsd5 := regt0;
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 64 =>
case endaddr42 is
when "000" => regsd1 := regt0(63 downto 32);
when "001" => regsd2 := regt0(31 downto 0);
when "010" => regsd3 := regt1(63 downto 32);
when "011" => regsd4 := regt1(31 downto 0);
when "100" => regsd5 := regt0(63 downto 32);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 128 =>
case endaddr42 is
when "000" => regsd1 := regt0(127 downto 96);
when "001" => regsd2 := regt0(95 downto 64);
when "010" => regsd3 := regt0(63 downto 32);
when "011" => regsd4 := regt0(31 downto 0);
when "100" => regsd5 := regt1(127 downto 96);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when others =>
case endaddr42 is
when "000" => regsd1 := regt0(ddrbits-1 downto ddrbits-32);
when "001" => regsd2 := regt0(ddrbits-33 downto ddrbits-64);
when "010" => regsd3 := regt0(ddrbits-65 downto ddrbits-96);
when "011" => regsd4 := regt0(ddrbits-97 downto ddrbits-128);
when "100" => regsd5 := regt0(ddrbits-129 downto ddrbits-160);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
end case;
-- Update lsb aliases for expanded fields in ddr2cfg5
if w5='1' then
regsd3(28) := regsd5(28); -- TRP
regsd3(22 downto 18) := regsd5(22 downto 18); -- TRFC
regsd1(26) := regsd5(8); -- TRCD
end if;
end if;
if (dr.hwrite='1' and dr.ctr(2 downto 1)="11") or dr.hwrite='0' then
dv.s := dsidle;
dv.response.done_tog := not dr.response.done_tog;
end if;
dv.cfg := (refon => regsd1(31), ocd => regsd1(30), emr => regsd1(29 downto 28),
trcd => regsd5(10 downto 9) & regsd1(26),
bsize => regsd1(27) & regsd1(25 downto 23), csize => regsd1(22 downto 21),
command => regsd1(20 downto 18), dllrst => regsd1(17), renable => regsd1(16),
cke => regsd1(15), refresh => regsd1(11 downto 0),
cal_pll => regsd3(30 downto 29), cal_rst => regsd3(31),
trp => regsd5(30 downto 29) & regsd3(28),
twr => regsd3(27 downto 23),
trfc => regsd5(25 downto 23) & regsd3(22 downto 18),
readdly => regsd4(23 downto 22) & regsd3(17 downto 16), cal_inc => regsd3(15 downto 8),
cal_en => regsd3(7 downto 0),
eightbanks => regsd4(8), dqsctrl => regsd4(7 downto 0),
caslat => regsd4(10 downto 9),
odten => regsd5(17 downto 16), tras => regsd5(4 downto 0), strength => regsd5(15),
trtp => regsd4(13), cbcal_inc => regsd4(31 downto 28), cbcal_en => regsd4(27 downto 24),
regmem => regsd4(21)
);
when dsrefresh =>
if dr.ctr(7 downto 0)=dr.cfg.trfc then
dv.s := dsidle;
end if;
when dspreall =>
-- Wait for tRP (eightbanks=0) or tRP+1 (eightbanks=1)
if dr.ctr(3 downto 0)=std_logic_vector(("0" & unsigned(dr.cfg.trp)) + (2+eightbanks)) then
dv.s := dsidle;
end if;
end case;
if goto_caslat='1' then
dv.s := dscaslat;
-- Set counter to -4 for read and -1 for write to compensate
-- write-read diff and pipelining.
-- Only need lowest three bits so set highest 3 to '0' as usual
dv.ctr(5 downto 3) := "000";
dv.ctr(2 downto 0) := "100";
if vreq.hwrite='1' then
dv.ctr(2 downto 0) := "111";
end if;
dv.casctr := std_logic_vector(to_unsigned(ddr_burstlen/2, dv.casctr'length));
dv.hwcas := '0';
dv.pchpend := '1';
end if;
-- CAS and precharge handling
-- FSM above sets up casctr and pchpend
dv.twr_plus_cl := std_logic_vector(("0" & unsigned(dr.cfg.twr)) + ("0000" & unsigned(dr.cfg.caslat)));
if dr.prectr /= zerov(dr.prectr'length) then
dv.prectr := std_logic_vector(unsigned(dr.prectr)-1);
end if;
dv.read_pend := '0' & dr.read_pend(dr.read_pend'high downto 1);
dv.datacas := '1';
if dr.casctr /= zerov(dr.casctr'length) then
if dr.datacas='1' then
dv.datacas := '0';
-- dv.sdo_casn := '0';
dv.sdo_wen := not dr.hwrite;
if dr.hwrite='0' then
case dr.cfg.caslat is
when "00" => dv.read_pend(4 downto 3) := "11";
when "01" => dv.read_pend(5 downto 4) := "11";
when "10" => dv.read_pend(6 downto 5) := "11";
when others => dv.read_pend(7 downto 6) := "11";
end case;
end if;
elsif dr.hwidth='1' then
dv.hwcas := not dr.hwcas;
if dr.hwcas='1' then
dv.casctr := std_logic_vector(unsigned(dr.casctr)-1);
if l2blen-l2ddrw > 1 then
dv.sdo_address(l2blen-l2ddrw+1 downto 3) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw+1 downto 3)+1));
end if;
dv.sdo_address(2) := '0';
else
dv.sdo_address(2) := not dr.sdo_address(2);
end if;
else
dv.casctr := std_logic_vector(unsigned(dr.casctr)-1);
if l2blen-l2ddrw > 1 then
dv.sdo_address(l2blen-l2ddrw downto 2) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 2)+1));
end if;
dv.sdo_address(1) := '0';
end if;
-- Set up precharge counter (will not run until casctr=0)
if dr.hwrite='0' then
dv.prectr := "00000" & dr.cfg.trtp;
else
dv.prectr := dr.twr_plus_cl;
end if;
end if;
o.read_pend := dv.read_pend(7 downto 0);
dv.rasn_pre := '1';
if precharge_next='1' and block_precharge='0' then
dv.pchpend := '0';
dv.sdo_wen := '0';
-- dv.sdo_rasn := '0';
dv.rasn_pre := '0';
dv.prectr := "000" & dr.cfg.trp;
end if;
-- Refresh and init handling
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
case dr.cmds is
when dcrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel, dr.refctr'length)) then
dv.cmds := dcoff;
end if;
-- Bypass reset delay by writing anything to regsd2
if dr.start_tog_prev='1' and
vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001" then
dv.cmds := dcoff;
end if;
when dcoff =>
-- Wait for renable to be set high and phy to be locked
dv.refctr := (others => '0');
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
dv.cfg.dllrst := '1';
dv.cfg.ocd := '0';
dv.cmds := dcinit1;
end if;
when dcinit1 =>
-- Wait >=400 ns
if dr.refctr=std_logic_vector(to_unsigned((MHz*4+9)/10, dr.refctr'length)) then
dv.cmds := dcinit2;
dv.cfg.command := CMD_PRE;
dv.cfg.emr := "00";
end if;
when dcinit2 =>
-- MR order 2,3,1,0
-- 2xcycles per command
if dr.cfg.command="000" then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := (not dr.cfg.emr(0)) & dr.cfg.emr(1); -- 00->10->11->01->00
if dr.cfg.emr="01" then
dv.cmds := dcinit3;
dv.refctr := (others => '0');
end if;
end if;
when dcinit3 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_PRE;
dv.cmds := dcinit4;
end if;
when dcinit4 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_REF;
dv.cmds := dcinit5;
end if;
when dcinit5 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_REF;
dv.cmds := dcinit6;
end if;
when dcinit6 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := "00";
dv.cfg.dllrst := '0';
dv.cmds := dcinit7;
dv.refctr := (others => '0');
end if;
when dcinit7 =>
if dr.refctr(7 downto 0)=std_logic_vector(to_unsigned(200,8)) then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := "01";
dv.cfg.ocd := '1';
dv.cmds := dcinit8;
end if;
when dcinit8 =>
if dr.cfg.command="000" then
if dr.cfg.ocd='1' then
dv.cfg.ocd := '0';
dv.cfg.command := CMD_EMR;
else
dv.cmds := dcon;
dv.cfg.renable := '0';
end if;
end if;
dv.refctr := (others => '0');
when dcon =>
if dr.cfg.cke='0' then
dv.cmds := dcoff;
elsif dr.cfg.renable='1' then
dv.cmds := dcinit2;
dv.refctr := (others => '0');
elsif dr.refctr(11 downto 0)=dr.cfg.refresh then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
end case;
-- Calculate next address
dv.ramaddr(0) := dv.ctr(0) xor dv.col(1);
if rbuf_wabits > 1 then
dv.ramaddr(rbuf_wabits-1 downto 1) :=
std_logic_vector(unsigned(dr.col(rbuf_wabits downto 2)) +
unsigned(dv.ctr(rbuf_wabits-1 downto 1)));
end if;
-- print("col: " & tost(dr.col) & ", dv.ctr: " & tost(dv.ctr) & ", res: " & tost(dv.ramaddr));
if eightbanks=0 then dv.cfg.eightbanks:='0'; end if;
rbwd := dv.rbwdata;
rbwa := dr.ramaddr;
rbw := dv.rbwrite;
if plmemwrite then
rbwd := dr.rbwdata;
rbwa := dr.ramaddr_prev;
rbw := dr.rbwrite;
end if;
if not plmemread then
o.dqm := dr.sdo_dqm;
o.sdwen := dr.sdo_wen;
o.data := dv.sdo_data;
o.cb := dv.sdo_cb;
end if;
-- half-width output data muxing, placed after (potential) pipeline regs.
if hwidthen/=0 and dr.hwidth='1' then
if dr.hwctr='1' then
o.data(ddrbits/2-1 downto 0) := o.data(2*ddrbits-ddrbits/2-1 downto ddrbits);
o.data(2*ddrbits-ddrbits/2-1 downto ddrbits) := o.data(2*ddrbits-1 downto 2*ddrbits-ddrbits/2);
if chkbits > 0 then
o.cb(chkbits/2-1 downto 0) := o.cb(2*chkbits-chkbits/2-1 downto chkbits);
o.cb(2*chkbits-chkbits/2-1 downto chkbits) := o.cb(2*chkbits-1 downto 2*chkbits-chkbits/2);
end if;
o.dqm(ddrbits/16-1 downto 0) := o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8);
o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8) := o.dqm(ddrbits/4-1 downto ddrbits/4-ddrbits/16);
else
o.data(2*ddrbits-ddrbits/2-1 downto ddrbits) := o.data(ddrbits-1 downto ddrbits/2);
if chkbits > 0 then
o.cb(2*chkbits-chkbits/2-1 downto chkbits) := o.cb(chkbits-1 downto chkbits/2);
end if;
o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8) := o.dqm(ddrbits/8-1 downto ddrbits/16);
end if;
end if;
if ddr_rst='0' then
dv.s := dsidle;
dv.cmds := dcrstdel;
dv.response := ddr_response_none;
dv.casctr := (others => '0');
dv.refctr := (others => '0');
dv.pchpend := '0';
dv.refpend := '0';
dv.rbwrite := '0';
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_nbdrive := not oepols;
dv.sdo_csn := (others => '1');
dv.rastimer := (others => '0');
dv.tras_met := '0';
dv.cfg.command := "000";
dv.cfg.emr := "00";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 4);
dv.cfg.refon := '0';
dv.cfg.trfc := conv_std_logic_vector(TRFC*MHz/1000-2, 8);
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
dv.sdo_dqm := (others => '1');
dv.cfg.dllrst := '0';
dv.cfg.cke := '0';
dv.cfg.ocd := '0';
dv.cfg.readdly := conv_std_logic_vector(readdly, 4);
dv.cfg.eightbanks := conv_std_logic_vector(eightbanks, 1)(0);
dv.cfg.odten := std_logic_vector(to_unsigned(odten,2));
dv.cfg.dqsctrl := (others => '0');
dv.cfg.strength := '0';
if pwron = 1 then dv.cfg.renable := '1'; else dv.cfg.renable:='0'; end if;
-- Default to min 15 ns tRCD, 15 ns tRP, min(7.5 ns,2*tCK) tRTP
-- Use CL=3 for DDR2-400/533, 4 for DDR2-667, 5 for DDR2-800
dv.cfg.trcd := "000";
dv.cfg.trp := "000";
dv.cfg.trtp := '0';
dv.cfg.caslat := "00";
dv.cfg.regmem := '0';
if MHz > 130 then
dv.cfg.trcd := "001";
dv.cfg.trp := "001";
end if;
if MHz > 200 then
-- Will work up to 600 MHz, then trcd/trp needs to be expanded
dv.cfg.trcd := std_logic_vector(to_unsigned((15 * MHz + 999) / 1000 - 2, 3));
dv.cfg.trp := std_logic_vector(to_unsigned((15 * MHz + 999) / 1000 - 2, 3));
end if;
if MHz > 267 then
-- Works up to 400 MHz, then trtp will need to be expanded
dv.cfg.trtp := '1';
dv.cfg.caslat := "01";
end if;
if MHz > 334 then
dv.cfg.caslat := "10";
end if;
dv.cfg.cal_rst := '1'; -- Reset input delays
dv.sdo_ba := (others => '0');
dv.sdo_address := (others => '0');
-- Default to min 45 ns tRAS
dv.cfg.tras := std_logic_vector(to_unsigned((45*MHz+999)/1000 - 2, 5));
dv.read_pend := (others => '0');
if ddr_syncrst /= 0 then
dv.cfg.cke := '0';
dv.sdo_bdrive := not oepols;
dv.sdo_qdrive := not oepols;
dv.sdo_odt := '0';
if phyptctrl /= 0 then
o.sdcke := "00";
o.bdrive := not oepols;
o.qdrive := not oepols;
o.odt := (others => '0');
end if;
end if;
end if;
if dr.cfg.odten="00" then
dv.sdo_odt := '0';
end if;
if octen=0 then
dv.sdo_oct := '0';
end if;
for x in 0 to chkbits/4-1 loop
o.cbdqm(x) := o.dqm(x*ddrbits/chkbits);
end loop;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if dr.cfg.command /= "000" then
-- print("Command: " & tost(dr.cfg.command) & " -> casn:" & tost(dv.sdo_casn) & ",rasn:" & tost(dv.sdo_rasn) & ",wen:" & tost(dv.sdo_wen));
end if;
-- Dynamic nosync handling (nosync=2)
if plmemwrite then
dv.response1 := dr.response;
dv.response2 := dr.response;
else
dv.response1 := dv.response;
dv.response2 := dv.response;
end if;
if reqsel='1' then dv.response1 := ddr_response_none; end if;
if reqsel='0' then dv.response2 := ddr_response_none; end if;
if nosync > 1 then
resp := dr.response1;
elsif plmemwrite then
resp := dr.response_prev;
else
resp := dr.response;
end if;
resp2 := dr.response2;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
rbwdata <= rbwd;
rbwaddr <= rbwa;
rbwrite <= rbw;
wbraddr <= wbra;
sdo <= o;
response <= resp;
response2 <= resp2;
ndr <= dv;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.cfg.cke <= '0';
dr.sdo_bdrive <= not oepols;
dr.sdo_qdrive <= not oepols;
dr.sdo_odt <= '0';
end if;
end process;
end;
|
gpl-2.0
|
b6a7ae179ab067803466e214584099fc
| 0.535859 | 3.380147 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/adapters/sgmii.vhd
| 1 | 7,045 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII to GMII Ethernet bridge
-- Provide a valid MDC clock input for proper functioning
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library opencores;
use opencores.ge_1000baseX_comp.all;
entity sgmii is
generic (
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
phy_addr : integer := 0;
mode : integer := 0 -- unused
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
ser_rx_p : in std_logic;
ser_rx_n : in std_logic;
ser_tx_p : out std_logic;
ser_tx_n : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
tx_clk : out std_logic;
tx_rstn : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
rx_clk : out std_logic;
rx_rstn : out std_logic;
-- optional MDIO interface to PCS
mdc : in std_logic; -- must be provided
mdio_o : in std_logic := '0';
mdio_oe : in std_logic := '1';
mdio_i : out std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
) ;
end entity ;
architecture rtl of sgmii is
signal tx_in_int_reversed, rx_out_int_reversed, tx_in_int, rx_out_int, rx_out_pll_int : std_logic_vector(9 downto 0);
signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rx_rstn_int, rx_rst_int, rx_pll_rstn_int, rx_pll_rst_int, tx_pll_rst_int, tx_pll_rstn_int, startup_enable_int : std_logic;
signal mdio_int, bitslip_int : std_logic;
signal rx_int_clk : std_logic_vector(0 downto 0) ;
signal debug_int : std_logic_vector(31 downto 0) ;
signal ready_sig : std_logic;
begin
rx_rst_int <= not rx_rstn_int;
rx_pll_rst_int <= not rx_pll_rstn_int;
tx_pll_rst_int <= not tx_pll_rstn_int;
pma0: serdes
generic map (
fabtech => fabtech,
transtech => transtech
)
port map (
clk_125 => clk_125,
rst_125 => rst_125,
rx_in_p => ser_rx_p,
rx_in_n => ser_rx_n,
rx_out => rx_out_int,
rx_clk => rx_clk_int,
rx_rstn => rx_rstn_int,
rx_pll_clk => rx_pll_clk_int,
rx_pll_rstn => rx_pll_rstn_int,
tx_pll_clk => tx_pll_clk_int,
tx_pll_rstn => tx_pll_rstn_int,
tx_in => tx_in_int,
tx_out_p => ser_tx_p,
tx_out_n => ser_tx_n,
bitslip => bitslip_int,
apbin => apbin,
apbout => apbout,
m2gl_padin => m2gl_padin,
m2gl_padout => m2gl_padout,
serdes_clk125 => serdes_clk125,
serdes_ready => ready_sig
);
str0: if (fabtech = stratix3) or (fabtech = stratix4) or (is_unisim(fabtech) = 1) generate
-- COMMA DETECTOR WITH BITSLIP LOGIC
cd0: comma_detect
generic map (
bsbreak => 16,
bswait => 63
)
port map (
clk => rx_clk_int,
rstn => rx_rstn_int,
indata => rx_out_int,
bitslip => bitslip_int
);
-- ELASTIC BUFFER WITH INTERNAL FIFO
eb0: elastic_buffer
generic map (
tech => memtech,
abits => 7
)
port map (
wr_clk => rx_clk_int,
wr_rst => rx_rst_int,
wr_data => rx_out_int,
rd_clk => rx_pll_clk_int,
rd_rst => rx_pll_rst_int,
rd_data => rx_out_pll_int
);
rx_aligned <= '0'; --not used
end generate;
igl2 : if (fabtech = igloo2) generate
-- comma detector and word aligner
wa0: word_aligner
port map (
clk => rx_clk_int,
rstn => rx_rstn_int,
rx_in => rx_out_int,--rx_out_igl2,
val_in => rx_rstn_int,
rx_out => rx_out_pll_int,
val_out => open,
aligned => rx_aligned);
end generate;
pcs0 : ge_1000baseX
generic map (
PHY_ADDR => phy_addr,
BASEX_AN_MODE => mode
)
port map(
rx_ck => rx_pll_clk_int,
tx_ck => tx_pll_clk_int,
rx_reset => rx_pll_rst_int,
tx_reset => tx_pll_rst_int,
startup_enable => startup_enable_int,
tbi_rxd => rx_out_pll_int, -- abcdefghij
tbi_txd => tx_in_int, -- abcdefghij
gmii_rxd => rxd,
gmii_rx_dv => rx_dv,
gmii_rx_er => rx_er,
gmii_col => rx_col,
gmii_cs => rx_crs,
gmii_txd => txd,
gmii_tx_en => tx_en,
gmii_tx_er => tx_er,
repeater_mode => '0',
mdc_reset => rst_125,
mdio_i => mdio_int,
mdio_o => mdio_i,
mdc => mdc,
debug => debug_int
);
mdio_int <= mdio_o when mdio_oe = '0' else
'0';
startup_enable_int <= (not rst_125) and ready_sig;
rx_clk <= rx_pll_clk_int; --rx_clk_int;
rx_rstn <= rx_pll_rstn_int;
tx_clk <= tx_pll_clk_int; --clk_125;
tx_rstn <= tx_pll_rstn_int;
end architecture ; -- rtl
|
gpl-2.0
|
991acb27536d1b1c0bc6e3a5ad532e66
| 0.516962 | 3.370813 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3sl150/leon3mp.vhd
| 1 | 24,319 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.net.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000; -- frequency of main clock (used for PLLs)
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clk125 : in std_ulogic;
errorn : out std_ulogic;
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
--rxd1 : in std_logic;
--txd1 : out std_logic;
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
-- flash/ssram bus
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 0);
rstoutn : out std_ulogic;
sram_advn : out std_ulogic;
sram_csn : out std_logic;
sram_wen : out std_logic;
sram_ben : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_clk : out std_ulogic;
sram_psn : out std_ulogic;
sram_wait : in std_logic_vector(1 downto 0);
flash_clk : out std_ulogic;
flash_advn : out std_logic;
flash_cen : out std_logic;
flash_oen : out std_logic;
flash_resetn: out std_logic;
flash_wen : out std_logic;
max_csn : out std_logic;
-- sram_adsp_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (8 downto 0); -- ddr dm
ddr_dqsp : inout std_logic_vector (8 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (8 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (15 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (71 downto 0); -- ddr data
-- ddra_cke : out std_logic;
ddra_csb : out std_logic;
-- ddra_web : out std_ulogic; -- ddr write enable
-- ddra_rasb : out std_ulogic; -- ddr ras
-- ddra_casb : out std_ulogic; -- ddr cas
-- ddra_ad : out std_logic_vector (14 downto 0); -- ddr address
-- ddra_ba : out std_logic_vector (2 downto 0); -- ddr bank address
--
-- ddrb_cke : out std_logic;
ddrb_csb : out std_logic;
-- ddrb_web : out std_ulogic; -- ddr write enable
-- ddrb_rasb : out std_ulogic; -- ddr ras
-- ddrb_casb : out std_ulogic; -- ddr cas
-- ddrb_ad : out std_logic_vector (14 downto 0); -- ddr address
-- ddrb_ba : out std_logic_vector (2 downto 0); -- ddr bank address
--
-- ddrab_clk : inout std_logic_vector(1 downto 0);
-- ddrab_clkb : inout std_logic_vector(1 downto 0);
-- ddrab_odt : out std_logic_vector(1 downto 0);
-- ddrab_dqsp : inout std_logic_vector(1 downto 0); -- ddr dqs
-- ddrab_dqsn : inout std_logic_vector(1 downto 0); -- ddr dqs
-- ddrab_dm : out std_logic_vector(1 downto 0); -- ddr dm
-- ddrab_dq : inout std_logic_vector (15 downto 0);-- ddr data
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ddr_clk_fb : std_ulogic;
-- -- DDR2 Device A&B
-- signal ddrab_clkv : std_logic_vector(2 downto 0);
-- signal ddrab_clkbv : std_logic_vector(2 downto 0);
-- signal ddra_ckev : std_logic_vector(1 downto 0);
-- signal ddra_csbv : std_logic_vector(1 downto 0);
-- signal ddrb_ckev : std_logic_vector(1 downto 0);
-- signal ddrb_csbv : std_logic_vector(1 downto 0);
-- signal lockab : std_logic;
-- signal clkmlab : std_logic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sram_clkl : std_ulogic;
signal cgi,cgi2 : clkgen_in_type;
signal cgo,cgo2 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal lclk, lclkout, lclk125, clkm125 : std_ulogic;
signal dsubre : std_ulogic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
cgi2.pllctrl <= "00"; cgi2.pllrst <= not resetn; cgi2.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clk125_pad : clkpad generic map (tech => padtech) port map (clk125, lclk125);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
clkm125 <= lclk125;
phy_gtx_clk <= lclk125;
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, sram_clkl);
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, sram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0 : ahbuart -- Debug UART
-- generic map (hindex => NCPU, pindex => 4, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
-- end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#a00#, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
srams_pad : outpad generic map ( tech => padtech)
port map (sram_csn, vcc(0));
flash_cen_pad : outpad generic map (tech => padtech)
port map (flash_cen, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
srams_pad : outpad generic map ( tech => padtech)
port map (sram_csn, memo.ramsn(0));
sram_oen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.oen);
sram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_ben, memo.wrn);
sram_wri_pad : outpad generic map (tech => padtech)
port map (sram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
sram_advn_pad : outpad generic map (tech => padtech)
port map (sram_advn, gnd(0));
sram_psn_pad : outpad generic map (tech => padtech)
port map (sram_psn, vcc(0));
flash_advn_pad : outpad generic map (tech => padtech)
port map (flash_advn, gnd(0));
flash_cen_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
flash_wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
flash_reset_pad : outpad generic map (tech => padtech)
port map (flash_resetn, resetn);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
end generate;
max_csn_pad : outpad generic map (tech => padtech)
port map (max_csn, vcc(0));
ddrsp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech,
memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => 125000/1000, rskew => 0, TRFC => CFG_DDR2SP_TRFC,
clkmul => (CFG_DDR2SP_FREQ*5)/125, clkdiv => 5, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => dbits,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
odten => 3, octen => 1, readdly => 1)
port map ( resetn, rstn, clkm125, clkm, clkm125, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, ddr_clk_fb, ddr_clk_fb, ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm(dbits/8-1 downto 0), ddr_dqsp(dbits/8-1 downto 0), ddr_dqsn(dbits/8-1 downto 0),
ddr_ad(13 downto 0), ddr_ba(1 downto 0), ddr_dq(dbits-1 downto 0), ddr_odt);
ddr_clk <= ddr_clkv(2 downto 0); ddr_clkb <= ddr_clkbv(2 downto 0);
ddr_cke <= ddr_ckev(1 downto 0); ddr_csb <= ddr_csbv(1 downto 0);
ddr_ad(15 downto 14) <= (others => '0');
ddr_ba(2) <= '0';
end generate;
noddr : if (CFG_DDR2SP = 0) generate lock <= '1'; end generate;
-- Disable DDR2 Device A and B
ddra_csb <= '1';
ddrb_csb <= '1';
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 18,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
-- loopback
u1i.rxd <= u1o.txd;
--upads : if CFG_AHB_UART = 0 generate
-- u1i.rxd <= rxd1; txd1 <= u1o.txd;
--end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
gpioi.din(i) <= gpio(i);
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP3SL150 PSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
33ab345d8183be882393399f319ecf6f
| 0.550064 | 3.595358 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/can/can_oc.in.vhd
| 6 | 350 |
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT : integer := CONFIG_CAN_FT;
|
gpl-2.0
|
1dcfa91165cd224f0ffd4a518f692f07
| 0.68 | 3.723404 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/stdlib/stdlib.vhd
| 1 | 19,850 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: stdlib
-- File: stdlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package for common VHDL functions
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.version.all;
package stdlib is
constant LIBVHDL_VERSION : integer := grlib_version;
constant LIBVHDL_BUILD : integer := grlib_build;
-- pragma translate_off
constant LIBVHDL_DATE : string := grlib_date;
-- pragma translate_on
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
constant zero128 : std_logic_vector(127 downto 0) := (others => '0');
constant one32 : std_logic_vector(31 downto 0) := (others => '1');
constant one64 : std_logic_vector(63 downto 0) := (others => '1');
constant one128 : std_logic_vector(127 downto 0) := (others => '1');
type log2arr is array(0 to 512) of integer;
constant log2 : log2arr := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant log2x : log2arr := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
function log2ext(i: integer) return integer;
function decode(v : std_logic_vector) return std_logic_vector;
function genmux(s,v : std_logic_vector) return std_ulogic;
function xorv(d : std_logic_vector) return std_ulogic;
function orv(d : std_logic_vector) return std_ulogic;
function andv(d : std_logic_vector) return std_ulogic;
function notx(d : std_logic_vector) return boolean;
function notx(d : std_ulogic) return boolean;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
function "+" (i : integer; d : std_logic_vector) return std_logic_vector;
function "-" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function "-" (a, b : std_logic_vector) return std_logic_vector;
function "+" (a, b : std_logic_vector) return std_logic_vector;
function "*" (a, b : std_logic_vector) return std_logic_vector;
function unsigned_mul (a, b : std_logic_vector) return std_logic_vector;
function signed_mul (a, b : std_logic_vector) return std_logic_vector;
function mixed_mul (a, b : std_logic_vector; sign : std_logic) return std_logic_vector;
--function ">" (a, b : std_logic_vector) return boolean;
function "<" (i : integer; b : std_logic_vector) return boolean;
function conv_integer(v : std_logic_vector) return integer;
function conv_integer(v : std_logic) return integer;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector;
function conv_std_logic(b : boolean) return std_ulogic;
attribute sync_set_reset : string;
attribute async_set_reset : string;
-- Reporting and diagnostics
-- pragma translate_off
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
function tost_any(s: std_ulogic) return string;
function tost_bits(s: std_logic_vector) return string;
function tost(b: boolean) return string;
function tost(r: real) return string;
procedure print(s : string);
component report_version
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end component;
component report_design
generic (msg1, fabtech, memtech : string := ""; mdel : integer := 4);
end component;
-- pragma translate_on
function unary_to_slv(i: std_logic_vector) return std_logic_vector;
end;
package body stdlib is
function notx(d : std_logic_vector) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
function notx(d : std_ulogic) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
-- generic decoder
function decode(v : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0);
variable i : integer range res'range;
begin
res := (others => '0'); i := 0;
if notx(v) then i := to_integer(unsigned(v)); end if;
res(i) := '1';
return(res);
end;
-- generic multiplexer
function genmux(s,v : std_logic_vector) return std_ulogic is
variable res : std_logic_vector(v'length-1 downto 0);
variable i : integer range res'range;
begin
res := v; i := 0;
if notx(s) then i := to_integer(unsigned(s)); end if;
return(res(i));
end;
-- vector XOR
function xorv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '0';
for i in d'range loop tmp := tmp xor d(i); end loop;
return(tmp);
end;
-- vector OR
function orv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '0';
for i in d'range loop tmp := tmp or d(i); end loop;
return(tmp);
end;
-- vector AND
function andv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '1';
for i in d'range loop tmp := tmp and d(i); end loop;
return(tmp);
end;
-- unsigned multiplication
function "*" (a, b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) * unsigned(b)));
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
-- signed multiplication
function signed_mul (a, b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(signed(a) * signed(b)));
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
-- unsigned multiplication
function unsigned_mul (a, b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) * unsigned(b)));
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
-- signed/unsigned multiplication
function mixed_mul (a, b : std_logic_vector; sign : std_logic) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
if sign = '0' then
return(std_logic_vector(unsigned(a) * unsigned(b)));
else
return(std_logic_vector(signed(a) * signed(b)));
end if;
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
-- unsigned addition
function "+" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) + unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
function "+" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
-- unsigned subtraction
function "-" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) - unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) - i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(i - unsigned(d)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) - unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function ">=" (a, b : std_logic_vector) return boolean is
begin
return(unsigned(a) >= unsigned(b));
end;
function "<" (i : integer; b : std_logic_vector) return boolean is
begin
return( i < to_integer(unsigned(b)));
end;
function ">" (a, b : std_logic_vector) return boolean is
begin
return(unsigned(a) > unsigned(b));
end;
function conv_integer(v : std_logic_vector) return integer is
begin
if notx(v) then return(to_integer(unsigned(v)));
else return(0); end if;
end;
function conv_integer(v : std_logic) return integer is
begin
if notx(v) then
if v = '1' then return(1);
else return(0); end if;
else return(0); end if;
end;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_unsigned(i, w));
return(tmp);
end;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_signed(i, w));
return(tmp);
end;
function conv_std_logic(b : boolean) return std_ulogic is
begin
if b then return('1'); else return('0'); end if;
end;
function log2ext(i: integer) return integer is
-- variable v: std_logic_vector(31 downto 0);
begin
-- workaround for DC bug
-- if i=0 then return 0; end if;
-- v := std_logic_vector(to_unsigned((i-1),v'length));
-- for x in v'high downto v'low loop
-- if v(x)='1' then return x+1; end if;
-- end loop;
-- return 0;
for x in 1 to 32 loop
if (2**x > i) then return (x-1); end if;
end loop;
return 32;
end;
-- pragma translate_off
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost_any(s: std_ulogic) return string is
begin
case s is
when '1' => return "1";
when '0' => return "0";
when '-' => return "-";
when 'U' => return "U";
when 'X' => return "X";
when 'Z' => return "Z";
when 'H' => return "H";
when 'L' => return "L";
when 'W' => return "W";
end case;
end;
function tost_bits(s: std_logic_vector) return string is
constant len: natural := s'length;
variable str: string(1 to len);
variable i: integer;
begin
i := 1;
for x in s'range loop
str(i to i) := tost_any(s(x));
i := i+1;
end loop;
return str;
end;
function tost(b: boolean) return string is
begin
if b then return "true"; else return "false"; end if;
end tost;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
function tost(r: real) return string is
variable x: real;
variable i,j: integer;
variable s: string(1 to 30);
variable c: character;
begin
if r = 0.0 then
return "0.0000";
elsif r < 0.0 then
return "-" & tost(-r);
elsif r < 0.001 then
x:=r; i:=0;
while x<1.0 loop x:=x*10.0; i:=i+1; end loop;
return tost(x) & "e-" & tost(i);
elsif r >= 1000000.0 then
x:=10000000.0; i:=6;
while r>=x loop x:=x*10.0; i:=i+1; end loop;
return tost(10.0*r/x) & "e+" & tost(i);
else
i:=0; x:=r+0.00005;
while x >= 10.0 loop x:=x/10.0; i:=i+1; end loop;
j := 1;
while i > -5 loop
if x >= 9.0 then c:='9'; x:=x-9.0;
elsif x >= 8.0 then c:='8'; x:=x-8.0;
elsif x >= 7.0 then c:='7'; x:=x-7.0;
elsif x >= 6.0 then c:='6'; x:=x-6.0;
elsif x >= 5.0 then c:='5'; x:=x-5.0;
elsif x >= 4.0 then c:='4'; x:=x-4.0;
elsif x >= 3.0 then c:='3'; x:=x-3.0;
elsif x >= 2.0 then c:='2'; x:=x-2.0;
elsif x >= 1.0 then c:='1'; x:=x-1.0;
else c:='0';
end if;
s(j) := c;
j:=j+1;
if i=0 then s(j):='.'; j:=j+1; end if;
i:=i-1;
x := x * 10.0;
end loop;
return s(1 to j-1);
end if;
end tost;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
-- pragma translate_on
function unary_to_slv(i: std_logic_vector) return std_logic_vector is
variable o : std_logic_vector(log2(i'length)-1 downto 0);
begin
-- -- 16 bits unary to binary conversion
-- o(0) := i(1) or i(3) or i(5) or i(7) or i(9) or i(11) or i(13) or i(15);
-- o(1) := i(2) or i(3) or i(6) or i(7) or i(10) or i(11) or i(14) or i(15);
-- o(2) := i(4) or i(5) or i(6) or i(7) or i(12) or i(13) or i(14) or i(15);
-- o(3) := i(8) or i(9) or i(10) or i(11) or i(12) or i(13) or i(14) or i(15);
--
-- -- parametrized conversion
--
-- o(0) := i(1);
--
-- o(0) := unary_to_slv(i(3 downto 2)) or unary_to_slv(i(1 downto 0));
-- o(1) := orv(i(3 downto 2));
--
-- o(1 downto 0) := unary_to_slv(i(7 downto 4)) or unary_to_slv(i(3 downto 0));
-- o(2) := orv(i(7 downto 4));
--
-- o(2 downto 0) := unary_to_slv(i(15 downto 8)) or unary_to_slv(i(7 downto 0));
-- o(3) := orv(i(15 downto 8));
--
assert i'length = 0 or i'length = 2**log2(i'length)
report "unary_to_slv: input vector size must be power of 2"
severity failure;
if i'length > 2 then
-- recursion on left and right halves
o(log2(i'length)-2 downto 0) := unary_to_slv(i(i'left downto (i'left-i'length/2+1))) or unary_to_slv(i((i'left-i'length/2) downto i'right));
o(log2(i'length)-1) := orv(i(i'left downto (i'left-i'length/2+1)));
else
o(0 downto 0) := ( 0 => i(i'left));
end if;
return o;
end unary_to_slv;
end;
|
gpl-2.0
|
051c4edf3a2f602bddd40f2dfe8f1ee3
| 0.624534 | 2.738309 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/adqsout.vhd
| 3 | 8,705 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic--;
--dfflo : out std_logic;
--dffhi : out std_logic;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : stratixiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "false",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => dqs_reg,
o => dqs_buf,
obar => dqsn_buf
);
-- Outout enable and oct for DQS, DQSN ----------------------------------------------
dqs_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
dqs_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg_n <= not dqsn_oe_reg;
dqsn_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DQS, DQSN) -----------------------------------------------------------
dqs_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqs_buf,
oe => dqs_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqs_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqs_pad,
obar => open
);
dqsn_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqsn_buf,
oe => dqsn_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqsn_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqsn_pad,
obar => open
);
end;
|
gpl-2.0
|
3370c1065f75a842f63a67fa7bc746ce
| 0.394486 | 4.173058 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/fmf/flash/flash.vhd
| 3 | 5,307 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.ALL;
USE ieee.vital_primitives.ALL;
library fmf;
use fmf.gen_utils.all;
use fmf.conversions.all;
package flash is
component s25fl064a
generic (
tipd_SCK : VitalDelayType01 := VitalZeroDelay01;
tipd_SI : VitalDelayType01 := VitalZeroDelay01;
tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_SCK_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_CSNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tsetup_SI_SCK : VitalDelayType := UnitDelay;
tsetup_CSNeg_SCK : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_SCK : VitalDelayType := UnitDelay;
tsetup_WNeg_CSNeg : VitalDelayType := UnitDelay;
thold_SI_SCK : VitalDelayType := UnitDelay;
thold_CSNeg_SCK : VitalDelayType := UnitDelay;
thold_HOLDNeg_SCK : VitalDelayType := UnitDelay;
thold_WNeg_CSNeg : VitalDelayType := UnitDelay;
tpw_SCK_posedge : VitalDelayType := UnitDelay;
tpw_SCK_negedge : VitalDelayType := UnitDelay;
tpw_CSNeg_posedge : VitalDelayType := UnitDelay;
tperiod_SCK_rd : VitalDelayType := UnitDelay;
tperiod_SCK_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 3 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 384 sec;
tdevice_WR : VitalDelayType := 60 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES : VitalDelayType := 30 us;
tdevice_PU : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "s25fl064a.mem";
UserPreload : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
SCK : IN std_ulogic := 'U';
SI : IN std_ulogic := 'U';
CSNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
SO : OUT std_ulogic := 'U'
);
end component;
component m25p80
generic (
tipd_C : VitalDelayType01 := VitalZeroDelay01;
tipd_D : VitalDelayType01 := VitalZeroDelay01;
tipd_SNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_C_Q : VitalDelayType01 := UnitDelay01;
tpd_SNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tsetup_D_C : VitalDelayType := UnitDelay;
tsetup_SNeg_C : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_C : VitalDelayType := UnitDelay;
tsetup_C_HOLDNeg : VitalDelayType := UnitDelay;
tsetup_WNeg_SNeg : VitalDelayType := UnitDelay;
thold_D_C : VitalDelayType := UnitDelay;
thold_SNeg_C : VitalDelayType := UnitDelay;
thold_HOLDNeg_C : VitalDelayType := UnitDelay;
thold_C_HOLDNeg : VitalDelayType := UnitDelay;
thold_WNeg_SNeg : VitalDelayType := UnitDelay;
tpw_C_posedge : VitalDelayType := UnitDelay;
tpw_C_negedge : VitalDelayType := UnitDelay;
tpw_SNeg_posedge : VitalDelayType := UnitDelay;
tperiod_C_rd : VitalDelayType := UnitDelay;
tperiod_C_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 5 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 20 sec;
tdevice_WR : VitalDelayType := 15 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES1 : VitalDelayType := 3 us;
tdevice_RES2 : VitalDelayType := 1.8 us;
tdevice_VSL : VitalDelayType := 10 us;
tdevice_PUW : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "m25p80.mem";
UserPreload : BOOLEAN := FALSE;
DebugInfo : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
C : IN std_ulogic := 'U';
D : IN std_ulogic := 'U';
SNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
Q : OUT std_ulogic := 'U'
);
end component;
end flash;
|
gpl-2.0
|
de00fbb26b34d3b00845983d5fba11bf
| 0.556058 | 4.38595 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/comp00.vhd
| 1 | 1,463 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comp00 is
port(
clkcmp: in std_logic ;
codopcmp: in std_logic_vector ( 3 downto 0 );
portAcmp: in std_logic_vector ( 7 downto 0 );
portBcmp: in std_logic_vector ( 7 downto 0 );
inFlagcmp: in std_logic;
outcmp: out std_logic_vector ( 7 downto 0 );
outFlagcmp: out std_logic );
end;
architecture comp0 of comp00 is
begin
pcmp: process(codopcmp, portAcmp, portBcmp)
begin
if(codopcmp = "1111") then
if(portAcmp > portBcmp) then
outcmp <= portAcmp;
else
outcmp <= portBcmp;
end if;
outFlagcmp <= '1';
else
outcmp <= (others => 'Z');
outFlagcmp <= 'Z';
end if;
end process pcmp;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end comp0;
|
apache-2.0
|
107bbf6274e423f5dfd4103727fdcd0c
| 0.508544 | 3.08 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xup/testbench.vhd
| 1 | 8,918 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sysace_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal errorn : std_logic;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(15 downto 0);
signal xdata : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal writen, read : std_ulogic;
signal oen : std_ulogic;
signal flash_rstn : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_logic; -- UART1 tx data
signal rxd1 : std_logic; -- UART1 rx data
signal gpio : std_logic_vector(31 downto 0); -- I/O port
signal flash_cex : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal emdc, emdio, eresetn : std_logic;
signal etx_slew : std_logic_vector(1 downto 0);
signal leds : std_logic_vector(1 downto 0);
signal vid_clock : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal cf_mpa : std_logic_vector(6 downto 0);
signal cf_mpd : std_logic_vector(15 downto 0);
signal cf_mp_ce_z : std_ulogic;
signal cf_mp_oe_z : std_ulogic;
signal cf_mp_we_z : std_ulogic;
signal cf_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
signal dsuen : std_ulogic;
signal dsubre : std_ulogic;
signal dsuact : std_ulogic;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sysace_clk <= not sysace_clk after 15 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H'; errorn <= 'H'; dsuen <= '0'; dsubre <= 'H';
ddr_clk_fb <= ddr_clk_fb_out; rxd1 <= txd1;
cf_mpd <= (others => 'H'); cf_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk, errorn, dsuen, dsubre, dsuact,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb_out, ddr_cke, ddr_csb,
ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
rxd1, txd1, leds(0), leds(1),
-- gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, eresetn, etx_slew, ps2clk, ps2data,
vid_clock, vid_blankn, vid_syncn, vid_hsync, vid_vsync,
vid_r, vid_g, vid_b,
cf_mpa, cf_mpd, cf_mp_ce_z, cf_mp_oe_z, cf_mp_we_z, cf_mpirq
);
ddrmem : for i in 0 to 1 generate
-- u3 : mt46v16m16
-- generic map (index => 3, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 2, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(5 downto 4));
-- u0 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(7 downto 6));
ddr0 : ddrram
generic map(width => 64, abits => 14, colbits => 9, rowbits => 14,
implbanks => 1, fname => sdramfile, speedbin => 1, density => 1)
port map (ck => ddr_clk(i), cke => ddr_cke(i), csn => ddr_csb(i),
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data,
gnd, gnd, romsn, writen, oen);
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
xdata <= "0000000000000000" & data;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, errorn, address(20 downto 1), xdata,
iosn, oen, writen, open);
data <= buskeep(data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
|
gpl-2.0
|
759dd60ca59285291b80022395b9435d
| 0.593519 | 3.156814 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/esa/pci/pci_arb.vhd
| 4 | 18,127 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
--============================================================================--
-- Design unit : pci_arb
--
-- File name : pci_arb.vhd
--
-- Purpose : Arbiter for the PCI bus
-- - configurable size: 4, 8, 16, 32 agents
-- - nested round-robbing in two different priority levels
-- - priority assignment hard-coded or APB-programmable
--
-- Reference : PCI Local Bus Specification, Revision 2.1,
-- PCI Special Interest Group, 1st June 1995
-- (for information: http:
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http:
--
-- Note : Numbering for req_n, gnt_n, or priority levels is in
-- increasing order <0 = left> to <NUMBER-1 = right>.
-- APB data/address arrays are in the conventional order:
-- The least significant bit is located to the
-- right, carrying the lower index number (usually 0).
-- The arbiter considers strong signal levels ('1' and '0')
-- only. Weak levels ('H', 'L') are not considered. The
-- appropriate translation function (to_X01) must be applied
-- to the inputs. This is usually done by the pads,
-- and therefore not contained in this model.
--
-- Configuration: The arbiter can be configured to NB_AGENTS = 4, 8, 16 or 32.
-- A priority level (0 = high, 1 = low) is assigned to each device.
-- Exception is agent NB_AGENTS-1, which has always lowest priority.
--
-- a) The priority levels are hard-coded, when APB_PRIOS = false.
-- In this case, the APB ports (pbi/pbo) are unconnected.
-- The constant ARB_LVL_C must then be set to appropriate values.
--
-- b) When APB_PRIOS = true, the levels are programmable via the
-- APB-address 0x80 (allows to be ored with the PCI interface):
-- Bit 31 (leftmost) = master 31 . . bit 0 (rightmost) = master 0.
-- Bit NB_AGENTS-1 is dont care at write and reads 1.
-- Bits NB_AGENTS to 31, if existing, are dont care and read 0.
-- The constant ARB_LVL_C is then the reset value.
--
-- Algorithm : The algorithm is described in the implementation note of
-- section 3.4 of the PCI standard:
-- The bus is granted by two nested round-robbing loops.
-- An agent number and a priority level is assigned to each agent.
-- The agent number determines, the pair of req_n/gnt_n lines.
-- Agents are counted from 0 to NB_AGENTS-1.
-- All agents in one level have equal access to the bus
-- (round-robbing); all agents of level 1 as a group have access
-- equal to each agent of level 0.
-- Re-arbitration occurs, when frame_n is asserted, as soon
-- as any other master has requested the bus, but only
-- once per transaction.
--
-- b) With programmable priorities. The priority level of all
-- agents (except NB_AGENTS-1) is programmable via APB.
-- In a 256 byte APB address range, the priority level of
-- agent N is accessed via the address 0x80 + 4*N. The APB
-- slave returns 0 on all non-implemented addresses, the
-- address bits (1:0) are not decoded. Since only addresses
-- >= 0x80 are occupied, it can be used in parallel (ored
-- read data) with our PCI interface (uses <= 0x78).
-- The constant ARB_LVL_C in pci_arb_pkg is the reset value.
--
-- Timeout: The "broken master" timeout is another reason for
-- re-arbitration (section 3.4.1 of the standard). Grant is
-- removed from an agent, which has not started a cycle
-- within 16 cycles after request (and grant). Reporting of
-- such a 'broken' master is not implemented.
--
-- Turnover: A turnover cycle is required by the standard, when re-
-- arbitration occurs during idle state of the bus.
-- Notwithstanding to the standard, "idle state" is assumed,
-- when frame_n is high for more than 1 cycle.
--
-- Bus parking : The bus is parked to agent 0 after reset, it remains granted
-- to the last owner, if no other agent requests the bus.
-- When another request is asserted, re-arbitration occurs
-- after one turnover cycle.
--
-- Lock : Lock is defined as a resource lock by the PCI standard.
-- The optional bus lock mentioned in the standard is not
-- considered here and there are no special conditions to
-- handle when lock_n is active.
-- in arbitration.
--
-- Latency : Latency control in PCI is via the latency counters of each
-- agent. The arbiter does not perform any latency check and
-- a once granted agent continues its transaction until its
-- grant is removed AND its own latency counter has expired.
-- Even though, a bus re-arbitration occurs during a
-- transaction, the hand-over only becomes effective,
-- when the current owner deasserts frame_n.
--
-- Limitations : [add here known bugs and limitations]
--
-- Library : work
--
-- Dependencies : LEON config package
-- package amba, can be retrieved from:
-- http:
--
-- Author : Roland Weigand <[email protected]>
-- European Space Agency (ESA)
-- Microelectronics Section (TOS-ESM)
-- P.O. Box 299
-- NL-2200 AG Noordwijk ZH
-- The Netherlands
--
-- Contact : mailto:[email protected]
-- http:
-- Copyright (C): European Space Agency (ESA) 2002.
-- This source code is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2 of the License, or (at your option) any
-- later version. For full details of the license see file
-- http:
--
-- It is recommended that any use of this VHDL source code is
-- reported to the European Space Agency. It is also recommended
-- that any use of the VHDL source code properly acknowledges the
-- European Space Agency as originator.
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit. This information does not
-- necessarily reflect the policy of the European Space Agency.
--
-- Simulator : Modelsim 5.5e on Linux RedHat 7.2
--
-- Synthesis : Synopsys Version 1999.10 on Sparc + Solaris 5.5.1
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.0 R. W. 2000/11/02 File created
-- 0.1 J.Gaisler 2001/04/10 Integrated in LEON
-- 0.2 R. Weigand 2001/04/25 Connect arb_lvl reg to AMBA clock/reset
-- 0.3 R. Weigand 2002/03/19 Default assignment to owneri in find_next
-- 1.0 RW. 2002/04/08 Implementation of TMR registers
-- Removed recursive function call
-- Fixed ARB_LEVELS = 2
-- 3.0 R. Weigand 2002/04/16 Released for leon2
-- 4.0 M. Isomaki 2004/10/19 Minor changes for GRLIB integration
-- 4.1 J.Gaisler 2004/11/17 Minor changes for GRLIB integration
--$Log$
-- Revision 3.1 2002/07/31 13:22:09 weigand
-- Bugfix for cases where no valid request in level 0 (level 1 was not rearbitrated)
--
-- Revision 3.0 2002/07/24 12:19:38 weigand
-- Installed RCS with version 3.0
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library esa;
use esa.pci_arb_pkg.all;
entity pci_arb is
generic(NB_AGENTS : integer := 4;
ARB_SIZE : integer := 2;
APB_EN : integer := 1
);
port (clk : in clk_type; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in clk_type; -- APB clock
prst_n : in std_logic; -- APB reset
pbi : in EAPB_Slv_In_Type; -- APB inputs
pbo : out EAPB_Slv_Out_Type -- APB outputs
);
end pci_arb;
architecture rtl of pci_arb is
subtype agent_t is std_logic_vector(ARB_SIZE-1 downto 0);
subtype arb_lvl_t is std_logic_vector(NB_AGENTS-1 downto 0);
subtype agentno_t is integer range 0 to NB_AGENTS-1;
-- Note: the agent with the highest index (3, 7, 15, 31) is always in level 1
-- Example: x010 = prio 0 for agent 2 and 0, prio 1 for agent 3 and 1.
-- Default: start with all devices equal priority at level 1.
constant ARB_LVL_C : arb_lvl_t := (others => '1');
constant all_ones : std_logic_vector(0 to NB_AGENTS-1) := (others => '1');
--Necessary definitions from amba.vhd and iface.vhd
--added to pci_arb package with modified names to avoid
--name clashes in GRLIB
constant APB_PRIOS : boolean := APB_EN = 1;
signal owner0, owneri0 : agent_t; -- current owner in level 0
signal owner1, owneri1 : agent_t; -- current owner in level 1
signal cown, cowni : agent_t; -- current level
signal rearb, rearbi : std_logic; -- re-arbitration flag
signal tout, touti : std_logic_vector(3 downto 0); -- timeout counter
signal turn, turni : std_logic; -- turnaround cycle
signal arb_lvl, arb_lvli : arb_lvl_t; -- := ARB_LVL_C; -- level registers
type nmstarr is array (0 to 3) of agentno_t;
type nvalarr is array (0 to 3) of boolean;
begin -- rtl
----------------------------------------------------------------------------
-- PCI ARBITER
----------------------------------------------------------------------------
-- purpose: Grants the bus depending on the request signals. All agents have
-- equal priority, if another request occurs during a transaction, the bus is
-- granted to the new agent. However, PCI protocol specifies that the master
-- can finish the current transaction within the limit of its latency timer.
arbiter : process(cown, owner0, owner1, req_n, rearb, tout, turn, frame_n,
arb_lvl, rst_n)
variable owner0v, owner1v : agentno_t; -- integer variables for current owner
variable new_request : agentno_t; -- detected request
variable nmst : nmstarr;
variable nvalid : nvalarr;
begin -- process arbiter
-- default assignments
rearbi <= rearb;
owneri0 <= owner0;
owneri1 <= owner1;
cowni <= cown;
touti <= tout;
turni <= '0'; -- no turnaround
-- re-arbitrate once during the transaction,
-- or when timeout counter expired (bus idle).
if (frame_n = '0' and rearb = '0') or turn = '1' then
owner0v := conv_integer(owner0);
owner1v := conv_integer(owner1);
new_request := conv_integer(cown);
nvalid(0 to 3) := (others => false);
nmst(0 to 3) := (others => 0);
-- Determine next request in both priority levels
rob : for i in NB_AGENTS-1 downto 0 loop
-- consider all masters with valid request
if req_n(i) = '0' then
-- next in prio level 0
if arb_lvl(i) = '0' then
if i > owner0v then
nmst(0) := i; nvalid(0) := true;
elsif i < owner0v then
nmst(1) := i; nvalid(1) := true;
end if;
-- next in prio level 1
elsif arb_lvl(i) = '1' then
if i > owner1v then
nmst(2) := i; nvalid(2) := true;
elsif i < owner1v then
nmst(3) := i; nvalid(3) := true;
end if;
end if; -- arb_lvl
end if; -- req_n
end loop rob;
-- select new master
if nvalid(0) then -- consider level 0 before wrap
new_request := nmst(0);
owner0v := nmst(0);
-- consider level 1 only once, except when no request in level 0
elsif owner0v /= NB_AGENTS-1 or not nvalid(1) then
if nvalid(2) then -- level 1 before wrap
new_request := nmst(2);
owner0v := NB_AGENTS-1;
owner1v := nmst(2);
elsif nvalid(3) then -- level 1 after wrap
new_request := nmst(3);
owner0v := NB_AGENTS-1;
owner1v := nmst(3);
end if;
elsif nvalid(1) then -- level 0 after wrap
new_request := nmst(1);
owner0v := nmst(1);
end if;
owneri0 <= conv_std_logic_vector(owner0v, ARB_SIZE);
owneri1 <= conv_std_logic_vector(owner1v, ARB_SIZE);
-- rearbitration if any request asserted & different from current owner
if conv_integer(cown) /= new_request then
-- if idle state: turnaround cycle required by PCI standard
cowni <= conv_std_logic_vector(new_request, ARB_SIZE);
touti <= "0000"; -- reset timeout counter
if turn = '0' then
rearbi <= '1'; -- only one re-arbitration
end if;
end if;
elsif frame_n = '1' then
rearbi <= '0';
end if;
-- if frame deasserted, but request asserted: count timeout
if req_n = all_ones then -- no request: prepare timeout counter
touti <= "1111";
elsif frame_n = '1' then -- request, but no transaction
if tout = "1111" then -- timeout expired, re-arbitrate
turni <= '1'; -- remove grant, turnaround cycle
touti <= "0000"; -- next cycle re-arbitrate
else
touti <= tout + 1;
end if;
end if;
grant : for i in 0 to NB_AGENTS-1 loop
if i = conv_integer(cown) and turn = '0' then
gnt_n(i) <= '0';
else
gnt_n(i) <= '1';
end if;
end loop grant;
-- synchronous reset
if rst_n = '0' then
touti <= "0000";
cowni <= (others => '0');
owneri0 <= (others => '0');
owneri1 <= (others => '0');
rearbi <= '0';
turni <= '0';
new_request := 0;
end if;
end process arbiter;
arb_lvl(NB_AGENTS-1) <= '1'; -- always prio 1.
fixed_prios : if not APB_PRIOS generate -- assign constant value
arb_lvl(NB_AGENTS-2 downto 0) <= ARB_LVL_C(NB_AGENTS-2 downto 0);
end generate fixed_prios;
-- Generate APB regs and APB slave
apbgen : if APB_PRIOS generate
-- purpose: APB read and write of arb_lvl configuration registers
-- type: memoryless
-- inputs: pbi, arb_lvl, prst_n
-- outputs: pbo, arb_lvli
config : process (pbi, arb_lvl, prst_n)
begin -- process config
arb_lvli <= arb_lvl;
pbo.PRDATA <= (others => '0'); -- default for unimplemented addresses
-- register select at (byte-) addresses 0x80
if pbi.PADDR(7 downto 0) = "10000000" and pbi.PSEL = '1' then -- address select
if (pbi.PWRITE and pbi.PENABLE) = '1' then -- APB write
arb_lvli <= pbi.PWDATA(NB_AGENTS-1 downto 0);
end if;
pbo.PRDATA(NB_AGENTS-1 downto 0) <= arb_lvl;
end if;
-- synchronous reset
if prst_n = '0' then
arb_lvli <= ARB_LVL_C; -- assign default value
end if;
end process config;
-- APB registers
apb_regs : process (pclk)
begin -- process regs
-- activities triggered by asynchronous reset (active low)
if pclk'event and pclk = '1' then -- '
arb_lvl(NB_AGENTS-2 downto 0) <= arb_lvli(NB_AGENTS-2 downto 0);
end if;
end process apb_regs;
end generate apbgen;
-- PCI registers
regs0 : process (clk)
begin -- process regs
if clk'event and clk = '1' then -- '
tout <= touti;
owner0 <= owneri0;
owner1 <= owneri1;
cown <= cowni;
rearb <= rearbi;
turn <= turni;
end if;
end process regs0;
end rtl;
|
gpl-2.0
|
d62888408f2ff23999078722fb4303af
| 0.540189 | 4.185408 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/alt/adqin.vhd
| 3 | 3,943 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
library altera_mf;
use altera_mf.all;
entity adqin is
port(
clk : in std_logic;
dq_pad : in std_logic; -- DQ pad
dq_h : out std_logic;
dq_l : out std_logic;
config_clk : in std_logic;
config_clken : in std_logic;
config_datain : in std_logic;
config_update : in std_logic
);
end;
architecture rtl of adqin is
component cycloneiii_io_ibuf is
generic (
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
port (
i : in std_logic := '0';
ibar : in std_logic := '0';
o : out std_logic
);
end component;
component altddio_in
generic (
intended_device_family : string;
invert_input_clocks : string;
lpm_type : string;
power_up_high : string;
width : natural
);
port (
datain : in std_logic_vector (0 downto 0);
inclock : in std_logic ;
dataout_h : out std_logic_vector (0 downto 0);
dataout_l : out std_logic_vector (0 downto 0)
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal inputdelay : std_logic_vector(3 downto 0);
signal dq_buf, dq_h_tmp, dq_l_tmp : std_logic_vector(0 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
-- In buffer (DQ) --------------------------------------------------------------------
dq_buf0 : cycloneiii_io_ibuf
generic map(
differential_mode => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_ibuf"
)
port map(
i => dq_pad,
ibar => open,
o => dq_buf(0)
);
-- Input capture register (DQ) -------------------------------------------------------
altddio_in_component : altddio_in
generic map (
intended_device_family => "Cyclone III",
invert_input_clocks => "off",
lpm_type => "altddio_in",
power_up_high => "off",
width => 1
)
port map (
datain => dq_buf,
inclock => clk,
dataout_h => dq_h_tmp,
dataout_l => dq_l_tmp
);
dq_h <= dq_h_tmp(0); dq_l <= dq_l_tmp(0);
-- dq_reg0 : cycloneiii_ddio_in
-- generic map(
-- power_up => "low",
-- async_mode => "clear",
-- sync_mode => "none",
-- use_clkn => "false",
-- lpm_type => "cycloneiii_ddio_in"
-- )
-- port map(
-- datain => dq_dq_buf,
-- clk => clk,
-- clkn => open,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- regoutlo => dq_l,
-- regouthi => dq_h
-- --dfflo : out std_logic;
-- --devclrn : in std_logic := '1';
-- --devpor : in std_logic := '1'
-- );
end;
|
gpl-2.0
|
be66803d43eb22f747beaabdb519c1c8
| 0.378392 | 4.120167 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/can/can.vhd
| 1 | 6,941 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: can
-- File: can.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: CAN component declartions
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package can is
component can_mod
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic;
testen : in std_logic);
end component;
component can_oc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end component;
component can_mc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 2 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
end component;
component can_rd
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end component;
component canmux
port(
sel : in std_logic;
canrx : out std_logic;
cantx : in std_logic;
canrxv : in std_logic_vector(0 to 1);
cantxv : out std_logic_vector(0 to 1)
);
end component;
-----------------------------------------------------------------------------
-- interface type declarations for can controller
-----------------------------------------------------------------------------
type can_in_type is record
rx: std_logic_vector(1 downto 0); -- receive lines
end record;
type can_out_type is record
tx: std_logic_vector(1 downto 0); -- transmit lines
en: std_logic_vector(1 downto 0); -- transmit enables
end record;
-----------------------------------------------------------------------------
-- component declaration for grcan controller
-----------------------------------------------------------------------------
component grcan is
generic (
hindex: integer := 0;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#ffc#;
pirq: integer := 1; -- index of first irq
singleirq: integer := 0; -- single irq output
txchannels: integer range 1 to 1 := 1; -- 1 to 1 channels
rxchannels: integer range 1 to 1 := 1; -- 1 to 1 channels
ptrwidth: integer range 16 to 16 := 16);-- 16 to 64k messages
-- 2k to 8M bits
port (
rstn: in std_ulogic;
clk: in std_ulogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
cani: in can_in_type;
cano: out can_out_type);
end component;
-----------------------------------------------------------------------------
-- component declaration for grhcan controller
-----------------------------------------------------------------------------
component grhcan is
generic (
hindex: integer := 0;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#ffc#;
pirq: integer := 1; -- index of first irq
txchannels: integer range 1 to 1 := 1; -- 1 to 16 channels
rxchannels: integer range 1 to 1 := 1; -- 1 to 16 channels
ptrwidth: integer range 16 to 16 := 16; -- 16 to 64k messages
-- 2k to 8 m bits
singleirq: Integer := 0; -- single irq output
version: Integer := 0); -- 0=516, 1=524
port (
rstn: in std_ulogic;
clk: in std_ulogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
cani: in can_in_type;
cano: out can_out_type);
end component;
end;
|
gpl-2.0
|
ac54eb2d8d16e9e3c713d9e85d2c377a
| 0.476012 | 4.166267 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spictrl.vhd
| 1 | 11,173 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrl
-- File: spictrl.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Wrapper for SPICTRL core
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spictrl is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0; -- APB address
pmask : integer := 16#fff#; -- APB mask
pirq : integer := 0; -- interrupt index
-- SPI controller configuration
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0; -- Output enable polarity
odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
-- set if pads are i/o or od pads.
automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
twen : integer range 0 to 1 := 1; -- Enable three wire mode
maxwlen : integer range 0 to 15 := 0; -- Maximum word length
netlist : integer := 0; -- Use netlist (tech)
syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
memtech : integer := 0; -- Memory technology
ft : integer range 0 to 2 := 0; -- Fault-Tolerance
scantest : integer range 0 to 1 := 0; -- Scan test support
syncrst : integer range 0 to 1 := 0; -- Use only sync reset
automask0 : integer := 0; -- Mask 0 for automated transfers
automask1 : integer := 0; -- Mask 1 for automated transfers
automask2 : integer := 0; -- Mask 2 for automated transfers
automask3 : integer := 0; -- Mask 3 for automated transfers
ignore : integer range 0 to 1 := 0 -- Ignore samples
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end entity spictrl;
architecture rtl of spictrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant SPICTRL_REV : integer := 5;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPICTRL, 0, SPICTRL_REV, pirq),
1 => apb_iobar(paddr, pmask));
-----------------------------------------------------------------------------
-- Component
-----------------------------------------------------------------------------
component spictrlx
generic (
rev : integer := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
syncram : integer range 0 to 1 := 1;
memtech : integer range 0 to NTECH := 0;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0;
ignore : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spii_ignore : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal apbo_pirq : std_ulogic;
begin
ctrl_rtl : if netlist = 0 generate
rtlc : spictrlx
generic map (
rev => SPICTRL_REV,
fdepth => fdepth,
slvselen => slvselen,
slvselsz => slvselsz,
oepol => oepol,
odmode => odmode,
automode => automode,
acntbits => acntbits,
aslvsel => aslvsel,
twen => twen,
maxwlen => maxwlen,
syncram => syncram,
memtech => memtech,
ft => ft,
scantest => scantest,
syncrst => syncrst,
automask0 => automask0,
automask1 => automask1,
automask2 => automask2,
automask3 => automask3,
ignore => ignore)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi.psel(pindex),
apbi_penable => apbi.penable,
apbi_paddr => apbi.paddr,
apbi_pwrite => apbi.pwrite,
apbi_pwdata => apbi.pwdata,
apbi_testen => apbi.testen,
apbi_testrst => apbi.testrst,
apbi_scanen => apbi.scanen,
apbi_testoen => apbi.testoen,
apbo_prdata => apbo.prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii.miso,
spii_mosi => spii.mosi,
spii_sck => spii.sck,
spii_spisel => spii.spisel,
spii_astart => spii.astart,
spii_cstart => spii.cstart,
spii_ignore => spii.ignore,
spio_miso => spio.miso,
spio_misooen => spio.misooen,
spio_mosi => spio.mosi,
spio_mosioen => spio.mosioen,
spio_sck => spio.sck,
spio_sckoen => spio.sckoen,
spio_enable => spio.enable,
spio_astart => spio.astart,
spio_aready => spio.aready,
slvsel => slvsel);
end generate ctrl_rtl;
ctrl_netlist : if netlist /= 0 generate
netlc : spictrl_net
generic map (
tech => netlist,
fdepth => fdepth,
slvselen => slvselen,
slvselsz => slvselsz,
oepol => oepol,
odmode => odmode,
automode => automode,
acntbits => acntbits,
aslvsel => aslvsel,
twen => twen,
maxwlen => maxwlen,
automask0 => automask0,
automask1 => automask1,
automask2 => automask2,
automask3 => automask3)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi.psel(pindex),
apbi_penable => apbi.penable,
apbi_paddr => apbi.paddr,
apbi_pwrite => apbi.pwrite,
apbi_pwdata => apbi.pwdata,
apbi_testen => apbi.testen,
apbi_testrst => apbi.testrst,
apbi_scanen => apbi.scanen,
apbi_testoen => apbi.testoen,
apbo_prdata => apbo.prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii.miso,
spii_mosi => spii.mosi,
spii_sck => spii.sck,
spii_spisel => spii.spisel,
spii_astart => spii.astart,
spii_cstart => spii.cstart,
spio_miso => spio.miso,
spio_misooen => spio.misooen,
spio_mosi => spio.mosi,
spio_mosioen => spio.mosioen,
spio_sck => spio.sck,
spio_sckoen => spio.sckoen,
spio_enable => spio.enable,
spio_astart => spio.astart,
spio_aready => spio.aready,
slvsel => slvsel);
end generate ctrl_netlist;
spio.ssn <= (others => '0');
irqgen : process(apbo_pirq)
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
irq := (others => '0'); irq(pirq) := apbo_pirq;
apbo.pirq <= irq;
end process;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spictrl" & tost(pindex) & ": SPI controller, rev " &
tost(SPICTRL_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
gpl-2.0
|
fb7c1ceda01a2a6978a5d2b72710f6d6
| 0.51168 | 4.158169 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/amba/devices.vhd
| 1 | 45,095 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Cobham Gaisler AB
-- Description: Vendor and devices IDs for AMBA plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices is
-- Vendor codes
constant VENDOR_RESERVED : amba_vendor_type := 16#00#; -- Do not use!
constant VENDOR_GAISLER : amba_vendor_type := 16#01#;
constant VENDOR_PENDER : amba_vendor_type := 16#02#;
constant VENDOR_ESA : amba_vendor_type := 16#04#;
constant VENDOR_ASTRIUM : amba_vendor_type := 16#06#;
constant VENDOR_OPENCHIP : amba_vendor_type := 16#07#;
constant VENDOR_OPENCORES : amba_vendor_type := 16#08#;
constant VENDOR_CONTRIB : amba_vendor_type := 16#09#;
constant VENDOR_DLR : amba_vendor_type := 16#0A#;
constant VENDOR_EONIC : amba_vendor_type := 16#0B#;
constant VENDOR_TELECOMPT : amba_vendor_type := 16#0C#;
constant VENDOR_DTU : amba_vendor_type := 16#0D#;
constant VENDOR_BSC : amba_vendor_type := 16#0E#;
constant VENDOR_RADIONOR : amba_vendor_type := 16#0F#;
constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#;
constant VENDOR_MENTA : amba_vendor_type := 16#11#;
constant VENDOR_SUN : amba_vendor_type := 16#13#;
constant VENDOR_MOVIDIA : amba_vendor_type := 16#14#;
constant VENDOR_ORBITA : amba_vendor_type := 16#17#;
constant VENDOR_SYNOPSYS : amba_vendor_type := 16#21#;
constant VENDOR_NASA : amba_vendor_type := 16#22#;
constant VENDOR_S3 : amba_vendor_type := 16#31#;
constant VENDOR_ACTEL : amba_vendor_type := 16#AC#;
constant VENDOR_APPLECORE : amba_vendor_type := 16#AE#;
constant VENDOR_C3E : amba_vendor_type := 16#C3#;
constant VENDOR_CBKPAN : amba_vendor_type := 16#C8#;
constant VENDOR_CAL : amba_vendor_type := 16#CA#;
constant VENDOR_CETON : amba_vendor_type := 16#CB#;
constant VENDOR_EMBEDDIT : amba_vendor_type := 16#EA#;
-- Cobham Gaisler device ids
constant GAISLER_LEON2DSU : amba_device_type := 16#002#;
constant GAISLER_LEON3 : amba_device_type := 16#003#;
constant GAISLER_LEON3DSU : amba_device_type := 16#004#;
constant GAISLER_ETHAHB : amba_device_type := 16#005#;
constant GAISLER_APBMST : amba_device_type := 16#006#;
constant GAISLER_AHBUART : amba_device_type := 16#007#;
constant GAISLER_SRCTRL : amba_device_type := 16#008#;
constant GAISLER_SDCTRL : amba_device_type := 16#009#;
constant GAISLER_SSRCTRL : amba_device_type := 16#00A#;
constant GAISLER_I2C2AHB : amba_device_type := 16#00B#;
constant GAISLER_APBUART : amba_device_type := 16#00C#;
constant GAISLER_IRQMP : amba_device_type := 16#00D#;
constant GAISLER_AHBRAM : amba_device_type := 16#00E#;
constant GAISLER_AHBDPRAM : amba_device_type := 16#00F#;
constant GAISLER_GRIOMMU2 : amba_device_type := 16#010#;
constant GAISLER_GPTIMER : amba_device_type := 16#011#;
constant GAISLER_PCITRG : amba_device_type := 16#012#;
constant GAISLER_PCISBRG : amba_device_type := 16#013#;
constant GAISLER_PCIFBRG : amba_device_type := 16#014#;
constant GAISLER_PCITRACE : amba_device_type := 16#015#;
constant GAISLER_DMACTRL : amba_device_type := 16#016#;
constant GAISLER_AHBTRACE : amba_device_type := 16#017#;
constant GAISLER_DSUCTRL : amba_device_type := 16#018#;
constant GAISLER_CANAHB : amba_device_type := 16#019#;
constant GAISLER_GPIO : amba_device_type := 16#01A#;
constant GAISLER_AHBROM : amba_device_type := 16#01B#;
constant GAISLER_AHBJTAG : amba_device_type := 16#01C#;
constant GAISLER_ETHMAC : amba_device_type := 16#01D#;
constant GAISLER_SWNODE : amba_device_type := 16#01E#;
constant GAISLER_SPW : amba_device_type := 16#01F#;
constant GAISLER_AHB2AHB : amba_device_type := 16#020#;
constant GAISLER_USBDC : amba_device_type := 16#021#;
constant GAISLER_USB_DCL : amba_device_type := 16#022#;
constant GAISLER_DDRMP : amba_device_type := 16#023#;
constant GAISLER_ATACTRL : amba_device_type := 16#024#;
constant GAISLER_DDRSP : amba_device_type := 16#025#;
constant GAISLER_EHCI : amba_device_type := 16#026#;
constant GAISLER_UHCI : amba_device_type := 16#027#;
constant GAISLER_I2CMST : amba_device_type := 16#028#;
constant GAISLER_SPW2 : amba_device_type := 16#029#;
constant GAISLER_AHBDMA : amba_device_type := 16#02A#;
constant GAISLER_NUHOSP3 : amba_device_type := 16#02B#;
constant GAISLER_CLKGATE : amba_device_type := 16#02C#;
constant GAISLER_SPICTRL : amba_device_type := 16#02D#;
constant GAISLER_DDR2SP : amba_device_type := 16#02E#;
constant GAISLER_SLINK : amba_device_type := 16#02F#;
constant GAISLER_GRTM : amba_device_type := 16#030#;
constant GAISLER_GRTC : amba_device_type := 16#031#;
constant GAISLER_GRPW : amba_device_type := 16#032#;
constant GAISLER_GRCTM : amba_device_type := 16#033#;
constant GAISLER_GRHCAN : amba_device_type := 16#034#;
constant GAISLER_GRFIFO : amba_device_type := 16#035#;
constant GAISLER_GRADCDAC : amba_device_type := 16#036#;
constant GAISLER_GRPULSE : amba_device_type := 16#037#;
constant GAISLER_GRTIMER : amba_device_type := 16#038#;
constant GAISLER_AHB2PP : amba_device_type := 16#039#;
constant GAISLER_GRVERSION : amba_device_type := 16#03A#;
constant GAISLER_APB2PW : amba_device_type := 16#03B#;
constant GAISLER_PW2APB : amba_device_type := 16#03C#;
constant GAISLER_GRCAN : amba_device_type := 16#03D#;
constant GAISLER_I2CSLV : amba_device_type := 16#03E#;
constant GAISLER_U16550 : amba_device_type := 16#03F#;
constant GAISLER_AHBMST_EM : amba_device_type := 16#040#;
constant GAISLER_AHBSLV_EM : amba_device_type := 16#041#;
constant GAISLER_GRTESTMOD : amba_device_type := 16#042#;
constant GAISLER_ASCS : amba_device_type := 16#043#;
constant GAISLER_IPMVBCTRL : amba_device_type := 16#044#;
constant GAISLER_SPIMCTRL : amba_device_type := 16#045#;
constant GAISLER_L4STAT : amba_device_type := 16#047#;
constant GAISLER_LEON4 : amba_device_type := 16#048#;
constant GAISLER_LEON4DSU : amba_device_type := 16#049#;
constant GAISLER_PWM : amba_device_type := 16#04A#;
constant GAISLER_L2CACHE : amba_device_type := 16#04B#;
constant GAISLER_SDCTRL64 : amba_device_type := 16#04C#;
constant GAISLER_GR1553B : amba_device_type := 16#04D#;
constant GAISLER_1553TST : amba_device_type := 16#04E#;
constant GAISLER_GRIOMMU : amba_device_type := 16#04F#;
constant GAISLER_FTAHBRAM : amba_device_type := 16#050#;
constant GAISLER_FTSRCTRL : amba_device_type := 16#051#;
constant GAISLER_AHBSTAT : amba_device_type := 16#052#;
constant GAISLER_LEON3FT : amba_device_type := 16#053#;
constant GAISLER_FTMCTRL : amba_device_type := 16#054#;
constant GAISLER_FTSDCTRL : amba_device_type := 16#055#;
constant GAISLER_FTSRCTRL8 : amba_device_type := 16#056#;
constant GAISLER_MEMSCRUB : amba_device_type := 16#057#;
constant GAISLER_FTSDCTRL64: amba_device_type := 16#058#;
constant GAISLER_NANDFCTRL : amba_device_type := 16#059#;
constant GAISLER_N2DLLCTRL : amba_device_type := 16#05A#;
constant GAISLER_N2PLLCTRL : amba_device_type := 16#05B#;
constant GAISLER_SPI2AHB : amba_device_type := 16#05C#;
constant GAISLER_DDRSDMUX : amba_device_type := 16#05D#;
constant GAISLER_AHBFROM : amba_device_type := 16#05E#;
constant GAISLER_PCIEXP : amba_device_type := 16#05F#;
constant GAISLER_APBPS2 : amba_device_type := 16#060#;
constant GAISLER_VGACTRL : amba_device_type := 16#061#;
constant GAISLER_LOGAN : amba_device_type := 16#062#;
constant GAISLER_SVGACTRL : amba_device_type := 16#063#;
constant GAISLER_T1AHB : amba_device_type := 16#064#;
constant GAISLER_MP7WRAP : amba_device_type := 16#065#;
constant GAISLER_GRSYSMON : amba_device_type := 16#066#;
constant GAISLER_GRACECTRL : amba_device_type := 16#067#;
constant GAISLER_ATAHBSLV : amba_device_type := 16#068#;
constant GAISLER_ATAHBMST : amba_device_type := 16#069#;
constant GAISLER_ATAPBSLV : amba_device_type := 16#06A#;
constant GAISLER_MIGDDR2 : amba_device_type := 16#06B#;
constant GAISLER_LCDCTRL : amba_device_type := 16#06C#;
constant GAISLER_SWITCHOVER: amba_device_type := 16#06D#;
constant GAISLER_FIFOUART : amba_device_type := 16#06E#;
constant GAISLER_MUXCTRL : amba_device_type := 16#06F#;
constant GAISLER_B1553BC : amba_device_type := 16#070#;
constant GAISLER_B1553RT : amba_device_type := 16#071#;
constant GAISLER_B1553BRM : amba_device_type := 16#072#;
constant GAISLER_AES : amba_device_type := 16#073#;
constant GAISLER_ECC : amba_device_type := 16#074#;
constant GAISLER_PCIF : amba_device_type := 16#075#;
constant GAISLER_CLKMOD : amba_device_type := 16#076#;
constant GAISLER_HAPSTRAK : amba_device_type := 16#077#;
constant GAISLER_TEST_1X2 : amba_device_type := 16#078#;
constant GAISLER_WILD2AHB : amba_device_type := 16#079#;
constant GAISLER_BIO1 : amba_device_type := 16#07A#;
constant GAISLER_AESDMA : amba_device_type := 16#07B#;
constant GAISLER_GRPCI2 : amba_device_type := 16#07C#;
constant GAISLER_GRPCI2_DMA: amba_device_type := 16#07D#;
constant GAISLER_GRPCI2_TB : amba_device_type := 16#07E#;
constant GAISLER_MMA : amba_device_type := 16#07F#;
constant GAISLER_SATCAN : amba_device_type := 16#080#;
constant GAISLER_CANMUX : amba_device_type := 16#081#;
constant GAISLER_GRTMRX : amba_device_type := 16#082#;
constant GAISLER_GRTCTX : amba_device_type := 16#083#;
constant GAISLER_GRTMDESC : amba_device_type := 16#084#;
constant GAISLER_GRTMVC : amba_device_type := 16#085#;
constant GAISLER_GEFFE : amba_device_type := 16#086#;
constant GAISLER_GPREG : amba_device_type := 16#087#;
constant GAISLER_GRTMPAHB : amba_device_type := 16#088#;
constant GAISLER_SPWCUC : amba_device_type := 16#089#;
constant GAISLER_SPW2_DMA : amba_device_type := 16#08A#;
constant GAISLER_SPWROUTER : amba_device_type := 16#08B#;
constant GAISLER_EDCLMST : amba_device_type := 16#08C#;
constant GAISLER_GRPWTX : amba_device_type := 16#08D#;
constant GAISLER_GRPWRX : amba_device_type := 16#08E#;
constant GAISLER_GPREGBANK : amba_device_type := 16#08F#;
constant GAISLER_MIG_7SERIES : amba_device_type := 16#090#;
constant GAISLER_GRSPW2_SIST : amba_device_type := 16#091#;
constant GAISLER_SGMII : amba_device_type := 16#092#;
constant GAISLER_RGMII : amba_device_type := 16#093#;
constant GAISLER_IRQGEN : amba_device_type := 16#094#;
constant GAISLER_GRDMAC : amba_device_type := 16#095#;
constant GAISLER_AHB2AVLA : amba_device_type := 16#096#;
constant GAISLER_SPWTDP : amba_device_type := 16#097#;
constant GAISLER_L3STAT : amba_device_type := 16#098#;
constant GAISLER_GR740THS : amba_device_type := 16#099#;
constant GAISLER_GRRM : amba_device_type := 16#09A#;
constant GAISLER_CMAP : amba_device_type := 16#09B#;
constant GAISLER_CPGEN : amba_device_type := 16#09C#;
constant GAISLER_AMBAPROT : amba_device_type := 16#09D#;
constant GAISLER_IGLOO2_BRIDGE : amba_device_type := 16#09E#;
constant GAISLER_AHB2AXI : amba_device_type := 16#09F#;
constant GAISLER_AXI2AHB : amba_device_type := 16#0A0#;
-- Sun Microsystems
constant SUN_T1 : amba_device_type := 16#001#;
constant SUN_S1 : amba_device_type := 16#011#;
-- Caltech
constant CAL_DDRCTRL : amba_device_type := 16#188#;
-- CBK PAN
constant CBKPAN_FTNANDCTRL : amba_device_type := 16#001#;
constant CBKPAN_FTEEPROMCTRL : amba_device_type := 16#002#;
constant CBKPAN_FTSDCTRL16 : amba_device_type := 16#003#;
constant CBKPAN_STIXCTRL : amba_device_type := 16#300#;
-- European Space Agency device ids
constant ESA_LEON2 : amba_device_type := 16#002#;
constant ESA_LEON2APB : amba_device_type := 16#003#;
constant ESA_IRQ : amba_device_type := 16#005#;
constant ESA_TIMER : amba_device_type := 16#006#;
constant ESA_UART : amba_device_type := 16#007#;
constant ESA_CFG : amba_device_type := 16#008#;
constant ESA_IO : amba_device_type := 16#009#;
constant ESA_MCTRL : amba_device_type := 16#00F#;
constant ESA_PCIARB : amba_device_type := 16#010#;
constant ESA_HURRICANE : amba_device_type := 16#011#;
constant ESA_SPW_RMAP : amba_device_type := 16#012#;
constant ESA_AHBUART : amba_device_type := 16#013#;
constant ESA_SPWA : amba_device_type := 16#014#;
constant ESA_BOSCHCAN : amba_device_type := 16#015#;
constant ESA_IRQ2 : amba_device_type := 16#016#;
constant ESA_AHBSTAT : amba_device_type := 16#017#;
constant ESA_WPROT : amba_device_type := 16#018#;
constant ESA_WPROT2 : amba_device_type := 16#019#;
constant ESA_PDEC3AMBA : amba_device_type := 16#020#;
constant ESA_PTME3AMBA : amba_device_type := 16#021#;
-- OpenChip IDs
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- Gleichmann's device ids
constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#;
constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#;
constant GLEICHMANN_DAC : amba_device_type := 16#003#;
constant GLEICHMANN_HPI : amba_device_type := 16#004#;
constant GLEICHMANN_SPI : amba_device_type := 16#005#;
constant GLEICHMANN_HIFC : amba_device_type := 16#006#;
constant GLEICHMANN_ADCDAC : amba_device_type := 16#007#;
constant GLEICHMANN_SPIOC : amba_device_type := 16#008#;
constant GLEICHMANN_AC97 : amba_device_type := 16#009#;
-- MENTA device ids
constant MENTA_EFPGA_IP : amba_device_type := 16#002#;
-- DTU device ids
constant DTU_IV : amba_device_type := 16#001#;
constant DTU_RBMMTRANS : amba_device_type := 16#002#;
constant DTU_FTMCTRL : amba_device_type := 16#054#;
-- BSC device ids
constant BSC_CORE1 : amba_device_type := 16#001#;
constant BSC_CORE2 : amba_device_type := 16#002#;
-- Orbita device ids
constant ORBITA_1553B : amba_device_type := 16#001#;
constant ORBITA_429 : amba_device_type := 16#002#;
constant ORBITA_SPI : amba_device_type := 16#003#;
constant ORBITA_I2C : amba_device_type := 16#004#;
constant ORBITA_SMARTCARD : amba_device_type := 16#064#;
constant ORBITA_SDCARD : amba_device_type := 16#065#;
constant ORBITA_UART16550 : amba_device_type := 16#066#;
constant ORBITA_CRYPTO : amba_device_type := 16#067#;
constant ORBITA_SYSIF : amba_device_type := 16#068#;
constant ORBITA_PIO : amba_device_type := 16#069#;
constant ORBITA_RTC : amba_device_type := 16#0C8#;
constant ORBITA_COLORLCD : amba_device_type := 16#12C#;
constant ORBITA_PCI : amba_device_type := 16#190#;
constant ORBITA_DSP : amba_device_type := 16#1F4#;
constant ORBITA_USBHOST : amba_device_type := 16#258#;
constant ORBITA_USBDEV : amba_device_type := 16#2BC#;
-- Actel device ids
constant ACTEL_COREMP7 : amba_device_type := 16#001#;
-- NASA device ids
constant NASA_EP32 : amba_device_type := 16#001#;
-- AppleCore device ids
constant APPLECORE_UTLEON3 : amba_device_type := 16#001#;
constant APPLECORE_UTLEON3DSU : amba_device_type := 16#002#;
constant APPLECORE_APBPERFCNT : amba_device_type := 16#003#;
-- Contribution library IDs
constant CONTRIB_CORE1 : amba_device_type := 16#001#;
constant CONTRIB_CORE2 : amba_device_type := 16#002#;
-- grlib system device ids
subtype system_device_type is integer range 0 to 16#ffff#;
constant LEON3_ACT_FUSION : system_device_type := 16#0105#;
constant LEON3_RTAX_CID1 : system_device_type := 16#0201#;
constant LEON3_RTAX_CID2 : system_device_type := 16#0202#;
constant LEON3_RTAX_CID3 : system_device_type := 16#0203#;
constant LEON3_RTAX_CID4 : system_device_type := 16#0204#;
constant LEON3_RTAX_CID5 : system_device_type := 16#0205#;
constant LEON3_RTAX_CID6 : system_device_type := 16#0206#;
constant LEON3_RTAX_CID7 : system_device_type := 16#0207#;
constant LEON3_RTAX_CID8 : system_device_type := 16#0208#;
constant LEON3_PROXIMA : system_device_type := 16#0252#;
constant ALTERA_DE2 : system_device_type := 16#0302#;
constant ALTERA_DE4 : system_device_type := 16#0303#;
constant XILINX_ML401 : system_device_type := 16#0401#;
constant LEON3FT_GRXC4V : system_device_type := 16#0453#;
constant XILINX_ML501 : system_device_type := 16#0501#;
constant XILINX_ML505 : system_device_type := 16#0505#;
constant XILINX_ML506 : system_device_type := 16#0506#;
constant XILINX_ML507 : system_device_type := 16#0507#;
constant XILINX_ML509 : system_device_type := 16#0509#;
constant XILINX_ML510 : system_device_type := 16#0510#;
constant MICROSEMI_M2GL_EVAL : system_device_type := 16#0560#;
constant XILINX_SP601 : system_device_type := 16#0601#;
constant XILINX_ML605 : system_device_type := 16#0605#;
-- pragma translate_off
constant GAISLER_DESC : vendor_description := "Cobham Gaisler ";
constant gaisler_device_table : device_table_type := (
GAISLER_LEON2DSU => "LEON2 Debug Support Unit ",
GAISLER_LEON3 => "LEON3 SPARC V8 Processor ",
GAISLER_LEON3DSU => "LEON3 Debug Support Unit ",
GAISLER_ETHAHB => "OC ethernet AHB interface ",
GAISLER_AHBRAM => "Single-port AHB SRAM module ",
GAISLER_AHBDPRAM => "Dual-port AHB SRAM module ",
GAISLER_APBMST => "AHB/APB Bridge ",
GAISLER_AHBUART => "AHB Debug UART ",
GAISLER_SRCTRL => "Simple SRAM Controller ",
GAISLER_SDCTRL => "PC133 SDRAM Controller ",
GAISLER_SSRCTRL => "Synchronous SRAM Controller ",
GAISLER_APBUART => "Generic UART ",
GAISLER_IRQMP => "Multi-processor Interrupt Ctrl.",
GAISLER_GPTIMER => "Modular Timer Unit ",
GAISLER_PCITRG => "Simple 32-bit PCI Target ",
GAISLER_PCISBRG => "Simple 32-bit PCI Bridge ",
GAISLER_PCIFBRG => "Fast 32-bit PCI Bridge ",
GAISLER_PCITRACE => "32-bit PCI Trace Buffer ",
GAISLER_DMACTRL => "PCI/AHB DMA controller ",
GAISLER_AHBTRACE => "AMBA Trace Buffer ",
GAISLER_DSUCTRL => "DSU/ETH controller ",
GAISLER_GRTM => "CCSDS Telemetry Encoder ",
GAISLER_GRTC => "CCSDS Telecommand Decoder ",
GAISLER_GRPW => "PacketWire to AMBA AHB I/F ",
GAISLER_GRCTM => "CCSDS Time Manager ",
GAISLER_GRHCAN => "ESA HurriCANe CAN with DMA ",
GAISLER_GRFIFO => "FIFO Controller ",
GAISLER_GRADCDAC => "ADC / DAC Interface ",
GAISLER_GRPULSE => "General Purpose I/O with Pulses",
GAISLER_GRTIMER => "Timer Unit with Latches ",
GAISLER_AHB2PP => "AMBA AHB to Packet Parallel I/F",
GAISLER_GRVERSION => "Version and Revision Register ",
GAISLER_APB2PW => "PacketWire Transmit Interface ",
GAISLER_PW2APB => "PacketWire Receive Interface ",
GAISLER_GRCAN => "CAN Controller with DMA ",
GAISLER_AHBMST_EM => "AMBA Master Emulator ",
GAISLER_AHBSLV_EM => "AMBA Slave Emulator ",
GAISLER_CANAHB => "OC CAN AHB interface ",
GAISLER_GPIO => "General Purpose I/O port ",
GAISLER_AHBROM => "Generic AHB ROM ",
GAISLER_AHB2AHB => "AHB-to-AHB Bridge ",
GAISLER_AHBDMA => "Simple AHB DMA controller ",
GAISLER_NUHOSP3 => "Nuhorizons Spartan3 IO I/F ",
GAISLER_CLKGATE => "Clock gating unit ",
GAISLER_FTAHBRAM => "Generic FT AHB SRAM module ",
GAISLER_FTSRCTRL => "Simple FT SRAM Controller ",
GAISLER_LEON3FT => "LEON3-FT SPARC V8 Processor ",
GAISLER_FTMCTRL => "Memory controller with EDAC ",
GAISLER_FTSDCTRL => "FT PC133 SDRAM Controller ",
GAISLER_FTSRCTRL8 => "FT 8-bit SRAM/16-bit IO Ctrl ",
GAISLER_FTSDCTRL64=> "64-bit FT SDRAM Controller ",
GAISLER_AHBSTAT => "AHB Status Register ",
GAISLER_AHBJTAG => "JTAG Debug Link ",
GAISLER_ETHMAC => "GR Ethernet MAC ",
GAISLER_SWNODE => "SpaceWire Node Interface ",
GAISLER_SPW => "SpaceWire Serial Link ",
GAISLER_VGACTRL => "VGA controller ",
GAISLER_APBPS2 => "PS2 interface ",
GAISLER_LOGAN => "On chip Logic Analyzer ",
GAISLER_SVGACTRL => "SVGA frame buffer ",
GAISLER_T1AHB => "Niagara T1 PCX/AHB bridge ",
GAISLER_B1553BC => "AMBA Wrapper for Core1553BBC ",
GAISLER_B1553RT => "AMBA Wrapper for Core1553BRT ",
GAISLER_B1553BRM => "AMBA Wrapper for Core1553BRM ",
GAISLER_SATCAN => "SatCAN controller ",
GAISLER_CANMUX => "CAN Bus multiplexer ",
GAISLER_GRTMRX => "CCSDS Telemetry Receiver ",
GAISLER_GRTCTX => "CCSDS Telecommand Transmitter ",
GAISLER_GRTMDESC => "CCSDS Telemetry Descriptor ",
GAISLER_GRTMVC => "CCSDS Telemetry VC Generator ",
GAISLER_GRTMPAHB => "CCSDS Telemetry VC AHB Input ",
GAISLER_GEFFE => "Geffe Generator ",
GAISLER_SPWCUC => "CCSDS CUC / SpaceWire I/F ",
GAISLER_GPREG => "General Purpose Register ",
GAISLER_AES => "Advanced Encryption Standard ",
GAISLER_AESDMA => "AES 256 DMA ",
GAISLER_GRPCI2 => "GRPCI2 PCI/AHB bridge ",
GAISLER_GRPCI2_DMA=> "GRPCI2 DMA interface ",
GAISLER_GRPCI2_TB => "GRPCI2 Trace buffer ",
GAISLER_MMA => "Memory Mapped AMBA ",
GAISLER_ECC => "Elliptic Curve Cryptography ",
GAISLER_PCIF => "AMBA Wrapper for CorePCIF ",
GAISLER_USBDC => "GR USB 2.0 Device Controller ",
GAISLER_USB_DCL => "USB Debug Communication Link ",
GAISLER_DDRMP => "Multi-port DDR controller ",
GAISLER_ATACTRL => "ATA controller ",
GAISLER_DDRSP => "Single-port DDR266 controller ",
GAISLER_EHCI => "USB Enhanced Host Controller ",
GAISLER_UHCI => "USB Universal Host Controller ",
GAISLER_I2CMST => "AMBA Wrapper for OC I2C-master ",
GAISLER_I2CSLV => "I2C Slave ",
GAISLER_U16550 => "Simple 16550 UART ",
GAISLER_SPICTRL => "SPI Controller ",
GAISLER_DDR2SP => "Single-port DDR2 controller ",
GAISLER_GRTESTMOD => "Test report module ",
GAISLER_CLKMOD => "CPU Clock Switching Ctrl module",
GAISLER_SLINK => "SLINK Master ",
GAISLER_HAPSTRAK => "HAPS HapsTrak I/O Port ",
GAISLER_TEST_1X2 => "HAPS TEST_1x2 interface ",
GAISLER_WILD2AHB => "WildCard CardBus interface ",
GAISLER_BIO1 => "Basic I/O board BIO1 ",
GAISLER_ASCS => "ASCS Master ",
GAISLER_SPW2 => "GRSPW2 SpaceWire Serial Link ",
GAISLER_IPMVBCTRL => "IPM-bus/MVBC memory controller ",
GAISLER_SPIMCTRL => "SPI Memory Controller ",
GAISLER_L4STAT => "LEON4 Statistics Unit ",
GAISLER_LEON4 => "LEON4 SPARC V8 Processor ",
GAISLER_LEON4DSU => "LEON4 Debug Support Unit ",
GAISLER_PWM => "PWM generator ",
GAISLER_L2CACHE => "L2-Cache Controller ",
GAISLER_SDCTRL64 => "64-bit PC133 SDRAM Controller ",
GAISLER_MP7WRAP => "CoreMP7 wrapper ",
GAISLER_GRSYSMON => "AMBA wrapper for System Monitor",
GAISLER_GRACECTRL => "System ACE I/F Controller ",
GAISLER_ATAHBSLV => "AMBA Test Framework AHB Slave ",
GAISLER_ATAHBMST => "AMBA Test Framework AHB Master ",
GAISLER_ATAPBSLV => "AMBA Test Framework APB Slave ",
GAISLER_MIGDDR2 => "Xilinx MIG DDR2 Controller ",
GAISLER_LCDCTRL => "LCD Controller ",
GAISLER_SWITCHOVER=> "Switchover Logic ",
GAISLER_FIFOUART => "UART with large FIFO ",
GAISLER_MUXCTRL => "Analogue multiplexer control ",
GAISLER_GR1553B => "MIL-STD-1553B Interface ",
GAISLER_1553TST => "MIL-STD-1553B Test Device ",
GAISLER_MEMSCRUB => "AHB Memory Scrubber ",
GAISLER_GRIOMMU => "IO Memory Management Unit ",
GAISLER_SPW2_DMA => "GRSPW Router DMA interface ",
GAISLER_SPWROUTER => "GRSPW Router ",
GAISLER_EDCLMST => "EDCL master interface ",
GAISLER_GRPWTX => "PacketWire Transmitter with DMA",
GAISLER_GRPWRX => "PacketWire Receiver with DMA ",
GAISLER_GRIOMMU2 => "IOMMU secondary master i/f ",
GAISLER_I2C2AHB => "I2C to AHB Bridge ",
GAISLER_NANDFCTRL => "NAND Flash Controller ",
GAISLER_N2PLLCTRL => "N2X PLL Dynamic Config. i/f ",
GAISLER_N2DLLCTRL => "N2X DLL Dynamic Config. i/f ",
GAISLER_GPREGBANK => "General Purpose Register Bank ",
GAISLER_SPI2AHB => "SPI to AHB Bridge ",
GAISLER_DDRSDMUX => "Muxed FT DDR/SDRAM controller ",
GAISLER_AHBFROM => "Flash ROM Memory ",
GAISLER_PCIEXP => "Xilinx PCI EXPRESS Wrapper ",
GAISLER_MIG_7SERIES => "Xilinx MIG DDR3 Controller ",
GAISLER_GRSPW2_SIST => "GRSPW Router SIST ",
GAISLER_SGMII => "XILINX SGMII Interface ",
GAISLER_RGMII => "Gaisler RGMII Interface ",
GAISLER_IRQGEN => "Interrupt generator ",
GAISLER_GRDMAC => "DMA Controller with APB bridge ",
GAISLER_AHB2AVLA => "Avalon-MM memory controller ",
GAISLER_SPWTDP => "CCSDS TDP / SpaceWire I/F ",
GAISLER_L3STAT => "LEON3 Statistics Unit ",
GAISLER_GR740THS => "Temperature sensor ",
GAISLER_GRRM => "Reconfiguration Module ",
GAISLER_CMAP => "CCSDS Memory Access Protocol ",
GAISLER_CPGEN => "Discrete Command Pulse Gen ",
GAISLER_AMBAPROT => "AMBA Protection Unit ",
GAISLER_IGLOO2_BRIDGE => "Microsemi IGLOO2 HPMS Wrapper ",
GAISLER_AHB2AXI => "AMBA AHB/AXI Bridge ",
GAISLER_AXI2AHB => "AMBA AXI/AHB Bridge ",
others => "Unknown Device ");
constant gaisler_lib : vendor_library_type := (
vendorid => VENDOR_GAISLER,
vendordesc => GAISLER_DESC,
device_table => gaisler_device_table
);
constant ESA_DESC : vendor_description := "European Space Agency ";
constant esa_device_table : device_table_type := (
ESA_LEON2 => "LEON2 SPARC V8 Processor ",
ESA_LEON2APB => "LEON2 Peripheral Bus ",
ESA_IRQ => "LEON2 Interrupt Controller ",
ESA_TIMER => "LEON2 Timer ",
ESA_UART => "LEON2 UART ",
ESA_CFG => "LEON2 Configuration Register ",
ESA_IO => "LEON2 Input/Output ",
ESA_MCTRL => "LEON2 Memory Controller ",
ESA_PCIARB => "PCI Arbiter ",
ESA_HURRICANE => "HurriCANe/HurryAMBA CAN Ctrl ",
ESA_SPW_RMAP => "UoD/Saab SpaceWire/RMAP link ",
ESA_AHBUART => "LEON2 AHB Debug UART ",
ESA_SPWA => "ESA/ASTRIUM SpaceWire link ",
ESA_BOSCHCAN => "SSC/BOSCH CAN Ctrl ",
ESA_IRQ2 => "LEON2 Secondary Irq Controller ",
ESA_AHBSTAT => "LEON2 AHB Status Register ",
ESA_WPROT => "LEON2 Write Protection ",
ESA_WPROT2 => "LEON2 Extended Write Protection",
ESA_PDEC3AMBA => "ESA CCSDS PDEC3AMBA TC Decoder ",
ESA_PTME3AMBA => "ESA CCSDS PTME3AMBA TM Encoder ",
others => "Unknown Device ");
constant esa_lib : vendor_library_type := (
vendorid => VENDOR_ESA,
vendordesc => ESA_DESC,
device_table => esa_device_table
);
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
constant GLEICHMANN_DESC : vendor_description := "Gleichmann Electronics ";
constant gleichmann_device_table : device_table_type := (
GLEICHMANN_CUSTOM => "Custom device ",
GLEICHMANN_GEOLCD01 => "GEOLCD01 graphics system ",
GLEICHMANN_DAC => "Sigma delta DAC ",
GLEICHMANN_HPI => "AHB-to-HPI bridge ",
GLEICHMANN_SPI => "SPI master ",
GLEICHMANN_HIFC => "Human interface controller ",
GLEICHMANN_ADCDAC => "Sigma delta ADC/DAC ",
GLEICHMANN_SPIOC => "SPI master for SDCard IF ",
GLEICHMANN_AC97 => "AC97 Controller ",
others => "Unknown Device ");
constant gleichmann_lib : vendor_library_type := (
vendorid => VENDOR_GLEICHMANN,
vendordesc => GLEICHMANN_DESC,
device_table => gleichmann_device_table
);
constant CONTRIB_DESC : vendor_description := "Various contributions ";
constant contrib_device_table : device_table_type := (
CONTRIB_CORE1 => "Contributed core 1 ",
CONTRIB_CORE2 => "Contributed core 2 ",
others => "Unknown Device ");
constant contrib_lib : vendor_library_type := (
vendorid => VENDOR_CONTRIB,
vendordesc => CONTRIB_DESC,
device_table => contrib_device_table
);
constant MENTA_DESC : vendor_description := "Menta ";
constant menta_device_table : device_table_type := (
MENTA_EFPGA_IP => "eFPGA Core IP ",
others => "Unknown Device ");
constant menta_lib : vendor_library_type := (
vendorid => VENDOR_MENTA,
vendordesc => MENTA_DESC,
device_table => menta_device_table
);
constant SUN_DESC : vendor_description := "Sun Microsystems ";
constant sun_device_table : device_table_type := (
SUN_T1 => "Niagara T1 SPARC V9 Processor ",
SUN_S1 => "Niagara S1 SPARC V9 Processor ",
others => "Unknown Device ");
constant sun_lib : vendor_library_type := (
vendorid => VENDOR_SUN,
vendordesc => SUN_DESC,
device_table => sun_device_table
);
constant OPENCORES_DESC : vendor_description := "OpenCores ";
constant opencores_device_table : device_table_type := (
others => "Unknown Device ");
constant opencores_lib : vendor_library_type := (
vendorid => VENDOR_OPENCORES,
vendordesc => OPENCORES_DESC,
device_table => opencores_device_table
);
constant CBKPAN_DESC : vendor_description := "CBK PAN ";
constant cbkpan_device_table : device_table_type := (
CBKPAN_FTNANDCTRL => "NAND FLASH controller w/DMA ",
CBKPAN_FTEEPROMCTRL => "Fault Toler. EEPROM Controller ",
CBKPAN_FTSDCTRL16 => "Fault Toler. 16-bit SDRAM Ctrl.",
CBKPAN_STIXCTRL => "SolO/STIX IDPU dedicated ctrl. ",
others => "Unknown Device ");
constant cbkpan_lib : vendor_library_type := (
vendorid => VENDOR_CBKPAN,
vendordesc => CBKPAN_DESC,
device_table => cbkpan_device_table
);
constant CETON_DESC : vendor_description := "Ceton Corporation ";
constant ceton_device_table : device_table_type := (
others => "Unknown Device ");
constant ceton_lib : vendor_library_type := (
vendorid => VENDOR_CETON,
vendordesc => CETON_DESC,
device_table => ceton_device_table
);
constant SYNOPSYS_DESC : vendor_description := "Synopsys Inc. ";
constant synopsys_device_table : device_table_type := (
others => "Unknown Device ");
constant synopsys_lib : vendor_library_type := (
vendorid => VENDOR_SYNOPSYS,
vendordesc => SYNOPSYS_DESC,
device_table => synopsys_device_table
);
constant EMBEDDIT_DESC : vendor_description := "Embedd.it ";
constant embeddit_device_table : device_table_type := (
others => "Unknown Device ");
constant embeddit_lib : vendor_library_type := (
vendorid => VENDOR_EMBEDDIT,
vendordesc => EMBEDDIT_DESC,
device_table => embeddit_device_table
);
constant dlr_device_table : device_table_type := (
others => "Unknown Device ");
constant DLR_DESC : vendor_description := "German Aerospace Center ";
constant dlr_lib : vendor_library_type := (
vendorid => VENDOR_DLR,
vendordesc => DLR_DESC,
device_table => dlr_device_table
);
constant eonic_device_table : device_table_type := (
others => "Unknown Device ");
constant EONIC_DESC : vendor_description := "Eonic BV ";
constant eonic_lib : vendor_library_type := (
vendorid => VENDOR_EONIC,
vendordesc => EONIC_DESC,
device_table => eonic_device_table
);
constant telecompt_device_table : device_table_type := (
others => "Unknown Device ");
constant TELECOMPT_DESC : vendor_description := "Telecom ParisTech ";
constant telecompt_lib : vendor_library_type := (
vendorid => VENDOR_TELECOMPT,
vendordesc => TELECOMPT_DESC,
device_table => telecompt_device_table
);
constant radionor_device_table : device_table_type := (
others => "Unknown Device ");
constant RADIONOR_DESC : vendor_description := "Radionor Communications ";
constant radionor_lib : vendor_library_type := (
vendorid => VENDOR_RADIONOR,
vendordesc => RADIONOR_DESC,
device_table => radionor_device_table
);
constant bsc_device_table : device_table_type := (
BSC_CORE1 => "Core 1 ",
BSC_CORE2 => "Core 2 ",
others => "Unknown Device ");
constant BSC_DESC : vendor_description := "BSC ";
constant bsc_lib : vendor_library_type := (
vendorid => VENDOR_BSC,
vendordesc => BSC_DESC,
device_table => bsc_device_table
);
constant dtu_device_table : device_table_type := (
DTU_IV => "Instrument Virtualizer ",
DTU_RBMMTRANS => "RB/MM Transfer ",
DTU_FTMCTRL => "Memory controller with 8CS ",
others => "Unknown Device ");
constant DTU_DESC : vendor_description := "DTU Space ";
constant dtu_lib : vendor_library_type := (
vendorid => VENDOR_DTU,
vendordesc => DTU_DESC,
device_table => dtu_device_table
);
constant orbita_device_table : device_table_type := (
ORBITA_1553B => "MIL-STD-1553B Controller ",
ORBITA_429 => "429 Interface ",
ORBITA_SPI => "SPI Interface ",
ORBITA_I2C => "I2C Interface ",
ORBITA_SMARTCARD => "Smart Card Reader ",
ORBITA_SDCARD => "SD Card Reader ",
ORBITA_UART16550 => "16550 UART ",
ORBITA_CRYPTO => "Crypto Engine ",
ORBITA_SYSIF => "System Interface ",
ORBITA_PIO => "Programmable IO module ",
ORBITA_RTC => "Real-Time Clock ",
ORBITA_COLORLCD => "Color LCD Controller ",
ORBITA_PCI => "PCI Module ",
ORBITA_DSP => "DPS Co-Processor ",
ORBITA_USBHOST => "USB Host ",
ORBITA_USBDEV => "USB Device ",
others => "Unknown Device ");
constant ORBITA_DESC : vendor_description := "Orbita ";
constant orbita_lib : vendor_library_type := (
vendorid => VENDOR_ORBITA,
vendordesc => ORBITA_DESC,
device_table => orbita_device_table
);
constant ACTEL_DESC : vendor_description := "Actel Corporation ";
constant actel_device_table : device_table_type := (
ACTEL_COREMP7 => "CoreMP7 Processor ",
others => "Unknown Device ");
constant actel_lib : vendor_library_type := (
vendorid => VENDOR_ACTEL,
vendordesc => ACTEL_DESC,
device_table => actel_device_table
);
constant NASA_DESC : vendor_description := "NASA ";
constant nasa_device_table : device_table_type := (
NASA_EP32 => "EP32 Forth processor ",
others => "Unknown Device ");
constant nasa_lib : vendor_library_type := (
vendorid => VENDOR_NASA,
vendordesc => NASA_DESC,
device_table => nasa_device_table
);
constant S3_DESC : vendor_description := "S3 Group ";
constant s3_device_table : device_table_type := (
others => "Unknown Device ");
constant s3_lib : vendor_library_type := (
vendorid => VENDOR_S3,
vendordesc => S3_DESC,
device_table => s3_device_table
);
constant APPLECORE_DESC : vendor_description := "AppleCore ";
constant applecore_device_table : device_table_type := (
APPLECORE_UTLEON3 => "AppleCore uT-LEON3 Processor ",
APPLECORE_UTLEON3DSU => "AppleCore uT-LEON3 DSU ",
others => "Unknown Device ");
constant applecore_lib : vendor_library_type := (
vendorid => VENDOR_APPLECORE,
vendordesc => APPLECORE_DESC,
device_table => applecore_device_table
);
constant C3E_DESC : vendor_description := "TU Braunschweig C3E ";
constant c3e_device_table : device_table_type := (
others => "Unknown Device ");
constant c3e_lib : vendor_library_type := (
vendorid => VENDOR_C3E,
vendordesc => C3E_DESC,
device_table => c3e_device_table
);
constant UNKNOWN_DESC : vendor_description := "Unknown vendor ";
constant unknown_device_table : device_table_type := (
others => "Unknown Device ");
constant unknown_lib : vendor_library_type := (
vendorid => 0,
vendordesc => UNKNOWN_DESC,
device_table => unknown_device_table
);
constant iptable : device_array := (
VENDOR_GAISLER => gaisler_lib,
VENDOR_ESA => esa_lib,
VENDOR_OPENCHIP => openchip_lib,
VENDOR_OPENCORES => opencores_lib,
VENDOR_CONTRIB => contrib_lib,
VENDOR_DLR => dlr_lib,
VENDOR_EONIC => eonic_lib,
VENDOR_TELECOMPT => telecompt_lib,
VENDOR_GLEICHMANN => gleichmann_lib,
VENDOR_MENTA => menta_lib,
VENDOR_EMBEDDIT => embeddit_lib,
VENDOR_SUN => sun_lib,
VENDOR_RADIONOR => radionor_lib,
VENDOR_ORBITA => orbita_lib,
VENDOR_SYNOPSYS => synopsys_lib,
VENDOR_CETON => ceton_lib,
VENDOR_ACTEL => actel_lib,
VENDOR_NASA => nasa_lib,
VENDOR_S3 => s3_lib,
others => unknown_lib);
type system_table_type is array (0 to 4095) of device_description;
constant system_table : system_table_type := (
LEON3_ACT_FUSION => "LEON3 Actel Fusion Dev. board ",
LEON3_RTAX_CID2 => "LEON3FT RTAX Configuration 2 ",
LEON3_RTAX_CID5 => "LEON3FT RTAX Configuration 5 ",
LEON3_RTAX_CID6 => "LEON3FT RTAX Configuration 6 ",
LEON3_RTAX_CID7 => "LEON3FT RTAX Configuration 7 ",
LEON3_RTAX_CID8 => "LEON3FT RTAX Configuration 8 ",
LEON3_PROXIMA => "LEON3 PROXIMA FPGA design ",
ALTERA_DE2 => "Altera DE2 Development board ",
ALTERA_DE4 => "TerASIC DE4 Development board ",
XILINX_ML401 => "Xilinx ML401 Development board ",
XILINX_ML501 => "Xilinx ML501 Development board ",
XILINX_ML505 => "Xilinx ML505 Development board ",
XILINX_ML506 => "Xilinx ML506 Development board ",
XILINX_ML507 => "Xilinx ML507 Development board ",
XILINX_ML509 => "Xilinx ML509 Development board ",
XILINX_ML510 => "Xilinx ML510 Development board ",
MICROSEMI_M2GL_EVAL=> "Microsemi IGLOO2 Evaluation kit",
XILINX_SP601 => "Xilinx SP601 Development board ",
XILINX_ML605 => "Xilinx ML605 Development board ",
others => "Unknown system ");
-- pragma translate_on
end;
|
gpl-2.0
|
448bb901c8a02113a62cc07a0d6c403f
| 0.593636 | 3.699647 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/adapters/gmii_to_mii.vhd
| 1 | 8,935 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gmii_to_mii
-- File: gmii_to_mii.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: GMII to MII Ethernet bridge
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.stdlib.all;
use grlib.config_types.all;
use grlib.config.all;
entity gmii_to_mii is
port (
tx_rstn : in std_logic;
rx_rstn : in std_logic;
-- MAC SIDE
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- PHY SIDE
miii : in eth_in_type;
miio : out eth_out_type
) ;
end entity ; -- gmii_to_mii
architecture rtl of gmii_to_mii is
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) /= 0;
type sgmii_10_100_state_type is (idle, running);
type sgmii_10_100_rx_type is record
state : sgmii_10_100_state_type;
count : integer;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_logic;
rx_en : std_logic;
rx_er : std_logic;
end record;
type sgmii_10_100_tx_type is record
state : sgmii_10_100_state_type;
count : integer;
txd_part : std_logic_vector(3 downto 0);
txd : std_logic_vector(7 downto 0);
tx_dv : std_logic;
tx_er : std_logic;
tx_er_part : std_logic;
tx_en : std_logic;
end record;
constant RES_RX : sgmii_10_100_rx_type := (
state => idle,
count => 0,
rxd => (others => '0'),
rx_dv => '0',
rx_en => '0',
rx_er => '0'
);
constant RES_TX : sgmii_10_100_tx_type := (
state => idle,
count => 0,
txd_part => (others => '0'),
txd => (others => '0'),
tx_dv => '0',
tx_er => '0',
tx_er_part => '0',
tx_en => '0'
);
signal r_rx, rin_rx : sgmii_10_100_rx_type;
signal r_tx, rin_tx : sgmii_10_100_tx_type;
signal rx_dv_int, rx_er_int, rx_col_int, rx_crs_int, tx_en_int, tx_er_int, tx_dv_int, rx_en_int : std_logic;
signal rxd_int, txd_int : std_logic_vector(7 downto 0);
begin
tx_10_100 : process(tx_rstn, r_tx, gmiio)
variable v_tx : sgmii_10_100_tx_type;
begin
v_tx := r_tx;
v_tx.tx_dv := '0';
tx_dv_int <= '1';
case r_tx.state is
when idle =>
if gmiio.tx_en = '1' and gmiio.gbit = '0' then
v_tx.state := running;
v_tx.count := 0;
tx_dv_int <= '0';
end if;
when running =>
-- increment counter for 10/100 sampling
if (r_tx.count >= 9 and gmiio.speed = '1') or (r_tx.count >= 99 and gmiio.speed = '0') then
v_tx.count := 0;
else
v_tx.count := r_tx.count + 1;
end if;
-- sample appropriately according to 10/100 settings
case r_tx.count is
when 0 =>
v_tx.txd_part := gmiio.txd(3 downto 0);
v_tx.tx_er_part := gmiio.tx_er;
v_tx.tx_dv := gmiio.tx_en;
when 5 =>
if gmiio.speed = '1' then
v_tx.txd := gmiio.txd(3 downto 0) & r_tx.txd_part;
v_tx.tx_er := r_tx.tx_er_part or gmiio.tx_er;
v_tx.tx_dv := gmiio.tx_en;
v_tx.tx_en := gmiio.tx_en;
-- exit condition
if gmiio.tx_en = '0' then
v_tx.state := idle;
v_tx.tx_en := '0';
end if;
end if;
when 50 =>
if gmiio.speed = '0' then
v_tx.txd := gmiio.txd(3 downto 0) & r_tx.txd_part;
v_tx.tx_er := r_tx.tx_er_part or gmiio.tx_er;
v_tx.tx_dv := gmiio.tx_en;
v_tx.tx_en := gmiio.tx_en;
-- exit condition
if gmiio.tx_en = '0' then
v_tx.state := idle;
v_tx.tx_en := '0';
end if;
end if;
when others =>
end case ;
tx_dv_int <= r_tx.tx_dv;
when others =>
end case ;
-- reset operation
if (not RESET_ALL) and (tx_rstn = '0') then
v_tx := RES_TX;
end if;
rin_tx <= v_tx;
end process ;
tx_regs : process(miii.gtx_clk, tx_rstn)
begin
if rising_edge(miii.gtx_clk) then
r_tx <= rin_tx;
if RESET_ALL and tx_rstn = '0' then
r_tx <= RES_TX;
end if;
end if;
end process;
miio.reset <= gmiio.reset;
miio.txd <= gmiio.txd when gmiio.gbit = '1' else r_tx.txd;
miio.tx_en <= gmiio.tx_en when gmiio.gbit = '1' else r_tx.tx_en;
miio.tx_er <= gmiio.tx_er when gmiio.gbit = '1' else r_tx.tx_er;
miio.tx_clk <= gmiio.tx_clk;
miio.mdc <= gmiio.mdc;
miio.mdio_o <= gmiio.mdio_o;
miio.mdio_oe <= gmiio.mdio_oe;
miio.gbit <= gmiio.gbit;
miio.speed <= gmiio.speed;
process (rx_rstn, r_rx, miii, gmiio)
variable v_rx : sgmii_10_100_rx_type;
begin
v_rx := r_rx;
v_rx.rx_en := '0';
rx_en_int <= '1';
case r_rx.state is
when idle =>
if miii.rx_dv = '1' and gmiio.gbit = '0' then
v_rx.state := running;
v_rx.count := 0;
rx_en_int <= '0';
end if;
when running =>
-- increment counter for 10/100 sampling
if (r_rx.count >= 9 and gmiio.speed = '1') or (r_rx.count >= 99 and gmiio.speed = '0') then
v_rx.count := 0;
else
v_rx.count := r_rx.count + 1;
end if;
-- sample appropriately according to 10/100 settings
case r_rx.count is
when 0 =>
v_rx.rxd := miii.rxd(3 downto 0) & miii.rxd(3 downto 0);
v_rx.rx_en := miii.rx_dv;
v_rx.rx_dv := miii.rx_dv;
v_rx.rx_er := miii.rx_er;
-- exit condition
if miii.rx_dv = '0' then
v_rx.state := idle;
v_rx.rx_dv := '0';
end if;
when 5 =>
if gmiio.speed = '1' then
v_rx.rxd := miii.rxd(7 downto 4) & miii.rxd(7 downto 4);
v_rx.rx_en := '1';
end if;
when 50 =>
if gmiio.speed = '0' then
v_rx.rxd := miii.rxd(7 downto 4) & miii.rxd(7 downto 4);
v_rx.rx_en := '1';
end if;
when others =>
end case ;
rx_en_int <= r_rx.rx_en;
when others =>
end case ;
-- reset operation
if (not RESET_ALL) and (rx_rstn = '0') then
v_rx := RES_RX;
end if;
-- update registers
rin_rx <= v_rx;
end process;
rx_regs : process(miii.rx_clk, rx_rstn)
begin
if rising_edge(miii.rx_clk) then
r_rx <= rin_rx;
if RESET_ALL and rx_rstn = '0' then
r_rx <= RES_RX;
end if;
end if;
end process;
---- RX Mux Select
gmiii.gtx_clk <= miii.gtx_clk;
gmiii.rmii_clk <= miii.rmii_clk;
gmiii.tx_clk <= miii.tx_clk;
gmiii.tx_clk_90 <= miii.tx_clk_90;
gmiii.tx_dv <= '1' when gmiio.gbit = '1' else tx_dv_int;
gmiii.rx_clk <= miii.rx_clk;
gmiii.rxd <= miii.rxd when gmiio.gbit = '1' else r_rx.rxd;
gmiii.rx_dv <= miii.rx_dv when gmiio.gbit = '1' else r_rx.rx_dv;
gmiii.rx_er <= miii.rx_er when gmiio.gbit = '1' else r_rx.rx_er;
gmiii.rx_en <= '1' when gmiio.gbit = '1' else rx_en_int;
gmiii.rx_col <= miii.rx_col when gmiio.gbit = '1' else r_rx.rx_dv and gmiio.tx_en; -- possible clock cross domain problem
gmiii.rx_crs <= miii.rx_crs when gmiio.gbit = '1' else r_rx.rx_dv or gmiio.tx_en;
gmiii.mdio_i <= miii.mdio_i;
gmiii.mdint <= miii.mdint;
gmiii.phyrstaddr <= miii.phyrstaddr;
gmiii.edcladdr <= miii.edcladdr;
gmiii.edclsepahb <= miii.edclsepahb;
gmiii.edcldisable <= miii.edcldisable;
end architecture;
|
gpl-2.0
|
d000b6029e03ee887b41bdf82ea855b9
| 0.517963 | 3.155014 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/dftlib/synciotest.vhd
| 1 | 8,673 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: synciotest
-- File: synciotest.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Synchronous I/O test module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity synciotest is
generic (
ninputs : integer := 1;
noutputs : integer := 1;
nbidir : integer := 1;
dirmode: integer range 0 to 2 := 0 -- 0=both, 1=in-only, 2=out-only
);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
datain: in std_logic_vector(ninputs+nbidir-1 downto 0);
dataout: out std_logic_vector(noutputs+nbidir-1 downto 0);
-- 000=stopped, 001=input 010=output one-by-one, 011=output prng
-- 110=on-off 111=on-off with oe toggle
-- bit 5:3 inverted copy of 2:0, otherwise stopped
tmode: in std_logic_vector(5 downto 0);
tmodeact: out std_ulogic;
tmodeoe: out std_ulogic -- 0=input, 1=output
);
end;
architecture rtl of synciotest is
constant bytelanes_in : integer := (ninputs+nbidir)/8; -- rounded down
constant bytelanes_out : integer := (noutputs+nbidir+7)/8; -- rounded up
function int_max(i1,i2: integer) return integer is
begin
if i1>i2 then return i1; else return i2; end if;
end int_max;
constant bytelanes_max: integer := int_max(bytelanes_in, bytelanes_out);
-- LFSR with period 255 (x^8+x^6+x^5+x^4+1)
-- Rotate 7 steps each time to remove correlation between bits
-- between successive samples
-- Step State -->shift direction--->
-- *8 7 *6 *5 *4 3 2 1
-- 0 a b c d e f g h
-- 1 h a hb hc hd e f g
-- 2 g h ga ghb ghc hd e f
-- 3 f g fh fga fghb ghc hd e
-- 4 e f eg efh efga fghb ghc hd
-- 5 hd e hdf hdeg def efga fghb ghc
-- 6 ghc hd ghce gcdf cde def efga fghb
-- 7 fghb ghc fgbd fbce hbcd cde def efga
subtype lfsrstate is std_logic_vector(8 downto 1);
function nextlfsr (s: lfsrstate) return lfsrstate is
variable nsx: lfsrstate;
variable a,b,c,d,e,f,g,h: std_ulogic;
begin
a := s(8);
b := s(7);
c := s(6);
d := s(5);
e := s(4);
f := s(3);
g := s(2);
h := s(1);
nsx := (f xor g xor h xor b) & (g xor h xor c) & (f xor g xor b xor d) & (f xor b xor c xor e)
& (h xor b xor c xor d) & (c xor d xor e) & (d xor e xor f) & (e xor f xor g xor a);
return nsx;
end nextlfsr;
type synciotest_regs is record
datareg: std_logic_vector(bytelanes_max*8-1 downto 0);
end record;
signal r,nr: synciotest_regs;
begin
comb: process(rstn, tmode, datain, r)
variable v: synciotest_regs;
variable nls: std_logic_vector(bytelanes_max*8-1 downto 0);
variable o: std_logic_vector(noutputs+nbidir-1 downto 0);
variable op: std_logic_vector(2**log2(bytelanes_out*8)-1 downto 0);
variable vact: std_ulogic;
variable voe: std_ulogic;
variable vrst, dx: std_logic_vector(bytelanes_max*8-1 downto 0);
begin
v := r;
o := r.datareg(noutputs+nbidir-1 downto 0);
op := (others => '0');
vact := '0';
voe := tmode(1);
for x in 0 to bytelanes_max-1 loop
nls(x*8+7 downto x*8) := nextlfsr(r.datareg(x*8+7 downto x*8));
end loop;
vrst := (others => '0');
for x in 0 to bytelanes_max-1 loop
vrst(x*8+7 downto x*8) := std_logic_vector(to_unsigned(x+1,8));
end loop;
dx := r.datareg xor vrst;
case tmode is
when "110001" =>
-- Use datareg as sampled input and LFSR state, compare input with
-- expected next state
if dirmode /= 2 then
vact := '1';
o(o'high downto nbidir) := (others => '0');
for x in 0 to bytelanes_in-1 loop
if datain(x*8+7 downto x*8) /= nls(x*8+7 downto x*8) then
o(nbidir+(x mod noutputs)) := '1';
end if;
v.datareg(x*8+7 downto x*8) := datain(x*8+7 downto x*8);
end loop;
-- handle ninputs % 8 != 0 by re-using bottom byte lane LFSR
if ninputs+nbidir > bytelanes_in*8 then
if datain(ninputs+nbidir-1 downto 8*bytelanes_in) /= nls(ninputs+nbidir-bytelanes_in*8-1 downto 0) then
o(nbidir+(bytelanes_in mod noutputs)) := '1';
end if;
end if;
end if;
when "101010" =>
if dirmode /= 1 then
vact := '1';
-- FIXME handle wrong reset vals
-- Use datareg as counter
-- Bits 2:0 pos in sequence "00101010"
-- Bits 3 inv controls value on other outputs than tested
-- Bits X:4 controls which bit is tested
if dx(3)='1' then
op := (others => '0');
else
op := (others => '1');
end if;
op(to_integer(unsigned(dx(log2(noutputs+nbidir)+3 downto 4)))) := not dx(0) and (dx(1) or dx(2));
o := op(noutputs+nbidir-1 downto 0);
dx(log2(noutputs+nbidir)+3 downto 0) :=
std_logic_vector(unsigned(dx(log2(noutputs+nbidir)+3 downto 0))+1);
v.datareg := dx xor vrst;
end if;
when "100011" =>
-- Use datareg as LFSR state, drive as output and clock in next state
if dirmode /= 1 then
vact := '1';
v.datareg := nls;
end if;
when "001110" =>
-- Toggle value on all outputs each cycle
if dirmode /= 1 then
vact := '1';
o := r.datareg(o'length-1 downto 2) & r.datareg(2) & r.datareg(2);
v.datareg(r.datareg'high downto 2) := (others => r.datareg(1));
v.datareg(0) := '1';
v.datareg(1) := r.datareg(1) xor r.datareg(0);
end if;
when "000111" =>
-- Toggle output-enable each cycle, toggle all outputs whenever OE changes
if dirmode /= 1 and nbidir > 0 then
vact := '1';
o := r.datareg(o'length-1 downto 2) & r.datareg(2) & r.datareg(2);
v.datareg(r.datareg'high downto 2) := (others => r.datareg(1));
voe := r.datareg(0);
-- 2-bit counter
v.datareg(0) := not v.datareg(0);
v.datareg(1) := r.datareg(1) xor r.datareg(0);
end if;
when others =>
end case;
if rstn='0' or tmode(2 downto 0)="000" then
v.datareg := vrst;
end if;
nr <= v;
dataout <= o;
tmodeact <= vact;
tmodeoe <= voe;
end process;
regs: process(clk)
begin
if rising_edge(clk) then
r <= nr;
end if;
end process;
--pragma translate_off
tg: if false generate
lfsrtest: process
variable s: lfsrstate;
variable stmap: std_logic_vector(255 downto 0);
variable i,x: integer;
begin
print("------ LFSR test ------");
stmap := (others => '0');
s := "10000000";
i := 0;
loop
x := to_integer(unsigned(s));
print("State: " & tost(s));
if stmap(x)='1' then
print("Looped after " & tost(i) & " iterations");
assert i=255 severity failure;
assert stmap(0)='0' severity failure;
for q in 1 to 255 loop
assert stmap(q)='1' severity failure;
end loop;
print("------ LFSR test done ------");
wait;
end if;
stmap(x) := '1';
s := nextlfsr(s);
i := i+1;
end loop;
end process;
end generate;
--pragma translate_on
end;
|
gpl-2.0
|
5f780ef4009ccd7c0e71f69a49585fda
| 0.549406 | 3.441667 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/micron/sdram/mt48lc16m16a2.vhd
| 3 | 68,384 |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
if L.all'length*4 < recdata'length then
hread(l, recdata(0 to L.all'length*4-1));
else
hread(l, recdata);
end if;
if index < 32 then
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
else
Bank_Load := recaddr(26 downto 25);
Rows_Load := recaddr(24 downto 12);
Cols_Load := recaddr(11 downto 3);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 1 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 1 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 1 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
|
gpl-2.0
|
d045d26a0a2fb28851bf6903f051fc61
| 0.4307 | 4.088485 | false | false | false | false |
lunod/lt24_ctrl
|
demo/genpix.vhd
| 1 | 5,404 |
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
-- Color format :
-- "1111100000000000" : red (5 bits, 15 downto 11)
-- "0000011111100000" : green (6 bits, 10 downto 5)
-- "0000000000011111" : blue (5 bits, 4 downto 0)
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity genpix is
generic(system_frequency: real := 50_000_000.0);
port(x : in std_logic_vector(7 downto 0); -- 0 .. 239 => 8 bits
y : in std_logic_vector(8 downto 0); -- 0 .. 319 => 9 bits
c : out std_logic_vector(15 downto 0); -- 16 bits colors
resetn: in std_logic;
clk : in std_logic);
end entity genpix;
---------------------------------------------------------------------------
architecture rtl of genpix is
constant t_cycles : natural := integer(system_frequency * 1.0e-1);
signal pos_x : unsigned(x'range);
signal pos_y : unsigned(y'range);
signal c0_reg, c1_reg, c2_reg, c3_reg: std_logic_vector(c'range);
signal split_x : unsigned(x'range);
signal split_y : unsigned(y'range);
begin
update_cpt: process(clk, resetn)
variable counter : natural range 0 to (t_cycles - 1);
begin
if resetn = '0' then
counter := 0;
c0_reg <= x"0000";
c1_reg <= x"F800";
c2_reg <= x"07E0";
c3_reg <= x"001F";
split_x <= (others => '0');
split_y <= (others => '0');
elsif rising_edge(clk) then
if (counter = t_cycles - 1) then
counter := 0;
-- Increments 16 bits color value by 1
c0_reg <= std_logic_vector(unsigned(c0_reg) + 1);
-- Increments only RED channel
c1_reg <= std_logic_vector(unsigned(c1_reg(15 downto 11)) + 1) &
"000000" &
"00000";
-- Increments only GREEN channel
c2_reg <= "00000" &
std_logic_vector(unsigned(c2_reg(10 downto 5)) + 1) &
"00000";
-- Increments only BLUE channel
c3_reg <= "00000" &
"000000" &
std_logic_vector(unsigned(c3_reg(4 downto 0)) + 1);
-- Moving line used to split screen into 2 areas
split_y <= (split_y + 1) mod 320;
split_x <= (split_x + 1) mod 240;
else
counter := counter + 1;
end if;
end if; -- resetn = '0'
end process update_cpt;
pos_x <= unsigned(x);
pos_y <= unsigned(y);
update_c:process(clk, resetn)
begin
if resetn = '0' then
c <= (others => '0');
elsif rising_edge(clk) then
-- Displays 3 colored pixels in a 1 pixel width black box
-- in the top left corner
if (pos_x < 5) and (pos_y = 0) then
c <= x"0000";
elsif (pos_x = 0) and (pos_y = 1) then
c <= x"0000";
elsif (pos_x = 1) and (pos_y = 1) then
c <= x"F800";
elsif (pos_x = 2) and (pos_y = 1) then
c <= x"07E0";
elsif (pos_x = 3) and (pos_y = 1) then
c <= x"001F";
elsif (pos_x = 4) and (pos_y = 1) then
c <= x"0000";
elsif (pos_x < 5) and (pos_y = 2) then
c <= x"0000";
-- Display 3 colored bands along the left side
elsif (pos_x < 10) then
c <= "11111" & "000000" & "00000"; -- R
elsif (pos_x < 20) then
c <= "00000" & "111111" & "00000"; -- V
elsif (pos_x < 30) then
c <= "00000" & "000000" & "11111"; -- B
-- Display 3 colored bands along the top side
elsif (pos_y < 10) then
c <= "11111" & "010000" & "01000";
elsif (pos_y < 20) then
c <= "01000" & "111111" & "01000";
elsif (pos_y < 30) then
c <= "01000" & "010000" & "11111";
-- Split the remaining screen area into 4 area-changing
-- sections, each filed with a single color
elsif pos_x < split_x then
if pos_y < split_y then
c <= c0_reg; -- x"07E0"; -- Green
else
c <= c1_reg; --x"001f"; -- Blue
end if; -- pos_x < 160
else
if pos_y < split_y then
c <= c2_reg; --x"F800"; -- Red
else
c <= c3_reg; --x"ffff";
end if; -- pos_x < 160
end if; -- pos_x < 120
end if; -- rising_edge(clk)
end process update_c;
end architecture rtl;
---------------------------------------------------------------------------
|
lgpl-3.0
|
29a3c80cd5272aa3fbcd99f50bd95def
| 0.504996 | 3.617135 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/grlfpw_net.vhd
| 1 | 41,452 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpw
-- File: grlfpw.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRLFPC wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grlfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 1 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grlfpw_net is
component grlfpw_0_axcelerator is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3 is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_altera
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_actfus is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3e is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3l is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
begin
alt : if (tech = altera) generate -- Cyclone, Stratix V, Cyclone V
grlfpw0 : grlfpw_0_altera
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtx : if (tech = stratix1) or (tech = stratix2) generate
grlfpw0 : grlfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grlfpw40 : grlfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grlfpw40 : grlfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
grlfpw0 : grlfpw_0_axcelerator
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
fus : if (tech = actfus) generate
grlfpw0 : grlfpw_0_actfus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3 : if (tech = apa3) generate
grlfpw0 : grlfpw_0_proasic3
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3l : if (tech = apa3l) generate
grlfpw0 : grlfpw_0_proasic3l
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3e : if (tech = apa3e) generate
grlfpw0 : grlfpw_0_proasic3e
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
uni : if (is_unisim(tech) = 1) generate
grlfpw0 : grlfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
|
gpl-2.0
|
132e7febe479a1ba52931ff5525d0882
| 0.640283 | 2.588485 | false | false | false | false |
aortiz49/MIPS-Processor
|
Hardware/add32.vhd
| 1 | 802 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add32 is
port(
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
sum : out std_logic_vector(31 downto 0)
);
end add32;
architecture arch of add32 is
signal temp_c : std_logic_vector(32 downto 0);
begin
add: for i in 0 to 31 generate --generate 32 1-bit adders for add32 entity
add32: entity work.add1
port map(
in1 => in1(i),
in0 => in0(i),
cin => temp_c(i), -- Cin will be previous value temp signal
cout => temp_c(i+1), -- cout will feed into cin
sum => sum(i)
);
end generate;
temp_c(0) <= '0'; -- Set cin to first adder to 0. Leaving it blank will result in an 'X' for sum(0)
end arch;
|
mit
|
f7cb1c1d730b234550dbc96682186a66
| 0.602244 | 2.756014 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml510/ahbrom.vhd
| 3 | 8,961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800015";
when 16#00064# => romdata <= X"03300000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A1FF";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE03";
when 16#00069# => romdata <= X"8410A265";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800005";
when 16#00074# => romdata <= X"03200000";
when 16#00075# => romdata <= X"0539A81B";
when 16#00076# => romdata <= X"8410A265";
when 16#00077# => romdata <= X"C4204000";
when 16#00078# => romdata <= X"05000080";
when 16#00079# => romdata <= X"82100000";
when 16#0007A# => romdata <= X"80A0E000";
when 16#0007B# => romdata <= X"02800005";
when 16#0007C# => romdata <= X"01000000";
when 16#0007D# => romdata <= X"82004002";
when 16#0007E# => romdata <= X"10BFFFFC";
when 16#0007F# => romdata <= X"8620E001";
when 16#00080# => romdata <= X"3D1003FF";
when 16#00081# => romdata <= X"BC17A3E0";
when 16#00082# => romdata <= X"BC278001";
when 16#00083# => romdata <= X"9C27A060";
when 16#00084# => romdata <= X"03100000";
when 16#00085# => romdata <= X"81C04000";
when 16#00086# => romdata <= X"01000000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
d46179e72afb82b83b62dcd367bfbb31
| 0.58085 | 3.287234 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddr2spax_ahb.vhd
| 1 | 16,843 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spa_ahb
-- File: ddr2spa_ahb.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynch AHB interface for DDR memory controller
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog: out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end ddr2spax_ahb;
architecture rtl of ddr2spax_ahb is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant ramwt: integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, DEVID, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ahbw: integer := log2(ahbbits);
constant l2ddrw: integer := log2(2*ddrbits);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_wabits: integer := 1+l2blen-5; -- log2(burstlen);
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw; -- log2(burstlen*32/ahbbits);
constant rbuf_rdbits: integer := ahbbits;
type ahbstate is (asnormal,asw1,asw2,asww1,asww2,aswr,aswwx);
type ahb_reg_type is record
s : ahbstate;
start_tog : std_logic;
ramaddr : std_logic_vector(l2blen-4 downto 2);
-- These are sent to the DDR layer
req : ddr_request_type;
-- Posted write following current request
nreq : ddr_request_type;
-- Read flow control
rctr_lin : std_logic_vector(3 downto 0);
endpos : std_logic_vector(7 downto log2(ddrbits/4));
block_read: std_logic_vector(1 downto 0);
-- Current AHB control signals
haddr : std_logic_vector(31 downto 0);
haddr_nonseq: std_logic_vector(9 downto 0);
hio : std_logic;
hsize : std_logic_vector(2 downto 0);
hwrite : std_logic;
hburst0 : std_logic;
-- AHB slave outputs
so_hready : std_logic;
-- From DDR layer
resp1,resp2: ddr_response_type;
end record;
signal ar,nar : ahb_reg_type;
begin
ahbcomb : process(ahbsi,rst,ar,response,rbrdata,hwidth,beid)
variable av: ahb_reg_type;
variable va2d: ddr_request_type;
variable so: ahb_slv_out_type;
variable vdone: std_logic;
variable vresp: ddr_response_type;
variable bigsize,midsize,canburst: std_logic;
variable inc_ramaddr: std_logic;
variable row: std_logic_vector(14 downto 0);
variable wbwa: std_logic_vector(wbuf_wabits-1 downto 0);
variable wbwd: std_logic_vector(wbuf_wdbits-1 downto 0);
variable wbw,wbwb: std_logic;
variable rbra: std_logic_vector(rbuf_rabits-1 downto 0);
variable ha0: std_logic_vector(31 downto 0);
variable rend,nrend: std_logic_vector(7 downto log2(ddrbits/4));
variable datavalid, writedone: std_logic;
variable rctr_gray: std_logic_vector(3 downto 0);
variable tog_start: std_logic;
variable regdata: std_logic_vector(31 downto 0);
begin
ha0 := ahbsi.haddr;
ha0(31 downto 20) := ha0(31 downto 20) and not std_logic_vector(to_unsigned(hmask,12));
av := ar;
so := (hready => ar.so_hready, hresp => HRESP_OKAY, hrdata => (others => '0'),
hsplit => (others => '0'), hirq => (others => '0'),
hconfig => hconfig, hindex => hindex);
wbw := '0';
wbwb := '0';
wbwa := ar.start_tog & ar.ramaddr;
wbwd := ahbreaddata(ahbsi.hwdata,ar.haddr(4 downto 2),
std_logic_vector(to_unsigned(log2(ahbbits/8),3)));
rbra := ar.ramaddr(l2blen-4 downto l2ahbw-3);
-- Determine whether the current hsize is a big (ahbbits-width) access
bigsize := '0';
if (ahbbits = 256 and ar.hsize(2)='1' and ar.hsize(0)='1') or
(ahbbits = 128 and ar.hsize(2)='1') or
(ahbbits = 64 and ar.hsize="011") then
bigsize := '1';
end if;
midsize := '0';
if ( (ahbbits = 256 and ((ar.hsize(2)='1' and ar.hsize(0)='0') or (ar.hsize(1 downto 0)="11"))) or
(ahbbits = 128 and ar.hsize="011") ) then
midsize := '1';
end if;
-- Determine whether sequential burst is allowed after current access
canburst := '0';
if (bigsize='1' and ar.haddr(l2blen-4 downto l2ahbw-3)/=(not zerov(l2blen-l2ahbw))) or
(ar.hsize="010" and ar.haddr(l2blen-4 downto 2)/=(not zerov(l2blen-5))) then
canburst := '1';
end if;
-- if canburst='1' then
-- print("ar.hsize=" & tost(ar.hsize) & "ar.haddr: " & tost(ar.haddr(l2blen-4 downto 2)) & " /= " & tost(not zerov(l2blen-5)));
-- end if;
if ar.hio='1' then
canburst := '0';
end if;
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.haddr := ha0;
av.ramaddr := ha0(log2(4*burstlen)-1 downto 2);
av.hio := ahbsi.hmbsel(1);
av.hsize := ahbsi.hsize;
av.hwrite := ahbsi.hwrite;
av.hburst0 := ahbsi.hburst(0);
if ahbsi.htrans(0)='0' or canburst='0' then
av.haddr_nonseq := ha0(9 downto 0);
end if;
end if;
-- Synchronize from DDR domain
av.resp1:=response; av.resp2:=ar.resp1;
vresp := ar.resp2;
if nosync /= 0 then vresp := response; end if;
vdone := vresp.done_tog;
-- Determine whether we can read more data in burst
datavalid := '0';
writedone := '0';
if ar.start_tog=vdone then
datavalid := '1';
writedone := '1';
end if;
if ar.rctr_lin="0000" then rend:=ar.haddr(7 downto l2ddrw-3); else rend:=ar.endpos; end if;
nrend := std_logic_vector(unsigned(rend)+1);
rctr_gray := lin2gray(ar.rctr_lin);
if ar.start_tog/=vdone and rctr_gray /= vresp.rctr_gray and ar.block_read(0)='0' then
av.rctr_lin := std_logic_vector(unsigned(ar.rctr_lin)+1);
av.endpos := nrend;
rend := nrend;
end if;
if 2*ddrbits > ahbbits then
if rend /= ar.haddr(7 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
else
if rend(7 downto log2(ahbbits/8)) /= ar.haddr(7 downto log2(ahbbits/8)) then
datavalid := '1';
end if;
if 2*ddrbits < ahbbits and ahbbits > 32 then
if ar.hsize="010" or ar.hsize="001" or ar.hsize="000" then
if rend(log2(ahbbits/8)-1 downto log2(ddrbits/4)) /=
ar.haddr(log2(ahbbits/8)-1 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
end if;
end if;
end if;
if ar.block_read(1)='1' or (ar.start_tog/=vdone and ar.block_read(0)='1') then
datavalid := '0';
writedone := '0';
end if;
if ar.block_read(1)='1' and ar.start_tog/=vdone then
av.block_read(1) := '0';
end if;
if ar.block_read(1)='0' and vresp.rctr_gray="0000" then
av.block_read(0) := '0';
end if;
-- FSM
inc_ramaddr := '0';
tog_start := '0';
case ar.s is
when asnormal =>
-- Idle and memory read state
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
-- Pass on address immediately to request for read case
av.req := (startaddr => ha0,
endaddr => ha0(9 downto 0),
hsize => ahbsi.hsize,
hwrite => ahbsi.hwrite,
hio => ahbsi.hmbsel(1),
burst => ahbsi.hburst(0),
maskdata => '0', maskcb => '0');
if ahbsi.hwrite='0' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
tog_start := '1';
elsif datavalid='1' then
inc_ramaddr := '1';
else
av.so_hready := '0';
-- grlib.testlib.print("Going to waitstate!");
end if;
else
av.s := asw1;
end if;
end if;
if ar.so_hready='0' and datavalid='1' then
av.so_hready := '1';
inc_ramaddr := '1';
end if;
when asw1 =>
-- Transfer data for write request
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.req.endaddr := ar.haddr(9 downto 0);
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
tog_start := '1';
end if;
else
av.s := asw2;
tog_start := '1';
end if;
when asw2 =>
-- Write request ongoing
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
elsif writedone='1' then
av.s := asnormal;
end if;
when asww1 =>
-- Transfer data for second write while write request ongoing
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
av.s := aswwx;
end if;
else
av.s := asww2;
end if;
when asww2 =>
-- Second write enqueued, wait for first write to finish
-- Any new request here will cause HREADY to go low
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.so_hready := '0';
av.s := aswwx;
elsif writedone='1' then
av.req := ar.nreq;
tog_start := '1';
av.s := asw2;
end if;
when aswr =>
-- Read request following ongoing write request
-- HREADY is low in this state
av.so_hready := '0';
if writedone='1' then
av.req := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.hwrite := '0';
tog_start := '1';
av.s := asnormal;
end if;
when aswwx =>
-- Write ongoing + write posted + another AHB request (read or write)
-- Keep HREADY low
av.so_hready := '0';
if writedone='1' then
tog_start := '1';
av.req := ar.nreq;
if ar.hwrite='1' then
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.so_hready := '1';
av.s := asww1;
else
av.s := aswr;
end if;
end if;
end case;
if tog_start='1' and (regarea=0 or av.req.hio='0' or av.req.startaddr(5)='0') then
av.start_tog := not ar.start_tog;
av.rctr_lin := "0000";
if ar.start_tog /= vdone then
av.block_read(1) := '1';
end if;
av.block_read(0) := '1';
end if;
if inc_ramaddr='1' then
if bigsize='1' then
av.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)))+1);
else
av.ramaddr(log2(4*burstlen)-1 downto 2) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto 2))+1);
end if;
end if;
-- Used only if regarea /= 0
regdata := (others => '0');
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/8),3));
if hwidth/='0' then
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/16),3));
end if;
regdata(15 downto 12) := beid;
-- If we are using AMBA-compliant data muxing, nothing needs to be done to
-- the hrdata vector. Otherwise, we need to duplicate 32-bit lanes
if regarea/=0 and ar.req.hio='1' and ar.req.startaddr(5)='1' then
so.hrdata := ahbdrivedata(regdata);
elsif CORE_ACDM /= 0 then
so.hrdata := ahbdrivedata(rbrdata);
else
so.hrdata := ahbselectdata(ahbdrivedata(rbrdata),ar.haddr(4 downto 2),ar.hsize);
end if;
if rst='0' then
av.s := asnormal;
av.block_read := "00";
av.start_tog := '0';
av.so_hready := '1';
so.hready := '1';
so.hresp := HRESP_OKAY;
end if;
if l2blen-l2ddrw < 4 then
av.rctr_lin(3 downto l2blen-l2ddrw) := (others => '0');
end if;
nar <= av;
request <= ar.req;
start_tog <= ar.start_tog;
ahbso <= so;
wbwrite <= wbw;
wbwritebig <= wbwb;
wbwaddr <= wbwa;
wbwdata <= wbwd;
rbraddr <= rbra;
end process;
ahbregs : process(clk_ahb)
begin
if rising_edge(clk_ahb) then
ar <= nar;
end if;
end process;
end;
|
gpl-2.0
|
34925ec4366cddb03c32be3230720820
| 0.542481 | 3.51555 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmulru.vhd
| 1 | 6,015 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulru
-- File: mmulru.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulru is
generic (
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end mmulru;
architecture rtl of mmulru is
constant entries_log : integer := log2(entries);
component mmulrue
generic (
position : integer;
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type
);
end component;
type lru_rtype is record
bar : std_logic_vector(1 downto 0);
clear : std_logic_vector(M_ENT_MAX-1 downto 0);
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
signal c,r : lru_rtype;
signal lruei : mmulruei_a (entries-1 downto 0);
signal lrueo : mmulrueo_a (entries-1 downto 0);
begin
p0: process (rst, r, lrui, lrueo)
variable v : lru_rtype;
variable reinit : std_logic;
variable pos : std_logic_vector(entries_log-1 downto 0);
variable touch : std_logic;
begin
v := r;
-- #init
reinit := '0';
--# eather element in luri or element 0 to top
pos := lrui.pos(entries_log-1 downto 0);
touch := lrui.touch;
if (lrui.touchmin) = '1' then
pos := lrueo(0).pos(entries_log-1 downto 0);
touch := '1';
end if;
for i in entries-1 downto 0 loop
lruei(i).pos <= (others => '0'); -- this is really ugly ...
lruei(i).left <= (others => '0');
lruei(i).right <= (others => '0');
lruei(i).pos(entries_log-1 downto 0) <= pos;
lruei(i).touch <= touch;
lruei(i).clear <= r.clear((entries-1)-i); -- reverse order
lruei(i).flush <= lrui.flush;
end loop;
lruei(entries-1).fromleft <= '0';
lruei(entries-1).fromright <= lrueo(entries-2).movetop;
lruei(entries-1).right(entries_log-1 downto 0) <= lrueo(entries-2).pos(entries_log-1 downto 0);
for i in entries-2 downto 1 loop
lruei(i).left(entries_log-1 downto 0) <= lrueo(i+1).pos(entries_log-1 downto 0);
lruei(i).right(entries_log-1 downto 0) <= lrueo(i-1).pos(entries_log-1 downto 0);
lruei(i).fromleft <= lrueo(i+1).movetop;
lruei(i).fromright <= lrueo(i-1).movetop;
end loop;
lruei(0).fromleft <= lrueo(1).movetop;
lruei(0).fromright <= '0';
lruei(0).left(entries_log-1 downto 0) <= lrueo(1).pos(entries_log-1 downto 0);
if not (r.bar = lrui.mmctrl1.bar) then
reinit := '1';
end if;
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (reinit = '1') then
v.bar := lrui.mmctrl1.bar;
v.clear := (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
v.clear(1 downto 0) := "11"; -- reverse order
when "10" =>
v.clear(2 downto 0) := "111"; -- reverse order
when "11" =>
v.clear(4 downto 0) := "11111"; -- reverse order
when others =>
v.clear(0) := '1';
end case;
end if;
--# drive signals
lruo.pos <= lrueo(0).pos;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r.bar <= lrui.mmctrl1.bar;
r.clear <= (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
r.clear(1 downto 0) <= "11"; -- reverse order
when "10" =>
r.clear(2 downto 0) <= "111"; -- reverse order
when "11" =>
r.clear(4 downto 0) <= "11111"; -- reverse order
when others =>
r.clear(0) <= '1';
end case;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r.bar <= mmctrl_type1_none.bar;
r.clear <= (others => '0');
r.clear(0) <= '1';
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
--# lru entries
lrue0: for i in entries-1 downto 0 generate
l1 : mmulrue
generic map ( position => i,
entries => entries )
port map (rst, clk, lruei(i), lrueo(i));
end generate lrue0;
end rtl;
|
gpl-2.0
|
b37f35e747b9007b6b2f8e516ce99af6
| 0.561264 | 3.511384 | false | false | false | false |
ECE492W2014G4/G4Capstone
|
MUX3x1.vhd
| 1 | 923 |
library ieee;
use ieee.std_logic_1164.all;
entity MUX5X1 is
port(
clk: in std_logic;
distortion: in std_logic_vector(15 downto 0);
reverb: in std_logic_vector(15 downto 0);
AUDIO_IN: in std_logic_vector(15 downto 0);
audio_loop : in std_logic_vector(15 downto 0);
OUTPUT: out std_logic_vector(15 downto 0);
SEL: in std_logic_vector(4 downto 0)
);
end entity MUX5X1;
architecture arch of MUX5X1 is
begin
MUX: process(clk,SEL)
begin
if(rising_edge(clk)) then
case SEL is
when "00001" =>
OUTPUT <= distortion;
when "00010" =>
OUTPUT <= reverb;
when "001--" =>
OUTPUT <= audio_loop;
when others =>
--no effect to be applied
--distortion component has a passthrough functionality (it simply passes through the audio when an effect is not applied)
OUTPUT <= AUDIO_IN;
end case;
end if;
end process;
end arch;
|
gpl-3.0
|
3fed50784ea0e02d6cf18c91974d27bb
| 0.638137 | 3.193772 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-xc3sd-1800/ahbrom.vhd
| 3 | 8,968 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A033";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE03";
when 16#00069# => romdata <= X"8410A250";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"05248820";
when 16#00077# => romdata <= X"8410A3CD";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000080";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
9fdbaced9445cd4c5ec9fd26a5a58c20
| 0.580397 | 3.293426 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/adq_dqs/output_dqs_iobuf_inst.vhd
| 3 | 7,464 |
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_out
-- ============================================================
-- File Name: output_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_out
--
-- Simulation Library Files(s):
-- stratixiii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altiobuf_out CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b oe
--VERSION_BEGIN 8.0SP1 cbx_altiobuf_in 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratixiii 2008:06:18:296807 VERSION_END
LIBRARY stratixiii;
USE stratixiii.all;
--synthesis_resources = stratixiii_io_obuf 2 stratixiii_pseudo_diff_out 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY output_dqs_iobuf_inst_iobuf_out_sdp IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1');
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1')
);
END output_dqs_iobuf_inst_iobuf_out_sdp;
ARCHITECTURE RTL OF output_dqs_iobuf_inst_iobuf_out_sdp IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_obuf_ba_o : STD_LOGIC;
SIGNAL wire_obufa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_obar : STD_LOGIC;
--SIGNAL oe_b : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT stratixiii_io_obuf
GENERIC
(
bus_hold : STRING := "false";
open_drain_output : STRING := "false";
shift_series_termination_control : STRING := "false";
sim_dynamic_termination_control_is_connected : STRING := "false";
lpm_type : STRING := "stratixiii_io_obuf"
);
PORT
(
dynamicterminationcontrol : IN STD_LOGIC := '0';
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT stratixiii_pseudo_diff_out
PORT
(
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataout(0) <= wire_obufa_o;
dataout_b(0) <= wire_obuf_ba_o;
--oe_b <= (OTHERS => '1');
obuf_ba : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
i => wire_pseudo_diffa_obar,
o => wire_obuf_ba_o,
oe => oe_b(0)
);
obufa : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
i => wire_pseudo_diffa_o,
o => wire_obufa_o,
oe => oe(0)
);
pseudo_diffa : stratixiii_pseudo_diff_out
PORT MAP (
i => datain(0),
o => wire_pseudo_diffa_o,
obar => wire_pseudo_diffa_obar
);
END RTL; --output_dqs_iobuf_inst_iobuf_out_sdp
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY output_dqs_iobuf_inst IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END output_dqs_iobuf_inst;
ARCHITECTURE RTL OF output_dqs_iobuf_inst IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT output_dqs_iobuf_inst_iobuf_out_sdp
PORT (
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(0 DOWNTO 0);
dataout_b <= sub_wire1(0 DOWNTO 0);
output_dqs_iobuf_inst_iobuf_out_sdp_component : output_dqs_iobuf_inst_iobuf_out_sdp
PORT MAP (
datain => datain,
oe => oe,
oe_b => oe_b,
dataout => sub_wire0,
dataout_b => sub_wire1
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: pseudo_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_oe STRING "TRUE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
-- Retrieval info: USED_PORT: dataout_b 0 0 1 0 OUTPUT NODEFVAL "dataout_b[0..0]"
-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
-- Retrieval info: CONNECT: dataout_b 0 0 1 0 @dataout_b 0 0 1 0
-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.cmp FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst_inst.vhd FALSE FALSE
-- Retrieval info: LIB_FILE: stratixiii
|
gpl-2.0
|
74905e04d43fbc43482b71abd64b7325
| 0.641077 | 3.304117 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/iopad_tm.vhd
| 1 | 3,673 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_tm, iopad_tmvv
-- File: iopad_tm.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Tech map for IO pad with built-in test mux
------------------------------------------------------------------------------
-- This is implemented recursively by passing in the test signals via the cfgi
-- input for technologies that support it, and muxing manually for others.
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_tm is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
test: in std_ulogic; ti,ten : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopad_tm is
signal mi,men: std_ulogic;
signal mcfgi: std_logic_vector(19 downto 0);
begin
notm: if has_tm_pads(tech)=0 generate
mi <= ti when test='1' else i;
men <= ten when test='1' else en;
mcfgi <= cfgi;
end generate;
hastm: if has_tm_pads(tech)/=0 generate
mi <= i;
men <= en;
mcfgi <= cfgi(19 downto 3) & ti & ten & test;
end generate;
p: iopad
generic map (tech => tech, level => level, slew => slew,
voltage => voltage, strength => strength,
oepol => oepol, filter => filter)
port map (pad => pad, i => mi, en => men, o => o, cfgi => mcfgi);
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_tmvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
test: in std_ulogic;
ti : in std_logic_vector(width-1 downto 0);
ten : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopad_tmvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_tm generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en(j), o(j), test, ti(j), ten(j), cfgi);
end generate;
end;
|
gpl-2.0
|
0f12bcf1048406274ea348cb1ddd4f74
| 0.612306 | 3.740326 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-de2-ep2c35/config.vhd
| 1 | 5,711 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
8e2badfe12c9396f0c602d452042dafd
| 0.645246 | 3.649201 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/lpddr2if.vhd
| 1 | 8,374 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_ca: out std_logic_vector(9 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(1 downto 0);
mem_dq: inout std_logic_vector(15 downto 0);
mem_dqs: inout std_logic_vector(1 downto 0);
mem_dqs_n: inout std_logic_vector(1 downto 0);
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of lpddr2if is
component lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_ca : out std_logic_vector(9 downto 0); -- mem_ca
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(63 downto 0); -- readdata
avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component lpddr2ctrl1;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
ctrl0: lpddr2ctrl1
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_ca => mem_ca,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(63 downto 0),
avl_wdata => avlsi.wdata(63 downto 0),
avl_be => avlsi.be(7 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_locked => open,
pll_avl_clk => open,
pll_config_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 64) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 64,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
|
gpl-2.0
|
4d4fe8cc2daaa82e259acefe7723e961
| 0.476236 | 3.658366 | false | false | false | false |
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