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|---|---|---|---|---|---|---|---|---|---|---|---|---|
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp605/pcie.vhd
| 3 | 4,261 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pcie is
component pcie_master_fifo_sp605 is
generic (
memtech : integer := DEFMEMTECH;
dmamst : integer := NAHBMST;
fifodepth : integer := 5;
hslvndx : integer := 0;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#;
haddr : integer := 16#A00#;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcie_master_target_sp605 is
generic (
master : integer := 1;
hmstndx : integer := 0;
hslvndx : integer := 0;
abits : integer := 21;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask : integer := 16#FFE#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr : integer := 0;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System In terface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pciedma is
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
fifodepth : integer := 5; -- FIFO depth
device_id : integer := 9; -- PCI device ID
vendor_id : integer := 16#10EE#; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#A00#;
hmask : integer := 16#FFF#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#
);
port(
rst : in std_logic;
clk : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
end;
|
gpl-2.0
|
649bf54a9b7202333853fc37205bfcb6
| 0.50927 | 3.486907 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25/testbench.vhd
| 1 | 10,973 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Cyclone-III LEON3 Demonstration design test bench
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_cen : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
-- ATA signals
signal ata_rst : std_logic;
signal ata_data : std_logic_vector(15 downto 0);
signal ata_da : std_logic_vector(2 downto 0);
signal ata_cs0 : std_logic;
signal ata_cs1 : std_logic;
signal ata_dior : std_logic;
signal ata_diow : std_logic;
signal ata_iordy : std_logic;
signal ata_intrq : std_logic;
signal ata_dmack : std_logic;
signal cf_gnd_da : std_logic_vector(10 downto 3);
signal cf_atasel : std_logic;
signal cf_we : std_logic;
signal cf_power : std_logic;
signal cf_csel : std_logic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
address(0) <= '0';
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address(25 downto 1), data, romsn, oen, writen, open,
ssram_cen, ssram_wen, ssram_bw, ssram_oen,
ssram_clk, ssram_adscn, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
dsubren, dsuact, rxd1, txd1, gpio);
-- ddr0 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
datazz <= "HHHH";
ssram_adsp_n <= '1'; ssram_adv_n <= '1';
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => data,
iAddr => address(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_cen,
iCE2 => vcc, inCE3 => gnd, iZz => gnd);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, romsn, writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
d28d0c8c0e0b2bb8d8cf551dab423e58
| 0.582156 | 3.060809 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica04_OsciladorEnable/oscint.vhd
| 1 | 632 |
library ieee;
use ieee.std_logic_1164.all;
library lattice;
use lattice.components.all;
entity OSCINT is
port(
osc_dis: in std_logic;
tmr_rst: in std_logic;
osc_out: out std_logic;
tmr_out: out std_logic);
end;
architecture OSCIN of OSCINT is
component OSCTIMER
generic(TIMER_DIV: string);
port(
DYNOSCDIS: in std_logic;
TIMERRES: in std_logic;
OSCOUT: out std_logic;
TIMEROUT: out std_logic);
end component;
begin
inst00: OSCTIMER
generic map(TIMER_DIV => "1048576")
port map(
DYNOSCDIS => osc_dis,
TIMERRES => tmr_rst,
OSCOUT => osc_out,
TIMEROUT => tmr_out
);
end OSCIN;
|
apache-2.0
|
d8cbfb79d150b03fd868677960930299
| 0.672468 | 2.712446 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xup/ahbrom.vhd
| 3 | 6,755 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 368;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18E008";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"05000008";
when 16#00049# => romdata <= X"82100000";
when 16#0004A# => romdata <= X"3D1003FF";
when 16#0004B# => romdata <= X"BC17A3E0";
when 16#0004C# => romdata <= X"BC278001";
when 16#0004D# => romdata <= X"9C27A060";
when 16#0004E# => romdata <= X"03100000";
when 16#0004F# => romdata <= X"81C04000";
when 16#00050# => romdata <= X"01000000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"01000000";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"00000000";
when 16#00059# => romdata <= X"00000000";
when 16#0005A# => romdata <= X"00000000";
when 16#0005B# => romdata <= X"00000000";
when 16#0005C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
4ee2a51b9488f044e88ff31760cfcfa5
| 0.578534 | 3.308031 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3sl150/testbench.vhd
| 1 | 13,026 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Stratix-III LEON3 Demonstration design test bench
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1; -- number of ram banks
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
constant lresp : boolean := false;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal Rst : std_logic := '0'; -- Reset
signal clk : std_logic := '0';
signal clk125 : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal txd1, rxd1 : std_ulogic;
-- PSRAM and FLASH control
signal sram_advn : std_logic;
signal sram_csn : std_logic;
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector (0 to 3);
signal sram_oen : std_ulogic;
signal sram_clk : std_ulogic;
signal sram_adscn : std_ulogic;
signal sram_psn : std_ulogic;
signal sram_adv_n : std_ulogic;
signal sram_wait : std_logic_vector(1 downto 0);
signal flash_clk, flash_cen, max_csn : std_logic;
signal flash_advn, flash_oen, flash_resetn, flash_wen : std_logic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (8 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (15 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (2 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (71 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (71 downto 0); -- ddr data
--signal ddra_cke : std_logic;
--signal ddra_csb : std_logic;
--signal ddra_web : std_ulogic; -- ddr write enable
--signal ddra_rasb : std_ulogic; -- ddr ras
--signal ddra_casb : std_ulogic; -- ddr cas
--signal ddra_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddra_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrb_cke : std_logic;
--signal ddrb_csb : std_logic;
--signal ddrb_web : std_ulogic; -- ddr write enable
--signal ddrb_rasb : std_ulogic; -- ddr ras
--signal ddrb_casb : std_ulogic; -- ddr cas
--signal ddrb_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddrb_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrab_clk : std_logic_vector(1 downto 0);
--signal ddrab_clkb : std_logic_vector(1 downto 0);
--signal ddrab_odt : std_logic_vector(1 downto 0);
--signal ddrab_dqsp : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dqsn : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dm : std_logic_vector(1 downto 0); -- ddr dm
--signal ddrab_dq : std_logic_vector (15 downto 0);-- ddr data
-- Ethernet
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 4 * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
address(0) <= '0';
ddr_dq(71 downto dbits) <= (others => 'H');
ddr_dq2(71 downto dbits) <= (others => 'H');
ddr_dqsp(8 downto dbits/8) <= (others => 'H');
ddr_dqsn(8 downto dbits/8) <= (others => 'H');
ddr_rdqs(8 downto dbits/8) <= (others => 'H');
ddr_dm(8 downto dbits/8) <= (others => 'H');
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow, 50000, dbits)
port map (rst, clk, clk125, error, dsubren, dsuact,
-- rxd1, txd1,
gpio, address(25 downto 1), data, open,
sram_advn, sram_csn, sram_wen, sram_ben, sram_oen, sram_clk, sram_psn, sram_wait,
flash_clk, flash_advn, flash_cen, flash_oen, flash_resetn, flash_wen,
max_csn, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
open, open,
-- ddra_cke, ddra_csb, ddra_web, ddra_rasb, ddra_casb, ddra_ad(14 downto 0), ddra_ba, ddrb_cke,
-- ddrb_csb, ddrb_web, ddrb_rasb, ddrb_casb, ddrb_ad(14 downto 0), ddrb_ba, ddrab_clk, ddrab_clkb,
-- ddrab_odt, ddrab_dqsp, ddrab_dqsn, ddrab_dm, ddrab_dq,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n
);
ddr2delay : delay_wire
generic map(data_width => dbits, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => ddr_dq(dbits-1 downto 0), b => ddr_dq2(dbits-1 downto 0));
ddr0 : ddr2ram
generic map(width => dbits, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0),
odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm(dbits/8-1 downto 0), ba => ddr_ba(1 downto 0),
a => ddr_ad(12 downto 0), dq => ddr_dq2(dbits-1 downto 0),
dqs => ddr_dqsp(dbits/8-1 downto 0), dqsn =>ddr_dqsn(dbits/8-1 downto 0));
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, flash_cen, flash_wen, flash_oen);
-- -- 32 bit prom
-- prom0 : for i in 0 to 3 generate
-- sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
-- port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), flash_cen,
-- flash_wen, flash_oen);
-- end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), sram_csn,
sram_wen, sram_oen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, sram_oen, sram_wen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
284a474b25a3108efce3ef5900d18003
| 0.592047 | 3.039197 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2sgx90-av/config.vhd
| 1 | 7,127 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#02007A#;
constant CFG_ETH_ENL : integer := 16#CC0001#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
gpl-2.0
|
d44325dd4be06130ebc46a991b7287e7
| 0.654974 | 3.599495 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-cpci-xc4v/dprc_fir_demo/fir_v2.vhd
| 4 | 4,971 |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir
-- File: fir_v2.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter core (version 2) -- for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fir is
port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end fir;
architecture fir_rtl of fir is
type fsm_state is (idle, fill_sh, running, step);
type sh_type is array (0 to 9) of unsigned(7 downto 0);
type regs is record
state : fsm_state;
sh : sh_type;
cdata : unsigned(8 downto 0);
acc : unsigned(31 downto 0);
citer : unsigned(4 downto 0);
start : std_logic;
end record;
signal reg, reg_in : regs;
type coeffT is array (0 to 9) of unsigned(7 downto 0);
constant coeff : coeffT := (to_unsigned(21,8),to_unsigned(23,8),to_unsigned(21,8),to_unsigned(19,8),to_unsigned(13,8),to_unsigned(9,8),to_unsigned(13,8),to_unsigned(15,8),to_unsigned(21,8),to_unsigned(17,8));
begin
out_data <= std_logic_vector(reg.acc);
comb_proc: process(reg, start, in_data)
variable vreg : regs;
begin
vreg := reg;
in_data_read <= '0';
out_data_write <= '0';
case vreg.state is
when idle =>
if vreg.start='1' then
vreg.state := fill_sh;
in_data_read <= '1';
end if;
vreg.cdata := (others=>'0');
vreg.acc := (others=>'0');
vreg.citer := (others=>'0');
when fill_sh =>
if vreg.citer=9 then
vreg.state := running;
vreg.citer := (others=>'0');
else
in_data_read <= '1';
vreg.citer := vreg.citer + 1;
end if;
for i in 9 downto 1 loop --shift
vreg.sh(i) := vreg.sh(i-1);
end loop;
vreg.sh(0) := unsigned(in_data(7 downto 0));
when running =>
if vreg.citer=9 then
vreg.state := step;
in_data_read <= '1';
end if;
vreg.acc := vreg.acc + (vreg.sh(to_integer(vreg.citer))*coeff(to_integer(vreg.citer)));
vreg.citer := vreg.citer + 1;
when step =>
if vreg.cdata=90 then
vreg.state := idle;
else
vreg.state := running;
vreg.cdata := vreg.cdata + 1;
vreg.citer := (others=>'0');
vreg.acc := (others=>'0');
for i in 9 downto 1 loop --shift
vreg.sh(i) := vreg.sh(i-1);
end loop;
vreg.sh(0) := unsigned(in_data(7 downto 0));
end if;
out_data_write <= '1';
end case;
vreg.start := start;
reg_in <= vreg;
end process;
reg_proc: process(clk,rst)
begin
if (rst='1') then
reg.state <= idle;
for i in 0 to 9 loop
reg.sh(i) <= (others=>'0');
end loop;
reg.cdata <= (others=>'0');
reg.acc <= (others=>'0');
reg.citer <= (others=>'0');
reg.start <= '0';
elsif rising_edge(clk) then
reg <= reg_in;
end if;
end process;
end fir_rtl;
|
gpl-2.0
|
3801a2d17b7ea578b65ad90f025c4ec1
| 0.58278 | 3.783105 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-minimal/testbench.vhd
| 1 | 3,922 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
clkperiod : integer := 10 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rstn : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCE : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Output signals for LEDs
signal led : std_logic_vector(15 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
rstn <= not rst;
dsubre <= '0';
urxd <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech)
port map (
clk => clk,
btnCpuResetn => rstn,
-- PROM
address => address(22 downto 0),
data => data(31 downto 16),
RamOE => oen,
RamWE => writen,
RamCE => RamCE,
-- AHB Uart
RsRx => dsurx,
RsTx => dsutx,
-- Output signals for LEDs
led => led
);
sram0 : sram
generic map (index => 4, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(31 downto 24), RamCE, writen, oen);
sram1 : sram
generic map (index => 5, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(23 downto 16), RamCE, writen, oen);
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
end;
|
gpl-2.0
|
6069bc4a324979e93a9c89f78eb463de
| 0.576237 | 4.055843 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica02_Original/topadder4bit00txt.txt.vhd
| 1 | 2,811 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packagetopadder4bit00.all;
entity topadder4bit00 is
port(
SL: in std_logic ;
Ai: in std_logic_vector ( 3 downto 0 );
Bi: in std_logic_vector ( 3 downto 0 );
So: out std_logic_vector ( 3 downto 0 );
LED: out std_logic );
attribute loc: string;
attribute loc of SL: signal is "p104";
attribute loc of Ai: signal is "p125, p124, p123, p122";
attribute loc of Bi: signal is "p116, p115, p114, p113";
attribute loc of So: signal is "p24, p23, p22, p21";
attribute loc of LED: signal is "p12";
end;
architecture topadder4bit0 of topadder4bit00 is
signal SB, CS, SA: std_logic_vector(3 downto 0);
signal Sao: std_logic;
begin
U06: xor00 port map(Ax => SL,
Bx => Bi(0),
Yx => SB(0));
U07: xor00 port map(Ax => SL,
Bx => Bi(1),
Yx => SB(1));
U08: xor00 port map(Ax => SL,
Bx => Bi(2),
Yx => SB(2));
U09: xor00 port map(Ax => SL,
Bx => Bi(3),
Yx => SB(3));
U10: topfa4bit00 port map(C00 => SL,
A00 => Ai(0),
B00 => SB(0),
C01 => CS(0),
S00 => SA(0));
U11: topfa4bit00 port map(C00 => CS(0),
A00 => Ai(1),
B00 => SB(1),
C01 => CS(1),
S00 => SA(1));
U12: topfa4bit00 port map(C00 => CS(1),
A00 => Ai(2),
B00 => SB(2),
C01 => CS(2),
S00 => SA(2));
U13: topfa4bit00 port map(C00 => CS(2),
A00 => Ai(3),
B00 => SB(3),
C01 => CS(3),
S00 => SA(3));
U14: and00 port map(Aa => Sao,
Ba => SA(0),
Ya => So(0));
U15: and00 port map(Aa => Sao,
Ba => SA(1),
Ya => So(1));
U16: and00 port map(Aa => Sao,
Ba => SA(2),
Ya => So(2));
U17: and00 port map(Aa => Sao,
Ba => SA(3),
Ya => So(3));
U18: nxor00 port map(Anx => CS(3),
Bnx => CS(2),
Ynx => Sao);
U19: xor00 port map(Ax => CS(3),
Bx => CS(2),
Yx => LED);
end topadder4bit0;
|
apache-2.0
|
ab1eefe87c0a21244e17ebb47be9555d
| 0.373888 | 3.748 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/regfile_3p_l3.vhd
| 1 | 3,248 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: regfile_3p_l3
-- File: regfile_3p_l3.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: 3-port regfile implemented with two 2-port rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library techmap;
use techmap.gencomp.all;
use grlib.stdlib.all;
entity regfile_3p_l3 is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64;
testen : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of regfile_3p_l3 is
constant rfinfer : boolean := (regfile_3p_infer(tech) = 1);
signal wd1, wd2 : std_logic_vector((dbits -1 + 8) downto 0);
signal e1, e2 : std_logic_vector((dbits-1) downto 0);
signal we1, we2 : std_ulogic;
signal vcc, gnd : std_ulogic;
signal vgnd : std_logic_vector(dbits-1 downto 0);
signal write2, renable2 : std_ulogic;
begin
vcc <= '1'; gnd <= '0'; vgnd <= (others => '0');
we1 <= we
;
we2 <= we
;
s0 : if rfinfer generate
inf : regfile_3p generic map (0, abits, dbits, wrfst, numregs, testen, memtest_vlen)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2,
testin
);
end generate;
s1 : if not rfinfer generate
rhu : regfile_3p generic map (tech, abits, dbits, wrfst, numregs, testen, memtest_vlen)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2,
testin
);
end generate;
end;
|
gpl-2.0
|
a94be9fb87582a764026b81228a1a003
| 0.596983 | 3.641256 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/cypress/ssram/cy7c1354b.vhd
| 4 | 16,375 |
-----------------------------------------------------------------------------------------
--
-- File Name: CY7C1354B.VHD
-- Version: 2.0
-- Date: Nov 22nd, 2004
-- Model: BUS Functional
--
--
-- Author: RKF
-- Company: Cypress Semiconductor
-- Model: CY7C1354B (256k x 36)
-- Mode: Pipelined
--
-- Description: NoBL SRAM VHDL Model
--
-- Limitation: None
--
-- Note: - BSDL Model available separately
-- - Set simulator resolution to "ps" timescale
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 2004 Cypress Semiconductor
-- All rights reserved
--
-- Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor
--
-- Rev Author Date Changes
-- --- -------- ------- ----------
-- 2.0 RKF 11/22/2004 - Second Release
-- - Fully Tested with New Test Bench and Test Vectors
-----------------------------------------------------------------------------------------
LIBRARY ieee,work,grlib;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
-- Use work.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use ieee.std_logic_1164.all;
use std.textio.all;
ENTITY cy7c1354 IS
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant parameters
addr_bits : INTEGER := 18;
data_bits : INTEGER := 36;
-- Timing parameters for -5 (225 Mhz)
tCYC : TIME := 4.4 ns;
tCH : TIME := 1.8 ns;
tCL : TIME := 1.8 ns;
tCO : TIME := 2.8 ns;
tAS : TIME := 1.4 ns;
tCENS : TIME := 1.4 ns;
tWES : TIME := 1.4 ns;
tDS : TIME := 1.4 ns;
tAH : TIME := 0.4 ns;
tCENH : TIME := 0.4 ns;
tWEH : TIME := 0.4 ns;
tDH : TIME := 0.4 ns
-- Timing parameters for -5 (200 Mhz)
--tCYC : TIME := 5.0 ns;
--tCH : TIME := 2.0 ns;
--tCL : TIME := 2.0 ns;
--tCO : TIME := 3.2 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
-- Timing parameters for -5 (166 Mhz)
--tCYC : TIME := 6.0 ns;
--tCH : TIME := 2.4 ns;
--tCL : TIME := 2.4 ns;
--tCO : TIME := 3.5 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
);
-- Port Declarations
PORT (
Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O
Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address
Mode : IN STD_LOGIC := '1'; -- Burst Mode
Clk : IN STD_LOGIC; -- Clk
CEN_n : IN STD_LOGIC; -- CEN#
AdvLd_n : IN STD_LOGIC; -- Adv/Ld#
Bwa_n : IN STD_LOGIC; -- Bwa#
Bwb_n : IN STD_LOGIC; -- BWb#
Bwc_n : IN STD_LOGIC; -- Bwc#
Bwd_n : IN STD_LOGIC; -- BWd#
Rw_n : IN STD_LOGIC; -- RW#
Oe_n : IN STD_LOGIC; -- OE#
Ce1_n : IN STD_LOGIC; -- CE1#
Ce2 : IN STD_LOGIC; -- CE2
Ce3_n : IN STD_LOGIC; -- CE3#
Zz : IN STD_LOGIC -- Snooze Mode
);
END cy7c1354;
ARCHITECTURE behave OF cy7c1354 IS
SIGNAL ce : STD_LOGIC := '0';
SIGNAL doe : STD_LOGIC := '0';
SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
BEGIN
ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2;
doe <= NOT(Oe_n) AND NOT(Zz);
-- Output Buffers
WITH doe SELECT
Dq <= TRANSPORT dout AFTER (tCO) WHEN '1',
(OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
-- Check for Clock Timing Violation
-- clk_check : PROCESS
-- VARIABLE clk_high, clk_low : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF Clk = '1' AND NOW >= tCYC THEN
-- ASSERT (NOW - clk_low >= tCH)
-- REPORT "Clk width low - tCH violation"
-- SEVERITY ERROR;
-- ASSERT (NOW - clk_high >= tCYC)
-- REPORT "Clk period high - tCYC violation"
-- SEVERITY ERROR;
-- clk_high := NOW;
-- ELSIF Clk = '0' AND NOW /= 0 ns THEN
-- ASSERT (NOW - clk_high >= tCL)
-- REPORT "Clk width high - tCL violation"
-- SEVERITY ERROR;
-- ASSERT (NOW - clk_low >= tCYC)
-- REPORT "Clk period low - tCYC violation"
-- SEVERITY ERROR;
-- clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT (Addr'LAST_EVENT >= tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (CEN_n'LAST_EVENT >= tCENS)
REPORT "CKE# - tCENS violation"
SEVERITY ERROR;
ASSERT (Ce1_n'LAST_EVENT >= tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (Ce2'LAST_EVENT >= tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (Ce3_n'LAST_EVENT >= tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (AdvLd_n'LAST_EVENT >= tWES)
REPORT "ADV/LD# - tWES violation"
SEVERITY ERROR;
ASSERT (Rw_n'LAST_EVENT >= tWES)
REPORT "RW# - tWES violation"
SEVERITY ERROR;
ASSERT (Bwa_n'LAST_EVENT >= tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (Bwb_n'LAST_EVENT >= tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (Bwc_n'LAST_EVENT >= tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (Bwd_n'LAST_EVENT >= tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
--ASSERT (Dq'LAST_EVENT >= tDS)
-- REPORT "Dq - tDS violation"
-- SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH);
IF Clk'DELAYED(tAH) = '1' THEN
ASSERT (Addr'LAST_EVENT > tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF Clk'DELAYED(tCENH) = '1' THEN
ASSERT (CEN_n'LAST_EVENT > tCENH)
REPORT "CKE# - tCENH violation"
SEVERITY ERROR;
END IF;
--IF Clk'DELAYED(tDH) = '1' THEN
-- ASSERT (Dq'LAST_EVENT > tDH)
-- REPORT "Dq - tDH violation"
-- SEVERITY ERROR;
--END IF;
IF Clk'DELAYED(tWEH) = '1' THEN
ASSERT (Ce1_n'LAST_EVENT > tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (Ce2'LAST_EVENT > tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (Ce3_n'LAST_EVENT > tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (AdvLd_n'LAST_EVENT > tWEH)
REPORT "ADV/LD# - tWEH violation"
SEVERITY ERROR;
ASSERT (Rw_n'LAST_EVENT > tWEH)
REPORT "RW# - tWEH violation"
SEVERITY ERROR;
ASSERT (Bwa_n'LAST_EVENT > tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (Bwb_n'LAST_EVENT > tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (Bwc_n'LAST_EVENT > tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (Bwd_n'LAST_EVENT > tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Main Program
main : PROCESS
-- TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits / 4) - 1 DOWNTO 0);
TYPE memory_array IS ARRAY (0 TO (2**addr_bits) - 1) OF STD_LOGIC_VECTOR ((data_bits / 4) - 1 DOWNTO 0);
VARIABLE Addr_in : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
VARIABLE first_Addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Addr_read : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
VARIABLE Addr_write : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0';
VARIABLE bank0 : memory_array;
VARIABLE bank1 : memory_array;
VARIABLE bank2 : memory_array;
VARIABLE bank3 : memory_array;
VARIABLE ce_in : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE rw_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "111";
VARIABLE bwa_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
VARIABLE bwb_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
VARIABLE bwc_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
VARIABLE bwd_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
VARIABLE bcnt : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
BEGIN
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := '0' & recdata((i*32) to (i*32+7));
bank2 (ai+i) := '0' & recdata((i*32+8) to (i*32+8+7));
bank1 (ai+i) := '0' & recdata((i*32+16) to (i*32+16+7));
bank0 (ai+i) := '0' & recdata((i*32+24) to (i*32+24+7));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
WAIT ON Clk;
IF Clk'EVENT AND Clk = '1' THEN
IF CEN_n = '0' AND Zz = '0' THEN
-- Write Address Register
Addr_write := Addr_read;
-- Read Address Register
Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0;
-- Address Register
IF AdvLd_n = '0' and ce = '1' THEN
Addr_in := Addr;
first_Addr := Addr(1 DOWNTO 0);
bcnt := Addr(1 DOWNTO 0);
END IF;
-- Burst Logic
IF Mode = '0' AND AdvLd_n = '1' THEN
bcnt := bcnt + 1;
ELSIF Mode = '1' AND AdvLd_n = '1' THEN
IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN
bcnt := bcnt + 1;
ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN
bcnt := bcnt - 1;
END IF;
END IF;
bAddr1 := bcnt (1);
bAddr0 := bcnt (0);
-- Read Logic
ce_in (0) := ce_in (1);
IF AdvLd_n = '0' THEN
ce_in (1) := ce;
END IF;
rw_in (0) := rw_in (1);
rw_in (1) := rw_in (2);
IF AdvLd_n = '0' THEN
rw_in (2) := NOT(ce AND NOT(Rw_n));
END IF;
-- Write Registry and Data Coherency Control Logic
bwa_in (0) := bwa_in (1);
bwb_in (0) := bwb_in (1);
bwc_in (0) := bwc_in (1);
bwd_in (0) := bwd_in (1);
bwa_in (1) := bwa_in (2);
bwb_in (1) := bwb_in (2);
bwc_in (1) := bwc_in (2);
bwd_in (1) := bwd_in (2);
bwa_in (2) := Bwa_n;
bwb_in (2) := Bwb_n;
bwc_in (2) := Bwc_n;
bwd_in (2) := Bwd_n;
-- Write Data to Memory
IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN
bank0 (CONV_INTEGER1 (Addr_write)) := '0' & Dq ( ((data_bits-4) / 4) - 1 DOWNTO 0);
END IF;
IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN
bank1 (CONV_INTEGER1 (Addr_write)) := '0' & Dq (((data_bits-4) / 2 - 1) DOWNTO ((data_bits-4) / 4));
END IF;
IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN
bank2 (CONV_INTEGER1 (Addr_write)) := '0' & Dq ((3 * ((data_bits-4) / 4)) - 1 DOWNTO ((data_bits-4) / 2));
END IF;
IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN
bank3 (CONV_INTEGER1 (Addr_write)) := '0' & Dq ((data_bits-4) - 1 DOWNTO (3 * ((data_bits-4) / 4)));
END IF;
END IF;
Addr_read_sig <= Addr_read;
-- Read Data from Memory Array
IF ce_in (0) = '1' AND rw_in (1) = '1' THEN
dout (((data_bits-4) / 4) - 1 DOWNTO 0) <= bank0 (CONV_INTEGER1 (Addr_read))(7 downto 0);
dout (((data_bits-4) / 2 - 1) DOWNTO ((data_bits-4) / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))(7 downto 0);
dout ((3 * ((data_bits-4) / 4)) - 1 DOWNTO ((data_bits-4) / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))(7 downto 0);
dout ((data_bits-4) - 1 DOWNTO (3 * ((data_bits-4) / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))(7 downto 0);
-- dout ((data_bits / 4) - 1 DOWNTO 0) <= bank0 (CONV_INTEGER1 (Addr_read));
-- dout ((data_bits / 2 - 1) DOWNTO (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read));
-- dout ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read));
-- dout (data_bits - 1 DOWNTO (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read));
ELSE
dout <= (OTHERS => 'Z');
END IF;
END IF;
END PROCESS;
END behave;
|
gpl-2.0
|
8b4e12afe9b5b0c15698c47f2d4d3ae2
| 0.448733 | 3.534427 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-nuhorizons-3s1500/leon3mp.vhd
| 1 | 24,538 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(7 downto 0);
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_ulogic;
signal lclk, pci_lclk, sdfb : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal resetn : std_ulogic;
signal pbsw : std_logic_vector(4 downto 1);
signal ledo : std_logic_vector(8 downto 1);
signal memi : memory_in_type;
signal memo : memory_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal s_eth_din : std_logic_vector(31 downto 0);
constant ahbmmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+ CFG_GRETH;
constant BOARD_FREQ : integer := 50000; -- board frequency in KHz
constant CPU_FREQ : integer := (BOARD_FREQ*CFG_CLKMUL)/CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
sdram_clk_pad : skew_outpad
generic map (tech => padtech, slew => 1, strength => 24, skew => -60)
port map (sdram_clk, sdclkl, rstn);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
resetn <= pbsw(4);
ledo(2) <= not cgo.clklock;
ledo(3) <= pbsw(3);
clk_pad : clkpad generic map (tech => padtech) port map (pll_clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
nahbm => ahbmmax, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
ledo(8) <= dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1'; dsui.break <= pbsw(1); ledo(1) <= not dsuo.active;
end generate;
end generate;
nodcom : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= u2i.rxd; u2o.txd <= duo.txd; u2o.rtsn <= gnd(0);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- PROM/SDRAM Memory controller ------------------------------------
----------------------------------------------------------------------
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
memi.bwidth <= "00" when CFG_MCTRL_RAM16BIT = 0 else "01";
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : entity work.smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0),
wpo, sdo, s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe, s_eth_din);
addr_pad : outpadv generic map (width => 21, tech => padtech)
port map (flash_a(20 downto 0), memo.address(21 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
rom8 : if CFG_MCTRL_RAM16BIT = 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (flash_d(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
data15_pad : iopad generic map (tech => padtech)
port map (flash_d(15), memo.address(0), gnd(0), open);
end generate;
rom16 : if CFG_MCTRL_RAM16BIT = 1 generate
data_pad : iopadv generic map (tech => padtech, width => 16)
port map (flash_d(15 downto 0), memo.data(31 downto 16),
memo.bdrive(0), memi.data(31 downto 16));
end generate;
sa_pad : outpadv generic map (width => 12, tech => padtech)
port map (sdram_a, memo.sa(11 downto 0));
sba1_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdram_ba(1 downto 0), memo.sa(14 downto 13));
sba2_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdram_ba(3 downto 2), memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sdram_d(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
end generate;
sdcke_pad : outpad generic map (tech => padtech)
port map (sdram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (sdram_wen, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdram_csn, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (sdram_rasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdram_casn, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (sdram_dqm, sdo.dqm(3 downto 0));
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (sdram_cke, gnd(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdram_csn, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 4, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(4));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(4) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts, u1o.rtsn);
ua2 : if (CFG_UART2_ENABLE /= 0) and (CFG_AHB_UART = 0) generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
ua2rx_pad : inpad generic map (tech => padtech) port map (uart2_rxd, u2i.rxd);
ua2tx_pad : outpad generic map (tech => padtech) port map (uart2_txd, u2o.txd);
ua2cts_pad : inpad generic map (tech => padtech) port map (uart2_cts, u2i.ctsn);
ua2rts_pad : outpad generic map (tech => padtech) port map (uart2_rts, u2o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if CFG_GRETH = 0 generate -- no eth
etho <= eth_out_none;
end generate;
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 0)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 0)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
ereset_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- I/O interface ---------------------------------------------------
-----------------------------------------------------------------------
pb_sw_pad : inpadv generic map (width => 4, tech => padtech)
port map (pb_sw, pbsw);
led_pad : outpadv generic map (width => 8, tech => padtech)
port map (led, ledo);
rom8 : if CFG_MCTRL_RAM16BIT = 0 generate
byte_pad : outpad generic map (tech => padtech) port map (flash_byte, gnd(0));
end generate;
rom16 : if CFG_MCTRL_RAM16BIT = 1 generate
byte_pad : outpad generic map (tech => padtech) port map (flash_byte, vcc(0));
end generate;
rpn_pad : outpad generic map (tech => padtech) port map (flash_rpn, rstn);
wpn_pad : outpad generic map (tech => padtech) port map (flash_wpn, vcc(0));
ready_pad : inpad generic map (tech => padtech) port map (flash_ready, open);
smsc_data_pads : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (smsc_data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), s_eth_din(31-i*8 downto 24-i*8));
end generate;
smsc_addr_pad : outpadv generic map (tech => padtech, width => 15)
port map (smsc_addr, memo.address(15 downto 1));
smsc_nbe_pad : outpadv generic map (tech => padtech, width => 4)
port map (smsc_nbe, s_eth_nbe);
smsc_reset_pad : outpad generic map (tech => padtech)
port map (smsc_resetn, rstn);
smsc_nrd_pad : outpad generic map (tech => padtech)
port map (smsc_nrd, s_eth_readn);
smsc_nwr_pad : outpad generic map (tech => padtech)
port map (smsc_nwr, s_eth_writen);
smsc_ncs_pad : outpad generic map (tech => padtech)
port map (smsc_ncs, memo.iosn);
smsc_aen_pad : outpad generic map (tech => padtech)
port map (smsc_aen, s_eth_aen);
smsc_lclk_pad : outpad generic map (tech => padtech)
port map (smsc_lclk, vcc(0));
smsc_wnr_pad : outpad generic map (tech => padtech)
port map (smsc_wnr, vcc(0));
smsc_rdyrtn_pad : outpad generic map (tech => padtech)
port map (smsc_rdyrtn, vcc(0));
smsc_cycle_pad : outpad generic map (tech => padtech)
port map (smsc_cycle, vcc(0));
smsc_nads_pad : outpad generic map (tech => padtech)
port map (smsc_nads, gnd(0));
-- lcd_data_pad : iopadv generic map (width => 8, tech => padtech)
-- port map (lcd_data, nuo.lcd_data, nuo.lcd_ben, nui.lcd_data);
-- lcd_rs_pad : outpad generic map (tech => padtech)
-- port map (lcd_rs, nuo.lcd_rs);
-- lcd_rw_pad : outpad generic map (tech => padtech)
-- port map (lcd_rw, nuo.lcd_rw );
-- lcd_en_pad : outpad generic map (tech => padtech)
-- port map (lcd_en, nuo.lcd_en);
-- lcd_backl_pad : outpad generic map (tech => padtech)
-- port map (lcd_backl, nuo.lcd_backl);
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Nuhorizon SP3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
2c486b9c03a74adaab26377b779f5846
| 0.567528 | 3.445864 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/iopad_ddr.vhd
| 1 | 4,948 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ddr, iopad_ddrv, iopad_ddrvv
-- File: iopad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates an iopad connected to DDR register.
-- Special case for easic90 tech since this tech requires that
-- oe is directly connected between DDR register and pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity iopad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
oepol : integer := 0);
port (
pad : inout std_ulogic;
i1, i2 : in std_ulogic; -- Input H and L
en : in std_ulogic; -- Output enable
o1, o2 : out std_ulogic; -- Output H and L
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddr is
signal oe, oen, d, q : std_ulogic;
begin
def: if (tech /= easic90) generate
p : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad, q, en, d);
ddrregi : ddr_ireg generic map (tech)
port map (o1, o2, c1, c2, ce, d, r, s);
ddrrego : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
oe <= '0'; oen <= '0'; -- Not used in this configuration
end generate def;
nex : if (tech = easic90) generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
p : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, q, oe, d);
ddrregi : nextreme_iddr_reg
port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r);
ddrrego : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => oen, q => q,
oe => oe, rstb => r);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en, o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrvv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en(j), o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
|
gpl-2.0
|
bf5891d82acc56d2df6839a2f86cb3f4
| 0.581043 | 3.382092 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/clkgen_stratixiii.vhd
| 1 | 7,254 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity stratix3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of stratix3_pll is
component altpll
generic (
intended_device_family : string := "Stratix III" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0";
inclk0_input_frequency : positive;
width_clock : positive := 10;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (9 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal fb : std_logic;
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix III",
--operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 10, compensate_clock => "CLK1",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 10,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_stratixiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_stratixiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : stratix3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_stratixiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_stratixiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
gpl-2.0
|
bb2bc015b84aa6d1ede4a236215c78ad
| 0.586022 | 3.492537 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica03_Oscilador/div00txt.vhd
| 1 | 654 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div00 is
port(
clkdiv: in std_logic;
outdiv: out std_logic);
end;
architecture div0 of div00 is
signal sdiv: std_logic_vector(11 downto 0);
begin
pdiv: process()
begin
if (clkdiv'event and clkdiv = '1') then
if (sdiv < "100000000000") then
outdiv <= '1';
sdiv <= sdiv + 1;
elsif (sdiv > "100000000000") then
outdiv <= '0';
sdiv <= sdiv + 1;
end if;
end if;
end process pdiv;
end div0;
|
apache-2.0
|
d578f8ffa38039152a3b52313047cc92
| 0.536697 | 3.593407 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/adq_dqs/bidir_dqs_iobuf_inst.vhd
| 3 | 9,271 |
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="TRUE" USE_DYNAMIC_TERMINATION_CONTROL="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataio_b dataout dynamicterminationcontrol dynamicterminationcontrol_b oe oe_b
--VERSION_BEGIN 8.0SP1 cbx_altiobuf_in 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratixiii 2008:06:18:296807 VERSION_END
LIBRARY stratixiii;
USE stratixiii.all;
--synthesis_resources = stratixiii_io_ibuf 1 stratixiii_io_obuf 2 stratixiii_pseudo_diff_out 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bidir_dqs_iobuf_inst_iobuf_bidir_fkv IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio_b : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dynamicterminationcontrol : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
dynamicterminationcontrol_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1')
);
END bidir_dqs_iobuf_inst_iobuf_bidir_fkv;
ARCHITECTURE RTL OF bidir_dqs_iobuf_inst_iobuf_bidir_fkv IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_ibufa_o : STD_LOGIC;
SIGNAL wire_obuf_ba_o : STD_LOGIC;
SIGNAL wire_obufa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_obar : STD_LOGIC;
COMPONENT stratixiii_io_ibuf
GENERIC
(
bus_hold : STRING := "false";
differential_mode : STRING := "false";
lpm_type : STRING := "stratixiii_io_ibuf"
);
PORT
(
i : IN STD_LOGIC := '0';
ibar : IN STD_LOGIC := '0';
o : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_io_obuf
GENERIC
(
bus_hold : STRING := "false";
open_drain_output : STRING := "false";
shift_series_termination_control : STRING := "false";
--sim_dynamic_termination_control_is_connected : STRING := "false";
lpm_type : STRING := "stratixiii_io_obuf"
);
PORT
(
dynamicterminationcontrol : IN STD_LOGIC := '0';
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT stratixiii_pseudo_diff_out
PORT
(
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataio(0) <= wire_obufa_o;
dataio_b(0) <= wire_obuf_ba_o;
dataout(0) <= wire_ibufa_o;
ibufa : stratixiii_io_ibuf
GENERIC MAP (
bus_hold => "false"
)
PORT MAP (
i => dataio(0),
ibar => dataio_b(0),
o => wire_ibufa_o
);
obuf_ba : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
dynamicterminationcontrol => dynamicterminationcontrol_b(0),
i => wire_pseudo_diffa_obar,
o => wire_obuf_ba_o,
oe => oe_b(0)
);
obufa : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
dynamicterminationcontrol => dynamicterminationcontrol(0),
i => wire_pseudo_diffa_o,
o => wire_obufa_o,
oe => oe(0)
);
pseudo_diffa : stratixiii_pseudo_diff_out
PORT MAP (
i => datain(0),
o => wire_pseudo_diffa_o,
obar => wire_pseudo_diffa_obar
);
END RTL; --bidir_dqs_iobuf_inst_iobuf_bidir_fkv
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bidir_dqs_iobuf_inst IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dyn_term_ctrl : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dyn_term_ctrl_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio_b : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END bidir_dqs_iobuf_inst;
ARCHITECTURE RTL OF bidir_dqs_iobuf_inst IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT bidir_dqs_iobuf_inst_iobuf_bidir_fkv
PORT (
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio_b : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dynamicterminationcontrol_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dynamicterminationcontrol : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(0 DOWNTO 0);
bidir_dqs_iobuf_inst_iobuf_bidir_fkv_component : bidir_dqs_iobuf_inst_iobuf_bidir_fkv
PORT MAP (
datain => datain,
dynamicterminationcontrol_b => dyn_term_ctrl_b,
oe => oe,
oe_b => oe_b,
dynamicterminationcontrol => dyn_term_ctrl,
dataout => sub_wire0,
dataio => dataio,
dataio_b => dataio_b
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "TRUE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
-- Retrieval info: USED_PORT: dataio 0 0 1 0 BIDIR NODEFVAL "dataio[0..0]"
-- Retrieval info: USED_PORT: dataio_b 0 0 1 0 BIDIR NODEFVAL "dataio_b[0..0]"
-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
-- Retrieval info: USED_PORT: dyn_term_ctrl 0 0 1 0 INPUT NODEFVAL "dyn_term_ctrl[0..0]"
-- Retrieval info: USED_PORT: dyn_term_ctrl_b 0 0 1 0 INPUT NODEFVAL "dyn_term_ctrl_b[0..0]"
-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
-- Retrieval info: USED_PORT: oe_b 0 0 1 0 INPUT NODEFVAL "oe_b[0..0]"
-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
-- Retrieval info: CONNECT: @dynamicterminationcontrol_b 0 0 1 0 dyn_term_ctrl_b 0 0 1 0
-- Retrieval info: CONNECT: @dynamicterminationcontrol 0 0 1 0 dyn_term_ctrl 0 0 1 0
-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
-- Retrieval info: CONNECT: @oe_b 0 0 1 0 oe_b 0 0 1 0
-- Retrieval info: CONNECT: dataio_b 0 0 1 0 @dataio_b 0 0 1 0
-- Retrieval info: CONNECT: dataio 0 0 1 0 @dataio 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst.cmp FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst_inst.vhd FALSE FALSE
-- Retrieval info: LIB_FILE: stratixiii
|
gpl-2.0
|
69fb5c70c83580f1a76270cd0838e11a
| 0.647287 | 3.299288 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-atlys/config.vhd
| 1 | 7,346 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020765#;
constant CFG_ETH_ENL : integer := 16#003456#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (16);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 16;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#03#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (30000);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
9f158dfdff50fbd8f4cf59d4f8c36ec4
| 0.650422 | 3.567751 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/esa/memoryctrl/mctrl.in.vhd
| 6 | 635 |
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
|
gpl-2.0
|
294ceabc775906efc80a8c94631e32a0
| 0.710236 | 3.469945 | false | true | false | false |
rhexsel/cmips
|
cMIPS/vhdl/io.vhd
| 1 | 41,541 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: from_stdin
-- read a signle character from stdout
-- returns LF ('\n'=0x0a) if there are no charachters on input
-- on the first ever read, returna LF on the empty line read
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out reg32);
end from_stdin;
architecture simulation of from_stdin is
begin
U_READ_IN: process(clk,sel)
variable L : line;
variable this : character;
variable good : boolean := FALSE;
begin
if falling_edge(clk) and sel = '0' then
read(L, this, good);
if not(good) then
readline(input, L);
this := LF;
end if;
data <= x"000000" & std_logic_vector(to_unsigned(character'pos(this),8));
assert TRUE report "STD_IOrd= " & this;
end if;
end process U_READ_IN;
end architecture simulation;
-- ++ from_stdin +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of from_stdin is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: print_data
-- print an integer to stdout, 32bit hexadecimal
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in reg32);
end print_data;
architecture simulation of print_data is
file output : text open write_mode is "STD_OUTPUT";
begin
U_WRITE_OUT: process(sel,clk)
variable msg : line;
begin
if falling_edge(clk) and sel = '0' then
write ( msg, string'(SLV32HEX(data)) );
writeline( output, msg );
end if;
end process U_WRITE_OUT;
end architecture simulation;
-- ++ print_data +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of print_data is
begin
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: to_stdout
-- print a signle character to stdout
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end to_stdout;
architecture simulation of to_stdout is
file output : text open write_mode is "STD_OUTPUT";
begin
U_WRITE_OUT: process(clk,sel)
variable msg : line;
begin
if falling_edge(clk) and sel = '0' then
if (data(7 downto 0) = x"00") or (data(7 downto 0) = x"0a") then
writeline( output, msg );
else
write(msg, character'val(to_integer( unsigned(data(7 downto 0)))));
end if;
end if;
end process U_WRITE_OUT;
end architecture simulation;
-- ++ to_stdout +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of to_stdout is
begin
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: write_data_to_file
-- write one 32bit integer to file "output.data"
-- if( addr(3 downto 0) ) = "0000" then write to file
-- if( addr(3 downto 0) ) = "0100" then close file
-- if( addr(3 downto 0) ) = "0111" then assert dump_ram
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity write_data_file is
generic (OUTPUT_FILE_NAME : string := "output.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : in reg32;
byte_sel : in reg4;
dump_ram : out std_logic);
end write_data_file;
architecture simulation of write_data_file is
type uint_file_type is file of integer;
file output_file: uint_file_type open write_mode is OUTPUT_FILE_NAME;
begin
U_write_uint: process (clk,sel)
begin
dump_ram <= '0';
if falling_edge(clk) and sel = '0' then
if addr(3 downto 0) = b"0000" then -- data write
if wr = '0' then
write( output_file, to_integer(signed(data)) );
assert TRUE report "IOwr[" & SLV32HEX(addr) &"]:" & SLV32HEX(data);
end if;
elsif addr(3 downto 0) = b"0100" then -- close output file
file_close(output_file);
elsif addr(3 downto 0) = b"0111" then -- dump RAM
dump_ram <= '1';
end if;
end if;
end process U_write_uint;
end architecture simulation; -- write_file_data
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of write_data_file is
begin
dump_ram <= 'X';
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: read_data_file
-- read one 32bit integer from file "input.data"
-- if not EOF then write data to file
-- else status <= 1
-- on a read, return last status (EOF=1 or otherwise=0)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity read_data_file is
generic (INPUT_FILE_NAME : string := "input.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : out reg32;
byte_sel : in reg4);
end read_data_file;
architecture simulation of read_data_file is
type uint_file_type is file of integer;
file input_file: uint_file_type open read_mode is INPUT_FILE_NAME;
signal status : reg32 := (others => '0');
begin
U_read_uint: process(clk,sel)
variable datum : integer := 0;
variable value : reg32; -- for debugging only
begin
data <= (others => 'X');
if falling_edge(clk) and sel = '0' then
if addr(3 downto 0) = b"0000" then -- data read
if wr = '1' then
if not endfile(input_file) then
read( input_file, datum );
data <= std_logic_vector(to_unsigned(datum, 32));
status <= x"00000000"; -- NOT_EndOfFile
value := std_logic_vector(to_unsigned(datum, 32)); -- DEBUG
assert TRUE report "IOrd[" & SLV32HEX(addr) &"]:"& SLV32HEX(value);
else
status <= x"00000001"; -- EndOfFile
end if;
else
data <= (others => 'X');
end if;
else -- status read
if wr = '1' then
data <= status;
else
data <= (others => 'X');
end if;
end if;
end if;
end process U_read_uint;
end architecture simulation;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of read_data_file is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: generate interrupt after N clock cycles
-- Generates an interrupt after N cycles, N <= 2**30
-- Counting stops on reaching limit stored to counter.
-- data(31) = 1 enables interrupt on reaching limit;
-- data(31) = 0 disables interrupts
-- data(30) = 1 enables counting
-- data(30) = 0 stops counter and delays interrupt (forever?)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity do_interrupt is
port (rst : in std_logic;
clk : in std_logic; -- clock pulses counted
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
constant NUM_BITS : integer := 30;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant START_COUNT : c_width := (others => '0');
end do_interrupt;
architecture behavioral of do_interrupt is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component countNup is
generic (NUM_BITS: integer);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector;
co: out std_logic);
end component countNup;
component FFDsimple is
port(clk, rst : in std_logic;
D : in std_logic;
Q : out std_logic);
end component FFDsimple;
signal Dlimit, Qlimit, Q: c_width;
signal ld_cnt, ld_reg, en, cnt_en, int_en, equals : std_logic;
signal i_ena, c_ena : std_logic;
begin
ld_reg <= wr when sel = '0' else '1';
ld_cnt <= not ld_reg;
Dlimit <= data_inp(NUM_BITS-1 downto 0);
U_LIMIT: registerN generic map (NUM_BITS, START_COUNT)
port map (clk, rst, ld_reg, Dlimit, Qlimit);
en <= cnt_en and (not equals);
U_COUNTER: countNup generic map (NUM_BITS)
port map (clk, rst, ld_cnt, en, START_COUNT, Q, open);
c_ena <= data_inp(30) when (sel='0' and wr='0') else cnt_en;
U_COUNT_EN: FFDsimple port map (clk, rst, c_ena, cnt_en);
i_ena <= data_inp(31) when (sel='0' and wr='0') else int_en;
U_INTERR_EN: FFDsimple port map (clk, rst, i_ena, int_en);
equals <= '1' when (Q = Qlimit(NUM_BITS-1 downto 0) ) else '0';
irq <= '1' when (equals = '1' and int_en = '1') else '0';
data_out <= int_en & cnt_en & Q;
end behavioral;
-- ++ do_interrupt +++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: simple UART bus interface (a wrapper to the real UART)
-- 8 data bits, no parity, 1 stop bit (8N1), catches: framing, overrun
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity simple_uart is
port (rst : in std_logic;
clk : in std_logic; -- processor clock
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic; -- serial transmission (output)
rxdat : in std_logic; -- serial reception (input)
rts : out std_logic;
cts : in std_logic;
irq : out std_logic; -- interrupt request
bit_rt : out std_logic_vector); -- communication speed; for TB only
end simple_uart;
architecture behavioral of simple_uart is
component uart_int is
port(clk, rst: in std_logic;
s_ctrlwr, s_stat : in std_logic; -- select registers
s_tx, s_rx : in std_logic; -- select registers
s_intwr, s_intrd : in std_logic; -- select interrupt register
d_inp: in std_logic_vector; -- 32 bit input
d_out: out std_logic_vector; -- 32 bit output
txdat: out std_logic; -- serial transmission (output)
rxdat: in std_logic; -- serial reception (input)
rts: out std_logic;
cts: in std_logic;
irq_all: out std_logic; -- interrupt request
bit_rt: out std_logic_vector); -- communication speed - for TB only
end component uart_int;
signal s_ctrlwr, s_stat, s_tx, s_rx, s_intwr, s_intrd : std_logic;
signal d_inp, d_out : reg32;
begin
U_UART: uart_int port map (clk, rst, s_ctrlwr, s_stat, s_tx, s_rx,
s_intwr, s_intrd,
d_inp,d_out, txdat,rxdat, rts,cts, irq, bit_rt);
-- a3a2 wr register (aligned to word addresses)
-- 00 0 control, W+r IO_UART_ADDR +0
-- 01 x status, R IO_UART_ADDR +4
-- 10 0 interrupt conmtrol W IO_UART_ADDR +8
-- 10 1 interrupt conmtrol R IO_UART_ADDR +8
-- 11 0 transmission W IO_UART_ADDR +12
-- 11 1 reception R IO_UART_ADDR +12
s_ctrlwr <= '1' when sel = '0' and addr = b"00" and wr = '0' else '0'; -- W
s_stat <= '1' when sel = '0' and addr = b"01" else '0'; -- R+W
s_intwr <= '1' when sel = '0' and addr = b"10" and wr = '0' else '0'; -- W
s_intrd <= '1' when sel = '0' and addr = b"10" and wr = '1' else '0'; -- R
s_tx <= '1' when sel = '0' and addr = b"11" and wr = '0' else '0'; -- W-O
s_rx <= '1' when sel = '0' and addr = b"11" and wr = '1' else '0'; -- R-O
data_out <= d_out;
d_inp <= data_inp;
end behavioral;
-- ++ simple uart +++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: system statistics: gather statistics in one place
-- processor reads performance counters, on word boundaries, adressed as
-- cnt_dc_ref when "00000", 0
-- cnt_dc_rd_hit when "00100", 4
-- cnt_dc_wr_hit when "01000", 8
-- cnt_dc_flush when "01100", 12
-- cnt_ic_ref when "10000", 16
-- cnt_ic_hit when "10100", 20
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : out reg32;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end sys_stats;
architecture simulation of sys_stats is
begin
U_SYNC_OUTPUT: process(clk,sel)
variable i_c : integer := 0;
begin
data <= (others => '0');
if falling_edge(clk) and sel = '0' then
case addr(4 downto 2) is
when "000" => i_c := cnt_dc_ref;
when "001" => i_c := cnt_dc_rd_hit;
when "010" => i_c := cnt_dc_wr_hit;
when "011" => i_c := cnt_dc_flush;
when "100" => i_c := cnt_ic_ref;
when "101" => i_c := cnt_ic_hit;
when others => i_c := 0;
end case;
end if;
data <= std_logic_vector(to_unsigned(i_c,32));
end process U_SYNC_OUTPUT;
end architecture simulation;
-- ++ system statistics ++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of sys_stats is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: to_7seg
-- input format:
-- b14 b13 b12 b09 b08 b07..b04 b03..b02
-- red gre blu MSdot msdot MSdigit msdigit
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out reg8;
display1 : out reg8;
red : out std_logic;
green : out std_logic;
blue : out std_logic);
-- 2 decimal points, 2 hex digits, 3 leds
constant NUM_BITS : integer := 15;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant INIT_VALUE : c_width := (others => '0');
end to_7seg;
architecture behavioral of to_7seg is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component display_7seg is
port(data_i : in std_logic_vector(3 downto 0);
decimal_i : in std_logic;
disp_7seg_o : out std_logic_vector(7 downto 0));
end component display_7seg;
signal value : std_logic_vector(NUM_BITS-1 downto 0);
signal middle : std_logic;
begin
U_HOLD_data: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, sel, data(NUM_BITS-1 downto 0), value);
red <= value(14);
green <= value(13);
blue <= value(12);
U_DSP1: display_7seg port map (value(7 downto 4), value(9), display1);
U_DSP0: display_7seg port map (value(3 downto 0), value(8), display0);
U_sim: process(sel,rst,clk)
begin
middle <= not(sel) and not(clk); -- to remove spurious reports
if rst = '1' then
assert not(rising_edge(middle))
report "dsp7seg: "& SLV32HEX(data) severity NOTE;
end if;
end process;
end behavioral;
-- ++ to_7seg +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: read_keys
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity read_keys is
generic (DEB_CYCLES: natural); -- debouncing interval
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
constant DEB_BITS : integer := 16; -- debounce counter width
constant CNT_MAX : integer := (2**DEB_BITS - 1);
constant x_DEB_CYCLES : std_logic_vector(DEB_BITS-1 downto 0)
:= std_logic_vector(to_unsigned((CNT_MAX - DEB_CYCLES),DEB_BITS));
constant NUM_BITS : integer := 4; -- four bits to hold key number
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant NO_KEY : c_width := (others => '0');
end read_keys;
architecture behavioral of read_keys is
component FFD is
port(clk, rst, set : in std_logic;
D : in std_logic; Q : out std_logic);
end component FFD;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector(NUM_BITS-1 downto 0);
Q: out std_logic_vector(NUM_BITS-1 downto 0));
end component registerN;
component countNup is
generic (NUM_BITS: integer := 16);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector((NUM_BITS - 1) downto 0);
Q: out std_logic_vector((NUM_BITS - 1) downto 0);
co: out std_logic);
end component countNup;
type kbd_state is (st_idle, st_start, st_wait, st_load, st_release);
signal kbd_current_st, kbd_next_st : kbd_state;
attribute SYN_ENCODING of kbd_state : type is "safe";
-- signal kbd_dbg_st : integer; -- debugging only
signal cnt_ld, cnt_en, new_ld : std_logic;
signal press, debounced, rdy_clr, ready : std_logic;
signal keys_data, cpu_data : reg4;
signal d : reg2;
-- signal count : std_logic_vector(DEB_BITS-1 downto 0); -- debugging only
begin
data(31) <= ready;
data(30 downto 8) <= (others => '0');
data(7) <= sw(3);
data(6) <= sw(2);
data(5) <= sw(1);
data(4) <= sw(0);
data(3 downto 0) <= cpu_data(3 downto 0);
U_DEBOUNCER: countNup generic map (DEB_BITS)
port map (clk=>clk, rst=>rst, ld=>cnt_ld, en=>cnt_en,
D=>x_DEB_CYCLES, Q=>open, co=>debounced);
U_NEW_DATA: registerN generic map (4, NO_KEY)
port map (clk, rst, new_ld, keys_data, cpu_data);
d <= new_ld & sel; -- new_ld, sel active in '0'
with d select
rdy_clr <= '1' when "00",
'1' when "01",
'0' when "10",
ready when others;
U_READY: FFD port map (clk, rst, '1', rdy_clr, ready);
press <= BOOL2SL(keys_data /= b"0000");
-- translate key position to key code
-- code for key 0 cannot be zero; value-holding register is reset to "0000"
with kbd select
keys_data <= "0001" when "000000000001", -- 1
"0010" when "000000000010", -- 2
"0011" when "000000000100", -- 3
"0100" when "000000001000", -- 4
"0101" when "000000010000", -- 5
"0110" when "000000100000", -- 6
"0111" when "000001000000", -- 7
"1000" when "000010000000", -- 8
"1001" when "000100000000", -- 9
"1010" when "001000000000", -- *
"1111" when "010000000000", -- 0, cannot be "0000"
"1011" when "100000000000", -- #
"0000" when others; -- no key depressed
-- ---------------------------------------------------------------------
U_KBD_st_reg: process(rst,clk)
begin
if rst = '0' then
kbd_current_st <= st_idle;
elsif rising_edge(clk) then
kbd_current_st <= kbd_next_st;
end if;
end process U_KBD_st_reg; ----------------------------------------------
-- kbd_dbg_st <= integer(kbd_state'pos(kbd_current_st)); -- for debugging
U_KBD_st_transitions: process(kbd_current_st, press, debounced) --------
begin
case kbd_current_st is
when st_idle => -- 0
if press = '1' then
kbd_next_st <= st_start;
else
kbd_next_st <= st_idle;
end if;
when st_start => -- 1
kbd_next_st <= st_wait;
when st_wait => -- 2
if debounced = '1' then
kbd_next_st <= st_load;
else
kbd_next_st <= st_wait;
end if;
when st_load => -- 3
kbd_next_st <= st_release;
when st_release => -- 4
if press = '1' then
kbd_next_st <= st_release;
else
kbd_next_st <= st_idle;
end if;
end case;
end process U_KBD_st_transitions; ------------------------------------
U_KBD_outputs: process(kbd_current_st) ------------------------------
begin
case kbd_current_st is
when st_idle |st_release => -- 0,4
new_ld <= '1';
cnt_ld <= '0';
cnt_en <= '0';
when st_start => -- 1
new_ld <= '1';
cnt_ld <= '1';
cnt_en <= '0';
when st_wait => -- 2
new_ld <= '1';
cnt_ld <= '0';
cnt_en <= '1';
when st_load => -- 3
new_ld <= '0';
cnt_ld <= '1';
cnt_en <= '0';
end case;
end process U_KBD_outputs; -------------------------------------------
end behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: LCD display controller
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic); -- LCD backlight on=1
constant NUM_BITS : integer := 8;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant INIT_VALUE : c_width := (others => '0');
end LCD_display;
architecture rtl of LCD_display is
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
type lcd_state is (st_init, st_idle, st_n, st_n1, st_n2, st_n3,
st_n4, st_n5, st_n6, st_n7, st_n8, st_n9, st_na, st_nb);
attribute SYN_ENCODING of lcd_state : type is "safe";
signal lcd_current_st, lcd_next_st : lcd_state;
signal lcd_current : integer; -- debugging only
signal waiting, wait1, wait2, n_sel: std_logic;
signal sel_rs, RS, sel_rw, RW,lcd_enable,lcd_read : std_logic;
signal inp_data, out_data : reg8;
begin
n_sel <= not(sel);
U_WAIT_ON_READS: component wait_states generic map (1)
port map (rst, clk, sel, wait1);
U_WAIT2: FFDsimple port map (clk, rst, wait1, wait2);
rdy <= not(wait1 or wait2 or waiting); -- wait for 260ns
sel_rs <= addr when sel = '0' else RS;
U_INPUT_RS: FFDsimple port map (clk, rst, sel_rs, RS);
U_INPUT: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, sel, data_inp(NUM_BITS-1 downto 0), inp_data);
U_OUTPUT: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, lcd_read, out_data, data_out(NUM_BITS-1 downto 0));
data_out(31 downto NUM_BITS) <= (others => 'X');
-- TESTING ONLY
-- out_data <= b"00000000" when RW = '1' else (others => 'X');
out_data <= LCD_DATA when RW = '1' else (others => 'Z');
LCD_DATA <= inp_data when RW = '0' else (others => 'Z');
LCD_RS <= RS; -- LCD register select 0=ctrl, 1=data
sel_rw <= wr when sel = '0' else RW;
U_INPUT_RW: FFD port map (clk, '1', rst, sel_rw, RW);
LCD_RW <= RW; -- LCD read=1, 0=write
LCD_EN <= lcd_enable; -- LCD enable=1
LCD_BLON <= '1'; -- LCD backlight
-- state register----------------------------------------------------
U_st_reg: process(rst,clk)
begin
if rst = '0' then
lcd_current_st <= st_init;
elsif rising_edge(clk) then
lcd_current_st <= lcd_next_st;
end if;
end process U_st_reg;
lcd_current <= lcd_state'pos(lcd_current_st); -- debugging only
U_st_transitions: process(lcd_current_st, RW, sel)
begin
case lcd_current_st is
when st_init => -- 0
lcd_next_st <= st_idle;
when st_idle => -- 1
if sel = '0' then
lcd_next_st <= st_n;
else
lcd_next_st <= st_idle;
end if;
when st_n => -- 2
lcd_next_st <= st_n1;
when st_n1 => -- 3, setup for Enable is 20ns
lcd_next_st <= st_n2;
when st_n2 => -- 4, keep Enable=1 for 200ns
lcd_next_st <= st_n3;
when st_n3 => -- 5, data setup is 100ns
lcd_next_st <= st_n4;
when st_n4 => -- 6
lcd_next_st <= st_n5;
when st_n5 => -- 7
lcd_next_st <= st_n6;
when st_n6 => -- 8
lcd_next_st <= st_n7;
when st_n7 => -- 9
lcd_next_st <= st_n8;
when st_n8 => -- 10, can read now
lcd_next_st <= st_n9;
when st_n9 => -- 11, data hold for Enable is >40ns
lcd_next_st <= st_na;
when st_na => -- 12
lcd_next_st <= st_nb;
when st_nb => -- 13
lcd_next_st <= st_idle;
when others => -- ??
lcd_next_st <= st_idle; -- Enable cycle >500ns
end case;
end process U_st_transitions;
U_st_outputs: process(lcd_current_st)
begin
case lcd_current_st is
when st_init =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
when st_idle =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
when st_n | st_n1 =>
lcd_enable <= '0'; -- disable, waiting for setup
lcd_read <= '1';
waiting <= '1';
when st_n2 | st_n3 | st_n4 | st_n5 | st_n6 | st_n7 =>
lcd_enable <= '1'; -- enable, waiting
lcd_read <= '1';
waiting <= '1';
when st_n8 =>
lcd_enable <= '1'; -- enable, still waiting
lcd_read <= '0';
waiting <= '1';
when st_n9 =>
lcd_enable <= '1'; -- enable, still waiting
lcd_read <= '1';
waiting <= '1';
when st_na =>
lcd_enable <= '0'; -- disable, still waiting
lcd_read <= '1';
waiting <= '1';
when st_nb =>
lcd_enable <= '0'; -- disable, stop waiting
lcd_read <= '1'; -- held inp data for 40ns
waiting <= '0';
when others =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
end case;
end process U_st_outputs;
end architecture rtl;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
architecture fake of LCD_display is
begin
rdy <= HI;
data_out <= (others => 'X');
LCD_RS <= LO; -- LCD register select 0=ctrl, 1=data
LCD_RW <= HI; -- LCD read=1, 0=write
LCD_EN <= LO; -- LCD enable=1
LCD_BLON <= LO; -- LCD backlight on=1
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: SDcard bus interface (a wrapper to the SDcard controller)
-- base + b"0000" -> address register
-- base + b"0100" -> data registers (RD/WR)
-- base + b"1000" -> control register
-- base + b"1100" -> status register
--
-- Software must ALWAYS check status(31) = busy before reading/writing
-- to controller. If controller is not busy, check for errors.
-- In case of errors, reset controller by writing 0x10 to control register.
-- Wait states (rdy=0) are inserted as needed by the bus interface.
--
-- Control register: bit(4)=1 reset the controller (because of error)
-- bit(1)=1 perform a sector READ
-- bit(0)=1 perform a sector WRITE
-- bit(0) and bit(1) shall not be both set
--
-- Status register: bit(31)=1 controller is busy (busy_o=1)
-- bit(30)=1 simultaneous read and write commands
-- bit(15..0) controller error bits (see SDcard.vhd)
--
-- Address register: 32 bits, can be written to, and read from
--
-- Data register: data write (sw by CPU), data read (lw by CPU)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.SdCardPckg.all;
use work.p_wires.all;
entity SDcard is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in reg2; -- a03, a02
data_inp : in reg32;
data_out : out reg32;
sdc_cs : out std_logic; -- SDcard chip-select
sdc_clk : out std_logic; -- SDcard serial clock
sdc_mosi_o : out std_logic; -- SDcard serial data out (to card)
sdc_miso_i : in std_logic; -- SDcard serial data inp (fro card)
irq : out std_logic); -- interrupt request (not yet used)
end SDCard;
architecture rtl of SDcard is
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
component SdCardCtrl is
generic (
FREQ_G : real; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real; -- Slow SPI clock freq during init (MHz).
SPI_FREQ_G : real; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural; -- Num bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t); -- Type of SD card connected.
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic; -- active-high, synchronous reset.
rd_i : in std_logic; -- active-high read block request.
wr_i : in std_logic; -- active-high write block request.
continue_i : in std_logic; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector; -- Block address.
data_i : in std_logic_vector; -- Data to write to block.
data_o : out std_logic_vector; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy.
hndShk_i : in std_logic; -- High when host has new or has taken data.
hndShk_o : out std_logic; -- High when cntlr has taken or new data.
error_o : out std_logic_vector;
-- I/O signals to the external SD card.
cs_bo : out std_logic; -- Active-low chip-select.
sclk_o : out std_logic; -- Serial clock to SD card.
mosi_o : out std_logic; -- Serial data output to SD card.
miso_i : in std_logic; -- Serial data input from SD card.
state : out std_logic_vector); -- state, debugging only
end component SdCardCtrl;
-- use fake / rtl
for U_SDcard : SdCardCtrl use entity work.SdCardCtrl(fake);
signal s_addr, s_stat, s_ctrl, s_read, s_write : std_logic;
signal continue, busy, hndShk_i, hndShk_o, wr_i, rd_i : std_logic;
signal wait1, waiting, new_trans, new_data_rd, sdc_rst : std_logic;
signal ctrl_err, set_wr_i, set_rd_i : std_logic;
signal do_reset, do_reset1 : std_logic;
signal data_rd, data_rd_reg, data_wr_reg : reg8;
signal error_o : reg16;
signal addr_reg : reg32;
signal sel_data_out : reg3;
signal state : reg5;
signal w : reg5;
begin
U_SDcard: SdCardCtrl
-- generic map (50.0, 0.400, 12.5, 512, SD_CARD_E)
generic map (50.0, 25.0, 25.0, 512, SD_CARD_E)
port map (clk, sdc_rst, rd_i, wr_i, '0', addr_reg,
data_wr_reg, data_rd, busy, hndshk_i, open, error_o,
-- data_wr_reg, data_rd, busy, hndshk_i, hndshk_o, error_o,
sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i, state);
hndshk_i <= waiting;
U_WAIT1: component wait_states generic map (1)
port map (rst, clk, new_trans, wait1);
U_WAIT: process(rst, clk, wait1, hndshk_o)
variable w : std_logic;
begin
if rst = '0' then
w := '0';
elsif rising_edge(clk) then
if wait1 = '1' then -- new transaction started
w := '1';
end if;
if hndshk_o = '1' then -- transaction ended
w := '0';
end if;
end if;
waiting <= w;
end process U_WAIT;
rdy <= not(wait1 or waiting); -- wait for controller
new_data_rd <= not(hndshk_o);
U_W1: FFDsimple port map (clk, rst, wait1, w(0));
U_W2: FFDsimple port map (clk, rst, w(0), w(1));
U_W3: FFDsimple port map (clk, rst, w(1), w(2));
U_W4: FFDsimple port map (clk, rst, w(2), w(3));
U_W5: FFDsimple port map (clk, rst, w(3), w(4));
U_W6: FFDsimple port map (clk, rst, w(4), hndshk_o);
-- a3a2 wr register (aligned to word addresses: a1a0=00)
-- 00 0 write to ADDR register (32 bits)
-- 00 1 returns current value of ADDR
-- 01 1 read from data register (8 bits, least significant byte)
-- 01 0 write to data register (8 bits, least significant byte)
-- 10 0 write to control register
-- 10 1 read from control register
-- 11 0 no effect (not possible to write to status register)
-- 11 1 read status register
new_trans <= '0' when addr = b"01" and sel = '0' else '1';
s_addr <= '0' when sel = '0' and addr = b"00" and wr = '0' else '1';
s_write <= '0' when sel = '0' and addr = b"01" and wr = '0' else '1';
s_read <= '0' when sel = '0' and addr = b"01" and wr = '1' else '1';
s_ctrl <= '1' when sel = '0' and addr = b"10" and wr = '0' else '0';
s_stat <= '1' when sel = '0' and addr = b"11" and wr = '1' else '0';
do_reset <= '1' when s_ctrl = '1' and data_inp(4) = '1' else '0';
U_RESET1: FFDsimple port map (clk, rst, do_reset, do_reset1);
sdc_rst <= not(rst) or do_reset or do_reset1; -- held HI for 2 cycles
-- hold wr_i active until first access to WR-register
set_wr_i <= ((s_ctrl and data_inp(0)) or (wr_i and s_write)) and s_write;
U_WR_STROBE: FFDsimple port map (clk, rst, set_wr_i, wr_i);
-- hold rd_i active until first access to RD-register
set_rd_i <= ((s_ctrl and data_inp(1)) or (rd_i and s_read)) and s_read;
U_RD_STROBE: FFDsimple port map (clk, rst, set_rd_i, rd_i);
ctrl_err <= wr_i and rd_i; -- cannot both read AND write
U_ADDR_REG: registerN generic map (32, x"00000000")
port map (clk, rst, s_addr, data_inp, addr_reg);
U_WRITE_REG: registerN generic map (8, x"00")
port map (clk, rst, s_write, data_inp(7 downto 0), data_wr_reg);
U_READ_REG: registerN generic map (8, x"00")
port map (clk, rst, new_data_rd, data_rd, data_rd_reg);
sel_data_out <= sel & addr;
with sel_data_out select
data_out <= addr_reg when "000",
x"000000" & data_rd_reg when "001",
x"000000" & b"000" & ctrl_err & b"00" & rd_i & wr_i when "010",
busy & ctrl_err & b"00" & b"000" & state & x"0" & error_o when "011",
(others => 'X') when others;
end architecture rtl;
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of SDcard is
begin
rdy <= HI;
data_out <= (others => 'X');
sdc_cs <= HI;
sdc_clk <= LO; -- SDcard serial clock
sdc_mosi_o <= LO; -- SDcard serial data out (to card)
irq <= LO; -- interrupt request (not yet used)
end architecture fake;
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
34d6236589d587f9488de1aa0b0e0fd3
| 0.508967 | 3.544454 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/grethm.vhd
| 1 | 6,482 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethm
-- File: grethm.vhd
-- Author: Jiri Gaisler
-- Description: Module to select between greth and greth1g
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
entity grethm is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of grethm is
begin
m100 : if giga = 0 generate
u0 : greth
generic map (
hindex => hindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
apbi => apbi,
apbo => apbo,
ethi => ethi,
etho => etho);
end generate;
m1000 : if giga = 1 generate
u0 : greth_gbit
generic map (
hindex => hindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
ramdebug => ramdebug,
mdiohold => mdiohold,
gmiimode => gmiimode
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
apbi => apbi,
apbo => apbo,
ethi => ethi,
etho => etho);
end generate;
end architecture;
|
gpl-2.0
|
a50d62adb61d4d73cafe0560be5d0a54
| 0.469454 | 4.454983 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de0-nano/ahbrom.vhd
| 3 | 8,961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A033";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A81B";
when 16#00069# => romdata <= X"8410A260";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0538201B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D100FFF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
5ce30bea2df8ecca34ecfc865fa37713
| 0.58085 | 3.28844 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/inpad.vhd
| 1 | 5,301 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad
-- File: inpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= transport to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_inpad generic map (level, voltage) port map (pad, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_inpad generic map (level, voltage) port map (pad, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_inpad port map (pad, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_inpad generic map (level, voltage) port map (pad, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o);
end generate;
um : if (tech = umc) generate
x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
rhs : if (tech = rhs65) generate
x0 : rhs65_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
dar : if (tech = dare) generate
x0 : dare_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_inpad generic map(level, voltage) port map(pad, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
pereg : if (tech = peregrine) generate
x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o);
end generate;
eas : if (tech = easic90) generate
x0 : nextreme_inpad generic map (level, voltage) port map (pad, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_inpad generic map (level, voltage) port map (pad, o);
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpadv is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := 0; width : integer := 1;
filter : integer := 0; strength : integer := 0);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpadv is
begin
v : for i in width-1 downto 0 generate
x0 : inpad generic map (tech, level, voltage, filter, strength) port map (pad(i), o(i));
end generate;
end;
|
gpl-2.0
|
8514e8efddd388e755d9aa0e7dea2055
| 0.645727 | 3.505952 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/inferred/ddrphy_datapath.vhd
| 1 | 9,277 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy_datapath
-- File: ddrphy_datapath.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR/DDR2 PHY data path (digital part of phy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
-- Enable extra resync stage clocked by clkresync
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
-- Control signals synchronous to clk0
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0); -- Clk enable control signal to memory
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic; -- Run dqs strobe (active low)
dqs_oen : in std_ulogic; -- DQS output enable (active low)
ddrclk_en : in std_logic_vector(nclk-1 downto 0) -- Enable/stop ddr_clk
);
end;
architecture rtl of ddrphy_datapath is
signal vcc,gnd: std_ulogic;
signal dqs_en_inv,dqs_en_inv180: std_ulogic;
signal dqcaptr,dqcaptf: std_logic_vector(dbits-1 downto 0);
signal dqsyncr,dqsyncf: std_logic_vector(dbits-1 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- DDR interface clock signal
-----------------------------------------------------------------------------
-- 90 degree shifted relative to master clock, gated by ddrclk_en
genclk: for x in 0 to nclk-1 generate
clkreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => ddrclk_en(x), d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clk(x));
clkbreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => gnd, d2 => ddrclk_en(x), ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clkb(x));
end generate;
-----------------------------------------------------------------------------
-- Control signals RAS,CAS,WE,BA,ADDR,CS,ODT,CKE
-----------------------------------------------------------------------------
rasreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => rasn, q => ddr_rasb);
casreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => casn, q => ddr_casb);
wereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => wen, q => ddr_web);
genba: for x in 0 to bankbits-1 generate
bareg: grdff generic map (tech => regtech)
port map (clk => clk0, d => ba(x), q => ddr_ba(x));
end generate;
gencs: for x in 0 to ncs-1 generate
csreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => csn(x), q => ddr_csb(x));
ckereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => cke(x), q => ddr_cke(x));
odtreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => odt(x), q => ddr_odt(x));
end generate;
genaddr: for x in 0 to abits-1 generate
addrreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => addr(x), q => ddr_ad(x));
end generate;
-----------------------------------------------------------------------------
-- Outgoing data, output enable, DQS, DQSOEN, DM
-----------------------------------------------------------------------------
gendqout: for x in 0 to dbits-1 generate
dqoutreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqout(x+dbits), d2 => dqout(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dq_out(x));
dqoenreg: grdff
generic map (tech => regtech)
port map (clk => clk0, d => oen, q => ddr_dq_oen(x));
end generate;
-- dqs_en -> invert -> delay -> +90-deg DDR-regs -> dqs_out
-- In total oen is delayed 5/4 cycles. We use 1/2 cycle delay
-- instead of 1 cycle delay to get better timing margin to DDR regs.
-- DQSOEN is delayed one cycle just like ctrl sigs
dqs_en_inv <= not dqs_en;
dqseninv180reg: grdff
generic map (tech => regtech)
port map (clk => clk180, d => dqs_en_inv, q => dqs_en_inv180);
gendqsout: for x in 0 to dbits/8-1 generate
dqsreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqs_en_inv180, d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_dqs_out(x));
dqsoenreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqs_oen, q => ddr_dqs_oen(x));
end generate;
gendm: for x in 0 to dbits/8-1 generate
dmreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dm(x+dbits/8), d2 => dm(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dm(x));
end generate;
-----------------------------------------------------------------------------
-- Incoming data
-----------------------------------------------------------------------------
gendqin: for x in 0 to dbits-1 generate
-- capture using dqs+90
-- Note: The ddr_ireg delivers both edges on c1 rising edge, therefore c1
-- is connected to inverted clock (c1 rising edge == dqs falling edge)
dqcaptreg: ddr_ireg generic map (tech => regtech)
port map (d => ddr_dq_in(x),
c1 => ddr_dqs_in90n(x/8), c2 => ddr_dqs_in90(x/8), ce => vcc, r => gnd, s => gnd,
q1 => dqcaptf(x), q2 => dqcaptr(x));
-- optional extra resync stage
ifresync: if resync=1 generate
genresync: for x in 0 to dbits-1 generate
dqsyncrreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptr(x), q => dqsyncr(x));
dqsyncfreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptf(x), q => dqsyncf(x));
end generate;
end generate;
noresync: if resync/=1 generate
dqsyncr <= dqcaptr;
dqsyncf <= dqcaptf;
end generate;
-- sample in clk0 domain
gensamp: if resync/=2 generate
dqinregr: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncr(x), q => dqin(x+dbits));
dqinregf: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncf(x), q => dqin(x));
end generate;
nosamp: if resync=2 generate
dqin(x+dbits) <= dqsyncr(x);
dqin(x) <= dqsyncf(x);
end generate;
end generate;
end;
|
gpl-2.0
|
83a4caae95987b1ac63ef98457a97154
| 0.54619 | 3.626661 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys4ddr/ahbrom.vhd
| 1 | 8,961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE05";
when 16#00069# => romdata <= X"8410A25F";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"05248820";
when 16#00077# => romdata <= X"8410A3CD";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000080";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D11FFFF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
0e8d4bad701093c2b7c1ae3f6b4a97f2
| 0.58085 | 3.28844 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/gr1553b/simtrans1553.vhd
| 1 | 3,729 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: simtrans1553
-- File: simtrans1553.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: 1553 Transceiver simulation model
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity simtrans1553_single is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
buswire: inout wire1553;
rxen: in std_logic;
txin: in std_logic;
txP: in std_logic;
txN: in std_logic;
rxP: out std_logic;
rxN: out std_logic
);
end;
architecture b of simtrans1553_single is
signal bw_rxd, bw_txd: wire1553;
begin
bw_rxd <= transport buswire after rxdelay;
buswire <= bw_txd after txdelay;
rxpr: process(bw_rxd,rxen)
variable p,n: std_ulogic;
begin
p:='U'; n:='U';
case rxen is
when '0' => p:='0'; n:='0';
when '1' =>
case bw_rxd is
when 'U' => null;
when 'X' => p := 'X'; n := 'X';
when '0' => p := '0'; n := '0';
when '+' => p := '1'; n := '0';
when '-' => p := '0'; n := '1';
end case;
when 'X' => p:='X'; n:='X';
when others => null;
end case;
rxP <= p;
rxN <= n;
end process;
txpr: process(txin, txP, txN)
variable w: wire1553;
begin
w := 'U';
if txin='1' or (txP='0' and txN='0') or (txP='1' and txN='1') then
w := '0';
elsif txin='0' and txP='1' and txN='0' then
w := '+';
elsif txin='0' and txP='0' and txN='1' then
w := '-';
elsif txin='X' or txP='X' or txN='X' then
w := 'X';
elsif txin='U' or (txP='U' and txN='U') then
w := 'U';
else
w := 'X';
end if;
bw_txd <= w;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity simtrans1553 is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
busA: inout wire1553;
busB: inout wire1553;
rxenA: in std_logic;
txinA: in std_logic;
txAP: in std_logic;
txAN: in std_logic;
rxAP: out std_logic;
rxAN: out std_logic;
rxenB: in std_logic;
txinB: in std_logic;
txBP: in std_logic;
txBN: in std_logic;
rxBP: out std_logic;
rxBN: out std_logic
);
end;
architecture s of simtrans1553 is
begin
at: simtrans1553_single
generic map (txdelay,rxdelay)
port map (busA,rxenA,txinA,txAP,txAN,rxAP,rxAN);
bt: simtrans1553_single
generic map (txdelay,rxdelay)
port map (busB,rxenB,txinB,txBP,txBN,rxBP,rxBN);
end;
|
gpl-2.0
|
25fb5db87502c4a1fb6a0e765c127830
| 0.563154 | 3.421101 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2c2ahbx.vhd
| 1 | 18,522 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahbx
-- File: i2c2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with i2c2ahb or i2c2ahb_apb
-- before use.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a I2C memory device. To write to the core, issue the
-- following I2C bus sequence:
--
-- 0. START condition
-- 1. Send core's I2C address with direction = write
-- 2. Send 32-bit address to be used for AMBA bus
-- 3. Send data to be written
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. When the core's internal FIFO is full, the core will use clock
-- stretching to stall the transfer.
--
-- To write to the core, issue the following I2C bus sequence:
--
-- 0. START condition
-- 1. Send core's I2C address with direction = write
-- 2. Send 32-bit address to be used for AMBA bus
-- 3. Send repeated start condition
-- 4. Send core's I2C address with direction = read
-- 5. Read bytes
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). When the buffer is empty the core will use clock stretching
-- to stall the transfer.
--
-- The cores control/status register is accessed via address i2caddr + 1. The
-- register has the following layout:
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7:6 | Reserved, always zero (RO) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | NACK: NACK instead of using clock stretching (RW) |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filters used on SCL and SDA
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2c2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type;
--
i2c2ahbi : in i2c2ahb_in_type;
i2c2ahbo : out i2c2ahb_out_type
);
end entity i2c2ahbx;
architecture rtl of i2c2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type state_type is (idle, checkaddr, sclhold, movebyte, handshake);
type i2c2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
nack : std_ulogic;
prot : std_ulogic;
-- Transfer phase
i2caddr : std_ulogic;
ahbacc : std_ulogic;
ahbadd : std_ulogic;
rec : std_ulogic;
bcnt : std_logic_vector(1 downto 0);
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : i2c2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_I2C2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, i2ci, amo, i2c2ahbi)
variable v : i2c2ahb_reg_type;
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable slv : std_ulogic;
variable cfg : std_ulogic;
variable lb : std_ulogic;
begin
v := r; ahbreq := '0'; slv := '0'; cfg := '0'; lb := '0';
hrdata := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.state is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
if r.sreg(7 downto 1) = i2c2ahbi.slvaddr then slv := '1'; end if;
if r.sreg(7 downto 1) = i2c2ahbi.cfgaddr then cfg := '1'; end if;
v.rec := not r.sreg(0);
if (slv or cfg) = '1' then
if (slv and r.dodma) = '1' then
-- Core is busy performing DMA
if r.nack = '1' then v.state := idle;
else v.state := sclhold; end if;
else
v.state := handshake;
end if;
else
-- Slave address did not match
v.state := idle;
end if;
v.hwrite := v.rec;
if (slv and not r.dodma) = '1' then v.dodma := not v.rec; end if;
v.ahbacc := slv; v.bcnt := "00"; v.ahbadd := '0';
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the core is ready to process another
-- transfer. It is also used when a data byte has been transmitted or
-- received to keep SCL low until a DMA operation has completed.
-- In the transmit case we keep SCL low before the rising edge of the
-- first byte, so we go directly to move byte. In the receive case we
-- stretch the ACK cycle so we jump to handshake next.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if r.dodma = '0' then
if (not r.rec and not r.i2caddr) = '1' then
v.state := movebyte;
else
v.state := handshake;
end if;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if (r.i2caddr or r.rec or v.scl) = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if (r.i2caddr or r.rec) = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.i2caddr = '1' then
v.state := checkaddr;
else
v.state := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
-- Falling edge
if (r.scl and not v.scl) = '1' then
if (r.i2caddr or not r.ahbacc) = '1' then
-- Also handles first byte on AHB read access
if (r.rec or r.i2caddr) = '1' then
v.sdaoen := I2C_LOW;
else
v.sdaoen := I2C_HIZ;
end if;
if (not r.i2caddr and r.rec) = '1' then
-- Control register access
v.nack := r.sreg(2);
v.hsize := r.sreg(1 downto 0);
end if;
else
-- AHB access
if r.rec = '1' then
-- First we need a 4 byte address, then we handle data.
v.bcnt := r.bcnt + 1;
if r.ahbadd = '0' then
-- We could check if the address is within the allowed memory
-- area here, and nack otherwise, but we do it when the access
-- is performed instead, to have one check for all cases.
v.haddr := r.haddr(23 downto 0) & r.sreg;
if r.bcnt = "11" then v.ahbadd := '1'; end if;
v.sdaoen := I2C_LOW;
elsif r.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.bcnt := "00"; end if;
v.sdaoen := I2C_LOW;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
end if;
end if;
-- Previous DMA is not finished yet
if (r.dodma and r.ahbacc) = '1' then
if r.nack = '0' then
-- Hold clock low and handle data when DMA is finished
v.state := sclhold;
v.scloen := I2C_LOW;
else
-- NAK byte
v.sdaoen := I2C_HIZ;
v.state := idle;
end if;
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if (r.i2caddr or not r.ahbacc) = '1' then
if r.sda = I2C_ACK then
v.state := movebyte;
else
v.state := idle;
end if;
else
if r.rec = '1' then
v.state := movebyte;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended
-- and we should wait for the master's next action. If the master
-- ACKs the byte the core we will continue to transmit data until
-- we reach the last available byte. When the last byte has been
-- transmitted we will act depending on if we are allowed to enter
-- sclhold. If we can, we enter sclhold and start a new DMA
-- operation, otherwise we stop communicating until the next start
-- condition.
v.bcnt := r.bcnt + 1;
if r.sda = I2C_ACK then
if lb = '1' then
if r.nack = '1' then
v.state := idle;
else
v.dodma := '1'; v.bcnt := "00";
v.state := sclhold;
end if;
else
v.state := movebyte;
end if;
else
v.state := idle;
end if;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
end if;
end if;
v.i2caddr := '0';
if r.ahbacc = '0' then
-- Control register access
v.sreg := zero32(7 downto 6) & r.prot & r.mexc &
r.dodma & r.nack & r.hsize;
end if;
end if;
end case;
if i2c2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((i2c2ahbi.haddr xor r.haddr) and i2c2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if i2c2ahbi.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.state := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.state := movebyte;
v.cnt := (others => '0');
v.i2caddr := '1';
end if;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.hsize := HSIZE_WORD(1 downto 0);
v.mexc := '0';
v.dodma := '0';
v.nack := '0';
v.prot := '0';
v.scl := '0';
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
if i2c2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
i2c2ahbo.dma <= r.dodma;
i2c2ahbo.wr <= r.hwrite;
i2c2ahbo.prot <= r.prot;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= i2c2ahbi.en;
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("i2c2ahb" & tost(hindex) & ": I2C to AHB bridge");
-- pragma translate_on
end architecture rtl;
|
gpl-2.0
|
9ca4ef50e1e2f50101d86bb3d8d0066a
| 0.475273 | 3.889542 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spi2ahb_apb.vhd
| 1 | 6,856 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb_apb
-- File: spi2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from SPI.
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity spi2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb_apb;
architecture rtl of spi2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPI2AHB, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
spi2ahbi : spi2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal spi2ahbo : spi2ahb_out_type;
begin
bridge : spi2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter,
cpol => cpol, cpha => cpha)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
spii => spii, spio => spio, spi2ahbi => r.spi2ahbi,
spi2ahbo => spi2ahbo);
comb: process (r, rstn, apbi, spi2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := spi2ahbo.prot; v.dmax := spi2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.spi2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.spi2ahbi.haddr;
when MASK_OFF => apbout := r.spi2ahbi.hmask;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.spi2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.spi2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.spi2ahbi.hmask := apbi.pwdata;
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((spi2ahbo.dma and not r.dmax) or
(spi2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or spi2ahbo.prot; v.wr := spi2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.spi2ahbi.en := conv_std_logic(resen = 1);
v.spi2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.spi2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in spi2ahbx...
end architecture rtl;
|
gpl-2.0
|
a570e1cd94bbb9ee6d444d4f053b2ec5
| 0.536319 | 3.796235 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/unisim/memory_unisim.vhd
| 1 | 28,117 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Xilinx rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB16 block rams
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S36;
use unisim.RAMB16_S18;
use unisim.RAMB16_S9;
use unisim.RAMB16_S4;
use unisim.RAMB16_S2;
use unisim.RAMB16_S1;
--pragma translate_on
entity unisim_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of unisim_syncram is
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+72 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 8)) generate
x : for i in 0 to ((dbits-1)/72) generate
r0 : RAMB16_S36_S36
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
xa(8 downto 0), ya(8 downto 0), clk, clk,
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
enable, enable, gnd, gnd, write, write);
end generate;
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/36) generate
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
enable, gnd, write);
end generate;
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/18) generate
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
enable, gnd, write);
end generate;
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
enable, gnd, write);
end generate;
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
end generate;
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
end generate;
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to (dbits-1) generate
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
clk, di((i+1)-1 downto i), enable, gnd, write);
end generate;
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a15 : if abits > 14 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 14 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 14 not supported for unisim_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
LIBRARY ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S18_S18;
use unisim.RAMB16_S9_S9;
use unisim.RAMB16_S4_S4;
use unisim.RAMB16_S2_S2;
use unisim.RAMB16_S1_S1;
--pragma translate_on
entity unisim_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of unisim_syncram_dp is
component RAMB16_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/36) generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
enable1, enable2, gnd, gnd, write1, write2);
-- vcc, vcc, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : RAMB16_S18_S18
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB16_S4_S4
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB16_S2_S2
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
a_to_high : if abits > 14 generate
x : process
begin
assert false
report "Address depth larger than 14 not supported for unisim_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
entity unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture behav of unisim_syncram_2p is
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
signal write2, renable2 : std_ulogic;
signal datain2 : std_logic_vector((dbits-1) downto 0);
begin
-- nowf: if wrfst = 0 generate
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
-- end generate;
-- wf : if wrfst = 1 generate
-- write2 <= '0' when (waddress /= raddress) else write;
-- renable2 <= renable or write2; datain2 <= datain;
-- end generate;
a0 : if abits <= 5 and GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
a6 : if abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0 generate
x0 : unisim_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, datain2, dataout, renable2, write2);
end generate;
end;
-- parametrisable sync ram generator using unisim block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end;
architecture behav of unisim_syncram64 is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a8 : if abits <= 8 generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(63 downto 32), dataout(31 downto 0), open, open,
xa(8 downto 0), ya(8 downto 0), clk, clk,
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
end generate;
a9 : if abits > 8 generate
x1 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1));
x2 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity unisim_syncram128 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end;
architecture behav of unisim_syncram128 is
component unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
x0 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2));
x1 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of unisim_syncram128bw is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a11 : if abits <= 10 generate
x0 : for i in 0 to 7 generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(i*8+7+64 downto i*8+64), dataout(i*8+7 downto i*8), open, open,
xa(10 downto 0), ya(10 downto 0), clk, clk,
datain(i*8+7+64 downto i*8+64), datain(i*8+7 downto i*8), gnd(0 downto 0), gnd(0 downto 0),
enable(i+8), enable(i), gnd(0), gnd(0), write(i+8), write(i));
end generate;
end generate;
a12 : if abits > 10 generate
x0 : for i in 0 to 15 generate
x2 : unisim_syncram generic map ( abits, 8)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i));
end generate;
end generate;
end;
|
gpl-2.0
|
7c56dda12dd90d3b813304d492f122f4
| 0.614646 | 3.043954 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc3s1000/vga_clkgen.vhd
| 1 | 2,038 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clk50;
when "10" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
|
gpl-2.0
|
a180582bd8ba93fed0eaa52bb3d0cb2d
| 0.631992 | 3.82364 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/jtag/libjtagcom.vhd
| 1 | 2,881 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libjtagcom
-- File: libjtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Commulnications link signal and component declarations
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
package libjtagcom is
type tap_in_type is record
en : std_ulogic;
tdo : std_ulogic;
end record;
type tap_out_type is record
tck : std_ulogic;
tdi : std_ulogic;
inst : std_logic_vector(7 downto 0);
asel : std_ulogic;
dsel : std_ulogic;
reset : std_ulogic;
capt : std_ulogic;
shift : std_ulogic;
upd : std_ulogic;
end record;
component jtagcom
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
reread : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tck : in std_ulogic;
trst : in std_ulogic
);
end component;
component jtagcom2 is
generic (
gatetech: integer := 0;
isel : integer range 0 to 1 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tckp : in std_ulogic;
tckn : in std_ulogic;
trst : in std_ulogic
);
end component;
end;
|
gpl-2.0
|
12276503680ddf22a1868d785df8ca99
| 0.581742 | 3.846462 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/ringosc.vhd
| 1 | 2,525 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ringosc
-- File: ringosc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Ring-oscillator with tech mapping
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ringosc is
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end ;
architecture rtl of ringosc is
component ringosc_rhumc
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_ut130hbd
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_rhs65
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
begin
dr : if tech = rhumc generate
drx : ringosc_rhumc port map (roen, roout);
end generate;
ut130r : if tech = ut130 generate
ut130rx : ringosc_ut130hbd port map (roen, roout);
end generate;
rhs65r : if tech = rhs65 generate
rhs65rx : ringosc_rhs65 port map (roen, roout);
end generate;
-- pragma translate_off
gen : if tech /= rhumc and tech /= ut130 and tech /= rhs65 generate
signal tmp : std_ulogic := '0';
begin
tmp <= not tmp after 1 ns when roen = '1' else '0';
roout <= tmp;
end generate;
-- pragma translate_on
end architecture rtl;
|
gpl-2.0
|
13d21773faec3783f3d0ced2769e4d99
| 0.605941 | 4.066023 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/jtag/bscanregs.vhd
| 1 | 2,806 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: bscanregs
-- File: bscanregs.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG boundary scan registers, single-ended IO
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bscanregs is
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end;
architecture hier of bscanregs is
signal itdi: std_logic_vector(nsigs downto 0);
begin
disgen: if enable=0 generate
sigo <= sigi;
itdi <= (others => '0');
tdo <= '0';
end generate;
engen: if enable /= 0 generate
g0: for x in 0 to nsigs-1 generate
irgen: if ((dirmask / (2**x)) mod 2)=0 generate
ireg: scanregi
generic map (tech)
port map (sigi(x),sigo(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdi,bsdrive,bshighz);
end generate;
orgen: if ((dirmask / (2**x)) mod 2)/=0 generate
oreg: scanrego
generic map (tech)
port map (sigo(x),sigi(x),sigi(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdo,bsdrive);
end generate;
end generate;
itdi(0) <= tdi;
tdo <= itdi(nsigs);
end generate;
end;
|
gpl-2.0
|
33a623963ea790b08988bea853ee48da
| 0.596222 | 3.751337 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-clock-gate/clkgate.vhd
| 1 | 2,514 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkgate is
generic (tech : integer := 0; ncpu : integer := 1; dsuen : integer := 1);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0)
);
end;
architecture rtl of clkgate is
signal npwd, xpwd, ypwd : std_logic_vector(ncpu-1 downto 0);
signal vrst, wrst : std_logic_vector(ncpu-1 downto 0);
signal clken: std_logic_vector(ncpu-1 downto 0);
signal xrst, vcc : std_ulogic;
begin
vcc <= '1';
cand : for i in 0 to ncpu-1 generate
clken(i) <= not npwd(i);
clkand0 : clkand generic map (tech) port map (clkin, clken(i), clkcpu(i));
end generate;
cand0 : clkand generic map (tech) port map (clkin, vcc, clkahb);
vrst <= (others => rst);
r1 : if dsuen = 1 generate
nreg : process(clkin)
begin
if falling_edge(clkin) then
npwd <= pwd and vrst;
end if;
end process;
end generate;
r2 : if dsuen = 0 generate
reg : process(clkin)
begin
if rising_edge(clkin) then
xrst <= rst;
xpwd <= pwd and wrst;
end if;
end process;
wrst <= (others => xrst);
nreg : process(clkin)
begin
if falling_edge(clkin) then
npwd <= xpwd;
end if;
end process;
end generate;
end;
|
gpl-2.0
|
37e28306c058cb6655f8d9be47ef6a40
| 0.614956 | 3.724444 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep1c20/testbench.vhd
| 1 | 11,843 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clkout : out std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector (3 downto 0);
iosn : out std_ulogic;
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_ulogic; -- sdram clock enable
sdcsn : out std_ulogic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector (1 downto 0);
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
rxd1 : in std_ulogic; -- UART1 rx data
txd1 : out std_ulogic; -- UART1 tx data
-- for smc lan chip
eth_aen : out std_ulogic;
eth_readn : out std_ulogic;
eth_writen : out std_ulogic;
eth_nbe : out std_logic_vector (3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic
);
end component;
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
pllref <= clkout;
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech, ncpu,
disas, dbguart, pclow )
port map (rst, clk, clkout, pllref, error, address, data,
ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen,
sa(11 downto 0), sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba,
dsutx, dsurx, dsubren, dsuact,
rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
-- optional sdram
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
4fa01d2a92c46eb2babb34db2b5b8da2
| 0.571139 | 3.219081 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-cpci-xc4v/dprc_fir_demo/fir_ahb_dma_apb.vhd
| 4 | 13,836 |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir_ahb_dma_apb
-- File: fir_ahb_dma_apb.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter peripheral example for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dma2ahb_package.all;
library techmap;
use techmap.gencomp.all;
entity fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset : in std_ulogic);
end fir_ahb_dma_apb;
architecture fir_abh_rtl of fir_ahb_dma_apb is
component fir port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end component;
type fir_in_type is record
start : std_ulogic;
in_data : std_logic_vector(31 downto 0);
end record;
type fir_out_type is record
data_read : std_ulogic;
data_write : std_ulogic;
out_data : std_logic_vector(31 downto 0);
end record;
type fifo_type is record
wen : std_ulogic;
ren : std_logic;
idata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(8 downto 0);
waddr : std_logic_vector(8 downto 0);
end record;
type apbreg_type is record
control : std_logic_vector(31 downto 0);
address_in : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
timer : std_logic_vector(31 downto 0);
end record;
type apbreg_control is record
clear_control : std_ulogic;
clear_timer : std_ulogic;
en_timer : std_ulogic;
end record;
type fsm_state is (idle, idata_request, idata_wait, core_wait, odata_request, odata_wait);
signal pstate, nstate : fsm_state;
type regs is record
cgrant : std_logic_vector(8 downto 0);
cready : std_logic_vector(8 downto 0);
cokay : std_logic_vector(8 downto 0);
cidata : std_logic_vector(8 downto 0);
codata : std_logic_vector(8 downto 0);
address : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
end record;
signal dmain : dma_in_type;
signal dmaout : dma_out_type;
signal ifir : fir_in_type;
signal ofir : fir_out_type;
signal fifo_in, fifo_out, regfifo_out : fifo_type;
signal fifo_o1data, fifo_o2data : std_logic_vector(31 downto 0);
signal reg_apb, reg_apb_in : apbreg_type;
signal reg_control : apbreg_control;
signal reg, reg_in : regs;
signal rst_core : std_ulogic;
signal ofir_wen : std_logic;
signal ofir_data : std_logic_vector(31 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_CONTRIB, CONTRIB_CORE2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
rst_core <= not(rstn) or rm_reset;
-- APB interface signals
apbo.pirq <= (others => '0'); --no interrupt
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- DMA2AHB signals
dmain.Beat <= HINCR;
dmain.Size <= HSIZE32;
dmain.Reset <= not(rstn);
dmain.Data <= fifo_o2data;
fifo_in.idata <= dmaout.Data;
-- FIFOs / Core signals
ifir.in_data <= fifo_o1data;
fifo_in.waddr <= reg.cready;
fifo_in.raddr <= reg.cidata;
fifo_out.waddr <= reg.codata;
fifo_out.idata <= ofir.out_data;
fifo_in.ren <= ofir.data_read;
fifo_out.wen <= ofir.data_write;
comb : process(reg_apb, apbi, reg_control, pstate, reg, dmaout, regfifo_out, ofir)
variable readdata : std_logic_vector(31 downto 0);
variable regvi : apbreg_type;
variable regv : regs;
variable vfifo_out : fifo_type;
begin
-- APB interface ----------------------
-- assign register outputs to variables
regvi := reg_apb;
-- read register
readdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" =>
readdata := reg_apb.control;
when "01" =>
readdata := reg_apb.address_in;
when "10" =>
readdata := reg_apb.address_out;
when "11" =>
readdata := reg_apb.timer;
when others =>
readdata := (others => '0');
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
regvi.control := apbi.pwdata;
when "01" =>
regvi.address_in := apbi.pwdata;
when "10" =>
regvi.address_out := apbi.pwdata;
when others =>
end case;
end if;
-- timer
if reg_control.clear_timer='1' then
regvi.timer := (others=>'0');
elsif reg_control.en_timer='1' then
regvi.timer := regvi.timer+'1';
end if;
-- clear control registers
if reg_control.clear_control='1' then
regvi.control := std_logic_vector(to_unsigned(2,32));
end if;
-- assign variables to register inputs
reg_apb_in <= regvi;
-- drive bus with read data
apbo.prdata <= readdata;
-------------------------------------
-- fsm (read, execute, write --------
regv := reg;
vfifo_out := regfifo_out;
ifir.start <= '0';
fifo_in.wen <= '0';
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Store <= '0';
dmain.Lock <= '0';
reg_control.clear_timer<='0';
reg_control.en_timer<='0';
reg_control.clear_control<='0';
case pstate is
when idle =>
if (reg_apb.control=std_logic_vector(to_unsigned(1,32))) then
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
reg_control.clear_timer<='1';
else
nstate <= pstate;
end if;
regv.address := reg_apb.address_in;
regv.cgrant := (others=>'0');
regv.cready := (others=>'0');
regv.cidata := (others=>'0');
regv.codata := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address;
when idata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(100,9)) then
nstate <= idata_wait;
else
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when idata_wait =>
if regv.cready=std_logic_vector(to_unsigned(100,9)) then
nstate <= core_wait;
ifir.start <= '1';
else
nstate <= idata_wait;
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when core_wait =>
if regv.codata=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_request;
else
nstate <= core_wait;
end if;
regv.address_out := reg_apb.address_out;
regv.cready := (others=>'0');
regv.cgrant := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address_out;
when odata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_wait;
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Lock <= '0';
dmain.Store <= '0';
else
nstate <= odata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
dmain.Store <= '1';
end if;
dmain.Address <= reg.address_out;
when odata_wait =>
if regv.cokay=std_logic_vector(to_unsigned(91,9)) then
nstate <= idle;
reg_control.clear_control<='1';
else
nstate <= odata_wait;
end if;
dmain.Address <= reg.address_out;
end case;
if (pstate/=idle) then
reg_control.en_timer<='1';
end if;
-------------------------------------
-- counters update ------------------
if (dmaout.Ready='1') then
regv.cready := regv.cready+1;
end if;
if (dmaout.Okay='1') then
regv.cokay := regv.cokay+1;
regv.address_out := regv.address_out+4;
end if;
if (dmaout.Grant='1') then
regv.cgrant := regv.cgrant+1;
regv.address := regv.address+4;
end if;
if (ofir.data_read='1') then
regv.cidata := regv.cidata+1;
end if;
if (ofir.data_write='1') then
regv.codata := regv.codata+1;
end if;
-------------------------------------
vfifo_out.raddr := regv.cokay;
reg_in <= regv;
fifo_out.raddr <= vfifo_out.raddr;
end process;
regs_proc : process(clk,rstn)
begin
if (rstn='0') then
reg_apb.control <= (others => '0');
reg_apb.address_in <= (others => '0');
reg_apb.address_out <= (others => '0');
reg_apb.timer <= (others => '0');
reg.cgrant <= (others => '0');
reg.cready <= (others => '0');
reg.cokay <= (others => '0');
reg.cidata <= (others => '0');
reg.codata <= (others => '0');
reg.address <= (others => '0');
reg.address_out <= (others => '0');
pstate <= idle;
elsif rising_edge(clk) then
reg_apb <= reg_apb_in;
reg <= reg_in;
pstate <= nstate;
end if;
end process;
regs_core: process(clk,rst_core)
begin
if (rst_core='1') then
ofir.data_write <= '0';
ofir.out_data <= (others => '0');
elsif rising_edge(clk) then
ofir.data_write<=ofir_wen;
ofir.out_data<=ofir_data;
end if;
end process;
-- DMA2AHB
fir_dma_to_ahb : dma2ahb generic map (
hindex=>hindex, vendorid=>VENDOR_CONTRIB, deviceid=>CONTRIB_CORE2)
port map (hclk=>clk, hresetn=>rstn, dmain=>dmain, dmaout=>dmaout, ahbin=>ahbin, ahbout=>ahbout);
-- FIR core
fir_core : fir port map (clk => clk, rst => rst_core, start => ifir.start, in_data => ifir.in_data, in_data_read => ofir.data_read,
out_data => ofir_data, out_data_write => ofir_wen);
-- Input data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, fifo_in.ren, fifo_in.raddr, fifo_o1data, clk, fifo_in.wen, fifo_in.waddr, fifo_in.idata);
-- Output data buffer
ram1 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, '1', fifo_out.raddr, fifo_o2data, clk, fifo_out.wen, fifo_out.waddr, fifo_out.idata); -- First word Fall Through
end fir_abh_rtl;
|
gpl-2.0
|
8653e973ac0db2e1715a6820a4a1ba14
| 0.52508 | 3.946378 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/ptf/pt_pci_monitor.vhd
| 1 | 14,806 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_monitor
-- File: pcitb_monitor.vhd
-- Author:
-- Description: PCI Monitor.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
entity pt_pci_monitor is
generic (dbglevel : integer := 1);
port (pciin : in pci_type);
end pt_pci_monitor;
architecture tb of pt_pci_monitor is
constant T_O : integer := 9;
type pci_array_type is array(0 to 2) of pci_type;
type reg_type is record
pci : pci_array_type;
frame_deass : boolean;
m_wait_data_phase : boolean;
t_wait_data_phase : boolean;
stop_asserted : boolean;
device_sel : boolean;
first : boolean;
current_master : integer;
master_cnt : integer;
irdy_cnt : integer;
trdy_cnt : integer;
end record;
signal r,rin : reg_type;
signal init_done : boolean := false;
begin
init : process
begin
if init_done = false then
wait until pciin.syst.rst = '0';
wait until pciin.syst.rst = '1';
init_done <= true;
else
wait until pciin.syst.rst = '0';
init_done <= false;
end if;
end process;
comb : process(pciin)
variable i : integer;
variable v : reg_type;
begin
v := r;
v.pci(0) := pciin; v.pci(1) := r.pci(0); v.pci(2) := r.pci(1);
if r.pci(0).ifc.frame = 'H' then v.frame_deass := false;
elsif (r.pci(0).ifc.frame and not r.pci(1).ifc.frame) = '1' then v.frame_deass := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.m_wait_data_phase := false;
elsif r.pci(0).ifc.irdy = '0' then v.m_wait_data_phase := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.t_wait_data_phase := false;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.t_wait_data_phase := true; end if;
if r.pci(0).ifc.frame = '0' and r.pci(1).ifc.frame = 'H' then
for i in 0 to 20 loop
if r.pci(0).arb.gnt(i) = '0' then v.current_master := i; end if;
end loop;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy) = '0' then
if (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '1' then
v.master_cnt := r.master_cnt+1;
else v.master_cnt := 0; end if;
else v.master_cnt := 0; end if;
if (r.pci(0).ifc.irdy and not r.pci(0).ifc.frame) = '1' then
v.irdy_cnt := r.irdy_cnt+1;
else v.irdy_cnt := 0; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then
v.trdy_cnt := r.trdy_cnt+1;
else v.trdy_cnt := 0; end if;
if r.pci(0).ifc.devsel = '0' then v.device_sel := true;
elsif (to_x01(r.pci(1).ifc.devsel) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then v.device_sel := false; end if;
if r.pci(0).ifc.stop = '0' then v.stop_asserted := true;
elsif r.pci(0).ifc.frame = '0' then v.stop_asserted := false; end if;
if (r.pci(1).ifc.frame = 'H' and r.pci(0).ifc.frame = '0') then v.first := true;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.first := false; end if;
rin <= v;
end process;
clkprc : process(pciin.syst)
begin
if rising_edge(pciin.syst.clk) then
r <= rin;
if init_done then
if (r.pci(0).ifc.frame = '0' and r.frame_deass = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was reasserted during the same transaction.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy and not r.pci(1).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was deasserted without IRDY# asserted.");
end if;
end if;
if (r.m_wait_data_phase and r.device_sel) then
if (r.pci(0).ifc.frame /= r.pci(1).ifc.frame) or (r.pci(0).ifc.irdy /= r.pci(1).ifc.irdy) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master changed IRDY# or FRAME# before current data phase was completed.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy and r.pci(1).ifc.frame and not r.pci(2).ifc.irdy) = '1' and r.stop_asserted = true) then
if not ((r.pci(1).arb.req(r.current_master) and (r.pci(0).arb.req(r.current_master) or r.pci(2).arb.req(r.current_master))) = '1') then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master at slot %d did not release its REQ# when the bus returned to idle state.",r.current_master);
end if;
end if;
end if;
if (r.pci(0).ifc.stop and not r.pci(1).ifc.stop and not r.pci(0).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until FRAME# was deasserted.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(1).ifc.frame and not r.pci(0).ifc.stop and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not release STOP# after FRAME# was deasserted.");
end if;
end if;
if r.t_wait_data_phase = true then
if (r.pci(0).ifc.devsel /= r.pci(1).ifc.devsel) or (r.pci(0).ifc.trdy /= r.pci(1).ifc.trdy) or (r.pci(0).ifc.stop /= r.pci(1).ifc.stop) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current target changed DEVSEL#, STOP# or TRDY# before current data phase was completed.");
end if;
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.stop and not r.pci(1).ifc.frame and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until the last data phase.");
end if;
end if;
if (r.pci(2).ifc.frame and not (r.pci(2).ifc.trdy and r.pci(2).ifc.stop)) = '1' then
if r.pci(1).ifc.irdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master kept IRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.trdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept TRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.stop = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept STOP# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.frame /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state FRAME# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.irdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state IRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.trdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state TRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.stop /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state STOP# after turn-around cycle.");
end if;
end if;
end if;
if (r.master_cnt > 16 and r.first = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete its initial data phase in 16 clkc.");
end if;
end if;
if r.irdy_cnt > 8 then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not complete its initial data phase in 8 clkc.");
end if;
end if;
if (r.trdy_cnt > 8 and r.device_sel = true and r.first = false) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete a data phase in 8 clkc.");
end if;
end if;
if not r.device_sel then
if (r.pci(0).ifc.irdy and not r.pci(1).ifc.irdy) = '1' then
if dbglevel > 0 then
assert false
report "**"
severity note;
printf("PCI_MONITOR: Master abort detected.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy = 'H' and r.pci(1).ifc.frame = '0')
or (r.pci(1).ifc.irdy or r.pci(1).ifc.trdy) = '0') then
if r.pci(0).ad.par = 'Z' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current Master/Target is not generating parity during a data phase.");
end if;
elsif r.pci(0).ad.par /= xorv(r.pci(1).ad.ad & r.pci(1).ad.cbe) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Parity error detected.");
end if;
end if;
end if;
end if;
end if;
end process;
adchk : process(pciin.ad)
begin
if init_done then
-- for i in 0 to 31 loop
-- if pciin.ad.ad(i) = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: AD lines have multiple drivers.");
-- end if;
-- end if;
-- end loop;
for i in 0 to 3 loop
if pciin.ad.cbe(i) = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: CBE# lines have multiple drivers.");
end if;
end if;
end loop;
-- if pciin.ad.par = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: PAR line has multiple drivers.");
-- end if;
-- end if;
end if;
end process;
ifcchk : process(pciin.ifc)
begin
if init_done then
if pciin.ifc.frame = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: FRAME# line has multiple drivers.");
end if;
end if;
if pciin.ifc.irdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: IRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.trdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: TRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.stop = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: STOP# line has multiple drivers.");
end if;
end if;
if pciin.ifc.devsel = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: DEVSEL# line has multiple drivers.");
end if;
end if;
end if;
end process;
arbchk : process(pciin.arb)
variable gnt_set : boolean;
begin
gnt_set := false;
if init_done then
for i in 0 to 20 loop
if pciin.arb.gnt(i) = '0' then
if gnt_set then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: GNT# is asserted for more than one PCI master.");
end if;
else gnt_set := true; end if;
end if;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
gpl-2.0
|
048978bed381b079858d70078215e0be
| 0.529583 | 3.755009 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/sim/sram.vhd
| 1 | 5,439 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram
-- File: sram.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity sram is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- Clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(7 downto 0);
ce1 : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram is
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**Abits)-1)) of BYTE;
signal DINT,DI,DO : BYTE;
constant ahigh : integer := abits - 1;
signal wrpre : std_ulogic;
function Vpar(vec : std_logic_vector) return std_ulogic is
variable par : std_ulogic := '1';
begin
for i in vec'range loop --'
par := par xor vec(i);
end loop;
return par;
end;
begin
RAM : process(CE1,WE,DI,A,OE,D)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if FIRST then
if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
if index = 6 then
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
elsif (index = 4) or (index = 5) then
recaddr(31 downto abits+1) := (others => '0');
ai := conv_integer(recaddr)/2;
for i in 0 to 7 loop
MEMA(ai+i) := recdata((i*16+(index-4)*8) to (i*16+(index-4)*8+7));
end loop;
else
recaddr(31 downto abits+2) := (others => '0');
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7));
end loop;
end if;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
else
if (TO_X01(not CE1) = '1') then
if not is_x(a) then ai := conv_integer(A(abits-1 downto 0)); else ai := 0; end if;
dint <= mema(ai);
end if;
if (TO_X01(CE1 or WE) = '1') then
if wrpre = '1' then
mema(ai) := to_x01(std_logic_vector(DI));
end if;
end if;
end if;
wrpre <= TO_X01((not CE1) and (not WE));
DI <= D;
end process;
BUFS : process(CE1,WE,DINT,OE)
variable DRIVEB : std_logic;
begin
DRIVEB := TO_X01((not CE1) and (not OE) and WE);
case DRIVEB is
when '1' => D <= DINT after tacc * 1 ns;
when '0' => D <= "ZZZZZZZZ" after 8 ns;
when others => D <= "XXXXXXXX";
end case;
end process;
end sim;
-- pragma translate_on
|
gpl-2.0
|
91d88f818ce4217eb1328a4e2fe14e00
| 0.547895 | 3.534113 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2sgx90-av/prgmem.vhd
| 3 | 5,738 |
------------------------------------------------------
-- Program-Memory
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use std.textio.all;
-- Important NOTE:
-- ---------------
--
-- The ROM_BITS generic controls the size of the internal
-- ROM. The ROM is located in upper part of program memory
-- and is initialized by the given (intel-).hex-file.
-- If there's no such file, everything is filled up with
-- 'null'. Everything before the ROM is always nulled.
-- If you don't want a System-ROM, just set ROM_BITS to 0.
entity prgmem is
generic (
INIT_FILE_NAME : string; -- => init file for rom
PRGM_MEM : positive := 12; -- => 4k word
MEM_WIDTH : positive := 32
);
port (
-- common signals
clk : in std_logic; -- normal system clock
reset : in std_logic;
-- access (r)
addr : in std_logic_vector(PRGM_MEM-1 downto 0);
data : out std_logic_vector(MEM_WIDTH-1 downto 0)
);
end entity;
architecture Behavioral of prgmem is
-- some constants
constant MEM_DEPTH : positive := 2**PRGM_MEM;
-- constant MEM_WIDTH : positive := ;
-- constant ROM_DEPTH : positive := 2**ROM_BITS ;
-- constant ROM_POS : integer := rom_start(PRGM_MEM, ROM_BITS);
-- declare memory type
type MEM_TYPE is array(0 to MEM_DEPTH - 1) of std_logic_vector(MEM_WIDTH-1 downto 0);
type BYTE_STRING is array(1 downto 0) of character;
type WORD_STRING is array(3 downto 0) of character;
function CHAR_TO_INT ( char : in character) return integer is
variable r : integer := 0;
begin
case char is
when 'A' => r := 10;
when 'B' => r := 11;
when 'C' => r := 12;
when 'D' => r := 13;
when 'E' => r := 14;
when 'F' => r := 15;
when 'a' => r := 10;
when 'b' => r := 11;
when 'c' => r := 12;
when 'd' => r := 13;
when 'e' => r := 14;
when 'f' => r := 15;
when '1' => r := 1;
when '2' => r := 2;
when '3' => r := 3;
when '4' => r := 4;
when '5' => r := 5;
when '6' => r := 6;
when '7' => r := 7;
when '8' => r := 8;
when '9' => r := 9;
when others => null;
end case;
return r;
end function;
function BYTE_TO_INT ( bytechars : in string(1 to 2)) return integer is
begin
return CHAR_TO_INT(bytechars(1))*16+CHAR_TO_INT(bytechars(2));
end function;
function WORD_TO_INT ( wordchars : in string(1 to 4)) return integer is
begin
return BYTE_TO_INT(wordchars(1) & wordchars(2))*256+BYTE_TO_INT(wordchars(3) & wordchars(4));
end function;
-- function for loading the init values
impure function InitRamFromFile (file_name : in string) return MEM_TYPE is
FILE init_file : text;-- is in file_name;
variable rline : line;
variable memory : MEM_TYPE;
-- variable offs : integer := 0;
variable count : integer;
variable linemode : integer;
variable addr : integer;
variable tmp_chr : character;
variable tmp_byte : string(1 to 2);--BYTE_STRING;
variable tmp_word : string(1 to 4);--WORD_STRING;
variable tmp_addr : integer;
variable tmp_v : std_logic_vector(MEM_WIDTH-1 downto 0);
begin
-- first just null everything
for i in 0 to MEM_DEPTH-1 loop
memory(i) := (others => '0');
end loop;
file_open(init_file, file_name, READ_MODE);
-- read rom file
while (not endfile(init_file)) loop
readline (init_file, rline);
exit when endfile (init_file);
read (rline, tmp_chr);
if tmp_chr = ':' then --beginning of line is correct
--how much to read
read (rline, tmp_byte);
count := BYTE_TO_INT(tmp_byte);
--addr
read (rline, tmp_word);
addr := WORD_TO_INT(tmp_word);
--line mode
read (rline, tmp_byte);
linemode := BYTE_TO_INT(tmp_byte);
if linemode = 0 then
-- loop every PROGRAM-WORD
for i in 0 to (count/(MEM_WIDTH/8) - 1) loop
tmp_v := (others=>'0');
-- loop for every BYTE IN PROGRAM-WORD
for j in 0 to MEM_WIDTH/8-1 loop
read (rline, tmp_byte);
tmp_v((j+1)*8-1 downto j*8) := std_logic_vector(to_unsigned(BYTE_TO_INT(tmp_byte),8));
end loop;
-- store in memory
memory(addr/(MEM_WIDTH/8) + i) := tmp_v;
end loop;
end if;
end if;
end loop;
file_close(init_file);
return memory;
end function;
-- define memory and initialize it
signal memory : MEM_TYPE := InitRamFromFile(INIT_FILE_NAME);
signal mem_addr : std_logic_vector(PRGM_MEM-1 downto 0);
signal mem_doa : std_logic_vector(15 downto 0);
signal mem_we : std_logic;
-- output register
signal reg_cmd_out : std_logic_vector(MEM_WIDTH-1 downto 0);
signal reg_const_out : std_logic_vector(MEM_WIDTH-1 downto 0);
signal reg_lpmspm : std_logic_vector(MEM_WIDTH-1 downto 0);
begin
mem_addr <= addr;
---------------------------------------------------
-- infering the block ram
process(clk)
begin
if clk'event and clk = '1' then
data <= memory(to_integer(unsigned(addr)));
end if;
end process;
end architecture;
|
gpl-2.0
|
c57d5fa2e78dc7a9f5b2430aa8bbfa2e
| 0.51917 | 3.680564 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/leon3s.vhd
| 1 | 6,626 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end;
architecture rtl of leon3s is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc
);
end;
|
gpl-2.0
|
28ba6225fb04d3dee32a9b6ad1380f0a
| 0.465439 | 3.96529 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/grpci2/grpci2_phy.vhd
| 1 | 25,488 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2_phy
-- File: grpci2_phy.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: Logic controlled by the PCI control signals in the GRPCI2 core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config.all;
use grlib.config_types.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2_phy is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end;
architecture rtl of grpci2_phy is
constant oeon : std_logic := conv_std_logic_vector(oepol,1)(0);
constant oeoff : std_logic := not conv_std_logic_vector(oepol,1)(0);
constant ones32 : std_logic_vector(31 downto 0) := (others => '1');
type phy_m_reg_type is record
state : pci_master_state_type;
cfi : integer range 0 to 2;
pi_irdy_or_trdy : std_logic;
last : std_logic_vector(1 downto 0);
hold : std_logic_vector(1 downto 0);
term : std_logic_vector(1 downto 0);
end record;
type phy_t_reg_type is record
cfi : integer range 0 to 2;
pi_irdy_or_trdy : std_logic;
hold : std_logic_vector(0 downto 0);
stop : std_logic;
abort : std_logic;
diswithout : std_logic;
addr_perr : std_logic;
end record;
type phy_reg_type is record
po : pci_reg_out_type;
m : phy_m_reg_type;
t : phy_t_reg_type;
end record;
signal pr, prin : phy_reg_type;
signal pi, piin, piin_buf : pci_in_type; -- Registered PCI signals.
signal po, poin, po_keep : pci_reg_out_type; -- PCI output signals (to drive pads)
signal poin_keep : std_logic_vector(90 downto 0);
signal raden, rinaden, rinaden_tmp : std_logic_vector(31 downto 0);
signal pcirst : std_logic_vector(2 downto 0); -- PCI reset
signal xarst : std_ulogic;
signal pcisynrst : std_ulogic;
attribute sync_set_reset of pcisynrst : signal is "true";
attribute syn_keep : boolean;
attribute syn_keep of poin_keep : signal is true;
begin
phycomb : process(pcii, pr, pi, po, phyi, pcisynrst, rinaden)
variable pv : phy_reg_type;
variable pci : pci_in_type;
begin
-- defaults ---------------------------------------------------------------------
pv := pr;
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.lock := '1'; pv.po.devsel := '1';
pv.po.serr := '1';
pv.po.devselen := oeoff; pv.po.trdyen := oeoff; pv.po.stopen := oeoff;
pv.po.aden := (others => oeoff); pv.po.cbeen := (others => oeoff);
pv.po.frameen := oeoff; pv.po.irdyen := oeoff;
pv.po.perren := oeoff; pv.po.serren := oeoff;
pv.po.reqen := oeon; -- Always on (point-to-point signal, tri-state during reset)
-- PCI input mux ----------------------------------------------------------------
pci := pcii;
if bypass /= 0 then
if pr.po.aden(0) = oeon then pci.ad := pr.po.ad; end if;
if pr.po.cbeen(0) = oeon then pci.cbe := pr.po.cbe; end if;
if pr.po.frameen = oeon then pci.frame := pr.po.frame; end if;
if pr.po.irdyen = oeon then pci.irdy := pr.po.irdy; end if;
if pr.po.trdyen = oeon then pci.trdy := pr.po.trdy; end if;
if pr.po.stopen = oeon then pci.stop := pr.po.stop; end if;
if pr.po.paren = oeon then pci.par := pr.po.par; end if;
if pr.po.devselen = oeon then pci.devsel := pr.po.devsel; end if;
if pr.po.perren = oeon then pci.perr := pr.po.perr; end if;
if pr.po.serren = oeon then pci.serr := pr.po.serren; end if;
end if;
-- Master -----------------------------------------------------------------------
pv.m.pi_irdy_or_trdy := pi.irdy or pi.trdy;
if ((not (pr.po.irdy or pci.trdy)) and pr.m.pi_irdy_or_trdy) = '1' then
if pr.m.state = pm_m_data or pr.m.state = pm_turn_ar then
--pv.m.cfi := pr.m.cfi + 1;
case pr.m.cfi is
when 0 => pv.m.cfi := 1;
when 1 => pv.m.cfi := 2;
when others => pv.m.cfi := 0;
end case;
end if;
elsif ((pr.po.irdy or pci.trdy) and (not pr.m.pi_irdy_or_trdy)) = '1' then
if pr.m.state = pm_m_data or pr.m.state = pm_turn_ar then
--pv.m.cfi := pr.m.cfi - 1;
case pr.m.cfi is
when 2 => pv.m.cfi := 1;
when 1 => pv.m.cfi := 0;
when others => pv.m.cfi := 0;
end case;
end if;
end if;
-- PCI state machine
case pr.m.state is
when pm_idle =>
if pci.gnt = '0' and (pci.frame and pci.irdy) = '1' then
if phyi.m_request = '1' then pv.m.state := pm_addr;
else pv.m.state := pm_dr_bus; end if;
end if;
pv.m.cfi := 0;
when pm_addr =>
pv.m.state := pm_m_data;
when pm_m_data =>
if pr.po.frame = '0' or (pr.po.frame and pci.trdy and pci.stop and not phyi.m_mabort) = '1' then
pv.m.state := pm_m_data;
elsif (pr.po.frame and (phyi.m_mabort or not pci.stop)) = '1' then
pv.m.state := pm_s_tar;
else
pv.m.state := pm_turn_ar;
end if;
when pm_turn_ar =>
if pci.gnt = '0' then
if phyi.m_request = '1' then pv.m.state := pm_addr; -- remove if no back-to-back
else pv.m.state := pm_dr_bus; end if;
else
pv.m.state := pm_idle;
end if;
when pm_s_tar =>
if pci.gnt = '0' then pv.m.state := pm_dr_bus;
else pv.m.state := pm_idle; end if;
when pm_dr_bus =>
if pci.gnt = '1' then pv.m.state := pm_idle;
elsif phyi.m_request = '1' then pv.m.state := pm_addr; end if;
pv.m.cfi := 0;
when others =>
end case;
if phyi.pr_m_fstate = pmf_fifo then
if (phyi.pv_m_cfifo(0).valid = '1' and phyi.pv_m_cfifo(1).valid = '1' and phyi.pv_m_cfifo(2).valid = '1')
or (phyi.pv_m_cfifo(0).valid = '1' and phyi.pr_m_done_fifo = '1' and not (phyi.pv_m_cfifo(1).valid = '0' and phyi.pv_m_cfifo(2).valid = '1')) then
pv.m.hold(0) := '0';
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar))
or (phyi.pr_m_abort(0)) = '1' then
if phyi.pr_m_cfifo(pv.m.cfi).last = '1' and pr.m.last(0) = '0' then pv.m.last(0) := '1'; end if; -- This is the last data phase
pv.m.last(1) := pr.m.last(0);
if phyi.pr_m_done_fifo = '1' and phyi.pr_m_cfifo(pv.m.cfi).valid = '0' then pv.m.last(1) := '1'; end if; -- This is the last data phase
pv.m.hold(1) := pr.m.hold(0);
end if;
if (pr.m.state = pm_m_data or pr.m.state = pm_addr) and phyi.pr_m_cfifo(pv.m.cfi).hold = '1' then pv.m.hold(0) := '1'; end if; -- Transfer not done but no avalible fifo => deassert IRDY#
if (pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar) then
pv.m.last := (others => '0');
pv.m.hold(0) := '0';
end if;
if phyi.pr_m_cfifo(0).last = '1' and phyi.pr_m_first(0) = '1' and pr.m.state = pm_addr and (phyi.pr_m_cbe_cmd = MEM_WRITE or phyi.pr_m_cbe_cmd = CONF_WRITE or phyi.pr_m_cbe_cmd = IO_WRITE) then pv.m.last := "11"; end if; -- Single data phase
if phyi.pr_m_first(1) = '1' and pr.m.state = pm_m_data and phyi.pr_m_cfifo(pv.m.cfi).last = '1' then pv.m.last(0) := '1'; end if; -- This is the last data phase
end if;
if phyi.pr_m_fstate = pmf_idle then
pv.m.last := (others => '0');
pv.m.hold := (others => '0');
end if;
-- PCI master latency timer timeout
pv.m.term := phyi.pv_m_term;
if pci.gnt = '1' then
if phyi.pr_m_ltimer = x"00" and pr.m.state = pm_m_data and phyi.pr_m_burst = '1' and phyi.pr_m_fstate /= pmf_idle then
pv.m.term(0) := '1';
end if;
end if;
-- FRAME#
if (pci.frame and pci.irdy and not pci.gnt and phyi.m_request) = '1' -- Address phase
or (pr.po.frame = '0' and phyi.m_mabort = '0' -- Not Master abort
and (pr.po.irdy or pci.stop) = '1' -- Not Disconnect
and ((phyi.pr_m_first(0) or not (pr.po.irdy or pci.trdy)) and (phyi.pr_m_cfifo(pv.m.cfi).last or pv.m.term(0))) = '0') then -- Not last data phase
pv.po.frame := '0';
end if;
-- IRDY#
if (pr.po.frame = '0' and phyi.m_mabort = '0' and (pr.m.hold(0) = '0' or (not pr.po.irdy and (pci.trdy and pci.stop)) = '1')) -- Access ongoing, not Master abort, not hold (no data available)
or (pr.po.frame and not phyi.m_mabort and not pr.po.irdy and (pci.trdy and pci.stop)) = '1' then -- Last data phase, not Master abort (if first access, can get master abort)
pv.po.irdy := '0';
end if;
-- Output enable ctrl signals
if (pci.frame and pci.irdy and not pci.gnt) = '1' -- Address phase
or pr.po.frame = '0' -- Access ongoing
or (not pr.po.irdy and (pci.stop and pci.trdy)) = '1' then -- Last data phase
pv.po.frameen := oeon;
pv.po.cbeen := (others => oeon);
end if;
pv.po.irdyen := pr.po.frameen;
-- REQ#
if (phyi.m_request) = '1' and (phyi.m_mabort or phyi.pr_m_abort(0)) = '0' then
pv.po.req := '0';
end if;
-- Output enable req
--pv.po.reqen := oeon; -- always on if not in reset
-- CBE#
if pr.po.irdy = '0' or pr.po.req = '0' or phyi.m_request = '1' then
if pr.m.state /= pm_idle and (pr.m.state /= pm_dr_bus) then pv.po.cbe := phyi.pr_m_cbe_data;
else pv.po.cbe := phyi.pr_m_cbe_cmd; end if;
else
pv.po.cbe := (others => '0');
end if;
-- Target -----------------------------------------------------------------------
pv.t.pi_irdy_or_trdy := pi.irdy or pi.trdy;
if (pr.t.pi_irdy_or_trdy and (not (pci.irdy or pr.po.trdy))) = '1' then
if phyi.pr_t_state = pt_s_data or phyi.pr_t_state = pt_turn_ar or phyi.pr_t_state = pt_backoff then
--pv.t.cfi := pr.t.cfi + 1;
case pr.t.cfi is
when 0 => pv.t.cfi := 1;
when 1 => pv.t.cfi := 2;
when others => pv.t.cfi := 0;
end case;
end if;
elsif ((not pr.t.pi_irdy_or_trdy) and (pci.irdy or pr.po.trdy)) = '1' then
if phyi.pr_t_state = pt_s_data or phyi.pr_t_state = pt_turn_ar or phyi.pr_t_state = pt_backoff then
--pv.t.cfi := pr.t.cfi - 1;
case pr.t.cfi is
when 2 => pv.t.cfi := 1;
when 1 => pv.t.cfi := 0;
when others => pv.t.cfi := 0;
end case;
end if;
end if;
pv.t.hold(0) := (phyi.pr_t_cfifo(pv.t.cfi).hold or pr.t.hold(0) or phyi.pv_t_hold_write) and phyi.pv_t_hold_reset;
pv.t.stop := (phyi.pr_t_cfifo(pv.t.cfi).stlast or pr.t.stop) and phyi.pv_t_hold_reset;
if phyi.pr_t_state = pt_s_data and phyi.pr_t_cfifo(pv.t.cfi).err = '1' and (phyi.pr_t_stoped = '0' or pr.t.abort = '1') and phyi.t_retry = '0' then pv.t.abort := '1';
else pv.t.abort := '0'; end if;
pv.t.diswithout := phyi.pv_t_diswithout;
-- Disconnect without data if CBE change in burst
if pci.cbe /= pi.cbe and (phyi.pr_t_state = pt_s_data and phyi.pr_t_fstate = ptf_write) then pv.t.diswithout := '1'; end if;
-- Parity error detected on address phase
if (phyi.pr_t_state = pt_idle or phyi.pr_t_state = pt_turn_ar) and pi.frame = '0' then
pv.t.addr_perr := (pci.par xor xorv(pi.ad & pi.cbe));
else
pv.t.addr_perr := '0';
end if;
-- TRDY#
if (phyi.pr_t_state = pt_s_data and ((phyi.t_ready and not phyi.t_retry) = '1' and pv.t.diswithout = '0' and
pv.t.abort = '0') and (pr.po.stop and not phyi.pr_t_stoped) = '1' and (phyi.pr_t_first_word or not pci.frame) = '1') -- Target accessed, data/fifo available, not stoped
or (not pr.po.trdy and pci.irdy) = '1' then -- During master waitstates
pv.po.trdy := '0';
end if;
-- STOP#
if
(pr.po.stop = '1' and phyi.pr_t_stoped = '0' and phyi.pr_t_lcount = "111" and pr.po.trdy = '1') -- latency timerout
or ((
((phyi.t_abort = '1' or pv.t.diswithout = '1') and (pci.irdy or pr.po.trdy) = '0' and pci.frame = '0') -- transfer done or disconnect without data (when cbe has changed during write to target)
or (pv.t.abort = '1' and (((pci.irdy or pr.po.trdy) = '0' and pci.frame = '0') or phyi.pr_t_first_word = '1')) -- To signal target abort
or ((phyi.pr_t_cfifo(0).valid and phyi.pr_t_cfifo(0).hold and phyi.pr_t_cfifo(0).stlast and phyi.pr_t_first_word) = '1') -- When first word in this access is the last word in the transfer
) and pr.po.stop = '1' and phyi.pr_t_stoped = '0') -- Only stop when master is ready (and target ready)
or (pr.po.stop = '0' and pci.frame = '0') -- When stop and frame are asserted
or (phyi.t_retry = '1' and pr.po.stop = '1' and phyi.pr_t_stoped = '0') then -- To signal retry
pv.po.stop := '0';
end if;
-- DEVSEL#
if (phyi.pr_t_state /= pt_s_data and phyi.pv_t_state = pt_s_data)
or (pr.po.devsel = '0' and (pci.frame and not pci.irdy and not (pr.po.trdy and pr.po.stop)) = '0'
and pv.t.abort = '0' -- To signal target abort
) then
pv.po.devsel := '0';
end if;
-- Output enable ctrl signals
if phyi.pv_t_state = pt_s_data or phyi.pv_t_state = pt_backoff then
pv.po.devselen := oeon; pv.po.trdyen := oeon; pv.po.stopen := oeon;
end if;
-- Master & Target --------------------------------------------------------------
-- AD
if (pr.m.state /= pm_idle and pr.m.state /= pm_dr_bus and phyi.pr_m_fstate = pmf_fifo) then
pv.po.ad := phyi.pr_m_cfifo(pv.m.cfi).data; -- PCI master data
elsif (phyi.pr_t_state = pt_s_data and phyi.pv_t_state /= pt_turn_ar) then
pv.po.ad := phyi.pr_t_cfifo(pv.t.cfi).data; -- PCI target data
else
pv.po.ad := phyi.pr_m_addr; -- Address
end if;
-- Output enable AD [target]
if phyi.pr_t_state = pt_s_data and phyi.pv_t_state /= pt_turn_ar and phyi.pr_t_cur_acc_0_read = '1'
and (pci.frame and (not pr.po.stop or not pr.po.trdy)) = '0' then
pv.po.aden := (others => oeon);
end if;
-- Output enable AD [master]
if (pcii.frame and pcii.irdy and not pcii.gnt) = '1'
or ((pr.m.state = pm_addr or pr.m.state = pm_m_data) and phyi.pr_m_fstate /= pmf_read and (pr.po.frame and (not pci.stop or not pci.trdy)) = '0') then
pv.po.aden := (others => oeon);
end if;
-- PAR
pv.po.par := xorv(pr.po.ad & pci.cbe);
-- Output enable PAR
pv.po.paren := pr.po.aden(15); -- AD[15] should be closest to PAR
-- PERR
pv.po.perr := pi.irdy or pi.trdy or not (pci.par xor xorv(pi.ad & pi.cbe)); -- Signal perr two cycles after data phase is completed
-- Output enable PERR
if phyi.pr_conf_comm_perren = '1' and -- Parity error response enable bit[6] = 1
(phyi.pr_m_perren(0) = '1' -- During master read
or (phyi.pr_t_state = pt_s_data and phyi.pr_t_cur_acc_0_read = '0') -- Write to target
or (pr.po.perr = '0' and pr.po.perren = oeon)) then -- Parity error on last phase
pv.po.perren := oeon;
end if;
-- SERR & Output enable for SERR
if phyi.pr_conf_comm_perren = '1' and phyi.pr_conf_comm_serren = '1' and pv.t.addr_perr = '1' then
pv.po.serren := oeon;
end if;
-- PCI reset --------------------------------------------------------------------
-- soft reset
if (pcisynrst and not phyi.pcisoftrst(2) and not phyi.pcisoftrst(1)) = '0' then -- Master reset
-- Master
pv.m.state := pm_idle;
pv.m.cfi := 0;
pv.m.hold := (others => '0');
pv.m.term := (others => '0');
end if;
if (pcisynrst and not phyi.pcisoftrst(2) and not phyi.pcisoftrst(0)) = '0' then -- Target reset
-- Target
pv.t.cfi := 0;
pv.t.hold := (others => '0');
pv.t.stop := '0';
pv.t.addr_perr := '0';
end if;
if (pcisynrst and not phyi.pcisoftrst(2)) = '0' then -- Hard reset
-- PCI signals
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.devsel := '1';
end if;
---------------------------------------------------------------------------------
piin <= pci;
prin <= pv;
poin <= pv.po;
phyo.pciv <= pci;
phyo.pr_m_state <= pr.m.state;
phyo.pr_m_last <= pr.m.last;
phyo.pr_m_hold <= pr.m.hold;
phyo.pr_m_term <= pr.m.term;
phyo.pr_t_hold <= pr.t.hold;
phyo.pr_t_stop <= pr.t.stop;
phyo.pr_t_abort <= pr.t.abort;
phyo.pr_t_diswithout <= pr.t.diswithout;
phyo.pr_t_addr_perr <= pr.t.addr_perr;
phyo.pcirsto(0) <= pcisynrst;
phyo.pr_po <= pr.po;
phyo.pio <= pi;
phyo.poo <= po;
-- PCI output signals
pcio.ad <= po.ad; pcio.vaden <= po.aden;
pcio.cbe <= po.cbe; pcio.cbeen <= po.cbeen;
pcio.frame <= po.frame; pcio.frameen <= po.frameen;
pcio.irdy <= po.irdy; pcio.irdyen <= po.irdyen;
pcio.trdy <= po.trdy; pcio.trdyen <= po.trdyen;
pcio.stop <= po.stop; pcio.stopen <= po.stopen;
pcio.devsel <= po.devsel; pcio.devselen <= po.devselen;
pcio.par <= po.par; pcio.paren <= po.paren;
pcio.perr <= po.perr; pcio.perren <= po.perren;
pcio.req <= po.req; pcio.reqen <= po.reqen;
pcio.int <= '0'; pcio.inten <= phyi.pciinten(0);
pcio.vinten <= phyi.pciinten;
pcio.rst <= phyi.pcirstout;
pcio.serr <= po.serr; pcio.serren <= po.serren;
if SCANTEST/=0 and GRLIB_CONFIG_ARRAY(GRLIB_EXTERNAL_TESTOEN)=0 then
if phyi.testen='1' then
pcio.vaden <= (others => phyi.testoen);
pcio.cbeen <= (others => phyi.testoen);
pcio.frameen <= phyi.testoen;
pcio.irdyen <= phyi.testoen;
pcio.trdyen <= phyi.testoen;
pcio.stopen <= phyi.testoen;
pcio.devselen <= phyi.testoen;
pcio.paren <= phyi.testoen;
pcio.perren <= phyi.testoen;
pcio.reqen <= phyi.testoen;
pcio.inten <= phyi.testoen;
pcio.vinten <= (others => phyi.testoen);
pcio.rst <= phyi.testoen xor oeon;
pcio.serren <= phyi.testoen;
end if;
end if;
-- Unused signals
pcio.lock <= oeoff; pcio.locken <= oeoff;
pcio.aden <= oeoff; pcio.ctrlen <= oeoff;
pcio.pme_enable <= oeoff; pcio.pme_clear <= oeoff;
pcio.power_state <= (others => oeoff);
end process;
-- po_keep <= poin_keep;
poin_keep(31 downto 0) <= poin.ad; po_keep.ad <= poin_keep(31 downto 0);
poin_keep(63 downto 32) <= poin.aden; po_keep.aden <= poin_keep(63 downto 32);
poin_keep(67 downto 64) <= poin.cbe; po_keep.cbe <= poin_keep(67 downto 64);
poin_keep(71 downto 68) <= poin.cbeen; po_keep.cbeen <= poin_keep(71 downto 68);
poin_keep( 72) <= poin.frame; po_keep.frame <= poin_keep( 72);
poin_keep( 73) <= poin.frameen; po_keep.frameen <= poin_keep( 73);
poin_keep( 74) <= poin.irdy; po_keep.irdy <= poin_keep( 74);
poin_keep( 75) <= poin.irdyen; po_keep.irdyen <= poin_keep( 75);
poin_keep( 76) <= poin.trdy; po_keep.trdy <= poin_keep( 76);
poin_keep( 77) <= poin.trdyen; po_keep.trdyen <= poin_keep( 77);
poin_keep( 78) <= poin.stop; po_keep.stop <= poin_keep( 78);
poin_keep( 79) <= poin.stopen; po_keep.stopen <= poin_keep( 79);
poin_keep( 80) <= poin.devsel; po_keep.devsel <= poin_keep( 80);
poin_keep( 81) <= poin.devselen; po_keep.devselen <= poin_keep( 81);
poin_keep( 82) <= poin.par; po_keep.par <= poin_keep( 82);
poin_keep( 83) <= poin.paren; po_keep.paren <= poin_keep( 83);
poin_keep( 84) <= poin.perr; po_keep.perr <= poin_keep( 84);
poin_keep( 85) <= poin.perren; po_keep.perren <= poin_keep( 85);
poin_keep( 86) <= poin.lock; po_keep.lock <= poin_keep( 86);
poin_keep( 87) <= poin.locken; po_keep.locken <= poin_keep( 87);
poin_keep( 88) <= poin.req; po_keep.req <= poin_keep( 88);
poin_keep( 89) <= poin.reqen; po_keep.reqen <= poin_keep( 89);
poin_keep( 90) <= poin.serren; po_keep.serren <= poin_keep( 90);
po_keep.inten <= phyi.pciinten(0);
po_keep.vinten <= phyi.pciinten;
xarst <= phyi.testrst when scantest/=0 and phyi.testen='1' else pcirst(0);
phyreg : process(pciclk, phyi.pciasyncrst, pcirst, xarst)
begin
if rising_edge(pciclk) then
pr <= prin;
pi <= piin;
po <= po_keep;
if iotmact /= '0' then
po.ad <= iotdout(31 downto 0);
po.cbe <= iotdout(35 downto 32);
po.frame <= iotdout(36);
po.irdy <= iotdout(37);
po.trdy <= iotdout(38);
po.par <= iotdout(39);
po.perr <= iotdout(40);
po.serr <= iotdout(41);
po.devsel <= iotdout(42);
po.stop <= iotdout(43);
po.req <= iotdout(44);
po.reqen <= oeon;
if iotmoe /= '0' then
po.aden <= (others => oeon); po.cbeen <= (others => oeon); po.frameen <= oeon;
po.devselen <= oeon; po.trdyen <= oeon; po.irdyen <= oeon; po.stopen <= oeon;
po.paren <= oeon; po.perren <= oeon; po.locken <= oeon;
po.inten <= oeon; po.vinten <= (others => oeon); po.serren <= oeon;
else
po.aden <= (others => oeoff); po.cbeen <= (others => oeoff); po.frameen <= oeoff;
po.devselen <= oeoff; po.trdyen <= oeoff; po.irdyen <= oeoff; po.stopen <= oeoff;
po.paren <= oeoff; po.perren <= oeoff; po.locken <= oeoff;
po.inten <= oeoff; po.vinten <= (others => oeoff); po.serren <= oeoff;
end if;
end if;
pcisynrst <= pcirst(1) and pcirst(2);
pcirst(0) <= pcirst(1) and pcirst(2);
pcirst(1) <= pcirst(2); pcirst(2) <= '1';
end if;
if phyi.pciasyncrst = '0' then pcirst <= (others => '0'); end if;
if xarst = '0' then -- asynch reset required
po.ad <= (others => '1'); pi.ad <= (others => '1'); -- for virtex-4 all registers in IOB need to have same reset
po.trdy <= '1'; pi.trdy <= '1'; po.stop <= '1'; pi.stop <= '1';
po.irdy <= '1'; pi.irdy <= '1'; po.frame <= '1'; pi.frame <= '1';
po.cbe <= (others => '1'); pi.cbe <= (others => '1');
po.par <= '1'; pi.par <= '1';
po.perr <= '1'; pi.perr <= '1';
po.devsel <= '1'; pi.devsel <= '1';
pi.serr <= '1';
po.aden <= (others => oeoff); po.cbeen <= (others => oeoff); po.frameen <= oeoff;
po.devselen <= oeoff; po.trdyen <= oeoff; po.irdyen <= oeoff; po.stopen <= oeoff;
po.paren <= oeoff; po.perren <= oeoff; po.locken <= oeoff; po.reqen <= oeoff;
po.inten <= oeoff; po.vinten <= (others => oeoff); po.serren <= oeoff;
end if;
end process;
iotdin(45) <= pi.idsel;
iotdin(44) <= pi.gnt;
iotdin(43) <= pi.stop;
iotdin(42) <= pi.devsel;
iotdin(41) <= pi.serr;
iotdin(40) <= pi.perr;
iotdin(39) <= pi.par;
iotdin(38) <= pi.trdy;
iotdin(37) <= pi.irdy;
iotdin(36) <= pi.frame;
iotdin(35 downto 32) <= pi.cbe;
iotdin(31 downto 0) <= pi.ad;
end;
|
gpl-2.0
|
13ce7b5720219669fd4c9ca91cb02656
| 0.536017 | 3.096962 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/ptf/pt_pci_master.vhd
| 1 | 19,324 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_master
-- File: pt_pci_master.vhd
-- Author: Nils Johan Wessman, Aeroflex Gaisler
-- Description: PCI Testbench Master
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
use grlib.stdlib.tost;
use grlib.testlib.print;
entity pt_pci_master is
generic (
slot : integer := 0;
tval : time := 7 ns);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- Debug interface signals
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end pt_pci_master;
architecture behav of pt_pci_master is
-- NEW =>
type access_element_type;
type access_element_ptr is access access_element_type;
type access_element_type is record
acc : pt_pci_access_type;
nxt : access_element_ptr;
end record;
constant idle_acc : pt_pci_access_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'),
0, 0, 0, 0, false, false, false, false, 0, 0);
signal pci_core : pt_pci_master_in_type;
signal core_pci : pt_pci_master_out_type;
-- Description: Insert a access at the "tail" of the linked list of accesses
procedure add_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type) is
variable elem : access_element_ptr;
begin -- insert_access
elem := acc_tail;
if elem /= NULL then
elem.nxt := new access_element_type'(acc, NULL);
acc_tail := elem.nxt;
else
acc_head := new access_element_type'(acc, NULL);
acc_tail := acc_head;
end if;
end add_acc;
-- Description: Get the access at the "head" of the linked list of accesses
-- and remove if from the list
procedure pop_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem : access_element_ptr;
begin -- pop_access
elem := acc_head;
if elem /= NULL then
found := true;
acc <= elem.acc;
if elem = acc_tail then
acc_head := NULL;
acc_tail := NULL;
else
acc_head := elem.nxt;
end if;
deallocate(elem);
else
found := false;
acc <= idle_acc;
end if;
end pop_acc;
-- Description: Searches the list for a result to a particular id.
procedure get_res (
variable res_head : inout access_element_ptr;
variable res_tail : inout access_element_ptr;
signal accin : in pt_pci_access_type;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- get_result
prev := res_head;
elem := res_head;
while elem /= NULL and not lfound loop
-- Check if result is a match for id
if accin.id = elem.acc.id then
acc <= elem.acc;
lfound := true;
if prev = res_head then
res_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = res_tail then
res_tail := NULL;
end if;
deallocate(elem);
end if;
if not lfound then
prev := elem;
elem := elem.nxt;
end if;
end loop;
if lfound then found := true;
else found := false; acc <= idle_acc; end if;
end get_res;
-- Description:
procedure rm_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type;
constant rmall : in boolean )is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- rm_access
prev := acc_head;
elem := acc_head;
while elem /= NULL and not lfound loop
if rmall = true then
prev := elem;
elem := elem.nxt;
deallocate(prev);
else
if acc.addr = elem.acc.addr then
if prev = acc_head then
acc_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = acc_tail then
acc_tail := NULL;
end if;
deallocate(elem);
lfound := true;
else
prev := elem;
elem := elem.nxt;
end if;
end if;
end loop;
if rmall = true then
acc_head := NULL;
acc_tail := NULL;
end if;
end rm_acc;
-- <= NEW
type state_type is(idle, addr, data, turn, active, done);
type reg_type is record
state : state_type;
pcien : std_logic_vector(3 downto 0);
perren : std_logic_vector(1 downto 0);
read : std_logic;
grant : std_logic;
perr_ad : std_logic_vector(31 downto 0);
perr_cbe : std_logic_vector(3 downto 0);
devsel_timeout : integer range 0 to 3;
pci : pci_type;
acc : pt_pci_access_type;
parerr : std_logic;
end record;
signal r,rin : reg_type;
begin
-- NEW =>
core_acc : process
variable acc_head : access_element_ptr := NULL;
variable acc_tail : access_element_ptr := NULL;
variable res_head : access_element_ptr := NULL;
variable res_tail : access_element_ptr := NULL;
variable res_to_find : pt_pci_access_type := idle_acc;
variable found : boolean;
begin
if pci_core.req /= '1' and dbgi.req /= '1' then
wait until pci_core.req = '1' or dbgi.req = '1';
end if;
if dbgi.req = '1' then
dbgo.res_found <= '0';
if dbgi.add = true then
add_acc(acc_head, acc_tail, dbgi.acc);
elsif dbgi.remove = true then
rm_acc(acc_head, acc_tail, dbgi.acc, dbgi.rmall);
elsif dbgi.get_res = true then
dbgo.valid <= false;
get_res(res_head, res_tail, dbgi.acc, dbgo.acc, found);
if found = true then dbgo.valid <= true; res_to_find := idle_acc;
else res_to_find := dbgi.acc; end if;
else
dbgo.valid <= false;
pop_acc(acc_head, acc_tail, dbgo.acc, found);
if found = true then dbgo.valid <= true; end if;
end if;
dbgo.ack <= '1';
wait until dbgi.req = '0';
dbgo.ack <= '0';
end if;
if pci_core.req = '1' then
if pci_core.add = true then
add_acc(acc_head, acc_tail, pci_core.acc);
elsif pci_core.add_res = true then
add_acc(res_head, res_tail, pci_core.acc);
if res_to_find.valid = true and pci_core.acc.id = res_to_find.id then
dbgo.res_found <= '1';
end if;
else
core_pci.valid <= false;
pop_acc(acc_head, acc_tail, core_pci.acc, found);
if found = true then core_pci.valid <= true; end if;
end if;
core_pci.ack <= '1';
wait until pci_core.req = '0';
core_pci.ack <= '0';
end if;
end process;
-- <= NEW
pt_pci_core : process
procedure sync_with_core is
begin
pci_core.req <= '1';
wait until core_pci.ack = '1';
pci_core.req <= '0';
wait until core_pci.ack = '0';
end sync_with_core;
function check_data(
constant pci_data : std_logic_vector(31 downto 0);
constant comp_data : std_logic_vector(31 downto 0);
constant cbe : std_logic_vector(3 downto 0))
return boolean is
variable res : boolean := true;
variable data : std_logic_vector(31 downto 0);
begin
data := comp_data;
if cbe(0) = '1' then data(7 downto 0) := (others => '-'); end if;
if cbe(1) = '1' then data(15 downto 8) := (others => '-'); end if;
if cbe(2) = '1' then data(23 downto 16) := (others => '-'); end if;
if cbe(3) = '1' then data(31 downto 24) := (others => '-'); end if;
for i in 0 to 31 loop
if pci_data(i) /= data(i) and data(i) /= '-' then res := false; end if;
end loop;
return res;
end check_data;
variable v : reg_type;
variable vpciin : pci_type;
begin
if to_x01(pciin.syst.rst) = '0' then
v.state := idle;
v.pcien := (others => '0');
v.pci := pci_idle;
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
v.read := '0';
v.perren := (others => '0');
v.parerr := '0';
elsif rising_edge(pciin.syst.clk) then
v := r;
vpciin := pciin;
v.grant := to_x01(vpciin.ifc.frame) and to_x01(vpciin.ifc.irdy) and not r.pci.arb.req(slot) and not to_x01(vpciin.arb.gnt(slot));
v.pcien(1) := r.pcien(0); v.pcien(2) := r.pcien(1);
v.pci.ad.par := xorv(r.pci.ad.ad & r.pci.ad.cbe & r.parerr);
v.perr_ad := vpciin.ad.ad; v.perr_cbe := vpciin.ad.cbe;
v.pci.err.perr := (not xorv(r.perr_ad & r.perr_cbe & to_x01(vpciin.ad.par))) or not r.read;
v.perren(1) := r.perren(0);
case r.state is
when idle =>
if core_pci.valid = true then
if r.acc.idle = false then
v.pci.arb.req(slot) := '0';
if v.grant = '1' then
v.pcien(0) := '1';
v.pci.ifc.frame := '0';
v.pci.ad.ad := core_pci.acc.addr;
v.pci.ad.cbe := core_pci.acc.cbe_cmd;
if core_pci.acc.parerr = 2 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := addr;
v.read := '0';
v.perren := (others => '0');
end if;
else -- Idle cycle
if r.acc.ws <= 0 then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
else
v.acc.ws := r.acc.ws - 1;
end if;
end if;
else
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
end if;
when addr =>
if r.acc.last = true and r.acc.ws <= 0 then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
if (r.acc.cbe_cmd = MEM_READ or r.acc.cbe_cmd = MEM_R_MULT or r.acc.cbe_cmd = MEM_R_LINE
or r.acc.cbe_cmd = IO_READ or r.acc.cbe_cmd = CONF_READ) then
v.read := '1';
end if;
if r.acc.ws <= 0 then v.pci.ifc.irdy := '0'; v.pci.ad.ad := r.acc.data;
else v.acc.ws := r.acc.ws - 1; v.pci.ad.ad := (others => '-'); end if;
v.pci.ad.cbe := r.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := data;
v.devsel_timeout := 0;
when data =>
if r.pci.ifc.irdy = '1' and r.acc.ws /= 0 then
v.acc.ws := r.acc.ws - 1;
else
v.pci.ifc.irdy := '0';
v.pci.ad.ad := r.acc.data;
if r.acc.last = true or to_x01(vpciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
end if;
if to_x01(vpciin.ifc.devsel) = '1' then
if r.devsel_timeout < 3 then
v.devsel_timeout := r.devsel_timeout + 1;
else
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
if r.pci.ifc.frame = '1' then
v.pcien(0) := '0';
v.state := idle;
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: MASTER ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: MASTER ABORT");
end if;
end if;
end if;
end if;
end if;
--if to_x01(vpciin.ifc.trdy) = '0' and r.pci.ifc.irdy = '0' then
if (to_x01(vpciin.ifc.trdy) = '0' or (r.acc.cod = 1 and to_x01(vpciin.ifc.stop) = '0')) and r.pci.ifc.irdy = '0' then
if r.read = '1' then v.perren(0) := '1'; end if; -- only drive perr from read
if r.pci.ifc.frame = '1' then -- done
v.pcien(0) := '0'; v.pci.ifc.irdy := '1';
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= vpciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
v.state := idle;
else
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= vpciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if core_pci.valid = true then
v.pci.ad.cbe := v.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
if v.acc.ws <= 0 then
v.pci.ad.ad := v.acc.data;
if v.acc.last = true or to_x01(vpciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
else
v.pci.ad.ad := (others => '-');
if v.pci.ifc.frame = '0' then v.pci.ifc.irdy := '1'; end if; -- If frame => '1', do not add waitstates (irdey => '1')
v.acc.ws := v.acc.ws - 1;
end if;
else
assert false
report "No valid acces in list, access required! (no access is marked LAST)"
severity FAILURE;
end if;
end if;
if r.acc.debug >= 1 then
if r.acc.cod = 1 and to_x01(vpciin.ifc.stop) = '0' and to_x01(vpciin.ifc.trdy) = '1' then
if r.read = '1' then
print("PCITBM Read[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
else
print("PCITBM WRITE[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
end if;
else
if r.read = '1' then
if check_data(vpciin.ad.ad, r.pci.ad.ad, r.pci.ad.cbe) = false then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad) & " != " & tost(r.pci.ad.ad));
elsif r.acc.debug >= 2 then
print("PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad));
end if;
else
if r.acc.debug >= 2 then
print("PCITBM Write[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad));
end if;
end if;
end if;
end if;
elsif to_x01(vpciin.ifc.stop) = '0' and r.pci.ifc.frame = '1' then -- Disconnect
v.pcien(0) := '0';
v.pci.ifc.irdy := '1';
v.state := idle;
if to_x01(vpciin.ifc.devsel) = '1' then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: TARGET ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: TARGET ABORT");
end if;
end if;
end if;
end if;
when turn =>
when active =>
when done =>
when others =>
end case;
end if;
r <= v;
wait on pciin.syst.clk, pciin.syst.rst;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when (r.pcien(0) and not r.read) = '1' else (others => 'Z') after tval;
pciout.ad.cbe <= r.pci.ad.cbe after tval when r.pcien(0) = '1' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.pcien(1) = '1' and (r.read = '0' or r.pcien(3 downto 0) = "0011")) else 'Z' after tval;
pciout.ifc.frame <= r.pci.ifc.frame after tval when r.pcien(0) = '1' else 'Z' after tval;
pciout.ifc.irdy <= r.pci.ifc.irdy after tval when r.pcien(1) = '1' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when (r.pcien(2) and r.perren(1)) = '1' else 'Z' after tval;
pciout.err.serr <= r.pci.err.serr after tval when r.pcien(2) = '1' else 'Z' after tval;
-- Unused signals
pciout.arb <= arb_const;
pciout.arb.req(slot) <= r.pci.arb.req(slot) after tval;
-- Unused signals
pciout.ifc.trdy <= 'Z';
pciout.ifc.stop <= 'Z';
pciout.ifc.devsel <= 'Z';
pciout.ifc.lock <= 'Z';
pciout.ifc.idsel <= (others => 'Z');
pciout.err.serr <= 'Z';
pciout.syst <= syst_const;
pciout.ext64 <= ext64_const;
pciout.cache <= cache_const;
pciout.int <= (others => 'Z');
end;
-- pragma translate_on
|
gpl-2.0
|
539125c797417808cede923f22573d29
| 0.529238 | 3.349047 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-111/testbench.vhd
| 1 | 7,162 |
-------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
library micron;
use micron.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_dram_dqs : std_logic_vector(1 downto 0);
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(1 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic_vector(1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.417 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_dqs(1),
mcb3_dram_dqs => mcb3_dram_dqs(0),
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm(0),
mcb3_dram_udm => mcb3_dram_dm(1),
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>4, lddelay => 15 us)
port map (ck => mcb3_dram_ck, cke => mcb3_dram_cke, csn => csb,
rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n,
dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a,
dq => mcb3_dram_dq, dqs => mcb3_dram_dqs);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
gpl-2.0
|
c1434e7c0deba19224a144f9578d2559
| 0.55222 | 3.360863 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2cmst.vhd
| 1 | 11,738 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cmst
-- File: i2cmst.vhd
-- Author: Jan Andersson - Gaisler Research
-- Contact: [email protected]
-- Description:
--
-- APB interface to OpenCores I2C-master. This is an GRLIB AMBA wrapper
-- that instantiates the byte- and bit-controller of the OpenCores I2C
-- master (OC core developed by Richard Herveille, [email protected]).
-- The OC byte- and bit-controller are located under lib/opencores/i2c
--
-- The original master had a WISHBONE interface with registers
-- aligned at byte boundaries. This wrapper has a slighly different
-- alignment of the registers, and also (optionally) adds a filter
-- filter register (FR):
--
-- +------------+--------------------------------------+
-- | Offset | Bits in word |
-- | |---------+---------+---------+--------+
-- | | 31 - 24 | 23 - 16 | 15 - 8 | 7 - 0 |
-- +------------+---------+---------+---------+--------+
-- | 0x00 | 0x00 | 0x00 | PRERhi | PRERlo |
-- | 0x04 | 0x00 | 0x00 | 0x00 | CTR |
-- | 0x08 | 0x00 | 0x00 | 0x00 | TXR |
-- | 0x08 | 0x00 | 0x00 | 0x00 | RXR |
-- | 0x0C | 0x00 | 0x00 | 0x00 | CR |
-- | 0x0C | 0x00 | 0x00 | 0x00 | SR |
-- | 0x10 | FR |
-- +------------+---------+---------+---------+--------+
--
-- Revision 1 of this core also sets the TIP bit when STO is set.
--
-- Revision 2 of this core adds a filter generic to adjust the low pass filter
--
-- Revision 3 of this core adds yet another filter generic that can be set to
-- make the filter soft configurable.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.i2c.all;
library opencores;
use opencores.i2coc.all;
entity i2cmst is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
oepol : integer range 0 to 1 := 0; -- output enable polarity
filter : integer range 2 to 512 := 2; -- filter bit size
dynfilt : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cmst;
architecture rtl of i2cmst is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant I2CMST_REV : integer := 3;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CMST, 0, I2CMST_REV, pirq),
1 => apb_iobar(paddr, pmask));
constant PRER_addr : std_logic_vector(7 downto 2) := "000000";
constant CTR_addr : std_logic_vector(7 downto 2) := "000001";
constant TXR_addr : std_logic_vector(7 downto 2) := "000010";
constant RXR_addr : std_logic_vector(7 downto 2) := "000010";
constant CR_addr : std_logic_vector(7 downto 2) := "000011";
constant SR_addr : std_logic_vector(7 downto 2) := "000011";
constant FR_addr : std_logic_vector(7 downto 2) := "000100";
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
-- Register interface
type ctrl_reg_type is record -- Control register
en : std_ulogic;
ien : std_ulogic;
end record;
type cmd_reg_type is record -- Command register
sta : std_ulogic;
sto : std_ulogic;
rd : std_ulogic;
wr : std_ulogic;
ack : std_ulogic;
end record;
type sts_reg_type is record -- Status register
rxack : std_ulogic;
busy : std_ulogic;
al : std_ulogic;
tip : std_ulogic;
ifl : std_ulogic;
end record;
-- Core registers
type i2c_reg_type is record
-- i2c registers
prer : std_logic_vector(15 downto 0); -- clock prescale register
ctrl : ctrl_reg_type; -- control register
txr : std_logic_vector(7 downto 0); -- transmit register
cmd : cmd_reg_type; -- command register
sts : sts_reg_type; -- status register
filt : std_logic_vector((filter-1)*dynfilt downto 0); -- filter register
--
irq : std_ulogic;
end record;
-- Signals to and from byte controller block
signal rxr : std_logic_vector(7 downto 0); -- Receive register
signal done : std_logic; -- Signals completion of command
signal rxack : std_logic; -- Received acknowledge
signal busy : std_logic; -- I2C core busy
signal al : std_logic; -- Aribitration lost
signal irst : std_ulogic; -- Internal, negated reset signal
signal iscloen : std_ulogic; -- Internal SCL output enable
signal isdaoen : std_ulogic; -- Internal SDA output enable
-- Register interface
signal r, rin : i2c_reg_type;
signal vcc : std_logic;
begin
-- Byte Controller from OpenCores I2C master,
-- by Richard Herveille ([email protected]). The asynchronous
-- reset is tied to '1'. Only the synchronous reset is used.
vcc <= '1';
byte_ctrl: i2c_master_byte_ctrl
generic map (
filter => filter,
dynfilt => dynfilt)
port map (
clk => clk,
rst => irst,
nReset => vcc,
ena => r.ctrl.en,
clk_cnt => r.prer,
start => r.cmd.sta,
stop => r.cmd.sto,
read => r.cmd.rd,
write => r.cmd.wr,
ack_in => r.cmd.ack,
din => r.txr,
filt => r.filt,
cmd_ack => done,
ack_out => rxack,
i2c_busy => busy,
i2c_al => al,
dout => rxr,
scl_i => i2ci.scl,
scl_o => i2co.scl,
scl_oen => iscloen,
sda_i => i2ci.sda,
sda_o => i2co.sda,
sda_oen => isdaoen);
-- OC I2C logic has active high reset.
irst <= not rstn;
i2co.enable <= r.ctrl.en;
-- Fix output enable polarity
soepol0: if oepol = 0 generate
i2co.scloen <= iscloen;
i2co.sdaoen <= isdaoen;
end generate soepol0;
soepol1: if oepol /= 0 generate
i2co.scloen <= not iscloen;
i2co.sdaoen <= not isdaoen;
end generate soepol1;
comb: process (r, rstn, rxr, rxack, busy, al, done, apbi)
variable v : i2c_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(7 downto 2);
variable apbout : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
-- Command done or arbitration lost, clear command register
if (done or al) = '1' then
v.cmd := ('0', '0', '0', '0', '0');
end if;
-- Update status register
v.sts := (rxack => rxack,
busy => busy,
al => al or (r.sts.al and not r.cmd.sta),
tip => r.cmd.rd or r.cmd.wr or r.cmd.sto,
ifl => done or al or r.sts.ifl);
v.irq := (done or al) and r.ctrl.ien;
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when PRER_addr =>
apbout(15 downto 0) := r.prer;
when CTR_addr =>
apbout(7 downto 6) := r.ctrl.en & r.ctrl.ien;
when RXR_addr =>
apbout(7 downto 0) := rxr;
when SR_addr =>
apbout(7 downto 5) := r.sts.rxack & r.sts.busy & r.sts.al;
apbout(1 downto 0) := r.sts.tip & r.sts.ifl;
when FR_addr =>
if dynfilt /= 0 then apbout(r.filt'range) := r.filt; end if;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when PRER_addr => v.prer := apbi.pwdata(15 downto 0);
when CTR_addr => v.ctrl.en := apbi.pwdata(7);
v.ctrl.ien := apbi.pwdata(6);
when TXR_addr => v.txr := apbi.pwdata(7 downto 0);
when CR_addr =>
-- Check that core is enabled and that WR and RD has been cleared
-- before accepting new command.
if (r.ctrl.en and not (r.cmd.wr or r.cmd.rd)) = '1' then
v.cmd.sta := apbi.pwdata(7);
v.cmd.sto := apbi.pwdata(6);
v.cmd.rd := apbi.pwdata(5);
v.cmd.wr := apbi.pwdata(4);
v.cmd.ack := apbi.pwdata(3);
end if;
-- Bit 0 of CR is interrupt acknowledge. The core will only pulse one
-- interrupt per irq event. Software does not have to clear the
-- interrupt flag...
if apbi.pwdata(0) = '1' then
v.sts.ifl := '0';
end if;
when FR_addr =>
if dynfilt /= 0 then v.filt := apbi.pwdata(r.filt'range); end if;
when others => null;
end case;
end if;
if rstn = '0' then
v.prer := (others => '1');
v.ctrl := ('0', '0');
v.txr := (others => '0');
v.cmd := ('0','0','0','0', '0');
v.sts := ('0','0','0','0', '0');
if dynfilt /= 0 then v.filt := (others => '1'); end if;
end if;
if dynfilt = 0 then v.filt := (others => '0'); end if;
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cmst" & tost(pindex) & ": AMBA Wrapper for OC I2C-master rev " &
tost(I2CMST_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
gpl-2.0
|
d75f8b2cd1d5786eab48fa1210d2f4ac
| 0.516868 | 3.654421 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc3s1000/config.vhd
| 1 | 5,428 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00F0#;
constant CFG_GRGPIO_WIDTH : integer := (18);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
68d5d881a6d87934266d776847f3b064
| 0.643699 | 3.655219 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2s60-ddr/testbench.vhd
| 1 | 10,615 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_ce1n : std_logic;
signal ssram_ce2 : std_logic;
signal ssram_ce3n : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssaddr : std_logic_vector(20 downto 2);
signal ssdata : std_logic_vector(31 downto 0);
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_dqs2 : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (15 downto 0); -- ddr data
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
dqs2delay : delay_wire
generic map(data_width => ddr_dqs'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dqs, b => ddr_dqs2);
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address, data, romsn, oen, writen, open, open,
ssram_ce1n, ssram_ce2, ssram_ce3n, ssram_wen, ssram_bw, ssram_oen, ssaddr, ssdata,
ssram_clk, ssram_adscn, ssram_adsp_n, ssram_adv_n, iosn,
ddr_clkin, ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs2, ddr_ad, ddr_ba, ddr_dq2,
dsubren, dsuact, rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
ddr2: ddrram
generic map (width => 16, abits => 13,
colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, igndqs => 1)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => ssdata,
iAddr => ssaddr(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_ce1n,
iCE2 => ssram_ce2, inCE3 => ssram_ce3n, iZz => gnd);
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
538c997543b62673798c449285feb7ae
| 0.582949 | 3.065261 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/allddr.vhd
| 1 | 47,830 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allddr
-- File: allddr.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: DDR input/output registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allddr is
component rhumc_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component unisim_iddr_reg is
generic ( tech : integer := virtex4; arch : integer := 0);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component gen_iddr_reg
generic (scantest: integer; noasync: integer);
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen: in std_ulogic;
testrst: in std_ulogic);
end component;
component rhumc_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ec_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component unisim_oddr_reg
generic (tech : integer := virtex4; arch : integer := 0);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component gen_oddr_reg
generic (scantest: integer; noasync: integer);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen: in std_ulogic;
testrst: in std_ulogic);
end component;
component axcel_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component axcel_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component nextreme_oddr_reg
port(
CK : in std_ulogic;
DH : in std_ulogic;
DL : in std_ulogic;
DOE : in std_ulogic;
Q : out std_ulogic;
OE : out std_ulogic;
RSTB : in std_ulogic);
end component;
component nextreme_iddr_reg
port(
CK : in std_ulogic;
D : in std_ulogic;
QH : out std_ulogic;
QL : out std_ulogic;
RSTB : in std_ulogic);
end component;
component apa3_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3e_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3e_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3l_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3l_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component igloo2_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component igloo2_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component spartan3e_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex4_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0)
);
end component;
component virtex2_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component stratixii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component cycloneiii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component generic_ddr_phy_wo_pads
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic
);
end component;
component tsmc90_tci_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clk90_sigi_0 : in std_logic;
rclk_sigi_1 : in std_logic;
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
--ddr_clk_fb_out : out std_logic;
--ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqsin : in std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_dqsout : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_dqsoen : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dqin : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dqout : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dqoen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- ddr address
ba : in std_logic_vector ( 1 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
conf : in std_logic_vector(63 downto 0);
tstclkout : out std_logic_vector(3 downto 0)
);
end component;
component virtex5_ddr2_phy_wo_pads
generic (
MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0; ddelayb8: integer := 0;
ddelayb9 : integer := 0; ddelayb10 : integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := virtex5; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr addr
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0)
);
end component;
component stratixii_ddr2_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- PLL locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
component stratixiii_ddr2_phy
generic (
MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := stratix3; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- ddr addrees
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0);
oct : in std_logic
);
end component;
component spartan3a_ddr2_phy
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan3;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end component;
component easic90_ddr2_phy
generic (
tech : integer;
MHz : integer;
clk_mul : integer;
clk_div : integer;
dbits : integer;
rstdelay : integer := 200;
eightbanks : integer range 0 to 1 := 0);
port (
rstn : in std_logic;
clk : in std_logic;
clkout : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_ulogic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic;
ddr_rasb : out std_ulogic;
ddr_casb : out std_ulogic;
ddr_dm : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0);
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (13 downto 0);
ddr_ba : out std_logic_vector (1+eightbanks downto 0);
ddr_dq : inout std_logic_vector (dbits-1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0);
dqout : in std_logic_vector (dbits*2-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0);
dqs_gate : in std_ulogic);
end component;
component spartan6_ddr2_phy_wo_pads
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan6;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3; ncs : integer := 2 );
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0);
ddr_dq_out : out std_logic_vector (dbits-1 downto 0);
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0);
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
component generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
--clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end component;
component n2x_ddr2_phy is
generic (
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
norefclk : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
ctrl2en : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clk270d : in std_logic; -- input clock shifted 270 degrees
-- for operating without PLL
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
rden_pad : inout std_logic_vector(dbits/8-1 downto 0); -- pad delay comp. dummy I/O
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
noen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_logic;
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
-- Pass through to pads
dq_control : in std_logic_vector(17 downto 0);
dqs_control : in std_logic_vector(17 downto 0);
ck_control : in std_logic_vector(17 downto 0);
cmd_control : in std_logic_vector(17 downto 0);
compen : in std_logic;
compupd : in std_logic
);
end component;
component ut90nhbd_ddr_phy_wo_pads is
generic (
MHz: integer := 100;
abits: integer := 15;
dbits: integer := 96;
nclk: integer := 3;
ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_ulogic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component generic_lpddr2phy_wo_pads is
generic (
tech : integer := 0;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- clkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
end;
|
gpl-2.0
|
d12cc215a10e31fed16d37b29b8234be
| 0.538867 | 3.298166 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/ddrphy.vhd
| 1 | 55,139 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy
-- File: ddrphy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddrphy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest: integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- return clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_logic;
signal lddr_cke, lddr_csb: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_logic;
signal lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1 downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits-1 downto 0);
begin
strat2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
cyc3 : if (tech = cyclone3) generate
ddr_phy0 : cycloneiii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) generate
ddr_phy0 : virtex2_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddr_phy0 : virtex4_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew,
phyiconf => phyiconf
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, ck);
clkread <= '0';
dqvalid <= '1';
end generate;
xc3se : if (tech = spartan3e) or (tech = spartan6) generate
ddr_phy0 : spartan3e_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
dqvalid <= '1';
end generate;
-----------------------------------------------------------------------------
-- For technologies where the PHY does not have pads,
-- instantiate ddrphy_wo_pads + pads
-----------------------------------------------------------------------------
seppads: if ddrphy_builtin_pads(tech)=0 generate
phywop: ddrphy_wo_pads
generic map (tech,MHz,rstdelay,dbits,clk_mul,clk_div,
rskew,mobile,abits,nclk,ncs,scantest,phyiconf)
port map (
rst,clk,clkout,clkoutret,clkread,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,lddr_cke,lddr_csb,
lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,
lddr_dq_in,lddr_dq_out,lddr_dq_oen,
addr,ba,dqin,dqout,dm,oen,dqs,dqsoen,rasn,casn,wen,csn,cke,ck,
moben,dqvalid,testen,testrst,scanen,testoen);
pads: ddrpads
generic map (tech,dbits,abits,nclk,ncs,0)
port map (ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,ddr_dm,ddr_dqs,
ddr_ad,ddr_ba,ddr_dq,
open,open,open,open,open,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen);
end generate;
nseppads: if ddrphy_builtin_pads(tech)/=0 generate
lddr_clk <= (others => '0');
lddr_clkb <= (others => '0');
lddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
lddr_cke <= (others => '0');
lddr_csb <= (others => '0');
lddr_web <= '0';
lddr_rasb <= '0';
lddr_casb <= '0';
lddr_dm <= (others => '0');
lddr_dqs_in <= (others => '0');
lddr_dqs_out <= (others => '0');
lddr_dqs_oen <= (others => '0');
lddr_ad <= (others => '0');
lddr_ba <= (others => '0');
lddr_dq_in <= (others => '0');
lddr_dq_out <= (others => '0');
lddr_dq_oen <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddrphy_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
rskew : integer := 0; mobile: integer := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (1 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wo_pads is
begin
gut90: if (tech = ut90) generate
ddr_phy0: ut90nhbd_ddr_phy_wo_pads
generic map (
MHz => MHz, abits => abits, dbits => dbits,
nclk => nclk, ncs => ncs)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen, ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen, rasn, casn, wen, csn, cke, ck,
moben, dqvalid, testen, testrst, scanen, testoen
);
ddr_clk_fb_out <= '0';
clkread <= '0';
end generate;
inf : if (tech = inferred) generate
ddr_phy0 : generic_ddr_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew, mobile => mobile,
abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen, ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, ck, moben);
clkread <= '0';
dqvalid <= '1';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddrpads is
generic (tech: integer := virtex5;
dbits: integer := 16;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1 downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1 downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0) -- ddr data
);
end;
architecture rtl of ddrpads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- DDR clock feedback
fbclkpadgen: if ddrphy_has_fbclk(tech)/=0 generate
fbclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk_fb_out, lddr_clk_fb_out);
fbclk_in_pad : inpad generic map (tech => tech)
port map (ddr_clk_fb, lddr_clk_fb);
end generate;
nfbclkpadgen: if ddrphy_has_fbclk(tech)=0 generate
ddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
end generate;
-- External DDR clock
ddrclocks : for i in 0 to nclk-1 generate
-- DDR_CLK/B
xc456v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddrclk_pad : outpad_ds generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), ddr_clkb(i), lddr_clk(i), vcc);
end generate;
noxc456v : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex6)) generate
-- DDR_CLK
ddrclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), lddr_clk(i));
-- DDR_CLKB
ddrclkb_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clkb(i), lddr_clkb(i));
end generate;
end generate;
-- DDR single-edge control signals
-- RAS
rasn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb, lddr_rasb);
-- CAS
casn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb, lddr_casb);
-- WEN
wen_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web, lddr_web);
-- BA
bagen : for i in 0 to 1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba(i), lddr_ba(i));
end generate;
-- ADDRESS
dagen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad(i), lddr_ad(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to ncs-1 generate
csn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_csb(i), lddr_csb(i));
cke_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_cke(i), lddr_cke(i));
end generate;
-- DQS pads
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (pad => ddr_dqs(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
-- DQM pads
dmgen : for i in 0 to dbits/8-1 generate
ddr_bm_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_dm(i), lddr_dm(i));
end generate;
-- Data bus pads
ddgen : for i in 0 to dbits-1 generate
dq_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (pad => ddr_dq(i), i => lddr_dq_out(i), en => lddr_dq_oen(i),
o => lddr_dq_in(i));
end generate;
-- Second copy of address/data lines
ctrl2gen: if ctrl2en/=0 generate
rasn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb2, lddr_rasb);
casn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb2, lddr_casb);
wen2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web2, lddr_web);
ba2gen : for i in 0 to 1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba2(i), lddr_ba(i));
da2gen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad2(i), lddr_ad(i));
end generate;
end generate;
end generate;
ctrl2ngen: if ctrl2en=0 generate
ddr_rasb2 <= '0';
ddr_casb2 <= '0';
ddr_web2 <= '0';
ddr_ba2 <= (others => '0');
ddr_ad2 <= (others => '0');
end generate;
end;
------------------------------------------------------------------
-- DDR2 PHY with tech mapping ------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr2pads is
generic (tech: integer := virtex5;
dbits: integer := 16;
eightbanks: integer := 0;
dqsse: integer range 0 to 1 := 0;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of ddr2pads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- DDR clock feedback
fbclkpadgen: if ddr2phy_has_fbclk(tech)/=0 generate
fbclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk_fb_out, lddr_clk_fb_out);
fbclk_in_pad : inpad generic map (tech => tech)
port map (ddr_clk_fb, lddr_clk_fb);
end generate;
nfbclkpadgen: if ddr2phy_has_fbclk(tech)=0 generate
ddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
end generate;
-- External DDR clock
ddrclocks : for i in 0 to nclk-1 generate
-- DDR_CLK/B
xc456v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = spartan6)
or (tech = virtex7) or (tech = kintex7) or (tech = artix7) or (tech = zynq7000) generate
ddrclk_pad : outpad_ds generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), ddr_clkb(i), lddr_clk(i), vcc);
end generate;
noxc456v : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = spartan6)
or (tech = virtex7) or (tech = kintex7) or (tech = artix7) or (tech = zynq7000)) generate
-- DDR_CLK
ddrclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), lddr_clk(i));
-- DDR_CLKB
ddrclkb_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clkb(i), lddr_clkb(i));
end generate;
end generate;
-- DDR single-edge control signals
-- RAS
rasn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb, lddr_rasb);
-- CAS
casn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb, lddr_casb);
-- WEN
wen_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web, lddr_web);
-- BA
bagen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba(i), lddr_ba(i));
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_odt(i), lddr_odt(i));
end generate;
-- ADDRESS
dagen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad(i), lddr_ad(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to ncs-1 generate
csn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_csb(i), lddr_csb(i));
cke_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_cke(i), lddr_cke(i));
end generate;
-- DQS pads
dqsse0 : if dqsse = 0 generate
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad_ds generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
end generate;
dqsse1 : if dqsse = 1 generate
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (pad => ddr_dqs(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
end generate;
-- DQM pads
dmgen : for i in 0 to dbits/8-1 generate
ddr_bm_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_dm(i), lddr_dm(i));
end generate;
-- Data bus pads
ddgen : for i in 0 to dbits-1 generate
dq_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (pad => ddr_dq(i), i => lddr_dq_out(i), en => lddr_dq_oen(i),
o => lddr_dq_in(i));
end generate;
-- Second copy of address/data lines
ctrl2gen: if ctrl2en/=0 generate
rasn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb2, lddr_rasb);
casn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb2, lddr_casb);
wen2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web2, lddr_web);
ba2gen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba2(i), lddr_ba(i));
da2gen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad2(i), lddr_ad(i));
end generate;
end generate;
end generate;
ctrl2ngen: if ctrl2en=0 generate
ddr_rasb2 <= '0';
ddr_casb2 <= '0';
ddr_web2 <= '0';
ddr_ba2 <= (others => '0');
ddr_ad2 <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.n2x_padcontrol_none;
-- With built-in pads
entity ddr2phy is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
ctrl2en: integer := 0;
resync: integer := 0; custombits: integer := 8; extraio: integer := 0;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_logic;
signal lddr_cke, lddr_csb: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_logic;
signal lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_dqsn_in,lddr_dqsn_out,lddr_dqsn_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1+eightbanks downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits-1 downto 0);
signal lddr_odt: std_logic_vector(ncs-1 downto 0);
signal customdin_exp: std_logic_vector(132 downto 0);
begin
customdin_exp(custombits-1 downto 0) <= customdin;
customdin_exp(customdin_exp'high downto custombits) <= (others => '0');
-- For technologies without PHY-specific registers
nreggen: if ddr2phy_has_reg(tech)=0 and ddr2phy_builtin_pads(tech)/=0 generate
regrdata <= x"0000000000000000";
end generate;
ncustgen: if ddr2phy_has_custom(tech)=0 and ddr2phy_builtin_pads(tech)/=0 generate
customdout <= (others => '0');
end generate;
stra2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock, ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
dqin_valid <= '1';
end generate;
stra3 : if (tech = stratix3) generate
ddr_phy0 : stratixiii_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk,
tech => tech, rskew => rskew, eightbanks => eightbanks
)
port map (
rst, clk, clkref, clkout, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_pll, cal_rst, odt, oct);
dqin_valid <= '1';
end generate;
sp3a : if (tech = spartan3) generate
ddr_phy0 : spartan3a_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, tech => tech, rskew => rskew,
eightbanks => eightbanks)
port map ( rst, clk, clkout, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_pll, odt);
dqin_valid <= '1';
end generate;
nextreme : if (tech = easic90) generate
ddr_phy0 : easic90_ddr2_phy
generic map (
tech => tech,
MHz => MHz,
clk_mul => clk_mul,
clk_div => clk_div,
dbits => dbits,
rstdelay => rstdelay,
eightbanks => eightbanks)
port map (
rst, clk, clkout, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, odt, '1');
dqin_valid <= '1';
end generate;
nextreme2 : if (tech = easic45) generate
-- This requires dbits/8 extra bidir I/O that are suppliedd on the ddr_dqs port
ddr_phy0 : n2x_ddr2_phy
generic map (
MHz => MHz, rstdelay => rstdelay,
dbits => dbits, clk_mul => clk_mul, clk_div => clk_div, norefclk => norefclk,
eightbanks => eightbanks, dqsse => dqsse, abits => abits,
nclk => nclk, ncs => ncs, ctrl2en => ctrl2en)
port map (
rst => rst, clk => clk, clk270d => clkref,
clkout => clkout, clkoutret => clkoutret, lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_cke => ddr_cke,
ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs(dbits/8-1 downto 0), ddr_dqsn => ddr_dqsn, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt, rden_pad => ddr_dqs(dbits/4-1 downto dbits/8),
addr => addr, ba => ba, dqin => dqin, dqout => dqout, dm => dm,
noen => noen,
rasn => rasn, casn => casn, wen => wen, csn => csn, cke => cke,
odt => odt, read_pend => read_pend, dqin_valid => dqin_valid,
regwdata => regwdata, regwrite => regwrite, regrdata => regrdata,
ddr_web2 => ddr_web2, ddr_rasb2 => ddr_rasb2, ddr_casb2 => ddr_casb2,
ddr_ad2 => ddr_ad2, ddr_ba2 => ddr_ba2,
dq_control => customdin_exp(73 downto 56),
dqs_control => customdin_exp(55 downto 38),
ck_control => customdin_exp(37 downto 20),
cmd_control => customdin_exp(19 downto 2),
compen => customdin_exp(0),
compupd => customdin_exp(1)
);
ddr_clk_fb_out <= '0';
customdout <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- For technologies where the PHY does not have pads,
-- instantiate ddr2phy_wo_pads + pads
-----------------------------------------------------------------------------
seppads: if ddr2phy_builtin_pads(tech)=0 generate
phywop: ddr2phy_wo_pads
generic map (tech,MHz,rstdelay,dbits,clk_mul,clk_div,
ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7,
ddelayb8,ddelayb9,ddelayb10,ddelayb11,
numidelctrl,norefclk,rskew,eightbanks,dqsse,abits,nclk,ncs,
resync,custombits,scantest)
port map (
rst,clk,clkref,clkout,clkoutret,clkresync,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,lddr_cke,lddr_csb,
lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,
lddr_dq_in,lddr_dq_out,lddr_dq_oen,lddr_odt,
addr,ba,dqin,dqout,dm,oen,noen,dqs,dqsoen,rasn,casn,wen,csn,cke,
cal_en,cal_inc,cal_pll,cal_rst,odt,oct,
read_pend,regwdata,regwrite,regrdata,dqin_valid,customclk,customdin,customdout,
testen,testrst,scanen,testoen);
pads: ddr2pads
generic map (tech,dbits,eightbanks,dqsse,abits,nclk,ncs,ctrl2en)
port map (ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,ddr_dm,ddr_dqs,ddr_dqsn,
ddr_ad,ddr_ba,ddr_dq,ddr_odt,
ddr_web2,ddr_rasb2,ddr_casb2,ddr_ad2,ddr_ba2,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen,lddr_odt);
end generate;
nseppads: if ddr2phy_builtin_pads(tech)/=0 generate
lddr_clk <= (others => '0');
lddr_clkb <= (others => '0');
lddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
lddr_cke <= (others => '0');
lddr_csb <= (others => '0');
lddr_web <= '0';
lddr_rasb <= '0';
lddr_casb <= '0';
lddr_dm <= (others => '0');
lddr_dqs_in <= (others => '0');
lddr_dqs_out <= (others => '0');
lddr_dqs_oen <= (others => '0');
lddr_dqsn_in <= (others => '0');
lddr_dqsn_out <= (others => '0');
lddr_dqsn_oen <= (others => '0');
lddr_ad <= (others => '0');
lddr_ba <= (others => '0');
lddr_dq_in <= (others => '0');
lddr_dq_out <= (others => '0');
lddr_dq_oen <= (others => '0');
lddr_odt <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
-- without pads (typically used for ASIC technologies)
entity ddr2phy_wo_pads is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
resync : integer := 0; custombits: integer := 8; scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wo_pads is
begin
-- For technologies without PHY-specific registers
nreggen: if ddr2phy_has_reg(tech)=0 generate
regrdata <= x"0000000000000000";
end generate;
ncustgen: if ddr2phy_has_custom(tech)=0 generate
customdout <= (others => '0');
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6)
or (tech = artix7) or (tech = kintex7) or (tech = virtex7) or (tech=zynq7000) generate
ddr_phy0 : virtex5_ddr2_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7, ddelayb8 => ddelayb8,
ddelayb9 => ddelayb9, ddelayb10 => ddelayb10, ddelayb11 => ddelayb11,
numidelctrl => numidelctrl, norefclk => norefclk,
tech => tech, eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkref, clkout, clkoutret, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba,
ddr_dq_in, ddr_dq_out, ddr_dq_oen,ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
ddr_clk_fb_out <= '0';
dqin_valid <= '1';
end generate;
sp6 : if (tech = spartan6) generate
ddr_phy0 : spartan6_ddr2_phy_wo_pads
generic map (
MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
tech => tech, rskew => rskew,
eightbanks => eightbanks,
abits => abits, nclk => nclk, ncs => ncs)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
ddr_clkb <= (others => '0');
ddr_clk_fb_out <= '0';
dqin_valid <= '1';
end generate;
inf : if (has_ddr2phy(tech) = 0) generate
ddr_phy0 : generic_ddr2_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew,
eightbanks => eightbanks, abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba,
ddr_dq_in, ddr_dq_out, ddr_dq_oen, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, "111", odt
);
dqin_valid <= '1';
end generate;
end;
-------------------------------------------------------------------------------
-- LPDDR2 phy
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity lpddr2phy_wo_pads is
generic (
tech : integer := virtex5;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- ckkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture tmap of lpddr2phy_wo_pads is
begin
inf: if true generate
phy0: generic_lpddr2phy_wo_pads
generic map (
tech => tech,
dbits => dbits,
nclk => nclk,
ncs => ncs,
clkratio => clkratio,
scantest => scantest)
port map (
rst => rst,
clkin => clkin,
clkin2 => clkin2,
clkout => clkout,
clkoutret => clkoutret,
clkout2 => clkout2,
lock => lock,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_ca => ddr_ca,
ddr_dm => ddr_dm,
ddr_dqs_in => ddr_dqs_in,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ca => ca,
cke => cke,
csn => csn,
dqin => dqin,
dqout => dqout,
dm => dm,
ckstop => ckstop,
boot => boot,
wrpend => wrpend,
rdpend => rdpend,
wrreq => wrreq,
rdvalid => rdvalid,
refcal => refcal,
refcalwu => refcalwu,
refcaldone => refcaldone,
phycmd => phycmd,
phycmden => phycmden,
phycmdin => phycmdin,
phycmdout => phycmdout,
testen => testen,
testrst => testrst,
scanen => scanen,
testoen => testoen);
end generate;
end;
|
gpl-2.0
|
b4c2f1624e4f0a6a87b156141b2d4c87
| 0.55663 | 3.286583 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp601/leon3mp.vhd
| 1 | 24,279 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk27 : in std_ulogic;
clk200_p : in std_ulogic;
clk200_n : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(1 downto 0); -- dm
ddr_dqs : inout std_logic_vector(1 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(1 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(2 downto 0); -- bank address
ddr_dq : inout std_logic_vector(15 downto 0); -- data
ddr_odt : out std_logic;
ddr_rzq : inout std_logic;
ddr_zio : inout std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SPI flash
-- spi_sel_n : inout std_ulogic;
-- spi_clk : out std_ulogic;
-- spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_clk_fb : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 27000; -- CLK input frequency in KHz
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk27_pad : clkpad generic map (tech => padtech) port map (clk27, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8, devid => XILINX_SP601)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
clk200_pad : inpad_ds generic map (tech => padtech, voltage => x25v)
port map (clk200_p, clk200_n, lclk200);
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR2_FREQ/1000, clkmul => 5, clkdiv => 8,
TRFC => CFG_DDR2SP_TRFC,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => 16, eightbanks => 1, odten => 0)
port map ( cgo.clklock, rstn, lclk200, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk <= core_ddr_clk(0);
ddr_clkb <= core_ddr_clkb(0);
ddr_cke <= core_ddr_cke(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp601 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => clk200_n,
clk_mem_p => clk200_p,
test_error => open
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
-- spimctrl0 : spimctrl -- SPI Memory Controller
-- generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
-- ioaddr => 16#002#, iomask => 16#fff#,
-- spliten => CFG_SPLIT, oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--
-- -- MISO is shared with Flash data 0
-- spmi.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spmo.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
-- slvsel0_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, spmo.csn);
-- end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
-- spi1 : spictrl
-- generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
-- fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
-- slvselsz => CFG_SPICTRL_SLVS, odmode => 0)
-- port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
-- spii.spisel <= '1'; -- Master only
-- -- MISO is shared with Flash data 0
-- spii.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spio.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spio.sck);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, slvsel(0));
-- end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, gnd);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, gnd);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan6 SP601 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
gpl-2.0
|
377d499d7426620ffdde18bde7379979
| 0.531818 | 3.670295 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc3s1600e/leon3mp.vhd
| 1 | 23,353 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
reset : in std_ulogic;
-- resoutn : out std_logic;
clk_50mhz : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
-- ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
-- dsuact : out std_ulogic;
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART for serial console I/O
urxd1 : in std_ulogic;
utxd1 : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
spi : out std_ulogic;
led : out std_logic_vector(5 downto 0);
ps2clk : inout std_logic;
ps2data : inout std_logic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic;
vid_g : out std_logic;
vid_b : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal vgao : apbvga_out_type;
signal ldsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1, rxd2 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
rstneg <= not reset; spi <= '1';
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
led(5) <= lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
-- cgo.clklock <= '1';
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= ldsubre;
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd2);
dui.rxd <= rxd2;
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(2) <= not rxd2; led(3) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
byten <= '1'; -- 16-bit flash
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc : ddrspa generic map ( fabtech => spartan3e, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => 2*BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 2*5, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
cgo.clklock, rstn, clk2x, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, open, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (urxd1, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (utxd1, txd1);
led(0) <= not rxd1; led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
-- vga : if CFG_VGA_ENABLE /= 0 generate
-- vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
-- port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
-- video_clock_pad : outpad generic map ( tech => padtech)
-- port map (vid_clock, dac_clk);
-- dac_clk <= not clkm;
-- end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk1 => 0, clk2 => 0, burstlen => 5)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
end generate;
-- blank_pad : outpad generic map (tech => padtech)
-- port map (vid_blankn, vgao.blank);
-- comp_sync_pad : outpad generic map (tech => padtech)
-- port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpad generic map (tech => padtech)
port map (vid_r, vgao.video_out_r(7));
video_out_g_pad : outpad generic map (tech => padtech)
port map (vid_g, vgao.video_out_g(7));
video_out_b_pad : outpad generic map (tech => padtech)
port map (vid_b, vgao.video_out_b(7));
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 31, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent Spartan3E Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
gpl-2.0
|
c11419118322027d312e15702bea865e
| 0.541943 | 3.654045 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/testgrouppolito/pr/async_dprc.vhd
| 1 | 18,012 |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: async_dprc
-- File: async_dprc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc async mode (see the DPR IP-core user manual for operations details).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library techmap;
use techmap.gencomp.all;
entity async_dprc is
generic (
technology : integer := virtex4; -- Target technology
fifo_depth : integer := 9); -- true FIFO depth = 2**fifo_depth
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition);
end async_dprc;
architecture async_dprc_rtl of async_dprc is
type icap_state is (IDLE, START, READ_LENGTH, WRITE_ICAP, WRITE_ICAP_VERIFY, END_CONFIG, ABORT, ICAP_ERROR_LATENCY);
signal pstate, nstate : icap_state;
type ahb_state is (IDLE_AHB, START_AHB, GRANTED, WAIT_WRITE_END, BUS_CNTL_ERROR, FIFO_FULL, ICAP_ERROR);
signal present_state, next_state : ahb_state;
-- fifo types
type ififo_type is record
wen : std_ulogic;
waddress : std_logic_vector(fifo_depth downto 0);
waddress_gray : std_logic_vector(fifo_depth downto 0);
idata : std_logic_vector(31 downto 0);
full : std_ulogic;
end record;
type ofifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(fifo_depth downto 0);
raddress_gray : std_logic_vector(fifo_depth downto 0);
odata : std_logic_vector(31 downto 0);
empty : std_ulogic;
end record;
-- cdc control signals for async_dprc
type cdc_async is record
start : std_ulogic;
stop : std_ulogic;
icap_errn : std_ulogic;
icap_end : std_ulogic;
end record;
signal fifo_in, regfifo_in : ififo_type;
signal fifo_out, regfifo_out : ofifo_type;
signal raddr_sync, waddr_sync : std_logic_vector(fifo_depth downto 0);
signal cdc_ahb, rcdc_ahb, cdc_icap, rcdc_icap : cdc_async;
type regs_ahb is record
c_grant : std_logic_vector(19 downto 0);
c_ready : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
rm_reset : std_logic_vector(31 downto 0);
address : std_logic_vector(31 downto 0);
rst_persist : std_ulogic;
end record;
type regs_icap is record
c_bitstream : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
end record;
signal reg, regin : regs_ahb;
signal regicap, reginicap :regs_icap;
signal rstact : std_ulogic;
begin
-- fixed signals
dmai.Data <= (others => '0');
dmai.Beat <= HINCR;
dmai.Size <= HSIZE32;
dmai.Store <= '0'; --Only read transfer requests
dmai.Reset <= not(rstn);
dmai.Address <= reg.address;
rm_reset <= reg.rm_reset;
icapi.idata <= fifo_out.odata;
fifo_in.idata <= dmao.Data;
fifo_in.wen <= dmao.Ready;
-------------------------------
-- ahb bus clock domain
-------------------------------
ahbcomb: process(raddr_sync, regfifo_in, fifo_in, rcdc_ahb, cdc_ahb, reg, present_state, rstn, rstact, apbregi, dmao)
variable vfifo_in : ififo_type;
variable vcdc_ahb : cdc_async;
variable regv : regs_ahb;
variable raddr_sync_decoded : std_logic_vector(fifo_depth downto 0);
begin
apbcontrol.timer_clear <= '0';
apbcontrol.status_clr <= '0';
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Lock <= '0';
apbcontrol.status_value <= (others=>'0');
apbcontrol.status_en <= '0';
apbcontrol.control_clr <= '0';
apbcontrol.timer_en <= '0';
rstact <= '0';
regv := reg;
vcdc_ahb := rcdc_ahb;
vcdc_ahb.start := '0';
vcdc_ahb.stop := '0';
-- initialize fifo signals
vfifo_in.waddress := regfifo_in.waddress;
vfifo_in.full := '0';
-- fifo full generation
gray_decoder(raddr_sync,fifo_depth,raddr_sync_decoded);
if (vfifo_in.waddress(fifo_depth)=raddr_sync_decoded(fifo_depth) and (vfifo_in.waddress(fifo_depth-1 downto 0)-raddr_sync_decoded(fifo_depth-1 downto 0))>(2**fifo_depth-16)) then
vfifo_in.full := '1';
elsif (vfifo_in.waddress(fifo_depth)/= raddr_sync_decoded(fifo_depth) and (raddr_sync_decoded(fifo_depth-1 downto 0)-vfifo_in.waddress(fifo_depth-1 downto 0))<16) then
vfifo_in.full := '1';
end if;
case present_state is
when IDLE_AHB =>
if (apbregi.control/=X"00000000") then
next_state <= START_AHB;
apbcontrol.timer_clear <= '1'; -- clear timer register
apbcontrol.status_clr <= '1'; -- clear status register
regv.c_grant := apbregi.control(19 downto 0);
regv.c_ready := apbregi.control(19 downto 0);
regv.address := apbregi.address;
vcdc_ahb.start := '1'; -- start icap write controller
else
next_state <= IDLE_AHB;
end if;
when START_AHB =>
if (dmao.Grant and dmao.Ready)='1' then
next_state <= GRANTED;
else
next_state <= START_AHB;
end if;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
vcdc_ahb.start := '1'; -- start icap write controller
when GRANTED =>
if (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, no more requests are needed
next_state <= WAIT_WRITE_END;
elsif (vfifo_in.full='1') then
next_state<=FIFO_FULL;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
when FIFO_FULL =>
if ((regv.c_grant=regv.c_ready) and (vfifo_in.full='0')) then
next_state <= GRANTED;
else
next_state <= FIFO_FULL;
end if;
when WAIT_WRITE_END =>
if (cdc_ahb.icap_end='1') then
next_state <= IDLE_AHB;
regv.rst_persist := '0';
apbcontrol.status_value(3 downto 0) <= "1111";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
else
next_state <= WAIT_WRITE_END;
end if;
when BUS_CNTL_ERROR =>
next_state <= IDLE_AHB;
regv.rst_persist := '1';
apbcontrol.status_value(3 downto 0) <= "0100";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcdc_ahb.stop := '1';
when ICAP_ERROR =>
next_state <= IDLE_AHB;
regv.rst_persist := '1';
apbcontrol.status_value(3 downto 0) <= "1000";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
end case;
if (present_state/=IDLE_AHB) and (cdc_ahb.icap_errn='0') then
next_state <= ICAP_ERROR;
end if;
if (present_state/=IDLE_AHB) then
apbcontrol.timer_en <= '1'; -- Enable timer
rstact <= '1';
if dmao.Ready='1' then
regv.c_ready:=regv.c_ready-1;
end if;
if dmao.Grant='1' then
regv.c_grant:=regv.c_grant-1;
regv.address:=regv.address+4;
end if;
end if;
if (dmao.Fault or dmao.Retry)='1' then
next_state <= BUS_CNTL_ERROR;
vcdc_ahb.stop := '1';
end if;
-- write fifo
if fifo_in.wen = '1' then
vfifo_in.waddress := vfifo_in.waddress +1;
end if;
gray_encoder(vfifo_in.waddress,vfifo_in.waddress_gray);
-- latched fifo write address
fifo_in.waddress <= vfifo_in.waddress;
fifo_in.waddress_gray <= vfifo_in.waddress_gray;
-- update fifo full
fifo_in.full <= vfifo_in.full;
-- reconfigurable modules synchrounous reset generation (active high)
for i in 0 to 31 loop
regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist));
end loop;
-- registers assignment
cdc_ahb.start <= vcdc_ahb.start;
cdc_ahb.stop <= vcdc_ahb.stop;
regin <= regv;
end process;
ahbreg: process(clkm,rstn)
begin
if rstn='0' then
regfifo_in.waddress <= (others =>'0');
regfifo_in.waddress_gray <= (others =>'0');
rcdc_ahb.start <= '0';
rcdc_ahb.stop <= '0';
present_state <= IDLE_AHB;
reg.rm_reset <= (others=>'0');
reg.c_grant <= (others=>'0');
reg.c_ready <= (others=>'0');
reg.c_latency <= (others=>'0');
reg.address <= (others=>'0');
reg.rst_persist <= '0';
elsif rising_edge(clkm) then
regfifo_in <= fifo_in;
rcdc_ahb <= cdc_ahb;
present_state <= next_state;
reg <= regin;
end if;
end process;
-------------------------------
-- synchronization registers
-------------------------------
-- input d is already registered in the source clock domain
syn_gen0: for i in 0 to fifo_depth generate -- fifo addresses
syncreg_inst0: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regfifo_in.waddress_gray(i), q => waddr_sync(i));
syncreg_inst1: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regfifo_out.raddress_gray(i), q => raddr_sync(i));
end generate;
-- CDC control signals
syncreg_inst2: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_errn, q => cdc_ahb.icap_errn);
syncreg_inst3: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_end, q => cdc_ahb.icap_end);
syncreg_inst4: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.start, q => cdc_icap.start);
syncreg_inst5: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.stop, q => cdc_icap.stop);
-------------------------------
-- icap clock domain
-------------------------------
icapcomb: process(waddr_sync, regfifo_out, fifo_out, cdc_icap, pstate, regicap, icapo)
variable vfifo_out : ofifo_type;
variable vcdc_icap : cdc_async;
variable vregicap : regs_icap;
begin
icapi.cen <= '1';
icapi.wen <= '1';
vcdc_icap.icap_end := '0';
vcdc_icap.icap_errn := '1';
vregicap := regicap;
-- initialize fifo signals
vfifo_out.raddress := regfifo_out.raddress;
vfifo_out.empty := '0';
vfifo_out.ren := '0';
-- fifo empty generation
gray_encoder(vfifo_out.raddress,vfifo_out.raddress_gray);
if (vfifo_out.raddress_gray=waddr_sync) then
vfifo_out.empty := '1';
end if;
case pstate is
when IDLE =>
if (cdc_icap.start='1') then
nstate <= START;
else
nstate <= IDLE;
end if;
when START =>
if (fifo_out.empty='0') then
vfifo_out.ren := '1';
nstate <= READ_LENGTH;
else
nstate <= START;
end if;
icapi.wen <= '0';
when READ_LENGTH =>
nstate <= WRITE_ICAP;
vregicap.c_bitstream := fifo_out.odata(19 downto 0);
if (fifo_out.empty='0') then
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
when WRITE_ICAP =>
if (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status
nstate <= WRITE_ICAP_VERIFY;
elsif (vregicap.c_bitstream=0) then
nstate <= ICAP_ERROR_LATENCY;
elsif (fifo_out.empty='0') then
nstate <= WRITE_ICAP;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP;
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when WRITE_ICAP_VERIFY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_bitstream=0) then
nstate <= ICAP_ERROR_LATENCY;
elsif (fifo_out.empty='0') then
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP_VERIFY;
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when END_CONFIG =>
nstate <= IDLE;
vfifo_out.raddress := (others=>'0');
vcdc_icap.icap_end := '1';
when ABORT =>
if (vregicap.c_latency=4) then
nstate <= IDLE;
vregicap.c_latency := (others=>'0');
else
nstate <= ABORT;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.raddress := (others=>'0');
when ICAP_ERROR_LATENCY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_latency=4) then
nstate <= END_CONFIG;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_end := '1';
else
nstate <= ICAP_ERROR_LATENCY;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.wen <= '0';
end case;
if (cdc_icap.stop='1') then
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vfifo_out.ren := '1';
end if;
-- read fifo
if vfifo_out.ren = '1' then
vfifo_out.raddress := vfifo_out.raddress +1;
end if;
if regfifo_out.ren = '1' then
vregicap.c_bitstream := vregicap.c_bitstream -1; -- because fifo introduces 1-cycle latency on output data
end if;
-- latched fifo read address
fifo_out.raddress <= vfifo_out.raddress;
fifo_out.raddress_gray <= vfifo_out.raddress_gray;
-- update fifo empty
fifo_out.empty <= vfifo_out.empty;
cdc_icap.icap_errn <= vcdc_icap.icap_errn;
cdc_icap.icap_end <= vcdc_icap.icap_end;
reginicap <= vregicap;
fifo_out.ren <= vfifo_out.ren;
end process;
icapreg: process(clk100,rstn)
begin
if rstn='0' then
regfifo_out.raddress <= (others =>'0');
regfifo_out.raddress_gray <= (others =>'0');
regfifo_out.ren <= '0';
regicap.c_bitstream <= (others =>'0');
regicap.c_latency <= (others =>'0');
rcdc_icap.start <= '0';
rcdc_icap.stop <= '0';
elsif rising_edge(clk100) then
regfifo_out <= fifo_out;
pstate <= nstate;
regicap <= reginicap;
rcdc_icap <= cdc_icap;
end if;
end process;
ram0 : syncram_2p generic map ( tech => technology, abits => fifo_depth, dbits => 32, sepclk => 1) -- 2**fifo_depth 32-bit data RAM
port map (clk100, fifo_out.ren, fifo_out.raddress(fifo_depth-1 downto 0), fifo_out.odata, clkm, fifo_in.wen, fifo_in.waddress(fifo_depth-1 downto 0), fifo_in.idata);
end async_dprc_rtl;
|
gpl-2.0
|
dba4583c0c1c728f5c19891e1ec9b9ee
| 0.58783 | 3.743142 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/grpci1/pciahbmst.vhd
| 1 | 5,748 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pciahbmst
-- File: pciahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Generic AHB master interface
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
entity pciahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in pci_ahb_dma_in_type;
dmao : out pci_ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of pciahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable kblimit : std_logic; -- 1 kB limit indicator
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq; kblimit := '0';
haddr := dmai.address; hbusreq := dmai.start; hwdata := dmai.wdata;
newaddr := dmai.address(10 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(10 downto 0) + inc;
if (newaddr(10) xor haddr(10)) = '1' then kblimit := '1'; end if;
end if;
-- hburst := HBURST_SINGLE;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
-- hburst := HBURST_INCR;
if (r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr(9 downto 0);
if dmai.busy = '1' then htrans := HTRANS_BUSY;
elsif kblimit = '1' then htrans := HTRANS_IDLE;
else htrans := HTRANS_SEQ; end if;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if rst = '0' then v.retry := '0'; v.active := '0'; end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= ahbdrivedata(dmai.wdata);
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= '0' & dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr(9 downto 0);
dmao.rdata <= ahbreadword(ahbi.hrdata);
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
|
gpl-2.0
|
784975cb6a87e49d9f1aa7f4c823749a
| 0.590466 | 3.574627 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2cmst_gen.vhd
| 1 | 3,423 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cmst_gen
-- File: i2cmst_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Contact: [email protected]
-- Description: Generic I2CMST, see i2cmst.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.i2c.all;
entity i2cmst_gen is
generic (
oepol : integer range 0 to 1 := 0; -- output enable polarity
filter : integer range 2 to 512 := 2; -- filter bit size
dynfilt : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2cmst_gen;
architecture rtl of i2cmst_gen is
-- APB signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
apbi.psel(0) <= psel;
apbi.psel(1 to NAPBSLV-1) <= (others => '0');
apbi.penable <= penable;
apbi.paddr <= paddr;
apbi.pwrite <= pwrite;
apbi.pwdata <= pwdata;
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
prdata <= apbo.prdata;
irq <= apbo.pirq(0);
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2cmst
generic map (pindex => 0, paddr => 0, pmask => 0, pirq => 0,
oepol => oepol, filter => filter, dynfilt => dynfilt)
port map (rstn, clk, apbi, apbo, i2ci, i2co);
end architecture rtl;
|
gpl-2.0
|
82a4c24d4fdc6328b4c01717ae0127a6
| 0.595676 | 3.294514 | false | false | false | false |
rhexsel/cmips
|
cMIPS/vhdl/packageMemory_fpga.vhd
| 1 | 17,515 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
package p_MEMORY is
-- To simplify (and accelerate) the RAM address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address which is at a different power of two than the ROM base.
-- Otherwise, the base must be subtracted from the address on every
-- reference, which means having an adder in the critical path.
-- Not good at all.
-- The address ranges for ROM, RAM and I/O must be distinct in the
-- uppermost 16 bits of the address (bits 31..16).
constant HI_SEL_BITS : integer := 31;
constant LO_SEL_BITS : integer := 16;
-- x_IO_ADDR_RANGE can have only ONE bit set, thus being a power of 2.
-- ACHTUNG: changing that definition may break some of the test programs.
-- begin DO NOT change these names as several scripts depend on them --
-- you may change the values, not names neither formatting --
constant x_INST_BASE_ADDR : reg32 := x"00000000";
constant x_INST_MEM_SZ : reg32 := x"00002000";
constant x_DATA_BASE_ADDR : reg32 := x"00010000";
constant x_DATA_MEM_SZ : reg32 := x"00002000";
constant x_IO_BASE_ADDR : reg32 := x"3c000000";
constant x_IO_MEM_SZ : reg32 := x"00002000";
constant x_IO_ADDR_RANGE : reg32 := x"00000020";
constant x_SDRAM_BASE_ADDR : reg32 := x"04000000";
constant x_SDRAM_MEM_SZ : reg32 := x"02000000";
constant x_EXCEPTION_0000 : reg32 := x"00000130"; -- TLBrefill
constant x_EXCEPTION_0100 : reg32 := x"00000200"; -- CacheError
constant x_EXCEPTION_0180 : reg32 := x"00000280"; -- generalExcpHandler
constant x_EXCEPTION_0200 : reg32 := x"00000400"; -- separInterrHandler
constant x_EXCEPTION_BFC0 : reg32 := x"000004E0"; -- NMI, soft-reset
constant x_ENTRY_POINT : reg32 := x"00000500"; -- main()
-- end DO NOT change these names --
constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR));
constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ));
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR));
constant DATA_MEM_SZ : integer := to_integer(signed(x_DATA_MEM_SZ));
constant SDRAM_BASE_ADDR : integer := to_integer(signed(x_SDRAM_BASE_ADDR));
constant SDRAM_MEM_SZ : integer := to_integer(signed(x_SDRAM_MEM_SZ));
constant IO_BASE_ADDR : integer := to_integer(signed(x_IO_BASE_ADDR));
constant IO_MEM_SZ : integer := to_integer(signed(x_IO_MEM_SZ));
constant IO_ADDR_RANGE : integer := to_integer(signed(x_IO_ADDR_RANGE));
-- maximum number of IO devices, must be a power of two.
constant IO_MAX_NUM_DEVS : integer := 16;
constant IO_ADDR_BITS : integer := log2_ceil(IO_MAX_NUM_DEVS * IO_ADDR_RANGE);
-- I/O addresses are IO_ADDR_RANGE apart
constant IO_PRINT_ADDR : integer := IO_BASE_ADDR;
constant IO_STDOUT_ADDR : integer := IO_BASE_ADDR + 1*IO_ADDR_RANGE;
constant IO_STDIN_ADDR : integer := IO_BASE_ADDR + 2*IO_ADDR_RANGE;
constant IO_READ_ADDR : integer := IO_BASE_ADDR + 3*IO_ADDR_RANGE;
constant IO_WRITE_ADDR : integer := IO_BASE_ADDR + 4*IO_ADDR_RANGE;
constant IO_COUNT_ADDR : integer := IO_BASE_ADDR + 5*IO_ADDR_RANGE;
constant IO_FPU_ADDR : integer := IO_BASE_ADDR + 6*IO_ADDR_RANGE;
constant IO_UART_ADDR : integer := IO_BASE_ADDR + 7*IO_ADDR_RANGE;
constant IO_STATS_ADDR : integer := IO_BASE_ADDR + 8*IO_ADDR_RANGE;
constant IO_DSP7SEG_ADDR : integer := IO_BASE_ADDR + 9*IO_ADDR_RANGE;
constant IO_KEYBD_ADDR : integer := IO_BASE_ADDR + 10*IO_ADDR_RANGE;
constant IO_LCD_ADDR : integer := IO_BASE_ADDR + 11*IO_ADDR_RANGE;
constant IO_SDC_ADDR : integer := IO_BASE_ADDR + 12*IO_ADDR_RANGE;
constant IO_HIGHEST_ADDR : integer :=
IO_BASE_ADDR + (IO_MAX_NUM_DEVS - 1)*IO_ADDR_RANGE;
-- DATA CACHE parameters ================================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that DC_INDEX_BITS >= 6 (64 sets/way)
constant DC_TOTAL_CAPACITY : natural := 2*1024;
constant DC_NUM_WAYS : natural := 1; -- direct mapped
constant DC_VIA_CAPACITY : natural := DC_TOTAL_CAPACITY / DC_NUM_WAYS;
constant DC_BTS_PER_WORD : natural := 32;
constant DC_BYTES_PER_WORD : natural := 4;
constant DC_WORDS_PER_BLOCK : natural := 4;
constant DC_NUM_WORDS : natural := DC_VIA_CAPACITY / DC_BYTES_PER_WORD;
constant DC_NUM_BLOCKS : natural := DC_NUM_WORDS / DC_WORDS_PER_BLOCK;
constant DC_INDEX_BITS : natural := log2_ceil( DC_NUM_BLOCKS );
constant DC_WORD_SEL_BITS : natural := log2_ceil( DC_WORDS_PER_BLOCK );
constant DC_BYTE_SEL_BITS : natural := log2_ceil( DC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant DC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_signed(DC_INDEX_BITS - 6, 3));
constant DC_LINE_SIZE: reg3 :=
std_logic_vector(to_signed(DC_WORD_SEL_BITS + 1, 3));
constant DC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_signed(DC_NUM_WAYS - 1, 3));
-- INSTRUCTION CACHE parameters =========================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that IC_INDEX_BITS >= 6 (64 sets/via)
constant IC_TOTAL_CAPACITY : natural := 1024; -- 2*1024;
constant IC_NUM_WAYS : natural := 1; -- direct mapped
constant IC_VIA_CAPACITY : natural := IC_TOTAL_CAPACITY / IC_NUM_WAYS;
constant IC_BTS_PER_WORD : natural := 32;
constant IC_BYTES_PER_WORD : natural := 4;
constant IC_WORDS_PER_BLOCK : natural := 4;
constant IC_NUM_WORDS : natural := IC_VIA_CAPACITY / IC_BYTES_PER_WORD;
constant IC_NUM_BLOCKS : natural := IC_NUM_WORDS / IC_WORDS_PER_BLOCK;
constant IC_INDEX_BITS : natural := log2_ceil( IC_NUM_BLOCKS );
constant IC_WORD_SEL_BITS : natural := log2_ceil( IC_WORDS_PER_BLOCK );
constant IC_BYTE_SEL_BITS : natural := log2_ceil( IC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant IC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_signed(IC_INDEX_BITS - 6, 3));
constant IC_LINE_SIZE: reg3 :=
std_logic_vector(to_signed(IC_WORD_SEL_BITS + 1, 3));
constant IC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_signed(IC_NUM_WAYS - 1, 3));
-- constants to access the cache statistics counters
constant dcache_Stats_ref : reg3 := "000";
constant dcache_Stats_rdhit : reg3 := "001";
constant dcache_Stats_wrhit : reg3 := "010";
constant dcache_Stats_flush : reg3 := "011";
constant icache_Stats_ref : reg3 := "100";
constant icache_Stats_hit : reg3 := "101";
-- MMU parameters ========================================================
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant MMU_CAPACITY : natural := 8;
constant MMU_CAPACITY_BITS : natural := log2_ceil( MMU_CAPACITY );
constant MMU_SIZE: reg6 :=
std_logic_vector(to_signed( (MMU_CAPACITY-1), 6) );
constant MMU_WIRED_INIT : reg32 := x"00000000";
constant VABITS : natural := 32;
constant PABITS : natural := 32;
constant PAGE_SZ : natural := 4096; -- 4k pages
constant PAGE_SZ_BITS : natural := log2_ceil( PAGE_SZ );
constant PPN_BITS : natural := PABITS - PAGE_SZ_BITS;
constant VA_HI_BIT : natural := 31; -- VAaddr in EntryHi 31..PG_size
constant VA_LO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant ASID_HI_BIT : natural := 7; -- ASID in EntryHi 7..0
constant ASID_LO_BIT : natural := 0;
constant EHI_ASIDLO_BIT : natural := 0;
constant EHI_ASIDHI_BIT : natural := 7;
constant EHI_G_BIT : natural := 8;
constant EHI_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant EHI_AHI_BIT : natural := 31;
constant EHI_ZEROS : std_logic_vector(PAGE_SZ_BITS-EHI_G_BIT-1 downto 0) := (others => '0');
constant TAG_ASIDLO_BIT : natural := 0;
constant TAG_ASIDHI_BIT : natural := 7;
constant TAG_G_BIT : natural := 8;
constant TAG_Z_BIT : natural := 9;
constant TAG_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant TAG_AHI_BIT : natural := 31;
constant ELO_G_BIT : natural := 0;
constant ELO_V_BIT : natural := 1;
constant ELO_D_BIT : natural := 2;
constant ELO_CLO_BIT : natural := 3;
constant ELO_CHI_BIT : natural := 5;
constant ELO_ALO_BIT : natural := 6;
constant ELO_AHI_BIT : natural := ELO_ALO_BIT + PPN_BITS - 1;
constant DAT_G_BIT : natural := 0;
constant DAT_V_BIT : natural := 1;
constant DAT_D_BIT : natural := 2;
constant DAT_CLO_BIT : natural := 3;
constant DAT_CHI_BIT : natural := 5;
constant DAT_ALO_BIT : natural := 6;
constant DAT_AHI_BIT : natural := DAT_ALO_BIT + PPN_BITS - 1;
constant DAT_REG_BITS : natural := DAT_ALO_BIT + PPN_BITS;
constant ContextPTE_init : reg9 := b"000000000";
constant mmu_PageMask : reg32 := x"00001800"; -- pg 68, 4k pages only
subtype mmu_dat_reg is std_logic_vector (DAT_AHI_BIT downto 0);
subtype MMU_idx_bits is std_logic_vector(MMU_CAPACITY_BITS-1 downto 0);
constant MMU_idx_0s : std_logic_vector(30 downto MMU_CAPACITY_BITS) :=
(others => '0');
constant MMU_IDX_BIT : natural := 31; -- probe hit=1, miss=0
-- VA tags map a pair of PHY pages, thus VAddr is 1 bit less than (VABITS-1..PAGE_SZ_BITS)
constant tag_zeros : std_logic_vector(PAGE_SZ_BITS downto 0) := (others => '0');
constant tag_ones : std_logic_vector(VABITS-1 downto PAGE_SZ_BITS+1) := (others => '1');
constant tag_mask : reg32 := tag_ones & tag_zeros;
constant tag_g : reg32 := x"00000100";
-- physical addresses for 8 ROM pages
constant x_ROM_PPN_0 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_ROM_PPN_1 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_ROM_PPN_2 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_ROM_PPN_3 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_ROM_PPN_4 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_ROM_PPN_5 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_ROM_PPN_6 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_ROM_PPN_7 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_ROM0 : reg32 := (x_ROM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM0 : mmu_dat_reg :=
x_ROM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM1 : mmu_dat_reg :=
x_ROM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM2 : reg32 := (x_ROM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM2 : mmu_dat_reg :=
x_ROM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM3 : mmu_dat_reg :=
x_ROM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM4 : reg32 := (x_ROM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM4 : mmu_dat_reg :=
x_ROM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM5 : mmu_dat_reg :=
x_ROM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM6 : reg32 := (x_ROM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM6 : mmu_dat_reg :=
x_ROM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM7 : mmu_dat_reg :=
x_ROM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 RAM pages
constant x_RAM_PPN_0 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_RAM_PPN_1 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_RAM_PPN_2 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_RAM_PPN_3 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_RAM_PPN_4 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_RAM_PPN_5 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_RAM_PPN_6 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_RAM_PPN_7 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_RAM0 : reg32 := (x_RAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM0 : mmu_dat_reg :=
x_RAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM1 : mmu_dat_reg :=
x_RAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM2 : reg32 := (x_RAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM2 : mmu_dat_reg :=
x_RAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM3 : mmu_dat_reg :=
x_RAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM4 : reg32 := (x_RAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM4 : mmu_dat_reg :=
x_RAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM5 : mmu_dat_reg :=
x_RAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM6 : reg32 := (x_RAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM6 : mmu_dat_reg :=
x_RAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM7 : mmu_dat_reg :=
x_RAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 2 pages reserved for I/O devices
constant x_IO_PPN_0 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_IO_PPN_1 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 1*PAGE_SZ, 32));
constant MMU_ini_tag_IO : reg32 := (x_IO_BASE_ADDR and tag_mask) or tag_g;
constant MMU_ini_dat_IO0 : mmu_dat_reg :=
x_IO_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_IO1 : mmu_dat_reg :=
x_IO_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 SDRAM pages
constant x_SDRAM_PPN_0 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_SDRAM_PPN_1 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_SDRAM_PPN_2 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_SDRAM_PPN_3 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_SDRAM_PPN_4 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_SDRAM_PPN_5 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_SDRAM_PPN_6 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_SDRAM_PPN_7 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_SDR0 : reg32 := (x_SDRAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR0 : mmu_dat_reg :=
x_SDRAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR1 : mmu_dat_reg :=
x_SDRAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR2 : reg32 := (x_SDRAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR2 : mmu_dat_reg :=
x_SDRAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR3 : mmu_dat_reg :=
x_SDRAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR4 : reg32 := (x_SDRAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR4 : mmu_dat_reg :=
x_SDRAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR5 : mmu_dat_reg :=
x_SDRAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR6 : reg32 := (x_SDRAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR6 : mmu_dat_reg :=
x_SDRAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR7 : mmu_dat_reg :=
x_SDRAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
end p_MEMORY;
-- package body p_MEMORY is
-- end p_MEMORY;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
eb7d5548e2d90e1859db869703a88ea5
| 0.641051 | 2.955121 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/inferred/sim_pll.vhd
| 1 | 6,490 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: sim_pll
-- File: sim_pll.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulated PLL with input frequency checking
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000;
-- Lock tolerance in ps
locktol: integer := 2
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end;
architecture sim of sim_pll is
signal clkout1,clkout2,clkout3,clkout4: std_logic;
signal tp: time := 1 ns;
signal timeset: boolean := false;
signal fb: std_ulogic;
signal comp: time := 0 ns;
signal llock: std_logic;
begin
o1 <= transport clkout1 after tp + (tp*clkdiv1*(clkphase1 mod 360)) / (clkmul*360);
o2 <= transport clkout2 after tp + (tp*clkdiv2*(clkphase2 mod 360)) / (clkmul*360);
o3 <= transport clkout3 after tp + (tp*clkdiv3*(clkphase3 mod 360)) / (clkmul*360);
o4 <= transport clkout4 after tp + (tp*clkdiv4*(clkphase4 mod 360)) / (clkmul*360);
lock <= llock after tp*20; -- 20 cycle inertia on lock signal
freqmeas: process(i)
variable ts,te: time;
variable mf: integer;
variable warned: boolean := false;
variable first: boolean := true;
begin
if rising_edge(i) and (now /= (0 ps)) then
ts := te;
te := now;
if first then
first := false;
else
mf := (1 ms) / (te-ts);
assert (mf >= minfreq and mf <= maxfreq) or warned or rst='0' or llock/='1'
report "Input frequency out of range, " &
"measured: " & tost(mf) & ", min:" & tost(minfreq) & ", max:" & tost(maxfreq)
severity warning;
if (mf < minfreq or mf > maxfreq) and rst/='0' and llock='1' then warned := true; end if;
if llock='0' or te-ts-tp > locktol*(1 ps) or te-ts-tp < -locktol*(1 ps) then
tp <= te-ts;
timeset <= true;
end if;
end if;
end if;
end process;
genclk: process
variable divcount1,divcount2,divcount3,divcount4: integer;
variable compen: boolean;
variable t: time;
variable compps: integer;
begin
compen := false;
clkout1 <= '0';
clkout2 <= '0';
clkout3 <= '0';
clkout4 <= '0';
if not timeset or rst='0' then
wait until timeset and rst/='0';
end if;
divcount1 := 0;
divcount2 := 0;
divcount3 := 0;
divcount4 := 0;
fb <= '1';
clkout1 <= '1';
clkout2 <= '1';
clkout3 <= '1';
clkout4 <= '1';
oloop: loop
for x in 0 to 2*clkmul-1 loop
if x=0 then fb <= '1'; end if;
if x=clkmul then fb <= '0'; end if;
t := tp/(2*clkmul);
if compen and comp /= (0 ns) then
-- Handle compensation below resolution limit (1 ps assumed)
if comp < 2*clkmul*(1 ps) and comp > -2*clkmul*(1 ps) then
compps := abs(comp / (1 ps));
if x > 0 and x <= compps then
if comp > 0 ps then
t := t + 1 ps;
else
t := t - 1 ps;
end if;
end if;
else
t:=t+comp/(2*clkmul);
end if;
end if;
if t > (0 ns) then
wait on rst for t;
else
wait for 1 ns;
end if;
exit oloop when rst='0';
divcount1 := divcount1+1;
if divcount1 >= clkdiv1 then
clkout1 <= not clkout1;
divcount1 := 0;
end if;
divcount2 := divcount2+1;
if divcount2 >= clkdiv2 then
clkout2 <= not clkout2;
divcount2 := 0;
end if;
divcount3 := divcount3+1;
if divcount3 >= clkdiv3 then
clkout3 <= not clkout3;
divcount3 := 0;
end if;
divcount4 := divcount4+1;
if divcount4 >= clkdiv4 then
clkout4 <= not clkout4;
divcount4 := 0;
end if;
end loop;
compen := true;
end loop oloop;
end process;
fbchk: process(fb,i)
variable last_i,prev_i: time;
variable last_fb,prev_fb: time;
variable vlock: std_logic := '0';
begin
if falling_edge(i) then
prev_i := last_i;
last_i := now;
end if;
if falling_edge(fb) then
-- Update phase compensation
if last_i < last_fb+tp/2 then
comp <= (last_i - last_fb);
else
comp <= last_i - now;
end if;
prev_fb := last_fb;
last_fb := now;
end if;
if (last_i<=(last_fb+locktol*(1 ps)) and last_i>=(last_fb-locktol*(1 ps)) and
prev_i<=(prev_fb+locktol*(1 ps)) and prev_i>=(prev_fb-locktol*(1 ps))) then
vlock := '1';
end if;
if prev_fb > last_i+locktol*(1 ps) or prev_i>last_fb+locktol*(1 ps) then
vlock := '0';
end if;
llock <= vlock;
end process;
end;
|
gpl-2.0
|
6da1f8095568a1c5279246d39346f235
| 0.542065 | 3.689596 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmuiface.vhd
| 1 | 8,046 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmuiface
-- File: mmuiface.vhd
-- Author: Konrad Eisele, Jiri Gaisler - Gaisler Research
-- Description: MMU interface types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
library techmap;
use techmap.gencomp.all;
package mmuiface is
type mmutlbcam_in_type is record
mmctrl : mmctrl_type1;
tagin : tlbcam_tfp;
tagwrite : tlbcam_reg;
trans_op : std_logic;
flush_op : std_logic;
write_op : std_logic;
wb_op : std_logic;
mmuen : std_logic;
mset : std_logic;
end record;
type mmutlbcami_a is array (natural range <>) of mmutlbcam_in_type;
type mmutlbcam_out_type is record
pteout : std_logic_vector(31 downto 0);
LVL : std_logic_vector(1 downto 0); -- level in pth
hit : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0); -- for diagnostic access
valid : std_logic; -- for diagnostic access
vaddr : std_logic_vector(31 downto 0); -- for diagnostic access
NEEDSYNC : std_logic;
WBNEEDSYNC : std_logic;
end record;
type mmutlbcamo_a is array (natural range <>) of mmutlbcam_out_type;
-- mmu i/o
type mmuidc_data_in_type is record
data : std_logic_vector(31 downto 0);
su : std_logic;
read : std_logic;
isid : mmu_idcache;
wb_data : std_logic_vector(31 downto 0);
end record;
type mmuidc_data_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
cache : std_logic;
accexc : std_logic;
end record;
constant mmuidco_zero : mmuidc_data_out_type := ('0', zero32, '0', '0');
type mmudc_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
-- dcache extra signals
flush_op : std_logic;
diag_op : std_logic;
wb_op : std_logic;
fsread : std_logic;
mmctrl1 : mmctrl_type1;
end record;
type mmudc_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
-- dcache extra signals
mmctrl2 : mmctrl_type2;
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
tlbmiss : std_logic;
end record;
type mmuic_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
end record;
type mmuic_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
tlbmiss : std_logic;
end record;
constant mmudco_zero : mmudc_out_type := ('0', mmuidco_zero,
mmctrl2_zero, mmuidco_zero, '0');
constant mmuico_zero : mmuic_out_type := ('0', mmuidco_zero, '0');
--#lrue i/o
type mmulrue_in_type is record
touch : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
clear : std_logic;
flush : std_logic;
left : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromleft : std_logic;
right : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromright : std_logic;
end record;
type mmulruei_a is array (natural range <>) of mmulrue_in_type;
type mmulrue_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
movetop : std_logic;
end record;
constant mmulrue_out_none : mmulrue_out_type := (zero32(M_ENT_MAX_LOG-1 downto 0), '0');
type mmulrueo_a is array (natural range <>) of mmulrue_out_type;
--#lru i/o
type mmulru_in_type is record
touch : std_logic;
touchmin : std_logic;
flush : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
mmctrl1 : mmctrl_type1;
end record;
type mmulru_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
end record;
--#mmu: tw i/o
type memory_mm_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
lock : std_logic;
end record;
constant mci_zero : memory_mm_in_type := (X"00000000", X"00000000",
"00", '0', '0', '0', '0');
type memory_mm_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
cache : std_logic; -- cacheable data
end record;
type mmutw_in_type is record
walk_op_ur : std_logic;
areq_ur : std_logic;
tlbmiss : std_logic;
data : std_logic_vector(31 downto 0);
adata : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
end record;
type mmutwi_a is array (natural range <>) of mmutw_in_type;
type mmutw_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
lvl : std_logic_vector(1 downto 0);
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
end record;
type mmutwo_a is array (natural range <>) of mmutw_out_type;
-- mmu tlb i/o
type mmutlb_in_type is record
flush_op : std_logic;
wb_op : std_logic;
trans_op : std_logic;
transdata : mmuidc_data_in_type;
s2valid : std_logic;
mmctrl1 : mmctrl_type1;
end record;
type mmutlbi_a is array (natural range <>) of mmutlb_in_type;
type mmutlbfault_out_type is record
fault_pro : std_logic;
fault_pri : std_logic;
fault_access : std_logic;
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
fault_su : std_logic;
fault_read : std_logic;
fault_isid : mmu_idcache;
fault_addr : std_logic_vector(31 downto 0);
end record;
constant mmutlbfault_out_zero : mmutlbfault_out_type := (
fault_pro => '0',
fault_pri => '0',
fault_access => '0',
fault_mexc => '0',
fault_trans => '0',
fault_inv => '0',
fault_lvl => (others => '0'),
fault_su => '0',
fault_read => '0',
fault_isid => id_icache,
fault_addr => (others => '0'));
type mmutlb_out_type is record
transdata : mmuidc_data_out_type;
fault : mmutlbfault_out_type;
nexttrans : std_logic;
s1finished : std_logic;
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
end record;
type mmutlbo_a is array (natural range <>) of mmutlb_out_type;
end;
|
gpl-2.0
|
d6c38e01ac1d4407f7490331a894321a
| 0.587 | 3.407878 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys4/config.vhd
| 1 | 7,877 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
gpl-2.0
|
194ec848559e43a104079c2f8bfe4b6f
| 0.653929 | 3.573956 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-de2-ep2c35/mypackage.vhd
| 3 | 1,630 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
--use grlib.devices.all;
--use grlib.stdlib.all;
--library techmap;
--use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
package mypackage is
type lcd_out_type is record
rs : std_ulogic;
rw : std_ulogic;
e : std_ulogic;
db : std_logic_vector(7 downto 0);
db_oe : std_ulogic;
end record;
type lcd_in_type is record
db : std_logic_vector(7 downto 0);
end record;
component sdctrl16
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 16;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component apblcd
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer range 0 to 1 := 0;
tas : integer range 0 to 15 := 1;
epw : integer range 0 to 127 := 12
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
lcdo : out lcd_out_type;
lcdi : in lcd_in_type
);
end component;
end;
|
gpl-2.0
|
ced261dbeb49501b2391fae41bf2bcbd
| 0.563804 | 3.165049 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp601/config.vhd
| 1 | 7,885 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (18);
constant CFG_CLKDIV : integer := (9);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
7e40b4b7ee7310c796401a999b1b0b42
| 0.65428 | 3.577586 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica06_SumadorRestador8Bits/topadder00txt.vhd
| 1 | 4,570 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packageadder00.all;
use packagefa00.all;
use ha00.all;
entity topadder00 is
port(
SL: in std_logic ;
Ai: in std_logic_vector ( 7 downto 0 );
Bi: in std_logic_vector ( 7 downto 0 );
LED: out std_logic ;
So: out std_logic_vector ( 7 downto 0 ) );
attribute loc: string;
attribute loc of SL: signal is "p103";
attribute loc of Ai: signal is "p125, p124, p123, p122, p121, p120, p117, p110";
attribute loc of Bi: signal is "p116, p115, p114, p113, p112, p111, p105, p104";
attribute loc of So: signal is "p4, p5, p6, p7, p8, p9, p11, p12";
attribute loc of LED: signal is "p24";
end;
architecture topadder0 of topadder00 is
signal SB, CS, SA: std_logic_vector(7 downto 0);
signal SYnx: std_logic;
begin
UA00: xor00 port map(Ax => SL,
Bx => Bi(0),
Yx => SB(0));
UA01: xor00 port map(Ax => SL,
Bx => Bi(1),
Yx => SB(1));
UA02: xor00 port map(Ax => SL,
Bx => Bi(2),
Yx => SB(2));
UA03: xor00 port map(Ax => SL,
Bx => Bi(3),
Yx => SB(3));
UA04: xor00 port map(Ax => SL,
Bx => Bi(4),
Yx => SB(4));
UA05: xor00 port map(Ax => SL,
Bx => Bi(5),
Yx => SB(5));
UA06: xor00 port map(Ax => SL,
Bx => Bi(6),
Yx => SB(6));
UA07: xor00 port map(Ax => SL,
Bx => Bi(7),
Yx => SB(7));
UA08: topfa00 port map(C00 => SL,
A00 => Ai(0),
B00 => SB(0),
C01 => CS(0),
S00 => SA(0));
UA09: topfa00 port map(C00 => CS(0),
A00 => Ai(1),
B00 => SB(1),
C01 => CS(1),
S00 => SA(1));
UA10: topfa00 port map(C00 => CS(1),
A00 => Ai(2),
B00 => SB(2),
C01 => CS(2),
S00 => SA(2));
UA11: topfa00 port map(C00 => CS(2),
A00 => Ai(3),
B00 => SB(3),
C01 => CS(3),
S00 => SA(3));
UA12: topfa00 port map(C00 => CS(3),
A00 => Ai(4),
B00 => SB(4),
C01 => CS(4),
S00 => SA(4));
UA13: topfa00 port map(C00 => CS(4),
A00 => Ai(5),
B00 => SB(5),
C01 => CS(5),
S00 => SA(5));
UA14: topfa00 port map(C00 => CS(5),
A00 => Ai(6),
B00 => SB(6),
C01 => CS(6),
S00 => SA(6));
UA15: topfa00 port map(C00 => CS(6),
A00 => Ai(7),
B00 => SB(7),
C01 => CS(7),
S00 => SA(7));
UA16: and00 port map(Ba => SA(0),
Aa => SYnx,
Ya => So(0));
UA17: and00 port map(Ba => SA(1),
Aa => SYnx,
Ya => So(1));
UA18: and00 port map(Ba => SA(2),
Aa => SYnx,
Ya => So(2));
UA19: and00 port map(Ba => SA(3),
Aa => SYnx,
Ya => So(3));
UA20: and00 port map(Ba => SA(4),
Aa => SYnx,
Ya => So(4));
UA21: and00 port map(Ba => SA(5),
Aa => SYnx,
Ya => So(5));
UA22: and00 port map(Ba => SA(6),
Aa => SYnx,
Ya => So(6));
UA23: and00 port map(Ba => SA(7),
Aa => SYnx,
Ya => So(7));
UA24: nxor00 port map(Anx => CS(7),
Bnx => CS(6),
Ynx => SYnx);
UA25: xor00 port map(Bx => CS(7),
Ax => CS(6),
Yx => LED);
end topadder0;
|
apache-2.0
|
018fedf9f280711ad01f1693c90df607
| 0.336324 | 3.833893 | false | false | false | false |
aortiz49/MIPS-Processor
|
Hardware/MIPS_lib.vhd
| 1 | 4,209 |
library ieee;
use ieee.std_logic_1164.all;
package MIPS_lib is
--ALU CONSTANTS-----------------------------------------------------------------------------
constant F_SUM : std_logic_vector(3 downto 0) := "0010"; -- Add
constant F_SUB : std_logic_vector(3 downto 0) := "0110"; -- Subtract
constant F_AND : std_logic_vector(3 downto 0) := "0000"; -- AND
constant F_OR : std_logic_vector(3 downto 0) := "0001"; -- OR
constant F_NOR : std_logic_vector(3 downto 0) := "1100"; -- NOR
constant F_SLT : std_logic_vector(3 downto 0) := "0111"; -- Set if less than; signed
constant F_SLTU : std_logic_vector(3 downto 0) := "1111"; -- Set if less than; unsigned
constant F_SHFT : std_logic_vector(3 downto 0) := "0011"; -- shift
--------------------------------------------------------------------------------------------
--ALU OP------------------------------------------------------------------------------------
constant ADD : std_logic_vector(2 downto 0) := "000"; -- add
constant BEQ : std_logic_vector(2 downto 0) := "001"; -- sub
constant ANDI : std_logic_vector(2 downto 0) := "010"; -- and
constant ORI : std_logic_vector(2 downto 0) := "011"; -- or
constant LUI : std_logic_vector(2 downto 0) := "101"; -- shift
constant R_TYPE : std_logic_vector(2 downto 0) := "100"; -- R-type (varied)
constant SLTI : std_logic_vector(2 downto 0) := "110"; -- slti
constant SLTIU : std_logic_vector(2 downto 0) := "111"; -- sltiu
--------------------------------------------------------------------------------------------
--ALU FUNCT---------------------------------------------------------------------------------
constant CTRL_ADD : std_logic_vector(5 downto 0) := "100000"; -- add
constant CTRL_ADDU : std_logic_vector(5 downto 0) := "100001"; -- addu
constant CTRL_SUB : std_logic_vector(5 downto 0) := "100010"; -- sub
constant CTRL_AND : std_logic_vector(5 downto 0) := "100100"; -- and
constant CTRL_OR : std_logic_vector(5 downto 0) := "100101"; -- or
constant CTRL_NOR : std_logic_vector(5 downto 0) := "100111"; -- nor
constant CTRL_SLT : std_logic_vector(5 downto 0) := "101010"; -- slt
constant CTRL_SLL : std_logic_vector(5 downto 0) := "000000"; -- sll
constant CTRL_SRL : std_logic_vector(5 downto 0) := "000010"; -- srl
constant CTRL_SLTU : std_logic_vector(5 downto 0) := "101011"; -- sltu
constant CTRL_JR : std_logic_vector(5 downto 0) := "001000"; -- jr
constant CTRL_SUBU : std_logic_vector(5 downto 0) := "100011"; -- sub unsigned
--------------------------------------------------------------------------------------------
--INSTRUCTIONS------------------------------------------------------------------------------
constant OPC_LUI : std_logic_vector(5 downto 0) := "001111"; -- lui
constant OPC_ANDI : std_logic_vector(5 downto 0) := "001100"; -- andi
constant OPC_ORI : std_logic_vector(5 downto 0) := "001101"; -- ori
constant OPC_SLTI : std_logic_vector(5 downto 0) := "001010"; -- slti
constant OPC_SLTIU : std_logic_vector(5 downto 0) := "001011"; -- sltiu
constant OPC_ADDI : std_logic_vector(5 downto 0) := "001000"; -- addi
constant OPC_ADDIU : std_logic_vector(5 downto 0) := "001001"; -- addiu
constant OPC_R : std_logic_vector(5 downto 0) := "000000"; -- r-types
constant OPC_SB : std_logic_vector(5 downto 0) := "101000"; -- sb
constant OPC_SH : std_logic_vector(5 downto 0) := "101001"; -- sh
constant OPC_J : std_logic_vector(5 downto 0) := "000010"; -- j
constant OPC_JAL : std_logic_vector(5 downto 0) := "000011"; -- jal
constant OPC_BEQ : std_logic_vector(5 downto 0) := "000100"; -- beq
constant OPC_BNEQ : std_logic_vector(5 downto 0) := "000101"; -- bneq
constant OPC_SW : std_logic_vector(5 downto 0) := "101011"; -- sw
constant OPC_LW : std_logic_vector(5 downto 0) := "100011"; -- lw
constant OPC_LBU : std_logic_vector(5 downto 0) := "100100"; -- lbu
constant OPC_LHU : std_logic_vector(5 downto 0) := "100101"; -- lbu
END MIPS_lib;
|
mit
|
3a16722e805aadd53570e8d225fbade0
| 0.515799 | 2.743807 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/ahb2axi.vhd
| 3 | 9,719 |
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2axi
-- File: ahb2axi.vhd
-- Author: Jiri Gaisler
--
-- AHB/AXI bridge for Zynq S_AXI_GP0 AXI3 slave
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2axi is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
cidsz : integer := 6;
clensz : integer := 4
);
port(
rstn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
m_axi_araddr : out std_logic_vector ( 31 downto 0 );
m_axi_arburst : out std_logic_vector ( 1 downto 0 );
m_axi_arcache : out std_logic_vector ( 3 downto 0 );
m_axi_arid : out std_logic_vector ( cidsz-1 downto 0 );
m_axi_arlen : out std_logic_vector ( clensz-1 downto 0 );
m_axi_arlock : out std_logic_vector (1 downto 0);
m_axi_arprot : out std_logic_vector ( 2 downto 0 );
m_axi_arqos : out std_logic_vector ( 3 downto 0 );
m_axi_arready : in std_logic;
m_axi_arsize : out std_logic_vector ( 2 downto 0 );
m_axi_arvalid : out std_logic;
m_axi_awaddr : out std_logic_vector ( 31 downto 0 );
m_axi_awburst : out std_logic_vector ( 1 downto 0 );
m_axi_awcache : out std_logic_vector ( 3 downto 0 );
m_axi_awid : out std_logic_vector ( cidsz-1 downto 0 );
m_axi_awlen : out std_logic_vector ( clensz-1 downto 0 );
m_axi_awlock : out std_logic_vector (1 downto 0);
m_axi_awprot : out std_logic_vector ( 2 downto 0 );
m_axi_awqos : out std_logic_vector ( 3 downto 0 );
m_axi_awready : in std_logic;
m_axi_awsize : out std_logic_vector ( 2 downto 0 );
m_axi_awvalid : out std_logic;
m_axi_bid : in std_logic_vector ( cidsz-1 downto 0 );
m_axi_bready : out std_logic;
m_axi_bresp : in std_logic_vector ( 1 downto 0 );
m_axi_bvalid : in std_logic;
m_axi_rdata : in std_logic_vector ( 31 downto 0 );
m_axi_rid : in std_logic_vector ( cidsz-1 downto 0 );
m_axi_rlast : in std_logic;
m_axi_rready : out std_logic;
m_axi_rresp : in std_logic_vector ( 1 downto 0 );
m_axi_rvalid : in std_logic;
m_axi_wdata : out std_logic_vector ( 31 downto 0 );
m_axi_wid : out std_logic_vector ( cidsz-1 downto 0 );
m_axi_wlast : out std_logic;
m_axi_wready : in std_logic;
m_axi_wstrb : out std_logic_vector ( 3 downto 0 );
m_axi_wvalid : out std_logic
);
end ;
architecture rtl of ahb2axi is
type bstate_type is (idle, read1, read2, read3, write1, write2, write3);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
m_axi_arlen : std_logic_vector (clensz-1 downto 0 );
m_axi_rdata : std_logic_vector (31 downto 0 );
m_axi_arvalid : std_logic;
m_axi_awvalid : std_logic;
m_axi_rready : std_logic;
m_axi_wstrb : std_logic_vector (3 downto 0 );
m_axi_bready : std_logic;
m_axi_wvalid : std_logic;
m_axi_wlast : std_logic;
m_axi_bresp : std_logic_vector (1 downto 0 );
m_axi_awaddr : std_logic_vector (31 downto 0 );
end record;
signal r, rin : reg_type;
begin
comb: process( rstn, r, ahbsi, m_axi_arready, m_axi_rlast, m_axi_rvalid,
m_axi_awready, m_axi_wready, m_axi_bvalid, m_axi_bresp, m_axi_rdata )
variable v : reg_type;
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector (3 downto 0 );
begin
v := r;
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.haddr := ahbsi.haddr;
if ahbsi.htrans = "10" then
if v.hburst = "000" then v.m_axi_arlen := (others => '0');
else
v.m_axi_arlen := (others => '0');
v.m_axi_arlen(2 downto 0) := not ahbsi.haddr(4 downto 2);
end if;
end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
case r.hsize(1 downto 0) is
when "00" => wstrb := decode(not r.haddr(1 downto 0));
when "01" =>
if r.haddr(1) = '1' then wstrb := "0011"; else wstrb := "1100"; end if;
when others => wstrb := "1111";
end case;
case r.bstate is
when idle =>
if v.hsel = '1' then
if v.hwrite = '1' then v.bstate := write3; v.hready := '1';
else v.bstate := read1; v.m_axi_arvalid := '1';end if;
end if;
when read1 =>
if m_axi_arready = '1' then
v.m_axi_arvalid := '0'; v.bstate := read2; v.m_axi_rready := '1';
end if;
when read2 =>
v.hready := '0';
if m_axi_rvalid = '1' then
v.m_axi_rdata := m_axi_rdata; v.hready := '1';
end if;
if (r.hready = '1') and (ahbsi.htrans /= "11") then
v.bstate := read3;
if v.hsel = '1' then v.hready := '0'; end if;
end if;
if (m_axi_rlast = '1') and (m_axi_rvalid = '1') then
v.bstate := idle; v.m_axi_rready := '0';
end if;
when read3 =>
if (m_axi_rlast = '1') and (m_axi_rvalid = '1') then
v.bstate := idle; v.m_axi_rready := '0';
end if;
when write1 =>
if m_axi_awready = '1' then
v.m_axi_awvalid := '0'; v.bstate := write2; v.m_axi_wvalid := '1';
v.m_axi_wlast := '1';
end if;
when write2 =>
if m_axi_wready = '1' then
v.m_axi_wlast := '0'; v.bstate := idle;
v.m_axi_wvalid := '0'; v.m_axi_wlast := '0';
end if;
when write3 =>
v.m_axi_awvalid := '1';
v.m_axi_awaddr := "0001" & r.haddr(27 downto 2) & "00";
v.m_axi_wstrb := wstrb; v.hwdata := ahbsi.hwdata;
v.bstate := write1;
end case;
if (m_axi_bvalid = '1') and (r.m_axi_bresp = "00") then v.m_axi_bresp := m_axi_bresp; end if;
readdata := (others => '0');
readdata(1 downto 0) := r.m_axi_bresp;
if rstn = '0' then
v.bstate := idle; v.hready := '1';
v.m_axi_arvalid := '0'; v.m_axi_rready := '0';
v.m_axi_rready := '0'; v.m_axi_wstrb := (others => '0');
v.m_axi_bready := '0'; v.m_axi_wvalid := '0'; v.m_axi_wlast := '0';
v.m_axi_bresp := "00"; v.m_axi_awvalid := '0';
end if;
rin <= v;
apbo.prdata <= readdata;
end process;
m_axi_araddr <= "0001" & r.haddr(27 downto 2) & "00";
m_axi_arburst <= "01";
m_axi_arcache <= "0011";
m_axi_arid <= (others => '0');
m_axi_arlen <= r.m_axi_arlen;
m_axi_arlock <= (others => '0');
m_axi_arprot <= "001";
m_axi_arsize <= "010";
m_axi_arvalid <= r.m_axi_arvalid;
m_axi_rready <= r.m_axi_rready;
m_axi_arqos <= (others => '0');
m_axi_awaddr <= r.m_axi_awaddr;
m_axi_awburst <= "01";
m_axi_awcache <= "0011";
m_axi_awid <= (others => '0');
m_axi_awlen <= (others => '0');
m_axi_awlock <= (others => '0');
m_axi_awprot <= "001";
m_axi_awsize <= "010";
m_axi_awvalid <= r.m_axi_awvalid;
m_axi_awqos <= (others => '0');
m_axi_rready <= r.m_axi_rready;
m_axi_wstrb <= r.m_axi_wstrb;
m_axi_bready <= '1';
m_axi_wvalid <= r.m_axi_wvalid;
m_axi_wlast <= r.m_axi_wlast;
m_axi_wdata <= r.hwdata;
m_axi_wid <= (others => '0');
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.m_axi_rdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
gpl-2.0
|
5deef4bc0ca4c4cc0238a7688a71f063
| 0.552012 | 2.975811 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/not00.vhd
| 1 | 1,278 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity not00 is
port(
clkn: in std_logic ;
codopn: in std_logic_vector ( 3 downto 0 );
inFlagn: in std_logic;
portAn: in std_logic_vector ( 7 downto 0 );
outn: out std_logic_vector ( 7 downto 0 );
outFlagn: out std_logic );
end;
architecture not0 of not00 is
begin
pnot: process(codopn, portAn)
begin
if(codopn = "0011") then
outn <= not portAn;
outFlagn <= '1';
else
outn <= (others => 'Z');
outFlagn <= 'Z';
end if;
end process pnot;
-- pnot: process(clkn, codopn, inFlagn)
-- --variable auxn: bit:='0';
-- begin
-- if (clkn = '1') then
----clkn'event and
-- if (codopn = "0011") then
-- --if (inFlagn = '1') then
-- --if (auxn = '0') then
-- --auxn:= '1';
-- outn <= not(portAn);
-- outFlagn <= '1';
-- --end if;
-- --else
-- --outFlagn <= '0';
-- --end if;
-- else
-- outn <= (others => 'Z');
-- outFlagn <= 'Z';
-- --auxn:='0';
-- end if;
-- end if;
-- end process pnot;
end not0;
|
apache-2.0
|
9b96680dfc829b8f1ebce8312b8b1230
| 0.471831 | 2.85906 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx60/config.vhd
| 1 | 6,315 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 4;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#010a#;
constant CFG_ETH_ENM : integer := 16#020060#;
constant CFG_ETH_ENL : integer := 16#000015#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 0;
constant CFG_DDRSP_INIT : integer := 0;
constant CFG_DDRSP_FREQ : integer := 100;
constant CFG_DDRSP_COL : integer := 9;
constant CFG_DDRSP_SIZE : integer := 8;
constant CFG_DDRSP_RSKEW : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FE0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
aa66c64aed2fcc9f04d2f0622816337e
| 0.644022 | 3.602396 | false | false | false | false |
aortiz49/MIPS-Processor
|
Hardware/reg32.vhd
| 1 | 622 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg32 is
port(
d : in std_logic_vector(31 downto 0);
rst : in std_logic;
en : in std_logic;
clk : in std_logic; -- clock.
q : out std_logic_vector(31 DOWNTO 0) -- output
);
end reg32;
architecture bhv of reg32 is
begin
process(clk,rst)
begin
if rst = '1' then
q <= (others => '0');
elsif (clk = '1' and clk'event) then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end bhv;
|
mit
|
8ed88bad7a43b4a10dbc672dd2440b86
| 0.491961 | 2.990385 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/virtex/memory_virtex.vhd
| 1 | 14,268 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_virtex.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Memory generators for Xilinx Virtex rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB4 block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1;
use unisim.RAMB4_S2;
use unisim.RAMB4_S4;
use unisim.RAMB4_S8;
use unisim.RAMB4_S16;
use unisim.RAMB4_S16_S16;
--pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
library techmap;
use techmap.gencomp.all;
entity virtex_syncram is
generic ( abits : integer := 6; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of virtex_syncram is
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S16_S16
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+32 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0';
dataout <= do(dbits-1 downto 0);
di(dbits-1 downto 0) <= datain; di(dbits+32 downto dbits) <= (others => '0');
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a7 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits <= 32)) generate
r0 : RAMB4_S16_S16
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map ( do(31 downto 16), do(15 downto 0),
xa(7 downto 0), ya(7 downto 0), clk, clk, di(31 downto 16),
di(15 downto 0), enable, enable, gnd, gnd, write, write);
do(dbits+32 downto 32) <= (others => '0');
end generate;
a8 : if (((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits > 32)) or (abits = 8)) generate
x : for i in 0 to ((dbits-1)/16) generate
r : RAMB4_S16 port map ( do (((i+1)*16)-1 downto i*16), xa(7 downto 0),
clk, di (((i+1)*16)-1 downto i*16), enable, gnd, write );
end generate;
do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r : RAMB4_S8 port map ( do (((i+1)*8)-1 downto i*8), xa(8 downto 0),
clk, di (((i+1)*8)-1 downto i*8), enable, gnd, write );
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB4_S4 port map ( do (((i+1)*4)-1 downto i*4), xa(9 downto 0),
clk, di (((i+1)*4)-1 downto i*4), enable, gnd, write );
end generate;
do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB4_S2 port map ( do (((i+1)*2)-1 downto i*2), xa(10 downto 0),
clk, di (((i+1)*2)-1 downto i*2), enable, gnd, write );
end generate;
do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to (dbits-1) generate
r : RAMB4_S1 port map ( do (i downto i), xa(11 downto 0),
clk, di(i downto i), enable, gnd, write );
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a13 : if abits > 12 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1_S1;
use unisim.RAMB4_S2_S2;
use unisim.RAMB4_S4_S4;
use unisim.RAMB4_S8_S8;
use unisim.RAMB4_S16_S16;
--pragma translate_on
entity virtex_syncram_dp is
generic (
abits : integer := 6; dbits : integer := 8
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of virtex_syncram_dp is
component RAMB4_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+16 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+16 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+16 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a8 : if abits <= 8 generate
x : for i in 0 to ((dbits-1)/16) generate
r0 : RAMB4_S16_S16
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16),
addr1(7 downto 0), addr2(7 downto 0), clk1, clk2,
di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r0 : RAMB4_S8_S8
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a10: if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB4_S4_S4
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a11: if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB4_S2_S2
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a12: if abits = 12 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB4_S1_S1
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for virtex_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
gpl-2.0
|
a3a3da5c3348c690cfa0dfbd18c7e755
| 0.600294 | 2.977462 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/umc18/components/umc_simprims.vhd
| 1 | 17,470 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umc_simprims
-- File: umc_simprims.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple UMC 0.18 simulation models
------------------------------------------------------------------------------
-- pragma translate_off
-- input pad
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3V is begin Z <= to_X01(A) after 1 ns; end;
-- input pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3VPU is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPU is begin
Z <= to_X01(A) after 1 ns; --A <= 'H';
end;
-- input pad with pull-down
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3VPD is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPD is begin
Z <= to_X01(A) after 1 ns; --A <= 'L';
end;
-- schmitt input pad
library ieee;
use ieee.std_logic_1164.all;
entity ISTRT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ISTRT3V is begin Z <= to_X01(A) after 1 ns; end;
-- output pads
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V4 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V4 is begin Z <= to_X01(A) after 3 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V12 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V12 is begin Z <= to_X01(A) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V24 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V24 is begin Z <= to_X01(A) after 1 ns; end;
-- tri-state output pads
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR4 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR4 is begin
Z <= to_X01(A) after 3 ns when to_X01(en) = '1' else
'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR12 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR12 is begin
Z <= to_X01(A) after 2 ns when to_X01(en) = '1' else
'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR24 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR24 is begin
Z <= to_X01(A) after 1 ns when to_X01(en) = '1' else
'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
end;
-- bidirectional pads
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V4 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V4 is begin
IO <= to_X01(A) after 3 ns when to_X01(en) = '1' else
'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V12 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V12 is begin
IO <= to_X01(A) after 2 ns when to_X01(en) = '1' else
'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V24 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V24 is begin
IO <= to_X01(A) after 1 ns when to_X01(en) = '1' else
'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Receiver is port( A, AN : in std_logic; Z : out std_logic); end;
architecture struct of LVDS_Receiver is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(A) after 1 ns when to_x01(A xor AN) = '1' else yn after 1 ns;
Z <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Driver is port (A, Vref, HI : in std_logic; Z, ZN : out std_logic ); end;
architecture struct of LVDS_Driver is begin
Z <= A after 1 ns;
ZN <= not A after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Biasmodule is port ( RefR : in std_logic; Vref, HI : out std_logic); end;
architecture struct of LVDS_Biasmodule is begin end;
-- single-port memory
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end;
architecture behav of UMC_SIM_SRAM is
subtype memword is std_logic_vector(dbits-1 downto 0);
type mem_type is array (0 to 2**abits-1) of memword;
signal qint : memword;
begin
m : process(clk)
variable mem : mem_type;
begin
if rising_edge(clk) then
qint <= (others => 'X');
if to_X01(wen) = '0' then mem(conv_integer(a)) := data;
elsif to_X01(wen) = '1' then qint <= mem(conv_integer(a)); end if;
end if;
end process;
q <= qint when to_X01(oen) = '0' else
(others => 'Z') when to_X01(oen) = '1' else (others => 'X');
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_2048wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (11, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_1024wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (10, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_512wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (9, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_256wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (8, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_128wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (7, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_64wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (6, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_32wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (5, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_2048wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (11, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_1024wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (10, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_512wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (9, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_256wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (8, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_128wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (7, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_64wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (6, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_32wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (5, 40) port map (a, data, csn, wen, oen, q, clk);
end;
-- pragma translate_on
|
gpl-2.0
|
c40f0c67a9ca799d50c28f2c4acdec26
| 0.632513 | 2.732249 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/fmf/flash/m25p80.vhd
| 3 | 51,454 |
--------------------------------------------------------------------------------
-- File Name: m25p80.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 G.Gojanovic 05 Jun 27 initial version
--
--------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library: FLASH MEMORY
-- Technology: CMOS
-- Part: M25P80
--
-- Description: 8Mbit Serial Flash memory w/ 40MHz SPI Bus Interface
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE STD.textio.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF; USE FMF.gen_utils.ALL;
USE FMF.conversions.ALL;
-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY m25p80 IS
GENERIC (
-- tipd delays: interconnect path delays
tipd_C : VitalDelayType01 := VitalZeroDelay01;
tipd_D : VitalDelayType01 := VitalZeroDelay01;
tipd_SNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
-- tpd delays
tpd_C_Q : VitalDelayType01 := UnitDelay01;--tV
tpd_SNeg_Q : VitalDelayType01Z := UnitDelay01Z;--tDIS
tpd_HOLDNeg_Q : VitalDelayType01Z := UnitDelay01Z;--tLZ,tHZ
--tsetup values
tsetup_D_C : VitalDelayType := UnitDelay; --tDVCH /
tsetup_SNeg_C : VitalDelayType := UnitDelay; --tSLCH /
tsetup_HOLDNeg_C : VitalDelayType := UnitDelay; --tHHCH /
tsetup_C_HOLDNeg : VitalDelayType := UnitDelay; --tHLCH \
tsetup_WNeg_SNeg : VitalDelayType := UnitDelay; --tWHSL \
--thold values
thold_D_C : VitalDelayType := UnitDelay; --tCHDX /
thold_SNeg_C : VitalDelayType := UnitDelay; --tCHSL /
thold_HOLDNeg_C : VitalDelayType := UnitDelay; --tCHHL /
thold_C_HOLDNeg : VitalDelayType := UnitDelay; --tCHHH \
thold_WNeg_SNeg : VitalDelayType := UnitDelay; --tWPH \
--tpw values: pulse width
tpw_C_posedge : VitalDelayType := UnitDelay; --tCH
tpw_C_negedge : VitalDelayType := UnitDelay; --tCL
tpw_SNeg_posedge : VitalDelayType := UnitDelay; --tSHSL
-- tperiod min (calculated as 1/max freq)
tperiod_C_rd : VitalDelayType := UnitDelay; -- fC=20MHz
tperiod_C_fast_rd : VitalDelayType := UnitDelay; -- fC=25/40MHz
-- tdevice values: values for internal delays
-- Page Program Operation
tdevice_PP : VitalDelayType := 5 ms; --tPP
--Sector Erase Operation
tdevice_SE : VitalDelayType := 3 sec; --tSE
--Bulk Erase Operation
tdevice_BE : VitalDelayType := 20 sec; --tBE
--Write Status Register Operation
tdevice_WR : VitalDelayType := 15 ms; --tW
--Deep Power Down
tdevice_DP : VitalDelayType := 3 us; --tDP
--Release from Deep Power Down ES not read
tdevice_RES1 : VitalDelayType := 3 us; --tRES1
--Release from Deep Power Down ES read
tdevice_RES2 : VitalDelayType := 1.8 us; --tRES2
--VCC (min) to S# Low
tdevice_VSL : VitalDelayType := 10 us; --tVSL
--Time delay to Write instruction
tdevice_PUW : VitalDelayType := 10 ms; --tPUW
-- generic control parameters
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
-- memory file to be loaded
mem_file_name : STRING := "m25p80.mem";
UserPreload : BOOLEAN := FALSE; --TRUE;
DebugInfo : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
-- For FMF SDF technology file usage
TimingModel : STRING := DefaultTimingModel
);
PORT (
C : IN std_ulogic := 'U'; --serial clock input
D : IN std_ulogic := 'U'; --serial data input
SNeg : IN std_ulogic := 'U'; -- chip select input
HOLDNeg : IN std_ulogic := 'U'; -- hold input
WNeg : IN std_ulogic := 'U'; -- write protect input
Q : OUT std_ulogic := 'U' --serial data output
);
ATTRIBUTE VITAL_LEVEL0 of m25p80 : ENTITY IS TRUE;
END m25p80;
-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of m25p80 IS
ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;
CONSTANT PartID : STRING := "m25p80";
CONSTANT MaxData : NATURAL := 16#FF#; --255;
CONSTANT SecSize : NATURAL := 16#FFFF#; --65535
CONSTANT SecNum : NATURAL := 15;
CONSTANT HiAddrBit : NATURAL := 23;
CONSTANT AddrRANGE : NATURAL := 16#FFFFF#;
CONSTANT BYTE : NATURAL := 8;
--Electronic Signature
CONSTANT ES : NATURAL := 16#13#;
-- interconnect path delay signals
SIGNAL C_ipd : std_ulogic := 'U';
SIGNAL D_ipd : std_ulogic := 'U';
SIGNAL SNeg_ipd : std_ulogic := 'U';
SIGNAL HOLDNeg_ipd : std_ulogic := 'U';
SIGNAL WNeg_ipd : std_ulogic := 'U';
--- internal delays
SIGNAL PP_in : std_ulogic := '0';
SIGNAL PP_out : std_ulogic := '0';
SIGNAL PUW_in : std_ulogic := '0';
SIGNAL PUW_out : std_ulogic := '0';
SIGNAL SE_in : std_ulogic := '0';
SIGNAL SE_out : std_ulogic := '0';
SIGNAL BE_in : std_ulogic := '0';
SIGNAL BE_out : std_ulogic := '0';
SIGNAL WR_in : std_ulogic := '0';
SIGNAL WR_out : std_ulogic := '0';
SIGNAL DP_in : std_ulogic := '0';
SIGNAL DP_out : std_ulogic := '0';
SIGNAL RES1_in : std_ulogic := '0';
SIGNAL RES1_out : std_ulogic := '0';
SIGNAL RES2_in : std_ulogic := '0';
SIGNAL RES2_out : std_ulogic := '0';
SIGNAL VSL_in : std_ulogic := '0';
SIGNAL VSL_out : std_ulogic := '0';
BEGIN
---------------------------------------------------------------------------
-- Internal Delays
---------------------------------------------------------------------------
-- Artificial VITAL primitives to incorporate internal delays
PP :VitalBuf(PP_out, PP_in, (tdevice_PP ,UnitDelay));
PUW :VitalBuf(PUW_out, PUW_in, (tdevice_PUW ,UnitDelay));
SE :VitalBuf(SE_out, SE_in, (tdevice_SE ,UnitDelay));
BE :VitalBuf(BE_out, BE_in, (tdevice_BE ,UnitDelay));
WR :VitalBuf(WR_out, WR_in, (tdevice_WR ,UnitDelay));
DP :VitalBuf(DP_out, DP_in, (tdevice_DP ,UnitDelay));
RES1 :VitalBuf(RES1_out, RES1_in, (tdevice_RES1 ,UnitDelay));
RES2 :VitalBuf(RES2_out, RES2_in, (tdevice_RES2 ,UnitDelay));
VSL :VitalBuf(VSL_out, VSL_in, (tdevice_VSL ,UnitDelay));
---------------------------------------------------------------------------
-- Wire Delays
---------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN
w_1 : VitalWireDelay (C_ipd, C, tipd_C);
w_2 : VitalWireDelay (D_ipd, D, tipd_D);
w_3 : VitalWireDelay (SNeg_ipd, SNeg, tipd_SNeg);
w_4 : VitalWireDelay (HOLDNeg_ipd, HOLDNeg, tipd_HOLDNeg);
w_5 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
END BLOCK;
---------------------------------------------------------------------------
-- Main Behavior Block
---------------------------------------------------------------------------
Behavior: BLOCK
-- State Machine : State_Type
TYPE state_type IS (IDLE,
DP_DOWN,
WRITE_SR,
SECTOR_ER,
BULK_ER,
PAGE_PG
);
-- Instruction Type
TYPE instruction_type IS (NONE,
WREN,
WRDI,
WRSR,
RDSR,
READ,
FAST_READ,
SE,
BE,
PP,
DP,
RES_READ_ES
);
TYPE WByteType IS ARRAY (0 TO 255) OF INTEGER RANGE -1 TO MaxData;
--Flash Memory Array
TYPE MemArray IS ARRAY (0 TO AddrRANGE) OF INTEGER RANGE -1 TO MaxData;
---------------------------------------------------------------------------
-- memory declaration
---------------------------------------------------------------------------
SHARED VARIABLE Mem : MemArray := (OTHERS => MaxData);
-- states
SIGNAL current_state : state_type; --
SIGNAL next_state : state_type; --
SIGNAL WByte : WByteType := (others => 0);
SIGNAL Instruct : instruction_type;
--zero delay signal
SIGNAL Q_zd : std_logic :='Z';
SIGNAL Q_temp : std_logic :='Z';
-- powerup parameters
SIGNAL ChipSelectOk : std_logic := '0';
SIGNAL WriteOk : std_logic := '0';
SHARED VARIABLE Status_reg : std_logic_vector(7 downto 0)
:= (others => '0');
SIGNAL Status_reg_in : std_logic_vector(7 downto 0)
:= (others => '0');
ALIAS WIP :std_logic IS Status_reg(0);
ALIAS WEL :std_logic IS Status_reg(1);
ALIAS BP0 :std_logic IS Status_reg(2);
ALIAS BP1 :std_logic IS Status_reg(3);
ALIAS BP2 :std_logic IS Status_reg(4);
ALIAS SRWD :std_logic IS Status_reg(7);
--Command Register
SIGNAL write : std_logic := '0';
SIGNAL read_out : std_logic := '0';
SIGNAL fast_rd : boolean := true;
SIGNAL rd : boolean := false;
SIGNAL es_read : boolean := false;
SIGNAL change_addr : std_logic := '0';
--FSM control signals
SIGNAL PDONE : std_logic := '1'; --Page Prog. Done
SIGNAL PSTART : std_logic := '0'; --Start Page Programming
SIGNAL WDONE : std_logic := '1'; --Write. Done
SIGNAL WSTART : std_logic := '0'; --Start Write
SIGNAL ESTART : std_logic := '0'; --Start Erase
SIGNAL EDONE : std_logic := '1'; --Erase Done
SIGNAL RES_in : std_logic := '0'; --RES1_in OR RES2_in
SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0;
SIGNAL Byte_number : NATURAL RANGE 0 TO 255 := 0;
SHARED VARIABLE Sec_Prot : std_logic_vector(SecNum downto 0) :=
(OTHERS => '0');
SIGNAL Address : NATURAL RANGE 0 TO AddrRANGE := 0;
-- timing check violation
SIGNAL Viol : X01 := '0';
PROCEDURE ADDRHILO_SEC(
VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE Addr : NATURAL) IS
VARIABLE sector : NATURAL RANGE 0 TO SecNum;
BEGIN
sector := Addr/16#10000#;
AddrLOW := sector*16#10000#;
AddrHIGH := sector*16#10000# + 16#0FFFF#;
END AddrHILO_SEC;
PROCEDURE ADDRHILO_PG(
VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE Addr : NATURAL) IS
VARIABLE page : NATURAL RANGE 0 TO 65535;
BEGIN
page := Addr/16#100#;
AddrLOW := Page*16#100#;
AddrHIGH := Page*16#100# + 16#FF#;
END AddrHILO_PG;
BEGIN
----------------------------------------------------------------------------
--Power Up parameters timing
---------------------------------------------------------------------------
ChipSelectOk <= '1' AFTER tdevice_VSL;
WriteOk <= '1' AFTER tdevice_PUW;
---------------------------------------------------------------------------
-- VITAL Timing Checks Procedures
---------------------------------------------------------------------------
VITALTimingCheck: PROCESS(D_ipd, C_ipd, SNeg_ipd, HOLDNeg_ipd,
WNeg_ipd)
-- Timing Check Variables
VARIABLE Tviol_D_C : X01 := '0';
VARIABLE TD_D_C : VitalTimingDataType;
VARIABLE Tviol_HOLD_C : X01 := '0';
VARIABLE TD_HOLD_C : VitalTimingDataType;
VARIABLE Tviol_S_C : X01 := '0';
VARIABLE TD_S_C : VitalTimingDataType;
VARIABLE Tviol_WS_S : X01 := '0';
VARIABLE TD_WS_S : VitalTimingDataType;
VARIABLE Tviol_WH_S : X01 := '0';
VARIABLE TD_WH_S : VitalTimingDataType;
VARIABLE Pviol_S : X01 := '0';
VARIABLE PD_S : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_C : X01 := '0';
VARIABLE PD_C : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_C_rd : X01 := '0';
VARIABLE PD_C_rd : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_C_fast_rd : X01 := '0';
VARIABLE PD_C_fast_rd : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Violation : X01 := '0';
BEGIN
---------------------------------------------------------------------------
-- Timing Check Section
---------------------------------------------------------------------------
IF (TimingChecksOn) THEN
-- Setup/Hold Check between D and C
VitalSetupHoldCheck (
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => C_ipd,
RefSignalName => "C",
SetupHigh => tsetup_D_C,
SetupLow => tsetup_D_C,
HoldHigh => thold_D_C,
HoldLow => thold_D_C,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_D_C,
Violation => Tviol_D_C
);
-- Setup/Hold Check between HOLD# and C /
VitalSetupHoldCheck (
TestSignal => HOLDNeg_ipd,
TestSignalName => "HOLD#",
RefSignal => C_ipd,
RefSignalName => "C",
SetupHigh => tsetup_C_HOLDNeg,
SetupLow => tsetup_HOLDNeg_C,
HoldHigh => thold_C_HOLDNeg,
HoldLow => thold_HOLDNeg_C,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_HOLD_C,
Violation => Tviol_HOLD_C
);
-- Setup/Hold Check between CS# and C
VitalSetupHoldCheck (
TestSignal => SNeg_ipd,
TestSignalName => "S#",
RefSignal => C_ipd,
RefSignalName => "C",
SetupHigh => tsetup_SNeg_C,
SetupLow => tsetup_SNeg_C,
HoldHigh => thold_SNeg_C,
HoldLow => thold_SNeg_C,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_S_C,
Violation => Tviol_S_C
);
-- Setup Check between W# and CS# \
VitalSetupHoldCheck (
TestSignal => WNeg_ipd,
TestSignalName => "W#",
RefSignal => SNeg_ipd,
RefSignalName => "S#",
SetupHigh => tsetup_WNeg_SNeg,
CheckEnabled => true,
RefTransition => '\',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WS_S,
Violation => Tviol_WS_S
);
-- Hold Check between W# and CS# /
VitalSetupHoldCheck (
TestSignal => WNeg_ipd,
TestSignalName => "W#",
RefSignal => SNeg_ipd,
RefSignalName => "S#",
HoldHigh => thold_WNeg_SNeg,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WH_S,
Violation => Tviol_WH_S
);
-- Period Check S#
VitalPeriodPulseCheck (
TestSignal => SNeg_ipd,
TestSignalName => "S#",
PulseWidthHigh => tpw_SNeg_posedge,
PeriodData => PD_S,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_S,
HeaderMsg => InstancePath & PartID,
CheckEnabled => true );
-- Period Check C for everything but READ
VitalPeriodPulseCheck (
TestSignal => C_ipd,
TestSignalName => "C",
PulseWidthLow => tpw_C_negedge,
PulseWidthHigh => tpw_C_posedge,
PeriodData => PD_C,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_C,
HeaderMsg => InstancePath & PartID,
CheckEnabled => true );
-- Period Check C for READ
VitalPeriodPulseCheck (
TestSignal => C_ipd,
TestSignalName => "C",
Period => tperiod_C_rd,
PeriodData => PD_C_rd,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_C_rd,
HeaderMsg => InstancePath & PartID,
CheckEnabled => rd );
-- Period Check C for other than READ
VitalPeriodPulseCheck (
TestSignal => C_ipd,
TestSignalName => "C",
Period => tperiod_C_fast_rd,
PeriodData => PD_C_fast_rd,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_C_fast_rd,
HeaderMsg => InstancePath & PartID,
CheckEnabled => fast_rd );
Violation := Tviol_D_C OR
Tviol_HOLD_C OR
Tviol_S_C OR
Tviol_WS_S OR
Tviol_WH_S OR
Pviol_C OR
Pviol_C_rd OR
Pviol_C_fast_rd OR
Pviol_S;
Viol <= Violation;
ASSERT Violation = '0'
REPORT InstancePath & partID & ": simulation may be" &
" inaccurate due to timing violations"
SEVERITY WARNING;
END IF;
END PROCESS VITALTimingCheck;
----------------------------------------------------------------------------
-- sequential process for FSM state transition
----------------------------------------------------------------------------
StateTransition : PROCESS(next_state, WriteOk)
BEGIN
IF WriteOk = '1' THEN
current_state <= next_state;
END IF;
END PROCESS StateTransition;
---------------------------------------------------------------------------
-- Write cycle decode
---------------------------------------------------------------------------
BusCycleDecode : PROCESS(C_ipd, SNeg_ipd, HOLDNeg_ipd, D_ipd, RES_in)
TYPE bus_cycle_type IS (STAND_BY,
CODE_BYTE,
ADDRESS_BYTES,
DUMMY_BYTES,
DATA_BYTES
);
VARIABLE bus_cycle_state : bus_cycle_type;
VARIABLE data_cnt : NATURAL := 0;
VARIABLE addr_cnt : NATURAL := 0;
VARIABLE code_cnt : NATURAL := 0;
VARIABLE dummy_cnt : NATURAL := 0;
VARIABLE bit_cnt : NATURAL := 0;
VARIABLE Data_in : std_logic_vector(2047 downto 0)
:= (others => '0');
VARIABLE code : std_logic_vector(7 downto 0);
VARIABLE code_in : std_logic_vector(7 downto 0);
VARIABLE Byte_slv : std_logic_vector(7 downto 0);
VARIABLE addr_bytes : std_logic_vector(HiAddrBit downto 0);
VARIABLE Address_in : std_logic_vector(23 downto 0);
BEGIN
CASE bus_cycle_state IS
WHEN STAND_BY =>
IF falling_edge(SNeg_ipd) THEN
Instruct <= NONE;
write <= '1';
code_cnt := 0;
addr_cnt := 0;
data_cnt := 0;
dummy_cnt := 0;
bus_cycle_state := CODE_BYTE;
END IF;
WHEN CODE_BYTE =>
IF rising_edge(C_ipd) AND HOLDNeg_ipd = '1' THEN
Code_in(code_cnt) := D_ipd;
code_cnt := code_cnt + 1;
IF code_cnt = BYTE THEN
--MSB first
FOR I IN 7 DOWNTO 0 LOOP
code(i) := code_in(7-i);
END LOOP;
CASE code IS
WHEN "00000110" =>
Instruct <= WREN;
bus_cycle_state := DATA_BYTES;
WHEN "00000100" =>
Instruct <= WRDI;
bus_cycle_state := DATA_BYTES;
WHEN "00000001" =>
Instruct <= WRSR;
bus_cycle_state := DATA_BYTES;
WHEN "00000101" =>
Instruct <= RDSR;
bus_cycle_state := DATA_BYTES;
WHEN "00000011" =>
Instruct <= READ;
bus_cycle_state := ADDRESS_BYTES;
WHEN "00001011" =>
Instruct <= FAST_READ;
bus_cycle_state := ADDRESS_BYTES;
WHEN "10101011" =>
Instruct <= RES_READ_ES;
bus_cycle_state := DUMMY_BYTES;
WHEN "11011000" =>
Instruct <= SE;
bus_cycle_state := ADDRESS_BYTES;
WHEN "11000111" =>
Instruct <= BE;
bus_cycle_state := DATA_BYTES;
WHEN "00000010" =>
Instruct <= PP;
bus_cycle_state := ADDRESS_BYTES;
WHEN "10111001" =>
Instruct <= DP;
bus_cycle_state := DATA_BYTES;
WHEN others =>
null;
END CASE;
END IF;
END IF;
WHEN ADDRESS_BYTES =>
IF rising_edge(C_ipd) AND HOLDNeg_ipd = '1' THEN
Address_in(addr_cnt) := D_ipd;
addr_cnt := addr_cnt + 1;
IF addr_cnt = 3*BYTE THEN
FOR I IN 23 DOWNTO 0 LOOP
addr_bytes(23-i) := Address_in(i);
END LOOP;
Address <= to_nat(addr_bytes);
change_addr <= '1','0' AFTER 1 ns;
IF Instruct = FAST_READ THEN
bus_cycle_state := DUMMY_BYTES;
ELSE
bus_cycle_state := DATA_BYTES;
END IF;
END IF;
END IF;
WHEN DUMMY_BYTES =>
IF rising_edge(C_ipd) AND HOLDNeg_ipd = '1' THEN
dummy_cnt := dummy_cnt + 1;
IF dummy_cnt = BYTE THEN
IF Instruct = FAST_READ THEN
bus_cycle_state := DATA_BYTES;
END IF;
ELSIF dummy_cnt = 3*BYTE THEN
bus_cycle_state := DATA_BYTES;
es_read <= true;
END IF;
END IF;
IF rising_edge(SNeg_ipd) THEN
IF (HOLDNeg_ipd = '1' AND dummy_cnt = 0 AND
Instruct = RES_READ_ES) THEN
write <= '0';
es_read <= false;
END IF;
bus_cycle_state := STAND_BY;
END IF;
WHEN DATA_BYTES =>
IF falling_edge(C_ipd) AND SNeg_ipd = '0' AND
HOLDNeg_ipd = '1' THEN
IF Instruct = READ OR Instruct = RES_READ_ES
OR Instruct = FAST_READ OR Instruct = RDSR THEN
read_out <= '1', '0' AFTER 1 ns;
END IF;
END IF;
IF rising_edge(C_ipd) AND HOLDNeg_ipd = '1' THEN
IF data_cnt > 2047 THEN
--In case of PP, if more than 256 bytes are
--sent to the device
IF bit_cnt = 0 THEN
FOR I IN 0 TO (255*BYTE - 1) LOOP
Data_in(i) := Data_in(i+8);
END LOOP;
END IF;
Data_in(2040 + bit_cnt) := D_ipd;
bit_cnt := bit_cnt + 1;
IF bit_cnt = 8 THEN
bit_cnt := 0;
END IF;
data_cnt := data_cnt + 1;
ELSE
Data_in(data_cnt) := D_ipd;
data_cnt := data_cnt + 1;
bit_cnt := 0;
END IF;
END IF;
IF rising_edge(SNeg_ipd) THEN
bus_cycle_state := STAND_BY;
es_read <= true;
IF HOLDNeg_ipd = '1' AND WriteOk = '1' THEN
CASE Instruct IS
WHEN WREN | WRDI | DP | BE | SE =>
IF data_cnt = 0 THEN
write <= '0';
END IF;
WHEN RES_READ_ES =>
write <= '0';
WHEN WRSR =>
IF data_cnt = 8 THEN
write <= '0';
Status_reg_in <= Data_in(7 downto 0);
--MSB first
END IF;
WHEN PP =>
IF ((data_cnt mod 8) = 0 AND
data_cnt > BYTE) THEN
write <= '0';
FOR I IN 0 TO 255 LOOP
FOR J IN 7 DOWNTO 0 LOOP
Byte_slv(j) :=
Data_in((i*8) + (7-j));
END LOOP;
WByte(i) <= to_nat(Byte_slv);
END LOOP;
IF data_cnt > 256*BYTE THEN
Byte_number <= 255;
ELSE
Byte_number <= data_cnt/8-1;
END IF;
END IF;
WHEN others =>
null;
END CASE;
END IF;
END IF;
END CASE;
END PROCESS BusCycleDecode;
---------------------------------------------------------------------------
-- Timing control for the Page Program
---------------------------------------------------------------------------
ProgTime : PROCESS(PSTART)
VARIABLE pob : time;
BEGIN
IF LongTimming THEN
pob := tdevice_PP;
ELSE
pob := tdevice_PP / 100;
END IF;
IF rising_edge(PSTART) AND PDONE = '1' THEN
IF NOT Sec_Prot(SA) = '1' THEN
PDONE <= '0', '1' AFTER pob;
END IF;
END IF;
END PROCESS ProgTime;
---------------------------------------------------------------------------
-- Timing control for the Write Status Register
---------------------------------------------------------------------------
WriteTime : PROCESS(WSTART)
VARIABLE wob : time;
BEGIN
IF LongTimming THEN
wob := tdevice_WR;
ELSE
wob := tdevice_WR / 100;
END IF;
IF rising_edge(WSTART) AND WDONE = '1' THEN
WDONE <= '0', '1' AFTER wob;
END IF;
END PROCESS WriteTime;
---------------------------------------------------------------------------
-- Timing control for the Bulk Erase
---------------------------------------------------------------------------
ErsTime : PROCESS(ESTART)
VARIABLE seo : time;
VARIABLE beo : time;
VARIABLE duration : time;
BEGIN
IF LongTimming THEN
seo := tdevice_SE;
beo := tdevice_BE;
ELSE
seo := tdevice_SE / 100;
beo := tdevice_BE / 100;
END IF;
IF rising_edge(ESTART) AND EDONE = '1' THEN
IF Instruct = BE THEN
duration := beo;
ELSE --Instruct = SE
duration := seo;
END IF;
EDONE <= '0', '1' AFTER duration;
END IF;
END PROCESS ErsTime;
---------------------------------------------------------------------------
-- Main Behavior Process
-- combinational process for next state generation
---------------------------------------------------------------------------
StateGen :PROCESS(write, SNeg, WDONE, PDONE, EDONE)
VARIABLE sect : NATURAL RANGE 0 TO SecNum;
BEGIN
-----------------------------------------------------------------------
-- Functionality Section
-----------------------------------------------------------------------
CASE current_state IS
WHEN IDLE =>
IF falling_edge(write) THEN
IF Instruct = WRSR AND WEL = '1'
AND not(SRWD = '1' AND WNeg = '0') THEN
-- can not execute if HPM is entered
-- or if WEL bit is zero
next_state <= WRITE_SR;
ELSIF Instruct = PP AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
next_state <= PAGE_PG;
END IF;
ELSIF Instruct = SE AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
next_state <= SECTOR_ER;
END IF;
ELSIF Instruct = BE AND WEL = '1' AND
(BP0 = '0' AND BP1 = '0' AND BP2 = '0') THEN
next_state <= BULK_ER;
ELSIF Instruct = DP THEN
next_state <= DP_DOWN;
ELSE
next_state <= IDLE;
END IF;
END IF;
WHEN WRITE_SR =>
IF rising_edge(WDONE) THEN
next_state <= IDLE;
END IF;
WHEN PAGE_PG =>
IF rising_edge(PDONE) THEN
next_state <= IDLE;
END IF;
WHEN BULK_ER | SECTOR_ER =>
IF rising_edge(EDONE) THEN
next_state <= IDLE;
END IF;
WHEN DP_DOWN =>
IF falling_edge(write) AND Instruct = RES_READ_ES THEN
next_state <= IDLE;
END IF;
END CASE;
END PROCESS StateGen;
---------------------------------------------------------------------------
--FSM Output generation and general funcionality
---------------------------------------------------------------------------
Functional : PROCESS(write,read_out, WDONE, PDONE, EDONE, current_state,
SNeg_ipd, HOLDNeg_ipd, Instruct, Address, WByte,
WriteOk, RES1_out, RES2_out, change_addr,
ChipSelectOk, WNeg_ipd, RES1_in, RES2_in)
TYPE WDataType IS ARRAY (0 TO 255) OF INTEGER RANGE -1 TO MaxData;
VARIABLE WData : WDataType:= (OTHERS => 0);
VARIABLE oe : boolean := FALSE;
VARIABLE AddrLo : NATURAL;
VARIABLE AddrHi : NATURAL;
VARIABLE Addr : NATURAL;
VARIABLE read_cnt : NATURAL;
VARIABLE read_addr : NATURAL RANGE 0 TO AddrRANGE;
VARIABLE data_out : std_logic_vector(7 downto 0);
VARIABLE ident_out : std_logic_vector(23 downto 0);
VARIABLE old_bit : std_logic_vector(7 downto 0);
VARIABLE new_bit : std_logic_vector(7 downto 0);
VARIABLE old_int : INTEGER RANGE -1 to MaxData;
VARIABLE new_int : INTEGER RANGE -1 to MaxData;
VARIABLE wr_cnt : NATURAL RANGE 0 TO 255;
VARIABLE sect : NATURAL RANGE 0 TO SecNum;
VARIABLE BP : std_logic_vector(2 downto 0) := "000";
BEGIN
-----------------------------------------------------------------------
-- Functionality Section
-----------------------------------------------------------------------
oe := rising_edge(read_out) AND ChipSelectOk = '1';
RES_in <= RES1_in OR RES2_in; --this way, both timing conditions on
--Release from Deep Power Down are merged
IF Instruct'EVENT THEN
read_cnt := 0;
fast_rd <= true;
rd <= false;
END IF;
IF rising_edge(change_addr) THEN
read_addr := Address;
END IF;
IF RES1_out'EVENT AND RES1_out = '1' THEN
RES1_in <= '0';
END IF;
IF RES2_out'EVENT AND RES2_out = '1' THEN
RES2_in <= '0';
END IF;
CASE current_state IS
WHEN IDLE =>
IF falling_edge(write) AND WriteOK = '1' THEN
IF RES_in = '1' AND Instruct /= DP THEN
ASSERT false
REPORT InstancePath & partID & "Command results" &
" can be corrupted, a delay of tRES" &
" currently in progress."
SEVERITY WARNING;
END IF;
IF Instruct = WREN THEN
WEL := '1';
ELSIF Instruct = WRDI THEN
WEL := '0';
ELSIF Instruct = WRSR AND WEL = '1'
AND not(SRWD = '1' AND WNeg_ipd = '0') THEN
-- can not execute if HPM is entered
-- or if WEL bit is zero
WSTART <= '1', '0' AFTER 1 ns;
WIP := '1';
ELSIF Instruct = PP AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
PSTART <= '1', '0' AFTER 1 ns;
WIP := '1';
SA <= sect;
Addr := Address;
wr_cnt := Byte_number;
FOR I IN wr_cnt DOWNTO 0 LOOP
IF Viol /= '0' AND Sec_Prot(SA) /= '0' THEN
WData(i) := -1;
ELSE
WData(i) := WByte(i);
END IF;
END LOOP;
END IF;
ELSIF Instruct = SE AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
ESTART <= '1', '0' AFTER 1 ns;
WIP := '1';
Addr := Address;
END IF;
ELSIF Instruct = BE AND WEL = '1' AND
(BP0 = '0' AND BP1 = '0' AND BP2 = '0') THEN
ESTART <= '1', '0' AFTER 1 ns;
WIP := '1';
END IF;
ELSIF oe AND RES_in = '0' THEN
IF Instruct = RDSR THEN
--Read Status Register
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
ELSIF Instruct = READ OR Instruct = FAST_READ THEN
--Read Memory array
IF Instruct = READ THEN
fast_rd <= false;
rd <= true;
END IF;
data_out := to_slv(Mem(read_addr),8);
Q_zd <= data_out(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
IF read_addr = AddrRANGE THEN
read_addr := 0;
ELSE
read_addr := read_addr + 1;
END IF;
END IF;
ELSE --IF Instruct = RES_READ_ES - look at assertion of oe
data_out := to_slv(ES, 8);
Q_zd <= data_out(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ELSIF oe AND RES_in = '1' THEN
Q_zd <= 'X';
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
ASSERT false
REPORT InstancePath & partID & "Command results" &
" can be corrupted, a delay of tRES" &
" currently in progress."
SEVERITY WARNING;
END IF;
WHEN WRITE_SR =>
IF oe AND Instruct = RDSR THEN
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
IF WDONE = '1' THEN
WIP := '0';
WEL := '0';
SRWD := Status_reg_in(0);--MSB first
BP2 := Status_reg_in(3);
BP1 := Status_reg_in(4);
BP0 := Status_reg_in(5);
BP := BP2 & BP1 & BP0;
CASE BP IS
WHEN "000" =>
Sec_Prot := (others => '0');
WHEN "001" =>
Sec_Prot(15) := '1';
WHEN "010" =>
Sec_Prot(15 downto 14):= "11";
WHEN "011" =>
Sec_Prot(15 downto 12):= to_slv(16#F#,4);
WHEN "100" =>
Sec_Prot(15 downto 8):= to_slv(16#FF#,8);
WHEN others =>
Sec_Prot := (others => '1');
END CASE;
END IF;
WHEN PAGE_PG =>
IF oe AND Instruct = RDSR THEN
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ADDRHILO_PG(AddrLo, AddrHi, Addr);
FOR I IN Addr TO Addr + wr_cnt LOOP
new_int := WData(i-Addr);
IF (i - AddrLo) >= 256 THEN
old_int := Mem(i - 256);
IF new_int > -1 THEN
new_bit := to_slv(new_int,8);
IF old_int > -1 THEN
old_bit := to_slv(old_int,8);
FOR j IN 0 TO 7 LOOP
IF old_bit(j) = '0' THEN
new_bit(j) := '0';
END IF;
END LOOP;
new_int := to_nat(new_bit);
END IF;
WData(i-Addr) := new_int;
ELSE
WData(i-Addr) := -1;
END IF;
ELSE
old_int := Mem(i);
IF new_int > -1 THEN
new_bit := to_slv(new_int,8);
IF old_int > -1 THEN
old_bit := to_slv(old_int,8);
FOR j IN 0 TO 7 LOOP
IF old_bit(j) = '0' THEN
new_bit(j) := '0';
END IF;
END LOOP;
new_int := to_nat(new_bit);
END IF;
WData(i-Addr) := new_int;
ELSE
WData(i-Addr) := -1;
END IF;
END IF;
END LOOP;
FOR I IN Addr TO Addr + wr_cnt LOOP
IF (i - AddrLo) >= 256 THEN
Mem (i - 256) := -1;
ELSE
Mem (i) := -1;
END IF;
END LOOP;
IF PDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN Addr TO Addr + wr_cnt LOOP
IF (i - AddrLo) >= 256 THEN
Mem(i - 256) := WData(i-Addr);
ELSE
Mem (i) := WData(i-Addr);
END IF;
END LOOP;
END IF;
WHEN SECTOR_ER =>
IF oe AND Instruct = RDSR THEN
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ADDRHILO_SEC(AddrLo, AddrHi, Addr);
FOR i IN AddrLo TO AddrHi LOOP
Mem(i) := -1;
END LOOP;
IF EDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN AddrLo TO AddrHi LOOP
Mem(i) := MaxData;
END LOOP;
END IF;
WHEN BULK_ER =>
IF oe AND Instruct = RDSR THEN
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
FOR i IN 0 TO AddrRANGE LOOP
Mem(i) := -1;
END LOOP;
IF EDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN 0 TO AddrRANGE LOOP
Mem(i) := MaxData;
END LOOP;
END IF;
WHEN DP_DOWN =>
IF falling_edge(write) THEN
IF Instruct = RES_READ_ES THEN
IF es_read THEN
RES1_in <= '1';
ELSE
RES2_in <= '1';
END IF;
END IF;
ELSIF oe AND Instruct = RES_READ_ES THEN
--Read Electronic Signature
data_out := to_slv(ES,8);
Q_zd <= data_out(7 - read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
END CASE;
--Output Disable Control
IF ((SNeg_ipd = '1') OR (HOLDNeg_ipd = '0')) THEN
Q_temp <= Q_zd;
Q_zd <= 'Z';
END IF;
IF ((SNeg_ipd = '0') AND rising_edge(HOLDNeg_ipd) AND C_ipd = '0') THEN
Q_zd <= Q_temp;
END IF;
END PROCESS Functional;
---------------------------------------------------------------------------
---- File Read Section - Preload Control
---------------------------------------------------------------------------
MemPreload : PROCESS
-- text file input variables
FILE mem_file : text is mem_file_name;
VARIABLE ind : NATURAL RANGE 0 TO AddrRANGE := 0;
VARIABLE buf : line;
BEGIN
---------------------------------------------------------------------------
--m25p80 memory preload file format -----------------------------------
---------------------------------------------------------------------------
-- / - comment
-- @aaaaa - <aaaaa> stands for address
-- dd - <dd> is byte to be written at Mem(aaaaa++)
-- (aaaaa is incremented at every load)
-- only first 1-6 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
---------------------------------------------------------------------------
-- memory preload
IF (mem_file_name /= "none" AND UserPreload) THEN
ind := 0;
Mem := (OTHERS => MaxData);
WHILE (not ENDFILE (mem_file)) LOOP
READLINE (mem_file, buf);
IF buf(1) = '/' THEN
NEXT;
ELSIF buf(1) = '@' THEN
ind := h(buf(2 to 6)); --address
ELSE
IF ind <= AddrRANGE THEN
Mem(ind) := h(buf(1 to 2));
END IF;
IF ind < AddrRANGE THEN
ind := ind + 1;
ELSIF ind >= AddrRANGE THEN
ASSERT false
REPORT "Given preload address is out of" &
"memory address range"
SEVERITY warning;
END IF;
END IF;
END LOOP;
END IF;
WAIT;
END PROCESS MemPreload;
Q_OUT: PROCESS(Q_zd)
VARIABLE Q_GlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01Z (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Q_zd,
GlitchData => Q_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => C_ipd'LAST_EVENT,
PathDelay => VitalExtendtofillDelay(tpd_C_Q),
PathCondition => true),
1 => (InputChangeTime => SNeg_ipd'LAST_EVENT,
PathDelay => tpd_SNeg_Q,
PathCondition => SNeg_ipd = '1'),
2 => (InputChangeTime => HOLDNeg_ipd'LAST_EVENT,
PathDelay => tpd_HOLDNeg_Q,
PathCondition => TRUE)
)
);
END PROCESS Q_OUT;
END BLOCK behavior;
END vhdl_behavioral;
|
gpl-2.0
|
bc524cae48547db240e5b484aa10bea9
| 0.373576 | 5.208422 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml605/gtxclk.vhd
| 4 | 1,695 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
use unisim.IBUFDS_GTXE1;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity gtxclk is
port ( clk_p : in std_logic; -- input clock
clk_n : in std_logic; -- input clock
clkint : out std_ulogic; -- internal gtx clock
clkout : out std_ulogic -- external DDR clock
);
end;
architecture rtl of gtxclk is
component IBUFDS_GTXE1
generic (
CLKCM_CFG : boolean := TRUE;
CLKRCV_TRST : boolean := TRUE;
REFCLKOUT_DLY : bit_vector := b"0000000000"
);
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, clkl, clkin : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
x0 : ODDR port map ( Q => clkout, C => clkin, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
x1 : IBUFDS_GTXE1
port map ( O => clkl, ODIV2 => open, CEB => gnd,
I => clk_p, IB => clk_n);
x2 : BUFG port map (I => clkl, O => clkin);
clkint <= clkin;
end;
|
gpl-2.0
|
32fdfb4a779d584cbce8153e80214c82
| 0.549853 | 3.336614 | false | false | false | false |
joaocarlos/udlx-verilog
|
fpga/syn/clk_1mhz.vhd
| 1 | 14,759 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_1mhz.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY clk_1mhz IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END clk_1mhz;
ARCHITECTURE SYN OF clk_1mhz IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 50,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=clk_1mhz",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_1mhz.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_1mhz.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_1mhz.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_1mhz.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_1mhz.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_1mhz.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_1mhz_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
lgpl-3.0
|
8372f28bb824bb8f011e7eca2e4ea31a
| 0.699844 | 3.358898 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-pci-xc2v3000/config.vhd
| 1 | 7,001 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000006#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
676843dfcf56c249618b4077cc456ae8
| 0.646193 | 3.588416 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/sim/delay_wire.vhd
| 1 | 2,549 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Delayed bidirectional wire
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity delay_wire is
generic(
data_width : integer := 1;
delay_atob : real := 0.0;
delay_btoa : real := 0.0
);
port(
a : inout std_logic_vector(data_width-1 downto 0);
b : inout std_logic_vector(data_width-1 downto 0);
x : in std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end delay_wire;
architecture rtl of delay_wire is
signal a_dly,b_dly : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
constant zvector : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
function errinj(a,b: std_logic_vector) return std_logic_vector is
variable r: std_logic_vector(a'length-1 downto 0);
begin
r := a;
for k in a'length-1 downto 0 loop
if (a(k)='0' or a(k)='1') and b(k)='1' then
r(k) := not a(k);
end if;
end loop;
return r;
end;
begin
process(a)
begin
if a'event then
if b_dly = zvector then
a_dly <= transport a after delay_atob*1 ns;
else
a_dly <= (others => 'Z');
end if;
end if;
end process;
process(b)
begin
if b'event then
if a_dly = zvector then
b_dly <= transport errinj(b,x) after delay_btoa*1 ns;
else
b_dly <= (others => 'Z');
end if;
end if;
end process;
a <= b_dly; b <= a_dly;
end;
|
gpl-2.0
|
ea2d919df7f93429eb7287d95bbc2c52
| 0.577874 | 3.625889 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/logan.vhd
| 1 | 16,981 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0; v.match_count := (others => '0');
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
|
gpl-2.0
|
0a474db389072d251749d84d2bf3fa36
| 0.497851 | 3.861073 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddrintpkg.vhd
| 1 | 17,656 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrintpkg
-- File: ddrintpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Internal components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
package ddrintpkg is
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
component ddr2buf is
generic (
tech : integer := 0;
wabits : integer := 6;
wdbits : integer := 8;
rabits : integer := 6;
rdbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits -1) downto 0);
dataout : out std_logic_vector((rdbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits -1) downto 0);
datain : in std_logic_vector((wdbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0));
end component;
type ddr_request_type is record
startaddr : std_logic_vector(31 downto 0);
endaddr : std_logic_vector(9 downto 0);
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
maskdata : std_ulogic;
maskcb : std_ulogic;
burst : std_ulogic;
end record;
type ddr_response_type is record
done_tog : std_ulogic;
rctr_gray : std_logic_vector(3 downto 0);
readerr : std_ulogic;
end record;
constant ddr_request_none: ddr_request_type :=
((others => '0'), (others => '0'), "000", '0','0','0','0','0');
constant ddr_response_none: ddr_response_type := ('0',"0000",'0');
component ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
component ft_ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := 64;
bufbits : integer := 96;
ddrbits : integer := 16;
hwidthen : integer := 0;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ce : out std_logic;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen)-2 downto 0);
wbwdata : out std_logic_vector(bufbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig : out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(bufbits-1 downto 0);
hwidth : in std_logic;
synccfg : in std_logic;
request2 : out ddr_request_type;
start_tog2 : out std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
constant FTFE_BEID_DDR2 : std_logic_vector(3 downto 0) := "0000";
constant FTFE_BEID_SDR : std_logic_vector(3 downto 0) := "0001";
constant FTFE_BEID_DDR1 : std_logic_vector(3 downto 0) := "0010";
constant FTFE_BEID_SSR : std_logic_vector(3 downto 0) := "0011";
constant FTFE_BEID_LPDDR2: std_logic_vector(3 downto 0) := "0100";
component ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
-- dynamic sync (nosync=2)
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
component ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- Other components re-using sub-components above
-----------------------------------------------------------------------------
component ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
ahbbits : integer := ahbdw;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Gray-code routines
-----------------------------------------------------------------------------
function lin2gray(l: std_logic_vector) return std_logic_vector;
function gray2lin(g: std_logic_vector) return std_logic_vector;
function nextgray(g: std_logic_vector) return std_logic_vector;
-----------------------------------------------------------------------------
-- Data-mask routines
-----------------------------------------------------------------------------
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector;
function masklast(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
end package;
package body ddrintpkg is
function lin2gray(l: std_logic_vector) return std_logic_vector is
variable lx,r: std_logic_vector(l'length-1 downto 0);
begin
lx := l;
r(l'length-1) := lx(l'length-1);
if l'length > 1 then
r(l'length-2 downto 0) := lx(l'length-1 downto 1) xor lx(l'length-2 downto 0);
end if;
return r;
end lin2gray;
function gray2lin(g: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector(15 downto 0);
variable r: std_logic_vector(g'length-1 downto 0);
begin
x := (others => '0');
x(g'length-1 downto 0) := g;
if g'length > 1 then
x(14 downto 0) := x(14 downto 0) xor x(15 downto 1);
end if;
if g'length > 2 then
x(13 downto 0) := x(13 downto 0) xor x(15 downto 2);
end if;
if g'length > 4 then
x(11 downto 0) := x(11 downto 0) xor x(15 downto 4);
end if;
if g'length > 8 then
x(7 downto 0) := x(7 downto 0) xor x(15 downto 8);
end if;
r := x(g'length-1 downto 0);
return r;
end gray2lin;
function nextgray(g: std_logic_vector) return std_logic_vector is
variable gx,r: std_logic_vector(g'length-1 downto 0);
variable gx3,r3: std_logic_vector(2 downto 0) := "000";
variable l,nl: std_logic_vector(g'length-1 downto 0);
begin
gx := g;
if gx'length = 1 then
r(0) := not gx(0);
elsif gx'length = 2 then
r(1) := gx(0);
r(0) := not gx(1);
elsif gx'length = 3 then
-- r(2) := (gx(1) or gx(0)) and (not gx(2) or not gx(0));
-- r(1) := (gx(1) or gx(0)) and (gx(2) or not gx(0));
-- r(0) := gx(2) xor gx(1);
gx3 := gx(2 downto 0);
case gx3 is
when "000" => r3 := "001";
when "001" => r3 := "011";
when "011" => r3 := "010";
when "010" => r3 := "110";
when "110" => r3 := "111";
when "111" => r3 := "101";
when "101" => r3 := "100";
when others => r3 := "000";
end case;
r(2 downto 0) := r3;
else
l := gray2lin(g);
nl := std_logic_vector(unsigned(l)+1);
r := lin2gray(nl);
end if;
return r;
end nextgray;
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
r := (others => '0');
a32 := addr(3 downto 2);
a432 := addr(4 downto 2);
case ddrbits is
when 32 =>
if addr(2)='0' then r := "00000000";
else r := "11110000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0000";
when "01" => r := x"F000";
when "10" => r := x"FF00";
when others => r := x"FFF0";
end case;
when 128 =>
case a432 is
when "000" => r := x"00000000";
when "001" => r := x"F0000000";
when "010" => r := x"FF000000";
when "011" => r := x"FFF00000";
when "100" => r := x"FFFF0000";
when "101" => r := x"FFFFF000";
when "110" => r := x"FFFFFF00";
when others => r := x"FFFFFFF0";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end maskfirst;
function masklast(addr: std_logic_vector(9 downto 0);
hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable xaddr: std_logic_vector(9 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
xaddr := addr;
if hsize(2)='1' then
xaddr(3 downto 2) := "11";
xaddr(3 downto 2) := "11";
end if;
if hsize(2)='1' and hsize(0)='1' then
xaddr(4) := '1';
end if;
if hsize(1 downto 0)="11" then
xaddr(2) := '1';
end if;
a32 := xaddr(3 downto 2);
a432 := xaddr(4 downto 2);
r := (others => '0');
case ddrbits is
when 32 =>
if xaddr(2)='0' then r := "00001111";
else r := "00000000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0FFF";
when "01" => r := x"00FF";
when "10" => r := x"000F";
when others => r := x"0000";
end case;
when 128 =>
case a432 is
when "000" => r := x"0FFFFFFF";
when "001" => r := x"00FFFFFF";
when "010" => r := x"000FFFFF";
when "011" => r := x"0000FFFF";
when "100" => r := x"00000FFF";
when "101" => r := x"000000FF";
when "110" => r := x"0000000F";
when others => r := x"00000000";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end masklast;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable r16: std_logic_vector(3 downto 0);
variable a10: std_logic_vector(1 downto 0);
begin
r16 := (others => '0');
if hsize(2 downto 1)="00" then
r16 := addr(1) & addr(1) & (not addr(1)) & (not addr(1));
if hsize(0)='0' then
r16 := r16 or (addr(0) & (not addr(0)) & addr(0) & (not addr(0)));
end if;
end if;
r := (others => '0');
for x in 0 to ddrbits/16-1 loop
r(x*4+3 downto x*4) := r16;
end loop;
return r;
end masksub32;
end;
|
gpl-2.0
|
c8b441e8c14dde14a108044ad8e6c94d
| 0.531151 | 3.610634 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/misc.vhd
| 1 | 51,907 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0; syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
wdogen : std_ulogic;
latchv : std_logic_vector(NAHBIRQ-1 downto 0);
latchd : std_logic_vector(NAHBIRQ-1 downto 0);
end record;
type gptimer_in_vector is array (natural range <>) of gptimer_in_type;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
type gptimer_out_vector is array (natural range <>) of gptimer_out_type;
constant gptimer_in_none : gptimer_in_type := ('0', '0', '0', (others => '0'), (others => '0'));
constant gptimer_out_none : gptimer_out_type :=
((others => '0'), (others => '0'), '1', '0');
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0;
gelatch : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer := 1;
autoscrub : integer := 0;
errcnten : integer := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ftahbram2 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
testen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbdpram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
component ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
component ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1);
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
type ahbmst2_request is record
req: std_logic; -- Request enable bit
wr: std_logic;
hsize: std_logic_vector(2 downto 0);
hburst: std_logic_vector(2 downto 0);
hprot: std_logic_vector(3 downto 0);
addr: std_logic_vector(32-1 downto 0);
burst_cont: std_logic; -- Set for all except the first request in a burst
burst_wrap: std_logic; -- High for the request where wrap occurs
end record;
constant ahbmst2_request_none: ahbmst2_request := (
req => '0', wr => '0', hsize => "010", hburst => "000", burst_cont => '0',
burst_wrap => '0', addr => (others => '0'), hprot => "0011");
type ahbmst2_in_type is record
request: ahbmst2_request;
wrdata: std_logic_vector(AHBDW-1 downto 0);
-- For back-to-back transfers or bursts, this must be set when done is high
-- and then copied over to request after the rising edge of clk.
next_request: ahbmst2_request;
-- Insert busy cycle, must only be asserted when request and next_request
-- are both part of the same burst.
busy: std_logic;
hlock: std_logic; -- Lock signal, passed through directly to AMBA.
keepreq: std_logic; -- Keep bus request high even when no request needs it.
end record;
type ahbmst2_out_type is record
done: std_logic;
flip: std_logic;
fail: std_logic;
rddata: std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst2 is
generic (
hindex: integer := 0;
venid: integer;
devid: integer;
version: integer;
dmastyle: integer range 1 to 3 := 3;
syncrst: integer range 0 to 1 := 1
);
port (
clk: in std_logic;
rst: in std_logic;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
m2i: in ahbmst2_in_type;
m2o: out ahbmst2_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_in_vector is array (natural range <>) of gpio_in_type;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type gpio_out_vector is array (natural range <>) of gpio_out_type;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0;
iflagreg : integer range 0 to 1:= 0;
bpmode : integer range 0 to 1 := 0;
inpen : integer range 0 to 1 := 0;
doutresv : integer := 0;
dirresv : integer := 0;
bpresv : integer := 0;
inpresv : integer := 0;
pulse : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
mlck : std_ulogic;
end record;
constant ahb2ahb_ctrl_none : ahb2ahb_ctrl_type := ('0', '0', '0');
type ahb2ahb_ifctrl_type is record
mstifen : std_ulogic;
slvifen : std_ulogic;
end record;
constant ahb2ahb_ifctrl_none : ahb2ahb_ifctrl_type := ('1', '1');
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer range 0 to 1 := 0;
dir : integer range 0 to 1 := 0; -- 0 - down, 1 - up
ffact : integer range 0 to 15:= 2;
pfen : integer range 0 to 1 := 0;
wburst : integer range 2 to 32 := 8;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 2 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0;
lckdac : integer range 0 to 2 := 0;
slvmaccsz : integer range 32 to 256 := 32;
mstmaccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
ifctrlen : integer range 0 to 1 := 0;
fcfs : integer range 0 to NAHBMST := 0;
fcfsmtech : integer range 0 to NTECH := inferred;
scantest : integer range 0 to 1 := 0;
split : integer range 0 to 1 := 1;
pipe : integer range 0 to 128 := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type;
ifctrl : in ahb2ahb_ifctrl_type := ahb2ahb_ifctrl_none
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer range 0 to 15 := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0;
--
lckdac : integer range 0 to 2 := 2;
maccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
fcfs : integer range 0 to NAHBMST := 0;
scantest : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov : in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov : in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
bitdepth : std_logic_vector(1 downto 0); -- Bith depth
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1'
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000", "00");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 16 to 16 := 16; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AMBA wrapper for System Monitor
-----------------------------------------------------------------------------
type grsysmon_in_type is record
convst : std_ulogic;
convstclk : std_ulogic;
vauxn : std_logic_vector(15 downto 0);
vauxp : std_logic_vector(15 downto 0);
vn : std_ulogic;
vp : std_ulogic;
end record;
type grsysmon_out_type is record
alm : std_logic_vector(2 downto 0);
ot : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
channel : std_logic_vector(4 downto 0);
end record;
constant grsysmon_in_gnd : grsysmon_in_type :=
('0', '0', (others => '0'), (others => '0'), '0', '0');
component grsysmon
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end component;
-----------------------------------------------------------------------------
-- AMBA System ACE Interface Controller
-----------------------------------------------------------------------------
type gracectrl_in_type is record
di : std_logic_vector(15 downto 0);
-- brdy : std_ulogic;
irq : std_ulogic;
end record;
type gracectrl_out_type is record
addr : std_logic_vector(6 downto 0);
do : std_logic_vector(15 downto 0);
cen : std_ulogic;
wen : std_ulogic;
oen : std_ulogic;
doen : std_ulogic; -- Data output enable to pad
end record;
constant gracectrl_none : gracectrl_out_type :=
((others => '1'), (others => '1'), '1', '1', '1', '1');
component gracectrl
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 16/8-bit mode
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
clkace : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end component;
-----------------------------------------------------------------------------
-- General purpose register
-----------------------------------------------------------------------------
component grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end component;
component grgprbank is
generic (
pindex: integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval: integer := 0;
extrst: integer := 0;
rdataen: integer := 0;
wproten: integer := 0;
partrstmsk: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0);
resval : in std_logic_vector(nregs*regbits-1 downto 0) := (others => '0');
rdata : in std_logic_vector(nregs*regbits-1 downto 0) := (others => '0');
wprot : in std_logic_vector(nregs-1 downto 0) := (others => '0');
partrst : in std_ulogic := '1'
);
end component;
-----------------------------------------------------------------------------
-- EDAC Memory scrubber
-----------------------------------------------------------------------------
type memscrub_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
clrcount: std_logic;
start : std_logic;
end record;
component memscrub is
generic(
hmindex : integer := 0;
hsindex : integer := 0;
ioaddr : integer := 0;
iomask : integer := 16#FFF#;
hirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3;
memwidth: integer := AHBDW;
-- Read block (cache line) burst size, must be even mult of 2
burstlen: integer := 2;
countlen: integer := 8
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
scrubi: in memscrub_in_type
);
end component;
type ahb_mst_iface_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type ahb_mst_iface_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
component ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end component;
-----------------------------------------------------------------------------
-- Clock gate unit
-----------------------------------------------------------------------------
component grclkgate
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
ungateen : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic);
end component;
component grclkgate2x
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0;
fpuclken : integer := 0;
nahbclk : integer := 1;
nahbclk2x: integer := 1;
balance : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0);
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_logic_vector(nahbclk-1 downto 0);
clkahb2x : out std_logic_vector(nahbclk2x-1 downto 0);
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2+fpuclken)*(ncpu/(2-fpuclken)-1) downto 0);
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component grclkgatex
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0;
fpuclken : integer := 0;
nahbclk : integer := 1;
nahbclk2x: integer := 1;
balance : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0);
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_logic_vector(nahbclk-1 downto 0);
clkahb2x : out std_logic_vector(nahbclk2x-1 downto 0);
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2+fpuclken)*(ncpu/(2-fpuclken)-1) downto 0);
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component ahbwbax is
generic (
ahbbits: integer;
blocksz: integer := 16;
mstmode: integer := 0
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Wide-side slave inputs
wi_hready: in std_ulogic;
wi_hsel: in std_ulogic;
wi_htrans: in std_logic_vector(1 downto 0);
wi_hsize: in std_logic_vector(2 downto 0);
wi_hburst: in std_logic_vector(2 downto 0);
wi_hwrite: in std_ulogic;
wi_haddr: in std_logic_vector(31 downto 0);
wi_hwdata: in std_logic_vector(AHBDW-1 downto 0);
wi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
wi_hmaster: in std_logic_vector(3 downto 0);
wi_hprot: in std_logic_vector(3 downto 0);
wi_hmastlock: in std_ulogic;
-- Wide-side slave outputs
wo_hready: out std_ulogic;
wo_hresp : out std_logic_vector(1 downto 0);
wo_hrdata: out std_logic_vector(AHBDW-1 downto 0);
-- Narrow-side slave inputs
ni_hready: out std_ulogic;
ni_htrans: out std_logic_vector(1 downto 0);
ni_hsize: out std_logic_vector(2 downto 0);
ni_hburst: out std_logic_vector(2 downto 0);
ni_hwrite: out std_ulogic;
ni_haddr: out std_logic_vector(31 downto 0);
ni_hwdata: out std_logic_vector(31 downto 0);
ni_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
ni_hmaster: out std_logic_vector(3 downto 0);
ni_hprot : out std_logic_vector(3 downto 0);
ni_hmastlock: out std_ulogic;
-- Narrow-side slave outputs
no_hready: in std_ulogic;
no_hresp: in std_logic_vector(1 downto 0);
no_hrdata: in std_logic_vector(31 downto 0)
);
end component;
component ahbswba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_type;
ahbsi_slv: out ahb_slv_in_type;
ahbso_slv: in ahb_slv_out_type
);
end component;
component ahbswbav is
generic (
slvmask: integer;
ahbbits: integer;
blocksz: integer
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_vector;
ahbsi_slv: out ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
ahbso_slv: in ahb_slv_out_vector
);
end component;
component ahbmwba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbmo_mst : in ahb_mst_out_type;
ahbmi_mst: out ahb_mst_in_type;
ahbmo_bus: out ahb_mst_out_type;
ahbmi_bus: in ahb_mst_in_type
);
end component;
component ahbpl is
generic (
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#;
wrretry: integer range 0 to 2 := 2
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Bus-side slave inputs
bi_hready: in std_ulogic;
bi_hsel: in std_ulogic;
bi_htrans: in std_logic_vector(1 downto 0);
bi_hsize: in std_logic_vector(2 downto 0);
bi_hburst: in std_logic_vector(2 downto 0);
bi_hwrite: in std_ulogic;
bi_haddr: in std_logic_vector(31 downto 0);
bi_hwdata: in std_logic_vector(ahbbits-1 downto 0);
bi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
bi_hmaster: in std_logic_vector(3 downto 0);
bi_hprot: in std_logic_vector(3 downto 0);
bi_hmastlock: in std_ulogic;
-- Bus-side slave outputs
bo_hready: out std_ulogic;
bo_hresp : out std_logic_vector(1 downto 0);
bo_hrdata: out std_logic_vector(ahbbits-1 downto 0);
-- Slave-side slave inputs
si_hready: out std_ulogic;
si_htrans: out std_logic_vector(1 downto 0);
si_hsize: out std_logic_vector(2 downto 0);
si_hburst: out std_logic_vector(2 downto 0);
si_hwrite: out std_ulogic;
si_haddr: out std_logic_vector(31 downto 0);
si_hwdata: out std_logic_vector(ahbbits-1 downto 0);
si_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
si_hmaster: out std_logic_vector(3 downto 0);
si_hprot : out std_logic_vector(3 downto 0);
si_hmastlock: out std_ulogic;
-- Slave-side slave outputs
so_hready: in std_ulogic;
so_hresp: in std_logic_vector(1 downto 0);
so_hrdata: in std_logic_vector(ahbbits-1 downto 0);
-- For use in master mode
mi_hgrant: in std_ulogic;
mo_hbusreq: out std_ulogic
);
end component;
component ahbpls is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
bi: in ahb_slv_in_type;
bo: out ahb_slv_out_type;
si: out ahb_slv_in_type;
so: in ahb_slv_out_type
);
end component;
component ahbplm is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
mi: out ahb_mst_in_type;
mo: in ahb_mst_out_type;
bi: in ahb_mst_in_type;
bo: out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- GRPULSE
-----------------------------------------------------------------------------
component grpulse
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1; -- Interrupt index
nchannel: Integer := 24; -- Number of channels
npulse: Integer := 8; -- Channels with pulses
imask: Integer := 16#ff0000#; -- Interrupt mask
ioffset: Integer := 8; -- Interrupt offset
invertpulse: Integer := 0; -- Invert pulses
cntrwidth: Integer := 10; -- Width of counter
syncrst: Integer := 1; -- Only synchronous reset
oepol: Integer := 1); -- Output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpioi: in gpio_in_type;
gpioo: out gpio_out_type);
end component;
-----------------------------------------------------------------------------
-- GRTIMER
-----------------------------------------------------------------------------
component grtimer is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1;
sepirq: Integer := 1; -- separate interrupts
sbits: Integer := 10; -- scaler bits
ntimers: Integer range 1 to 7 := 2; -- number of timers
nbits: Integer := 32; -- timer bits
wdog: Integer := 0;
glatch: Integer := 0;
gextclk: Integer := 0;
gset: Integer := 0);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpti: in gptimer_in_type;
gpto: out gptimer_out_type);
end component;
-----------------------------------------------------------------------------
-- GRVERSION
-----------------------------------------------------------------------------
component grversion
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
versionnr: Integer := 16#0123#;
revisionnr: Integer := 16#4567#);
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AHBFROM - Microsemi/Actel Flash ROM
-----------------------------------------------------------------------------
component ahbfrom is
generic (
tech: integer := 0;
hindex: integer := 0;
haddr: integer := 0;
hmask: integer := 16#fff#;
width8: integer := 0;
memoryfile: string := "from.mem";
progfile: string := "from.ufc");
port (
rstn: in std_ulogic;
clk: in std_ulogic;
ahbi: in ahb_slv_in_type;
ahbo: out ahb_slv_out_type);
end component;
-----------------------------------------------------------------------------
-- Interrupt generator
-----------------------------------------------------------------------------
component irqgen
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ngen : integer range 1 to 15 := 1
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
-- function nandtree(v : std_logic_vector) return std_ulogic is
-- variable a : std_logic_vector(v'length-1 downto 0);
-- variable b : std_logic_vector(v'length downto 0);
-- begin
--
-- a := v; b(0) := '1';
--
-- for i in 0 to v'length-1 loop
-- b(i+1) := a(i) nand b(i);
-- end loop;
--
-- return b(v'length);
--
-- end;
end;
|
gpl-2.0
|
55b9a773dd0c68af80bff35deabc7f20
| 0.513206 | 3.683699 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/amba/dma2ahb_tp.vhd
| 1 | 67,518 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_TestPackage (package declaration)
--
-- File name : dma2ahb_tp.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 New package
-- 1.5 SH 1 Sep 2005 New library TOPNET
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.8 SH 10 Nov 2005 Updated DMA2AHB interface usage
-- 1.9 SH 4 Jan 2006 Burst routines added
-- Fault reporting priority and timing improved
-- 1.9.1 SH 12 Jan 2006 Correct DmaComp8
-- 1.9.2 SH ## ### #### Corrected compare to allow pull-up
-- Adjusted printouts
-- 1.9.3 JA 14 Dec 2007 Support for halfword and byte bursts
-- 1.9.4 MI 4 Aug 2008 Support for Lock
-- 1.9.5 SH 4 Mar 2011 Modifed burst accesses to mimic real hw
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDIO.all;
use GRLIB.DMA2AHB_Package.all;
use GRLIB.STDLIB.all;
package DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Vector of words
-----------------------------------------------------------------------------
type Data_Vector is array (Natural range <> ) of
Std_Logic_Vector(32-1 downto 0);
-----------------------------------------------------------------------------
-- Constants for comparison
-----------------------------------------------------------------------------
constant DontCare32: Std_Logic_Vector(31 downto 0) := (others => '-');
constant DontCare24: Std_Logic_Vector(23 downto 0) := (others => '-');
constant DontCare16: Std_Logic_Vector(15 downto 0) := (others => '-');
constant DontCare8: Std_Logic_Vector( 7 downto 0) := (others => '-');
----------------------------------------------------------------------------
-- Constant for calculating burst lengths
----------------------------------------------------------------------------
constant WordSize: integer := 32;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
end package DMA2AHB_TestPackage;
package body DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (To_X01(O(i))=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Std_Logic_Vector(
constant i: Integer;
w: Integer)
return Std_Logic_Vector is
variable tmp: Std_Logic_Vector(w-1 downto 0);
begin
tmp := Std_Logic_Vector(To_UnSigned(i, w));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Integer(
constant i: Std_Logic_Vector)
return Integer is
variable tmp: Integer;
begin
tmp := To_Integer(UnSigned(i));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clock: in Std_ULogic;
constant Offset: in Time := 5 ns;
constant Enable: in Boolean := True) is
begin
if Enable then
wait until Clock = '1'; -- synchronise
if Offset > 0 ns then
wait for Offset; -- output offset delay
end if;
end if;
end procedure Synchronise;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
dmai.Size <= "10";
dmai.Lock <= '0';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure DMAInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable L: Line;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '1';
dmai.Data <= Data;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Data <= Data;
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
dmai.Lock <= '0';
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
dmai.Lock <= '0';
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Data := (others => 'X');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
Data := dmao.Data;
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if ScreenOutput and OK then
Data := Temp;
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure DMARead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
Write (L, String'(" : expected: "));
HWrite(L, CxData);
Write (L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure DMAComp;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
end procedure DMAWriteQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWrite(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
end procedure DMAWrite16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMAQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMARead16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1)='0' then
TmpCx := CxData & "----------------";
else
TmpCx := "----------------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
RxData := TmpRx(31 downto 16);
else
RxData := TmpRx(15 downto 0);
end if;
end procedure DMAComp16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
end procedure DMAWriteQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWrite(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
end procedure DMAWrite8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMAQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMARead8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1 downto 0)="00" then
TmpCx := CxData & "--------" & "--------" & "--------";
elsif Address(1 downto 0)="01" then
TmpCx := "--------" & CxData & "--------" & "--------";
elsif Address(1 downto 0)="10" then
TmpCx := "--------" & "--------" & CxData & "--------";
else
TmpCx := "--------" & "--------" & "--------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
RxData := TmpRx(31 downto 24);
elsif Address(1 downto 0)="01" then
RxData := TmpRx(23 downto 16);
elsif Address(1 downto 0)="10" then
RxData := TmpRx(15 downto 8);
else
RxData := TmpRx( 7 downto 0);
end if;
end procedure DMAComp8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '1';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
-- wait for first grant, indicating start of accesses
Synchronise(HCLK, 0 ns);
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
end if;
GCount := GCount-1;
-- first data
if Size=32 then
dmai.Data <= Data(0);
elsif Size=16 then
dmai.Data <= Data(0)(31 downto 16) & Data(0)(31 downto 16);
elsif Size=8 then
dmai.Data <= Data(0)(31 downto 24) & Data(0)(31 downto 24) &
Data(0)(31 downto 24) & Data(0)(31 downto 24);
end if;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.OKAY='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
Synchronise(HCLK, 0 ns);
exit;
elsif dmao.OKAY='1' then
-- for each OKAY, provide new data
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
while dmao.Ready='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if GCount/=0 then
report "DMAWriteQuietBurst: Too few grants received!"
severity Failure;
end if;
exit;
else
if Size=32 then
dmai.Data <= Data(DCount);
elsif Size=16 then
dmai.Data <= Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2)))) &
Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2))));
elsif Size=8 then
dmai.Data <= Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4))));
end if;
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if ScreenOutput and OK then
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end loop;
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWriteBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
variable DataPart: Integer := 0;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '0';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
if Address(1 downto 0) = "00" then
DataPart := 0;
else
DataPart := 1;
end if;
elsif Size=8 then
dmai.Size <= HSIZE8;
if Address(1 downto 0) = "00" then
DataPart := 0;
elsif Address(1 downto 0) = "01" then
DataPart := 1;
elsif Address(1 downto 0) = "10" then
DataPart := 2;
else
DataPart := 3;
end if;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
-- wait for first grant, indicating start of accesses
Synchronise(HCLK, 0 ns);
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
end if;
GCount := GCount-1;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response"));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
-- for each READY, store data
if Size=32 then
Data(DCount-1) := dmao.Data;
elsif Size=16 then
Data((DCount-1)/2)((31-16*((DCount-1) mod 2)) downto (16-(16*((DCount-1) mod 2)))) :=
dmao.Data((31-16*DataPart) downto (16-16*DataPart));
DataPart := (DataPart + 1) mod 2;
elsif Size=8 then
Data((DCount-1)/4)((31-8*((DCount-1) mod 4)) downto (24-(8*((DCount-1) mod 4)))) :=
dmao.Data((31-8*DataPart) downto (24-8*DataPart));
DataPart := (DataPart + 1) mod 4;
end if;
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
if GCount/=0 then
report "DMAQuietBurst: Too few grants received!"
severity Failure;
end if;
exit;
else
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Data_Vector(0 to Data'Length-1);
begin
DMAQuietBurst(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if ScreenOutput and OK then
Data := Temp;
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Temp(i));
WriteLine(Output, L);
end loop;
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Temp := (others => (others => '-'));
Data := Temp;
TP := False;
end if;
end procedure DMAReadBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Data_Vector(0 to CxData'Length-1);
begin
DMAQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
Data := (others => (others => '-'));
RxData := Data;
else
for i in 0 to Data'Length-1 loop
if not Compare(Data(i), CxData(i)) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
Write(L, String'(" : expected: "));
HWrite(L, CxData(i));
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end if;
end loop;
RxData := Data;
end if;
end procedure DMACompBurst;
end package body DMA2AHB_TestPackage; --======================================--
|
gpl-2.0
|
95548f38bab98f9ca76f339bbae4be20
| 0.447318 | 4.715273 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-de2-ep2c35/clkgen_de2.vhd
| 1 | 3,582 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity clkgen_de2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of clkgen_de2 is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
|
gpl-2.0
|
3fa38f621822ce7bbe3ce2d32a16396b
| 0.595757 | 3.673846 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/sparc/cpu_disas.vhd
| 1 | 4,345 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1'); --and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity fpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
end;
-- pragma translate_on
|
gpl-2.0
|
4639be5550957c66908df92e19ac3398
| 0.604143 | 3.445678 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/ec/orca/ORCA_L.vhd
| 5 | 118,143 |
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_L.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RDA_temp : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RDB_temp : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_TEMP;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_TEMP;
RDB_process: process(RDB_node, WEB_node)
begin
if (WEB_node = '1') then
if (BWRITE_MODE = "WRITETHROUGH") then
RDB_temp <= RDB_node;
elsif (BWRITE_MODE = "NORMAL") then
RDB_temp <= RDB_temp;
end if;
else
RDB_temp <= RDB_node;
end if;
end process;
RDA_process: process(RDA_node, WEA_node)
begin
if (WEA_node = '1') then
if (AWRITE_MODE = "WRITETHROUGH") then
RDA_temp <= RDA_node;
elsif (AWRITE_MODE = "NORMAL") then
RDA_temp <= RDA_temp;
end if;
else
RDA_temp <= RDA_node;
end if;
end process;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
--QQ 7_17 variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A + WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
-- ************************************************************************
--
-- Block Memory: Behavioral Model
-- The kernel of other RAM applications
-- ************************************************************************
--
-- Filename: SC_BLOCK_RAM_L.vhd
-- Description: BRAM behavioral model.
-- ************************************************************************
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L_SYNC is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end SC_BRAM_16K_L_SYNC;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L_SYNC is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node : std_logic := 'X';
signal RCLK_node : std_logic := 'X';
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
WCLK_node <= WCLK;
RCLK_node <= RCLK;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
--KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_PDP_16K_L is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_PDP_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_PDP_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
---************* SC_FIFO_L **************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL;
architecture LATTICE_BEHAV of READ_POINTER_CTRL is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= (others => '0');
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= (others => '0');
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FLAG_LOGIC is
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC;
architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Pointer (
IN_ADDR : in STD_LOGIC_VECTOR
) return BOOLEAN is
variable v_Valid_Flag : BOOLEAN := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Pointer;
--------------------------------------------------------------------------
-- Function: Calculate_Offset
-- Description:
--------------------------------------------------------------------------
function Calculate_Offset (
IN_TC : in STD_LOGIC_VECTOR;
TC_LENGTH: in INTEGER
) return STD_LOGIC_VECTOR is
variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
vTC_TEMP := IN_TC;
vOFFSET := vTC_FULL-vTC_TEMP;
return vOFFSET;
end Calculate_Offset;
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL: process (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
--variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_WP_Valid_Flag = TRUE) then
v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
end if;
v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);
if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then
v_WP_Check_FULL := (others => '0');
elsif( v_WP_Valid_Flag = TRUE ) then
v_WP_Check_FULL := W_POINTER + 1;
end if;
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = v_WP_Check_FULL then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (W_POINTER > R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
if v_WP_Check_AMFL_TMP1 >= R_POINTER then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
else
AMFULL_D <= '0';
end if;
elsif (W_POINTER < R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
AMFULL_D <= '1';
elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
end if;
end if;
end process FULL_AMFULL;
EMPTY_AMEMPTY: process (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
--variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
end if;
v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if GLOBAL_RST = '1' then
EMPTY_D <= '0';
AMEMPTY_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = W_POINTER then -- Different from TSPEC QQ 07 17,2002
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (W_POINTER < R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if v_RP_Check_AMET >= W_POINTER then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER > R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
AMEMPTY_D <= '0';
elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER = R_POINTER) then
AMEMPTY_D <= '0';
end if;
end if;
end process EMPTY_AMEMPTY;
end LATTICE_BEHAV;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
---USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;
entity SC_FIFO_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_16K_L;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Function: INT_TO_VEC
---------------------------------------------------------
function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: integer := 0;
variable vQUOTIENT: integer := 0;
begin
vQUOTIENT := INPUT_INT;
for i in 0 to INPUT_LENGTH -1 loop
vTRANS := 0;
while vQUOTIENT >1 loop
vQUOTIENT := vQUOTIENT - 2;
vTRANS := vTRANS + 1;
end loop;
case vQUOTIENT is
when 1 =>
vDATA_STD_VEC(i) := '1';
when 0 =>
vDATA_STD_VEC(i) := '0';
when others =>
null;
end case;
vQUOTIENT := vTRANS;
end loop;
return vDATA_STD_VEC;
end INT_TO_VEC;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L_SYNC
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end component;
component READ_POINTER_CTRL
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0);
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := '0';
signal WCLK_node : STD_LOGIC := '0';
signal RST_node : STD_LOGIC := '0';
signal RPRST_node : STD_LOGIC := '0';
signal RE_node : STD_LOGIC := '0';
signal RCLK_node : STD_LOGIC := '0';
signal FULLIN_node : STD_LOGIC := '0';
signal EMPTYIN_node : STD_LOGIC := '0';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal FULLIN_reg : STD_LOGIC := '0';
signal EMPTYIN_reg : STD_LOGIC := '0';
signal FULL_node : STD_LOGIC := '0';
signal EMPTY_node : STD_LOGIC := '0';
signal AMFULL_node : STD_LOGIC := '0';
signal AMEMPTY_node : STD_LOGIC := '0';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => '0');
signal TC_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal FULL_reg : STD_LOGIC := '0';
signal EMPTY_reg : STD_LOGIC := '0';
signal AMFULL_reg : STD_LOGIC := '0';
signal AMEMPTY_reg : STD_LOGIC := '0';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := '0';
-- architecture
begin
GND_sig <= '0';
WE_node <= WE and not(FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE and EMPTY_node;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
--TC_node <= TO_STD_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_node <= INT_TO_VEC(TERMINAL_COUNT,WADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
-- WE_reg <= WE_node and not (FULL_reg); --QQ
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
-- RE_reg <= RE_node and EMPTY_reg; --QQ
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- READ_POINTER_CTRL instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC instance for FIFO
FIFO_FL_INST: FLAG_LOGIC
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
RPOINTER_WIDTH => RADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
TERMINAL_COUNT => TC_node,
R_POINTER => RP_node,
W_POINTER => WP_node,
GLOBAL_RST => RST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_node,
WDA => DI_node,
RADA => RP_node,
REA => RE_node,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_node,
RADB => RP_node,
REB => GND_sig,
RDB => open,
WCLK => WCLK_node,
RCLK => RCLK_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- FIFO V2: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_FIFO_V2.vhd
-- Description: FIFO behavioral model.
-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL_V2 is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= TERMINAL_COUNT;
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL_V2 is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= TERMINAL_COUNT ;
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER ;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity FLAG_LOGIC_V2 is
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC_V2;
architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process (GLOBAL_RST, FIFO_CAP, FIFO_PTR)
begin
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
EMPTY_D <= '0';
AMEMPTY_D <= '0';
else
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
if (FIFO_PTR < RDATA_WIDTH) then
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
end if;
end process FULL_AMFULL_EMPTY_AMEMPTY;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 Main Body
-- READ_POINTER_CTRL_V2
-- WRITE_POINTER_CTRL_V2
-- FLAG_LOGIC_V2
-- SC_BRAM_16K
-- ************************************************************************
-- ************************************************************************
-- Top Design Entity definition
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SC_FIFO_V2_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 8;
RDATA_WIDTH : integer := 64;
ALMOST_FULL_X : integer := 2;
ALMOST_EMPTY_Y : integer := 2;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_V2_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_V2_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
component READ_POINTER_CTRL_V2
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL_V2
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC_V2
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal RPRST_node : STD_LOGIC := 'X';
signal RE_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal FULLIN_node : STD_LOGIC := 'X';
signal EMPTYIN_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WE_reg : STD_LOGIC := 'X';
signal RE_reg : STD_LOGIC := 'X';
signal FULLIN_reg : STD_LOGIC := 'X';
signal EMPTYIN_reg : STD_LOGIC := 'X';
signal FULL_node : STD_LOGIC := 'X';
signal EMPTY_node : STD_LOGIC := 'X';
signal AMFULL_node : STD_LOGIC := 'X';
signal AMEMPTY_node : STD_LOGIC := 'X';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal TC_W_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal TC_R_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal FULL_reg : STD_LOGIC := 'X';
signal EMPTY_reg : STD_LOGIC := 'X';
signal AMFULL_reg : STD_LOGIC := 'X';
signal AMEMPTY_reg : STD_LOGIC := 'X';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := 'X';
--QQ FIFOV2
signal FIFO_capacity : integer := 0;
signal FIFO_pointer : integer := 0;
-- architecture
begin
FIFO_capacity <= (TERMINAL_COUNT + 1) * WDATA_WIDTH;
GND_sig <= '0';
WE_node <= WE and not (FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
TC_W_node <= CONV_STD_LOGIC_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_R_node <= CONV_STD_LOGIC_VECTOR((TERMINAL_COUNT+1)*(WDATA_WIDTH/RDATA_WIDTH)-1,RADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
WE_reg <= '0';
RE_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
WE_reg <= WE_node and not FULL_reg; --Fix DTS14659
--WE_reg <= WE_node;
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
RE_reg <= RE_node and EMPTY_reg;
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- Set FIFO_pointer
FIFO_CAP_POINTER: process ( RP_node, WP_node, RST_node, RPRST_node)
begin
--WP ++, FIFO_CAP --
if (WP_node'event and RP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH - RDATA_WIDTH;
elsif(WP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH;
end if;
--RPRST Active, FIFO_CAP --
--RP ++, FIFO_CAP ++
if (RST_node = '1') then
FIFO_pointer <= 0;
elsif (RPRST_node = '1') then
FIFO_pointer <= (CONV_INTEGER(WP_node)+1) * WDATA_WIDTH;
elsif (RP_node'event and not(WP_node'event)) then
FIFO_pointer <= FIFO_pointer - RDATA_WIDTH;
end if;
end process FIFO_CAP_POINTER;
-- READ_POINTER_CTRL_V2 instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL_V2
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_R_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL_V2 instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL_V2
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_W_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC_V2 instance for FIFO
FIFO_FL_INST: FLAG_LOGIC_V2
generic map (
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
GLOBAL_RST => RST_node,
FIFO_CAP => FIFO_capacity,
FIFO_PTR => FIFO_pointer,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_reg,
WDA => DI_reg,
RADA => RP_node,
REA => RE_reg,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_reg,
RADB => RP_node,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- DPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_DP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_DPRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end SC_DPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_DPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CENA_node : STD_LOGIC := 'X';
signal CLKA_node : STD_LOGIC := 'X';
signal WRA_node : STD_LOGIC := 'X';
signal CSA_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTA_node : STD_LOGIC := 'X';
signal DIA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_node : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => '0');
signal DOA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal DIA_reg : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
signal ENA_reg : STD_LOGIC := 'X';
signal RENA_reg : STD_LOGIC := 'X';
signal CENB_node : STD_LOGIC := 'X';
signal CLKB_node : STD_LOGIC := 'X';
signal WRB_node : STD_LOGIC := 'X';
signal CSB_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTB_node : STD_LOGIC := 'X';
signal DIB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_node : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal DOB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal DIB_reg : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal ENB_reg : STD_LOGIC := 'X';
signal RENB_reg : STD_LOGIC := 'X';
signal v_MEM : STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
signal v_ADA : INTEGER;
signal v_ADB : INTEGER;
-- architecture
begin
CENA_node <= CENA;
CLKA_node <= CLKA;
WRA_node <= WRA;
CSA_node <= CSA;
RSTA_node <= RSTA;
DIA_node <= DIA;
ADA_node <= ADA;
-- DOA <= DOA_node;
CENB_node <= CENB;
CLKB_node <= CLKB;
WRB_node <= WRB;
CSB_node <= CSB;
RSTB_node <= RSTB;
DIB_node <= DIB;
ADB_node <= ADB;
-- DOB <= DOB_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(ADA_node, ADB_node)
begin
if (Valid_Address(ADA_node) = TRUE) then
v_ADA <= CONV_INTEGER(ADA_node);
end if;
if (Valid_Address(ADB_node) = TRUE) then
v_ADB <= CONV_INTEGER(ADB_node);
end if;
end process;
-- Register Port A DI/ AD / Enable inputs
register_A_inputs: process (CLKA_node, RSTA_node)
begin
if (RSTA_node = '1') then
DIA_reg <= (others =>'0');
ADA_reg <= (others =>'0');
ENA_reg <= '0';
RENA_reg <= '1';
elsif (CLKA_node'event and CLKA_node = '1') then
if (CENA_node = '1') then
DIA_reg <= DIA_node;
ADA_reg <= ADA_node;
ENA_reg <= WRA_node and CSA_node(0) and CSA_node(1);
RENA_reg <= '1';
end if;
end if;
end process register_A_inputs;
-- Register Port B DI/ AD / Enable inputs
register_B_inputs: process (CLKB_node, RSTB_node)
begin
if (RSTB_node = '1') then
DIB_reg <= (others =>'0');
ADB_reg <= (others =>'0');
ENB_reg <= '0';
RENB_reg <= '1';
elsif (CLKB_node'event and CLKB_node = '1') then
if (CENB_node = '1') then
DIB_reg <= DIB_node;
ADB_reg <= ADB_node;
ENB_reg <= WRB_node and CSB_node(0) and CSB_node(1);
RENB_reg <= '1';
end if;
end if;
end process register_B_inputs;
v_MEM_process: process (CLKA_node, CLKB_node)
begin
if (ENA_reg = '1' and CENA_node = '1') then
if (CLKA_node'event and CLKA_node = '1') then
for i in 0 to DATA_WIDTH_A - 1 loop
v_MEM(v_ADA*DATA_WIDTH_A+i) <= DIA_node(i) after 1 ps;
end loop;
end if;
end if;
if (ENB_reg = '1' and CENB_node = '1') then
if (CLKB_node'event and CLKB_node = '1') then
for i in 0 to DATA_WIDTH_B - 1 loop
v_MEM(v_ADB*DATA_WIDTH_B+i) <= DIB_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DOA_output_process: process (RSTA_node, ENA_reg, CENA_node, DOA_node, CLKA_node)
begin
if (RSTA_node = '1') then
DOA <= (others => '0');
elsif (CLKA_node = '1' and CENA_node = '1') then
if (ENA_reg = '1') then
if (AWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_A - 1 loop
DOA(j) <= v_MEM(v_ADA*DATA_WIDTH_A+j);
end loop;
else
DOA <= DOA_node;
end if;
else
DOA <= DOA_node;
end if;
end if;
end process;
DOB_output_process: process (RSTB_node, ENB_reg, CENB_node, DOB_node, CLKB_node)
begin
if (RSTB_node = '1') then
DOB <= (others => '0');
elsif (CLKB_node = '1' and CENB_node = '1') then
if (ENB_reg = '1') then
if (BWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_B - 1 loop
DOB(j) <= v_MEM(v_ADB*DATA_WIDTH_B+j);
end loop;
else
DOB <= DOB_node;
end if;
else
DOB <= DOB_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
DPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => AWRITE_MODE,
BWRITE_MODE => BWRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH_A,
RADDR_WIDTH_A => ADDR_WIDTH_A,
WADDR_WIDTH_B => ADDR_WIDTH_B,
RADDR_WIDTH_B => ADDR_WIDTH_B,
WDATA_WIDTH_A => DATA_WIDTH_A,
RDATA_WIDTH_A => DATA_WIDTH_A,
WDATA_WIDTH_B => DATA_WIDTH_B,
RDATA_WIDTH_B => DATA_WIDTH_B,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => ADA_reg,
WEA => ENA_reg,
WDA => DIA_reg,
RADA => ADA_reg,
REA => RENA_reg,
RDA => DOA_node,
WADB => ADB_reg,
WEB => ENB_reg,
WDB => DIB_reg,
RADB => ADB_reg,
REB => RENB_reg,
RDB => DOB_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- PseudoDPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_PDP_RAM.vhd
-- Description: Pseudo Dual Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_PDPRAM_16K_L is
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_PDPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_PDPRAM_16K_L is
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
-- Signal Declaration
signal WCEN_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal WE_node : STD_LOGIC := 'X';
signal WCS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RCEN_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal WD_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RD_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal RAD_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WD_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_reg : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RAD_reg : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
WCEN_node <= WCEN;
WCLK_node <= WCLK;
WE_node <= WE;
WCS_node <= WCS;
RCEN_node <= RCEN;
RCLK_node <= RCLK;
RST_node <= RST;
WD_node <= WD;
WAD_node <= WAD;
RAD_node <= RAD;
-- RD <= RD_node;
RD_output : process (RD_node, RST_node)
begin
if (RST_node = '1') then
RD <= (others => '0');
else
RD <= RD_node;
end if;
end process;
-- Register WD/WAD/ Enable inputs
register_write_inputs: process (WCLK_node, RST_node)
begin
if (RST_node = '1') then
WD_reg <= (others =>'0');
WAD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (WCLK_node'event and WCLK_node = '1') then
if (WCEN_node = '1') then
WD_reg <= WD_node;
WAD_reg <= WAD_node;
EN_reg <= WE_node and WCS_node(0) and WCS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_write_inputs;
-- Register RAD inputs
register_read_inputs: process (RCLK_node, RST_node)
begin
if (RST_node = '1') then
RAD_reg <= (others =>'0');
elsif (RCLK_node'event and RCLK_node = '1') then
if (RCEN_node = '1') then
RAD_reg <= RAD_node;
end if;
end if;
end process register_read_inputs;
-- BRAM instance for SPRAM
PDPRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WAD_reg,
WEA => EN_reg,
WDA => WD_reg,
RADA => RAD_reg,
REA => REN_reg,
RDA => RD_node,
WADB => WAD_reg,
WEB => GND_sig,
WDB => WD_reg,
RADB => RAD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- SPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_SP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_SPRAM_16K_L is
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end SC_SPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_SPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CEN_node : STD_LOGIC := 'X';
signal CLK_node : STD_LOGIC := 'X';
signal WR_node : STD_LOGIC := 'X';
signal CS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RST_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_node : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => '0');
signal DO_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_reg : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
signal v_MEM : STD_LOGIC_VECTOR((2**ADDR_WIDTH) * DATA_WIDTH-1 downto 0) := (others => '0');
signal v_AD : integer;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
CEN_node <= CEN;
CLK_node <= CLK;
WR_node <= WR;
CS_node <= CS;
RST_node <= RST;
DI_node <= DI;
AD_node <= AD;
-- DO <= DO_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(AD_node)
begin
if (Valid_Address(AD_node) = TRUE) then
v_AD <= CONV_INTEGER(AD_node);
end if;
end process;
-- Register DI/ AD / Enable inputs
register_inputs: process (CLK_node, RST_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
AD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (CLK_node'event and CLK_node = '1') then
if (CEN_node = '1') then
DI_reg <= DI_node;
AD_reg <= AD_node;
EN_reg <= WR_node and CS_node(0) and CS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_inputs;
v_MEM_process: process (EN_reg, DI_node, v_AD, CLK_node)
begin
if (CLK_node'event and CLK_node = '1') then
if (EN_reg = '1' and CEN_node = '1') then
for i in 0 to DATA_WIDTH - 1 loop
v_MEM(v_AD*DATA_WIDTH+i) <= DI_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DO_output_process: process (RST_node, EN_reg, DO_node, CLK_node)
begin
if (RST_node = '1') then
DO <= (others => '0');
elsif (CLK_node = '1' and CEN_node = '1') then
if (EN_reg = '1') then
if (WRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH - 1 loop
DO(j) <= v_MEM(v_AD*DATA_WIDTH+j);
end loop;
else
DO <= DO_node;
end if;
else
DO <= DO_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
SPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => WRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH,
RADDR_WIDTH_A => ADDR_WIDTH,
WADDR_WIDTH_B => ADDR_WIDTH,
RADDR_WIDTH_B => ADDR_WIDTH,
WDATA_WIDTH_A => DATA_WIDTH,
RDATA_WIDTH_A => DATA_WIDTH,
WDATA_WIDTH_B => DATA_WIDTH,
RDATA_WIDTH_B => DATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => AD_reg,
WEA => EN_reg,
WDA => DI_reg,
RADA => AD_reg,
REA => REN_reg,
RDA => DO_node,
WADB => AD_reg,
WEB => GND_sig,
WDB => DI_reg,
RADB => AD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dc is
generic (
module_type : string := "FIFO_DC";
module_width : integer := 1;
module_widthu : integer := 1;
module_numwords : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_width-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dc;
architecture fun_simulation of fifo_dc is
component SC_FIFO_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal Rst, FullIn, EmptyIn : std_logic;
begin
Rst <= '1';
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_16K_L
generic map (
WADDR_WIDTH => module_widthu,
WDATA_WIDTH => module_width,
RADDR_WIDTH => module_widthu,
RDATA_WIDTH => module_width,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwords - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dcx is
generic (
module_type : string := "FIFO_DCX";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_widthuw : integer := 1;
module_widthur : integer := 1;
module_numwordsw : integer := 2;
module_numwordsr : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_widthw-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dcx;
architecture fun_simulation of fifo_dcx is
component SC_FIFO_V2_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal FullIn, EmptyIn : std_logic;
begin
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_V2_16K_L
generic map (
WADDR_WIDTH => module_widthuw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthur,
RDATA_WIDTH => module_widthr,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwordsw - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp is
generic(
module_type : string := "RAM_DP";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_numwordsw : integer := 1;
module_widthadw : integer := 1;
module_widthadr : integer := 1;
module_numwordsr : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_addressw_control : string := "REGISTERED";
module_addressr_control : string := "REGISTERED";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED";
module_init_file : string := "");
port(
Data : in std_logic_vector (module_widthw-1 downto 0);
WrAddress : in std_logic_vector (module_widthadw-1 downto 0);
RdAddress : in std_logic_vector (module_widthadr-1 downto 0);
WrClock : in std_logic;
WrClockEn : in std_logic;
RdClock : in std_logic;
RdClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0));
end ram_dp;
architecture fun_simulation of ram_dp is
component SC_PDPRAM_16K_L
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal Q_K : std_logic_vector (module_widthr-1 downto 0);
signal Q_K_reg : std_logic_vector (module_widthr-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(RdClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (RdClock'EVENT and RdClock = '1') then
if (RdClockEn = '1') then
Q_K_reg <= Q_K;
elsif (RdClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressw_control = "UNREGISTERED") then
assert false report "Error: module_addressw_control should be REGISTERED" severity ERROR;
elsif(module_addressr_control = "UNREGISTERED") then
assert false report "Error: module_addressr_control should be REGISTERED" severity ERROR;
end if;
end process;
PDPRAM_inst : SC_PDPRAM_16K_L
generic map(
WADDR_WIDTH => module_widthadw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthadr,
RDATA_WIDTH => module_widthr,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsw*module_widthw,
MEM_INIT_FILE => module_init_file)
port map(
WCEN => WrClockEn,
WCLK => WrClock,
WE => WE,
WCS => cs,
RCLK => RdClock,
RCEN => RdClockEn,
RST => Reset,
WD => Data,
WAD => WrAddress,
RAD => RdAddress,
RD => Q_K
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp_true is
generic (
module_type : string := "RAM_DP_TRUE";
module_widtha : positive;
module_widthada : positive;
module_numwordsa : positive;
module_widthb : positive;
module_widthadb : positive;
module_numwordsb : positive;
module_indata : string :="REGISTERED";
module_outdata : string :="UNREGISTERED";
module_addressa_control : string :="REGISTERED";
module_addressb_control : string :="REGISTERED";
module_init_file : string := "";
module_hint : string :="UNUSED";
module_gsr : string := "DISABLED";
module_writemode_a : string := "NORMAL";
module_writemode_b : string := "NORMAL");
port (
DataInA : in std_logic_vector(module_widtha-1 downto 0);
AddressA : in std_logic_vector(module_widthada-1 downto 0);
DataInB : in std_logic_vector(module_widthb-1 downto 0);
AddressB : in std_logic_vector(module_widthadb-1 downto 0);
ClockA : in std_logic := '0';
ClockEnA : in std_logic := '0';
ClockB : in std_logic := '0';
ClockEnB : in std_logic := '0';
WrA : in std_logic;
WrB : in std_logic;
ResetA : in std_logic;
ResetB : in std_logic;
QA : out std_logic_vector(module_widtha-1 downto 0);
QB : out std_logic_vector(module_widthb-1 downto 0));
end ram_dp_true;
architecture fun_simulation of ram_dp_true is
component SC_DPRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 0;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end component;
signal CS : std_logic_vector ( 1 downto 0);
signal QA_int, QA_int_reg : std_logic_vector(module_widtha-1 downto 0);
signal QB_int, QB_int_reg : std_logic_vector(module_widthb-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
CS <= "11";
OutRegisterA : process(ClockA, ResetA)
begin
if(ResetA = '1') then QA_int_reg <= (others => '0');
elsif (ClockA'EVENT and ClockA = '1') then
if (ClockEnA = '1') then
QA_int_reg <= QA_int;
elsif (ClockEnA /= '0') then
QA_int_reg <= (others => 'X');
end if;
end if;
end process;
OutRegisterB : process(ClockB, ResetB)
begin
if(ResetB = '1') then QB_int_reg <= (others => '0');
elsif (ClockB'EVENT and ClockB = '1') then
if (ClockEnB = '1') then
QB_int_reg <= QB_int;
elsif (ClockEnB /= '0') then
QB_int_reg <= (others => 'X');
end if;
end if;
end process;
SelectA : process (QA_int , QA_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int;
elsif(module_outdata = "REGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
SelectB : process (QB_int , QB_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int;
elsif(module_outdata = "REGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int_reg;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
RAM_DP_INST : SC_DPRAM_16K_L
generic map(
ADDR_WIDTH_A => module_widthada,
DATA_WIDTH_A => module_widtha,
ADDR_WIDTH_B => module_widthadb,
DATA_WIDTH_B => module_widthb,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsa*module_widtha,
MEM_INIT_FILE => module_init_file,
AWRITE_MODE => module_writemode_a,
BWRITE_MODE => module_writemode_b
)
port map (
CENA => ClockEnA,
CLKA => ClockA,
WRA => WrA,
CSA => CS,
RSTA => ResetA,
DIA => DataInA,
ADA => AddressA,
DOA => QA_int,
CENB => ClockEnB,
CLKB => ClockB,
WRB => WrB,
CSB => CS,
RSTB => ResetB,
DIB => DataInB,
ADB => AddressB,
DOB => QB_int
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dq is
generic(
module_type : string := "RAM_DQ";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "";
module_hint : string := "UNUSED";
module_gsr : string := "DISABLED";
module_writemode : string := "NORMAL");
port(
Data : in std_logic_vector (module_width-1 downto 0);
Address : in std_logic_vector (module_widthad-1 downto 0);
Clock : in std_logic;
ClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end ram_dq;
architecture fun_simulation of ram_dq is
component SC_SPRAM_16K_L
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector (1 downto 0);
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(Clock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (Clock'EVENT and Clock = '1') then
if (ClockEn = '1') then
Q_K_reg <= Q_K;
elsif (ClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map (
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file,
WRITE_MODE => module_writemode)
port map (
CEN => ClockEn,
CLK => Clock,
WR => WE,
CS => cs,
RST => Reset,
DI => Data,
AD => Address,
DO => Q_K
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity rom is
generic (
module_type : string := "ROM";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_outdata : string := "REGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "init_file";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED");
port (
Address : in std_logic_vector (module_widthad-1 downto 0);
OutClock : in std_logic;
OutClockEn : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end rom;
architecture fun_simulation of rom is
component SC_SPRAM_16K_L
generic (
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal DI_sig : std_logic_vector (module_width-1 downto 0);
signal WE_sig : std_logic;
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
begin
cs <= "11";
WE_sig <= '0';
OutRegister : process(OutClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (OutClock'EVENT and OutClock = '1') then
if(OutClockEn = '1') then
Q_K_reg <= Q_K;
elsif(OutClockEn /= '0') then
Q_K_reg <= (others => 'X' );
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map(
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => 1,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file)
port map(
CEN => OutClockEn,
CLK => OutClock,
WR => WE_sig,
CS => cs,
RST => Reset,
DI => DI_sig,
AD => Address,
DO => Q_K
);
end;
|
gpl-2.0
|
9b0749f54f18924b1b5e918d1c1f5ab3
| 0.502053 | 3.512711 | false | false | false | false |
skrasser/papilio_synth
|
hdl/oscillator.vhd
| 1 | 1,232 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity oscillator is
port (data : out STD_LOGIC_VECTOR(7 downto 0);
freq : in STD_LOGIC_VECTOR(15 downto 0);
waveform : in STD_LOGIC;
clk : in STD_LOGIC
);
end oscillator;
architecture behavioral of oscillator is
component sawtooth
port (data : out STD_LOGIC_VECTOR(7 downto 0);
freq : in STD_LOGIC_VECTOR(15 downto 0);
clk : in STD_LOGIC
);
end component;
signal phase : STD_LOGIC_VECTOR(7 downto 0);
begin
-- use sawtooth to get phase
phasegen: sawtooth
port map(phase, freq, clk);
-- use input to select waveform
process(clk, phase, waveform)
begin
if rising_edge(clk) then -- latched so data is stable
if waveform = '0' then
-- just using phase for raw sawtooth
data <= phase;
else
if phase(7) = '0' then -- first half of sawtooth
-- ramp up at twice the speed
data <= phase(6 downto 0) & '0';
else
-- second half, ramp down
data <= (phase(6 downto 0) xor "1111111") & '0';
end if;
end if;
end if;
end process;
end behavioral;
|
mit
|
f127dc6b2d1535f59a59d4e4401bfe83
| 0.582792 | 3.779141 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-xc2v1500/config.vhd
| 1 | 5,464 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (16);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
1d657fe1d81744521f9cc8440d62bd57
| 0.642936 | 3.659745 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/gr1553b/gr1553b_pads.vhd
| 1 | 5,018 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_pads
-- File: gr1553b_pads.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Pad instantiations for GR1553B
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
library techmap;
use techmap.gencomp.all;
entity gr1553b_pads is
generic (
padtech: integer;
outen_pol: integer range 0 to 1;
level: integer := ttl;
slew: integer := 0;
voltage: integer := x33v;
strength: integer := 12;
filter: integer := 0
);
port (
txout: in gr1553b_txout_type;
rxin: out gr1553b_rxin_type;
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaoutenin : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busboutenin : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_pads is
begin
outin_gen: if outen_pol /= 0 generate
busa_outin_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutenin, txout.busA_txin);
busb_outin_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutenin, txout.busB_txin);
end generate;
outen_gen: if outen_pol = 0 generate
busa_outen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutenin, txout.busA_txen);
busb_outen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutenin, txout.busB_txen);
end generate;
busa_inen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busainen, txout.busA_rxen);
busa_inp_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busainp, rxin.busA_rxP);
busa_inn_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busainn, rxin.busA_rxN);
busa_outp_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutp, txout.busA_txP);
busa_outn_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutn, txout.busA_txN);
busb_inen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busbinen, txout.busB_rxen);
busb_inp_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busbinp, rxin.busB_rxP);
busb_inn_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busbinn, rxin.busB_rxN);
busb_outp_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutp, txout.busB_txP);
busb_outn_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutn, txout.busB_txN);
end;
|
gpl-2.0
|
866ae6e95c5766b58ad37e4c00637037
| 0.600837 | 3.979381 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/ahbrom.vhd
| 3 | 8,224 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800018";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E148";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"10800004";
when 16#00051# => romdata <= X"FD18C000";
when 16#00052# => romdata <= X"00000000";
when 16#00053# => romdata <= X"00000000";
when 16#00054# => romdata <= X"87444000";
when 16#00055# => romdata <= X"8730E01C";
when 16#00056# => romdata <= X"8688E00F";
when 16#00057# => romdata <= X"1280000B";
when 16#00058# => romdata <= X"03200000";
when 16#00059# => romdata <= X"82106300";
when 16#0005A# => romdata <= X"84102052";
when 16#0005B# => romdata <= X"C4206004";
when 16#0005C# => romdata <= X"C4206000";
when 16#0005D# => romdata <= X"C0206008";
when 16#0005E# => romdata <= X"84103FFF";
when 16#0005F# => romdata <= X"C4206014";
when 16#00060# => romdata <= X"84102007";
when 16#00061# => romdata <= X"C4206008";
when 16#00062# => romdata <= X"05000080";
when 16#00063# => romdata <= X"82100000";
when 16#00064# => romdata <= X"80A0E000";
when 16#00065# => romdata <= X"02800005";
when 16#00066# => romdata <= X"01000000";
when 16#00067# => romdata <= X"82004002";
when 16#00068# => romdata <= X"10BFFFFC";
when 16#00069# => romdata <= X"8620E001";
when 16#0006A# => romdata <= X"3D1003FF";
when 16#0006B# => romdata <= X"BC17A3E0";
when 16#0006C# => romdata <= X"BC278001";
when 16#0006D# => romdata <= X"9C27A060";
when 16#0006E# => romdata <= X"03100000";
when 16#0006F# => romdata <= X"81C04000";
when 16#00070# => romdata <= X"01000000";
when 16#00071# => romdata <= X"01000000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
0e2e74318ee7c6eace8450a025e592b9
| 0.580253 | 3.2896 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-jopdesign-ep1c12/config.vhd
| 1 | 7,407 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 2;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 2;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 1;
constant CFG_SRCTRL_PROMWS : integer := (3);
constant CFG_SRCTRL_RAMWS : integer := (2);
constant CFG_SRCTRL_IOWS : integer := (0);
constant CFG_SRCTRL_RMW : integer := 1;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := (19);
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
d1ddf8cc844173788d56ac241c63df9a
| 0.648036 | 3.609649 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/adapters/comma_detect.vhd
| 1 | 5,175 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: comma_detect
-- File: comma_detect.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII' comma detector with bitslip output signal
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
entity comma_detect is
generic (
bsbreak : integer range 0 to 31 := 0; -- number of extra deassertion cycles between bitslip assertions in a sequence
bswait : integer range 0 to 127 := 7 -- number of cycles to pause recognition after a sequence is issued
);
port (
clk : in std_logic;
rstn : in std_logic;
indata : in std_logic_vector(9 downto 0);
bitslip : out std_logic
);
end entity;
architecture arch of comma_detect is
type fsm_state_type is (idle, bitslip1, bitslip2, bitslip3);
type reg_type is record
data : std_logic_vector(19 downto 0);
state : fsm_state_type;
slipcnt : integer range 0 to 15;
slipbreak : integer range 0 to 31;
slipwait : integer range 0 to 127;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := (
data => (others => '0'),
state => idle,
slipcnt => 0,
slipbreak => 0,
slipwait => 0
);
signal r, rin : reg_type;
begin
comb : process( rstn, r, indata )
variable v : reg_type;
--variable vbitslip : std_logic_vector(15 downto 0);
begin
v := r;
v.data(19 downto 10) := r.data(9 downto 0);
v.data(9 downto 0) := indata;
-- -- we match pattern comma+, present in +K.28.x
-- for i in 19 downto 10 loop
-- if r.data(i downto i-6) = "0011111" then
-- vbitslip(9-(i-10)) := '1'; -- unary representation of number of bitslips
-- exit;
-- end if;
-- end loop ;
-- v.slipcnt := unary_to_slv(vbitslip);
case r.state is
when idle =>
-- we match pattern comma+, present in +K.28.x
if r.data(18 downto 12) = "0011111" then
v.slipcnt := 9;
elsif r.data(17 downto 11) = "0011111" then
v.slipcnt := 8;
elsif r.data(16 downto 10) = "0011111" then
v.slipcnt := 7;
elsif r.data(15 downto 9) = "0011111" then
v.slipcnt := 6;
elsif r.data(14 downto 8) = "0011111" then
v.slipcnt := 5;
elsif r.data(13 downto 7) = "0011111" then
v.slipcnt := 4;
elsif r.data(12 downto 6) = "0011111" then
v.slipcnt := 3;
elsif r.data(11 downto 5) = "0011111" then
v.slipcnt := 2;
elsif r.data(10 downto 4) = "0011111" then
v.slipcnt := 1;
else
v.slipcnt := 0;
end if;
if v.slipcnt /= 0 then
v.state := bitslip1;
end if;
when bitslip1 =>
v.slipcnt := r.slipcnt - 1;
v.state := bitslip2;
v.slipbreak := 0;
when bitslip2 =>
if r.slipcnt /= 0 then
if r.slipbreak = bsbreak then
v.state := bitslip1;
else
v.slipbreak := r.slipbreak + 1;
end if;
else
v.slipwait := 0;
v.state := bitslip3;
end if;
when bitslip3 =>
if r.slipwait = bswait then
v.state := idle;
v.data := (others => '0');
else
v.slipwait := r.slipwait + 1;
end if;
when others =>
end case ;
if (not RESET_ALL) and (rstn = '0') then
v.data := (others => '0');
v.state := idle;
end if;
rin <= v;
if r.state = bitslip1 then
bitslip <= '1';
else
bitslip <= '0';
end if;
end process ;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rstn = '0' then
r <= RES;
end if;
end if;
end process;
end architecture ;
|
gpl-2.0
|
af8dc3a4052c0563a74ee2e4276029bb
| 0.558454 | 3.725702 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/apll.vhd
| 4 | 9,287 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC;
phasedone : OUT STD_LOGIC
);
END apll;
ARCHITECTURE SYN OF apll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL scanclk_clk5 : STD_LOGIC ;
signal phasecounter_reg : std_logic_vector(3 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of phasecounter_reg : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of phasecounter_reg : signal is true;
constant period : integer := 1000000/freq;
function set_phase(freq : in integer) return string is
variable s : string(1 to 4) := "0000";
variable f,r : integer;
begin
f := freq;
while f /= 0 loop
r := f mod 10;
case r is
when 0 => s := "0" & s(1 to 3);
when 1 => s := "1" & s(1 to 3);
when 2 => s := "2" & s(1 to 3);
when 3 => s := "3" & s(1 to 3);
when 4 => s := "4" & s(1 to 3);
when 5 => s := "5" & s(1 to 3);
when 6 => s := "6" & s(1 to 3);
when 7 => s := "7" & s(1 to 3);
when 8 => s := "8" & s(1 to 3);
when 9 => s := "9" & s(1 to 3);
when others =>
end case;
f := f / 10;
end loop;
return s;
end function;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 21) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769"), -- 120 & 130 MHz
("1786", "3571", "5357"), ("1667", "3333", "5000"), -- 140 & 150 MHz
("1563", "3125", "4688"), ("1471", "2941", "4412"), -- 160 & 170 MHz
("1389", "2778", "4167"), ("1316", "2632", "3947"), -- 180 & 190 MHz
("1250", "2500", "3750"), ("1190", "2381", "3571")); -- 200 & 210 MHz
--constant pshift_90 : string := phasearr((freq*mult)/(10*div))(1);
constant pshift_90 : string := set_phase(100000/((4*freq*mult)/(10*div)));
--constant pshift_180 : string := phasearr((freq*mult)/(10*div))(2);
constant pshift_180 : string := set_phase(100000/((2*freq*mult)/(10*div)));
--constant pshift_270 : string := phasearr((freq*mult)/(10*div))(3);
constant pshift_270 : string := set_phase(300000/((4*freq*mult)/(10*div)));
constant pshift_rclk : string := set_phase(rskew);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
scanclk_clk5 <= sub_wire0(5);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
locked <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
-- quartus bug, cant be constant
--process(scanclk)
process(scanclk_clk5)
begin
--if rising_edge(scanclk) then
if rising_edge(scanclk_clk5) then -- use ddr clock/2 to not violate 100MHz max freq
phasecounter_reg <= "0110"; --phasecounter;
end if;
end process;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => div,--5,
clk0_duty_cycle => 50,
clk0_multiply_by => mult,--8,
clk0_phase_shift => "0",
clk1_divide_by => div,--5,
clk1_duty_cycle => 50,
clk1_multiply_by => mult,--8,
clk1_phase_shift => pshift_90,--"1250",
clk2_divide_by => div,--5,
clk2_duty_cycle => 50,
clk2_multiply_by => mult,--8,
clk2_phase_shift => pshift_180,--"2500",
clk3_divide_by => div,--5,
clk3_duty_cycle => 50,
clk3_multiply_by => mult,--8,
clk3_phase_shift => pshift_270,--"3750",
clk4_divide_by => div,
clk4_duty_cycle => 50,
clk4_multiply_by => mult,
clk4_phase_shift => pshift_rclk,--"0",
clk5_divide_by => div*2,
clk5_duty_cycle => 50,
clk5_multiply_by => mult,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => period,--8000,
intended_device_family => "Stratix III",
lpm_hint => "CBX_MODULE_PREFIX=apll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_USED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
phasestep => phasestep,
phaseupdown => phaseupdown,
inclk => sub_wire8,
phasecounterselect => phasecounter_reg,
areset => areset,
--scanclk => scanclk,
scanclk => scanclk_clk5,
clk => sub_wire0,
locked => sub_wire6,
phasedone => phasedone
);
END SYN;
|
gpl-2.0
|
30e5a9200abe76e6d5b2721435b215dc
| 0.609669 | 2.741955 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd
| 1 | 9,285 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '1'; -- Reset
signal rstn: std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal clk50 : std_ulogic := '1';
signal clk_200p : std_ulogic := '0';
signal clk_200n : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal eth_macclk, etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal erxdt, etxdt : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
clk50 <= not clk50 after 10 ns;
clk_200p <= not clk_200p after 2.5 ns;
clk_200n <= not clk_200n after 2.5 ns;
rst <= '1', '0' after 1000 ns;
rstn <= not rst;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
clk_50mhz => clk50,
clk_200p => clk_200p,
clk_200n => clk_200n,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
ddr0: ddrram
generic map (width => 16, abits => 13, colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, lddelay => (300 us)*CFG_MIG_DDR2)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 3)
port map(resoutn, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rstn, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
gpl-2.0
|
65f76c7cdd4de3561ada9be55384c7cf
| 0.542488 | 3.411095 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-asic/core.vhd
| 1 | 11,192 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.jtag.all;
use work.config.all;
entity core is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN;
bscanen : integer := CFG_BOUNDSCAN_EN;
oepol : integer := 0
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector (1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
dataen : out std_logic_vector(31 downto 0);
cbin : in std_logic_vector(7 downto 0);
cbout : out std_logic_vector(7 downto 0);
cben : out std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0);
sdwen : out std_ulogic;
sdrasn : out std_ulogic;
sdcasn : out std_ulogic;
sddqm : out std_logic_vector (3 downto 0);
dsutx : out std_ulogic;
dsurx : in std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic;
rxd1 : in std_ulogic;
txd2 : out std_ulogic;
rxd2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : out std_ulogic;
gpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
gpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
gpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
i2c_sclout : out std_ulogic;
i2c_sclen : out std_ulogic;
i2c_sclin : in std_ulogic;
i2c_sdaout : out std_ulogic;
i2c_sdaen : out std_ulogic;
i2c_sdain : in std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector (1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdioin : in std_logic;
emdioout : out std_logic;
emdioen : out std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tdoen : out std_ulogic;
chain_tck : out std_ulogic;
chain_tckn : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic
);
end;
architecture rtl of core is
signal vcc : std_logic_vector(15 downto 0);
signal gnd : std_ulogic;
signal clk1x : std_ulogic;
signal clk2x : std_ulogic;
signal clk4x : std_ulogic;
signal clk8x : std_ulogic;
signal lclk : std_ulogic;
-- signal lclkapb : std_ulogic;
signal lspw_clk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal lgtx_clk : std_ulogic;
signal lerx_clk : std_ulogic;
signal letx_clk : std_ulogic;
signal llock : std_ulogic;
signal scanen : std_ulogic;
signal testrst : std_ulogic;
signal testoen : std_ulogic;
signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
begin
-- Scan test mux logic not connected boundary scan chain
scanen <= dsubre when (testen = '1' and scantest = 1) else '0';
testrst <= dsuen when (testen = '1' and scantest = 1) else '1';
testoen <= dsurx when (testen = '1' and scantest = 1) else '0';
-- PLL for system clock
clkgen0: clkgen
generic map(
tech => CFG_CLKTECH,
clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV,
noclkfb => CFG_CLK_NOFB,
freq => 50000)
port map(
clkin => clk,
pciclkin => clk,
clk => clk1x,
clkn => open,
clk2x => clk2x,
sdclk => open,
pciclk => open,
cgi => cgi,
cgo => cgo,
clk4x => clk4x,
clk1xu => open,
clk2xu => open,
clkb => open,
clkc => open,
clk8x => open);
cgi.pllrst <= resetn;
cgi.pllref <= lclk; -- Note: Used as fbclk if CFG_CLK_NOFB = 0
cgi.clksel <= (others => '0');
-- PLL is bypassed, and disabled, when either testen(0) = 1 or clksel =
-- "00". Bit 0 of pllctrl input is used as the disable signal
cgi.pllctrl(0) <= '1' when (clksel = "00" or (testen = '1' and scantest = 1)) else '0';
cgi.pllctrl(1) <= '0';
-- Simulate lock signal when PLL not used
llock <= '1' when (clksel = "00" or (testen = '1' and scantest = 1)) else cgo.clklock;
lock <= llock;
-- Clock muxing inside boundary scan chain for CORE clock
core_clock_mux : entity work.core_clock_mux
generic map(
tech => fabtech,
scantest => scantest)
port map(
clksel => clksel,
testen => testen,
clkin => clk,
clk1x => clk1x,
clk2x => clk2x,
clk4x => clk4x,
clkout => lclk);
-- Clock muxing inside boundary scan chain for APB CORE clock
--apb_core_clock_mux : entity work.core_clock_mux
-- generic map(
-- tech => fabtech,
-- scantest => scantest)
-- port map(
-- clksel => clksel,
-- testen => testen,
-- clkin => clk,
-- clk1x => clk1x,
-- clk2x => clk1x,
-- clk4x => clk1x,
-- clkout => lclkapb);
-- Clock muxing inside boundary scan chain for SPW clock
spw_core_clock_mux : entity work.core_clock_mux
generic map(
tech => fabtech,
scantest => scantest)
port map(
clksel => spw_clksel,
testen => testen,
clkin => clk,
clk1x => spw_clk,
clk2x => spw_clk,
clk4x => spw_clk,
clkout => lspw_clk);
-- Ethernet Clock Mux for scan test
gtxclkmux : clkmux generic map (tech => fabtech) port map (gtx_clk,clk,testen,lgtx_clk);
rxclkclkmux : clkmux generic map (tech => fabtech) port map (erx_clk,clk,testen,lerx_clk);
txclkclkmux : clkmux generic map (tech => fabtech) port map (etx_clk,clk,testen,letx_clk);
-- Clock outputs
sdclk <= lclk;
-- Control the GPIO direction during test
-- Scantest mode. Lower half of the gpio are scan chain inputs in testmode
-- and upper half of the gpio are outputs, i.e. maximum number of scan
-- chains is the half number of GPIOs
-- Note: testen and testoen should have priority over resetn because the registers
-- in the reset generator are part of the scan chain, and the direction
-- of gpio(23:12) would then depend on the value of a register in the
-- scan chain.
gpioen(CFG_GRGPIO_WIDTH-1 downto (CFG_GRGPIO_WIDTH/2)) <= lgpioen(CFG_GRGPIO_WIDTH-1 downto (CFG_GRGPIO_WIDTH/2))
when (testoen = '0') else (others => '0') when oepol = 1 else (others => '1');
gpioen((CFG_GRGPIO_WIDTH/2)-1 downto 0) <= lgpioen((CFG_GRGPIO_WIDTH/2)-1 downto 0)
when (testoen = '0') else (others => '1') when oepol = 1 else (others => '0');
leon3core0 : entity work.leon3core
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart,
pclow, scantest*(1 - is_fpga(fabtech)))
port map (
resetn, clksel, lclk, lclk, --lclkapb,
llock, errorn,
address, datain, dataout, dataen, cbin, cbout, cben,
sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn,
wdogn, gpioin, gpioout, lgpioen,
i2c_sclout, i2c_sclen, i2c_sclin, i2c_sdaout, i2c_sdaen, i2c_sdain,
spi_miso, spi_mosi, spi_sck, spi_slvsel,
prom32,
spw_clksel,lspw_clk, spw_rxd, spw_rxs, spw_txd, spw_txs,
lgtx_clk, lerx_clk, erxd, erx_dv, letx_clk, etxd, etx_en, etx_er, erx_er, erx_col, erx_crs, emdint, emdioin, emdioout, emdioen, emdc ,
trst, tck, tms, tdi, tdo, tdoen,
scanen, testen, testrst, testoen,
chain_tck, chain_tckn, chain_tdi, chain_tdo,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
end;
|
gpl-2.0
|
3e4f0c358211ea017cf665cd0efe21a2
| 0.577555 | 3.468237 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys4ddr/ahbram_sim.vhd
| 1 | 11,821 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
-- Added Sx-Record read function
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.Numeric_Std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.stdio.all;
library techmap;
use techmap.gencomp.all;
entity ahbram_sim is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram_sim is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
type ram_type is array (0 to (2**ramaddr'length)-1) of std_logic_vector(ramdata'range);
signal ram : ram_type;
signal read_address : std_logic_vector(ramaddr'range);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
-- aram : syncrambw generic map (tech, abits, dw, scantest) port map (
-- clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
RamProc: process(clk) is
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if rising_edge(clk) then
if conv_integer(write) > 0 then
for i in 0 to dw/8-1 loop
if (write(i) = '1') then
ram(to_integer(unsigned(ramaddr)))(i*8+7 downto i*8) <= hwdata(i*8+7 downto i*8);
end if;
end loop;
end if;
read_address <= ramaddr;
end if;
if (rst = '0') and (FIRST = true) then
ram <= (others => (others => '0'));
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits+2) := (others => '0');
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
ram(ai+i) <= recdata((i*32) to (i*32+31));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
end process RamProc;
ramdata <= ram(to_integer(unsigned(read_address)));
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
end;
-- pragma translate_on
|
gpl-2.0
|
91bd0b99723e5ebb3751092284df4c5f
| 0.542847 | 3.424392 | false | false | false | false |
ECE492W2014G4/G4Capstone
|
vhdl_simulation/distortion_component_tb.vhd
| 1 | 2,706 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY distortion_component_tb IS
END distortion_component_tb;
--1111110010011001
--1111101110100100
--1111101110000100
--1111110000111111
--1111110110111000
--1111111110110000
--0000000111001111
--0000001110111000
--0000010100010001
--0000010110010101
--0000010100100000
ARCHITECTURE behavior OF distortion_component_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT distort --'distortion_component' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such.
PORT(
data_in : in std_logic_vector(15 downto 0); -- 16-bit data stream input
dist_en : in std_logic; -- 1-bit distortion enable signal
clipping_value: in std_logic_vector(15 downto 0); -- 16-bit input clipping threshold
clk : in std_logic;
reset : in std_logic;
data_out: out std_logic_vector(15 downto 0) -- 16-bit data stream output (either clipped or not)
);
END COMPONENT;
--declare inputs and initialize them
signal data_in : std_logic_vector(15 downto 0) := "0000000000000000";
signal dist_en : std_logic := '1';
signal clipping_value : std_logic_vector(15 downto 0) := "0000001111101000"; -- Clipped at 1000
signal clk : std_logic := '0';
signal reset : std_logic := '1';
--declare outputs and initialize them
signal data_out: std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
uut: distort PORT MAP (
clk => clk,
reset => reset,
data_in => data_in,
dist_en => dist_en,
clipping_value => clipping_value,
data_out => data_out
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
stim_proc: process
begin
wait for 10 ns;
data_in <="1111110010011001";
wait for 10 ns;
data_in <="1111101110100100";
wait for 10 ns;
data_in <="1111101110000100";
wait for 10 ns;
data_in <="0111110000111111";
wait for 10 ns;
data_in <="1111110110111000";
wait for 10 ns;
data_in <="1111111110110000";
wait for 10 ns;
data_in <="1111110000111111";
wait for 10 ns;
data_in <="0000000111001111";
wait for 10 ns;
data_in <="0000001110111000";
wait for 10 ns;
data_in <="0000010100010001";
wait for 10 ns;
data_in <="0000010110010101";
wait for 10 ns;
data_in <="0000010100100000";
wait for 10 ns;
report "Test bench Complete";
wait;
end process stim_proc;
END behavior;
|
gpl-3.0
|
a0ef9b08f71e6134621e58cad7790434
| 0.663341 | 3.565217 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbtrace.vhd
| 1 | 2,832 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace
-- File: ahbtrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end;
architecture rtl of ahbtrace is
begin
ahbt0 : ahbtrace_mb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
bwidth => bwidth,
ahbfilt => ahbfilt,
scantest => scantest,
exttimer => exttimer,
exten => exten)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmi => ahbmi,
tahbsi => ahbsi,
timer => timer,
astat => astat,
resen => resen);
end;
|
gpl-2.0
|
8961e28b24b556dbd73c5d2631568d28
| 0.558969 | 3.977528 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2sgx90-av/ft245uart.vhd
| 3 | 11,747 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: ft245uart.vhd
-- Authors: Jan Schirok - TU Dresden
-- Description: UART via USB FTDI FT245BL FIFO interface
-- interface: APB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ft245 is
type ft245_in_type is record
rddata : std_logic_vector(7 downto 0); -- data read from ft245
rxfn : std_logic; -- data avail (low active)
txen : std_logic; -- transmit possible (low active)
pwrenn : std_logic; -- dev is active (low active)
end record;
type ft245_out_type is record
wrdata : std_logic_vector(7 downto 0); -- data to ft245
oen : std_logic; -- output enable pad (low active)
rdn : std_logic; -- read enable (low active)
wr : std_logic; -- write enable (high active)
end record;
component ft245uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
use work.ft245.all;
entity ft245uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end;
architecture rtl of ft245uart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- CYCLE DEFINITIONS FOR FT245 COMMUNICATION
--number of counter bits for cycles
constant CYC_WIDTH : integer := 6;
--minimum length of ft245o.rdn pulse
constant RDPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(2, CYC_WIDTH);
--number of clk periods until rddata is valid
constant RDTODATA : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(6, CYC_WIDTH);
--minimum length of ft245o.wr pulse in clk periods
constant WRPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(8, CYC_WIDTH);
--timeout for rdwait/wrwait (cycles to wait for rxfn/txen => '1')
constant TIMEOUT : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(63, CYC_WIDTH);
--zero definition
constant CYNULL : std_logic_vector(CYC_WIDTH-1 downto 0)
:= (CYC_WIDTH-1 downto 0 => '0');
type rxtxfsmtype is (idle, rdact, rddata, rdwait, wrdata, wrwait);
type ft245regs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
loopb : std_ulogic; -- loop back mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
break : std_ulogic; -- break detected (data==0x0, reset in SW)
irq : std_ulogic; -- tx/rx interrupt (internal)
ft245i : ft245_in_type; -- input register
ft245o : ft245_out_type; -- output register
rxtxstate : rxtxfsmtype; -- recv/transmit fsm
-- rcnt : std_logic_vector(0 downto 0);
-- tcnt : std_logic_vector(0 downto 0);
rhold : std_logic_vector(7 downto 0);
thold : std_logic_vector(7 downto 0);
cyclecnt : std_logic_vector(CYC_WIDTH-1 downto 0);
end record;
signal r, rin : ft245regs;
begin
uartop : process(rst, r, apbi )
variable rdata : std_logic_vector(31 downto 0);
-- variable scaler : std_logic_vector(11 downto 0);
-- variable rxclk, txclk : std_logic_vector(2 downto 0);
-- variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddr : std_logic_vector(7 downto 2);
variable v : ft245regs;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- dready := '0'; thempty := '1';
-- dready := r.rcnt(0); --rfull := dready; tfull := r.tcnt(0);
-- thempty := not r.tcnt(0);
--thempty := not tfull;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddr(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold;
v.rsempty := '1';
-- v.rcnt(0) := '0';
when "000001" =>
rdata(3 downto 0) := r.break & r.tsempty & r.tsempty & not(r.rsempty); --fifo==shiftreg
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
--no fifo => rdata(31)='0'
rdata(7) := r.loopb;
rdata(3 downto 0) := r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
-- no scaler
null;
when "000100" =>
-- no debug
null;
when others =>
null;
end case;
end if;
paddr := "000000"; paddr(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddr(7 downto 2) is
when "000000" =>
v.thold := apbi.pwdata(7 downto 0);
v.tsempty := '0';
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when "000001" =>
v.break := apbi.pwdata(3);
when "000010" =>
v.loopb := apbi.pwdata(7);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
when "000100" =>
when others =>
null;
end case;
end if;
-- FSM
case r.rxtxstate is
when idle =>
-- loopback mode, rx/tx active, recv buf empty, send buf full
if r.loopb = '1' and r.rxen = '1' and r.txen = '1' and
r.rsempty = '1' and r.tsempty = '0' then
v.rxtxstate := idle; -- loop back in one cycle
v.rhold := r.thold; -- copy transmit byte in recv buf
v.rsempty := '0';
v.tsempty := '1';
-- something to recv, recv enabled, recv hold reg empty
elsif r.ft245i.rxfn = '0' and r.rxen = '1' and r.rsempty = '1' then
v.rxtxstate := rdact;
v.cyclecnt := RDTODATA;
v.ft245o.oen := '1'; -- pad oen deact
v.ft245o.rdn := '0'; -- read enable
-- external send fifo not full, send enabled, send reg not empty
elsif r.ft245i.txen = '0' and r.txen = '1' and r.tsempty = '0' then
v.rxtxstate := wrdata;
v.cyclecnt := WRPULSE;
v.ft245o.wr := '1';
v.ft245o.oen := '0'; -- pad oen act
v.ft245o.wrdata := r.thold;
v.tsempty := '1';
if r.tirqen = '1' then
v.irq := '1';
end if;
end if;
when rdact =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rddata;
--rdn stays low
v.cyclecnt := RDPULSE;
end if;
when rddata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rdwait;
v.rsempty := '0';
if r.rirqen = '1' then
v.irq := '1'; -- irq if enabled
end if;
v.rhold := r.ft245i.rddata;
if r.ft245i.rddata = "00000000" then
v.break := '1';
end if;
v.ft245o.rdn := '1'; -- deactivate
v.cyclecnt := TIMEOUT;
end if;
when rdwait =>
v.cyclecnt := r.cyclecnt - 1;
-- value read or timeout
if v.ft245i.rxfn = '1' or v.cyclecnt = CYNULL then
v.rxtxstate := idle;
end if;
when wrdata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := wrwait;
v.cyclecnt := TIMEOUT;
v.ft245o.wr := '0';
end if;
when wrwait =>
v.cyclecnt := r.cyclecnt - 1;
--either tx byte accepted or timeout
if r.ft245i.txen = '1' or r.cyclecnt = CYNULL then
v.rxtxstate := idle;
v.ft245o.oen := '1'; -- output pad deact
v.tsempty := '1';
end if;
end case;
-- reset if no power enable at ft245
if r.ft245i.pwrenn = '1' then
v.rxtxstate := idle;
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rsempty := '1'; v.tsempty := '1';
v.irq := '0';
end if;
-- reset operation
if rst = '0' then
v.rxen := '0'; v.txen := '0';
v.rirqen := '0'; v.tirqen := '0';
v.loopb := '0';
v.rsempty := '1'; v.tsempty := '1';
v.break := '0';
v.irq := '0';
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rxtxstate := idle;
v.rhold := (others => '0');
v.thold := (others => '0');
v.cyclecnt := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
ft245o <= r.ft245o;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
r.ft245i <= ft245i;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": FT245 UART rev " & tost(REVISION) & ", no fifo " &
", irq " & tost(pirq));
-- pragma translate_on
end;
|
gpl-2.0
|
53263a4c85a3f25f5cbcbe246edbe230
| 0.564995 | 3.341013 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/virage/memory_virage.vhd
| 1 | 16,189 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_virage_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Virage rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss1_128x32cm4sw0ab;
use virage.hdss1_256x32cm4sw0ab;
use virage.hdss1_512x32cm4sw0ab;
use virage.hdss1_512x38cm4sw0ab;
use virage.hdss1_1024x32cm4sw0ab;
use virage.hdss1_2048x32cm8sw0ab;
use virage.hdss1_4096x36cm8sw0ab;
use virage.hdss1_16384x8cm16sw0;
-- pragma translate_on
entity virage_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of virage_syncram is
component hdss1_128x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_256x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x38cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_1024x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_2048x32cm8sw0ab
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(40 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc : std_ulogic;
constant synopsys_bug : std_logic_vector(40 downto 0) := (others => '0');
begin
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(40 downto dbits) <= synopsys_bug(40 downto dbits);
dataout <= q(dbits -1 downto 0);
a7d32 : if (abits <= 7) and (dbits <= 32) generate
id0 : hdss1_128x32cm4sw0ab
port map (a(6 downto 0), gnd(6 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss1_256x32cm4sw0ab
port map (a(7 downto 0), gnd(7 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss1_512x32cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss1_512x38cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(37 downto 0), gnd(37 downto 0), q(37 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a10d32 : if (abits = 10) and (dbits <= 32) generate
id0 : hdss1_1024x32cm4sw0ab
port map (address(9 downto 0), gnd(9 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a11d32 : if (abits = 11) and (dbits <= 32) generate
id0 : hdss1_2048x32cm8sw0ab
port map (address(10 downto 0), gnd(10 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a12d36 : if (abits = 12) and (dbits <= 36) generate
id0 : hdss1_4096x36cm8sw0ab
port map (address(11 downto 0), gnd(11 downto 0), clk,
d(35 downto 0), gnd(35 downto 0), q(35 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a14d8 : if (abits = 14) and (dbits <= 8) generate
id0 : hdss1_16384x8cm16sw0
port map (address(13 downto 0), clk,
d(7 downto 0), q(7 downto 0),
enable, vcc, Write);
end generate;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_512x38cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_dp is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of virage_syncram_dp is
component hdss2_64x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_128x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_256x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x38cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_8192x8cm16sw0ab
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, d2, a1, a2, q1, q2, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain1; d1(40 downto dbits) <= (others => '0');
d2(dbits-1 downto 0) <= datain2; d2(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address2; a2(40 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); dataout2 <= q2(dbits-1 downto 0);
a6d32 : if (abits <= 6) and (dbits <= 32) generate
id0 : hdss2_64x32cm4sw0ab
port map (a1(5 downto 0), gnd(5 downto 0), a2(5 downto 0),
gnd(5 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a7d32 : if (abits = 7) and (dbits <= 32) generate
id0 : hdss2_128x32cm4sw0ab
port map (a1(6 downto 0), gnd(6 downto 0), a2(6 downto 0),
gnd(6 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss2_256x32cm4sw0ab
port map (a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0),
gnd(7 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss2_512x32cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss2_512x38cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(37 downto 0), gnd(37 downto 0), d2(37 downto 0), gnd(37 downto 0),
q1(37 downto 0), q2(37 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.rfss2_136x32cm2sw0ab;
use virage.rfss2_136x40cm2sw0ab;
use virage.rfss2_168x32cm2sw0ab;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_2p is
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture rtl of virage_syncram_2p is
component rfss2_136x32cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
component rfss2_136x40cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, a1, a2, q1, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain; d1(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddress; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddress; a2(40 downto abits) <= (others => '0');
dataout <= q1(dbits-1 downto 0);
id0 : rfss2_136x40cm2sw0ab
port map (
a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0), gnd(7 downto 0),
wclk, rclk, d1(39 downto 0), gnd(39 downto 0),
q1(39 downto 0),
vcc, write, gnd(0), gnd(0), gnd(0),
renable, vcc, gnd(0), gnd(0), gnd(0), gnd(0));
end;
|
gpl-2.0
|
b7a047f595ed198df0bb736708571dac
| 0.62141 | 2.916411 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-asic/bschain.vhd
| 1 | 11,945 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013, Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.jtag.all;
use work.config.all;
entity bschain is
generic (tech: integer := CFG_FABTECH;
enable: integer range 0 to 1 := CFG_BOUNDSCAN_EN;
hzsup: integer range 0 to 1 := 1);
port (
-- Chain control signals
chain_tck : in std_ulogic;
chain_tckn : in std_ulogic;
chain_tdi : in std_ulogic;
chain_tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
-- Pad-side signals
Presetn : in std_ulogic;
Pclksel : in std_logic_vector (1 downto 0);
Pclk : in std_ulogic;
Perrorn : out std_ulogic;
Paddress : out std_logic_vector(27 downto 0);
Pdatain : in std_logic_vector(31 downto 0);
Pdataout : out std_logic_vector(31 downto 0);
Pdataen : out std_logic_vector(31 downto 0);
Pcbin : in std_logic_vector(7 downto 0);
Pcbout : out std_logic_vector(7 downto 0);
Pcben : out std_logic_vector(7 downto 0);
Psdclk : out std_ulogic;
Psdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
Psdwen : out std_ulogic; -- sdram write enable
Psdrasn : out std_ulogic; -- sdram ras
Psdcasn : out std_ulogic; -- sdram cas
Psddqm : out std_logic_vector (3 downto 0); -- sdram dqm
Pdsutx : out std_ulogic; -- DSU tx data
Pdsurx : in std_ulogic; -- DSU rx data
Pdsuen : in std_ulogic;
Pdsubre : in std_ulogic;
Pdsuact : out std_ulogic;
Ptxd1 : out std_ulogic; -- UART1 tx data
Prxd1 : in std_ulogic; -- UART1 rx data
Ptxd2 : out std_ulogic; -- UART2 tx data
Prxd2 : in std_ulogic; -- UART2 rx data
Pramsn : out std_logic_vector (4 downto 0);
Pramoen : out std_logic_vector (4 downto 0);
Prwen : out std_logic_vector (3 downto 0);
Poen : out std_ulogic;
Pwriten : out std_ulogic;
Pread : out std_ulogic;
Piosn : out std_ulogic;
Promsn : out std_logic_vector (1 downto 0);
Pbrdyn : in std_ulogic;
Pbexcn : in std_ulogic;
Pwdogn : out std_ulogic;
Pgpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pprom32 : in std_ulogic;
Ppromedac : in std_ulogic;
Pspw_clksel : in std_logic_vector (1 downto 0);
Pspw_clk : in std_ulogic;
Pspw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_ten : out std_logic_vector(0 to CFG_SPW_NUM-1);
Plclk2x : in std_ulogic;
Plclk4x : in std_ulogic;
Plclkdis : out std_ulogic;
Plclklock : in std_ulogic;
Plock : out std_ulogic;
Proen : in std_ulogic;
Proout : out std_ulogic;
-- Core-side signals
Cresetn : out std_ulogic;
Cclksel : out std_logic_vector (1 downto 0);
Cclk : out std_ulogic;
Cerrorn : in std_ulogic;
Caddress : in std_logic_vector(27 downto 0);
Cdatain : out std_logic_vector(31 downto 0);
Cdataout : in std_logic_vector(31 downto 0);
Cdataen : in std_logic_vector(31 downto 0);
Ccbin : out std_logic_vector(7 downto 0);
Ccbout : in std_logic_vector(7 downto 0);
Ccben : in std_logic_vector(7 downto 0);
Csdclk : in std_ulogic;
Csdcsn : in std_logic_vector (1 downto 0); -- sdram chip select
Csdwen : in std_ulogic; -- sdram write enable
Csdrasn : in std_ulogic; -- sdram ras
Csdcasn : in std_ulogic; -- sdram cas
Csddqm : in std_logic_vector (3 downto 0); -- sdram dqm
Cdsutx : in std_ulogic; -- DSU tx data
Cdsurx : out std_ulogic; -- DSU rx data
Cdsuen : out std_ulogic;
Cdsubre : out std_ulogic;
Cdsuact : in std_ulogic;
Ctxd1 : in std_ulogic; -- UART1 tx data
Crxd1 : out std_ulogic; -- UART1 rx data
Ctxd2 : in std_ulogic; -- UART2 tx data
Crxd2 : out std_ulogic; -- UART2 rx data
Cramsn : in std_logic_vector (4 downto 0);
Cramoen : in std_logic_vector (4 downto 0);
Crwen : in std_logic_vector (3 downto 0);
Coen : in std_ulogic;
Cwriten : in std_ulogic;
Cread : in std_ulogic;
Ciosn : in std_ulogic;
Cromsn : in std_logic_vector (1 downto 0);
Cbrdyn : out std_ulogic;
Cbexcn : out std_ulogic;
Cwdogn : in std_ulogic;
Cgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cprom32 : out std_ulogic;
Cpromedac : out std_ulogic;
Cspw_clksel : out std_logic_vector (1 downto 0);
Cspw_clk : out std_ulogic;
Cspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_ten : in std_logic_vector(0 to CFG_SPW_NUM-1);
Clclk2x : out std_ulogic;
Clclk4x : out std_ulogic;
Clclkdis : in std_ulogic;
Clclklock : out std_ulogic;
Clock : in std_ulogic;
Croen : out std_ulogic;
Croout : in std_ulogic
);
end;
architecture rtl of bschain is
signal sr1_tdi, sr1a_tdi, sr2a_tdi, sr2_tdi, sr3a_tdi, sr3_tdi, sr4_tdi: std_ulogic;
signal sr1i, sr1o: std_logic_vector(4 downto 0);
signal sr3i, sr3o: std_logic_vector(41 downto 0);
signal sr5i, sr5o: std_logic_vector(11+5*CFG_SPW_NUM downto 0);
begin
-----------------------------------------------------------------------------
-- Scan chain registers (note: adjust order to match pad ring)
sr1a: bscanregs
generic map (tech => tech, nsigs => sr1i'length, dirmask => 2#00001#, enable => enable)
port map (sr1i, sr1o, chain_tck, chain_tckn, sr1a_tdi, chain_tdo,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr1i <= Presetn & Pclksel & Pclk & Cerrorn;
Cresetn <= sr1o(4); Cclksel <= sr1o(3 downto 2);
Cclk <= sr1o(1); Perrorn <= sr1o(0);
sr1b: bscanregs
generic map (tech => tech, nsigs => Paddress'length, dirmask => 16#3FFFFFFF#, enable => enable)
port map (Caddress, Paddress, chain_tck, chain_tckn, sr1_tdi, sr1a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2a: bscanregsbd
generic map (tech => tech, nsigs => Pdataout'length, enable => enable, hzsup => hzsup)
port map (Pdataout, Pdataen, Pdatain, Cdataout, Cdataen, Cdatain,
chain_tck, chain_tckn, sr2a_tdi, sr1_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2b: bscanregsbd
generic map (tech => tech, nsigs => Pcbout'length, enable => enable, hzsup => hzsup)
port map (Pcbout, Pcben, Pcbin, Ccbout, Ccben, Ccbin,
chain_tck, chain_tckn, sr2_tdi, sr2a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3a: bscanregs
generic map (tech => tech, nsigs => sr3i'length-30, dirmask => 2#11_11111111_10#, enable => enable)
port map (sr3i(sr3i'high downto 30), sr3o(sr3i'high downto 30), chain_tck, chain_tckn, sr3a_tdi, sr2_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3b: bscanregs
generic map (tech => tech, nsigs => 30, dirmask => 2#001101_01111111_11111111_11111001#, enable => enable)
port map (sr3i(29 downto 0), sr3o(29 downto 0), chain_tck, chain_tckn, sr3_tdi, sr3a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3i(41 downto 30) <= Csdclk & Csdcsn & Csdwen & Csdrasn & Csdcasn &
Csddqm & Cdsutx & Pdsurx;
sr3i(29 downto 23) <= Pdsuen & Pdsubre & Cdsuact & Ctxd1 & Prxd1 & Ctxd2 & Prxd2;
sr3i(22 downto 9) <= Cramsn & Cramoen & Crwen;
sr3i(8 downto 0) <= Coen & Cwriten & Cread & Ciosn & Cromsn(1 downto 0) & Pbrdyn & Pbexcn & Cwdogn;
Psdclk <= sr3o(41); Psdcsn <= sr3o(40 downto 39); Psdwen <= sr3o(38);
Psdrasn <= sr3o(37); Psdcasn <= sr3o(36); Psddqm <= sr3o(35 downto 32);
Pdsutx <= sr3o(31); Cdsurx <= sr3o(30); Cdsuen <= sr3o(29);
Cdsubre <= sr3o(28); Pdsuact <= sr3o(27); Ptxd1 <= sr3o(26);
Crxd1 <= sr3o(25); Ptxd2 <= sr3o(24); Crxd2 <= sr3o(23);
Pramsn <= sr3o(22 downto 18); Pramoen <= sr3o(17 downto 13); Prwen <= sr3o(12 downto 9);
Poen <= sr3o(8); Pwriten <= sr3o(7); Pread <= sr3o(6);
Piosn <= sr3o(5); Promsn <= sr3o(4 downto 3); Cbrdyn <= sr3o(2);
Cbexcn <= sr3o(1); Pwdogn <= sr3o(0);
sr4: bscanregsbd
generic map (tech => tech, nsigs => Pgpioin'length, enable => enable, hzsup => hzsup)
port map (Pgpioout, Pgpioen, Pgpioin, Cgpioout, Cgpioen, Cgpioin,
chain_tck, chain_tckn, sr4_tdi, sr3_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5: bscanregs
generic map (tech => tech, nsigs => sr5i'length, dirmask => 2#00000011_10010101#, enable => enable)
port map (sr5i, sr5o, chain_tck, chain_tckn, chain_tdi, sr4_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5i <= Pprom32 & Ppromedac & Pspw_clksel & Pspw_clk & Pspw_rxd & Pspw_rxs &
Cspw_txd & Cspw_txs & Cspw_ten & Plclk2x & Plclk4x &
Clclkdis & Plclklock & Clock & Proen & Croout;
Cprom32 <= sr5o(11+5*CFG_SPW_NUM);
Cpromedac <= sr5o(10+5*CFG_SPW_NUM);
Cspw_clksel <= sr5o(9+5*CFG_SPW_NUM downto 8+5*CFG_SPW_NUM);
Cspw_clk <= sr5o(7+5*CFG_SPW_NUM);
Cspw_rxd <= sr5o(6+5*CFG_SPW_NUM downto 7+4*CFG_SPW_NUM);
Cspw_rxs <= sr5o(6+4*CFG_SPW_NUM downto 7+3*CFG_SPW_NUM);
Pspw_txd <= sr5o(6+3*CFG_SPW_NUM downto 7+2*CFG_SPW_NUM);
Pspw_txs <= sr5o(6+2*CFG_SPW_NUM downto 7+CFG_SPW_NUM);
Pspw_ten <= sr5o(6+CFG_SPW_NUM downto 7);
Clclk2x <= sr5o(6);
Clclk4x <= sr5o(5);
Plclkdis <= sr5o(4);
Clclklock <= sr5o(3);
Plock <= sr5o(2);
Croen <= sr5o(1);
Proout <= sr5o(0);
end;
|
gpl-2.0
|
b5daf4424bd347f24aa493db98115942
| 0.585852 | 3.047194 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/mmu_icache.vhd
| 1 | 29,875 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_icache
-- File: mmu_icache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.leon3.all;
entity mmu_icache is
generic (
memtech : integer := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 1 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#;
mmuen : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_ulogic;
mmudci : in mmudc_in_type;
mmuici : out mmuic_in_type;
mmuico : in mmuic_out_type
);
end;
architecture rtl of mmu_icache is
constant MUXDATA : boolean := (is_fpga(memtech) = 1);
constant M_EN : boolean := (mmuen = 1);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '1');
constant fline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '0');
constant SETBITS : integer := log2x(ISETS);
constant ILRUBITS : integer := lru_table(ISETS);
constant LRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant LRAM_BITS : integer := log2(lramsize) + 10;
constant LRAMCS_EN : boolean := false;
subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0);
type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers
type rdatatype is (itag, idata, memory); -- sources during cache read
type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type;
type valid_type is array (0 to ISETS-1) of std_logic_vector(ilinesize - 1 downto 0);
subtype lock_type is std_logic_vector(0 to ISETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to ISETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(ILRUBITS-1 downto 0) := lru;
if isetlock = 1 then
unlocked := ISETS-1;
for i in ISETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case ISETS is
when 2 =>
if isetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset : std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru;
case ISETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(ILRUBITS-1 downto 0);
return(new_lru);
end;
type istatetype is (idle, trans, streaming, stop);
type icache_control_type is record -- all registers
req, burst, holdn : std_ulogic;
overrun : std_ulogic;
underrun : std_ulogic;
istate : istatetype; -- FSM vector
waddress : std_logic_vector(31 downto 2); -- write address buffer
vaddress : std_logic_vector(31 downto 2); -- virtual address buffer
valid : valid_type; --std_logic_vector(ilinesize-1 downto 0); -- valid bits
hit : std_ulogic;
su : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_ulogic;
rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter
lrr : std_ulogic;
setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
diagset : std_logic_vector(log2x(ISETS)-1 downto 0);
lock : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
cache : std_logic;
trans_op : std_logic;
cmiss : std_ulogic;
bpmiss : std_ulogic;
eocl : std_ulogic;
end record;
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(IOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1;
lru : lru_array;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : icache_control_type := (
req => '0',
burst => '0',
holdn => '1',
overrun => '0',
underrun => '0',
istate => idle,
waddress => (others => '0'), -- has special handling
vaddress => (others => '0'), -- has special handling
valid => (others => (others => '0')),
hit => '0',
su => '0',
flush => '0',
flush2 => '0',
faddr => (others => '0'),
diagrdy => '0',
rndcnt => (others => '0'),
lrr => '0',
setrepl => (others => '0'),
diagset => (others => '0'),
lock => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
cache => '0',
trans_op => '0',
cmiss => '0',
bpmiss => '0',
eocl => '0'
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : icache_control_type; -- r is registers, c is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant icfg : std_logic_vector(31 downto 0) :=
cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0,
lram, lramsize, lramstart, mmuen);
begin
ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn, mmuico, mmudci)
variable rdatasel : rdatatype;
variable twrite, diagen, dwrite : std_ulogic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : cdatatype;
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw : std_logic_vector((ilinesize -1) downto 0);
variable vmask : valid_type;
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_ulogic;
variable enable : std_ulogic;
variable error : std_ulogic;
variable whit, hit, valid, nvalid : std_ulogic;
variable cacheon : std_ulogic;
variable v : icache_control_type;
variable branch : std_ulogic;
variable eholdn : std_ulogic;
variable mds, write : std_ulogic;
variable memaddr : std_logic_vector(31 downto 2);
variable set : integer range 0 to MAXSETS-1;
variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
variable ctwrite, cdwrite, validv, nvalidv : std_logic_vector(0 to MAXSETS-1);
variable wlrr : std_ulogic;
variable vl : lru_reg_type;
variable vdiagset, rdiagset : integer range 0 to ISETS-1;
variable lock : std_logic_vector(0 to ISETS-1);
variable wlock : std_ulogic;
variable tag : cdatatype;
variable lramacc, ilramwr, lramcs : std_ulogic;
variable pftag : std_logic_vector(31 downto 2);
variable mmuici_trans_op : std_logic;
variable mmuici_su : std_logic;
variable mhold : std_ulogic;
variable shtag : std_logic_vector(ilinesize-1 downto 0);
begin
-- init local variables
v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl;
vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW);
v.cmiss := '0'; mhold := '0';
mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
if icen /= 0 then
cacheon := dco.icdiag.cctrl.ics(0) and not (r.flush
);
else cacheon := '0'; end if;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
wtag(TAG_HIGH downto TAG_LOW) := r.vaddress(TAG_HIGH downto TAG_LOW);
wlrr := r.lrr; wlock := r.lock;
set := 0; ctwrite := (others => '0'); cdwrite := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0'); ilramwr := '0';
lramacc := '0'; lramcs := '0';
vdiagset := 0; rdiagset := 0; lock := (others => '0');
pftag := (others => '0'); validv := (others => '0');
v.trans_op := r.trans_op and (not mmuico.grant);
mmuici_trans_op := r.trans_op;
mmuici_su := ici.su;
-- random replacement counter
if ISETS > 1 then
if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
if isetlock = 1 then
for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop;
end if;
--local ram access
if (lram = 1) and (ici.fpc(31 downto 24) = LRAM_START) then lramacc := '1'; end if;
-- generate cache hit and valid bits
hit := '0';
if irepl = dir then
set := conv_integer(ici.fpc(OFFSET_HIGH + SETBITS downto OFFSET_HIGH+1));
if (icramo.tag(set)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(set) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN)
then hit := not r.flush; end if;
validv(set) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(set)(ilinesize -1 downto 0));
else
for i in ISETS-1 downto 0 loop
if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(i) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN)
then hit := not r.flush; set := i; end if;
validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(i)(ilinesize -1 downto 0));
end loop;
end if;
for i in ISETS-1 downto 0 loop
shtag := (others => '0');
shtag(ilinesize-2 downto 0) := icramo.tag(i)(ilinesize-1 downto 1);
nvalidv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW), shtag);
end loop;
if (lramacc = '1') and (ISETS > 1) then set := 1; end if;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
valid := validv(set);
nvalid := nvalidv(set);
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
xaddr_inc := r.vaddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.vaddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main state machine
case r.istate is
when idle => -- main state and cache hit
for i in 0 to ISETS-1 loop
v.valid(i) := icramo.tag(i)(ilinesize-1 downto 0);
end loop;
--v.hit := '0';
v.hit := hit;
v.su := ici.su;
-- if (ici.inull or eholdn) = '0' then
if eholdn = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := dco.icdiag.cctrl.burst and not lastline;
if (eholdn and not (ici.inull or lramacc)) = '1' then
v.bpmiss := not (cacheon and hit and valid) and ici.nobpmiss;
v.eocl := not nvalid;
if not (cacheon and hit and valid) = '1' and ici.nobpmiss='0' then
v.istate := streaming;
v.holdn := '0'; v.overrun := '1'; v.cmiss := '1';
if M_EN and (mmudci.mmctrl1.e = '1') then
v.istate := trans;
mmuici_trans_op := '1';
v.trans_op := not mmuico.grant;
v.cache := '0';
--v.req := '0';
else
v.req := '1';
v.cache := '1';
end if;
else
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
v.waddress := ici.fpc(31 downto 2);
v.vaddress := ici.fpc(31 downto 2);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
if (ISETS > 1) then
if (irepl = lru) then
vl.set := conv_std_logic_vector(set, SETBITS);
vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW);
end if;
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (((not hit) and (not r.flush)) = '1') then
case irepl is
when rnd =>
if isetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS);
for i in ISETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := ici.fpc(OFFSET_HIGH+SETBITS downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1));
when lrr =>
v.setrepl := (others => '0');
if isetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS);
else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if;
end case;
end if;
if (isetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
when trans =>
if M_EN then
v.holdn := '0';
if (mmuico.transdata.finish = '1') then
if mmuico.transdata.accexc = '1' then
-- if su then always do mexc
error := r.su or not mmudci.mmctrl1.nf; mds := '0';
v.holdn := '0'; v.istate := stop; v.burst := '0';
else
v.cache := mmuico.transdata.cache;
v.waddress := mmuico.transdata.data(31 downto 2);
v.istate := streaming; v.req := '1';
end if;
end if;
mhold := '1';
end if;
when streaming => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.vaddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.inull)) and
not (write or r.underrun);
if mcio.ready = '1' then
-- mds := not (v.overrun and not r.underrun);
mds := not (r.overrun and not r.underrun);
-- v.req := r.burst;
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
if mcio.grant = '1' then
v.req := dco.icdiag.cctrl.burst and r.burst and
(not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and
not (v.underrun and not cacheon);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
v.istate := stop; v.holdn := '0';
end if;
when stop => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := idle; v.flush := r.flush2;
when others => v.istate := idle;
end case;
if mcio.retry = '1' then v.req := '1'; end if;
if lram = 1 then
if LRAMCS_EN then
if taddr(31 downto 24) = LRAM_START then lramcs := '1'; else lramcs := '0'; end if;
else
lramcs := '1';
end if;
end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := write;
if cacheon = '0' then
twrite := '0'; vmask := (others => (others => '0'));
elsif (dco.icdiag.cctrl.ics = "01") then
twrite := twrite and r.hit;
for i in 0 to ISETS-1 loop
vmask(i) := icramo.tag(i)(ilinesize-1 downto 0) or vmaskraw;
end loop;
else
for i in 0 to ISETS-1 loop
if r.hit = '1' then vmask(i) := r.valid(i) or vmaskraw;
else vmask(i) := vmaskraw; end if;
end loop;
end if;
if (mcio.mexc or not mcio.cache) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then
v.valid := vmask; v.hit := '1';
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
if (ISETS > 1) and (irepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
-- cache write signals
if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if;
if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if;
-- diagnostic cache access
if diagen = '1' then
if (ISETS /= 1) then
if (dco.icdiag.ilramen = '1') and (lram = 1) then
v.diagset := conv_std_logic_vector(1, SETBITS);
else
v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW);
end if;
end if;
end if;
case ISETS is
when 1 =>
vdiagset := 0; rdiagset := 0;
when 3 =>
if conv_integer(v.diagset) < 3 then vdiagset := conv_integer(v.diagset); end if;
if conv_integer(r.diagset) < 3 then rdiagset := conv_integer(r.diagset); end if;
when others =>
vdiagset := conv_integer(v.diagset);
rdiagset := conv_integer(r.diagset);
end case;
diagdata := icramo.data(rdiagset);
if diagen = '1' then -- diagnostic or local ram access
taddr(TAG_HIGH downto LINE_LOW) := dco.icdiag.addr(TAG_HIGH downto LINE_LOW);
wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW);
wlrr := dci.maddress(CTAG_LRRPOS);
wlock := dci.maddress(CTAG_LOCKPOS);
if (dco.icdiag.ilramen = '1') and (lram = 1) then
ilramwr := not dco.icdiag.read;
elsif dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
ctwrite := (others => '0'); cdwrite := (others => '0');
ctwrite(vdiagset) := not dco.icdiag.read;
diagdata := icramo.tag(rdiagset);
else
dwrite := not dco.icdiag.read; twrite := '0';
cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read;
ctwrite := (others => '0');
end if;
vmask := (others => dci.maddress(ilinesize -1 downto 0));
v.diagrdy := '1';
end if;
-- select data to return on read access
rdata := icramo.data;
case rdatasel is
when memory => rdata(0) := mcio.data; set := 0;
when others =>
end case;
if MUXDATA then
rdata(0) := rdata(set); set := 0;
end if;
-- cache flush
if ((ici.flush or
dco.icdiag.flush) = '1') and (icen /= 0)
then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
v.pflush := dco.icdiag.pflush; wtag := (others => '0');
v.pflushr := '1';
v.pflushaddr := dco.icdiag.pflushaddr;
v.pflushtyp := dco.icdiag.pflushtyp;
end if;
if (r.flush2 = '1') and (icen /= 0) then
twrite := '1'; ctwrite := (others => '1'); vmask := (others => (others => '0'));
v.faddr := r.faddr + 1;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := '0'; wlock := '0'; wtag := (others => '0'); v.lrr := '0';
if ((r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1))
) = '1' then
v.flush2 := '0';
end if;
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
v.pflushr := not r.pflushr;
if r.pflushr = '0' then
for i in ISETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := icramo.tag(i)(TAG_HIGH downto TAG_LOW); --icramo.itramout(i).tag;
--if (icramo.itramout(i).ctx = mmudci.mmctrl1.ctx) and
-- ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
-- (r.pflushtyp = '1')) then
ctwrite(i) := '1';
--end if;
end loop;
end if;
end if;
end if;
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.istate := idle; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0';
v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0');
v.diagset := (others => '0'); v.lock := '0';
v.waddress := ici.fpc(31 downto 2);
v.vaddress := ici.fpc(31 downto 2);
v.trans_op := '0';
v.bpmiss := '0';
end if;
if (not RESET_ALL and rst = '0') or (r.flush = '1') then
vl.lru := (others => (others => '0'));
end if;
-- Drive signals
c <= v; -- register inputs
cl <= vl; -- lru register inputs
-- tag ram inputs
enable := enable;
for i in 0 to ISETS-1 loop
tag(i) := (others => '0');
tag(i)(ilinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := wtag;
tag(i)(CTAG_LRRPOS) := wlrr;
tag(i)(CTAG_LOCKPOS) := wlock;
end loop;
icrami.tag <= tag;
icrami.tenable <= enable;
icrami.twrite <= ctwrite;
icrami.flush <= r.flush2;
icrami.ctx <= mmudci.mmctrl1.ctx;
-- data ram inputs
icrami.denable <= enable;
icrami.address <= taddr(19+LINE_LOW downto LINE_LOW);
icrami.data <= ddatain;
icrami.dwrite <= cdwrite;
-- local ram inputs
icrami.ldramin.enable <= (dco.icdiag.ilramen or lramcs or lramacc);
icrami.ldramin.read <= dco.icdiag.ilramen or lramacc;
icrami.ldramin.write <= ilramwr;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst and r.req;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- mmu <-> icache
mmuici.trans_op <= mmuici_trans_op;
mmuici.transdata.data <= r.waddress(31 downto 2) & "00";
mmuici.transdata.su <= r.su;
mmuici.transdata.isid <= id_icache;
mmuici.transdata.read <= '1';
mmuici.transdata.wb_data <= (others => '0');
-- IU data cache inputs
ico.data <= rdata;
ico.mexc <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
ico.set <= conv_std_logic_vector(set, 2);
ico.cfg <= icfg;
ico.bpmiss <= r.bpmiss;
ico.eocl <= r.eocl;
ico.cstat.chold <= not r.holdn;
ico.cstat.mhold <= mhold;
ico.cstat.tmiss <= mmuico.tlbmiss;
ico.cstat.cmiss <= r.cmiss;
if r.istate = idle then ico.idle <= '1'; else ico.idle <= '0'; end if;
end process;
-- Local registers
regs1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
r.waddress <= ici.fpc(31 downto 2);
r.vaddress <= ici.fpc(31 downto 2);
end if;
end if;
end process;
regs2 : if (ISETS > 1) and (irepl = lru) generate
regs2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then
rl <= LRES;
end if;
end if;
end process;
end generate;
nolru : if (ISETS = 1) or (irepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((ISETS > 2) and (irepl = lrr)) report
"Wrong instruction cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
gpl-2.0
|
afb6a47070cc98cef6a1d074a09b49e1
| 0.549992 | 3.4694 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/spw/wrapper/grspw_gen.vhd
| 1 | 11,150 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_gen
-- File: grspw_gen.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Generic GRSPW core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspw_gen is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmrenablex : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
begin
grspwc0 : grspwc
generic map(
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
tech => tech,
nodeaddr => nodeaddr,
destkey => destkey)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
d => d,
nd => nd,
dconnect => dconnect,
--spw out
do => do,
so => so,
rxrsto => rxrsto,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclk,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
rmapnodeaddr => rmapnodeaddr,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => clk,
testrst => testrst,
testen => testen
);
ntst: if scantest = 0 generate
rmrenablex <= rmrenable;
end generate;
tst: if scantest = 1 generate
rmrenablex <= rmrenable and not testen;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
end architecture;
|
gpl-2.0
|
e9b40fe04601b575df8359ba1bef2665
| 0.552018 | 4.063411 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-xc3s-1500/leon3mp.vhd
| 1 | 38,692 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk3 : in std_ulogic; -- 25 MHz ethernet clock
pllref : in std_ulogic;
errorn : out std_ulogic;
wdogn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
bexcn : in std_ulogic; -- DSU rx data
brdyn : in std_ulogic; -- DSU rx data
romsn : out std_logic_vector (1 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 rx data
rtsn1 : out std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART1 rx data
rtsn2 : out std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_ulogic;
usb_d : inout std_logic_vector(15 downto 0);
usb_linestate : in std_logic_vector(1 downto 0);
usb_opmode : out std_logic_vector(1 downto 0);
usb_reset : out std_ulogic;
usb_rxactive : in std_ulogic;
usb_rxerror : in std_ulogic;
usb_rxvalid : in std_ulogic;
usb_suspend : out std_ulogic;
usb_termsel : out std_ulogic;
usb_txready : in std_ulogic;
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic
);
end;
architecture rtl of leon3mp is
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
CFG_GRUSBDC;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, rst, ndsuact, wdogl : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_GRUSBDC;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_clkl : std_ulogic;
signal spw_clkln : std_ulogic;
signal stati : ahbstat_in_type;
signal uclk : std_ulogic;
signal usbi : grusb_in_type;
signal usbo : grusb_out_type;
constant SPW_LOOP_BACK : integer := 0;
signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate
apbo(9) <= apb_none; rtsn2 <= '0';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 20000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
vgaclk0 : entity work.vga_clkgen
port map (rstn, clk_sel, ethclk, clkm, clk50, video_clk);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
video_clk <= not clkm;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 17 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 13, paddr => 13, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd(0), vcc(0), can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd(0), vcc(0), can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_clkl <= clkm;
spw_rxclkn <= not spw_rxtxclk;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_spw_rx : clkgen -- clock generator
generic map (clktech, 12, 2, 0,
1, 0, 0, 0, 25000)
port map (ethclk, ethclk, spw_clkl, spw_clkln, open, open, open, cgi2, cgo2, open, open);
spw_rxclkn <= spw_clkln;
end generate;
spw_rxtxclk <= spw_clkl;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 2)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector((25*12/20)-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(CFG_SPW_PORTS*i+j) <= spwo(i).d(j);
stmp(CFG_SPW_PORTS*i+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(CFG_SPW_PORTS*i+j), spw_rxdn(CFG_SPW_PORTS*i+j),
dtmp(CFG_SPW_PORTS*i+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(CFG_SPW_PORTS*i+j), spw_rxsn(CFG_SPW_PORTS*i+j),
stmp(CFG_SPW_PORTS*i+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(CFG_SPW_PORTS*i+j), spw_txdn(CFG_SPW_PORTS*i+j),
spwo(i).d(j), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(CFG_SPW_PORTS*i+j), spw_txsn(CFG_SPW_PORTS*i+j),
spwo(i).s(j), gnd(0));
end generate;
end generate;
end generate;
end generate;
-------------------------------------------------------------------------------
--- USB -----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
usbo.oen <= '1'; usbo.reset <= '1';
end generate;
usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (usb_clkout, uclk);
usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
usb_txready_pad : inpad generic map (tech => padtech)
port map (usb_txready,usbi.txready);
usb_rxvalid_pad : inpad generic map (tech => padtech)
port map (usb_rxvalid,usbi.rxvalid);
usb_rxerror_pad : inpad generic map (tech => padtech)
port map (usb_rxerror,usbi.rxerror);
usb_rxactive_pad : inpad generic map (tech => padtech)
port map (usb_rxactive,usbi.rxactive);
usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
port map (usb_linestate,usbi.linestate);
usb_vbus_pad : inpad generic map (tech => padtech)
port map (usb_vbus, usbi.vbusvalid);
usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_reset,usbo.reset);
usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_suspend,usbo.suspendm);
usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_termsel,usbo.termselect);
usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_xcvrsel,usbo.xcvrselect(0));
usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_txvalid,usbo.txvalid);
usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
port map (usb_opmode,usbo.opmode);
usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 5, hirq => 7, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech)
port map(
uclk => uclk,
usbi => usbi,
usbo => usbo,
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
ahbsi => ahbsi,
ahbso => ahbso(5)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
port map (
uclk, usbi, usbo, clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
CFG_SPW_NUM*CFG_SPW_EN));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
e9f75190e4b3f0986eb33dfc39cf3a3e
| 0.556989 | 3.49395 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml501/leon3mp.vhd
| 1 | 35,658 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
sysace_clk_in : in std_ulogic; -- System ACE clock
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr2_ck : out std_logic_vector(1 downto 0);
ddr2_ck_n : out std_logic_vector(1 downto 0);
ddr2_cke : out std_logic_vector(1 downto 0);
ddr2_cs_n : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(1 downto 0);
ddr2_we_n : out std_ulogic; -- ddr write enable
ddr2_ras_n : out std_ulogic; -- ddr ras
ddr2_cas_n : out std_ulogic; -- ddr cas
ddr2_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr2_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr2_dqs_n : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr2_a : out std_logic_vector (13 downto 0); -- ddr address
ddr2_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr2_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
-- txd2 : out std_ulogic; -- UART2 tx data
-- rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(13 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
-- D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
D1 => vcc(0), D2 => gnd(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML501,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
bus_error(0) <= not dbgo(0).error;
bus_error(1) <= rstn;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr2_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr2_a(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr2_ba(1 downto 0), ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n, ddr2_we_n => ddr2_we_n,
ddr2_cs_n => ddr2_cs_n(CS_NUM-1 downto 0), ddr2_odt => ddr2_odt(0 downto 0),
ddr2_cke => ddr2_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr2_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr2_dqs(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr2_dqs_n(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr2_ck((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr2_ck_n((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
ddr2_a(13) <= '0';
ddr2_odt(1) <= '0';
ddr2_cs_n(1) <= '0';
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#E00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock,
clkml, clkml, ahbsi, ahbso(0),
ddr2_ck, ddr2_ck_n, ddr_clk_fb, ddr_clk_fb, ddr2_cke, ddr2_cs_n,
ddr2_we_n, ddr2_ras_n, ddr2_cas_n,
ddr2_dm, ddr2_dqs, ddr2_dqs_n, ddr2_a, ddr2_ba, ddr2_dq, ddr2_odt);
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 14)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 14)
port map (gpio, gpioo.dout(13 downto 0), gpioo.oen(13 downto 0),
gpioi.din(13 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML501),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
8563a5f95111caad2be2b2d02adfff6f
| 0.573279 | 3.303502 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2c2ahb.vhd
| 1 | 3,070 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb
-- File: i2c2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb;
architecture rtl of i2c2ahb is
signal i2c2ahbi : i2c2ahb_in_type;
begin
bridge : i2c2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
i2ci => i2ci,
i2co => i2co,
i2c2ahbi => i2c2ahbi,
i2c2ahbo => open);
i2c2ahbi.en <= '1';
i2c2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
i2c2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
i2c2ahbi.slvaddr <= conv_std_logic_vector(i2cslvaddr, 7);
i2c2ahbi.cfgaddr <= conv_std_logic_vector(i2ccfgaddr, 7);
end architecture rtl;
|
gpl-2.0
|
ff17630302750f8cb386848edee31ef6
| 0.586319 | 3.582264 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/libfpu.vhd
| 1 | 4,759 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libfpu
-- File: libfpu.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 FPU interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
package libfpu is
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
constant fpc_debug_none : fpc_debug_out_type := (data => X"00000000"
);
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
constant fpc_out_none : fpc_out_type := (X"00000000", '0', "00", '1', '0', '1',
fpc_debug_none);
component grfpwxsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
end;
|
gpl-2.0
|
adf8ffc72bf930e5bae1c4eccd825d1b
| 0.544022 | 3.959235 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spi_flash.vhd
| 1 | 20,164 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi_flash
-- File: spi_flash.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description:
--
-- SPI flash simulation models.
--
-- +--------------------------------------------------------+
-- | ftype | Memory device |
-- +--------+-----------------------------------------------+
-- | 1 | SD card |
-- +--------+-----------------------------------------------+
-- | 3 | Simple SPI |
-- +--------+-----------------------------------------------+
-- | 4 | SPI memory device |
-- +--------+-----------------------------------------------+
--
-- For ftype => 4, the memoffset generic can be used to specify an address
-- offset that till be automatically be removed by the memory model. For
-- instance, memoffset => 16#1000# and an access to 0x1000 will read the
-- internal memory array at offset 0x0. This is a quick hack to support booting
-- from SPIMCTRL that has an offset specified and not having to modify the
-- SREC.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib, gaisler;
use grlib.stdlib.all;
use grlib.stdio.all;
--use gaisler.sim.all;
entity spi_flash is
generic (
ftype : integer := 0; -- Flash type
debug : integer := 0; -- Debug output
fname : string := "prom.srec"; -- File to read from
readcmd : integer := 16#0B#; -- SPI memory device read command
dummybyte : integer := 1;
dualoutput : integer := 0;
memoffset : integer := 0); -- Addr. offset automatically removed
-- by Flash model
port (
sck : in std_ulogic;
di : inout std_logic;
do : inout std_logic;
csn : inout std_logic;
-- Test control inputs
sd_cmd_timeout : in std_ulogic := '0';
sd_data_timeout : in std_ulogic := '0'
);
end spi_flash;
architecture sim of spi_flash is
-- Description: Simple, incomplete, model of SD card
procedure simple_sd_model (
constant dbg : in integer;
signal sck : in std_ulogic;
signal di : in std_ulogic;
signal do : out std_ulogic;
signal csn : in std_ulogic;
-- Test control inputs
signal cmd_to : in std_ulogic; -- force command response timeout
signal data_to : in std_ulogic) is -- force data token timeout
type sd_state_type is (idle, wait_cmd55, wait_acmd41, wait_cmd16,
wait_cmd17);
type response_type is array (0 to 10) of std_logic_vector(7 downto 0);
variable state : sd_state_type := idle;
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : response_type;
variable resp_size : integer;
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(47 downto 0);
variable index : integer;
variable bcnt : integer;
constant CMD0 : std_logic_vector(5 downto 0) := "000000";
constant CMD16 : std_logic_vector(5 downto 0) := "010000";
constant CMD17 : std_logic_vector(5 downto 0) := "010001";
constant CMD55 : std_logic_vector(5 downto 0) := "110111";
constant ACMD41 : std_logic_vector(5 downto 0) := "101001";
constant R1 : std_logic_vector(7 downto 0) := X"00";
constant DATA_TOKEN : std_logic_vector(7 downto 0) := X"FE";
constant DATA_ERR_TOKEN : std_logic_vector(7 downto 0) := X"01";
begin -- simple_sd_model
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
-- Receive data
do <= '1';
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then -- Received a byte
command := command(39 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received byte: " &
tost(indata));
end if;
if (command(47 downto 46) = "01" and command(7 downto 0) = X"95") then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
case state is
when idle =>
if command(45 downto 40) = CMD0 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD0");
end if;
if cmd_to = '0' then
state := wait_cmd55;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd55 =>
if command(45 downto 40) = CMD55 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD55");
end if;
state := wait_acmd41;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_acmd41 =>
if command(45 downto 40) = ACMD41 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD41");
end if;
if cmd_to = '0' then
state := wait_cmd16;
else
state := idle;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd16 =>
if command(45 downto 40) = CMD16 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD16");
Print(time'image(now) & ": simple_sd_model: BLOCKLEN set to " &
tost(conv_integer(command(39 downto 8))));
end if;
state := wait_cmd17;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd17 =>
if command(45 downto 40) = CMD17 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD17");
Print(time'image(now) & ": simple_sd_model: Read from address " &
tost(conv_integer(command(39 downto 8))));
end if;
response(0) := R1;
response(1) := (others => '1');
response(2) := (others => '1');
response(3) := DATA_TOKEN;
-- Data response is address
response(4) := command(39 downto 32);
response(5) := command(31 downto 24);
response(6) := command(23 downto 16);
response(7) := command(15 downto 8);
if data_to = '1' then
resp_size := 1;
else
resp_size := 8;
end if;
respond := not cmd_to;
elsif command(45 downto 40) = CMD0 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD0");
end if;
if cmd_to = '0' then
state := wait_cmd55;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
end case;
received_command := '0';
end if;
if respond = '1' then
bcnt := 0;
while resp_size > bcnt loop
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: Responding with " &
tost(response(bcnt)));
end if;
index := 0;
while index < 8 loop
wait until falling_edge(sck);
do <= response(bcnt)(7);
response(bcnt)(7 downto 1) := response(bcnt)(6 downto 0);
index := index + 1;
end loop;
bcnt := bcnt + 1;
end loop;
respond := '0';
wait until rising_edge(sck);
else
do <= '1';
end if;
end loop;
end simple_sd_model;
-- purpose: Simple, incomplete, model of SPI Flash device
procedure simple_spi_flash_model (
constant dbg : in integer;
constant readcmd : in integer;
constant dummybyte : in boolean;
constant dualoutput : in boolean;
signal sck : in std_ulogic;
signal di : inout std_ulogic;
signal do : out std_ulogic;
signal csn : in std_ulogic) is
constant readinst : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(readcmd, 8);
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : std_logic_vector(31 downto 0);
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(39 downto 0);
variable index : integer;
begin -- simple_spi_flash_model
di <= 'Z'; do <= 'Z';
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then
command := command(31 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": simple_spi_flash_model: received byte: " &
tost(indata));
end if;
if ((dummybyte and command(39 downto 32) = readinst) or
(not dummybyte and command(31 downto 24) = readinst)) then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
response := (others => '0');
if dummybyte then
response(23 downto 0) := command(31 downto 8);
else
response(23 downto 0) := command(23 downto 0);
end if;
index := 31 - conv_integer(response(1 downto 0)) * 8;
response(1 downto 0) := (others => '0');
while csn = '0' loop
while index >= 0 and csn = '0' loop
wait until falling_edge(sck) or csn = '1';
if dualoutput then
do <= response(index);
di <= response(index-1);
index := index - 2;
else
do <= response(index);
index := index - 1;
end if;
end loop;
index := 31;
response := response + 4;
end loop;
if dualoutput then
di <= 'Z';
end if;
received_command := '0';
else
do <= '1';
end if;
end loop;
end simple_spi_flash_model;
-- purpose: SPI memory device that reads input from prom.srec
procedure spi_memory_model (
constant dbg : in integer;
constant readcmd : in integer;
constant dummybyte : in boolean;
constant dualoutput : in boolean;
signal sck : in std_ulogic;
signal di : inout std_ulogic;
signal do : inout std_ulogic;
signal csn : in std_ulogic) is
constant readinst : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(readcmd, 8);
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : std_logic_vector(31 downto 0);
variable address : std_logic_vector(23 downto 0);
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(39 downto 0);
variable index : integer;
file fload : text open read_mode is fname;
variable fline : line;
variable fchar : character;
variable rtype : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(31 downto 0);
variable rlen : std_logic_vector(7 downto 0);
variable rdata : std_logic_vector(0 to 127);
variable wordaddr : integer;
type mem_type is array (0 to 8388607) of std_logic_vector(31 downto 0);
variable mem : mem_type := (others => (others => '1'));
begin -- spi_memory_model
di <= 'Z'; do <= 'Z';
-- Load memory data from file
while not endfile(fload) loop
readline(fload, fline);
read(fline, fchar);
if fchar /= 'S' or fchar /= 's' then
hread(fline, rtype);
hread(fline, rlen);
raddr := (others => '0');
case rtype is
when "0001" =>
hread(fline, raddr(15 downto 0));
when "0010" =>
hread(fline, raddr(23 downto 0));
when "0011" =>
hread(fline, raddr);
raddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(fline, rdata);
for i in 0 to 3 loop
mem(conv_integer(raddr(31 downto 2)+i)) :=
rdata(i*32 to i*32+31);
end loop;
end if;
end loop;
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then
command := command(31 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: received byte: " &
tost(indata));
end if;
if ((dummybyte and command(39 downto 32) = readinst) or
(not dummybyte and command(31 downto 24) = readinst)) then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
response := (others => '0');
if dummybyte then
address := command(31 downto 8);
else
address := command(23 downto 0);
end if;
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: received address: " &
tost(address));
if memoffset /= 0 then
Print(time'image(now) & ": spi_memory_model: address after removed offset " &
tost(address-memoffset));
end if;
end if;
if memoffset /= 0 then
address := address - memoffset;
end if;
index := 31 - conv_integer(address(1 downto 0)) * 8;
while csn = '0' loop
response := mem(conv_integer(address(23 downto 2)));
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: responding with data: " &
tost(response(index downto 0)));
end if;
while index >= 0 and csn = '0' loop
wait until falling_edge(sck) or csn = '1';
if dualoutput then
do <= response(index);
di <= response(index-1);
index := index - 2;
else
do <= response(index);
index := index - 1;
end if;
end loop;
index := 31;
address := address + 4;
end loop;
if dualoutput then
di <= 'Z';
end if;
do <= 'Z';
received_command := '0';
else
do <= 'Z';
end if;
end loop;
end spi_memory_model;
signal vdd : std_ulogic := '1';
signal gnd : std_ulogic := '0';
begin -- sim
-- ftype0: if ftype = 0 generate
-- csn <= 'Z';
-- di <= 'Z';
-- flash0 : s25fl064a
-- generic map (tdevice_PU => 1 us,
-- TimingChecksOn => true,
-- MsgOn => debug = 1,
-- UserPreLoad => true)
-- port map (SCK => sck, SI => di, CSNeg => csn, HOLDNeg => vdd,
-- WNeg => vdd, SO => do);
-- end generate ftype0;
ftype1: if ftype = 1 generate
csn <= 'H';
di <= 'Z';
simple_sd_model(debug, sck, di, do, csn, sd_cmd_timeout, sd_data_timeout);
end generate ftype1;
-- ftype2: if ftype = 2 generate
-- csn <= 'Z';
-- di <= 'Z';
-- flash0 : m25p80
-- generic map (TimingChecksOn => false,
-- MsgOn => debug = 1,
-- UserPreLoad => true)
-- port map (C => sck, D => di, SNeg => csn, HOLDNeg => vdd,
-- WNeg => vdd, Q => do);
-- end generate ftype2;
ftype3: if ftype = 3 generate
csn <= 'Z';
simple_spi_flash_model (
dbg => debug,
readcmd => readcmd,
dummybyte => dummybyte /= 0,
dualoutput => dualoutput /= 0,
sck => sck,
di => di,
do => do,
csn => csn);
end generate ftype3;
ftype4: if ftype = 4 generate
spi_memory_model (
dbg => debug,
readcmd => readcmd,
dummybyte => dummybyte /= 0,
dualoutput => dualoutput /= 0,
sck => sck,
di => di,
do => do,
csn => csn);
csn <= 'Z';
end generate ftype4;
notsupported: if ftype > 4 generate
assert false report "spi_flash: no model" severity failure;
end generate notsupported;
end sim;
|
gpl-2.0
|
861867e55af4239448a5c8391e16bcc6
| 0.489337 | 4.127738 | false | false | false | false |
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