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elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc3s1000/testbench.vhd
| 1 | 7,785 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(19 downto 0);
signal data : std_logic_vector(31 downto 0);
signal mben : std_logic_vector(3 downto 0);
signal pio : std_logic_vector(17 downto 0);
signal ramsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal errorn : std_logic;
signal ps2clk : std_logic;
signal ps2data : std_logic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic;
signal vid_g : std_logic;
signal vid_b : std_logic;
signal switch : std_logic_vector(7 downto 0); -- switches
signal button : std_logic_vector(2 downto 0);
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst; dsuen <= '1'; dsubre <= '0';
rxd1 <= 'H';
ps2clk <= 'H'; ps2data <= 'H';
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
address(1 downto 0) <= "00";
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (rst, clk, errorn, address(19 downto 2), data,
ramsn, mben, oen, writen,
dsubre, dsuact, txd1, rxd1, pio, --switch, button,
ps2clk, ps2data,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b
);
sram0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sdramfile)
port map (address(19 downto 2), data(31-i*16 downto 16-i*16),
mben(i*2+1), mben(i*2), ramsn(i), writen, oen);
end generate;
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '0' then wait on errorn; end if;
assert (to_x01(errorn) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait for 2500 ns;
dsurst <= '0';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
|
gpl-2.0
|
8645949303ddc7cde657c9b9226dd32f
| 0.575466 | 3.032723 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml40x/testbench.vhd
| 1 | 10,420 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
signal sysace_clk_in : std_ulogic := '0';
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(22 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(26 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int_n : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk_in, plb_error, opb_error, flash_a23,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n,
sram_flash_we_n, flash_ce, sram_clk, sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_int_n,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
ddr0 : ddrram
generic map(width => 32, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
|
gpl-2.0
|
efa7adb440e49c382ca4463bb8d2ca6c
| 0.61142 | 2.996836 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/new/debounce.vhd
| 1 | 1,100 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 20);
PORT(
clk : IN STD_LOGIC;
button : IN STD_LOGIC;
result : OUT STD_LOGIC);
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL counter_set : STD_LOGIC;
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0');
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(rising_edge(clk)) THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic;
|
mit
|
c16cf589bb701b4543891798f0a3923e
| 0.601818 | 3.703704 | false | false | false | false |
luebbers/reconos
|
tools/fsmLanguage/fpga_scripts/pr_scripts/infer_bram.vhd
| 12 | 4,270 |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
gpl-3.0
|
7e19f3c678baccce520f340ec84cff00
| 0.546136 | 4.765625 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/simple_timebase_v1_00_a/hdl/vhdl/simple_timebase.vhd
| 1 | 21,648 |
------------------------------------------------------------------------------
-- simple_timebase.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: simple_timebase.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Feb 17 10:01:45 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library simple_timebase_v1_00_a;
use simple_timebase_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity simple_timebase is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity simple_timebase;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of simple_timebase is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity simple_timebase_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
gpl-3.0
|
5c6ce12624e2ab9ac69d3b6c6c0ad68f
| 0.449233 | 4.498753 | false | false | false | false |
five-elephants/hw-neural-sampling
|
sampler.vhdl
| 1 | 5,573 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
entity sampler is
generic (
num_samplers : integer := 8;
lfsr_polynomial : lfsr_state_t;
tau : positive := 20
);
port (
clk, reset : in std_ulogic;
phase : in phase_t;
bias : in weight_t;
sum_in : in signed(sum_in_size(num_samplers)-1 downto 0);
state : out std_ulogic;
membrane : out membrane_t;
fire : out std_ulogic;
seed : in lfsr_state_t
);
end sampler;
architecture rtl of sampler is
subtype sum_in_t is
signed(sum_in_size(num_samplers)-1 downto 0);
subtype zeta_t is integer range 0 to tau;
signal membrane_i : membrane_t;
signal zeta : zeta_t;
signal activate : std_ulogic;
begin
membrane <= membrane_i;
------------------------------------------------------------
membrane_adder: process(clk, reset)
variable sum_in_ext : membrane_t;
variable bias_ext : membrane_t;
begin
if reset = '1' then
membrane_i <= to_signed(0, membrane'length);
elsif rising_edge(clk) then
if phase = propagate then
bias_ext := shift_left(
resize(bias, bias_ext'length),
membrane_fraction-weight_fraction
);
sum_in_ext := shift_left(
resize(sum_in, sum_in_ext'length),
membrane_fraction-weight_fraction
);
membrane_i <= sum_in_ext + bias_ext;
end if;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
activation_function: entity work.activation(rtl)
generic map (
lfsr_polynomial => lfsr_polynomial
)
port map (
clk => clk,
reset => reset,
membrane => membrane_i,
active => activate,
seed => seed
);
------------------------------------------------------------
------------------------------------------------------------
refractory_fsm: process ( clk, reset )
variable over_thresh : boolean;
begin
if reset = '1' then
zeta <= 0;
fire <= '0';
elsif rising_edge(clk) then
if phase = evaluate then
over_thresh := (activate = '1');
fire <= '0';
case zeta is
when 1 =>
if over_thresh then
zeta <= tau;
fire <= '1';
else
zeta <= 0;
end if;
when 0 =>
if over_thresh then
zeta <= tau;
fire <= '1';
end if;
when others =>
zeta <= zeta - 1;
end case;
end if;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
refractory_fsm_output: process ( zeta )
begin
if zeta > 0 then
state <= '1';
else
state <= '0';
end if;
end process;
------------------------------------------------------------
end rtl;
architecture behave of sampler is
subtype sum_in_t is
signed(sum_in_size(num_samplers)-1 downto 0);
subtype zeta_t is integer range 0 to tau;
signal membrane_i : membrane_t;
signal zeta : zeta_t;
begin
membrane <= membrane_i;
------------------------------------------------------------
membrane_adder: process(clk, reset)
variable sum_in_ext : membrane_t;
variable bias_ext : membrane_t;
begin
if reset = '1' then
membrane_i <= to_signed(0, membrane'length);
elsif rising_edge(clk) then
if phase = propagate then
bias_ext := shift_left(
resize(bias, bias_ext'length),
membrane_fraction-weight_fraction
);
sum_in_ext := shift_left(
resize(sum_in, sum_in_ext'length),
membrane_fraction-weight_fraction
);
membrane_i <= sum_in_ext + bias_ext;
end if;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
refractory_fsm: process ( clk, reset )
constant log_tau : real := log(20.0);
variable seed1, seed2 : positive;
variable rand : real;
variable cmp : real;
variable u : real;
variable over_thresh : boolean;
begin
if reset = '1' then
zeta <= 0;
fire <= '0';
seed1 := to_integer(unsigned(seed));
seed2 := 1;
elsif rising_edge(clk) then
if phase = evaluate then
uniform(seed1, seed2, rand);
u := real(to_integer(membrane_i)) / 2.0**membrane_fraction;
cmp := 1.0 / (1.0 + exp(-u + log_tau));
over_thresh := rand < cmp;
fire <= '0';
case zeta is
when 1 =>
if over_thresh then
zeta <= tau;
fire <= '1';
else
zeta <= 0;
end if;
when 0 =>
if over_thresh then
zeta <= tau;
fire <= '1';
end if;
when others =>
zeta <= zeta - 1;
end case;
end if;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
refractory_fsm_output: process ( zeta )
begin
if zeta > 0 then
state <= '1';
else
state <= '0';
end if;
end process;
------------------------------------------------------------
end behave;
-- vim: set et fenc=utf-8 ff=unix sts=0 sw=2 ts=2 : --
|
apache-2.0
|
a7acc01f175e4903deab480971e7affc
| 0.45236 | 4.293529 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/new/Prng.vhd
| 1 | 836 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Seeded PRNG
-- Thanks wikipedia
entity Prng is
Generic
(
BITS : integer := 32
);
Port
(
seed : in std_logic_vector (BITS-1 downto 0);
seed_en : in std_logic;
clk : in std_logic;
rnd : out std_logic_vector (BITS-1 downto 0)
);
end Prng;
architecture Behavioral of Prng is
begin
process (clk)
variable tmp_a : std_logic_vector(BITS-1 downto 0) := ('1', '0', '1', others => '0');
variable tmp_b : std_logic := '0';
begin
if rising_edge(clk) then
if seed_en = '1' then
tmp_a := seed;
else
tmp_b := tmp_a(BITS-1) xor tmp_a(BITS-2);
tmp_a := tmp_a(BITS-2 downto 0) & tmp_b;
rnd <= tmp_a;
end if;
end if;
end process;
end Behavioral;
|
mit
|
7ec2341b5fb26847ec4ca3e88b148135
| 0.533493 | 3.178707 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_eth/pcores/arbiter_v2_01_a/hdl/vhdl/arbiter.vhd
| 1 | 8,300 |
-- very simple arbiter, slot 0 has highest priority, everything else can starve
-- due to lack of better knowledge: no generics are used.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity arbiter is
generic (
C_NR_SLOTS : integer := 3 -- it is not a "real" generic, e.g., we still have to adapt the number of ports and the number of signals manually
);
port (
i_ready : in std_logic_vector(0 to C_NR_SLOTS - 1); --every thread can tell whether it is ready to accept data
i_req_0 : in std_logic_vector(0 to C_NR_SLOTS - 1); --requests vector of thread Nr 0 (0 to 0 is allowed, loops are explicitly allowed)
i_req_1 : in std_logic_vector(0 to C_NR_SLOTS - 1); --requests vector of thread Nr. 1. (element 0 = 1 => want to talk with thread 0)
i_req_2 : in std_logic_vector(0 to C_NR_SLOTS - 1); --requests vector of thread Nr. 2.
o_grant_0 : out std_logic_vector(0 to C_NR_SLOTS - 1); --grant vector to thread NR 0. (element 0 = 1 => allowed to talk to thread 0)
o_grant_1 : out std_logic_vector(0 to C_NR_SLOTS - 1); --grant vector to thread NR 1. (element 0 = 1 => allowed to talk to thread 0)
o_grant_2 : out std_logic_vector(0 to C_NR_SLOTS - 1); --grant vector to thread Nr 2. (element 0 = 1 => allowed to talk to thread 0)
clk : in std_logic;
reset : in std_logic
);
end arbiter;
architecture Behavioral of arbiter is
signal req_for_thread_0 : std_logic_vector(0 to C_NR_SLOTS -1); -- request signals for talking with thread 0
signal req_for_thread_1 : std_logic_vector(0 to C_NR_SLOTS -1); -- element 0 = 1 => thread 0 wants to talk to thread 1
signal req_for_thread_2 : std_logic_vector(0 to C_NR_SLOTS -1);
signal grant_for_thread_0 : std_logic_vector(0 to C_NR_SLOTS -1); -- grant signals for talking with thread 0
signal grant_for_thread_1 : std_logic_vector(0 to C_NR_SLOTS -1); -- element 0 = 1 => thread 0 is allowed to talk to thread 1
signal grant_for_thread_2 : std_logic_vector(0 to C_NR_SLOTS -1);
type t_state is (STATE_INIT, STATE_WAIT, STATE_GRANT_0, STATE_GRANT_1, STATE_GRANT_2);
signal b0_state : t_state := STATE_INIT;
signal b0_state_next : t_state := STATE_INIT;
signal b1_state : t_state := STATE_INIT;
signal b1_state_next : t_state := STATE_INIT;
signal b2_state : t_state := STATE_INIT;
signal b2_state_next : t_state := STATE_INIT;
begin
-- how could this be done less ugly?...
req_for_thread_0(0) <= i_req_0(0);
req_for_thread_0(1) <= i_req_1(0);
req_for_thread_0(2) <= i_req_2(0);
req_for_thread_1(0) <= i_req_0(1);-- '1'
req_for_thread_1(1) <= i_req_1(1);-- '0'
req_for_thread_1(2) <= i_req_2(1);-- '0'
req_for_thread_2(0) <= i_req_0(2);
req_for_thread_2(1) <= i_req_1(2);
req_for_thread_2(2) <= i_req_2(2);
o_grant_0(0) <= grant_for_thread_0(0);
o_grant_0(1) <= grant_for_thread_1(0);
o_grant_0(2) <= grant_for_thread_2(0);
o_grant_1(0) <= grant_for_thread_0(1);
o_grant_1(1) <= grant_for_thread_1(1);
o_grant_1(2) <= grant_for_thread_2(1);
o_grant_2(0) <= grant_for_thread_0(2); --0
o_grant_2(1) <= grant_for_thread_1(2); --1
o_grant_2(2) <= grant_for_thread_2(2); --0
--computes the grant signal for bus_0 (e.g. determines who is allowed to send to the hwthread in slot 0.
bus_0 : process(req_for_thread_0, b0_state)
begin
b0_state_next <= b0_state;
case b0_state is
when STATE_INIT =>
b0_state_next <= STATE_WAIT;
grant_for_thread_0 <= (others => '0');
when STATE_WAIT => --highes priority has slot 0 the rest can starve.
if req_for_thread_0(0) = '1' then
b0_state_next <= STATE_GRANT_0;
grant_for_thread_0 <= "100";
elsif req_for_thread_0(1) = '1' then
b0_state_next <= STATE_GRANT_1;
grant_for_thread_0 <= "010";
elsif req_for_thread_0(2) = '1' then
b0_state_next <= STATE_GRANT_2;
grant_for_thread_0 <= "001";
else
b0_state_next <= STATE_WAIT;
grant_for_thread_0 <= "000";
end if;
when STATE_GRANT_0 => --he can send as long as he likes...
if req_for_thread_0(0) = '0' then
grant_for_thread_0 <= "000";
b0_state_next <= STATE_WAIT;
else
grant_for_thread_0 <= "100";
b0_state_next <= STATE_GRANT_0;
end if;
when STATE_GRANT_1 => --he can send as long as he likes...
if req_for_thread_0(1) = '0' then
grant_for_thread_0 <= "000";
b0_state_next <= STATE_WAIT;
else
grant_for_thread_0 <= "010";
b0_state_next <= STATE_GRANT_1;
end if;
when STATE_GRANT_2 => --he can send as long as he likes...
if req_for_thread_0(2) = '0' then
grant_for_thread_0 <= "000";
b0_state_next <= STATE_WAIT;
else
grant_for_thread_0 <= "001";
b0_state_next <= STATE_GRANT_2;
end if;
when others =>
b0_state_next <= STATE_INIT;
end case;
end process;
-- grant_for_thread_1 <= "100";
--computes the grant signal for bus_0 (e.g. determines who is allowed to send to the hwthread in slot 0.
bus_1 : process(req_for_thread_1, b1_state)
begin
b1_state_next <= b1_state;
grant_for_thread_1 <= "000";
case b1_state is
when STATE_INIT =>
b1_state_next <= STATE_WAIT;
grant_for_thread_1 <= "000";
when STATE_WAIT => --highes priority has slot 0 the rest can starve.
if req_for_thread_1(0) = '1' then
b1_state_next <= STATE_GRANT_0;
grant_for_thread_1 <= "100";
elsif req_for_thread_1(1) = '1' then
b1_state_next <= STATE_GRANT_1;
grant_for_thread_1 <= "010";
elsif req_for_thread_1(2) = '1' then
b1_state_next <= STATE_GRANT_2;
grant_for_thread_1 <= "001";
else
b1_state_next <= STATE_WAIT;
grant_for_thread_1 <= "000";
end if;
when STATE_GRANT_0 => --he can send as long as he likes...
if req_for_thread_1(0) = '0' then
grant_for_thread_1 <= "000";
b1_state_next <= STATE_WAIT;
else
grant_for_thread_1 <= "100";
b1_state_next <= STATE_GRANT_0;
end if;
when STATE_GRANT_1 => --he can send as long as he likes...
if req_for_thread_1(1) = '0' then
grant_for_thread_1 <= "000";
b1_state_next <= STATE_WAIT;
else
grant_for_thread_1 <= "010";
b1_state_next <= STATE_GRANT_1;
end if;
when STATE_GRANT_2 => --he can send as long as he likes...
if req_for_thread_1(2) = '0' then
grant_for_thread_1 <= "000";
b1_state_next <= STATE_WAIT;
else
grant_for_thread_1 <= "001";
b1_state_next <= STATE_GRANT_2;
end if;
when others =>
b1_state_next <= STATE_INIT;
end case;
end process;
bus_2 : process(req_for_thread_2, b2_state)
begin
b2_state_next <= b2_state;
case b2_state is
when STATE_INIT =>
b2_state_next <= STATE_WAIT;
grant_for_thread_2 <= (others => '0');
when STATE_WAIT => --highes priority has slot 0 the rest can starve.
if req_for_thread_2(0) = '1' then
b2_state_next <= STATE_GRANT_0;
grant_for_thread_2 <= "100";
elsif req_for_thread_2(1) = '1' then
b2_state_next <= STATE_GRANT_1;
grant_for_thread_2 <= "010";
elsif req_for_thread_2(2) = '1' then
b2_state_next <= STATE_GRANT_2;
grant_for_thread_2 <= "001";
else
b2_state_next <= STATE_WAIT;
grant_for_thread_2 <= "000";
end if;
when STATE_GRANT_0 => --he can send as long as he likes...
if req_for_thread_2(0) = '0' then
grant_for_thread_2 <= "000";
b2_state_next <= STATE_WAIT;
else
grant_for_thread_2 <= "100";
b2_state_next <= STATE_GRANT_0;
end if;
when STATE_GRANT_1 => --he can send as long as he likes...
if req_for_thread_2(1) = '0' then
grant_for_thread_2 <= "000";
b2_state_next <= STATE_WAIT;
else
grant_for_thread_2 <= "010";
b2_state_next <= STATE_GRANT_1;
end if;
when STATE_GRANT_2 => --he can send as long as he likes...
if req_for_thread_2(2) = '0' then
grant_for_thread_2 <= "000";
b2_state_next <= STATE_WAIT;
else
grant_for_thread_2 <= "001";
b2_state_next <= STATE_GRANT_2;
end if;
when others =>
b2_state_next <= STATE_INIT;
end case;
end process;
memzing : process(clk, reset)
begin
if reset = '1' then
b0_state <= STATE_INIT;
b1_state <= STATE_INIT;
b2_state <= STATE_INIT;
elsif rising_edge(clk) then
b0_state <= b0_state_next;
b1_state <= b1_state_next;
b2_state <= b2_state_next;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
c96cc44e4e9634646df0e79a438a4576
| 0.633494 | 2.5359 | false | false | false | false |
bzero/freezing-spice
|
src/decode_pkg.vhd
| 2 | 3,862 |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.common.all;
package decode_pkg is
-- structure for decoded instruction
type decoded_t is record
alu_func : alu_func_t;
op2_src : std_logic;
insn_type : insn_type_t;
branch_type : branch_type_t;
load_type : load_type_t;
store_type : store_type_t;
rs1 : std_logic_vector(4 downto 0);
rs2 : std_logic_vector(4 downto 0);
rd : std_logic_vector(4 downto 0);
imm : word;
opcode : std_logic_vector(6 downto 0);
rs1_rd : std_logic;
rs2_rd : std_logic;
use_imm : std_logic;
end record decoded_t;
constant c_decoded_reset : decoded_t := (alu_func => ALU_NONE,
op2_src => '0',
insn_type => OP_ILLEGAL,
branch_type => BRANCH_NONE,
load_type => LOAD_NONE,
store_type => STORE_NONE,
rs1 => "00000",
rs2 => "00000",
rd => "00000",
imm => (others => '0'),
opcode => (others => 'X'),
rs1_rd => '0',
rs2_rd => '0',
use_imm => '0');
-- Constants
constant c_op_load : std_logic_vector(6 downto 0) := "0000011";
constant c_op_misc_mem : std_logic_vector(6 downto 0) := "0001111";
constant c_op_imm : std_logic_vector(6 downto 0) := "0010011";
constant c_op_auipc : std_logic_vector(6 downto 0) := "0010111";
constant c_op_store : std_logic_vector(6 downto 0) := "0100011";
constant c_op_reg : std_logic_vector(6 downto 0) := "0110011";
constant c_op_lui : std_logic_vector(6 downto 0) := "0110111";
constant c_op_branch : std_logic_vector(6 downto 0) := "1100011";
constant c_op_jalr : std_logic_vector(6 downto 0) := "1100111";
constant c_op_jal : std_logic_vector(6 downto 0) := "1101111";
constant c_op_system : std_logic_vector(6 downto 0) := "1110011";
procedure print_insn (insn_type : in insn_type_t);
end package decode_pkg;
package body decode_pkg is
procedure print_insn (insn_type : in insn_type_t) is
variable l : line;
begin
write(l, string'("Instruction type: "));
if insn_type = OP_LUI then
write(l, string'("LUI"));
writeline(output, l);
elsif insn_type = OP_AUIPC then
write(l, string'("AUIPC"));
writeline(output, l);
elsif insn_type = OP_JAL then
write(l, string'("JAL"));
writeline(output, l);
elsif insn_type = OP_JALR then
write(l, string'("JALR"));
writeline(output, l);
elsif insn_type = OP_BRANCH then
write(l, string'("BRANCH"));
writeline(output, l);
elsif insn_type = OP_LOAD then
write(l, string'("LOAD"));
writeline(output, l);
elsif insn_type = OP_STORE then
write(l, string'("STORE"));
writeline(output, l);
elsif insn_type = OP_ALU then
write(l, string'("ALU"));
writeline(output, l);
else
write(l, string'("ILLEGAL"));
writeline(output, l);
end if;
end procedure print_insn;
end package body decode_pkg;
|
bsd-3-clause
|
dd4e034c3dd654914d7c44770ff5ad73
| 0.459347 | 4.09544 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_package.vhd
| 4 | 15,717 |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_package.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-- TESTBENCH_ac97_package.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_package.vhd
--
-- Description: Testbench utitlities for AC97
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package testbench_ac97_package is
procedure write_opb (signal OPB_Clk : in std_logic;
signal xferAck : in std_logic;
constant address : in std_logic_vector(0 to 31);
constant data : in std_logic_vector(0 to 31);
signal OPB_select : out std_logic;
signal OPB_RNW : out std_logic;
signal OPB_ABus : out std_logic_vector(0 to 31);
signal OPB_DBus : out std_logic_vector(0 to 31)
);
procedure read_opb (signal OPB_Clk : in std_logic;
signal xferAck : in std_logic;
constant address : in std_logic_vector(0 to 31);
signal OPB_select : out std_logic;
signal OPB_RNW : out std_logic;
signal OPB_ABus : out std_logic_vector(0 to 31);
signal OPB_DBus : out std_logic_vector(0 to 31)
);
procedure send_frame (signal clk : in std_logic;
variable slot0 : in std_logic_vector(15 downto 0);
variable slot1 : in std_logic_vector(19 downto 0);
variable slot2 : in std_logic_vector(19 downto 0);
variable slot3 : in std_logic_vector(19 downto 0);
variable slot4 : in std_logic_vector(19 downto 0);
variable slot5 : in std_logic_vector(19 downto 0);
variable slot6 : in std_logic_vector(19 downto 0);
variable slot7 : in std_logic_vector(19 downto 0);
variable slot8 : in std_logic_vector(19 downto 0);
variable slot9 : in std_logic_vector(19 downto 0);
variable slot10 : in std_logic_vector(19 downto 0);
variable slot11 : in std_logic_vector(19 downto 0);
variable slot12 : in std_logic_vector(19 downto 0);
signal SData_In : out std_logic);
procedure send_basic_frame (signal clk : in std_logic;
variable slot0 : in std_logic_vector(15 downto 0);
variable slot1 : in std_logic_vector(19 downto 0);
variable slot2 : in std_logic_vector(19 downto 0);
variable slot3 : in std_logic_vector(19 downto 0);
variable slot4 : in std_logic_vector(19 downto 0);
signal SData_In : out std_logic);
procedure read_ip (signal Bus2IP_Clk : in std_logic;
signal IP2bus_Data : in std_logic_vector(0 to 31);
constant address : in std_logic_vector(0 to 31);
signal Bus2IP_CS : out std_logic;
signal Bus2IP_Addr : out std_logic_vector(0 to 31);
signal Bus2IP_RdCE : out std_logic;
signal IP_READ : out std_logic_vector(0 to 31)
);
procedure write_ip (signal Bus2IP_Clk : in std_logic;
constant address : in std_logic_vector(0 to 31);
constant data : in std_logic_vector(0 to 31);
signal Bus2IP_CS : out std_logic;
signal Bus2IP_Addr : out std_logic_vector(0 to 31);
signal Bus2IP_Data : out std_logic_vector(0 to 31);
signal Bus2IP_WrCE : out std_logic
);
procedure delay(signal sig : in std_logic; constant cycles : in integer);
constant BIT_CLK_HALF_PERIOD : time := 40.69 ns;
constant FIFO_CTRL_OFFSET : std_logic_vector(0 to 31) := X"00000004";
constant STATUS_OFFSET : std_logic_vector(0 to 31) := X"00000004";
constant IN_FIFO_OFFSET : std_logic_vector(0 to 31) := X"00000000";
constant OUT_FIFO_OFFSET : std_logic_vector(0 to 31) := X"00000000";
constant REG_ADDR_OFFSET : std_logic_vector(0 to 31) := X"0000000C";
constant REG_DATA_OFFSET : std_logic_vector(0 to 31) := X"00000008";
constant REG_DATA_WRITE_OFFSET : std_logic_vector(0 to 31) := X"00000008";
constant FIFO_CLEAR_MASK : std_logic_vector(0 to 31) := X"00000003";
constant ENABLE_PLAY_INT_MASK : std_logic_vector(0 to 31) := X"00000004";
end testbench_ac97_package;
package body testbench_ac97_package is
procedure delay(signal sig : in std_logic; constant cycles : in integer) is
begin
for i in cycles-1 downto 0 loop
wait until sig'event and sig='1';
end loop;
end delay;
procedure write_opb(signal OPB_Clk : in std_logic;
signal xferAck : in std_logic;
constant address : in std_logic_vector(0 to 31);
constant data : in std_logic_vector(0 to 31);
signal OPB_select : out std_logic;
signal OPB_RNW : out std_logic;
signal OPB_ABus : out std_logic_vector(0 to 31);
signal OPB_DBus : out std_logic_vector(0 to 31)
) is
begin
wait until opb_clk'event and opb_clk='0';
OPB_select <= '1';
OPB_ABus <= address;
OPB_DBus <= data;
OPB_RNW <= '0';
wait until opb_clk'event and opb_clk='1' and xferAck='1';
OPB_select <= '0';
OPB_ABus <= X"0000_0000";
OPB_DBus <= X"0000_0000";
for i in 15 downto 0 loop
wait until opb_clk'event and opb_clk='0';
end loop;
end write_opb;
procedure read_opb (signal OPB_Clk : in std_logic;
signal xferAck : in std_logic;
constant address : in std_logic_vector(0 to 31);
signal OPB_select : out std_logic;
signal OPB_RNW : out std_logic;
signal OPB_ABus : out std_logic_vector(0 to 31);
signal OPB_DBus : out std_logic_vector(0 to 31)
) is
begin
wait until opb_clk'event and opb_clk='0';
OPB_select <= '1';
OPB_ABus <= address;
OPB_DBus <= X"0000_0000";
OPB_RNW <= '1';
wait until opb_clk'event and opb_clk='1' and xferAck='1';
OPB_select <= '0';
OPB_ABus <= X"0000_0000";
OPB_RNW <= '0';
for i in 15 downto 0 loop
wait until opb_clk'event and opb_clk='0';
end loop;
end read_opb;
procedure write_ip (signal Bus2IP_Clk : in std_logic;
constant address : in std_logic_vector(0 to 31);
constant data : in std_logic_vector(0 to 31);
signal Bus2IP_CS : out std_logic;
signal Bus2IP_Addr : out std_logic_vector(0 to 31);
signal Bus2IP_Data : out std_logic_vector(0 to 31);
signal Bus2IP_WrCE : out std_logic
) is
begin
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
Bus2IP_Addr <= address;
Bus2IP_Data <= data;
Bus2IP_CS <= '1';
Bus2IP_WrCE <= '1';
--wait until Bus2IP_Clk'event and Bus2IP_Clk='1' and IP2Bus_Ack='1';
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
Bus2IP_Addr <= (others => '0');
Bus2IP_CS <= '0';
Bus2IP_Data <= (others => '0');
Bus2IP_WrCE <= '0';
for i in 15 downto 0 loop
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
end loop;
end write_ip;
procedure read_ip (signal Bus2IP_Clk : in std_logic;
signal IP2bus_Data : in std_logic_vector(0 to 31);
constant address : in std_logic_vector(0 to 31);
signal Bus2IP_CS : out std_logic;
signal Bus2IP_Addr : out std_logic_vector(0 to 31);
signal Bus2IP_RdCE : out std_logic;
signal IP_READ : out std_logic_vector(0 to 31)
) is
begin
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
Bus2IP_Addr <= address;
Bus2IP_CS <= '1';
Bus2IP_RdCE <= '1';
--wait until Bus2IP_Clk'event and Bus2IP_Clk='1' and IP2Bus_Ack='1';
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
IP_READ <= IP2Bus_Data;
Bus2IP_Addr <= (others => '0');
Bus2IP_CS <= '0';
Bus2IP_RdCE <= '0';
for i in 15 downto 0 loop
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
end loop;
end read_ip;
procedure send_frame (signal clk : in std_logic;
variable slot0 : in std_logic_vector(15 downto 0);
variable slot1 : in std_logic_vector(19 downto 0);
variable slot2 : in std_logic_vector(19 downto 0);
variable slot3 : in std_logic_vector(19 downto 0);
variable slot4 : in std_logic_vector(19 downto 0);
variable slot5 : in std_logic_vector(19 downto 0);
variable slot6 : in std_logic_vector(19 downto 0);
variable slot7 : in std_logic_vector(19 downto 0);
variable slot8 : in std_logic_vector(19 downto 0);
variable slot9 : in std_logic_vector(19 downto 0);
variable slot10 : in std_logic_vector(19 downto 0);
variable slot11 : in std_logic_vector(19 downto 0);
variable slot12 : in std_logic_vector(19 downto 0);
signal SData_In : out std_logic) is
variable shift_16 : std_logic_vector(15 downto 0);
variable shift_20 : std_logic_vector(19 downto 0);
begin
-- Slot 0
shift_16 := slot0;
slot0_loop: for i in 15 downto 0 loop
sdata_in <= shift_16(i);
wait until clk'event and clk='1';
end loop;
-- Slot 1
shift_20 := slot1;
slot1_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 2
shift_20 := slot2;
slot2_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 3
shift_20 := slot3;
slot3_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 4
shift_20 := slot4;
slot4_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 5
shift_20 := slot5;
slot5_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 6
shift_20 := slot6;
slot6_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 7
shift_20 := slot7;
slot7_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 8
shift_20 := slot8;
slot8_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 9
shift_20 := slot9;
slot9_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 10
shift_20 := slot10;
slot10_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 11
shift_20 := slot11;
slot11_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 12
shift_20 := slot12;
slot12_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
end send_frame;
procedure send_basic_frame (signal clk : in std_logic;
variable slot0 : in std_logic_vector(15 downto 0);
variable slot1 : in std_logic_vector(19 downto 0);
variable slot2 : in std_logic_vector(19 downto 0);
variable slot3 : in std_logic_vector(19 downto 0);
variable slot4 : in std_logic_vector(19 downto 0);
signal SData_In : out std_logic) is
variable slot5 : std_logic_vector(19 downto 0) := X"00000";
variable slot6 : std_logic_vector(19 downto 0) := X"00000";
variable slot7 : std_logic_vector(19 downto 0) := X"00000";
variable slot8 : std_logic_vector(19 downto 0) := X"00000";
variable slot9 : std_logic_vector(19 downto 0) := X"00000";
variable slot10 : std_logic_vector(19 downto 0) := X"00000";
variable slot11 : std_logic_vector(19 downto 0) := X"00000";
variable slot12 : std_logic_vector(19 downto 0) := X"00000";
begin
send_frame(clk, slot0, slot1, slot2, slot3, slot4,
slot5, slot6, slot7, slot8, slot9, slot10, slot11,
slot12,sdata_in);
end send_basic_frame;
end testbench_ac97_package;
|
gpl-3.0
|
fc890848e8ae02dd15bedcbcad052d1c
| 0.492015 | 4.034138 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S8_S144.vhd
| 1 | 12,643 |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S8_S144.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (8 and 128) --
-- made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S8_S144 is
port (ADDRA : in STD_LOGIC_VECTOR (12 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DIA : in STD_LOGIC_VECTOR (7 downto 0);
DIB : in STD_LOGIC_VECTOR (127 downto 0);
DIPB : in STD_LOGIC_VECTOR (15 downto 0);
WEA : in STD_LOGIC;
WEB : in STD_LOGIC;
CLKA : in STD_LOGIC;
CLKB : in STD_LOGIC;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
DOA : out STD_LOGIC_VECTOR (7 downto 0);
DOB : out STD_LOGIC_VECTOR (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end entity BRAM_S8_S144;
architecture BRAM_S8_S144_arch of BRAM_S8_S144 is
component RAMB16_S2_S36
port (
ADDRA: IN std_logic_vector(12 downto 0);
ADDRB: IN std_logic_vector(8 downto 0);
DIA: IN std_logic_vector(1 downto 0);
DIB: IN std_logic_vector(31 downto 0);
DIPB: IN std_logic_vector(3 downto 0);
WEA: IN std_logic;
WEB: IN std_logic;
CLKA: IN std_logic;
CLKB: IN std_logic;
SSRA: IN std_logic;
SSRB: IN std_logic;
ENA: IN std_logic;
ENB: IN std_logic;
DOA: OUT std_logic_vector(1 downto 0);
DOB: OUT std_logic_vector(31 downto 0);
DOPB: OUT std_logic_vector(3 downto 0));
END component;
signal doa1 : std_logic_vector (1 downto 0);
signal dob1 : std_logic_vector (31 downto 0);
signal doa2 : std_logic_vector (1 downto 0);
signal dob2 : std_logic_vector (31 downto 0);
signal doa3 : std_logic_vector (1 downto 0);
signal dob3 : std_logic_vector (31 downto 0);
signal doa4 : std_logic_vector (1 downto 0);
signal dob4 : std_logic_vector (31 downto 0);
signal dia1 : std_logic_vector (1 downto 0);
signal dib1 : std_logic_vector (31 downto 0);
signal dia2 : std_logic_vector (1 downto 0);
signal dib2 : std_logic_vector (31 downto 0);
signal dia3 : std_logic_vector (1 downto 0);
signal dib3 : std_logic_vector (31 downto 0);
signal dia4 : std_logic_vector (1 downto 0);
signal dib4 : std_logic_vector (31 downto 0);
begin
dib1(1 downto 0) <= DIB(1 downto 0);
dib2(1 downto 0) <= DIB(3 downto 2);
dib3(1 downto 0) <= DIB(5 downto 4);
dib4(1 downto 0) <= DIB(7 downto 6);
dib1(3 downto 2) <= DIB(9 downto 8);
dib2(3 downto 2) <= DIB(11 downto 10);
dib3(3 downto 2) <= DIB(13 downto 12);
dib4(3 downto 2) <= DIB(15 downto 14);
dib1(5 downto 4) <= DIB(17 downto 16);
dib2(5 downto 4) <= DIB(19 downto 18);
dib3(5 downto 4) <= DIB(21 downto 20);
dib4(5 downto 4) <= DIB(23 downto 22);
dib1(7 downto 6) <= DIB(25 downto 24);
dib2(7 downto 6) <= DIB(27 downto 26);
dib3(7 downto 6) <= DIB(29 downto 28);
dib4(7 downto 6) <= DIB(31 downto 30);
dib1(9 downto 8) <= DIB(33 downto 32);
dib2(9 downto 8) <= DIB(35 downto 34);
dib3(9 downto 8) <= DIB(37 downto 36);
dib4(9 downto 8) <= DIB(39 downto 38);
dib1(11 downto 10) <= DIB(41 downto 40);
dib2(11 downto 10) <= DIB(43 downto 42);
dib3(11 downto 10) <= DIB(45 downto 44);
dib4(11 downto 10) <= DIB(47 downto 46);
dib1(13 downto 12) <= DIB(49 downto 48);
dib2(13 downto 12) <= DIB(51 downto 50);
dib3(13 downto 12) <= DIB(53 downto 52);
dib4(13 downto 12) <= DIB(55 downto 54);
dib1(15 downto 14) <= DIB(57 downto 56);
dib2(15 downto 14) <= DIB(59 downto 58);
dib3(15 downto 14) <= DIB(61 downto 60);
dib4(15 downto 14) <= DIB(63 downto 62);
dib1(17 downto 16) <= DIB(65 downto 64);
dib2(17 downto 16) <= DIB(67 downto 66);
dib3(17 downto 16) <= DIB(69 downto 68);
dib4(17 downto 16) <= DIB(71 downto 70);
dib1(19 downto 18) <= DIB(73 downto 72);
dib2(19 downto 18) <= DIB(75 downto 74);
dib3(19 downto 18) <= DIB(77 downto 76);
dib4(19 downto 18) <= DIB(79 downto 78);
dib1(21 downto 20) <= DIB(81 downto 80);
dib2(21 downto 20) <= DIB(83 downto 82);
dib3(21 downto 20) <= DIB(85 downto 84);
dib4(21 downto 20) <= DIB(87 downto 86);
dib1(23 downto 22) <= DIB(89 downto 88);
dib2(23 downto 22) <= DIB(91 downto 90);
dib3(23 downto 22) <= DIB(93 downto 92);
dib4(23 downto 22) <= DIB(95 downto 94);
dib1(25 downto 24) <= DIB(97 downto 96);
dib2(25 downto 24) <= DIB(99 downto 98);
dib3(25 downto 24) <= DIB(101 downto 100);
dib4(25 downto 24) <= DIB(103 downto 102);
dib1(27 downto 26) <= DIB(105 downto 104);
dib2(27 downto 26) <= DIB(107 downto 106);
dib3(27 downto 26) <= DIB(109 downto 108);
dib4(27 downto 26) <= DIB(111 downto 110);
dib1(29 downto 28) <= DIB(113 downto 112);
dib2(29 downto 28) <= DIB(115 downto 114);
dib3(29 downto 28) <= DIB(117 downto 116);
dib4(29 downto 28) <= DIB(119 downto 118);
dib1(31 downto 30) <= DIB(121 downto 120);
dib2(31 downto 30) <= DIB(123 downto 122);
dib3(31 downto 30) <= DIB(125 downto 124);
dib4(31 downto 30) <= DIB(127 downto 126);
-------------------------------------------
DOB(1 downto 0) <= dob1(1 downto 0);
DOB(3 downto 2) <= dob2(1 downto 0);
DOB(5 downto 4) <= dob3(1 downto 0);
DOB(7 downto 6) <= dob4(1 downto 0);
DOB(9 downto 8) <= dob1(3 downto 2);
DOB(11 downto 10) <= dob2(3 downto 2);
DOB(13 downto 12) <= dob3(3 downto 2);
DOB(15 downto 14) <= dob4(3 downto 2);
DOB(17 downto 16) <= dob1(5 downto 4);
DOB(19 downto 18) <= dob2(5 downto 4);
DOB(21 downto 20) <= dob3(5 downto 4);
DOB(23 downto 22) <= dob4(5 downto 4);
DOB(25 downto 24) <= dob1(7 downto 6);
DOB(27 downto 26) <= dob2(7 downto 6);
DOB(29 downto 28) <= dob3(7 downto 6);
DOB(31 downto 30) <= dob4(7 downto 6);
DOB(33 downto 32) <= dob1(9 downto 8);
DOB(35 downto 34) <= dob2(9 downto 8);
DOB(37 downto 36) <= dob3(9 downto 8);
DOB(39 downto 38) <= dob4(9 downto 8);
DOB(41 downto 40) <= dob1(11 downto 10);
DOB(43 downto 42) <= dob2(11 downto 10);
DOB(45 downto 44) <= dob3(11 downto 10);
DOB(47 downto 46) <= dob4(11 downto 10);
DOB(49 downto 48) <= dob1(13 downto 12);
DOB(51 downto 50) <= dob2(13 downto 12);
DOB(53 downto 52) <= dob3(13 downto 12);
DOB(55 downto 54) <= dob4(13 downto 12);
DOB(57 downto 56) <= dob1(15 downto 14);
DOB(59 downto 58) <= dob2(15 downto 14);
DOB(61 downto 60) <= dob3(15 downto 14);
DOB(63 downto 62) <= dob4(15 downto 14);
--------------------------------------------
DOB(65 downto 64) <= dob1(17 downto 16);
DOB(67 downto 66) <= dob2(17 downto 16);
DOB(69 downto 68) <= dob3(17 downto 16);
DOB(71 downto 70) <= dob4(17 downto 16);
DOB(73 downto 72) <= dob1(19 downto 18);
DOB(75 downto 74) <= dob2(19 downto 18);
DOB(77 downto 76) <= dob3(19 downto 18);
DOB(79 downto 78) <= dob4(19 downto 18);
DOB(81 downto 80) <= dob1(21 downto 20);
DOB(83 downto 82) <= dob2(21 downto 20);
DOB(85 downto 84) <= dob3(21 downto 20);
DOB(87 downto 86) <= dob4(21 downto 20);
DOB(89 downto 88) <= dob1(23 downto 22);
DOB(91 downto 90) <= dob2(23 downto 22);
DOB(93 downto 92) <= dob3(23 downto 22);
DOB(95 downto 94) <= dob4(23 downto 22);
DOB(97 downto 96) <= dob1(25 downto 24);
DOB(99 downto 98) <= dob2(25 downto 24);
DOB(101 downto 100) <= dob3(25 downto 24);
DOB(103 downto 102) <= dob4(25 downto 24);
DOB(105 downto 104) <= dob1(27 downto 26);
DOB(107 downto 106) <= dob2(27 downto 26);
DOB(109 downto 108) <= dob3(27 downto 26);
DOB(111 downto 110) <= dob4(27 downto 26);
DOB(113 downto 112) <= dob1(29 downto 28);
DOB(115 downto 114) <= dob2(29 downto 28);
DOB(117 downto 116) <= dob3(29 downto 28);
DOB(119 downto 118) <= dob4(29 downto 28);
DOB(121 downto 120) <= dob1(31 downto 30);
DOB(123 downto 122) <= dob2(31 downto 30);
DOB(125 downto 124) <= dob3(31 downto 30);
DOB(127 downto 126) <= dob4(31 downto 30);
dia1 <= DIA(1 downto 0);
dia2 <= DIA(3 downto 2);
dia3 <= DIA(5 downto 4);
dia4 <= DIA(7 downto 6);
DOA(1 downto 0) <= doa1;
DOA(3 downto 2) <= doa2;
DOA(5 downto 4) <= doa3;
DOA(7 downto 6) <= doa4;
bram1: RAMB16_S2_S36
port map (
ADDRA => addra(12 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIB => dib1,
DIPB => dipb(3 downto 0),
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOB => dob1,
DOPB => dopb(3 downto 0));
bram2: RAMB16_S2_S36
port map (
ADDRA => addra(12 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIB => dib2,
DIPB => dipb(7 downto 4),
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOB => dob2,
DOPB => dopb(7 downto 4));
bram3: RAMB16_S2_S36
port map (
ADDRA => addra(12 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia3,
DIB => dib3,
DIPB => dipb(11 downto 8),
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa3,
DOB => dob3,
DOPB => dopb(11 downto 8));
bram4: RAMB16_S2_S36
port map (
ADDRA => addra(12 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia4,
DIB => dib4,
DIPB => dipb(15 downto 12),
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa4,
DOB => dob4,
DOPB => dopb(15 downto 12));
end BRAM_S8_S144_arch;
|
gpl-3.0
|
0d63aa8f40a25df0168bb1a5d419c807
| 0.486435 | 3.657217 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/vector_heater_a_v1_00_a/hdl/vhdl/vector_heater_a.vhd
| 1 | 21,648 |
------------------------------------------------------------------------------
-- vector_heater_a.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: vector_heater_a.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Feb 28 11:50:03 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library vector_heater_a_v1_00_a;
use vector_heater_a_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity vector_heater_a is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity vector_heater_a;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of vector_heater_a is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity vector_heater_a_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
gpl-3.0
|
f7aad06bbe66d865d743c52ac390f821
| 0.448864 | 4.483844 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/generic_spram.vhd
| 1 | 5,219 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
entity generic_spram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 1024;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := false;
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "write_first";
g_init_file : string := ""
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- byte write enable, actiwe when g_
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
-- global write enable (masked by bwe_i if g_with_byte_enable = true)
we_i : in std_logic;
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data input
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_spram;
architecture syn of generic_spram is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
type t_string_file_type is file of string;
impure function f_bitstring_2_slv(s : string; num_bits : integer) return std_logic_vector is
begin
end function f_bitstring_2_slv;
impure function f_load_from_file(file_name : string) return t_ram_type is
file f : t_string_file_type;
variable fstatus : file_open_status;
begin
file_open(fstatus, f, file_name, read_mode);
if(fstatus /= open_ok) then
report "generic_spram: Cannot open memory initialization file: " & file_name severity failure;
end if;
end function f_load_from_file;
signal ram : t_ram_type;
signal s_we : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in : std_logic_vector(g_data_width-1 downto 0);
signal s_ram_out : std_logic_vector(g_data_width-1 downto 0);
begin
assert (g_init_file = "" or g_init_file = "none")
report "generic_spram: Memory initialization files not supported yet. Sorry :("
severity failure;
gen_with_byte_enable_writefirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "write_first") generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
begin
for i in 0 to c_num_bytes-1 loop
if s_we(i) = '1' then
s_ram_in(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
s_ram_out(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
else
s_ram_in(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
s_ram_out(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
end if;
end loop; -- i
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
ram(conv_integer(unsigned(a_i))) <= s_ram_in;
q_o <= s_ram_out;
end if;
end process;
end generate gen_with_byte_enable_writefirst;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
begin
for i in 0 to c_num_bytes-1 loop
if (s_we(i) = '1') then
s_ram_in(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
else
s_ram_in(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
ram(conv_integer(unsigned(a_i))) <= s_ram_in;
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(we_i = '1') then
ram(conv_integer(unsigned(a_i))) <= d_i;
q_o <= d_i;
else
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(we_i = '1') then
ram(conv_integer(unsigned(a_i))) <= d_i;
end if;
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end process;
end generate gen_without_byte_enable_readfirst;
end syn;
|
lgpl-3.0
|
cf92e276d394c219be97d172e2d50131
| 0.57808 | 3.172644 | false | false | false | false |
luebbers/reconos
|
demos/sort_demo_thermal/hw/src/sort8k.vhd
| 3 | 6,182 |
--
-- sort8k.vhd
-- eCos hardware thread using the bubble_sort module and mailboxes to
-- sort 8k-sized blocks of data in main memory. The incoming messages
-- on C_MB_START contain the addresses of the blocks, and an arbitrary
-- message sent to C_MB_DONE signals completion of the sorting process.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sort8k is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end sort8k;
architecture Behavioral of sort8k is
component bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (STATE_GET, STATE_READ, STATE_SORT, STATE_WAIT, STATE_WRITE, STATE_PUT);
signal state : t_state := STATE_GET;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- handshaking signals
signal sort_start : std_logic := '0';
signal sort_done : std_logic;
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => 2048,
G_AWIDTH => C_BURST_AWIDTH,
G_DWIDTH => C_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
o_RAMAddr => RAMAddr,
o_RAMData => o_RAMData,
i_RAMData => i_RAMData,
o_RAMWE => o_RAMWE,
start => sort_start,
done => sort_done
);
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
sort_start <= '0';
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- wait for/get data address. No error checking is done here.
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, address);
if done then
burst_counter := 0;
state <= STATE_READ;
end if;
-- read data from main memory into local burst RAM.
when STATE_READ =>
reconos_read_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_SORT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- start sorting module
when STATE_SORT =>
sort_start <= '1';
state <= STATE_WAIT;
-- wait for sort completion
when STATE_WAIT =>
sort_start <= '0';
if sort_done = '1' then
burst_counter := 0;
state <= STATE_WRITE;
end if;
-- write sorted data back to main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_PUT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- write message to DONE mailbox
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, address);
if done then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
f7361b73eec6bdee69c4784d44696036
| 0.544484 | 3.905243 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a/simulation/behavioral/my_core_wrapper.vhd
| 1 | 4,764 |
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_osif_tb_v2_01_a;
use xps_osif_tb_v2_01_a.all;
entity my_core_wrapper is
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end my_core_wrapper;
architecture STRUCTURE of my_core_wrapper is
component xps_osif_tb is
generic (
C_FAMILY : string;
C_MPLB_AWIDTH : integer;
C_MPLB_DWIDTH : integer;
C_MPLB_NATIVE_DWIDTH : integer;
C_MPLB_P2P : integer;
C_MPLB_SMALLEST_SLAVE : integer;
C_MPLB_CLK_PERIOD_PS : integer
);
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to (1));
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8-1));
M_MSize : out std_logic_vector(0 to (1));
M_size : out std_logic_vector(0 to (3));
M_type : out std_logic_vector(0 to (2));
M_TAttribute : out std_logic_vector(0 to (15));
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to (31));
M_ABus : out std_logic_vector(0 to (31));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to (1));
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to ((C_MPLB_DWIDTH-1)));
PLB_MRdWdAddr : in std_logic_vector(0 to (3));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
begin
my_core : xps_osif_tb
generic map (
C_FAMILY => "virtex5",
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 128,
C_MPLB_NATIVE_DWIDTH => 64,
C_MPLB_P2P => 0,
C_MPLB_SMALLEST_SLAVE => 128,
C_MPLB_CLK_PERIOD_PS => 10000
)
port map (
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
SYNCH_IN => SYNCH_IN,
SYNCH_OUT => SYNCH_OUT
);
end architecture STRUCTURE;
|
gpl-3.0
|
2312c66ab9c1b20fffd4983211248897
| 0.569899 | 3.201613 | false | false | false | false |
luebbers/reconos
|
core/pcores/cpu_hwt_bram_logic_v1_00_a/hdl/vhdl/cpu_hwt_bram_logic.vhd
| 1 | 5,620 |
--
-- \file cpu_hwt_bram_logic.vhd
--
-- BRAM control logic for CPU-HW threads
--
-- This BRAM is used to store the CPU reset vectors for switching software
-- threads.
--
-- \author Robert Meiche <[email protected]>
-- \date 22.09.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cpu_hwt_bram_logic is
generic (
BRAM_DWIDTH : integer := 64;
BRAM_AWIDTH : integer := 32;
CPU_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
--CPU Ports
CPU0_boot_sect_ready : out std_logic;
CPU0_set_boot_sect : in std_logic;
CPU0_boot_sect_data : in std_logic_vector(CPU_DWIDTH-1 downto 0);
CPU1_boot_sect_ready : out std_logic;
CPU1_set_boot_sect : in std_logic;
CPU1_boot_sect_data : in std_logic_vector(CPU_DWIDTH-1 downto 0);
--BRAM Ports
BRAM_Rst : out std_logic;
BRAM_CLK : out std_logic;
BRAM_EN : out std_logic;
BRAM_WEN : out std_logic_vector(0 to BRAM_DWIDTH/8-1); --Qualified WE
BRAM_Addr : out std_logic_vector(0 to BRAM_AWIDTH-1);
BRAM_Dout : out std_logic_vector(0 to BRAM_DWIDTH-1);
BRAM_Din : in std_logic_vector(0 to BRAM_DWIDTH-1)
);
end cpu_hwt_bram_logic;
architecture synth of cpu_hwt_bram_logic is
signal write_bootcode : std_logic;
signal bram_boot_data : std_logic_vector(0 to CPU_DWIDTH-1);
signal bram_boot_addr : std_logic_vector(0 to BRAM_AWIDTH-1);
signal ready_sigs: std_logic_vector(0 to 1); --connects the ready signals
signal set_sigs: std_logic_vector(0 to 1); --connects the set signals
--------------- state machine states
type SM_TYPE is (IDLE, WRITE, READY, WAIT_UNTIL_SET_ZERO);
signal state : SM_TYPE;
begin
CPU0_boot_sect_ready <= ready_sigs(0);
CPU1_boot_sect_ready <= ready_sigs(1);
set_sigs <= CPU0_set_boot_sect & CPU1_set_boot_sect;
BRAM_Rst <= reset;
BRAM_CLK <= clk;
BRAMWRITE: process(clk)
begin
if rising_edge(clk) then
if write_bootcode = '1' then
BRAM_EN <= '1';
BRAM_WEN <= "00001111";
BRAM_Dout <= X"deadbeef" & bram_boot_data;
BRAM_Addr <= bram_boot_addr;
else
BRAM_EN <= '0';
BRAM_WEN <= "00000000";
BRAM_Dout <= (others =>'0');
BRAM_Addr <= (others =>'0');
end if; --write_bootcode
end if;
end process;
BRAM_LOGIC_SM: process(clk, reset)
variable bootcode : std_logic_vector(CPU_DWIDTH-1 downto 0);
variable whichCPU : integer;
begin
if reset = '1' then
bram_boot_addr <= (others =>'0');
bram_boot_data <= (others =>'0');
write_bootcode <= '0';
state <= IDLE;
elsif rising_edge(clk) then
case state is
when IDLE =>
write_bootcode <= '0';
if CPU0_set_boot_sect = '1' then
bootcode:= CPU0_boot_sect_data;
whichCPU:= 0;
state <= WRITE;
elsif CPU1_set_boot_sect = '1' then
bootcode:= CPU1_boot_sect_data;
whichCPU:= 1;
state <= WRITE;
end if;
when WRITE =>
write_bootcode <= '1';
bram_boot_data <= bootcode;
bram_boot_addr <= X"FFFFFFFC";
state <= READY;
when READY =>
write_bootcode <= '1';
ready_sigs(whichCPU) <= '1';
state <= WAIT_UNTIL_SET_ZERO;
when WAIT_UNTIL_SET_ZERO =>
write_bootcode <= '0';
--after the ready signal for the corresponding CPU is set, the state machine
--waits that the cpu set its set-signal back to zero (then the cpu has booted correctly
-- and another CPU can now have the bootaddress 0xFFFFFFFC)
if set_sigs(whichCPU) = '0' then
ready_sigs(whichCPU) <= '0';
state <= IDLE;
else
ready_sigs(whichCPU) <= '1';
state <= WAIT_UNTIL_SET_ZERO;
end if;
when others =>
state <= IDLE;
end case;
end if;
end process;
end synth;
|
gpl-3.0
|
d815f7e11be6d38069ef074f8646da9b
| 0.526335 | 3.908206 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_subtypes.vhd
| 2 | 1,354 |
-- Copyright (c) 2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for subtype definitions.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
use work.vhdl_subtypes_pkg.all;
entity vhdl_subtypes is
port( a : out int_type_const;
b : out int_type;
c : out int_type_downto;
d : out time_type;
e : out uns_type_const
);
end vhdl_subtypes;
architecture test of vhdl_subtypes is
begin
process
begin
a <= 1;
b <= 2;
c <= 3;
d <= 4 s;
e <= 5;
wait;
end process;
end test;
|
gpl-2.0
|
89010b631df16bc0f58637de819be1b2
| 0.667651 | 3.835694 | false | true | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/framework/observation.vhd
| 1 | 41,201 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity observation is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- CHANGE 1 OF 7
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
-- END CHANGE
);
end observation;
architecture Behavioral of observation is
component uf_extract_observation is
Port(
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input/measurement data address
input_data_address : in std_logic_vector(0 to 31);
-- get data block
get_data_needed : out std_logic;
get_data_address : out std_logic_vector(0 to 31);
get_data_length : out integer;
-- receive data block
receive_data_en : in std_logic;
receive_data_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- recieved data
receive_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_LENGTH_LAST_BURST,
STATE_LENGTH_LAST_BURST_2,
STATE_READ_OBSERVATION_ARRAY_ADDRESS,
STATE_READ_INPUT_DATA_LINK_ADDRESS,
STATE_READ_PARAMETER_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_COPY_PARAMETER_ACK,
STATE_WAIT_FOR_MESSAGE,
STATE_READ_NEXT_PARTICLE,
STATE_READ_NEXT_PARTICLE_2,
STATE_READ_NEXT_PARTICLE_3,
STATE_READ_NEXT_PARTICLE_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_READ_INPUT_DATA_ADDRESS,
STATE_START_EXTRACT_OBSERVATION,
STATE_START_EXTRACT_OBSERVATION_WAIT,
STATE_EXTRACT_OBSERVATION,
STATE_GET_DATA,
STATE_GET_DATA_2,
STATE_GET_DATA_3,
STATE_GET_DATA_4,
STATE_GET_DATA_5,
STATE_GET_DATA_6,
STATE_GET_DATA_ACK,
STATE_GET_DATA_ACK_2,
STATE_WRITE_OBSERVATION,
STATE_WRITE_OBSERVATION_2,
STATE_WRITE_OBSERVATION_3,
STATE_WRITE_OBSERVATION_4,
STATE_MORE_PARTICLES,
STATE_MORE_PARTICLES_2,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2 );
-- current state
signal state : t_state := STATE_INIT;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--local RAM cache addresses
--signal local_ram_cache_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := "00000000000000000001111110000000";
--signal local_ram_cache_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := "11111100000";
signal local_ram_address_part_1_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := "00000000000";
signal local_ram_address_part_2_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := "10000000000";
signal local_ram_address_current_part_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := "10000000000";
--signal cache_min : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--signal cache_max : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- lin/pointer to memory word, where the input address is stored
signal input_data_link_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of observations
signal remaining_observations : integer := 2;
-- number of needed bursts
signal number_of_bursts : integer := 3;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 3;
-- length of last burst
signal length_of_last_burst : integer := 7;
-- size of a particle
signal particle_size : integer := 64;
-- number of particles
signal N : integer := 20;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal cache_offset : integer := 0;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 2;
-- counter for particle data
signal counter : integer := 0;
-- current particle data
signal particle_data : integer := 0;
-- parameter address
signal parameter_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter size
signal parameter_size : integer := 0;
-- parameter loaded
signal parameter_loaded : std_logic := '0';
-- parameters acknowledged by user process
signal parameter_loaded_ack : std_logic := '0';
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- new particle loaded
signal new_particle : std_logic := '0';
-- new particle loaded - ackowledgement
signal new_particle_ack : std_logic := '1';
-- input data address
signal input_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- input data length
signal get_data_length : integer := 0;
-- input data needed signal
signal get_data_needed : std_logic := '0';
-- word data address
signal get_data_address : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- word data enable
signal receive_data_en : std_logic := '0';
-- word address
signal receive_data_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- word_ack
signal receive_data_ack : std_logic := '0';
-- if the observation is extracted, this signal is set to '1'
signal finished : std_logic := '1';
-- number of get data bursts
signal number_of_data_bursts : integer := 0;
-- length of last get data burst
signal length_of_last_data_burst : integer := 0;
-- data burst counter
signal data_burst_counter : integer := 0;
--current address
signal current_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- for switch 1: corrected local ram address. the least bit is inverted,
-- -- because else the local ram will be used incorrect
signal o_RAMAddrExtractObservation : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this observation thread
signal o_RAMAddrObservation : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEExtractObservation : std_logic := '0';
-- for switch 2: Write enable, observation
signal o_RAMWEObservation : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataExtractObservation : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, observation
signal o_RAMDataObservation : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_extract_observation
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrExtractObservation,
o_RAMData=>o_RAMDataExtractObservation, i_RAMData=>i_RAMData,
o_RAMWE=>o_RAMWEExtractObservation, o_RAMClk=>o_RAMClk,
parameter_loaded=>parameter_loaded, parameter_loaded_ack=>parameter_loaded_ack,
new_particle=>new_particle, new_particle_ack=>new_particle_ack,
input_data_address=>input_data_address, get_data_needed=>get_data_needed,
get_data_address=>get_data_address, get_data_length=>get_data_length,
receive_data_en=>receive_data_en, receive_data_address=>receive_data_address,
receive_data_ack=>receive_data_ack,
init=>init, enable=>enable, finished=>finished);
-- -- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrExtractObservation(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrExtractObservation(C_TASK_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrObservation(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrObservation(C_TASK_BURST_AWIDTH-1);
--
-- switch 2: write enable
o_RAMWE <= o_RAMWEExtractObservation when enable = '1' else o_RAMWEObservation;
--
-- switch 3: output ram data
o_RAMData <= o_RAMDataExtractObservation when enable = '1' else o_RAMDataObservation;
-----------------------------------------------------------------------------
--
-- ReconOS State Machine for Observation:
--
-----------------------------------------------------------------------------
--
-- 1) read data from information struct + load parameter
--
-- 2) receive message m
--
-- 3) set current address for input data
--
-- 4) load current particle (into local rahttp://www.eintracht.de/aktuell/m, starting address (others=>'0'))
--
-- 5) start user process for observation extraction
--
-- 6) wait for finished signal of user process
--
-- 7) write observation into main memory (from local ram, starting address (others=>'0'))
--
-- 8) if more particle need to be processed
-- go to step 4
-- else
-- go to step 9
--
-- 9) send message m
--
-- 9*) send measurement
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--variable get_data_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_data_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable parameter_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case (state) is
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
if done then
enable <= '0';
parameter_loaded <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
new_particle <= '0';
state <= STATE_READ_PARTICLE_ADDRESS;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ INFORMATION_STRUCT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
new_particle <= '0';
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
state <= STATE_LENGTH_LAST_BURST;
when STATE_LENGTH_LAST_BURST =>
--! calculate number of reads (1 of 2)
length_of_last_burst <= observation_size mod 128;
state <= STATE_LENGTH_LAST_BURST_2;
when STATE_LENGTH_LAST_BURST_2 =>
--! calculate number of reads (2 of 2)
length_of_last_burst <= length_of_last_burst / 8;
state <= STATE_READ_OBSERVATION_ARRAY_ADDRESS;
when STATE_READ_OBSERVATION_ARRAY_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_INPUT_DATA_LINK_ADDRESS;
end if;
when STATE_READ_INPUT_DATA_LINK_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+24, input_data_link_address);
if done then
state <= STATE_READ_PARAMETER_SIZE;
end if;
when STATE_READ_PARAMETER_SIZE =>
--! read parameter size
reconos_read (done, o_osif, i_osif, information_struct+28, parameter_size_var);
if done then
parameter_size <= TO_INTEGER(SIGNED(parameter_size_var));
state <= STATE_READ_PARAMETER_ADDRESS;
end if;
when STATE_READ_PARAMETER_ADDRESS =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, information_struct+32, parameter_address);
if done then
state <= STATE_COPY_PARAMETER;
local_ram_address_if <= local_ram_start_address_if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ PARAMETERS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_COPY_PARAMETER =>
--! read parameter size
o_RAMWEObservation <= '0';
if (parameter_size > 0) then
parameter_size <= parameter_size - 1;
state <= STATE_COPY_PARAMETER_2;
else
state <= STATE_COPY_PARAMETER_ACK;
parameter_loaded <= '1';
enable <= '1';
init <= '0';
end if;
when STATE_COPY_PARAMETER_2 =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, parameter_address, ram_data);
if done then
state <= STATE_COPY_PARAMETER_3;
end if;
when STATE_COPY_PARAMETER_3 =>
--! read parameter size
parameter_address <= parameter_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
enable <= '0';
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
o_RAMDataObservation <= ram_data;
state <= STATE_COPY_PARAMETER;
when STATE_COPY_PARAMETER_ACK =>
--! read parameter size
if (parameter_loaded_ack = '1') then
enable <= '0';
init <= '1';
parameter_loaded <= '0';
state <= STATE_WAIT_FOR_MESSAGE;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 2: WAIT FOR MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
enable <= '0';
init <= '1';
parameter_loaded <= '0';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
temp <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
end if;
state <= STATE_READ_INPUT_DATA_ADDRESS;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 3: READ CURRENT INPUT DATA ADDRESS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_INPUT_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, input_data_link_address, input_data_address);
if done then
state <= STATE_READ_NEXT_PARTICLE;
end if;
-- CHANGE 5 of 7
-- input data address: 0x20000000
--input_data_address <= "00100000000000000000000000000000";
-- the particle array address: 0x10000000
--particle_array_address <= "00010000000000000000000000000000";
-- the observation array address: 0x11000000
--observation_array_address <= "00010001000000000000000000000000";
--state <= STATE_READ_NEXT_PARTICLE;
-- END CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 4: WRITE PARTICLE INTO CURRENT RAM
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_NEXT_PARTICLE =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
counter <= particle_size / 4;
local_ram_address_if <= local_ram_start_address_if;
state <= STATE_READ_NEXT_PARTICLE_2;
when STATE_READ_NEXT_PARTICLE_2 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
o_RAMWEObservation <= '0';
if (counter > 0) then
state <= STATE_READ_NEXT_PARTICLE_3;
counter <= counter - 1;
else
state <= STATE_START_EXTRACT_OBSERVATION;
end if;
when STATE_READ_NEXT_PARTICLE_3 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
reconos_read (done, o_osif, i_osif, particle_array_address, particle_data_var);
if done then
state <= STATE_READ_NEXT_PARTICLE_4;
particle_data <= TO_INTEGER(SIGNED(particle_data_var));
particle_array_address <= particle_array_address + 4;
end if;
when STATE_READ_NEXT_PARTICLE_4 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
local_ram_address_if <= local_ram_address_if + 1;
o_RAMDataObservation <= STD_LOGIC_VECTOR(TO_SIGNED(particle_data, 32));
state <= STATE_READ_NEXT_PARTICLE_2;
-- when STATE_READ_NEXT_PARTICLE =>
-- --! read next particle to local ram (writing the first 128 bytes to the local ram)
-- reconos_read_burst(done, o_osif, i_osif, local_ram_start_address, particle_array_address);
-- if done then
-- particle_array_address <= particle_array_address + particle_size;
-- state <= STATE_START_EXTRACT_OBSERVATION;
-- end if;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 5: START OBSERVATION EXTRACTION
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
when STATE_START_EXTRACT_OBSERVATION =>
--! start the user process
init <= '0';
enable <= '1';
new_particle <= '1';
state <= STATE_START_EXTRACT_OBSERVATION_WAIT;
when STATE_START_EXTRACT_OBSERVATION_WAIT =>
--! user process needs to start the execution
-- CHANGE CHANGE CHANGE
if new_particle_ack = '1' then
new_particle <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
-- END OF CHANGE CHANGE CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 6: WAIT FOR OBSERVATION EXTRACTION TO FINISH / ANSWER DATA CALLS INBETWEEN
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_EXTRACT_OBSERVATION =>
--! check if observation is finished, or it input data is needed (from cache)
if finished = '1' then
-- observation finished
enable <= '0';
init <= '1';
new_particle <= '0';
state <= STATE_WRITE_OBSERVATION;
elsif get_data_needed = '1' then
state <= STATE_GET_DATA;
end if;
when STATE_GET_DATA =>
--! calculate number of full bursts and length of last bursts
number_of_data_bursts <= get_data_length / 4;
state <= STATE_GET_DATA_2;
when STATE_GET_DATA_2 =>
--! calculate number of full bursts and length of last bursts
if (local_ram_address_current_part_if = local_ram_address_part_1_if) then
local_ram_address <= local_ram_start_address + 4096;
local_ram_address_if <= local_ram_address_part_2_if;
local_ram_address_current_part_if <= local_ram_address_part_2_if;
else
local_ram_address <= local_ram_start_address;
local_ram_address_if <= local_ram_address_part_1_if;
local_ram_address_current_part_if <= local_ram_address_part_1_if;
end if;
--number_of_data_bursts <= number_of_data_bursts + 2;
current_address <= get_data_address;
state <= STATE_GET_DATA_3;
when STATE_GET_DATA_3 =>
--! calculate number of full bursts and length of last bursts
o_RAMWEObservation <= '0';
enable <= '1';
if (number_of_data_bursts > 0) then
state <= STATE_GET_DATA_4;
number_of_data_bursts <= number_of_data_bursts - 1;
else
state <= STATE_GET_DATA_ACK;
end if;
when STATE_GET_DATA_4 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
reconos_read_s (done, o_osif, i_osif, current_address, ram_data);
if done then
state <= STATE_GET_DATA_5;
current_address <= current_address + 4;
end if;
when STATE_GET_DATA_5 =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
enable <= '0';
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
local_ram_address_if <= local_ram_address_if + 1;
o_RAMDataObservation <= ram_data;
state <= STATE_GET_DATA_3;
when STATE_GET_DATA_ACK =>
--! wait for acknowledgement
receive_data_en <= '1';
receive_data_address <= local_ram_address_current_part_if;
enable <= '1';
state <= STATE_GET_DATA_ACK_2;
when STATE_GET_DATA_ACK_2 =>
--! wait for acknowledgement
if receive_data_ack = '1' then
receive_data_en <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
-- when STATE_GET_DATA =>
-- --! calculate number of full bursts and length of last bursts
-- number_of_data_bursts <= get_data_length / 128;
-- length_of_last_data_burst <= get_data_length mod 128;
-- state <= STATE_GET_DATA_2;
--
--
-- when STATE_GET_DATA_2 =>
-- --! calculate number of full bursts and length of last bursts
-- if (length_of_last_data_burst > 0) then
-- length_of_last_data_burst <= length_of_last_data_burst + 8;
-- end if;
-- if (local_ram_address_current_part_if = local_ram_address_part_1_if) then
-- local_ram_address <= local_ram_start_address + 4096;
-- local_ram_address_current_part_if <= local_ram_address_part_2_if;
-- else
-- local_ram_address <= local_ram_start_address;
-- local_ram_address_current_part_if <= local_ram_address_part_1_if;
-- end if;
-- state <= STATE_GET_DATA_3;
--
--
-- when STATE_GET_DATA_3 =>
-- --! calculate number of full bursts and length of last bursts
-- length_of_last_data_burst <= length_of_last_data_burst / 8;
-- data_burst_counter <= 0;
-- if (get_data_address(29) = '0') then
-- -- double word aligned address
-- current_address <= get_data_address;
-- receive_data_address <= local_ram_address_current_part_if;
-- else
-- -- no double aligned address (=> change it)
-- current_address <= get_data_address - 4;
-- receive_data_address <= local_ram_address_current_part_if + 1;
-- end if;
-- state <= STATE_GET_DATA_4;
--
--
-- when STATE_GET_DATA_4 =>
-- --! read full data burst / last data burst
-- if (data_burst_counter < number_of_data_bursts) then
-- state <= STATE_GET_DATA_5;
-- data_burst_counter <= data_burst_counter + 1;
-- else
-- if (length_of_last_data_burst > 0) then
-- state <= STATE_GET_DATA_6;
-- else
-- state <= STATE_GET_DATA_ACK;
-- end if;
-- end if;
--
--
-- when STATE_GET_DATA_5 =>
-- --! read full data burst
-- reconos_read_burst(done, o_osif, i_osif, local_ram_address, current_address);
-- if done then
-- current_address <= current_address + 128;
-- local_ram_address <= local_ram_address + 128;
-- state <= STATE_GET_DATA_4;
-- end if;
--
--
-- when STATE_GET_DATA_6 =>
-- --! read last data burst (with defined length)
-- reconos_read_burst_l(done, o_osif, i_osif, local_ram_address, current_address, length_of_last_data_burst);
-- if done then
-- state <= STATE_GET_DATA_ACK;
-- end if;
--
--
-- when STATE_GET_DATA_ACK =>
-- --! wait for acknowledgement
-- receive_data_en <= '1';
-- state <= STATE_GET_DATA_ACK_2;
--
-- when STATE_GET_DATA_ACK_2 =>
-- --! wait for acknowledgement
-- if receive_data_ack = '1' then
-- receive_data_en <= '0';
-- state <= STATE_EXTRACT_OBSERVATION;
-- end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 7: WRITE OBSERVATION TO MAIN MEMORY
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WRITE_OBSERVATION =>
--! write observation (init)
number_of_bursts <= number_of_bursts_remember;
local_ram_address <= local_ram_start_address;
--write_histo_en <= '1';
state <= STATE_WRITE_OBSERVATION_2;
when STATE_WRITE_OBSERVATION_2 =>
--! write observation (check burst number)
if number_of_bursts > 0 then
-- more full bursts needed
state <= STATE_WRITE_OBSERVATION_3;
number_of_bursts <= number_of_bursts - 1;
elsif length_of_last_burst > 0 then
-- last burst needed (not full)
temp4 <= length_of_last_burst * 8;
state <= STATE_WRITE_OBSERVATION_4;
else
-- no last burst needed (which is not full)
state <= STATE_MORE_PARTICLES;
end if;
when STATE_WRITE_OBSERVATION_3 =>
--! write observation (write bursts)
reconos_write_burst(done, o_osif, i_osif, local_ram_address, observation_array_address);
if done then
observation_array_address <= observation_array_address + 128;
local_ram_address <= local_ram_address + 128;
state <= STATE_WRITE_OBSERVATION_2;
end if;
when STATE_WRITE_OBSERVATION_4 =>
--! write observation (write last burst)
reconos_write_burst_l(done, o_osif, i_osif, local_ram_address, observation_array_address, length_of_last_burst);
if done then
state <= STATE_MORE_PARTICLES;
observation_array_address <= observation_array_address + temp4;
local_ram_address <= local_ram_address + temp4;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 8: MORE PARTICLES?
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_MORE_PARTICLES =>
--! check if more particles need an observation
remaining_observations <= remaining_observations - 1;
state <= STATE_MORE_PARTICLES_2;
enable <= '0';
when STATE_MORE_PARTICLES_2 =>
--! check if more particles need an observation
if (remaining_observations > 0) then
state <= STATE_READ_NEXT_PARTICLE;
else
time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9: SEND MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
state <= STATE_SEND_MEASUREMENT_1;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9*: SEND MEASURMENT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
if (time_start < time_stop) then
time_measurement <= time_stop - time_start;
state <= STATE_SEND_MEASUREMENT_2;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_SEND_MEASUREMENT_2 =>
--! sends time measurement to message box
-- send message
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
if (done and success) then
state <= STATE_WAIT_FOR_MESSAGE;
end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
891ed8ee395af26406d3db0aa67f6eed
| 0.512342 | 4.22531 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/TESTBENCH_ac97_if.vhd
| 4 | 3,256 |
-------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_standalone.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:21 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_standalone is
end TESTBENCH_standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture behavioral of TESTBENCH_standalone is
component ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_Vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal bit_clk, sync, sdata_out, sdata_in : std_logic;
signal ac97_reset_n, fast_clk, reset : std_logic;
signal pcm_play_left, pcm_play_right : std_logic_vector(15 downto 0);
signal pcm_record_left, pcm_record_right : std_logic_vector(15 downto 0) := (others => '0');
begin -- behavioral
clk_PROCESS : process is
begin
fast_clk <= '0';
wait for 5 ns;
fast_clk <= '1';
wait for 5 ns;
end process;
reset_PROCESS : process is
begin
reset <= '1';
wait for 5 us;
reset <= '0';
wait;
end process;
uut : ac97_if
port map (
ClkIn => fast_clk,
Reset => reset,
PCM_Playback_Left => pcm_play_left,
PCM_Playback_Right => pcm_play_right,
PCM_Playback_Accept => open,
PCM_Record_Left => pcm_record_left,
PCM_Record_Right => pcm_record_right,
PCM_Record_Valid => open,
Debug => open,
AC97Reset_n => ac97_reset_n,
AC97Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
uut_1 : ac97_model
port map (
-- CODEC signals
AC97Reset_n => ac97_reset_n,
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
end behavioral;
|
gpl-3.0
|
79e60d940be6704268ef521cea5079e1
| 0.491093 | 3.712657 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/data/hw/pcores/hw_task_v1_01_b/hdl/vhdl/hw_task.vhd
| 1 | 3,170 |
------------
-- pcore top level wrapper
-- generated at 2008-02-18 16:25:27.273933 by 'mkhwtask.py hwt_data 1 ../src/hwt_data.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 13; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 11; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
-- time base
i_timeBase : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
);
end hw_task;
architecture structural of hw_task is
component burst_ram
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic
);
end component;
signal o_osif_flat_i : std_logic_vector(0 to 41);
signal i_osif_flat_i : std_logic_vector(0 to 44);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_data_i : entity hwt_data
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk,
i_timeBase => i_timeBase
);
burst_ram_i : burst_ram
port map (
addra => task2burst_Addr,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkb => clk,
dina => task2burst_Data,
dinb => i_burstData,
douta => burst2task_Data,
doutb => o_burstData,
wea => task2burst_WE,
web => i_burstWE
);
end structural;
|
gpl-3.0
|
880eaee69c23f3242bfa4d15000d5bc5
| 0.663091 | 2.802829 | false | false | false | false |
luebbers/reconos
|
support/pcores/message_manager_v1_00_a/hdl/vhdl/queue_tb.vhd
| 1 | 3,765 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:16:35 10/31/2006
-- Design Name: queue
-- Module Name: C:/queueProject/src/queue_tb.vhd
-- Project Name: myProj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: queue
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY queue_tb IS
END queue_tb;
ARCHITECTURE behavior OF queue_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT queue
generic(
ADDRESS_BITS : integer := 2;
DATA_BITS : integer := 32
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
add : IN std_logic;
remove : IN std_logic;
entryToAdd : IN std_logic_vector(0 to 31);
headValid : INOUT std_logic;
full : INOUT std_logic;
empty : INOUT std_logic;
head : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL add : std_logic := '0';
SIGNAL remove : std_logic := '0';
SIGNAL entryToAdd : std_logic_vector(0 to 31) := (others=>'0');
--BiDirs
SIGNAL headValid : std_logic;
SIGNAL full : std_logic;
SIGNAL empty : std_logic;
--Outputs
SIGNAL head : std_logic_vector(0 to 31);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: queue
GENERIC MAP(
ADDRESS_BITS => 2,
DATA_BITS => 32
)
PORT MAP(
clk => clk,
rst => rst,
add => add,
remove => remove,
entryToAdd => entryToAdd,
head => head,
headValid => headValid,
full => full,
empty => empty
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Place stimulus here
rst <= '1'; -- Reset the FIFO
wait for 20 ns;
rst <= '0';
wait for 20 ns;
entryToAdd <= x"1111_1111"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"2222_2222"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"3333_3333"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"4444_4444"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
entryToAdd <= x"5555_5555"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
clockProcess : PROCESS
BEGIN
clk <= '1'; -- clock cycle 10 ns
wait for 5 ns;
clk <= '0';
wait for 5 ns;
END PROCESS;
END;
|
gpl-3.0
|
222232cdcb09ccaf12e429875e307de2
| 0.586189 | 3.056006 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/PdmDes.vhd
| 1 | 6,470 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:24:36 04/02/2013
-- Design Name:
-- Module Name: PdmDes - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the deserializer of the microphone data. The module generates
-- the pdm_m_clk_o signal to the ADMP421 Microphone (M_CLK) and data is read on the positive
-- edge of this signal.
--
-- Then the module deserializes the signal on 16 bits when en_i = '1' (it means that recoding
-- is going on)
--
-- The module also generates the pdm_clk_rising_o signal, that is active when the positive edge of the
-- pdm_m_clk_o signal occures. This signal is used in the VGA controller, the MicDisplay component to
-- display audio data on the screen. The signal is two system clock period length, in order to make it
-- easier the synchronizing with the VGA clock domain (108MHz)
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity PdmDes is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_HZ : integer := 2000000
);
port(
clk_i : in std_logic;
en_i : in std_logic; -- Enable deserializing (during record)
done_o : out std_logic; -- Signaling that 16 bits are deserialized
data_o : out std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- output deserialized data
-- PDM
pdm_m_clk_o : out std_logic; -- Output M_CLK signal to the microphone
pdm_m_data_i : in std_logic; -- Input PDM data from the microphone
pdm_lrsel_o : out std_logic; -- Set to '0', therefore data is read on the positive edge
pdm_clk_rising_o : out std_logic -- Signaling the rising edge of M_CLK, used by the MicDisplay
-- component in the VGA controller
);
end PdmDes;
architecture Behavioral of PdmDes is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- Divider to create pdm_m_clk_0
signal cnt_clk : integer range 0 to 127 := 0;
-- Internal pdm_m_clk_o signal
signal clk_int : std_logic := '0';
-- Piped clk_int signal to create pdm_clk_rising
signal pdm_clk_rising : std_logic;
-- Shift register to deserialize incoming microphone data
signal pdm_tmp : std_logic_vector((C_NR_OF_BITS - 1) downto 0);
-- Count the number of bits
signal cnt_bits : integer range 0 to 31 := 0;
-- To create a pdm_clk_rising impulse of two clock period length
-- This signal will be registered in the MicDisplay module on the 108MHz pxlclk
signal pdm_clk_rising_reg : std_logic_vector (2 downto 0);
signal en_int : std_logic;
signal done_int : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- with L/R Sel tied to GND => output = DATA1 (rising edge)
pdm_lrsel_o <= '0';
-- Synchronize the enable input
SYNC: process(clk_i)
begin
if rising_edge(clk_i) then
en_int <= en_i;
end if;
end process SYNC;
------------------------------------------------------------------------
-- Deserializer
------------------------------------------------------------------------
-- Sample input serial data process
SHFT_IN: process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
pdm_tmp <= pdm_tmp(C_NR_OF_BITS-2 downto 0) & pdm_m_data_i;
end if;
end if;
end process SHFT_IN;
-- Count the number of sampled bits
CNT: process(clk_i) begin
if rising_edge(clk_i) then
if en_int = '0' then
cnt_bits <= 0;
else
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
cnt_bits <= 0;
else
cnt_bits <= cnt_bits + 1;
end if;
end if;
end if;
end if;
end process CNT;
-- Generate the done signal
process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = 0 then
if en_int = '1' then
done_int <= '1';
data_o <= pdm_tmp;
end if;
end if;
else
done_int <= '0';
end if;
end if;
end process;
done_o <= done_int;
-- Generate PDM Clock, that runs independent from the enable signal, therefore
-- the onboard microphone will always send data, that is displayed on the VGA screen
-- using the MicDisplay component
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if cnt_clk = (((C_SYS_CLK_FREQ_MHZ*1000000)/(C_PDM_FREQ_HZ*2))-1) then
cnt_clk <= 0;
clk_int <= not clk_int;
if clk_int = '0' then
pdm_clk_rising <= '1';
end if;
else
cnt_clk <= cnt_clk + 1;
pdm_clk_rising <= '0';
end if;
end if;
end process CLK_CNT;
pdm_m_clk_o <= clk_int;
-- Register pdm_clk_rising
-- to create a two clock period length impulse
RISING_IMP: process(clk_i)
begin
if rising_edge(clk_i) then
pdm_clk_rising_reg <= pdm_clk_rising_reg (1 downto 0) & pdm_clk_rising;
end if;
end process RISING_IMP;
-- Assign the output pdm_clk_rising impulse
ASSIGN_PDM_CLK_RISING_IMP: process(clk_i)
begin
if rising_edge(clk_i) then
pdm_clk_rising_o <= (pdm_clk_rising_reg(0) or pdm_clk_rising_reg(1)) and (not pdm_clk_rising_reg(2));
end if;
end process ASSIGN_PDM_CLK_RISING_IMP;
end Behavioral;
|
gpl-3.0
|
450aec3e73ffd8196e73ec34c8496345
| 0.517002 | 4.053885 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/synth/FrameBuffer.vhd
| 1 | 15,058 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY FrameBuffer IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FrameBuffer;
ARCHITECTURE FrameBuffer_arch OF FrameBuffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FrameBuffer_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FrameBuffer_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FrameBuffer_arch : ARCHITECTURE IS "FrameBuffer,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FrameBuffer_arch: ARCHITECTURE IS "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "FrameBuffer.mif",
C_INIT_FILE => "FrameBuffer.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 10240,
C_READ_DEPTH_A => 10240,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 10240,
C_READ_DEPTH_B => 10240,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.61856 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END FrameBuffer_arch;
|
mit
|
03e41a12fc6de0297a23c0868c1f6120
| 0.631956 | 3.061814 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_glitch_filt.vhd
| 1 | 4,193 |
--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana ([email protected])
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
-- Glitch filter consisting of a set of chained flip-flops followed by a
-- comparator. The comparator toggles to '1' when all FFs in the chain are
-- '1' and respectively to '0' when all the FFS in the chain are '0'.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana [email protected] File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity gc_glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input, synchronous to clk_i
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end entity gc_glitch_filt;
architecture behav of gc_glitch_filt is
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Glitch filtration logic
--============================================================================
glitch_filt(0) <= dat_i;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_len downto 1) <= (others => '0');
else
glitch_filt(g_len downto 1) <= glitch_filt(g_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
-- and set the data output based on the state of the glitch filter
p_output: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
dat_o <= '0';
elsif (unsigned(glitch_filt) = (glitch_filt'range => '1')) then
dat_o <= '1';
elsif (unsigned(glitch_filt) = (glitch_filt'range => '0')) then
dat_o <= '0';
end if;
end if;
end process p_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
|
lgpl-3.0
|
15f18a26896470bb7d1d56ea3afef2ed
| 0.460529 | 4.628035 | false | false | false | false |
luebbers/reconos
|
tests/simulation/plb/coop/test_coop.vhd
| 1 | 6,362 |
--!
--! \file test_coop.vhd
--!
--! Simulation testbench thread for cooperative multithreading
--!
--! \author Enno Luebbers <[email protected]>
--! \date 23.04.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 23.04.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_coop is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_coop;
architecture Behavioral of test_coop is
-- OS synchronization state machine states
type state_t is (STATE_CHECK,
STATE_YIELD,
STATE_POST_YIELD,
STATE_DELAY,
STATE_POST_DELAY,
STATE_LOCK,
STATE_POST_LOCK,
STATE_EXIT);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07");
constant decode : decode_t := (STATE_CHECK,
STATE_YIELD,
STATE_POST_YIELD,
STATE_DELAY,
STATE_POST_DELAY,
STATE_LOCK,
STATE_POST_LOCK,
STATE_EXIT);
-- resources used by thread
constant C_SEM_YIELD : std_logic_vector(0 to 31) := X"00000000";
constant C_SEM_DELAY : std_logic_vector(0 to 31) := X"00000001";
constant C_SEM_LOCK : std_logic_vector(0 to 31) := X"00000002";
constant C_MUTEX : std_logic_vector(0 to 31) := X"00000003";
constant C_DELAY : std_logic_vector(0 to 31) := X"0000007F"; -- delay for 128 ticks
signal state : state_t := STATE_CHECK;
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : state_t := STATE_CHECK;
variable resume_state_enc : reconos_state_enc_t := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_CHECK;
next_state := STATE_CHECK;
resume_state_enc := (others => '0');
done := false;
success := false;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
next_state := decode(to_integer(unsigned(resume_state_enc)));
else
next_state := STATE_YIELD;
end if;
end if;
-- test thread_yield()
when STATE_YIELD =>
-- on single-cycle calls, saved_state_enc must be set to the _next_ state
reconos_thread_yield(o_osif, i_osif, encode(STATE_POST_YIELD));
next_state := STATE_POST_YIELD;
when STATE_POST_YIELD =>
reconos_sem_post(o_osif, i_osif, C_SEM_YIELD);
next_state := STATE_DELAY;
-- test single-cycle blocking yielding call
when STATE_DELAY =>
reconos_thread_delay(o_osif, i_osif, C_DELAY); -- delay via OS
-- on single-cycle calls, saved_state_enc must be set to the _next_ state
reconos_flag_yield(o_osif, i_osif, encode(STATE_POST_DELAY));
next_state := STATE_POST_DELAY;
when STATE_POST_DELAY =>
reconos_sem_post(o_osif, i_osif, C_SEM_DELAY);
next_state := STATE_LOCK;
-- test multi-cycle blocking yielding call
when STATE_LOCK =>
reconos_mutex_lock(done, success, o_osif, i_osif, C_MUTEX);
-- on multi-cycle calls, saved_state_enc must be set to the _current_ state
reconos_flag_yield(o_osif, i_osif, encode(STATE_LOCK));
if done then
if success then
next_state := STATE_POST_LOCK;
else
next_state := STATE_EXIT;
end if;
end if;
when STATE_POST_LOCK =>
reconos_sem_post(o_osif, i_osif, C_SEM_LOCK);
next_state := STATE_EXIT;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
next_state := STATE_EXIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
2f84538b92ae65d7cb07340b333e3b8f
| 0.486954 | 4.10187 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/br986.vhd
| 2 | 845 |
-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity bug3 is
port (
clk1_i : in std_logic;
clk1_ib : in std_logic;
clk1_o : out std_logic
);
end bug3;
architecture bug3_syn of bug3 is
component IBUFDS generic (
DIFF_TERM : boolean := FALSE
); port(
O : out std_logic;
I : in std_logic;
IB : in std_logic
); end component;
begin
ibufds1 : ibufds
generic map (
DIFF_TERM => TRUE -- change to "1" and vhdlpp is happy
)
port map (
i => clk1_i,
ib => clk1_ib,
o => clk1_o
);
end bug3_syn;
entity ibufds is
generic (
DIFF_TERM : boolean := FALSE
);
port (
i : in std_logic;
ib : in std_logic;
o : out std_logic
);
end ibufds;
architecture ibufds_sim of ibufds is
begin
o <= i;
end ibufds_sim;
|
gpl-2.0
|
7d0ddd471eca61898d39aef382f9516f
| 0.611834 | 2.85473 | false | false | false | false |
bzero/freezing-spice
|
src/if.vhd
| 2 | 2,389 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.if_pkg.all;
entity instruction_fetch is
port (clk : in std_logic;
rst_n : in std_logic;
d : in if_in;
q : out if_out);
end entity instruction_fetch;
architecture Behavioral of instruction_fetch is
-------------------------------------------------
-- Types
-------------------------------------------------
type registers is record
pc : unsigned(word'range);
npc : unsigned(word'range);
end record registers;
-------------------------------------------------
-- Signals
-------------------------------------------------
signal r, rin : registers;
signal zero : std_logic := '1';
-------------------------------------------------
-- Constants
-------------------------------------------------
constant c_four : unsigned(2 downto 0) := to_unsigned(4, 3);
begin -- architecture Behavioral
-------------------------------------------------
-- assign outputs
-------------------------------------------------
q.fetch_addr <= std_logic_vector(rin.pc);
q.pc <= std_logic_vector(r.pc);
-------------------------------------------------
-- PC mux
-------------------------------------------------
pc_next_proc : process (d, r, zero) is
variable v : registers;
begin -- process pc_next_proc
-- defaults
v := r;
if (zero = '1') then
v.pc := (others => '0');
elsif (d.load_pc = '1') then
v.pc := unsigned(d.next_pc);
elsif (d.stall = '1') then
v.pc := r.pc;
else
v.pc := r.pc + c_four;
end if;
rin <= v;
end process pc_next_proc;
-------------------------------------------------
-- create the Program Counter register
-------------------------------------------------
pc_reg_proc : process (clk, rst_n) is
begin -- process pc_reg
if (rst_n = '0') then
r.pc <= (others => '0');
zero <= '1';
elsif (rising_edge(clk)) then
r <= rin;
zero <= '0';
end if;
end process pc_reg_proc;
end architecture Behavioral;
|
bsd-3-clause
|
bcae1d1f47d42cfa21b03cf447a5eabd
| 0.364169 | 4.740079 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/v_ram/v_ram_sim_netlist.vhdl
| 1 | 624,873 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Tue Mar 01 14:57:36 2016
-- Host : Dries007Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/v_ram/v_ram_sim_netlist.vhdl
-- Design : v_ram
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_mux__parameterized0\ is
port (
\^doutb\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
clkb : in STD_LOGIC;
DOUTB : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \v_ram_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \v_ram_blk_mem_gen_mux__parameterized0\ is
signal \doutb[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_7_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 4 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\doutb[0]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => DOUTB(0),
I1 => \doutb[0]_INST_0_i_1_n_0\,
O => \^doutb\(0),
S => sel_pipe_d1(4)
);
\doutb[0]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(2),
I1 => DOBDO(0),
I2 => sel_pipe_d1(3),
O => \doutb[0]_INST_0_i_1_n_0\
);
\doutb[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[10]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[10]_INST_0_i_2_n_0\,
I5 => \doutb[10]_INST_0_i_3_n_0\,
O => \^doutb\(10)
);
\doutb[10]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(7),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(7),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(7),
O => \doutb[10]_INST_0_i_1_n_0\
);
\doutb[10]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[10]_INST_0_i_4_n_0\,
I1 => \doutb[10]_INST_0_i_5_n_0\,
O => \doutb[10]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[10]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[10]_INST_0_i_6_n_0\,
I1 => \doutb[10]_INST_0_i_7_n_0\,
O => \doutb[10]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[10]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(7),
O => \doutb[10]_INST_0_i_4_n_0\
);
\doutb[10]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(7),
O => \doutb[10]_INST_0_i_5_n_0\
);
\doutb[10]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(7),
O => \doutb[10]_INST_0_i_6_n_0\
);
\doutb[10]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(7),
O => \doutb[10]_INST_0_i_7_n_0\
);
\doutb[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[11]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[11]_INST_0_i_2_n_0\,
I5 => \doutb[11]_INST_0_i_3_n_0\,
O => \^doutb\(11)
);
\doutb[11]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34\(0),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35\(0),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36\(0),
O => \doutb[11]_INST_0_i_1_n_0\
);
\doutb[11]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[11]_INST_0_i_4_n_0\,
I1 => \doutb[11]_INST_0_i_5_n_0\,
O => \doutb[11]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[11]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[11]_INST_0_i_6_n_0\,
I1 => \doutb[11]_INST_0_i_7_n_0\,
O => \doutb[11]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[11]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29\(0),
O => \doutb[11]_INST_0_i_4_n_0\
);
\doutb[11]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33\(0),
O => \doutb[11]_INST_0_i_5_n_0\
);
\doutb[11]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOPBDOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21\(0),
O => \doutb[11]_INST_0_i_6_n_0\
);
\doutb[11]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25\(0),
O => \doutb[11]_INST_0_i_7_n_0\
);
\doutb[1]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\(0),
I1 => \doutb[1]_INST_0_i_1_n_0\,
O => \^doutb\(1),
S => sel_pipe_d1(4)
);
\doutb[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0),
I2 => sel_pipe_d1(3),
O => \doutb[1]_INST_0_i_1_n_0\
);
\doutb[2]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\(0),
I1 => \doutb[2]_INST_0_i_1_n_0\,
O => \^doutb\(2),
S => sel_pipe_d1(4)
);
\doutb[2]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1),
I2 => sel_pipe_d1(3),
O => \doutb[2]_INST_0_i_1_n_0\
);
\doutb[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[3]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[3]_INST_0_i_2_n_0\,
I5 => \doutb[3]_INST_0_i_3_n_0\,
O => \^doutb\(3)
);
\doutb[3]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(0),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(0),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(0),
O => \doutb[3]_INST_0_i_1_n_0\
);
\doutb[3]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[3]_INST_0_i_4_n_0\,
I1 => \doutb[3]_INST_0_i_5_n_0\,
O => \doutb[3]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[3]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[3]_INST_0_i_6_n_0\,
I1 => \doutb[3]_INST_0_i_7_n_0\,
O => \doutb[3]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[3]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(0),
O => \doutb[3]_INST_0_i_4_n_0\
);
\doutb[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(0),
O => \doutb[3]_INST_0_i_5_n_0\
);
\doutb[3]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(0),
O => \doutb[3]_INST_0_i_6_n_0\
);
\doutb[3]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(0),
O => \doutb[3]_INST_0_i_7_n_0\
);
\doutb[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[4]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[4]_INST_0_i_2_n_0\,
I5 => \doutb[4]_INST_0_i_3_n_0\,
O => \^doutb\(4)
);
\doutb[4]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(1),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(1),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(1),
O => \doutb[4]_INST_0_i_1_n_0\
);
\doutb[4]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[4]_INST_0_i_4_n_0\,
I1 => \doutb[4]_INST_0_i_5_n_0\,
O => \doutb[4]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[4]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[4]_INST_0_i_6_n_0\,
I1 => \doutb[4]_INST_0_i_7_n_0\,
O => \doutb[4]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[4]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(1),
O => \doutb[4]_INST_0_i_4_n_0\
);
\doutb[4]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(1),
O => \doutb[4]_INST_0_i_5_n_0\
);
\doutb[4]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(1),
O => \doutb[4]_INST_0_i_6_n_0\
);
\doutb[4]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(1),
O => \doutb[4]_INST_0_i_7_n_0\
);
\doutb[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[5]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[5]_INST_0_i_2_n_0\,
I5 => \doutb[5]_INST_0_i_3_n_0\,
O => \^doutb\(5)
);
\doutb[5]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(2),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(2),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(2),
O => \doutb[5]_INST_0_i_1_n_0\
);
\doutb[5]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[5]_INST_0_i_4_n_0\,
I1 => \doutb[5]_INST_0_i_5_n_0\,
O => \doutb[5]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[5]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[5]_INST_0_i_6_n_0\,
I1 => \doutb[5]_INST_0_i_7_n_0\,
O => \doutb[5]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[5]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(2),
O => \doutb[5]_INST_0_i_4_n_0\
);
\doutb[5]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(2),
O => \doutb[5]_INST_0_i_5_n_0\
);
\doutb[5]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(2),
O => \doutb[5]_INST_0_i_6_n_0\
);
\doutb[5]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(2),
O => \doutb[5]_INST_0_i_7_n_0\
);
\doutb[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[6]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[6]_INST_0_i_2_n_0\,
I5 => \doutb[6]_INST_0_i_3_n_0\,
O => \^doutb\(6)
);
\doutb[6]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(3),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(3),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(3),
O => \doutb[6]_INST_0_i_1_n_0\
);
\doutb[6]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[6]_INST_0_i_4_n_0\,
I1 => \doutb[6]_INST_0_i_5_n_0\,
O => \doutb[6]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[6]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[6]_INST_0_i_6_n_0\,
I1 => \doutb[6]_INST_0_i_7_n_0\,
O => \doutb[6]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[6]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(3),
O => \doutb[6]_INST_0_i_4_n_0\
);
\doutb[6]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(3),
O => \doutb[6]_INST_0_i_5_n_0\
);
\doutb[6]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3),
O => \doutb[6]_INST_0_i_6_n_0\
);
\doutb[6]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(3),
O => \doutb[6]_INST_0_i_7_n_0\
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[7]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[7]_INST_0_i_2_n_0\,
I5 => \doutb[7]_INST_0_i_3_n_0\,
O => \^doutb\(7)
);
\doutb[7]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(4),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(4),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(4),
O => \doutb[7]_INST_0_i_1_n_0\
);
\doutb[7]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[7]_INST_0_i_4_n_0\,
I1 => \doutb[7]_INST_0_i_5_n_0\,
O => \doutb[7]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[7]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[7]_INST_0_i_6_n_0\,
I1 => \doutb[7]_INST_0_i_7_n_0\,
O => \doutb[7]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[7]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(4),
O => \doutb[7]_INST_0_i_4_n_0\
);
\doutb[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(4),
O => \doutb[7]_INST_0_i_5_n_0\
);
\doutb[7]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(4),
O => \doutb[7]_INST_0_i_6_n_0\
);
\doutb[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(4),
O => \doutb[7]_INST_0_i_7_n_0\
);
\doutb[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[8]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[8]_INST_0_i_2_n_0\,
I5 => \doutb[8]_INST_0_i_3_n_0\,
O => \^doutb\(8)
);
\doutb[8]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(5),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(5),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(5),
O => \doutb[8]_INST_0_i_1_n_0\
);
\doutb[8]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[8]_INST_0_i_4_n_0\,
I1 => \doutb[8]_INST_0_i_5_n_0\,
O => \doutb[8]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[8]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[8]_INST_0_i_6_n_0\,
I1 => \doutb[8]_INST_0_i_7_n_0\,
O => \doutb[8]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[8]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(5),
O => \doutb[8]_INST_0_i_4_n_0\
);
\doutb[8]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(5),
O => \doutb[8]_INST_0_i_5_n_0\
);
\doutb[8]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(5),
O => \doutb[8]_INST_0_i_6_n_0\
);
\doutb[8]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(5),
O => \doutb[8]_INST_0_i_7_n_0\
);
\doutb[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[9]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[9]_INST_0_i_2_n_0\,
I5 => \doutb[9]_INST_0_i_3_n_0\,
O => \^doutb\(9)
);
\doutb[9]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(6),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(6),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(6),
O => \doutb[9]_INST_0_i_1_n_0\
);
\doutb[9]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[9]_INST_0_i_4_n_0\,
I1 => \doutb[9]_INST_0_i_5_n_0\,
O => \doutb[9]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[9]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[9]_INST_0_i_6_n_0\,
I1 => \doutb[9]_INST_0_i_7_n_0\,
O => \doutb[9]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[9]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(6),
O => \doutb[9]_INST_0_i_4_n_0\
);
\doutb[9]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(6),
O => \doutb[9]_INST_0_i_5_n_0\
);
\doutb[9]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(6),
O => \doutb[9]_INST_0_i_6_n_0\
);
\doutb[9]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(6),
O => \doutb[9]_INST_0_i_7_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(3),
Q => sel_pipe_d1(3),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(4),
Q => sel_pipe_d1(4),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(2),
Q => sel_pipe(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(3),
Q => sel_pipe(3),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(4),
Q => sel_pipe(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_prim_wrapper_init is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end v_ram_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of v_ram_blk_mem_gen_prim_wrapper_init is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "INDEPENDENT";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ram_ena : in STD_LOGIC;
ram_enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => addrb(13 downto 0),
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => DOBDO(0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_ena,
ENBWREN => ram_enb,
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"11",
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
ENA : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \^ena\ : STD_LOGIC;
signal \^enb\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "INDEPENDENT";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
ENA <= \^ena\;
ENB <= \^enb\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => addra(16),
I1 => wea(0),
O => \^ena\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => addrb(16),
O => \^enb\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal ena_array : STD_LOGIC_VECTOR ( 6 to 6 );
signal enb_array : STD_LOGIC_VECTOR ( 6 to 6 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(6),
ENBWREN => enb_array(6),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(14),
I1 => wea(0),
I2 => addra(15),
I3 => addra(12),
I4 => addra(16),
I5 => addra(13),
O => ena_array(6)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(14),
O => enb_array(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal ena_array : STD_LOGIC_VECTOR ( 7 to 7 );
signal enb_array : STD_LOGIC_VECTOR ( 7 to 7 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(7),
ENBWREN => enb_array(7),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => addra(16),
I3 => addra(15),
I4 => wea(0),
I5 => addra(14),
O => ena_array(7)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(14),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\ is
signal ena_array : STD_LOGIC_VECTOR ( 8 to 8 );
signal enb_array : STD_LOGIC_VECTOR ( 8 to 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(8),
ENBWREN => enb_array(8),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => addra(15),
I1 => wea(0),
I2 => addra(12),
I3 => addra(13),
I4 => addra(16),
I5 => addra(14),
O => ena_array(8)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(16),
I1 => addrb(14),
I2 => addrb(15),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\ is
signal ena_array : STD_LOGIC_VECTOR ( 9 to 9 );
signal enb_array : STD_LOGIC_VECTOR ( 9 to 9 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(9),
ENBWREN => enb_array(9),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
I4 => addra(16),
I5 => addra(15),
O => ena_array(9)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(16),
I1 => addrb(14),
I2 => addrb(13),
I3 => addrb(12),
I4 => addrb(15),
O => enb_array(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\ is
signal ena_array : STD_LOGIC_VECTOR ( 10 to 10 );
signal enb_array : STD_LOGIC_VECTOR ( 10 to 10 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(10),
ENBWREN => enb_array(10),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(15),
I1 => wea(0),
I2 => addra(12),
I3 => addra(14),
I4 => addra(16),
I5 => addra(13),
O => ena_array(10)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(16),
I1 => addrb(14),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(15),
O => enb_array(10)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\ is
signal ena_array : STD_LOGIC_VECTOR ( 11 to 11 );
signal enb_array : STD_LOGIC_VECTOR ( 11 to 11 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(11),
ENBWREN => enb_array(11),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => addra(16),
I3 => addra(14),
I4 => wea(0),
I5 => addra(15),
O => ena_array(11)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__10\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addrb(16),
I1 => addrb(14),
I2 => addrb(15),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(11)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\ is
signal ena_array : STD_LOGIC_VECTOR ( 12 to 12 );
signal enb_array : STD_LOGIC_VECTOR ( 12 to 12 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(12),
ENBWREN => enb_array(12),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(15),
I1 => wea(0),
I2 => addra(12),
I3 => addra(13),
I4 => addra(16),
I5 => addra(14),
O => ena_array(12)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__11\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(16),
I1 => addrb(13),
I2 => addrb(12),
I3 => addrb(14),
I4 => addrb(15),
O => enb_array(12)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\ is
signal ena_array : STD_LOGIC_VECTOR ( 13 to 13 );
signal enb_array : STD_LOGIC_VECTOR ( 13 to 13 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(13),
ENBWREN => enb_array(13),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__12\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => addra(12),
I1 => addra(15),
I2 => addra(16),
I3 => addra(13),
I4 => wea(0),
I5 => addra(14),
O => ena_array(13)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__12\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addrb(16),
I1 => addrb(13),
I2 => addrb(15),
I3 => addrb(12),
I4 => addrb(14),
O => enb_array(13)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\ is
signal ena_array : STD_LOGIC_VECTOR ( 14 to 14 );
signal enb_array : STD_LOGIC_VECTOR ( 14 to 14 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(14),
ENBWREN => enb_array(14),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => addra(15),
I1 => addra(13),
I2 => addra(16),
I3 => addra(12),
I4 => wea(0),
I5 => addra(14),
O => ena_array(14)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__13\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addrb(16),
I1 => addrb(12),
I2 => addrb(15),
I3 => addrb(13),
I4 => addrb(14),
O => enb_array(14)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\ is
signal ena_array : STD_LOGIC_VECTOR ( 15 to 15 );
signal enb_array : STD_LOGIC_VECTOR ( 15 to 15 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(15),
ENBWREN => enb_array(15),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => wea(0),
I1 => addra(12),
I2 => addra(16),
I3 => addra(13),
I4 => addra(15),
I5 => addra(14),
O => ena_array(15)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__14\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => addrb(16),
I1 => addrb(15),
I2 => addrb(14),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(15)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\doutb[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_ena : out STD_LOGIC;
ram_enb : out STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \^ram_ena\ : STD_LOGIC;
signal \^ram_enb\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
ram_ena <= \^ram_ena\;
ram_enb <= \^ram_enb\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => wea(0),
I1 => addra(16),
I2 => addra(15),
I3 => addra(14),
O => \^ram_ena\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => addrb(15),
I1 => addrb(14),
I2 => addrb(16),
O => \^ram_enb\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \doutb[2]\(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ram_ena\,
ENBWREN => \^ram_enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\ is
signal ena_array : STD_LOGIC_VECTOR ( 16 to 16 );
signal enb_array : STD_LOGIC_VECTOR ( 16 to 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(16),
ENBWREN => enb_array(16),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__15\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => wea(0),
I1 => addra(16),
I2 => addra(15),
I3 => addra(12),
I4 => addra(13),
I5 => addra(14),
O => ena_array(16)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__15\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(15),
I1 => addrb(14),
I2 => addrb(16),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(16)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\ is
signal ena_array : STD_LOGIC_VECTOR ( 17 to 17 );
signal enb_array : STD_LOGIC_VECTOR ( 17 to 17 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(17),
ENBWREN => enb_array(17),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(12),
I1 => addra(16),
I2 => addra(15),
I3 => addra(13),
I4 => addra(14),
I5 => wea(0),
O => ena_array(17)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__16\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(14),
I2 => addrb(13),
I3 => addrb(12),
I4 => addrb(16),
O => enb_array(17)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\ is
signal ena_array : STD_LOGIC_VECTOR ( 18 to 18 );
signal enb_array : STD_LOGIC_VECTOR ( 18 to 18 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(18),
ENBWREN => enb_array(18),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => wea(0),
I1 => addra(16),
I2 => addra(15),
I3 => addra(12),
I4 => addra(14),
I5 => addra(13),
O => ena_array(18)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__17\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(14),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(16),
O => enb_array(18)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "INDEPENDENT";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal enb_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => wea(0),
I1 => addra(16),
I2 => addra(13),
I3 => addra(12),
I4 => addra(15),
I5 => addra(14),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(14),
O => enb_array(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal ena_array : STD_LOGIC_VECTOR ( 1 to 1 );
signal enb_array : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(1),
ENBWREN => enb_array(1),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(15),
I3 => addra(13),
I4 => addra(16),
I5 => addra(14),
O => ena_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(14),
O => enb_array(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal ena_array : STD_LOGIC_VECTOR ( 2 to 2 );
signal enb_array : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(2),
ENBWREN => enb_array(2),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => addra(13),
I1 => wea(0),
I2 => addra(15),
I3 => addra(12),
I4 => addra(16),
I5 => addra(14),
O => ena_array(2)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(13),
I3 => addrb(12),
I4 => addrb(14),
O => enb_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal ena_array : STD_LOGIC_VECTOR ( 3 to 3 );
signal enb_array : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => DOPBDOP(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(3),
ENBWREN => enb_array(3),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(15),
I3 => addra(14),
I4 => addra(16),
I5 => addra(13),
O => ena_array(3)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(14),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal ena_array : STD_LOGIC_VECTOR ( 4 to 4 );
signal enb_array : STD_LOGIC_VECTOR ( 4 to 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(4),
ENBWREN => enb_array(4),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => addra(14),
I1 => wea(0),
I2 => addra(15),
I3 => addra(13),
I4 => addra(16),
I5 => addra(12),
O => ena_array(4)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(14),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal ena_array : STD_LOGIC_VECTOR ( 5 to 5 );
signal enb_array : STD_LOGIC_VECTOR ( 5 to 5 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(5),
ENBWREN => enb_array(5),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(15),
I3 => addra(13),
I4 => addra(16),
I5 => addra(14),
O => ena_array(5)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(13),
I3 => addrb(12),
I4 => addrb(14),
O => enb_array(5)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_prim_width is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end v_ram_blk_mem_gen_prim_width;
architecture STRUCTURE of v_ram_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.v_ram_blk_mem_gen_prim_wrapper_init
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized0\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ram_ena : in STD_LOGIC;
ram_enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
DOBDO(0) => DOBDO(0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
ram_ena => ram_ena,
ram_enb => ram_enb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized1\ is
port (
ENA : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized10\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized11\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized12\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized13\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized14\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized15\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized15\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized16\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized17\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized18\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized19\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized2\ is
port (
\doutb[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_ena : out STD_LOGIC;
ram_enb : out STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
\doutb[2]\(1 downto 0) => \doutb[2]\(1 downto 0),
ram_ena => ram_ena,
ram_enb => ram_enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized20\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized21\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized21\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized22\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized22\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized22\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized22\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized3\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized4\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized5\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized6\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized7\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
DOPBDOP(0) => DOPBDOP(0),
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized8\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized9\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end v_ram_blk_mem_gen_generic_cstr;
architecture STRUCTURE of v_ram_blk_mem_gen_generic_cstr is
signal ram_doutb : STD_LOGIC;
signal ram_ena : STD_LOGIC;
signal ram_enb : STD_LOGIC;
signal \ramloop[10].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_8\ : STD_LOGIC;
begin
\has_mux_b.B\: entity work.\v_ram_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\(0) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\(0) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0) => \ramloop[3].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[8].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[8].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[8].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[8].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[8].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[8].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[8].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[8].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[7].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[7].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[7].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[7].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[7].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[7].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[7].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(7) => \ramloop[14].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(6) => \ramloop[14].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(5) => \ramloop[14].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(4) => \ramloop[14].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(3) => \ramloop[14].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(2) => \ramloop[14].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(1) => \ramloop[14].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(0) => \ramloop[14].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(7) => \ramloop[13].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(6) => \ramloop[13].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(5) => \ramloop[13].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(4) => \ramloop[13].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(3) => \ramloop[13].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(2) => \ramloop[13].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(1) => \ramloop[13].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(0) => \ramloop[13].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(7) => \ramloop[20].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(6) => \ramloop[20].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(5) => \ramloop[20].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(4) => \ramloop[20].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(3) => \ramloop[20].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(2) => \ramloop[20].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(1) => \ramloop[20].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(0) => \ramloop[20].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(7) => \ramloop[19].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(6) => \ramloop[19].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(5) => \ramloop[19].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(4) => \ramloop[19].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(3) => \ramloop[19].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(2) => \ramloop[19].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(1) => \ramloop[19].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(0) => \ramloop[19].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(7) => \ramloop[18].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(6) => \ramloop[18].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(5) => \ramloop[18].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(4) => \ramloop[18].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(3) => \ramloop[18].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(2) => \ramloop[18].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(1) => \ramloop[18].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(0) => \ramloop[18].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(7) => \ramloop[17].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(6) => \ramloop[17].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(5) => \ramloop[17].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(4) => \ramloop[17].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(3) => \ramloop[17].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(2) => \ramloop[17].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(1) => \ramloop[17].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(0) => \ramloop[17].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(7) => \ramloop[23].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(6) => \ramloop[23].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(5) => \ramloop[23].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(4) => \ramloop[23].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(3) => \ramloop[23].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(2) => \ramloop[23].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(1) => \ramloop[23].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(0) => \ramloop[23].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(7) => \ramloop[22].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(6) => \ramloop[22].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(5) => \ramloop[22].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(4) => \ramloop[22].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(3) => \ramloop[22].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(2) => \ramloop[22].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(1) => \ramloop[22].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(0) => \ramloop[22].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(7) => \ramloop[21].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(6) => \ramloop[21].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(5) => \ramloop[21].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(4) => \ramloop[21].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(3) => \ramloop[21].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(2) => \ramloop[21].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(1) => \ramloop[21].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(0) => \ramloop[21].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19\(0) => \ramloop[7].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20\(0) => \ramloop[6].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21\(0) => \ramloop[5].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22\(0) => \ramloop[12].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23\(0) => \ramloop[11].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24\(0) => \ramloop[10].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25\(0) => \ramloop[9].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26\(0) => \ramloop[16].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27\(0) => \ramloop[15].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28\(0) => \ramloop[14].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29\(0) => \ramloop[13].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30\(0) => \ramloop[20].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31\(0) => \ramloop[19].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32\(0) => \ramloop[18].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33\(0) => \ramloop[17].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34\(0) => \ramloop[23].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35\(0) => \ramloop[22].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36\(0) => \ramloop[21].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(7) => \ramloop[12].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(6) => \ramloop[12].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(5) => \ramloop[12].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(4) => \ramloop[12].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3) => \ramloop[12].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(2) => \ramloop[12].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(1) => \ramloop[12].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[12].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(7) => \ramloop[11].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(6) => \ramloop[11].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(5) => \ramloop[11].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(4) => \ramloop[11].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3) => \ramloop[11].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(2) => \ramloop[11].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(1) => \ramloop[11].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(0) => \ramloop[11].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(7) => \ramloop[10].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(6) => \ramloop[10].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(5) => \ramloop[10].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(4) => \ramloop[10].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(3) => \ramloop[10].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(2) => \ramloop[10].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(1) => \ramloop[10].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(0) => \ramloop[10].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(7) => \ramloop[9].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(6) => \ramloop[9].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(5) => \ramloop[9].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(4) => \ramloop[9].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(3) => \ramloop[9].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(2) => \ramloop[9].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(1) => \ramloop[9].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(0) => \ramloop[9].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(7) => \ramloop[16].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(6) => \ramloop[16].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(5) => \ramloop[16].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(4) => \ramloop[16].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(3) => \ramloop[16].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(2) => \ramloop[16].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(1) => \ramloop[16].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(0) => \ramloop[16].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(7) => \ramloop[15].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(6) => \ramloop[15].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(5) => \ramloop[15].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(4) => \ramloop[15].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(3) => \ramloop[15].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(2) => \ramloop[15].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(1) => \ramloop[15].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(0) => \ramloop[15].ram.r_n_7\,
DOBDO(0) => \ramloop[1].ram.r_n_0\,
DOPBDOP(0) => \ramloop[8].ram.r_n_8\,
DOUTB(0) => ram_doutb,
addrb(4 downto 0) => addrb(16 downto 12),
clkb => clkb,
\^doutb\(11 downto 0) => doutb(11 downto 0)
);
\ramloop[0].ram.r\: entity work.v_ram_blk_mem_gen_prim_width
port map (
DOUTB(0) => ram_doutb,
ENA => \ramloop[2].ram.r_n_0\,
ENB => \ramloop[2].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
\ramloop[10].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized9\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[10].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[10].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[10].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[10].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[10].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[10].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[10].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[10].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[10].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[11].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized10\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[11].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[11].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[11].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[11].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[11].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[11].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[11].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[11].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[11].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[12].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized11\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[12].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[12].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[12].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[12].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[12].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[12].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[12].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[12].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[12].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[13].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized12\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[13].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[13].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[13].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[13].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[13].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[13].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[13].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[13].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[13].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[14].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized13\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[14].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[14].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[14].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[14].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[14].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[14].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[14].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[14].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[14].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[15].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized14\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[15].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[15].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[15].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[15].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[15].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[15].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[15].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[15].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[15].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[16].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized15\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[16].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[16].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[16].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[16].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[16].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[16].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[16].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[16].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[16].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[17].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized16\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[17].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[17].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[17].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[17].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[17].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[17].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[17].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[17].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[17].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[18].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized17\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[18].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[18].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[18].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[18].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[18].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[18].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[18].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[18].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[18].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[19].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized18\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[19].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[19].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[19].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[19].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[19].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[19].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[19].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[19].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[19].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized0\
port map (
DOBDO(0) => \ramloop[1].ram.r_n_0\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
ram_ena => ram_ena,
ram_enb => ram_enb
);
\ramloop[20].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized19\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[20].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[20].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[20].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[20].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[20].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[20].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[20].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[20].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[20].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[21].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized20\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[21].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[21].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[21].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[21].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[21].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[21].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[21].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[21].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[21].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[22].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized21\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[22].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[22].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[22].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[22].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[22].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[22].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[22].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[22].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[22].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[23].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized22\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[23].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[23].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[23].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[23].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[23].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[23].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[23].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[23].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[23].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized1\
port map (
DOUTB(0) => \ramloop[2].ram.r_n_2\,
ENA => \ramloop[2].ram.r_n_0\,
ENB => \ramloop[2].ram.r_n_1\,
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(1),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized2\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(2 downto 1),
\doutb[2]\(1) => \ramloop[3].ram.r_n_0\,
\doutb[2]\(0) => \ramloop[3].ram.r_n_1\,
ram_ena => ram_ena,
ram_enb => ram_enb,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized3\
port map (
DOUTB(0) => \ramloop[4].ram.r_n_0\,
ENA => \ramloop[2].ram.r_n_0\,
ENB => \ramloop[2].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(2)
);
\ramloop[5].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized4\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[5].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[5].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[5].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[5].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[5].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[5].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[5].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[5].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[5].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized5\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[6].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[6].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[6].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[6].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[6].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[6].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[6].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[6].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[6].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized6\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[7].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[7].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[7].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[7].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[7].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[7].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[7].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[7].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[7].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[8].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized7\
port map (
DOPBDOP(0) => \ramloop[8].ram.r_n_8\,
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[8].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[8].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[8].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[8].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[8].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[8].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[8].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[8].ram.r_n_7\,
wea(0) => wea(0)
);
\ramloop[9].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized8\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[9].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[9].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[9].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[9].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[9].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[9].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[9].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[9].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[9].ram.r_n_8\,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_top : entity is "blk_mem_gen_top";
end v_ram_blk_mem_gen_top;
architecture STRUCTURE of v_ram_blk_mem_gen_top is
begin
\valid.cstr\: entity work.v_ram_blk_mem_gen_generic_cstr
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(11 downto 0) => dina(11 downto 0),
doutb(11 downto 0) => doutb(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_v8_3_1_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end v_ram_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of v_ram_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.v_ram_blk_mem_gen_top
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(11 downto 0) => dina(11 downto 0),
doutb(11 downto 0) => doutb(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 16 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 17;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 17;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of v_ram_blk_mem_gen_v8_3_1 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of v_ram_blk_mem_gen_v8_3_1 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of v_ram_blk_mem_gen_v8_3_1 : entity is "26";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of v_ram_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of v_ram_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of v_ram_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of v_ram_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 16.2184 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of v_ram_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of v_ram_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of v_ram_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of v_ram_blk_mem_gen_v8_3_1 : entity is "v_ram.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of v_ram_blk_mem_gen_v8_3_1 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of v_ram_blk_mem_gen_v8_3_1 : entity is 76800;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of v_ram_blk_mem_gen_v8_3_1 : entity is 76800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of v_ram_blk_mem_gen_v8_3_1 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of v_ram_blk_mem_gen_v8_3_1 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of v_ram_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of v_ram_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of v_ram_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of v_ram_blk_mem_gen_v8_3_1 : entity is 76800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of v_ram_blk_mem_gen_v8_3_1 : entity is 76800;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of v_ram_blk_mem_gen_v8_3_1 : entity is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of v_ram_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of v_ram_blk_mem_gen_v8_3_1 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of v_ram_blk_mem_gen_v8_3_1 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of v_ram_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of v_ram_blk_mem_gen_v8_3_1 : entity is "yes";
end v_ram_blk_mem_gen_v8_3_1;
architecture STRUCTURE of v_ram_blk_mem_gen_v8_3_1 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.v_ram_blk_mem_gen_v8_3_1_synth
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(11 downto 0) => dina(11 downto 0),
doutb(11 downto 0) => doutb(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of v_ram : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of v_ram : entity is "v_ram,blk_mem_gen_v8_3_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of v_ram : entity is "v_ram,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=v_ram.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=76800,C_READ_DEPTH_A=76800,C_ADDRA_WIDTH=17,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=76800,C_READ_DEPTH_B=76800,C_ADDRB_WIDTH=17,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=26,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.2184 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of v_ram : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of v_ram : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end v_ram;
architecture STRUCTURE of v_ram is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 17;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 17;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "26";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 16.2184 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "v_ram.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 76800;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 76800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 76800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 76800;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.v_ram_blk_mem_gen_v8_3_1
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => NLW_U0_douta_UNCONNECTED(11 downto 0),
doutb(11 downto 0) => doutb(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(16 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(16 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(16 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(16 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
mit
|
43286ead10b75ab13115ce963f14b13d
| 0.729718 | 4.505765 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/xwb_dpram.vhd
| 1 | 7,138 |
-------------------------------------------------------------------------------
-- Title : Dual-port RAM for WR core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_dpram.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma, CERN
-- Created : 2011-02-15
-- Last update: 2013-09-11
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Description:
--
-- Dual port RAM with wishbone interface
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-15 1.0 greg.d Created
-- 2011-06-09 1.01 twlostow Removed unnecessary generics
-- 2011-21-09 1.02 twlostow Struct-ized version
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
entity xwb_dpram is
generic(
g_size : natural := 16384;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave2_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity;
g_slave2_granularity : t_wishbone_address_granularity
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out
);
end xwb_dpram;
architecture struct of xwb_dpram is
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
signal s_wea : std_logic;
signal s_web : std_logic;
signal s_bwea : std_logic_vector(3 downto 0);
signal s_bweb : std_logic_vector(3 downto 0);
signal slave1_in : t_wishbone_slave_in;
signal slave1_out : t_wishbone_slave_out;
signal slave2_in : t_wishbone_slave_in;
signal slave2_out : t_wishbone_slave_out;
begin
U_Adapter1 : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => g_slave1_interface_mode,
g_master_granularity => WORD,
g_slave_use_struct => true,
g_slave_mode => g_slave1_interface_mode,
g_slave_granularity => g_slave1_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => slave1_i,
slave_o => slave1_o,
master_i => slave1_out,
master_o => slave1_in);
U_Adapter2 : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => g_slave2_interface_mode,
g_master_granularity => WORD,
g_slave_use_struct => true,
g_slave_mode => g_slave2_interface_mode,
g_slave_granularity => g_slave2_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => slave2_i,
slave_o => slave2_o,
master_i => slave2_out,
master_o => slave2_in);
GEN_INITF: if g_init_file /= "" and g_init_file /= "none" generate
-- Unfortunately stupid ISE has problem with understanding bytesel
-- description in generic_dpram so it instantiates this using numerous LUTs
-- for connecting BRAMs and supporting bytesel. When initialization with
-- file is not needed it's better to use GEN_NO_INITF.
U_DPRAM : generic_dpram
generic map(
-- standard parameters
g_data_width => 32,
g_size => g_size,
g_with_byte_enable => true,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_init_file,
g_dual_clock => false
)
port map(
rst_n_i => rst_n_i,
-- Port A
clka_i => clk_sys_i,
bwea_i => s_bwea,
wea_i => s_wea,
aa_i => slave1_in.adr(f_log2_size(g_size)-1 downto 0),
da_i => slave1_in.dat,
qa_o => slave1_out.dat,
-- Port B
clkb_i => clk_sys_i,
bweb_i => s_bweb,
web_i => s_web,
ab_i => slave2_in.adr(f_log2_size(g_size)-1 downto 0),
db_i => slave2_in.dat,
qb_o => slave2_out.dat
);
end generate;
GEN_NO_INITF: if g_init_file = "" or g_init_file = "none" generate
-- This trick splits ram into four 8-bit blocks of RAM. Now the problem ISE
-- has with understanding correctly bytesel is bypassed and the
-- implementation takes almost none LUTs, just BRAMs.
GEN_BYTESEL: for i in 0 to 3 generate
U_DPRAM: generic_dpram
generic map(
g_data_width => 8,
g_size => g_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => "",
g_dual_clock => false)
port map(
rst_n_i => rst_n_i,
-- Port A
clka_i => clk_sys_i,
wea_i => s_bwea(i),
aa_i => slave1_in.adr(f_log2_size(g_size)-1 downto 0),
da_i => slave1_in.dat((i+1)*8-1 downto i*8),
qa_o => slave1_out.dat((i+1)*8-1 downto i*8),
-- Port B
clkb_i => clk_sys_i,
web_i => s_bweb(i),
ab_i => slave2_in.adr(f_log2_size(g_size)-1 downto 0),
db_i => slave2_in.dat((i+1)*8-1 downto i*8),
qb_o => slave2_out.dat((i+1)*8-1 downto i*8)
);
end generate;
end generate;
-- I know this looks weird, but otherwise ISE generates distributed RAM instead of block
-- RAM
s_bwea <= slave1_in.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8);
s_bweb <= slave2_in.sel when s_web = '1' else f_zeros(c_wishbone_data_width/8);
s_wea <= slave1_in.we and slave1_in.stb and slave1_in.cyc;
s_web <= slave2_in.we and slave2_in.stb and slave2_in.cyc;
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(rst_n_i = '0') then
slave1_out.ack <= '0';
slave2_out.ack <= '0';
else
if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
slave1_out.ack <= '0';
else
slave1_out.ack <= slave1_in.cyc and slave1_in.stb;
end if;
if(slave2_out.ack = '1' and g_slave2_interface_mode = CLASSIC) then
slave2_out.ack <= '0';
else
slave2_out.ack <= slave2_in.cyc and slave2_in.stb;
end if;
end if;
end if;
end process;
slave1_out.stall <= '0';
slave2_out.stall <= '0';
slave1_out.err <= '0';
slave2_out.err <= '0';
slave1_out.rty <= '0';
slave2_out.rty <= '0';
end struct;
|
lgpl-3.0
|
18785db522a2bef6faf85449db30c03d
| 0.523256 | 3.296998 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.ip_user_files/ipstatic/axi_uartlite_v2_0_10/hdl/src/vhdl/axi_uartlite.vhd
| 1 | 17,037 |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_uartlite.vhd
-- Version: v1.02.a
-- Description: AXI UART Lite Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_lite_ipif_v3_0_3;
-- SLV64_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0_3.ipif_pkg.SLV64_ARRAY_TYPE;
-- INTEGER_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
-- calc_num_ce comoponent refered from ipif_pkg
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0_3.axi_lite_ipif;
library axi_uartlite_v2_0_10;
-- uartlite_core refered from axi_uartlite_v2_0_10
use axi_uartlite_v2_0_10.uartlite_core;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- AXI generics
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-- UART Lite generics
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
--System signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- Interrupt -- UART Interrupt
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
--UARTLite Interface Signals
-- rx -- Receive Data
-- tx -- Transmit Data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity axi_uartlite is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ : integer := 100_000_000;
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 4;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- UARTLite Parameters
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
interrupt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector
(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(31 downto 0);
s_axi_wstrb : in std_logic_vector
(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- UARTLite Interface Signals
rx : in std_logic;
tx : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
-------------------------------------------------------------------------------
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
end entity axi_uartlite;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of axi_uartlite is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0)
:= X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- UARTLite registers Base Address
ZEROES & X"00000000",
ZEROES & (X"00000000" or X"0000000F")
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 4
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"0000000F";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0)
:= (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector
(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal bus2ip_cs : std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
begin -- architecture IMP
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
bus2ip_reset <= not bus2ip_resetn;
--------------------------------------------------------------------------
-- ip2bus_data assignment - as core is using maximum upto 8 bits
--------------------------------------------------------------------------
ip2bus_data((C_S_AXI_DATA_WIDTH-1) downto 8) <= (others => '0');
--------------------------------------------------------------------------
-- Instansiating the UART core
--------------------------------------------------------------------------
UARTLITE_CORE_I : entity axi_uartlite_v2_0_10.uartlite_core
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_BAUDRATE => C_BAUDRATE,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => bus2ip_clk,
Reset => bus2ip_reset,
bus2ip_data => bus2ip_data(7 downto 0),
bus2ip_rdce => bus2ip_rdce(3 downto 0),
bus2ip_wrce => bus2ip_wrce(3 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
SIn_DBus => ip2bus_data(7 downto 0),
RX => rx,
TX => tx,
Interrupt => Interrupt
);
--------------------------------------------------------------------------
-- Instantiate AXI lite IPIF
--------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_3.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end architecture RTL;
|
mit
|
1e0144ba8c7b3fe55a91a9a401534df4
| 0.419381 | 4.5432 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/client/fifo/eth_fifo_8.vhd
| 1 | 9,735 |
-------------------------------------------------------------------------------
-- Title : 10/100/1G Ethernet FIFO for 8-bit Client Interface
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : eth_fifo_8.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------
-- Description: This is the top-level wrapper for the 10/100/1G Ethernet
-- FIFO. The top level wrapper consists of individual FIFOs
-- on the transmitter path and on the receiver path.
--
-- Each path consists of an 8-bit LocalLink-to-8-bit
-- client-interface FIFO.
--------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity eth_fifo_8 is
generic (
FULL_DUPLEX_ONLY : boolean := false); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
-- Transmit FIFO MAC TX Interface
tx_clk : in std_logic; -- MAC transmit clock
tx_reset : in std_logic; -- Synchronous reset (tx_clk)
tx_enable : in std_logic; -- Clock enable for tx_clk
tx_data : out std_logic_vector(7 downto 0); -- Data to MAC transmitter
tx_data_valid : out std_logic; -- Valid signal to MAC transmitter
tx_ack : in std_logic; -- Ack signal from MAC transmitter
tx_underrun : out std_logic; -- Underrun signal to MAC transmitter
tx_collision : in std_logic; -- Collsion signal from MAC transmitter
tx_retransmit : in std_logic; -- Retransmit signal from MAC transmitter
-- Transmit FIFO LocalLink Interface
tx_ll_clock : in std_logic; -- Local link write clock
tx_ll_reset : in std_logic; -- synchronous reset (tx_ll_clock)
tx_ll_data_in : in std_logic_vector(7 downto 0); -- Data to Tx FIFO
tx_ll_sof_in_n : in std_logic; -- sof indicator to FIFO
tx_ll_eof_in_n : in std_logic; -- eof indicator to FIFO
tx_ll_src_rdy_in_n : in std_logic; -- src ready indicator to FIFO
tx_ll_dst_rdy_out_n : out std_logic; -- dst ready indicator from FIFO
tx_fifo_status : out std_logic_vector(3 downto 0); -- FIFO memory status
tx_overflow : out std_logic; -- FIFO overflow indicator from FIFO
-- Receive FIFO MAC RX Interface
rx_clk : in std_logic; -- MAC receive clock
rx_reset : in std_logic; -- Synchronous reset (rx_clk)
rx_enable : in std_logic; -- Clock enable for rx_clk
rx_data : in std_logic_vector(7 downto 0); -- Data from MAC receiver
rx_data_valid : in std_logic; -- Valid signal from MAC receiver
rx_good_frame : in std_logic; -- Good frame indicator from MAC receiver
rx_bad_frame : in std_logic; -- Bad frame indicator from MAC receiver
rx_overflow : out std_logic; -- FIFO overflow indicator from FIFO
-- Receive FIFO LocalLink Interface
rx_ll_clock : in std_logic; -- Local link read clock
rx_ll_reset : in std_logic; -- synchronous reset (rx_ll_clock)
rx_ll_data_out : out std_logic_vector(7 downto 0); -- Data from Rx FIFO
rx_ll_sof_out_n : out std_logic; -- sof indicator from FIFO
rx_ll_eof_out_n : out std_logic; -- eof indicator from FIFO
rx_ll_src_rdy_out_n : out std_logic; -- src ready indicator from FIFO
rx_ll_dst_rdy_in_n : in std_logic; -- dst ready indicator to FIFO
rx_fifo_status : out std_logic_vector(3 downto 0) -- FIFO memory status
);
end eth_fifo_8;
architecture RTL of eth_fifo_8 is
component tx_client_fifo_8
generic (
FULL_DUPLEX_ONLY : boolean);
port (
-- MAC Interface
rd_clk : in std_logic;
rd_sreset : in std_logic;
rd_enable : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
tx_data_valid : out std_logic;
tx_ack : in std_logic;
tx_collision : in std_logic;
tx_retransmit : in std_logic;
overflow : out std_logic;
-- LocalLink Interface
wr_clk : in std_logic;
wr_sreset : in std_logic; -- synchronous reset (write_clock)
wr_data : in std_logic_vector(7 downto 0);
wr_sof_n : in std_logic;
wr_eof_n : in std_logic;
wr_src_rdy_n : in std_logic;
wr_dst_rdy_n : out std_logic;
wr_fifo_status : out std_logic_vector(3 downto 0)
);
end component tx_client_fifo_8;
component rx_client_fifo_8
port (
-- LocalLink Interface
rd_clk : in std_logic;
rd_sreset : in std_logic;
rd_data_out : out std_logic_vector(7 downto 0);
rd_sof_n : out std_logic;
rd_eof_n : out std_logic;
rd_src_rdy_n : out std_logic;
rd_dst_rdy_n : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
-- Client Interface
wr_sreset : in std_logic;
wr_clk : in std_logic;
wr_enable : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_data_valid : in std_logic;
rx_good_frame : in std_logic;
rx_bad_frame : in std_logic;
overflow : out std_logic
);
end component rx_client_fifo_8;
begin
tx_underrun <= '0';
-- Transmitter FIFO
tx_fifo_i : tx_client_fifo_8
generic map (
FULL_DUPLEX_ONLY => FULL_DUPLEX_ONLY)
port map (
rd_clk => tx_clk,
rd_sreset => tx_reset,
rd_enable => tx_enable,
tx_data => tx_data,
tx_data_valid => tx_data_valid,
tx_ack => tx_ack,
tx_collision => tx_collision,
tx_retransmit => tx_retransmit,
overflow => tx_overflow,
wr_clk => tx_ll_clock,
wr_sreset => tx_ll_reset,
wr_data => tx_ll_data_in,
wr_sof_n => tx_ll_sof_in_n,
wr_eof_n => tx_ll_eof_in_n,
wr_src_rdy_n => tx_ll_src_rdy_in_n,
wr_dst_rdy_n => tx_ll_dst_rdy_out_n,
wr_fifo_status => tx_fifo_status
);
-- Receiver FIFO
rx_fifo_i : rx_client_fifo_8
port map (
wr_clk => rx_clk,
wr_enable => rx_enable,
wr_sreset => rx_reset,
rx_data => rx_data,
rx_data_valid => rx_data_valid,
rx_good_frame => rx_good_frame,
rx_bad_frame => rx_bad_frame,
overflow => rx_overflow,
rd_clk => rx_ll_clock,
rd_sreset => rx_ll_reset,
rd_data_out => rx_ll_data_out,
rd_sof_n => rx_ll_sof_out_n,
rd_eof_n => rx_ll_eof_out_n,
rd_src_rdy_n => rx_ll_src_rdy_out_n,
rd_dst_rdy_n => rx_ll_dst_rdy_in_n,
rx_fifo_status => rx_fifo_status
);
end RTL;
|
gpl-3.0
|
3b8489ca23a764818a86133e982726d5
| 0.571341 | 3.768873 | false | false | false | false |
denis4net/hw_design
|
2/altera-project/src/clk.vhd
| 1 | 644 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity CLKBLK is
port (
NCLKEN, NCCLR: in std_logic;
CCK: in std_logic;
IN_CCK: out std_logic
);
end entity;
architecture arch of CLKBLK is
component D_TRIGER
port
(
D, CLK, NRST, NST: in std_logic;
Q, NQ: out std_logic
);
end component;
signal wire0, wire1: std_logic;
signal const_1: std_logic:= '1';
signal const_0: std_logic:= '0';
begin
D0: D_TRIGER port map(D=>wire0, Q=>wire1, NQ=>wire0, CLK=>CCK, NRST=>NCCLR, NST=>const_1);
process (CCK, NCLKEN)
begin
IN_CCK <= not NCLKEN and CCK;
end process;
end;
|
mit
|
b20eb0f13fb096cc597a12a6e2d4f5f2
| 0.677019 | 2.515625 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/mux.vhd
| 1 | 1,699 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
GENERIC(select_width, line_width : positive);
PORT(
INPUT : IN std_logic_vector(2**select_width*line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(line_width-1 DOWNTO 0)
);
END mux;
ARCHITECTURE recursive OF mux IS
SIGNAL submux_0_OUT, submux_1_OUT : std_logic_vector(line_width-1 DOWNTO 0);
COMPONENT mux
GENERIC(select_width, line_width : positive);
PORT(
INPUT : IN std_logic_vector(2**select_width*line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(line_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : mux USE ENTITY WORK.mux(recursive);
BEGIN
mux2to1: IF select_width=1 GENERATE
OUTPUT <= INPUT(2*line_width-1 DOWNTO line_width) WHEN SEL="1"
ELSE INPUT(line_width-1 DOWNTO 0);
END GENERATE;
muxNto1: IF select_width>1 GENERATE
submux_0: mux
GENERIC MAP(select_width => select_width-1, line_width => line_width)
PORT MAP(INPUT => INPUT(2**(select_width-1)*line_width-1 DOWNTO 0),
SEL => SEL(select_width-2 DOWNTO 0),
OUTPUT => submux_0_OUT);
submux_1: mux
GENERIC MAP(select_width => select_width-1, line_width => line_width)
PORT MAP(INPUT => INPUT(2**select_width*line_width-1 DOWNTO 2**(select_width-1)*line_width),
SEL => SEL(select_width-2 DOWNTO 0),
OUTPUT => submux_1_OUT);
OUTPUT <= submux_1_OUT WHEN SEL(select_width-1)='1' ELSE submux_0_OUT;
END GENERATE;
END recursive;
|
bsd-3-clause
|
8014baf54484851e213fada9a3058946
| 0.625662 | 3.344488 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/Nexys4DdrUserDemo.vhd
| 1 | 20,696 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas adapted from Sam Bobrowicz and Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
-- Design Name: Nexys4 DDR User Demo
-- Module Name: Nexys4DdrUserDemo - Behavioral
-- Project Name:
-- Target Devices: Nexys4 DDR Development Board, containing a XC7a100t-1 csg324 device
-- Tool versions:
-- Description:
-- This module represents the top - level design of the Nexys4 DDR User Demo.
-- The project connects to the VGA display in a 1280*1024 resolution and displays various
-- items on the screen:
-- - a Digilent / Analog Devices logo
--
-- - a mouse cursor, if an Usb mouse is connected to the board when the project is started
--
-- - the audio signal from the onboard ADMP421 Omnidirectional Microphone
-- - a small square representing the X and Y acceleration data from the ADXL362 onboard Accelerometer.
-- The square moves according the Nexys4 board position. Note that the X and Y axes
-- on the board are exchanged due to the accelerometer layout on the Nexys4 board.
-- The accelerometer display also displays the acceleration magnitude, calculated as
-- SQRT( X^2 + Y^2 +Z^2), where X, Y and Z represent the acceleration value on the respective axes
--
-- - The FPGA temperature, the onboard ADT7420 temperature sensor temperature value and the accelerometer
-- temperature value
--
-- - The value of the R, G and B components sent to the RGB Leds LD16 and LD17
--
-- Other features:
-- - The 16 Switches (SW0..SW15) are connected to LD0..LD15 except when audio recording is done
--
-- - Pressing BTNL, BTNC and BTNR will toggle between Red, Green and Blue colors on LD16 and LD17
-- Color sweeping returns when BTND is pressed. BTND also togles between LD16, LD17, none or both
--
-- - Pressing BTNU will start audio recording for about 5S, then the audio data will be played back
-- on the Audio output. While recording, LD15..LD0 will show a progressbar moving to left, while
-- playing back, LD15..LD0 will show a progressbar moving to right
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Nexys4DdrUserDemo is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
-- push-buttons
btnl_i : in std_logic;
btnc_i : in std_logic;
btnr_i : in std_logic;
btnd_i : in std_logic;
btnu_i : in std_logic;
-- switches
sw_i : in std_logic_vector(15 downto 0);
-- 7-segment display
disp_seg_o : out std_logic_vector(7 downto 0);
disp_an_o : out std_logic_vector(7 downto 0);
-- leds
led_o : out std_logic_vector(15 downto 0);
-- RGB leds
rgb1_red_o : out std_logic;
rgb1_green_o : out std_logic;
rgb1_blue_o : out std_logic;
rgb2_red_o : out std_logic;
rgb2_green_o : out std_logic;
rgb2_blue_o : out std_logic;
-- VGA display
vga_hs_o : out std_logic;
vga_vs_o : out std_logic;
vga_red_o : out std_logic_vector(3 downto 0);
vga_blue_o : out std_logic_vector(3 downto 0);
vga_green_o : out std_logic_vector(3 downto 0);
-- PDM microphone
pdm_clk_o : out std_logic;
pdm_data_i : in std_logic;
pdm_lrsel_o : out std_logic;
-- PWM audio
pwm_audio_o : inout std_logic;
pwm_sdaudio_o : out std_logic;
-- Temperature sensor
tmp_scl : inout std_logic;
tmp_sda : inout std_logic;
-- tmp_int : in std_logic; -- Not used in this project
-- tmp_ct : in std_logic; -- Not used in this project
-- SPI Interface signals for the ADXL362 accelerometer
sclk : out STD_LOGIC;
mosi : out STD_LOGIC;
miso : in STD_LOGIC;
ss : out STD_LOGIC;
-- PS2 interface signals
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
SCLK_DBG : out STD_LOGIC;
MOSI_DBG : out STD_LOGIC;
MISO_DBG : out STD_LOGIC;
SS_DBG : out STD_LOGIC;
PS2C_DBG : out std_logic;
PS2D_DBG : out std_logic;
-- DDR2 interface signals
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end Nexys4DdrUserDemo;
architecture Behavioral of Nexys4DdrUserDemo is
----------------------------------------------------------------------------------
-- Component Declarations
----------------------------------------------------------------------------------
-- 200 MHz Clock Generator
component ClkGen
port
(-- Clock in ports
clk_100MHz_i : in std_logic;
-- Clock out ports
clk_100MHz_o : out std_logic;
clk_200MHz_o : out std_logic;
-- Status and control signals
reset_i : in std_logic;
locked_o : out std_logic
);
end component;
component RgbLed is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
btnl_i : in std_logic;
btnc_i : in std_logic;
btnr_i : in std_logic;
btnd_i : in std_logic;
pwm1_red_o : out std_logic;
pwm1_green_o : out std_logic;
pwm1_blue_o : out std_logic;
pwm2_red_o : out std_logic;
pwm2_green_o : out std_logic;
pwm2_blue_o : out std_logic;
red_out : out std_logic_vector (7 downto 0);
green_out : out std_logic_vector (7 downto 0);
blue_out : out std_logic_vector (7 downto 0)
);
end component;
component sSegDemo is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
seg_o : out std_logic_vector(7 downto 0);
an_o : out std_logic_vector(7 downto 0));
end component;
component AudioDemo is
port (
-- Common
clk_i : in std_logic;
clk_200_i : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
rst_i : in std_logic;
-- Peripherals
btn_u : in std_logic;
leds_o : out std_logic_vector(15 downto 0);
-- Microphone PDM signals
pdm_m_clk_o : out std_logic; -- Output M_CLK signal to the microphone
pdm_m_data_i : in std_logic; -- Input PDM data from the microphone
pdm_lrsel_o : out std_logic; -- Set to '0', therefore data is read on the positive edge
-- Audio output signals
pwm_audio_o : inout std_logic; -- Output Audio data to the lowpass filters
pwm_sdaudio_o : out std_logic; -- Output Audio enable
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
pdm_clk_rising_o : out std_logic -- Signaling the rising edge of M_CLK, used by the MicDisplay
-- component in the VGA controller
);
end component;
component TempSensorCtl is
Generic (CLOCKFREQ : natural := 100); -- input CLK frequency in MHz
Port (
TMP_SCL : inout STD_LOGIC;
TMP_SDA : inout STD_LOGIC;
-- The Interrupt and Critical Temperature Signals
-- from the ADT7420 Temperature Sensor are not used in this design
-- TMP_INT : in STD_LOGIC;
-- TMP_CT : in STD_LOGIC;
TEMP_O : out STD_LOGIC_VECTOR(12 downto 0); --12-bit two's complement temperature with sign bit
RDY_O : out STD_LOGIC; --'1' when there is a valid temperature reading on TEMP_O
ERR_O : out STD_LOGIC; --'1' if communication error
CLK_I : in STD_LOGIC;
SRST_I : in STD_LOGIC
);
end component;
component AccelerometerCtl is
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
SCLK_FREQUENCY_HZ : integer := 1000000;
NUM_READS_AVG : integer := 16;
UPDATE_FREQUENCY_HZ : integer := 1000
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC; -- Reset button on the Nexys4 board is active low
-- SPI interface Signals
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC;
-- Accelerometer data signals
ACCEL_X_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_Y_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_MAG_OUT : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_TMP_OUT : out STD_LOGIC_VECTOR (11 downto 0)
);
end component;
COMPONENT MouseCtl is
PORT(
clk : in std_logic;
rst : in std_logic;
xpos : out std_logic_vector(11 downto 0);
ypos : out std_logic_vector(11 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
value : in std_logic_vector(11 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
END COMPONENT;
COMPONENT Vga is
PORT(
clk_i : in std_logic;
vga_hs_o : out std_logic;
vga_vs_o : out std_logic;
vga_red_o : out std_logic_vector(3 downto 0);
vga_blue_o : out std_logic_vector(3 downto 0);
vga_green_o : out std_logic_vector(3 downto 0);
RGB_LED_RED : in STD_LOGIC_VECTOR (7 downto 0);
RGB_LED_GREEN : in STD_LOGIC_VECTOR (7 downto 0);
RGB_LED_BLUE : in STD_LOGIC_VECTOR (7 downto 0);
ACCEL_RADIUS : in STD_LOGIC_VECTOR (11 downto 0);
LEVEL_THRESH : in STD_LOGIC_VECTOR (11 downto 0);
ACL_X_IN : in STD_LOGIC_VECTOR (8 downto 0);
ACL_Y_IN : in STD_LOGIC_VECTOR (8 downto 0);
ACL_MAG_IN : in STD_LOGIC_VECTOR (11 downto 0);
MIC_M_DATA_I : IN STD_LOGIC;
MIC_M_CLK_RISING : IN STD_LOGIC;
MOUSE_X_POS : in std_logic_vector (11 downto 0);
MOUSE_Y_POS : in std_logic_vector (11 downto 0);
XADC_TEMP_VALUE_I : in std_logic_vector (11 downto 0);
ADT7420_TEMP_VALUE_I : in std_logic_vector (12 downto 0);
ADXL362_TEMP_VALUE_I : in std_logic_vector (11 downto 0)
);
END COMPONENT;
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------------------------------------------------------------------
-- Inverted input reset signal
signal rst : std_logic;
-- Reset signal conditioned by the PLL lock
signal reset : std_logic;
signal resetn : std_logic;
signal locked : std_logic;
-- 100 MHz buffered clock signal
signal clk_100MHz_buf : std_logic;
-- 200 MHz buffered clock signal
signal clk_200MHz_buf : std_logic;
-- Progressbar signal when recording
signal led_audio : std_logic_vector(15 downto 0);
-- RGB LED signals
signal rgb_led_red: std_logic_vector (7 downto 0);
signal rgb_led_green: std_logic_vector (7 downto 0);
signal rgb_led_blue: std_logic_vector (7 downto 0);
-- ADXL362 Accelerometer data signals
signal ACCEL_X : STD_LOGIC_VECTOR (8 downto 0);
signal ACCEL_Y : STD_LOGIC_VECTOR (8 downto 0);
signal ACCEL_MAG : STD_LOGIC_VECTOR (11 downto 0);
signal ACCEL_TMP : STD_LOGIC_VECTOR (11 downto 0);
-- Mouse data signals
signal MOUSE_X_POS: std_logic_vector (11 downto 0);
signal MOUSE_Y_POS: std_logic_vector (11 downto 0);
-- ADT7420 Temperature Sensor raw Data Signal
signal tempValue : std_logic_vector(12 downto 0);
signal tempRdy, tempErr : std_logic;
-- XADC Temperature Sensor raw Data signal
signal fpgaTempValue : std_logic_vector(11 downto 0);
-- pdm_clk and pdm_clk_rising are needed by the VGA controller
-- to display incoming microphone data
signal pdm_clk : std_logic;
signal pdm_clk_rising : std_logic;
begin
-- Assign LEDs
led_o <= sw_i when (led_audio = X"0000") else led_audio;
-- The Reset Button on the Nexys4 board is active-low,
-- however many components need an active-high reset
rst <= not rstn_i;
-- Assign reset signals conditioned by the PLL lock
reset <= rst or (not locked);
-- active-low version of the reset signal
resetn <= not reset;
-- Assign pdm_clk output
pdm_clk_o <= pdm_clk;
----------------------------------------------------------------------------------
-- 200MHz Clock Generator
----------------------------------------------------------------------------------
Inst_ClkGen: ClkGen
port map (
clk_100MHz_i => clk_i,
clk_100MHz_o => clk_100MHz_buf,
clk_200MHz_o => clk_200MHz_buf,
reset_i => rst,
locked_o => locked
);
----------------------------------------------------------------------------------
-- Rgb Led Controller
----------------------------------------------------------------------------------
Inst_RGB: RgbLed
port map(
clk_i => clk_100MHz_buf,
rstn_i => resetn,
btnl_i => btnl_i,
btnc_i => btnc_i,
btnr_i => btnr_i,
btnd_i => btnd_i,
pwm1_red_o => rgb1_red_o,
pwm1_green_o => rgb1_green_o,
pwm1_blue_o => rgb1_blue_o,
pwm2_red_o => rgb2_red_o,
pwm2_green_o => rgb2_green_o,
pwm2_blue_o => rgb2_blue_o,
RED_OUT => rgb_led_red,
GREEN_OUT => rgb_led_green,
BLUE_OUT => rgb_led_blue
);
----------------------------------------------------------------------------------
-- Seven-Segment Display
----------------------------------------------------------------------------------
Inst_SevenSeg: sSegDemo
port map(
clk_i => clk_100MHz_buf,
rstn_i => resetn,
seg_o => disp_seg_o,
an_o => disp_an_o);
----------------------------------------------------------------------------------
-- Audio Demo
----------------------------------------------------------------------------------
Inst_Audio: AudioDemo
port map(
clk_i => clk_100MHz_buf,
clk_200_i => clk_200MHz_buf,
rst_i => reset,
device_temp_i => fpgaTempValue,
btn_u => btnu_i,
leds_o => led_audio,
pdm_m_clk_o => pdm_clk,
pdm_m_data_i => pdm_data_i,
pdm_lrsel_o => pdm_lrsel_o,
pwm_audio_o => pwm_audio_o,
pwm_sdaudio_o => pwm_sdaudio_o,
-- DDR2 signals
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
pdm_clk_rising_o => pdm_clk_rising
);
----------------------------------------------------------------------------------
-- FPGA Temperature Monitor
----------------------------------------------------------------------------------
Inst_FPGAMonitor: entity work.FPGAMonitor PORT MAP(
CLK_I => clk_100MHz_buf,
RST_I => reset,
TEMP_O => fpgaTempValue
);
----------------------------------------------------------------------------------
-- Temperature Sensor Controller
----------------------------------------------------------------------------------
Inst_TempSensorCtl: TempSensorCtl
GENERIC MAP (CLOCKFREQ => 100)
PORT MAP(
TMP_SCL => TMP_SCL,
TMP_SDA => TMP_SDA,
-- TMP_INT => TMP_INT,
-- TMP_CT => TMP_CT,
TEMP_O => tempValue,
RDY_O => tempRdy,
ERR_O => tempErr,
CLK_I => clk_100MHz_buf,
SRST_I => reset
);
----------------------------------------------------------------------------------
-- Accelerometer Controller
----------------------------------------------------------------------------------
Inst_AccelerometerCtl: AccelerometerCtl
generic map
(
SYSCLK_FREQUENCY_HZ => 100000000,
SCLK_FREQUENCY_HZ => 100000,
NUM_READS_AVG => 16,
UPDATE_FREQUENCY_HZ => 1000
)
port map
(
SYSCLK => clk_100MHz_buf,
RESET => reset,
-- Spi interface Signals
SCLK => sclk,
MOSI => mosi,
MISO => miso,
SS => ss,
-- Accelerometer data signals
ACCEL_X_OUT => ACCEL_X,
ACCEL_Y_OUT => ACCEL_Y,
ACCEL_MAG_OUT => ACCEL_MAG,
ACCEL_TMP_OUT => ACCEL_TMP
);
----------------------------------------------------------------------------------
-- Mouse Controller
----------------------------------------------------------------------------------
Inst_MouseCtl: MouseCtl
PORT MAP
(
clk => clk_100MHz_buf,
rst => reset,
xpos => MOUSE_X_POS,
ypos => MOUSE_Y_POS,
zpos => open,
left => open,
middle => open,
right => open,
new_event => open,
value => x"000",
setx => '0',
sety => '0',
setmax_x => '0',
setmax_y => '0',
ps2_clk => ps2_clk,
ps2_data => ps2_data
);
----------------------------------------------------------------------------------
-- VGA Controller
----------------------------------------------------------------------------------
Inst_VGA: Vga
port map(
clk_i => clk_100MHz_buf,
vga_hs_o => vga_hs_o,
vga_vs_o => vga_vs_o,
vga_red_o => vga_red_o,
vga_blue_o => vga_blue_o,
vga_green_o => vga_green_o,
RGB_LED_RED => rgb_led_red,
RGB_LED_GREEN => rgb_led_green,
RGB_LED_BLUE => rgb_led_blue,
ACCEL_RADIUS => X"007",
LEVEL_THRESH => X"020",
ACL_X_IN => ACCEL_X,
ACL_Y_IN => ACCEL_Y,
ACL_MAG_IN => ACCEL_MAG,
MIC_M_DATA_I => pdm_data_i,
MIC_M_CLK_RISING => pdm_clk_rising,
MOUSE_X_POS => MOUSE_X_POS,
MOUSE_Y_POS => MOUSE_Y_POS,
XADC_TEMP_VALUE_I => fpgaTempValue,
ADT7420_TEMP_VALUE_I => tempValue,
ADXL362_TEMP_VALUE_I => ACCEL_TMP
);
end Behavioral;
|
gpl-3.0
|
b2b7ceb19da10a80b976cf6cd42500d0
| 0.508746 | 3.67276 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/simple_timebase_v1_00_a/hdl/vhdl/user_logic.vhd
| 1 | 6,735 |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Thu Feb 17 10:01:45 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
signal timer : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
begin
process (Bus2IP_Clk, Bus2IP_Reset) is
begin
if Bus2IP_Reset = '1' then
timer <= (others => '0');
elsif rising_edge(Bus2IP_Clk) then
timer <= timer + 1;
if Bus2IP_WrCE(0) = '1' then
timer <= (others => '0');
end if;
end if;
end process;
IP2Bus_Data <= timer;
IP2Bus_WrAck <= Bus2IP_WrCE(0);
IP2Bus_RdAck <= Bus2IP_RdCE(0);
IP2Bus_Error <= '0';
end IMP;
|
gpl-3.0
|
d5d1944093a749c5cdd0ae493805bdcc
| 0.442465 | 4.587875 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/semaphore/hw/pcores/hw_task_v1_01_b/hdl/vhdl/hw_task.vhd
| 1 | 3,181 |
------------
-- pcore top level wrapper
-- generated at 2008-02-11 12:40:48.826899 by 'mkhwtask.py hwt_semaphore_post 1 ../src/hwt_semaphore_post.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 13; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 11; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end hw_task;
architecture structural of hw_task is
component burst_ram
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic
);
end component;
signal o_osif_flat_i : std_logic_vector(0 to 41);
signal i_osif_flat_i : std_logic_vector(0 to 44);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_semaphore_post_i : entity hwt_semaphore_post
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk,
i_timeBase => i_timeBase
);
burst_ram_i : burst_ram
port map (
addra => task2burst_Addr,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkb => clk,
dina => task2burst_Data,
dinb => i_burstData,
douta => burst2task_Data,
doutb => o_burstData,
wea => task2burst_WE,
web => i_burstWE
);
end structural;
|
gpl-3.0
|
35848a0cee60a801ce267dc6c36fa409
| 0.672116 | 2.787905 | false | false | false | false |
luebbers/reconos
|
tools/fsmLanguage/fpga_scripts/pr_scripts/parallel.vhd
| 1 | 10,408 |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parallel is
generic
(
-- The number of input bits into the priority encoder
INPUT_BITS : integer := 128;
-- The number of output bits from the priority encoder.
-- For correct operation the number of output bits should be
-- any number greater than or equal to log2( INPUT_BITS ).
OUTPUT_BITS : integer := 7;
-- The number of bits to consider at a time.
-- This number should be less that INPUT_BITS and should divide
-- INPUT_BITS evenly.
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to INPUT_BITS - 1);
enable : in std_logic;
output : out std_logic_vector(0 to OUTPUT_BITS - 1)
);
end entity parallel;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of parallel is
type find_state is ( narrow_search, prior_encode, prior_read );
-- Find the log base 2 of a natural number.
-- This function works for both synthesis and simulation
function log2( N : in natural ) return positive is
begin
if N <= 2 then
return 1;
else
return 1 + log2(N/2);
end if;
end;
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
-- Return the array slice that is used for a given chunk index
function bit_range( data : in std_logic_vector; index : in integer ) return std_logic_vector is
begin
return data( (index * CHUNK_BITS) to ((index + 1) * CHUNK_BITS) - 1 );
end function;
-- Given the number of INPUT_BITS and the number of CHUNK_BITS we
-- can determine the number of chunks we will need to look at.
constant CHUNK_NUM : integer := INPUT_BITS / CHUNK_BITS;
-- Given the number of CHUNK_BITS we can determine the number of output
-- bits that the priority encoder is going to return.
constant CHUNK_OUT : integer := log2( CHUNK_BITS );
-- The number of EXTRA bits is the number of extra bits that we number add
-- to the output of the priority encoder to get the real output.
constant EXTRA_BITS : integer := OUTPUT_BITS - CHUNK_OUT;
-- Enable signal delayed by 1 clock cycle
signal enable_d1 : std_logic;
-- Encoder finished flag
signal encoder_finished, encoder_finished_next : std_logic;
-- These two signals control the state transitions in the FSM which
-- produces the output for this entity.
signal find_current : find_state;
signal find_next : find_state;
-- These signals are the input signals into the priority encoder.
signal pri_in : std_logic_vector(0 to CHUNK_BITS - 1);
signal pri_in_next : std_logic_vector(0 to CHUNK_BITS - 1);
-- This signal is the output from the priority encoder.
signal pri_out : std_logic_vector(0 to CHUNK_OUT - 1 );
-- This is the overall output from the design. It could be removed
-- by just assigning to output instead, however, that would mean that
-- output would need to be an inout signal instead of just an out.
signal best : std_logic_vector(0 to OUTPUT_BITS - 1);
signal best_next : std_logic_vector(0 to OUTPUT_BITS - 1);
-- These signals are used to narrow our search for the highest priority.
signal narrow : std_logic_vector(0 to CHUNK_NUM - 1);
signal narrow_next : std_logic_vector(0 to CHUNK_NUM - 1);
-- This forces the synthesizer to recognize the pri_out signal as the
-- output from a priority encoder. XST documentation says that the
-- synthesizer will recognize a priority encoder by setting this to
-- "yes" but will not actually generate a priority encoder unless this
-- is set to "force".
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of pri_out: signal is "force";
begin
-- Output the best priority
output <= best;
-- This process is the priority encoder. It will determine the highest bits
-- set in the array pri_in and will return its index on the signal pri_out.
--
-- Notice that this process is NOT sensitive to the clock. This process
-- would not be recognized as a priority encoder if it were sensitive to
-- the clock.
priority_encoder : process ( pri_in ) is
begin
-- The default output. It no bits are set in the array (or if only
-- bit 0 is set) then this is the value returned.
pri_out <= (others => '0');
-- This statement loops over the entire array and finds the index of the
-- highest bit set. The index of the highest bit set is then converted
-- into a std_logic_vector and output onto pri_out.
--
-- Notice that the loop starts at the highest index and proceeds to the
-- lowest index. This is because in our system the lower the bit index
-- the higher the priority.
for i in pri_in'high downto 0 loop
if( pri_in(i) = '1' ) then
pri_out <= std_logic_vector( to_unsigned(i, pri_out'length) );
end if;
end loop;
end process priority_encoder;
-- This process controls the state transition from the current state
-- to the next state (and also handles reset). It also takes care of
-- transitioning FSM inputs to there next values.
find_best_next : process ( clk, rst, find_next ) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
find_current <= narrow_search;
best <= (others => '0');
pri_in <= (others => '0');
narrow <= (others => '0');
encoder_finished <= '0';
else
find_current <= find_next;
best <= best_next;
pri_in <= pri_in_next;
narrow <= narrow_next;
encoder_finished <= encoder_finished_next;
end if;
end if;
end process find_best_next;
delay_reg : process(clk) is
begin
if clk'event and clk = '1' then
if rst = '1' then
enable_d1 <= '0';
else
enable_d1 <= enable;
end if;
end if;
end process delay_reg;
-- This process implements the FSM logic. It is broken into three states.
-- NARROW_SEARCH:
-- This state narrows the priority search by taking each chunk of the input and
-- or'ing all of the chunks bits together. This provides an indication of which
-- chunk of the input contains the highest priority.
--
-- This allows use to use a smaller priority encoder as the expense of a 2 clock
-- cycle delay. However, the smaller priority encoder provides significant savings
-- in terms of slice utilization.
--
-- PRIOR_ENCODE:
-- This state determines which of the chunks contains the highest priority input and
-- then places that chunk's input bits onto the priority encoders input lines. If no
-- bits in the input array are set then the priority encoders input lines are NOT
-- changed.
--
-- PRIOR_READ:
-- This state reads the data off of the priority encoder and then adds the extra bits
-- needed to produce the full priority value. This is done because the priority encoder
-- returns the index of the highest bit of the selected chunk but we want the index
-- of the highest bit set in the input not in the chunk.
--
-- Luckily, the translation from chunk index to input index it straight forward because
-- chunks are just non-overlapping slices of the input array.
find_best_logic : process( find_current, input, best, pri_in, narrow, pri_out, enable, enable_d1, encoder_finished ) is
begin
find_next <= find_current;
best_next <= best;
pri_in_next <= pri_in;
narrow_next <= narrow;
encoder_finished_next <= encoder_finished;
case find_current is
when narrow_search =>
-- Begin when there is an edge on the enable line
if( (enable xor enable_d1) = '1' ) then
encoder_finished_next <= '0';
for i in narrow'high downto 0 loop
narrow_next(i) <= bit_set( bit_range( input, i ) );
end loop;
find_next <= prior_encode;
end if;
when prior_encode =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
pri_in_next <= bit_range( input, i );
--exit;
end if;
end loop;
find_next <= prior_read;
when prior_read =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
best_next <= std_logic_vector(to_unsigned(i,EXTRA_BITS)) & pri_out;
end if;
end loop;
encoder_finished_next <= '1';
find_next <= narrow_search;
end case;
end process find_best_logic;
end architecture imp;
|
gpl-3.0
|
61827768993b7560130475efc144180f
| 0.674289 | 3.642982 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_sim_netlist.vhdl
| 1 | 7,597 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Fri Mar 04 11:10:30 2016
-- Host : Dries007Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_sim_netlist.vhdl
-- Design : clk_wiz_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_1_clk_wiz_1_clk_wiz is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_1_clk_wiz_1_clk_wiz : entity is "clk_wiz_1_clk_wiz";
end clk_wiz_1_clk_wiz_1_clk_wiz;
architecture STRUCTURE of clk_wiz_1_clk_wiz_1_clk_wiz is
signal clk_in1_clk_wiz_1 : STD_LOGIC;
signal clk_out1_clk_wiz_1 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_1 : STD_LOGIC;
signal clkfbout_clk_wiz_1 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_1,
O => clkfbout_buf_clk_wiz_1
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_1
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_1,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 32.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 128.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_1,
CLKFBOUT => clkfbout_clk_wiz_1,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_1,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_1,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_1 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_1 : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of clk_wiz_1 : entity is "clk_wiz_1,clk_wiz_v5_2_1,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_wiz_1;
architecture STRUCTURE of clk_wiz_1 is
begin
inst: entity work.clk_wiz_1_clk_wiz_1_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1
);
end STRUCTURE;
|
mit
|
4fe9f1e3b51f4bdfa1651bf1d2040f63
| 0.648414 | 3.28306 | false | false | false | false |
luebbers/reconos
|
demos/pr_msg_demo/hw/src/thread.vhd
| 1 | 4,326 |
--!
--! \file thread.vhd
--!
--! Demo thread for partial reconfiguration (pr_msg_demo)
--!
--! \author Enno Luebbers <[email protected]>
--! \date 10.02.2011
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 10.02.2011 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity thread is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_THREAD_NUM : integer := 0 -- equals position in chain
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end thread;
architecture Behavioral of thread is
-- OS synchronization state machine states
type t_state is (STATE_INIT, STATE_RECV, STATE_SETBIT, STATE_NOTIFY, STATE_SEND, STATE_EXIT);
signal state : t_state := STATE_INIT;
-- buffer for modifying messages
signal msg : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of repeat cycles
signal repeat_count : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- signature
signal sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
constant C_MB_IN : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_OUT : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_NOTIFY : std_logic_vector(0 to 31) := X"00000002";
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
sig(C_THREAD_NUM) <= '1';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : t_state := STATE_INIT;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, sig);
state <= STATE_INIT;
next_state := STATE_INIT;
done := false;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read number of repeats from init data
when STATE_INIT =>
reconos_get_init_data_s(done, o_osif, i_osif, repeat_count);
next_state := STATE_RECV;
-- read data in message box
when STATE_RECV =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_IN, msg);
next_state := STATE_SETBIT;
-- set message bit
when STATE_SETBIT =>
msg(C_THREAD_NUM) <= '1';
next_state := STATE_NOTIFY;
-- notify main()
when STATE_NOTIFY =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_NOTIFY, sig);
next_state := STATE_SEND;
-- send modified message to next message box
when STATE_SEND =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_OUT, msg);
if repeat_count = 0 then
next_state := STATE_EXIT;
else
repeat_count <= repeat_count - 1;
next_state := STATE_RECV;
end if;
-- terminate
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, C_RECONOS_SUCCESS);
when others =>
next_state := STATE_INIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
71e72d62c61d3696825c5152f9e003f4
| 0.55386 | 3.511364 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/xwb_sdb_crossbar.vhd
| 1 | 7,816 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity xwb_sdb_crossbar is
generic(
g_num_masters : natural := 1;
g_num_slaves : natural := 1;
g_registered : boolean := false;
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Master connections (INTERCON is a slave)
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
-- Slave connections (INTERCON is a master)
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
end xwb_sdb_crossbar;
architecture rtl of xwb_sdb_crossbar is
alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
-- Pretty print device name
function f_trim(s : string) return string is
variable cut : natural;
begin
byte : for i in s'length downto 1 loop
cut := i;
exit byte when s(i) /= ' ';
end loop;
return s(1 to cut);
end f_trim;
-- Step 1. Place the SDB ROM on the bus
-- How much space does the ROM need?
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_bytes : natural := c_sdb_device_length / 8;
constant c_rom_bytes : natural := c_rom_entries * c_sdb_bytes;
-- Step 2. Find the size of the bus
function f_bus_end return unsigned is
variable result : unsigned(63 downto 0);
variable sdb_component : t_sdb_component;
constant zero : t_wishbone_address := (others => '0');
begin
-- The SDB block must be aligned
assert (g_sdb_addr and std_logic_vector(to_unsigned(c_rom_bytes - 1, c_wishbone_address_width))) = zero
report "SDB address is not aligned (" & f_bits2string(g_sdb_addr) & "). This is not supported by the crossbar."
severity Failure;
if not g_wraparound then
result := (others => '0');
for i in 0 to c_wishbone_address_width-1 loop
result(i) := '1';
end loop;
else
-- The ROM will be an addressed slave as well
result := (others => '0');
result(c_wishbone_address_width-1 downto 0) := unsigned(g_sdb_addr);
result := result + to_unsigned(c_rom_bytes, 64) - 1;
for i in g_num_slaves-1 downto 0 loop
if c_layout(i)(7) /= '1' then -- Ignore meta-information
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
if unsigned(sdb_component.addr_last) > result then
result := unsigned(sdb_component.addr_last);
end if;
end if;
end loop;
-- round result up to a power of two -1
for i in 62 downto 0 loop
result(i) := result(i) or result(i+1);
end loop;
end if;
return result;
end f_bus_end;
constant c_bus_end : unsigned(63 downto 0) := f_bus_end;
-- Step 3. Map device address begin values
function f_addresses return t_wishbone_address_array is
variable result : t_wishbone_address_array(g_num_slaves-1 downto 0);
variable sdb_component : t_sdb_component;
variable extend : unsigned(63 downto 0) := (others => '0');
begin
for i in g_num_slaves-1 downto 0 loop
if c_layout(i)(7) = '1' then
-- ignore meta-data
result(i) := (others => '1');
else
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
result(i) := sdb_component.addr_first(c_wishbone_address_width-1 downto 0);
-- Range must be valid
assert unsigned(sdb_component.addr_first) <= unsigned(sdb_component.addr_last)
report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & ") must precede sdb_component.addr_last address (" & f_bits2string(sdb_component.addr_last) & ")."
severity Failure;
-- Address must fit
extend(c_wishbone_address_width-1 downto 0) := unsigned(result(i));
assert unsigned(sdb_component.addr_first) = extend
report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & " does not fit in t_wishbone_address."
severity Failure;
end if;
end loop;
return result;
end f_addresses;
-- Step 3. Map device address end values
function f_masks return t_wishbone_address_array is
variable result : t_wishbone_address_array(g_num_slaves-1 downto 0);
variable sdb_component : t_sdb_component;
variable size : unsigned(63 downto 0);
constant zero : unsigned(63 downto 0) := (others => '0');
begin
for i in g_num_slaves-1 downto 0 loop
if c_layout(i)(7) = '1' then
-- ignore meta-data
result(i) := (others => '0');
else
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
size := unsigned(sdb_component.addr_last) - unsigned(sdb_component.addr_first);
-- size must be of the form 000000...00001111...1
assert (size and (size + to_unsigned(1, 64))) = zero
report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") has an address range that is not a power of 2 minus one (" & f_bits2string(std_logic_vector(size)) & "). This is not supported by the crossbar."
severity Warning;
-- fix the size up to the form 000...0001111...11
for j in c_wishbone_address_width-2 downto 0 loop
size(j) := size(j) or size(j+1);
end loop;
-- the base address must be aligned to the size
assert (unsigned(sdb_component.addr_first) and size) = zero
report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & ") is not aligned. This is not supported by the crossbar."
severity Failure;
size := c_bus_end - size;
result(i) := std_logic_vector(size(c_wishbone_address_width-1 downto 0));
end if;
end loop;
return result;
end f_masks;
constant c_rom_mask : unsigned(63 downto 0) :=
c_bus_end - to_unsigned(c_rom_bytes-1, 64);
constant c_sdb_mask : t_wishbone_address :=
std_logic_vector(c_rom_mask(c_wishbone_address_width-1 downto 0));
constant c_address : t_wishbone_address_array(g_num_slaves downto 0) :=
g_sdb_addr & f_addresses;
constant c_mask : t_wishbone_address_array(g_num_slaves downto 0) :=
c_sdb_mask & f_masks;
signal master_i_1 : t_wishbone_master_in_array(g_num_slaves downto 0);
signal master_o_1 : t_wishbone_master_out_array(g_num_slaves downto 0);
begin
master_i_1(g_num_slaves-1 downto 0) <= master_i;
master_o <= master_o_1(g_num_slaves-1 downto 0);
rom : sdb_rom
generic map(
g_layout => c_layout,
g_bus_end => c_bus_end)
port map(
clk_sys_i => clk_sys_i,
slave_i => master_o_1(g_num_slaves),
slave_o => master_i_1(g_num_slaves));
crossbar : xwb_crossbar
generic map(
g_num_masters => g_num_masters,
g_num_slaves => g_num_slaves + 1,
g_registered => g_registered,
g_address => c_address,
g_mask => c_mask)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => slave_i,
slave_o => slave_o,
master_i => master_i_1,
master_o => master_o_1);
end rtl;
|
lgpl-3.0
|
d6d7961e38680a58f9241b0465203915
| 0.619882 | 3.327373 | false | false | false | false |
luebbers/reconos
|
tests/automated/mbox/hw/hwthreads/mbox/hwt_mbox.vhd
| 1 | 2,524 |
----------------------------------------------------------------------------------
-- Company:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hwt_mbox is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end hwt_mbox;
architecture Behavioral of hwt_mbox is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
constant C_MBOX_GET : std_logic_vector(0 to 31) := X"00000000";
constant C_MBOX_PUT : std_logic_vector(0 to 31) := X"00000001";
type t_state is (STATE_GET, STATE_PUT, STATE_INC);
-- do not rely on initial values here, they won't work with
-- partial reconfiguration
signal state : t_state;
signal value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= clk;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_GET;
value <= X"00AFFE00";
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MBOX_GET, value);
if done and success then state <= STATE_INC; end if;
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_PUT, value);
if done and success then
state <= STATE_GET;
end if;
when STATE_INC =>
value <= value + 1;
state <= STATE_PUT;
when others => state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
fced47c020ad4e74f014d1efa55ef6d3
| 0.602219 | 3.415426 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/semaphore/hw/pcores/hw_task_v1_02_b/hdl/vhdl/hw_task.vhd
| 1 | 3,180 |
------------
-- pcore top level wrapper
-- generated at 2008-02-11 14:35:32.679588 by 'mkhwtask.py hwt_semaphore_wait 2 ../src/hwt_semaphore_wait.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 13; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 11; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end hw_task;
architecture structural of hw_task is
component burst_ram
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic
);
end component;
signal o_osif_flat_i : std_logic_vector(0 to 41);
signal i_osif_flat_i : std_logic_vector(0 to 44);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_semaphore_wait_i : entity hwt_semaphore_wait
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk,
i_timeBase => i_timeBase
);
burst_ram_i : burst_ram
port map (
addra => task2burst_Addr,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkb => clk,
dina => task2burst_Data,
dinb => i_burstData,
douta => burst2task_Data,
doutb => o_burstData,
wea => task2burst_WE,
web => i_burstWE
);
end structural;
|
gpl-3.0
|
04692619add0a308534f058b67ba465e
| 0.672327 | 2.789474 | false | false | false | false |
luebbers/reconos
|
core/pcores/ppc405_virtex4_v1_01_d/hdl/vhdl/ppc405_virtex4.vhd
| 1 | 24,879 |
--
-- \file ppc405_virtex4.vhd
--
-- PowerPC wrapper for Virtex-4
--
-- Used to connect PPC to OSIF
--
-- \author Robet Meiche <[email protected]>
-- \date 22.09.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library ppc405_virtex4_v1_01_a;
use ppc405_virtex4_v1_01_a.all;
library dcr_v29_v1_00_a;
use dcr_v29_v1_00_a.all;
library cpu_osif_adapter_v1_04_a;
use cpu_osif_adapter_v1_04_a.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.ALL;
entity ppc405_virtex4 is
generic (
C_EXT_RESET_HIGH : integer := 1;
CPU_USE_OTHER_CLK : integer := 0;
CPU_RESET_CYCLES : integer := 8;
CPU_MMU_ENABLE : integer := 1;
CPU_DCR_RESYNC : integer := 0;
C_BOOT_SECT_DATA : std_logic_vector := X"4bffd004"
);
port (
clk : in std_logic; --clock from OSIF
cpu_clk : in std_logic; -- Other clock from extern. Configurable via generic
reset : in std_logic;
--signals to osif
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
--debug signals
debug_idle_state : out std_logic;
debug_busy_state : out std_logic;
debug_reconos_ready : out std_logic;
--signal to/from bram_logic
boot_sect_ready : in std_logic;
set_boot_sect : out std_logic;
boot_sect_data : out std_logic_vector(31 downto 0);
--CPU PLB ports
PLBCLK : in std_logic;
C405PLBICUABUS : out std_logic_vector(0 to 31);
C405PLBICUBE : out std_logic_vector(0 to 7);
C405PLBICURNW : out std_logic;
C405PLBICUABORT : out std_logic;
C405PLBICUBUSLOCK : out std_logic;
C405PLBICUU0ATTR : out std_logic;
C405PLBICUGUARDED : out std_logic;
C405PLBICULOCKERR : out std_logic;
C405PLBICUMSIZE : out std_logic_vector(0 to 1);
C405PLBICUORDERED : out std_logic;
C405PLBICUPRIORITY : out std_logic_vector(0 to 1);
C405PLBICURDBURST : out std_logic;
C405PLBICUREQUEST : out std_logic;
C405PLBICUSIZE : out std_logic_vector(0 to 3);
C405PLBICUTYPE : out std_logic_vector(0 to 2);
C405PLBICUWRBURST : out std_logic;
C405PLBICUWRDBUS : out std_logic_vector(0 to 63);
C405PLBICUCACHEABLE : out std_logic;
PLBC405ICUADDRACK : in std_logic;
PLBC405ICUBUSY : in std_logic;
PLBC405ICUERR : in std_logic;
PLBC405ICURDBTERM : in std_logic;
PLBC405ICURDDACK : in std_logic;
PLBC405ICURDDBUS : in std_logic_vector(0 to 63);
PLBC405ICURDWDADDR : in std_logic_vector(0 to 3);
PLBC405ICUREARBITRATE : in std_logic;
PLBC405ICUWRBTERM : in std_logic;
PLBC405ICUWRDACK : in std_logic;
PLBC405ICUSSIZE : in std_logic_vector(0 to 1);
PLBC405ICUSERR : in std_logic;
PLBC405ICUSBUSYS : in std_logic;
C405PLBDCUABUS : out std_logic_vector(0 to 31);
C405PLBDCUBE : out std_logic_vector(0 to 7);
C405PLBDCURNW : out std_logic;
C405PLBDCUSIZE2 : out std_logic;
C405PLBDCUABORT : out std_logic;
C405PLBDCUBUSLOCK : out std_logic;
C405PLBDCUU0ATTR : out std_logic;
C405PLBDCUGUARDED : out std_logic;
C405PLBDCULOCKERR : out std_logic;
C405PLBDCUMSIZE : out std_logic_vector(0 to 1);
C405PLBDCUORDERED : out std_logic;
C405PLBDCUPRIORITY : out std_logic_vector(0 to 1);
C405PLBDCURDBURST : out std_logic;
C405PLBDCUREQUEST : out std_logic;
C405PLBDCUSIZE : out std_logic_vector(0 to 3);
C405PLBDCUTYPE : out std_logic_vector(0 to 2);
C405PLBDCUWRBURST : out std_logic;
C405PLBDCUWRDBUS : out std_logic_vector(0 to 63);
C405PLBDCUCACHEABLE : out std_logic;
C405PLBDCUWRITETHRU : out std_logic;
PLBC405DCUADDRACK : in std_logic;
PLBC405DCUBUSY : in std_logic;
PLBC405DCUERR : in std_logic;
PLBC405DCURDBTERM : in std_logic;
PLBC405DCURDDACK : in std_logic;
PLBC405DCURDDBUS : in std_logic_vector(0 to 63);
PLBC405DCURDWDADDR : in std_logic_vector(0 to 3);
PLBC405DCUREARBITRATE : in std_logic;
PLBC405DCUWRBTERM : in std_logic;
PLBC405DCUWRDACK : in std_logic;
PLBC405DCUSSIZE : in std_logic_vector(0 to 1);
PLBC405DCUSERR : in std_logic;
PLBC405DCUSBUSYS : in std_logic;
--OCM
BRAMDSOCMCLK : in std_logic;
BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31);
DSARCVALUE : in std_logic_vector(0 to 7);
DSCNTLVALUE : in std_logic_vector(0 to 7);
DSOCMBRAMABUS : out std_logic_vector(8 to 29);
DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3);
DSOCMBRAMEN : out std_logic;
DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
DSOCMBUSY : out std_logic;
BRAMISOCMCLK : in std_logic;
BRAMISOCMRDDBUS : in std_logic_vector(0 to 63);
BRAMISOCMDCRRDDBUS : in std_logic_vector(0 to 31);
ISARCVALUE : in std_logic_vector(0 to 7);
ISCNTLVALUE : in std_logic_vector(0 to 7);
ISOCMBRAMEN : out std_logic;
ISOCMBRAMEVENWRITEEN : out std_logic;
ISOCMBRAMODDWRITEEN : out std_logic;
ISOCMBRAMRDABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
DSOCMRDADDRVALID: out std_logic;
DSOCMWRADDRVALID: out std_logic;
DSOCMRWCOMPLETE : in std_logic;
ISOCMDCRBRAMEVENEN : out std_logic;
ISOCMDCRBRAMODDEN : out std_logic;
ISOCMDCRBRAMRDSELECT : out std_logic;
--CPU JTAG Interface
C405JTGCAPTUREDR : out std_logic;
C405JTGEXTEST : out std_logic;
C405JTGPGMOUT : out std_logic;
C405JTGSHIFTDR : out std_logic;
C405JTGTDO : out std_logic;
C405JTGTDOEN : out std_logic;
C405JTGUPDATEDR : out std_logic;
MCBJTAGEN : in std_logic;
JTGC405BNDSCANTDO : in std_logic;
JTGC405TCK : in std_logic;
JTGC405TDI : in std_logic;
JTGC405TMS : in std_logic;
JTGC405TRSTNEG : in std_logic
);
end ppc405_virtex4;
architecture structural of ppc405_virtex4 is
--constants for DCR
constant C_DCR_AWIDTH : integer := 10;
constant C_DCR_DWIDTH : integer := 32;
--constants for OSIF_ADAPTER
constant COMMANDREG_WIDTH : integer := 5;
constant DATAREG_WIDTH : integer := 32;
constant DONEREG_WIDTH : integer := 1;
constant CPU_DWIDTH : integer := 32;
--BOOTCODE for CPU_Start
--constant C_BOOT_SECT_DATA : std_logic_vector := X"4bffd004";--X"4bffd004";--X"4bfffff0";X"48000000";
--signals --------------------------------------------------------------------
---CPU_DCR -> CPU_HWT_DCR
signal CPU_C405DCRABUS : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal CPU_C405DCRDBUSOUT: std_logic_vector(0 to C_DCR_DWIDTH-1);
signal CPU_DCRC405DBUSIN : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal CPU_C405DCRREAD : std_logic;
signal CPU_C405DCRWRITE : std_logic;
signal CPU_DCRC405ACK : std_logic;
---OSIF_ADPTER -> CPU_HWT_DCR
signal o_dcrDBus : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal i_dcrABus : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal i_dcrDBus : std_logic_vector(0 to C_DCR_DWIDTH-1);
---Connect Ack, Read, Write to DCR
signal o_dcrAck_vec : std_logic_vector(0 to 0);
signal i_dcrRead_vec : std_logic_vector(0 to 0);
signal i_dcrWrite_vec : std_logic_vector(0 to 0);
---OSIF_ADAPTER -> PPC
signal cpu_reset : std_logic;
--OSIF_FLAT / Reset / busylocal
signal o_osif_flat_i : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal i_osif_flat_i : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal busy_local : std_logic;
signal i_reset : std_logic;
--clk signal for PowerPC
signal ppc_clk : std_logic;
--CPU signals which are not used
signal CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405TIMERCLKEN, CPMC405TIMERTICK, MCBCPUCLKEN, MCBTIMEREN, MCPPCRST : std_logic;
signal CPMC405CORECLKINACTIVE, RSTC405RESETCHIP, RSTC405RESETSYS : std_logic;
signal C405CPMCORESLEEPREQ,C405CPMMSRCE,C405CPMMSREE,C405CPMTIMERIRQ,C405CPMTIMERRESETREQ,C405XXXMACHINECHECK : std_logic;
signal EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ : std_logic;
signal C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT : std_logic;
signal C405DBGWBIAR : std_logic_vector(0 to 29);
--other sigs
signal net_vcc0 : std_logic;
begin
--other sigs
net_vcc0 <= '1';
--Processess for the GENERICS ---------------------------------------------------
--C_EXT_RESET_HIGH
RSTPROCESS: process(reset)
begin
if C_EXT_RESET_HIGH = 1 then
i_reset <= reset;
else
i_reset <= not reset;
end if;
end process;
--CPU_USE_OTHER_CLK :
--if 1 then use port cpu_clk otherwise use threadclk_port clk
CPU_CLK_PROCESS: process(clk, cpu_clk)
begin
if CPU_USE_OTHER_CLK = 1 then
ppc_clk <= cpu_clk;
else
ppc_clk <= clk;
end if;
end process;
--Process and assignments for OSIF ----------------------------------------------
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
-- overlay busy with local busy signal
--i_osif <= to_osif_os2task_t(i_osif_flat_i);
i_osif <= to_osif_os2task_t(i_osif_flat_i or (X"0000000000" & busy_local & "000000"));
register_osif_ports_proc: process(clk)
begin
if rising_edge(clk) then
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
end if;
end process;
-- infer latch for local busy signal
-- needed for asynchronous communication between thread and OSIF
busy_local_gen : process(i_reset, o_osif.request, i_osif.ack)
begin
if i_reset = '1' then
busy_local <= '0';
elsif o_osif.request = '1' then
busy_local <= '1';
elsif i_osif.ack = '1' then
busy_local <= '0';
end if;
end process;
--------- COMPONENTS ------------------------------------------------------------
cpu_osif_adapter_i : entity cpu_osif_adapter_v1_04_a.cpu_osif_adapter
generic map (
C_BASEADDR => B"0000011000",
C_HIGHADDR => B"0000011111",
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
COMMANDREG_WIDTH => COMMANDREG_WIDTH,
DATAREG_WIDTH => DATAREG_WIDTH,
DONEREG_WIDTH => DONEREG_WIDTH,
CPU_RESET_CYCLES => CPU_RESET_CYCLES,
CPU_DWIDTH => CPU_DWIDTH,
C_BOOT_SECT_DATA => C_BOOT_SECT_DATA
)
port map (
clk => clk,
reset => i_reset,
--dcr signals for Main CPU
o_dcrAck => o_dcrAck_vec(0),
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead_vec(0),
i_dcrWrite => i_dcrWrite_vec(0),
--signals to osif
i_osif => i_osif,
o_osif => o_osif,
cpu_reset => cpu_reset,
--debug signals
debug_idle_state => debug_idle_state,
debug_busy_state => debug_busy_state,
debug_reconos_ready => debug_reconos_ready,
--signal to/from bram_logic
boot_sect_ready => boot_sect_ready,
set_boot_sect => set_boot_sect,
boot_sect_data => boot_sect_data
);
CPU_HWT_DCR_BUS : entity dcr_v29_v1_00_a.dcr_v29
generic map (
C_DCR_NUM_SLAVES => 1,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_USE_LUT_OR => 1
)
port map (
M_dcrABus => CPU_C405DCRABUS,
M_dcrDBus => CPU_C405DCRDBUSOUT,
M_dcrRead => CPU_C405DCRREAD,
M_dcrWrite => CPU_C405DCRWRITE,
DCR_M_DBus => CPU_DCRC405DBUSIN,
DCR_Ack => CPU_DCRC405ACK,
DCR_ABus => i_dcrABus,
DCR_Sl_DBus => i_dcrDBus,
DCR_Read => i_dcrRead_vec,
DCR_Write => i_dcrWrite_vec,
Sl_dcrDBus => o_dcrDBus,
Sl_dcrAck => o_dcrAck_vec
);
CPU_HWT : entity ppc405_virtex4_v1_01_a.ppc405_virtex4
generic map (
-- C_IDCR_BASEADDR => B"0000010000",
-- C_IDCR_HIGHADDR => B"0000010011",
C_DISABLE_OPERAND_FORWARDING => 1,
C_MMU_ENABLE => CPU_MMU_ENABLE,
C_DETERMINISTIC_MULT => 0,
C_PLBSYNCBYPASS => 1,
C_APU_CONTROL => B"1101111000000000",
C_APU_UDI_1 => B"101000011000100110000011",
C_APU_UDI_2 => B"101000111000100110000011",
C_APU_UDI_3 => B"101001011000100111000011",
C_APU_UDI_4 => B"101001111000100111000011",
C_APU_UDI_5 => B"101010011000110000000011",
C_APU_UDI_6 => B"101010111000110000000011",
C_APU_UDI_7 => B"101011011000110001000011",
C_APU_UDI_8 => B"101011111000110001000011",
C_PVR_HIGH => B"0000",
C_PVR_LOW => B"0000"
)
port map (
CPMC405CLOCK => ppc_clk,
CPMDCRCLK => clk,
CPMFCMCLK => net_vcc0,
C405RSTCHIPRESETREQ => open,
C405RSTCORERESETREQ => open,
C405RSTSYSRESETREQ => open,
RSTC405RESETCHIP => '0',--RSTC405RESETCHIP,
RSTC405RESETCORE => cpu_reset,
RSTC405RESETSYS => '0',--RSTC405RESETSYS,
--PLB signals
PLBCLK => PLBCLK,
C405PLBICUABUS => C405PLBICUABUS,
C405PLBICUBE => C405PLBICUBE,
C405PLBICURNW => C405PLBICURNW,
C405PLBICUABORT => C405PLBICUABORT,
C405PLBICUBUSLOCK => C405PLBICUBUSLOCK,
C405PLBICUU0ATTR => C405PLBICUU0ATTR,
C405PLBICUGUARDED => C405PLBICUGUARDED,
C405PLBICULOCKERR => C405PLBICULOCKERR,
C405PLBICUMSIZE => C405PLBICUMSIZE,
C405PLBICUORDERED => C405PLBICUORDERED,
C405PLBICUPRIORITY => C405PLBICUPRIORITY,
C405PLBICURDBURST => C405PLBICURDBURST,
C405PLBICUREQUEST => C405PLBICUREQUEST,
C405PLBICUSIZE => C405PLBICUSIZE,
C405PLBICUTYPE => C405PLBICUTYPE,
C405PLBICUWRBURST => C405PLBICUWRBURST,
C405PLBICUWRDBUS => C405PLBICUWRDBUS,
C405PLBICUCACHEABLE => C405PLBICUCACHEABLE,
PLBC405ICUADDRACK => PLBC405ICUADDRACK,
PLBC405ICUBUSY => PLBC405ICUBUSY,
PLBC405ICUERR => PLBC405ICUERR,
PLBC405ICURDBTERM => PLBC405ICURDBTERM,
PLBC405ICURDDACK => PLBC405ICURDDACK,
PLBC405ICURDDBUS => PLBC405ICURDDBUS,
PLBC405ICURDWDADDR => PLBC405ICURDWDADDR,
PLBC405ICUREARBITRATE => PLBC405ICUREARBITRATE,
PLBC405ICUWRBTERM => PLBC405ICUWRBTERM,
PLBC405ICUWRDACK => PLBC405ICUWRDACK,
PLBC405ICUSSIZE => PLBC405ICUSSIZE,
PLBC405ICUSERR => PLBC405ICUSERR,
PLBC405ICUSBUSYS => PLBC405ICUSBUSYS,
C405PLBDCUABUS => C405PLBDCUABUS,
C405PLBDCUBE => C405PLBDCUBE,
C405PLBDCURNW => C405PLBDCURNW,
C405PLBDCUABORT => C405PLBDCUABORT,
C405PLBDCUBUSLOCK => C405PLBDCUBUSLOCK,
C405PLBDCUU0ATTR => C405PLBDCUU0ATTR,
C405PLBDCUGUARDED => C405PLBDCUGUARDED,
C405PLBDCULOCKERR => C405PLBDCULOCKERR,
C405PLBDCUMSIZE => C405PLBDCUMSIZE,
C405PLBDCUORDERED => C405PLBDCUORDERED,
C405PLBDCUPRIORITY => C405PLBDCUPRIORITY,
C405PLBDCURDBURST => C405PLBDCURDBURST,
C405PLBDCUREQUEST => C405PLBDCUREQUEST,
C405PLBDCUSIZE => C405PLBDCUSIZE,
C405PLBDCUTYPE => C405PLBDCUTYPE,
C405PLBDCUWRBURST => C405PLBDCUWRBURST,
C405PLBDCUWRDBUS => C405PLBDCUWRDBUS,
C405PLBDCUCACHEABLE => C405PLBDCUCACHEABLE,
C405PLBDCUWRITETHRU => C405PLBDCUWRITETHRU,
PLBC405DCUADDRACK => PLBC405DCUADDRACK,
PLBC405DCUBUSY => PLBC405DCUBUSY,
PLBC405DCUERR => PLBC405DCUERR,
PLBC405DCURDBTERM => PLBC405DCURDBTERM,
PLBC405DCURDDACK => PLBC405DCURDDACK,
PLBC405DCURDDBUS => PLBC405DCURDDBUS,
PLBC405DCURDWDADDR => PLBC405DCURDWDADDR,
PLBC405DCUREARBITRATE => PLBC405DCUREARBITRATE,
PLBC405DCUWRBTERM => PLBC405DCUWRBTERM,
PLBC405DCUWRDACK => PLBC405DCUWRDACK,
PLBC405DCUSSIZE => PLBC405DCUSSIZE,
PLBC405DCUSERR => PLBC405DCUSERR,
PLBC405DCUSBUSYS => PLBC405DCUSBUSYS,
--ocm signals
BRAMDSOCMCLK => BRAMDSOCMCLK,
BRAMDSOCMRDDBUS => BRAMDSOCMRDDBUS,
DSARCVALUE => DSARCVALUE,
DSCNTLVALUE => DSCNTLVALUE,
DSOCMBRAMABUS => DSOCMBRAMABUS,
DSOCMBRAMBYTEWRITE => DSOCMBRAMBYTEWRITE,
DSOCMBRAMEN => DSOCMBRAMEN,
DSOCMBRAMWRDBUS => DSOCMBRAMWRDBUS,
DSOCMBUSY => DSOCMBUSY,
BRAMISOCMCLK => BRAMISOCMCLK,
BRAMISOCMRDDBUS => BRAMISOCMRDDBUS,
BRAMISOCMDCRRDDBUS => BRAMISOCMDCRRDDBUS,
ISARCVALUE => ISARCVALUE,
ISCNTLVALUE => ISCNTLVALUE,
ISOCMBRAMEN => ISOCMBRAMEN,
ISOCMBRAMEVENWRITEEN => ISOCMBRAMEVENWRITEEN,
ISOCMBRAMODDWRITEEN => ISOCMBRAMODDWRITEEN,
ISOCMBRAMRDABUS => ISOCMBRAMRDABUS,
ISOCMBRAMWRABUS => ISOCMBRAMWRABUS,
ISOCMBRAMWRDBUS => ISOCMBRAMWRDBUS,
DSOCMRDADDRVALID=> DSOCMRDADDRVALID,
DSOCMWRADDRVALID=> DSOCMWRADDRVALID,
DSOCMRWCOMPLETE => DSOCMRWCOMPLETE,
ISOCMDCRBRAMEVENEN => ISOCMDCRBRAMEVENEN,
ISOCMDCRBRAMODDEN => ISOCMDCRBRAMODDEN,
ISOCMDCRBRAMRDSELECT => ISOCMDCRBRAMRDSELECT,
--DCR signals
EXTDCRABUS => CPU_C405DCRABUS,
EXTDCRDBUSOUT => CPU_C405DCRDBUSOUT,
EXTDCRREAD => CPU_C405DCRREAD,
EXTDCRWRITE => CPU_C405DCRWRITE,
EXTDCRACK => CPU_DCRC405ACK,
EXTDCRDBUSIN => CPU_DCRC405DBUSIN,
-- JTAG Interface
C405JTGCAPTUREDR => C405JTGCAPTUREDR, -- O
C405JTGEXTEST => C405JTGEXTEST, -- O
C405JTGPGMOUT => C405JTGPGMOUT, -- O
C405JTGSHIFTDR => C405JTGSHIFTDR, -- O
C405JTGTDO => C405JTGTDO, -- O
C405JTGTDOEN => C405JTGTDOEN, -- O
C405JTGUPDATEDR => C405JTGUPDATEDR, -- O
MCBJTAGEN => net_vcc0,--MCBJTAGEN, -- I
JTGC405BNDSCANTDO => JTGC405BNDSCANTDO, -- I
JTGC405TCK => JTGC405TCK, -- I
JTGC405TDI => JTGC405TDI, -- I
JTGC405TMS => JTGC405TMS, -- I
JTGC405TRSTNEG => JTGC405TRSTNEG,
--Ports which are not used -----------------------------------------------
--emac DCR signals
DCREMACABUS => open,
DCREMACCLK => open,
DCREMACDBUS => open,
DCREMACENABLER => open,
DCREMACREAD => open,
DCREMACWRITE => open,
EMACDCRACK => '0',
EMACDCRDBUS => X"00000000",
--FCM/APU
APUFCMDECODED => open,
APUFCMDECUDI => open,
APUFCMDECUDIVALID => open,
APUFCMENDIAN => open,
APUFCMFLUSH => open,
APUFCMINSTRUCTION => open,
APUFCMINSTRVALID => open,
APUFCMLOADBYTEEN => open,
APUFCMLOADDATA => open,
APUFCMLOADDVALID => open,
APUFCMOPERANDVALID => open,
APUFCMRADATA => open,
APUFCMRBDATA => open,
APUFCMWRITEBACKOK => open,
APUFCMXERCA => open,
FCMAPUCR => "0000",
FCMAPUDCDCREN => '0',
FCMAPUDCDFORCEALIGN => '0',
FCMAPUDCDFORCEBESTEERING => '0',
FCMAPUDCDFPUOP => '0',
FCMAPUDCDGPRWRITE => '0',
FCMAPUDCDLDSTBYTE => '0',
FCMAPUDCDLDSTDW => '0',
FCMAPUDCDLDSTHW => '0',
FCMAPUDCDLDSTQW => '0',
FCMAPUDCDLDSTWD => '0',
FCMAPUDCDLOAD => '0',
FCMAPUDCDPRIVOP => '0',
FCMAPUDCDRAEN => '0',
FCMAPUDCDRBEN => '0',
FCMAPUDCDSTORE => '0',
FCMAPUDCDTRAPBE => '0',
FCMAPUDCDTRAPLE => '0',
FCMAPUDCDUPDATE => '0',
FCMAPUDCDXERCAEN => '0',
FCMAPUDCDXEROVEN => '0',
FCMAPUDECODEBUSY => '0',
FCMAPUDONE => '0',
FCMAPUEXCEPTION => '0',
FCMAPUEXEBLOCKINGMCO => '0',
FCMAPUEXECRFIELD => "000",
FCMAPUEXENONBLOCKINGMCO => '0',
FCMAPUINSTRACK => '0',
FCMAPULOADWAIT => '0',
FCMAPURESULT => X"00000000",
FCMAPURESULTVALID => '0',
FCMAPUSLEEPNOTREADY => '0',
FCMAPUXERCA => '0',
FCMAPUXEROV => '0',
---------------------------
CPMC405CORECLKINACTIVE => '0',--CPMC405CORECLKINACTIVE, -- I
CPMC405CPUCLKEN => net_vcc0, --CPMC405CPUCLKEN, -- I
CPMC405JTAGCLKEN => net_vcc0, --CPMC405JTAGCLKEN, -- I
CPMC405TIMERCLKEN => net_vcc0, --CPMC405TIMERCLKEN, -- I
CPMC405TIMERTICK => net_vcc0, --CPMC405TIMERTICK, -- I
MCBCPUCLKEN => net_vcc0, --MCBCPUCLKEN, -- I
MCBTIMEREN => net_vcc0, --MCBTIMEREN, -- I
MCPPCRST => net_vcc0, --MCPPCRST,
C405CPMCORESLEEPREQ => C405CPMCORESLEEPREQ, -- O
C405CPMMSRCE => C405CPMMSRCE, -- O
C405CPMMSREE => C405CPMMSREE, -- O
C405CPMTIMERIRQ => C405CPMTIMERIRQ, -- O
C405CPMTIMERRESETREQ => C405CPMTIMERRESETREQ, -- O
C405XXXMACHINECHECK => C405XXXMACHINECHECK, -- O
-- Interrupt Controller Interface
EICC405CRITINPUTIRQ => '0',--EICC405CRITINPUTIRQ, -- I
EICC405EXTINPUTIRQ => '0',--EICC405EXTINPUTIRQ, -- I
-- Debug Interface
C405DBGLOADDATAONAPUDBUS => open,
C405DBGMSRWE => C405DBGMSRWE, -- O
C405DBGSTOPACK => C405DBGSTOPACK, -- O
C405DBGWBCOMPLETE => C405DBGWBCOMPLETE, -- O
C405DBGWBFULL => C405DBGWBFULL, -- O
C405DBGWBIAR => C405DBGWBIAR, -- O [0:29]
DBGC405DEBUGHALT => '0',--DBGC405DEBUGHALT, -- I
DBGC405EXTBUSHOLDACK => '0',--DBGC405EXTBUSHOLDACK, -- I
DBGC405UNCONDDEBUGEVENT => '0',--DBGC405UNCONDDEBUGEVENT,
-- Trace Interface
C405TRCCYCLE => open , -- O
C405TRCEVENEXECUTIONSTATUS => open, -- O [0:1]
C405TRCODDEXECUTIONSTATUS => open, -- O [0:1]
C405TRCTRACESTATUS => open, -- O [0:3]
C405TRCTRIGGEREVENTOUT => open, -- O
C405TRCTRIGGEREVENTTYPE => open, -- O [0:10]
TRCC405TRACEDISABLE => '0', -- I
TRCC405TRIGGEREVENTIN => '0' -- I
);
end structural;
|
gpl-3.0
|
6df036ff545d2519df9de2804039a7b4
| 0.576711 | 4.108836 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/thermal_monitor_v1_03_a/hdl/vhdl/user_logic.vhd
| 1 | 9,658 |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library thermal_monitor_v1_03_a;
use thermal_monitor_v1_03_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
--C_NUM_SENSORS : integer := 100;
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
sample_clk : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of sample_clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-- component icon
-- port (
-- CONTROL0 : inout std_logic_vector(35 downto 0));
-- end component;
--
-- ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-- component chipscope_ila
-- port (
-- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-- CLK : IN STD_LOGIC;
-- TRIG0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
-- end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of IMP: architecture is "true";
constant C_NUM_SENSORS : integer := C_NUM_REG;
constant C_OSC_INIT_CYCLES : integer := 1024*8;
constant C_OSC_MEASURE_CYCLES : integer := 131072; --8192;
constant C_ADDR_WIDTH : integer := integer(ceil(log2(real(C_NUM_SENSORS))));
constant C_COUNTER_WIDTH : integer := integer(ceil(log2(real(2*C_OSC_MEASURE_CYCLES))));
-- sensor net interface
type data_t is array(0 to C_NUM_SENSORS - 1) of std_logic_vector (C_COUNTER_WIDTH - 1 downto 0);
-- data signals from all sensors
signal data_net : data_t;
-- debug signals for sensors
signal osc_sig_net : std_logic_vector (C_NUM_SENSORS - 1 downto 0);
signal count_sig_net : std_logic_vector (C_NUM_SENSORS - 1 downto 0);
-- data to bus logic
signal data_out : std_logic_vector(C_COUNTER_WIDTH - 1 downto 0);
-- enable signal for ring oscillators
signal osc_en : std_logic;
-- enable signal to oscillation counters
signal rec_en : std_logic;
-- running = '1' during measurement
shared variable running : std_logic;
-- icon + ila signals
-- signal control0 : std_logic_vector(35 downto 0);
-- signal trig0 : std_logic_vector(3 downto 0);
-- signal trig1 : std_logic_vector(31 downto 0);
-- signal trig2 : std_logic_vector(31 downto 0);
-- signal trig3 : std_logic_vector(31 downto 0);
-- signal trig4 : std_logic_vector(31 downto 0);
-- signal trig5 : std_logic_vector(31 downto 0);
-- signal trig6 : std_logic_vector(31 downto 0);
-- signal trig7 : std_logic_vector(31 downto 0);
-- signal trig8 : std_logic_vector(31 downto 0);
-- signal trig9 : std_logic_vector(31 downto 0);
begin
-- instantiate ila and icon;
-- icon_i : icon
-- port map (
-- CONTROL0 => control0);
--
-- ila_i : chipscope_ila
-- port map (
-- CONTROL => control0,
-- CLK => sample_clk,
-- TRIG0 => trig0,
-- TRIG1 => trig1,
-- TRIG2 => trig2,
-- TRIG3 => trig3,
-- TRIG4 => trig4,
-- TRIG5 => trig5,
-- TRIG6 => trig6,
-- TRIG7 => trig7,
-- TRIG8 => trig8,
-- TRIG9 => trig9);
--
-- trig0(3) <= osc_en;
-- trig0(2) <= rec_en;
-- trig0(1) <= Bus2IP_Reset;
-- trig0(0) <= sample_clk;
-- Note: contrary to the documentation read and write ack signals can not be tied to '1'.
-- This would lead to the bus being locked forever.
-- connect data_out to bus logic
IP2Bus_Data(C_SLV_DWIDTH - 1 downto C_COUNTER_WIDTH) <= (others => '0');
IP2Bus_Data(C_COUNTER_WIDTH - 1 downto 0) <= data_out;
-- array of thermal sensors
thermal_sensors : for i in C_NUM_SENSORS - 1 downto 0 generate
begin
sensor : entity thermal_sensor
generic map (C_COUNTER_WIDTH => C_COUNTER_WIDTH)
port map (
clk => sample_clk,
rst => Bus2IP_Reset,
rec_en => rec_en,
osc_en => osc_en,
data => data_net(i),
osc_sig => osc_sig_net(i),
count_sig => count_sig_net(i)
);
end generate thermal_sensors;
-- debug_proc : process (osc_sig_net, count_sig_net) is
-- variable i : std_logic;
-- begin
-- for i in 0 to C_NUM_SENSORS - 1 loop
-- if i < 16 then
-- trig1(2*i) <= osc_sig_net(i);
-- trig1(2*i+1) <= count_sig_net(i);
-- elsif i < 32 then
-- trig2(2*(i-16)) <= osc_sig_net(i);
-- trig2(2*(i-16)+1) <= count_sig_net(i);
-- elsif i < 48 then
-- trig3(2*(i-32)) <= osc_sig_net(i);
-- trig3(2*(i-32)+1) <= count_sig_net(i);
-- elsif i < 64 then
-- trig4(2*(i-48)) <= osc_sig_net(i);
-- trig4(2*(i-48)+1) <= count_sig_net(i);
-- elsif i < 80 then
-- trig5(2*(i-64)) <= osc_sig_net(i);
-- trig5(2*(i-64)+1) <= count_sig_net(i);
-- elsif i < 96 then
-- trig6(2*(i-80)) <= osc_sig_net(i);
-- trig6(2*(i-80)+1) <= count_sig_net(i);
-- elsif i < 112 then
-- trig7(2*(i-96)) <= osc_sig_net(i);
-- trig7(2*(i-96)+1) <= count_sig_net(i);
-- elsif i < 128 then
-- trig8(2*(i-112)) <= osc_sig_net(i);
-- trig8(2*(i-112)+1) <= count_sig_net(i);
-- elsif i < 144 then
-- trig9(2*(i-128)) <= osc_sig_net(i);
-- trig9(2*(i-128)+1) <= count_sig_net(i);
-- end if;
-- end loop;
-- end process;
-- mux sensor signals to data_out, generate read ack
process(data_net) is
begin
IP2Bus_RdAck <= '0';
data_out <= (others => '0');
for i in C_NUM_SENSORS - 1 downto 0 loop
if Bus2IP_RdCE(i) = '1' then
data_out <= data_net(i);
if running = '0' then
IP2Bus_RdAck <= '1';
end if;
end if;
end loop;
end process;
-- measurement process, generate write ack
process(Bus2IP_Clk, Bus2IP_Reset) is
variable counter : integer range 0 to (2*(C_OSC_INIT_CYCLES + C_OSC_MEASURE_CYCLES));
--variable running : std_logic;
variable ack : std_logic;
begin
if Bus2IP_Reset = '1' then
counter := 0;
running := '1';
osc_en <= '0';
rec_en <= '0';
IP2Bus_WrAck <= '0';
elsif rising_edge(Bus2IP_Clk) then
-- generate write ack
IP2Bus_WrAck <= '0';
ack := '0';
for i in C_NUM_REG - 1 downto 0 loop
ack := ack or Bus2IP_WrCE(i);
end loop;
IP2Bus_WrAck <= ack;
-- oscillator timing
if ack = '1' then
if running = '0' then counter := 0; end if;
running := '1';
end if;
-- wait for oscillators to settle to a constant frequency, then perform measurement
if running = '1' then
counter := counter + 1;
osc_en <= '1';
if counter > C_OSC_INIT_CYCLES then
rec_en <= '1';
end if;
if counter = C_OSC_INIT_CYCLES + C_OSC_MEASURE_CYCLES then
running := '0';
rec_en <= '0';
osc_en <= '0';
end if;
end if;
end if;
end process;
-- no errors since all reads and writes are valid
IP2Bus_Error <= '0';
end IMP;
|
gpl-3.0
|
f99832f14c467df8703a5ada72de0f8c
| 0.543487 | 3.10347 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_init.vhd
| 3 | 1,482 |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests signal initializers.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_init is
end;
architecture test of vhdl_init is
-- Convert string to bitstring in initalizer
signal a : std_logic_vector(7 downto 0) := "11101001";
-- Initialize with aggregate expression
signal b : std_logic_vector(3 downto 0) := (0 => '0', 3 => '1', 1 => '1', 2 => '0');
-- Initialize with aggregate expression, inverted range
signal c : std_logic_vector(0 to 3) := (3 => '1', others => '0');
begin
-- Architecture statement part cannot be empty
-- Assign the previous value, otherwise you will get unknown value
a <= "11101001";
end test;
|
gpl-2.0
|
8350bb335a5c752684281b98fcc771f5
| 0.706478 | 3.962567 | false | true | false | false |
makestuff/vhdl
|
memctrl/memctrl/hexutil.vhdl
| 1 | 2,992 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hexutil is
function to_1(c : character) return std_logic;
function to_2(c : character) return std_logic_vector;
function to_3(c : character) return std_logic_vector;
function to_4(c : character) return std_logic_vector;
end package;
package body hexutil is
-- Return the bits of the supplied hex nibble
function to_4(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
case c is
when '0' =>
nibble := "0000";
when '1' =>
nibble := "0001";
when '2' =>
nibble := "0010";
when '3' =>
nibble := "0011";
when '4' =>
nibble := "0100";
when '5' =>
nibble := "0101";
when '6' =>
nibble := "0110";
when '7' =>
nibble := "0111";
when '8' =>
nibble := "1000";
when '9' =>
nibble := "1001";
when 'a' =>
nibble := "1010";
when 'A' =>
nibble := "1010";
when 'b' =>
nibble := "1011";
when 'B' =>
nibble := "1011";
when 'c' =>
nibble := "1100";
when 'C' =>
nibble := "1100";
when 'd' =>
nibble := "1101";
when 'D' =>
nibble := "1101";
when 'e' =>
nibble := "1110";
when 'E' =>
nibble := "1110";
when 'f' =>
nibble := "1111";
when 'F' =>
nibble := "1111";
when 'X' =>
nibble := "XXXX";
when 'x' =>
nibble := "XXXX";
when 'Z' =>
nibble := "ZZZZ";
when 'z' =>
nibble := "ZZZZ";
when others =>
nibble := "UUUU";
end case;
return nibble;
end function;
-- Return the least-significant bit of the supplied hex nibble
function to_1(c : character) return std_logic is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(0);
end function;
-- Return two least-significant bits of the supplied hex nibble
function to_2(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(1 downto 0);
end function;
-- Return three least-significant bits of the supplied hex nibble
function to_3(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(2 downto 0);
end function;
end package body;
|
gpl-3.0
|
1cd173bb37f235b1ff694b9fe0090887
| 0.624332 | 3.169492 | false | false | false | false |
denis4net/hw_design
|
2/altera-project/src/dtriger.vhd
| 1 | 837 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_TRIGER is
port
(
D, CLK, NRST, NST: in std_logic;
Q, NQ: out std_logic
);
end D_TRIGER;
architecture arch of D_TRIGER is
signal r: std_logic := '0';
begin
Q <= r;
NQ <= not r;
process(CLK, NRST, NST)
begin
if NST = '0' then
r <= '1';
elsif NRST = '0' then
r <= '0';
elsif(falling_edge(CLK)) then
r <= D;
end if;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_TRIGER is
port
(
T, NRST, NST: in std_logic;
Q: out std_logic
);
end T_TRIGER;
architecture T_TRIGER0 of T_TRIGER is
component D_TRIGER
port
(
D, CLK, NRST, NST: in std_logic;
Q, NQ: out std_logic
);
end component;
signal wire0: std_logic;
begin
dt: D_TRIGER port map(CLK=>T, NRST=>NRST, NST=>NST, Q=>Q, NQ=>wire0, D=>wire0);
end;
|
mit
|
ac2dd1a1fbda8a1d3931bebf65792bf5
| 0.626045 | 2.454545 | false | false | false | false |
bmazin/SDR
|
Firmware/dac_mkid_files/dac_mkid_interface_v1_01_a/hdl/vhdl/dac_mkid_interface.vhd
| 1 | 10,505 |
----------------------------------------------------------------------------------
-- dac_mkid_interface : DAC board with two DAC5681 for I and Q signals
----------------------------------------------------------------------------------
-- Authors: Sean McHugh, Bruno Serfass, Ran Duan
-- Create Date: 09/02/09
-- modification:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity section
--------------------------------------------------------------------------------
entity dac_mkid_interface is
Generic (
OUTPUT_CLK : INTEGER := 0;
CTRL_CLK_PHASE : INTEGER := 0
);
Port (
--------------------------------------
-- differential signals from/to DAC
--------------------------------------
-- clock from DAC
dac_clk_p : in STD_LOGIC;
dac_clk_n : in STD_LOGIC;
-- clock to DAC
dac_smpl_clk_i_p : out STD_LOGIC;
dac_smpl_clk_i_n : out STD_LOGIC;
dac_smpl_clk_q_p : out STD_LOGIC;
dac_smpl_clk_q_n : out STD_LOGIC;
-- enable analog output for DAC
dac_sync_i_p : out STD_LOGIC;
dac_sync_i_n : out STD_LOGIC;
dac_sync_q_p : out STD_LOGIC;
dac_sync_q_n : out STD_LOGIC;
-- data written to DAC
dac_data_i_p : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_i_n : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_q_p : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_q_n : out STD_LOGIC_VECTOR (15 downto 0);
-- configuration ports of DAC
dac_not_sdenb_i : out STD_LOGIC;
dac_not_sdenb_q : out STD_LOGIC;
dac_sclk : out STD_LOGIC;
dac_sdi : out STD_LOGIC;
dac_not_reset : out STD_LOGIC;
-- dac_phase : in STD_LOGIC;
--------------------------------------
-- signals from/to design
--------------------------------------
-- defined in xps_dac_mkid.m
dac_smpl_clk : in STD_LOGIC;
-- defined in dac_mkid yellow block and dac_mkid_mask.m
dac_data_i0 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_i1 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_q0 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_q1 : in STD_LOGIC_VECTOR (15 downto 0);
dac_sync_i : in STD_LOGIC;
dac_sync_q : in STD_LOGIC;
-- serial ports
not_sdenb_i : in STD_LOGIC;
not_sdenb_q : in STD_LOGIC;
sclk : in STD_LOGIC;
sdi : in STD_LOGIC;
not_reset : in STD_LOGIC;
-- phase : out STD_LOGIC
-- clock to FPGA
dac_clk_out : out STD_LOGIC;
dac_clk90_out : out STD_LOGIC;
dac_clk180_out : out STD_LOGIC;
dac_clk270_out : out STD_LOGIC;
-- dcm lock
dac_dcm_locked : out STD_LOGIC
);
end dac_mkid_interface;
--------------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------------
architecture Structural of dac_mkid_interface is
signal data_i : STD_LOGIC_VECTOR (15 downto 0);
signal data_q : STD_LOGIC_VECTOR (15 downto 0);
signal smpl_clk : STD_LOGIC;
signal dac_clk_in : STD_LOGIC;
signal dac_clk : STD_LOGIC;
signal dcm_clk : STD_LOGIC;
signal dcm_clk90 : STD_LOGIC;
signal dcm_clk180 : STD_LOGIC;
signal dcm_clk270 : STD_LOGIC;
signal clk : STD_LOGIC;
signal clk90 : STD_LOGIC;
signal clk180 : STD_LOGIC;
signal clk270 : STD_LOGIC;
begin
-----------------------------------------------------------------------
-- Serial input (DAC configuration)
-----------------------------------------------------------------------
OBUF_inst_not_sdenb_i : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_sdenb_i,
I => not_sdenb_i
);
OBUF_inst_not_sdenb_q : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_sdenb_q,
I => not_sdenb_q
);
OBUF_inst_sclk : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_sclk,
I => sclk
);
OBUF_inst_sdi : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_sdi,
I => sdi
);
OBUF_inst_not_reset : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_reset,
I => not_reset
);
-------------------------------------------------------------------
-- Sample clock in to DAC. "dac_smpl_clk_i_p/n" is a DDR clock. --
-------------------------------------------------------------------
BUFG_inst : BUFG
port map (O => smpl_clk,I => dac_smpl_clk);
OBUFDS_inst_smpl_clk_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_smpl_clk_i_p,
OB => dac_smpl_clk_i_n,
I => smpl_clk
);
OBUFDS_inst_smpl_clk_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_smpl_clk_q_p,
OB => dac_smpl_clk_q_n,
I => smpl_clk
);
----------------------------------
-- Enable analog output for DAC --
----------------------------------
OBUFDS_inst_dac_sync_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_sync_i_p,
OB => dac_sync_i_n,
I => dac_sync_i
);
OBUFDS_inst_dac_sync_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_sync_q_p,
OB => dac_sync_q_n,
I => dac_sync_q
);
-----------------------------------------------------------------------
-- DAC data outputs
-- Requires an ODDR to double the data rate, and an
-- OBUFDS to convert to differential signal.
-----------------------------------------------------------------------
-- DAC output I --
ODDR_inst_generate_data_i : for j in 0 to 15 generate
ODDR_inst_data_i : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => data_i(j),
C => smpl_clk,
CE => '1',
D1 => dac_data_i0(j),
D2 => dac_data_i1(j),
R => '0',
S => '0'
);
end generate;
OBUFDS_inst_generate_data_i : for j in 0 to 15 generate
OBUFDS_inst_data1_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_data_i_p(j),
OB => dac_data_i_n(j),
I => data_i(j)
);
end generate;
-- DAC output Q --
ODDR_inst_generate_data_q : for j in 0 to 15 generate
ODDR_inst_data_q : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => data_q(j),
C => smpl_clk,
CE => '1',
D1 => dac_data_q0(j),
D2 => dac_data_q1(j),
R => '0',
S => '0'
);
end generate;
OBUFDS_inst_generate_data1_q : for j in 0 to 15 generate
OBUFDS_inst_data1_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_data_q_p(j),
OB => dac_data_q_n(j),
I => data_q(j)
);
end generate;
-----------------------------------------------------------------------
-- Clock Management
-----------------------------------------------------------------------
GEN_DCM : if OUTPUT_CLK = 1 generate
IBUFDS_inst_dac_clk : IBUFGDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_clk_in,
I => dac_clk_p,
IB => dac_clk_n
);
BUFG_clk_dac : BUFG
port map (I => dac_clk_in, O => dac_clk);
BUFG_clk : BUFG
port map (I => dcm_clk, O => clk);
BUFG_clk90 : BUFG
port map (I => dcm_clk90, O => clk90);
BUFG_clk180 : BUFG
port map (I => dcm_clk180, O => clk180);
BUFG_clk270 : BUFG
port map (I => dcm_clk270, O => clk270);
-- out clock to fpga
dac_clk_out <= clk;
dac_clk90_out <= clk90;
dac_clk180_out <= clk180;
dac_clk270_out <= clk270;
-- DCM
CLK_DCM : DCM
generic map(
CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.000000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 0.000000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "HIGH",
DLL_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLKFB => clk,
CLKIN => dac_clk,
DSSEN => '0',
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => '0',
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
CLK0 => dcm_clk,
CLK2X => open,
CLK2X180 => open,
CLK90 => dcm_clk90,
CLK180 => dcm_clk180,
CLK270 => dcm_clk270,
LOCKED => dac_dcm_locked,
PSDONE => open,
STATUS => open
);
end generate;
end Structural;
|
gpl-2.0
|
67b6dd0f666f233d6caffd2f7c857263
| 0.401333 | 3.682089 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/FontROM/FontROM_sim_netlist.vhdl
| 1 | 25,326 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Thu Apr 14 23:40:55 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/FontROM/FontROM_sim_netlist.vhdl
-- Design : FontROM
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FontROM_dist_mem_gen_v8_0_9 is
port (
a : in STD_LOGIC_VECTOR ( 13 downto 0 );
d : in STD_LOGIC_VECTOR ( 0 to 0 );
dpra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clk : in STD_LOGIC;
we : in STD_LOGIC;
i_ce : in STD_LOGIC;
qspo_ce : in STD_LOGIC;
qdpo_ce : in STD_LOGIC;
qdpo_clk : in STD_LOGIC;
qspo_rst : in STD_LOGIC;
qdpo_rst : in STD_LOGIC;
qspo_srst : in STD_LOGIC;
qdpo_srst : in STD_LOGIC;
spo : out STD_LOGIC_VECTOR ( 0 to 0 );
dpo : out STD_LOGIC_VECTOR ( 0 to 0 );
qspo : out STD_LOGIC_VECTOR ( 0 to 0 );
qdpo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_ADDR_WIDTH : integer;
attribute C_ADDR_WIDTH of FontROM_dist_mem_gen_v8_0_9 : entity is 14;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of FontROM_dist_mem_gen_v8_0_9 : entity is "0";
attribute C_DEPTH : integer;
attribute C_DEPTH of FontROM_dist_mem_gen_v8_0_9 : entity is 16384;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of FontROM_dist_mem_gen_v8_0_9 : entity is "./";
attribute C_FAMILY : string;
attribute C_FAMILY of FontROM_dist_mem_gen_v8_0_9 : entity is "artix7";
attribute C_HAS_CLK : integer;
attribute C_HAS_CLK of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_D : integer;
attribute C_HAS_D of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_DPO : integer;
attribute C_HAS_DPO of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_DPRA : integer;
attribute C_HAS_DPRA of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_I_CE : integer;
attribute C_HAS_I_CE of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO : integer;
attribute C_HAS_QDPO of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_CE : integer;
attribute C_HAS_QDPO_CE of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_CLK : integer;
attribute C_HAS_QDPO_CLK of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_RST : integer;
attribute C_HAS_QDPO_RST of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_SRST : integer;
attribute C_HAS_QDPO_SRST of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO : integer;
attribute C_HAS_QSPO of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_CE : integer;
attribute C_HAS_QSPO_CE of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_RST : integer;
attribute C_HAS_QSPO_RST of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_SRST : integer;
attribute C_HAS_QSPO_SRST of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_SPO : integer;
attribute C_HAS_SPO of FontROM_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_HAS_WE : integer;
attribute C_HAS_WE of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_MEM_INIT_FILE : string;
attribute C_MEM_INIT_FILE of FontROM_dist_mem_gen_v8_0_9 : entity is "FontROM.mif";
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_PARSER_TYPE : integer;
attribute C_PARSER_TYPE of FontROM_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_PIPELINE_STAGES : integer;
attribute C_PIPELINE_STAGES of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_QCE_JOINED : integer;
attribute C_QCE_JOINED of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_QUALIFY_WE : integer;
attribute C_QUALIFY_WE of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_READ_MIF : integer;
attribute C_READ_MIF of FontROM_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_REG_A_D_INPUTS : integer;
attribute C_REG_A_D_INPUTS of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_REG_DPRA_INPUT : integer;
attribute C_REG_DPRA_INPUT of FontROM_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_SYNC_ENABLE : integer;
attribute C_SYNC_ENABLE of FontROM_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_WIDTH : integer;
attribute C_WIDTH of FontROM_dist_mem_gen_v8_0_9 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FontROM_dist_mem_gen_v8_0_9 : entity is "dist_mem_gen_v8_0_9";
end FontROM_dist_mem_gen_v8_0_9;
architecture STRUCTURE of FontROM_dist_mem_gen_v8_0_9 is
signal \<const0>\ : STD_LOGIC;
signal \spo[0]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_42_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \spo[0]_INST_0_i_9_n_0\ : STD_LOGIC;
begin
dpo(0) <= \<const0>\;
qdpo(0) <= \<const0>\;
qspo(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\spo[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000005040004"
)
port map (
I0 => a(12),
I1 => \spo[0]_INST_0_i_1_n_0\,
I2 => a(11),
I3 => a(3),
I4 => \spo[0]_INST_0_i_2_n_0\,
I5 => a(13),
O => spo(0)
);
\spo[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \spo[0]_INST_0_i_3_n_0\,
I1 => \spo[0]_INST_0_i_4_n_0\,
I2 => a(10),
I3 => \spo[0]_INST_0_i_5_n_0\,
I4 => a(2),
I5 => \spo[0]_INST_0_i_6_n_0\,
O => \spo[0]_INST_0_i_1_n_0\
);
\spo[0]_INST_0_i_10\: unisim.vcomponents.MUXF8
port map (
I0 => \spo[0]_INST_0_i_25_n_0\,
I1 => \spo[0]_INST_0_i_26_n_0\,
O => \spo[0]_INST_0_i_10_n_0\,
S => a(6)
);
\spo[0]_INST_0_i_11\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_27_n_0\,
I1 => \spo[0]_INST_0_i_28_n_0\,
O => \spo[0]_INST_0_i_11_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_12\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_29_n_0\,
I1 => \spo[0]_INST_0_i_30_n_0\,
O => \spo[0]_INST_0_i_12_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_13\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_31_n_0\,
I1 => \spo[0]_INST_0_i_32_n_0\,
O => \spo[0]_INST_0_i_13_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_14\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_33_n_0\,
I1 => \spo[0]_INST_0_i_34_n_0\,
O => \spo[0]_INST_0_i_14_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_15\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_35_n_0\,
I1 => \spo[0]_INST_0_i_36_n_0\,
O => \spo[0]_INST_0_i_15_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_16\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_37_n_0\,
I1 => \spo[0]_INST_0_i_38_n_0\,
O => \spo[0]_INST_0_i_16_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_17\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_39_n_0\,
I1 => \spo[0]_INST_0_i_40_n_0\,
O => \spo[0]_INST_0_i_17_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_18\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_41_n_0\,
I1 => \spo[0]_INST_0_i_42_n_0\,
O => \spo[0]_INST_0_i_18_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200100000000000"
)
port map (
I0 => a(7),
I1 => a(1),
I2 => a(9),
I3 => a(0),
I4 => a(8),
I5 => a(4),
O => \spo[0]_INST_0_i_19_n_0\
);
\spo[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \spo[0]_INST_0_i_7_n_0\,
I1 => \spo[0]_INST_0_i_8_n_0\,
I2 => a(10),
I3 => \spo[0]_INST_0_i_9_n_0\,
I4 => a(2),
I5 => \spo[0]_INST_0_i_10_n_0\,
O => \spo[0]_INST_0_i_2_n_0\
);
\spo[0]_INST_0_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000900000000000"
)
port map (
I0 => a(4),
I1 => a(7),
I2 => a(9),
I3 => a(1),
I4 => a(0),
I5 => a(8),
O => \spo[0]_INST_0_i_20_n_0\
);
\spo[0]_INST_0_i_21\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_43_n_0\,
I1 => \spo[0]_INST_0_i_44_n_0\,
O => \spo[0]_INST_0_i_21_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_22\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_45_n_0\,
I1 => \spo[0]_INST_0_i_46_n_0\,
O => \spo[0]_INST_0_i_22_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => a(8),
I1 => a(0),
I2 => a(1),
I3 => a(9),
I4 => a(7),
I5 => a(4),
O => \spo[0]_INST_0_i_23_n_0\
);
\spo[0]_INST_0_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => a(7),
I1 => a(9),
O => \spo[0]_INST_0_i_24_n_0\
);
\spo[0]_INST_0_i_25\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_47_n_0\,
I1 => \spo[0]_INST_0_i_48_n_0\,
O => \spo[0]_INST_0_i_25_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_26\: unisim.vcomponents.MUXF7
port map (
I0 => \spo[0]_INST_0_i_49_n_0\,
I1 => \spo[0]_INST_0_i_50_n_0\,
O => \spo[0]_INST_0_i_26_n_0\,
S => a(5)
);
\spo[0]_INST_0_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"CBC00000444C7773"
)
port map (
I0 => a(7),
I1 => a(4),
I2 => a(1),
I3 => a(0),
I4 => a(8),
I5 => a(9),
O => \spo[0]_INST_0_i_27_n_0\
);
\spo[0]_INST_0_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"104120420000AA0A"
)
port map (
I0 => a(4),
I1 => a(0),
I2 => a(9),
I3 => a(1),
I4 => a(7),
I5 => a(8),
O => \spo[0]_INST_0_i_28_n_0\
);
\spo[0]_INST_0_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"22202266BAC0888C"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(0),
I3 => a(1),
I4 => a(9),
I5 => a(7),
O => \spo[0]_INST_0_i_29_n_0\
);
\spo[0]_INST_0_i_3\: unisim.vcomponents.MUXF8
port map (
I0 => \spo[0]_INST_0_i_11_n_0\,
I1 => \spo[0]_INST_0_i_12_n_0\,
O => \spo[0]_INST_0_i_3_n_0\,
S => a(6)
);
\spo[0]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AE3E1C3E2F3E003E"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(7),
I3 => a(9),
I4 => a(1),
I5 => a(0),
O => \spo[0]_INST_0_i_30_n_0\
);
\spo[0]_INST_0_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"00D9000010D40000"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(7),
I3 => a(9),
I4 => a(1),
I5 => a(0),
O => \spo[0]_INST_0_i_31_n_0\
);
\spo[0]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"101A000020150000"
)
port map (
I0 => a(4),
I1 => a(9),
I2 => a(8),
I3 => a(0),
I4 => a(1),
I5 => a(7),
O => \spo[0]_INST_0_i_32_n_0\
);
\spo[0]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"00780000003F0000"
)
port map (
I0 => a(4),
I1 => a(7),
I2 => a(8),
I3 => a(9),
I4 => a(1),
I5 => a(0),
O => \spo[0]_INST_0_i_33_n_0\
);
\spo[0]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"407C0000001D0000"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(7),
I3 => a(9),
I4 => a(1),
I5 => a(0),
O => \spo[0]_INST_0_i_34_n_0\
);
\spo[0]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"7300550000555DAA"
)
port map (
I0 => a(4),
I1 => a(1),
I2 => a(0),
I3 => a(8),
I4 => a(7),
I5 => a(9),
O => \spo[0]_INST_0_i_35_n_0\
);
\spo[0]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000200F1111111"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(1),
I3 => a(0),
I4 => a(7),
I5 => a(9),
O => \spo[0]_INST_0_i_36_n_0\
);
\spo[0]_INST_0_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C000404BB4CBA4"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(1),
I3 => a(9),
I4 => a(0),
I5 => a(7),
O => \spo[0]_INST_0_i_37_n_0\
);
\spo[0]_INST_0_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"020A008851404140"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(9),
I3 => a(1),
I4 => a(0),
I5 => a(7),
O => \spo[0]_INST_0_i_38_n_0\
);
\spo[0]_INST_0_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"C000400000555480"
)
port map (
I0 => a(4),
I1 => a(0),
I2 => a(1),
I3 => a(8),
I4 => a(7),
I5 => a(9),
O => \spo[0]_INST_0_i_39_n_0\
);
\spo[0]_INST_0_i_4\: unisim.vcomponents.MUXF8
port map (
I0 => \spo[0]_INST_0_i_13_n_0\,
I1 => \spo[0]_INST_0_i_14_n_0\,
O => \spo[0]_INST_0_i_4_n_0\,
S => a(6)
);
\spo[0]_INST_0_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C11001000100010"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(7),
I3 => a(9),
I4 => a(1),
I5 => a(0),
O => \spo[0]_INST_0_i_40_n_0\
);
\spo[0]_INST_0_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000098004800"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(0),
I3 => a(1),
I4 => a(9),
I5 => a(7),
O => \spo[0]_INST_0_i_41_n_0\
);
\spo[0]_INST_0_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A00000000000000"
)
port map (
I0 => a(8),
I1 => a(0),
I2 => a(7),
I3 => a(1),
I4 => a(9),
I5 => a(4),
O => \spo[0]_INST_0_i_42_n_0\
);
\spo[0]_INST_0_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"508A8A8A561B5B1B"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(7),
I3 => a(1),
I4 => a(0),
I5 => a(9),
O => \spo[0]_INST_0_i_43_n_0\
);
\spo[0]_INST_0_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"6465025A4A580212"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(7),
I3 => a(9),
I4 => a(1),
I5 => a(0),
O => \spo[0]_INST_0_i_44_n_0\
);
\spo[0]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000AAABAAA3CCC"
)
port map (
I0 => a(4),
I1 => a(9),
I2 => a(0),
I3 => a(1),
I4 => a(7),
I5 => a(8),
O => \spo[0]_INST_0_i_45_n_0\
);
\spo[0]_INST_0_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"0111A3AAA3A0A3EE"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(9),
I3 => a(7),
I4 => a(1),
I5 => a(0),
O => \spo[0]_INST_0_i_46_n_0\
);
\spo[0]_INST_0_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"150015000055552A"
)
port map (
I0 => a(4),
I1 => a(1),
I2 => a(0),
I3 => a(8),
I4 => a(7),
I5 => a(9),
O => \spo[0]_INST_0_i_47_n_0\
);
\spo[0]_INST_0_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"04060C0010313131"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(7),
I3 => a(1),
I4 => a(0),
I5 => a(9),
O => \spo[0]_INST_0_i_48_n_0\
);
\spo[0]_INST_0_i_49\: unisim.vcomponents.LUT6
generic map(
INIT => X"020402042810B002"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(9),
I3 => a(1),
I4 => a(0),
I5 => a(7),
O => \spo[0]_INST_0_i_49_n_0\
);
\spo[0]_INST_0_i_5\: unisim.vcomponents.MUXF8
port map (
I0 => \spo[0]_INST_0_i_15_n_0\,
I1 => \spo[0]_INST_0_i_16_n_0\,
O => \spo[0]_INST_0_i_5_n_0\,
S => a(6)
);
\spo[0]_INST_0_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"2005250514645404"
)
port map (
I0 => a(4),
I1 => a(8),
I2 => a(7),
I3 => a(1),
I4 => a(0),
I5 => a(9),
O => \spo[0]_INST_0_i_50_n_0\
);
\spo[0]_INST_0_i_6\: unisim.vcomponents.MUXF8
port map (
I0 => \spo[0]_INST_0_i_17_n_0\,
I1 => \spo[0]_INST_0_i_18_n_0\,
O => \spo[0]_INST_0_i_6_n_0\,
S => a(6)
);
\spo[0]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8830"
)
port map (
I0 => \spo[0]_INST_0_i_19_n_0\,
I1 => a(6),
I2 => \spo[0]_INST_0_i_20_n_0\,
I3 => a(5),
O => \spo[0]_INST_0_i_7_n_0\
);
\spo[0]_INST_0_i_8\: unisim.vcomponents.MUXF8
port map (
I0 => \spo[0]_INST_0_i_21_n_0\,
I1 => \spo[0]_INST_0_i_22_n_0\,
O => \spo[0]_INST_0_i_8_n_0\,
S => a(6)
);
\spo[0]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080808F8080"
)
port map (
I0 => \spo[0]_INST_0_i_23_n_0\,
I1 => a(5),
I2 => a(6),
I3 => a(8),
I4 => \spo[0]_INST_0_i_24_n_0\,
I5 => a(4),
O => \spo[0]_INST_0_i_9_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FontROM is
port (
a : in STD_LOGIC_VECTOR ( 13 downto 0 );
spo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of FontROM : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of FontROM : entity is "FontROM,dist_mem_gen_v8_0_9,{}";
attribute core_generation_info : string;
attribute core_generation_info of FontROM : entity is "FontROM,dist_mem_gen_v8_0_9,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=14,C_DEFAULT_DATA=0,C_DEPTH=16384,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=FontROM.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=1,C_PARSER_TYPE=1}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FontROM : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of FontROM : entity is "dist_mem_gen_v8_0_9,Vivado 2015.4";
end FontROM;
architecture STRUCTURE of FontROM is
signal NLW_U0_dpo_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_qdpo_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_qspo_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_D : integer;
attribute C_HAS_D of U0 : label is 0;
attribute C_HAS_DPO : integer;
attribute C_HAS_DPO of U0 : label is 0;
attribute C_HAS_DPRA : integer;
attribute C_HAS_DPRA of U0 : label is 0;
attribute C_HAS_I_CE : integer;
attribute C_HAS_I_CE of U0 : label is 0;
attribute C_HAS_QDPO : integer;
attribute C_HAS_QDPO of U0 : label is 0;
attribute C_HAS_QDPO_CE : integer;
attribute C_HAS_QDPO_CE of U0 : label is 0;
attribute C_HAS_QDPO_CLK : integer;
attribute C_HAS_QDPO_CLK of U0 : label is 0;
attribute C_HAS_QDPO_RST : integer;
attribute C_HAS_QDPO_RST of U0 : label is 0;
attribute C_HAS_QDPO_SRST : integer;
attribute C_HAS_QDPO_SRST of U0 : label is 0;
attribute C_HAS_WE : integer;
attribute C_HAS_WE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_PIPELINE_STAGES : integer;
attribute C_PIPELINE_STAGES of U0 : label is 0;
attribute C_QCE_JOINED : integer;
attribute C_QCE_JOINED of U0 : label is 0;
attribute C_QUALIFY_WE : integer;
attribute C_QUALIFY_WE of U0 : label is 0;
attribute C_REG_DPRA_INPUT : integer;
attribute C_REG_DPRA_INPUT of U0 : label is 0;
attribute c_addr_width : integer;
attribute c_addr_width of U0 : label is 14;
attribute c_default_data : string;
attribute c_default_data of U0 : label is "0";
attribute c_depth : integer;
attribute c_depth of U0 : label is 16384;
attribute c_elaboration_dir : string;
attribute c_elaboration_dir of U0 : label is "./";
attribute c_has_clk : integer;
attribute c_has_clk of U0 : label is 0;
attribute c_has_qspo : integer;
attribute c_has_qspo of U0 : label is 0;
attribute c_has_qspo_ce : integer;
attribute c_has_qspo_ce of U0 : label is 0;
attribute c_has_qspo_rst : integer;
attribute c_has_qspo_rst of U0 : label is 0;
attribute c_has_qspo_srst : integer;
attribute c_has_qspo_srst of U0 : label is 0;
attribute c_has_spo : integer;
attribute c_has_spo of U0 : label is 1;
attribute c_mem_init_file : string;
attribute c_mem_init_file of U0 : label is "FontROM.mif";
attribute c_parser_type : integer;
attribute c_parser_type of U0 : label is 1;
attribute c_read_mif : integer;
attribute c_read_mif of U0 : label is 1;
attribute c_reg_a_d_inputs : integer;
attribute c_reg_a_d_inputs of U0 : label is 0;
attribute c_sync_enable : integer;
attribute c_sync_enable of U0 : label is 1;
attribute c_width : integer;
attribute c_width of U0 : label is 1;
begin
U0: entity work.FontROM_dist_mem_gen_v8_0_9
port map (
a(13 downto 0) => a(13 downto 0),
clk => '0',
d(0) => '0',
dpo(0) => NLW_U0_dpo_UNCONNECTED(0),
dpra(13 downto 0) => B"00000000000000",
i_ce => '1',
qdpo(0) => NLW_U0_qdpo_UNCONNECTED(0),
qdpo_ce => '1',
qdpo_clk => '0',
qdpo_rst => '0',
qdpo_srst => '0',
qspo(0) => NLW_U0_qspo_UNCONNECTED(0),
qspo_ce => '1',
qspo_rst => '0',
qspo_srst => '0',
spo(0) => spo(0),
we => '0'
);
end STRUCTURE;
|
mit
|
8dc6b2127ae6a922d67ce77c6e2aafd6
| 0.539959 | 2.490021 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/RgbLedDisplay.vhd
| 1 | 9,145 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy, Sam Bobrowicz
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 11:26:53 03/13/2014
-- Design Name:
-- Module Name: RgbLedDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RgbLedDisplay is
generic(
X_RGB_COL_WIDTH : natural := 50; -- = SZ_RGB_WIDTH - width of one RGB column
Y_RGB_COL_HEIGHT : natural := 150; -- = SZ_RGB_HEIGHT - height of one RGB column
X_RGB_R_LOC : natural := 1050; -- = FRM_RGB_R_H_LOC - X Location of the RGB LED RED Column
X_RGB_G_LOC : natural := 1125; -- = FRM_RGB_G_H_LOC - X Location of the RGB LED GREEN Column
X_RGB_B_LOC : natural := 1200; -- = FRM_RGB_B_H_LOC - X Location of the RGB LED BLUE Column
Y_RGB_1_LOC : natural := 675; -- = FRM_RGB_1_V_LOC - Y Location of the RGB LED LD16 Column
Y_RGB_2_LOC : natural := 840 -- = FRM_RGB_1_V_LOC + SZ_RGB_HEIGHT + 15 - Y Location of the RGB LED LD17 Column
);
Port (
pxl_clk : in STD_LOGIC;
RGB_LED_RED : in STD_LOGIC_VECTOR (4 downto 0);
RGB_LED_GREEN : in STD_LOGIC_VECTOR (4 downto 0);
RGB_LED_BLUE : in STD_LOGIC_VECTOR (4 downto 0);
H_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
-- RGB LED RED signal Data for the three columns
RGB_LED_R_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_R_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_R_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0);
-- RGB LED GREEN signal Data for the three columns
RGB_LED_G_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_G_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_G_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0);
-- RGB LED BLUE signal Data for the three columns
RGB_LED_B_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_B_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_B_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0)
);
end RgbLedDisplay;
architecture Behavioral of RgbLedDisplay is
-- RGB columns starting pixels
constant FRM_RGB_1_V_LOC : natural := Y_RGB_1_LOC;
constant FRM_RGB_2_V_LOC : natural := Y_RGB_2_LOC;
constant FRM_RGB_R_H_LOC : natural := X_RGB_R_LOC;
constant FRM_RGB_G_H_LOC : natural := X_RGB_G_LOC;
constant FRM_RGB_B_H_LOC : natural := X_RGB_B_LOC;
-- LD16 R, G, B Columns Top and Bottom locations
constant RGB1_COL_TOP : natural := FRM_RGB_1_V_LOC - 1;
constant RGB1_COL_BOTTOM : natural := FRM_RGB_1_V_LOC + Y_RGB_COL_HEIGHT + 1;
-- LD17 R, G, B Columns Top and Bottom locations
constant RGB2_COL_TOP : natural := FRM_RGB_2_V_LOC - 1;
constant RGB2_COL_BOTTOM : natural := FRM_RGB_2_V_LOC + Y_RGB_COL_HEIGHT + 1;
-- Scale factor for the height of the columns
constant SCALE_FACTOR : natural := natural (round(real(Y_RGB_COL_HEIGHT/30)));
-- Each column will have one moving color: the red column will be either red or white,
-- the green column either green or white, the blue column either blue or white
signal rgb_r_red_col : std_logic_vector(3 downto 0); -- Red signal for the Red column
signal rgb_g_red_col : std_logic_vector(3 downto 0); -- Green signal for the Red column
signal rgb_b_red_col : std_logic_vector(3 downto 0); -- Blue signal for the Red column
-- G and B color signals are the same for the red column
signal rgb_gb_red_col : std_logic_vector(3 downto 0);
signal rgb_r_green_col : std_logic_vector(3 downto 0); -- Red signal for the Green column
signal rgb_g_green_col : std_logic_vector(3 downto 0); -- Green signal for the Green column
signal rgb_b_green_col : std_logic_vector(3 downto 0); -- Blue signal for the Green column
-- R and B color signals are the same for the green column
signal rgb_rb_green_col : std_logic_vector(3 downto 0);
signal rgb_r_blue_col : std_logic_vector(3 downto 0); -- Red signal for the Blue column
signal rgb_g_blue_col : std_logic_vector(3 downto 0); -- Green signal for the Blue column
signal rgb_b_blue_col : std_logic_vector(3 downto 0); -- Blue signal for the Blue column
-- R and G color signals are the same for the blue column
signal rgb_rg_blue_col : std_logic_vector(3 downto 0);
-- Size of the columns according to the incoming RGB LED data
signal rgb_r_col_size : natural range 0 to Y_RGB_COL_HEIGHT;
signal rgb_g_col_size : natural range 0 to Y_RGB_COL_HEIGHT;
signal rgb_b_col_size : natural range 0 to Y_RGB_COL_HEIGHT;
begin
-- Set the sizes of the columns
-- Red column
process (RGB_LED_RED)
begin
if (conv_integer(unsigned((RGB_LED_RED))) = 31) then
rgb_r_col_size <= Y_RGB_COL_HEIGHT;
else
rgb_r_col_size <= SCALE_FACTOR * conv_integer(unsigned(RGB_LED_RED));
end if;
end process;
-- Green column
process (RGB_LED_GREEN)
begin
if (conv_integer(unsigned((RGB_LED_GREEN))) = 31) then
rgb_g_col_size <= Y_RGB_COL_HEIGHT;
else
rgb_g_col_size <= SCALE_FACTOR * conv_integer(unsigned(RGB_LED_GREEN));
end if;
end process;
-- Blue column
process (RGB_LED_BLUE)
begin
if (conv_integer(unsigned((RGB_LED_BLUE))) = 31) then
rgb_b_col_size <= Y_RGB_COL_HEIGHT;
else
rgb_b_col_size <= SCALE_FACTOR * conv_integer(unsigned(RGB_LED_BLUE));
end if;
end process;
-- RGB LED RED COLUMN
rgb_r_red_col <= x"F"; -- The column color will be either red or white
rgb_gb_red_col <= x"0" when (H_COUNT_I > FRM_RGB_R_H_LOC and H_COUNT_I < FRM_RGB_R_H_LOC + X_RGB_COL_WIDTH)
and -- Set for both RGB LEDs
( -- LD16 columns
(V_COUNT_I > RGB1_COL_BOTTOM - rgb_r_col_size - 1 and V_COUNT_I < RGB1_COL_BOTTOM)
or -- LD17 columns
(V_COUNT_I > RGB2_COL_BOTTOM - rgb_r_col_size - 1 and V_COUNT_I < RGB2_COL_BOTTOM)
)
else x"F";
rgb_g_red_col <= rgb_gb_red_col;
rgb_b_red_col <= rgb_gb_red_col;
-- RGB LED GREEN COLUMN
rgb_rb_green_col <= x"0" when (H_COUNT_I > FRM_RGB_G_H_LOC and H_COUNT_I < FRM_RGB_G_H_LOC + X_RGB_COL_WIDTH)
and -- Set for both RGB LEDs
( -- LD16 columns
(V_COUNT_I > RGB1_COL_BOTTOM - rgb_g_col_size - 1 and V_COUNT_I < RGB1_COL_BOTTOM)
or -- LD17 columns
(V_COUNT_I > RGB2_COL_BOTTOM - rgb_g_col_size - 1 and V_COUNT_I < RGB2_COL_BOTTOM)
)
else x"F";
rgb_g_green_col <= x"F"; -- The column color will be either green or white
rgb_r_green_col <= rgb_rb_green_col;
rgb_b_green_col <= rgb_rb_green_col;
-- RGB LED BLUE COLUMN
rgb_rg_blue_col <= x"0" when (H_COUNT_I > FRM_RGB_B_H_LOC and H_COUNT_I < FRM_RGB_B_H_LOC + X_RGB_COL_WIDTH)
and -- Set for both RGB LEDs
( -- LD16 columns
(V_COUNT_I > RGB1_COL_BOTTOM - rgb_b_col_size - 1 and V_COUNT_I < RGB1_COL_BOTTOM)
or -- LD17 columns
(V_COUNT_I > RGB2_COL_BOTTOM - rgb_b_col_size - 1 and V_COUNT_I < RGB2_COL_BOTTOM)
)
else x"F";
rgb_b_blue_col <= x"F"; -- The column color will be either blue or white
rgb_r_blue_col <= rgb_rg_blue_col;
rgb_g_blue_col <= rgb_rg_blue_col;
-- Assign outputs
process (pxl_clk)
begin
if pxl_clk'EVENT and pxl_clk = '1' then
-- RGB LED RED signal data for the three columns
RGB_LED_R_RED_COL <= rgb_r_red_col;
RGB_LED_R_GREEN_COL <= rgb_r_green_col;
RGB_LED_R_BLUE_COL <= rgb_r_blue_col;
-- RGB LED GREEN signal data for the three columns
RGB_LED_G_RED_COL <= rgb_g_red_col;
RGB_LED_G_GREEN_COL <= rgb_g_green_col;
RGB_LED_G_BLUE_COL <= rgb_g_blue_col;
-- RGB LED BLUE signal data for the three columns
RGB_LED_B_RED_COL <= rgb_b_red_col;
RGB_LED_B_GREEN_COL <= rgb_b_green_col;
RGB_LED_B_BLUE_COL <= rgb_b_blue_col;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
a9fc0553edb10d2e29fcec71431f9cf2
| 0.583926 | 3.202031 | false | false | false | false |
makestuff/vhdl
|
memctrl/memctrl/memctrl.vhdl
| 1 | 4,000 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memctrl_pkg.all;
entity memctrl is
generic (
-- These real-hardware defaults are overridden by the testbench
INIT_COUNT : unsigned(12 downto 0) := "1" & x"2C0" -- 100uS @ 48MHz
);
port(
-- Client interface
mcRst_in : in std_logic;
mcClk_in : in std_logic;
mcOp_in : in MCOpType;
mcAddr_in : in std_logic_vector(21 downto 0);
mcData_in : in std_logic_vector(15 downto 0);
mcData_out : out std_logic_vector(15 downto 0);
mcBusy_out : out std_logic;
-- SDRAM interface
ramRAS_out : out std_logic;
ramCAS_out : out std_logic;
ramWE_out : out std_logic;
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic
);
end entity;
architecture behavioural of memctrl is
type StateType is (
STATE_RESET,
STATE_INIT,
STATE_READ0,
STATE_READ1,
STATE_READ2,
STATE_IDLE
);
signal cmd : std_logic_vector(2 downto 0);
constant CMD_NOP : std_logic_vector(2 downto 0) := "111";
constant CMD_ACT : std_logic_vector(2 downto 0) := "011";
constant CMD_RD : std_logic_vector(2 downto 0) := "101";
constant CMD_WR : std_logic_vector(2 downto 0) := "100";
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_LMR : std_logic_vector(2 downto 0) := "000";
signal state : StateType;
signal state_next : StateType;
signal initCount : unsigned(12 downto 0);
signal initCount_next : unsigned(12 downto 0);
signal colAddr : std_logic_vector(7 downto 0);
signal colAddr_next : std_logic_vector(7 downto 0);
begin
ramRAS_out <= cmd(2);
ramCAS_out <= cmd(1);
ramWE_out <= cmd(0);
-- Infer registers
process(mcRst_in, mcClk_in)
begin
if ( mcRst_in = '1' ) then
state <= STATE_RESET;
initCount <= INIT_COUNT;
colAddr <= (others => '0');
elsif ( mcClk_in'event and mcClk_in = '1' ) then
state <= state_next;
initCount <= initCount_next;
colAddr <= colAddr_next;
end if;
end process;
-- Next state logic
process(state, initCount, colAddr, mcOp_in, mcAddr_in)
begin
state_next <= state;
initCount_next <= initCount - 1;
colAddr_next <= colAddr;
mcBusy_out <= '1';
ramBank_out <= (others => 'Z');
ramAddr_out <= (others => 'Z');
cmd <= CMD_NOP;
case state is
when STATE_RESET =>
state_next <= STATE_INIT;
initCount_next <= INIT_COUNT;
when STATE_INIT =>
if ( initCount = "0" & x"000" ) then
state_next <= STATE_IDLE;
end if;
when STATE_IDLE =>
mcBusy_out <= '0';
if ( mcOp_in = MC_RD ) then
state_next <= STATE_READ0;
colAddr_next <= mcAddr_in(7 downto 0); -- Save the column address
cmd <= CMD_ACT;
ramBank_out <= mcAddr_in(21 downto 20);
ramAddr_out <= mcAddr_in(19 downto 8);
end if;
when STATE_READ0 =>
state_next <= STATE_READ1;
cmd <= CMD_RD;
ramAddr_out <= "0000" & colAddr;
when STATE_READ1 =>
cmd <= CMD_PRE;
state_next <= STATE_READ2;
when STATE_READ2 =>
state_next <= STATE_IDLE;
end case;
end process;
ramLDQM_out <= '1';
ramUDQM_out <= '1';
mcData_out <= ramData_io and mcData_in;
end architecture;
|
gpl-3.0
|
f8df9ca8448375b997725550cff77169
| 0.65225 | 3.003003 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S72_S144.vhd
| 1 | 6,709 |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S72_S144.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (72 and 128) --
-- made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S72_S144 is
port (ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end entity BRAM_S72_S144;
architecture BRAM_S72_S144_arch of BRAM_S72_S144 is
component BRAM_S36_S72
port (ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
signal doa1 : std_logic_vector (31 downto 0);
signal dob1 : std_logic_vector (63 downto 0);
signal doa2 : std_logic_vector (31 downto 0);
signal dob2 : std_logic_vector (63 downto 0);
signal dia1 : std_logic_vector (31 downto 0);
signal dib1 : std_logic_vector (63 downto 0);
signal dia2 : std_logic_vector (31 downto 0);
signal dib2 : std_logic_vector (63 downto 0);
signal dipa1: std_logic_vector (3 downto 0);
signal dipa2: std_logic_vector (3 downto 0);
signal dopa1: std_logic_vector (3 downto 0);
signal dopa2: std_logic_vector (3 downto 0);
signal dipb1: std_logic_vector (7 downto 0);
signal dipb2: std_logic_vector (7 downto 0);
signal dopb1: std_logic_vector (7 downto 0);
signal dopb2: std_logic_vector (7 downto 0);
begin
dia1(31 downto 0) <= DIA(31 downto 0);
dia2(31 downto 0) <= DIA(63 downto 32);
dipa1(3 downto 0) <= DIPA(3 downto 0);
dipa2(3 downto 0) <= DIPA(7 downto 4);
DOA(31 downto 0) <= doa1;
DOA(63 downto 32) <= doa2;
DOPA(3 downto 0) <= dopa1;
DOPA(7 downto 4) <= dopa2;
dib1(31 downto 0) <= DIB(31 downto 0);
dib2(31 downto 0) <= DIB(63 downto 32);
dib1(63 downto 32) <= DIB(95 downto 64);
dib2(63 downto 32) <= DIB(127 downto 96);
dipb1(3 downto 0) <= DIPB(3 downto 0);
dipb2(3 downto 0) <= DIPB(7 downto 4);
dipb1(7 downto 4) <= DIPB(11 downto 8);
dipb2(7 downto 4) <= DIPB(15 downto 12);
DOPB(3 downto 0) <= dopb1(3 downto 0);
DOPB(7 downto 4) <= dopb2(3 downto 0);
DOPB(11 downto 8) <= dopb1(7 downto 4);
DOPB(15 downto 12) <= dopb2(7 downto 4);
DOB(31 downto 0) <= dob1(31 downto 0);
DOB(63 downto 32) <= dob2(31 downto 0);
DOB(95 downto 64) <= dob1(63 downto 32);
DOB(127 downto 96) <= dob2(63 downto 32);
bram1: BRAM_S36_S72
port map (
ADDRA => addra(9 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: BRAM_S36_S72
port map (
ADDRA => addra(9 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S72_S144_arch;
|
gpl-3.0
|
025020ff97bf961baa2949a04c233ba8
| 0.444179 | 4.105875 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/standalone/standalone.vhd
| 4 | 4,083 |
-------------------------------------------------------------------------------
-- Filename: standalone.vhd
--
-- Description: Sample circuit for doing audio standalone
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity standalone is
port (
ClkIn : in std_logic;
Reset_n : in std_logic;
LED : out std_logic_vector(3 downto 0);
DEBUG : out std_logic_vector(4 downto 0);
-- CODEC signals
AC97Reset_n : out std_logic;
AC97Clk : in std_logic; -- master clock for design
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.ac97_if_pkg.all;
architecture imp of standalone is
signal new_sample : std_logic;
signal left_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal leds_i : std_logic_vector(3 downto 0);
signal clkin_cntr : unsigned(26 downto 0) := (others => '0');
signal ac97clk_cntr : unsigned(26 downto 0) := (others => '0');
signal debug_i : std_logic_vector(3 downto 0);
signal reset_i : std_logic;
signal ac97reset_n_i,sync_i,sdata_out_i : std_logic;
component ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
-- CODEC signals (synchronized to AC97Clk)
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component ac97_if;
begin
reset_i <= not Reset_n;
delay_PROCESS : process (ClkIn) is
begin
if ClkIn'event and ClkIn='1' and new_sample = '1' then
left_channel_1 <= left_channel_0;
right_channel_1 <= right_channel_0;
left_channel_2 <= left_channel_1;
right_channel_2 <= right_channel_1;
end if;
end process;
LED <= not debug_i;
ac97_if_I : ac97_if
port map (
ClkIn => ClkIn,
Reset => Reset_i,
PCM_Playback_Left => left_channel_2,
PCM_Playback_Right => right_channel_2,
PCM_Playback_Accept => new_sample,
PCM_Record_Left => left_channel_0,
PCM_Record_Right => right_channel_0,
PCM_Record_Valid => open,
Debug => debug_i,
AC97Reset_n => AC97Reset_n_i,
AC97Clk => AC97Clk,
Sync => sync_i,
SData_Out => SData_Out_i,
SData_In => SData_in
);
AC97Reset_n <= AC97Reset_n_i;
Sync <= sync_i;
SData_Out <= SData_Out_i;
DEBUG(0) <= AC97Clk;
DEBUG(1) <= AC97Reset_n_i;
DEBUG(2) <= Sync_i;
DEBUG(3) <= SData_Out_i;
DEBUG(4) <= SData_In;
end architecture imp;
|
gpl-3.0
|
55d9c71121f3be60a107c86553a7e763
| 0.551555 | 3.466044 | false | false | false | false |
denis4net/hw_design
|
2/altera-project/src/memcell.vhd
| 1 | 819 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity MEMCELL is
port (
A, B, NRCK, CLOAD, NCCLR: in std_logic;
O: out std_logic
);
end MEMCELL;
architecture MEMCELL0 of MEMCELL is
component D_TRIGER
port
(
D, CLK, NRST, NST: in std_logic;
Q, NQ: out std_logic
);
end component;
component T_TRIGER
port
(
T, NRST, NST: in std_logic;
Q: out std_logic
);
end component;
signal d_q, d_nq: std_logic;
signal t_NS, t_NR: std_logic;
signal const_0: std_logic := '0';
signal const_1: std_logic := '1';
begin
D: D_TRIGER port map(D=>A, CLK=>NRCK, Q=>d_q, NQ=>d_nq, NRST=>const_1, NST=>const_1);
t_NS <= not (d_q and CLOAD);
t_NR <= not ((d_nq and CLOAD) or not NCCLR);
T: T_TRIGER port map(T=>B, NST=>t_NS, NRST=>t_NR, Q=>O);
end;
|
mit
|
89421e0b1addbf5880248ff8980db695
| 0.639805 | 2.387755 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a.robert/pcores/osif_tb_v1_00_c/simhdl/vhdl/osif_tb.vhd
| 1 | 27,863 |
--##### NOTE:
--##### THIS IS A TEMPLATE. It will be processed by mkbfmsim.py
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- osif_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: osif_tb.vhd
-- Version: 1.00.c
-- Description: IP testbench
-- Date: Tue Aug 1 12:52:05 2006 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_osif_v2_01_a;
library burst_ram_v2_01_a;
library osif_new_v1_00_a;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library work;
use work.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity osif_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
C_FIFO_DWIDTH : integer := 32;
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex2p";
C_DCR_BASEADDR : std_logic_vector := "0000000000";
C_DCR_HIGHADDR : std_logic_vector := "0000000011";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_REGISTER_OSIF_PORTS : integer := 1; -- route OSIF ports through registers
C_DCR_ILA : integer := 0; -- 0: no debug ILA, 1: include debug chipscope ILA for DCR debugging
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 64;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB bus interface, do not add or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity osif_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of osif_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant INTERRUPT : integer := 31;
signal busy_local : std_logic;
signal task_interrupt : std_logic;
signal task_busy : std_logic;
signal task_blocking : std_logic;
signal task_clk : std_logic;
signal task_reset : std_logic;
signal task_os2task_vec : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal task_os2task_vec_i : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal task_task2os_vec : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal task_os2task : osif_os2task_t;
signal task_task2os : osif_task2os_t;
signal burstAddr : std_logic_vector(0 to 13);
signal burstWrData : std_logic_vector(0 to 63);
signal burstRdData : std_logic_vector(0 to 63);
signal burstWE : std_logic;
signal burstBE : std_logic_vector(0 to 7);
signal task2burst_Addr : std_logic_vector(0 to 11);
signal task2burst_Data : std_logic_vector(0 to 31);
signal burst2task_Data : std_logic_vector(0 to 31);
signal task2burst_WE : std_logic;
signal VDEC_YCrCb : std_logic_vector(9 downto 2);
signal VDEC_LLC : std_logic;
signal VDEC_Rst : std_logic;
signal VDEC_OE : std_logic;
signal VDEC_PwrDn : std_logic;
---------
-- FIFO control and data lines
---------
signal fifo_clk : std_logic;
signal fifo_reset : std_logic;
signal fifo_read_remove : std_logic;
signal fifo_read_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_read_ready : std_logic;
signal fifo_write_add : std_logic;
signal fifo_write_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_write_ready : std_logic;
-- for simulation
signal fifo_read_add : std_logic;
signal fifo_read_datain : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_read_empty : std_logic;
signal fifo_read_full : std_logic;
signal fifo_read_valid : std_logic;
signal fifo_write_remove : std_logic;
signal fifo_write_dataout : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_write_empty : std_logic;
signal fifo_write_full : std_logic;
signal fifo_write_valid : std_logic;
---------
-- DCR stimuli
---------
signal PLB_Clk : std_logic;
signal PLB_Rst : std_logic;
signal dcrAck : std_logic;
signal dcrDBus_in : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal dcrABus : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal dcrDBus_out : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal dcrRead : std_logic;
signal dcrWrite : std_logic;
signal dcrICON : std_logic_vector(35 downto 0); -- chipscope
constant C_GND_TASK_DATA : std_logic_vector(0 to 31) := (others => '0');
constant C_GND_TASK_ADDR : std_logic_vector(0 to 11) := (others => '0');
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity osif_new_v1_00_a.osif_new
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_BURST_AWIDTH => 14,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_FAMILY => C_FAMILY,
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_DCR_ILA => C_DCR_ILA,
C_MPLB_AWIDTH =>C_MPLB_AWIDTH,
C_MPLB_DWIDTH =>C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH =>C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P =>C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE =>C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS =>C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
interrupt => task_interrupt,
busy => task_busy,
blocking => task_blocking,
-- task interface
task_clk => task_clk,
task_reset => task_reset,
osif_os2task_vec => task_os2task_vec,
osif_task2os_vec => task_task2os_vec,
-- burst mem interface
burstAddr => burstAddr,
burstWrData => burstWrData,
burstRdData => burstRdData,
burstWE => burstWE,
burstBE => burstBE,
-- "real" FIFO access signals
fifo_clk => fifo_clk,
fifo_reset => fifo_reset,
fifo_read_en => fifo_read_remove,
fifo_read_data => fifo_read_data,
fifo_read_ready => fifo_read_ready,
fifo_write_en => fifo_write_add,
fifo_write_data => fifo_write_data,
fifo_write_ready => fifo_write_ready,
-- MAP USER PORTS ABOVE THIS LINE ------------------
o_dcrAck => dcrAck,
o_dcrDBus => dcrDBus_in,
i_dcrABus => dcrABus,
i_dcrDBus => dcrDBus_out,
i_dcrRead => dcrRead,
i_dcrWrite => dcrWrite,
i_dcrICON => dcrICON,
-- sys_clk => PLB_Clk,
-- sys_reset => PLB_Rst,
-- SPLB_Clk => SPLB_Clk,
-- SPLB_Rst => SPLB_Rst ,
-- PLB_ABus => PLB_ABus,
-- PLB_UABus => PLB_UABus,
-- PLB_PAValid => PLB_PAValid,
-- PLB_SAValid => PLB_SAValid,
-- PLB_rdPrim => PLB_rdPrim,
-- PLB_wrPrim => PLB_wrPrim,
-- PLB_masterID => PLB_masterID,
-- PLB_abort => PLB_abort,
-- PLB_busLock => PLB_busLock,
-- PLB_RNW => PLB_RNW,
-- PLB_BE => PLB_BE,
-- PLB_MSize => PLB_MSize,
-- PLB_size => PLB_size ,
-- PLB_type => PLB_type,
-- PLB_lockErr => PLB_lockErr,
-- PLB_wrDBus => PLB_wrDBus,
-- PLB_wrBurst => PLB_wrBurst,
-- PLB_rdBurst => PLB_rdBurst,
-- PLB_wrPendReq => PLB_wrPendReq,
-- PLB_rdPendReq => PLB_rdPendReq,
-- PLB_wrPendPri => PLB_wrPendPri,
-- PLB_rdPendPri => PLB_rdPendPri,
-- PLB_reqPri => PLB_reqPri,
-- PLB_TAttribute => PLB_TAttribute,
-- Sl_addrAck => Sl_addrAck,
-- Sl_SSize => Sl_SSize,
-- Sl_wait => Sl_wait,
-- Sl_rearbitrate => Sl_rearbitrate,
-- Sl_wrDAck => Sl_wrDAck,
-- Sl_wrComp => Sl_wrComp,
-- Sl_wrBTerm => Sl_wrBTerm,
-- Sl_rdDBus => Sl_rdDBus,
-- Sl_rdWdAddr => Sl_rdWdAddr,
-- Sl_rdDAck => Sl_rdDAck,
-- Sl_rdComp => Sl_rdComp,
-- Sl_rdBTerm => Sl_rdBTerm ,
-- Sl_MBusy => Sl_MBusy,
-- Sl_MWrErr => Sl_MWrErr,
-- Sl_MRdErr => Sl_MRdErr,
-- Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock ,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst =>M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
PLB_Clk <= MPLB_Clk;
PLB_Rst <= MPLB_Rst;
------------------------------------------
-- user task
------------------------------------------
dont_register_osif_ports : if C_REGISTER_OSIF_PORTS = 0 generate
task_os2task_vec_i <= task_os2task_vec;
task_task2os_vec <= to_std_logic_vector(task_task2os);
end generate;
register_osif_ports : if C_REGISTER_OSIF_PORTS /= 0 generate
register_osif_ports_proc: process(task_clk)
begin
if rising_edge(task_clk) then
task_os2task_vec_i <= task_os2task_vec;
task_task2os_vec <= to_std_logic_vector(task_task2os);
end if;
end process;
end generate;
task_os2task <= to_osif_os2task_t(task_os2task_vec_i or (X"0000000000" & busy_local & "000000"));
-- task_inst: User task instatiation
task_0_inst: entity work.test_mutex
generic map (
C_BURST_AWIDTH => 12,
C_BURST_DWIDTH => 32
)
port map (
clk => task_clk,
reset => task_reset,
i_osif => task_os2task,
o_osif => task_task2os,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE
);
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
-- wait until (PLB_Rst'EVENT and PLB_Rst = '0');
-- assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
-- wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
-- wait until (PLB_Clk'EVENT and PLB_Clk = '1');
-- SYNCH_OUT(START) <= '1';
-- assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
-- wait until (PLB_Clk'EVENT and PLB_Clk = '1');
-- SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
-- wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
-- assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
-- wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
dcr_sim : process is
procedure OSIF_WRITE( where : in std_logic_vector(0 to 1);
what : in std_logic_vector(0 to C_DCR_DWIDTH-1) ) is
begin
dcrABus(C_DCR_AWIDTH-2 to C_DCR_AWIDTH-1) <= where;
dcrDBus_out <= what;
wait until rising_edge(PLB_Clk);
dcrWrite <= '1';
wait until rising_edge(PLB_Clk) and dcrAck = '1';
dcrWrite <= '0';
end procedure;
procedure OSIF_READ( where : in std_logic_vector(0 to 1);
variable what : out std_logic_vector(0 to C_DCR_DWIDTH-1) ) is
begin
dcrABus(C_DCR_AWIDTH-2 to C_DCR_AWIDTH-1) <= where;
wait until rising_edge(PLB_Clk);
dcrRead <= '1';
wait until rising_edge(PLB_Clk) and dcrAck = '1';
what := dcrDBus_in;
dcrRead <= '0';
end procedure;
constant OSIF_REG_COMMAND : std_logic_vector(0 to 1) := "00";
constant OSIF_REG_DATA : std_logic_vector(0 to 1) := "01";
constant OSIF_REG_DONE : std_logic_vector(0 to 1) := "10";
constant OSIF_REG_DATAX : std_logic_vector(0 to 1) := "10";
constant OSIF_CMDNEW : std_logic_vector(0 to C_DCR_DWIDTH-1) := X"FFFFFFFF";
variable dummy : std_logic_vector(0 to C_DCR_DWIDTH-1);
begin
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (PLB_Rst'EVENT and PLB_Rst = '0');
dcrABus <= C_DCR_BASEADDR;
dcrDBus_out <= (others => '0');
dcrICON <= (others => '0');
dcrRead <= '0';
dcrWrite <= '0';
-- sst-generated code starts here
-- %%%SST_TESTBENCH_START%%%
wait for 1000 ns;
-- write init data 00000005
OSIF_WRITE(OSIF_REG_COMMAND, OSIF_CMD_SET_INIT_DATA & X"000000");
OSIF_WRITE(OSIF_REG_DATA, X"00000005");
OSIF_WRITE(OSIF_REG_DONE, OSIF_CMDNEW);
wait for 100 ns;
-- write unlock
OSIF_WRITE(OSIF_REG_COMMAND, OSIF_CMD_UNBLOCK & X"000000");
OSIF_WRITE(OSIF_REG_DATA, X"00000000");
OSIF_WRITE(OSIF_REG_DONE, OSIF_CMDNEW);
wait for 100 ns;
-- read semaphore 00000000 wait
-- OSIF_READ(OSIF_REG_COMMAND, dummy);
-- assert dummy(0 to C_OSIF_CMD_WIDTH-1) = OSIF_CMD_SEM_WAIT report "*** ERROR: DCR command read mismatch! Expected OSIF_CMD_SEM_WAIT (SST line 9)." severity WARNING;
-- OSIF_READ(OSIF_REG_DATA, dummy);
-- assert dummy = X"00000000" report "*** ERROR: DCR data read mismatch (SST line 9)! ***" severity WARNING;
-- OSIF_READ(OSIF_REG_DATAX, dummy);
-- wait for 500 ns;
-- write unlock
-- OSIF_WRITE(OSIF_REG_COMMAND, OSIF_CMD_UNBLOCK & X"000000");
-- OSIF_WRITE(OSIF_REG_DATA, X"00000000");
-- OSIF_WRITE(OSIF_REG_DONE, OSIF_CMDNEW);
-- wait for 1000 ns;
-- read semaphore 00000001 post
-- OSIF_READ(OSIF_REG_COMMAND, dummy);
-- assert dummy(0 to C_OSIF_CMD_WIDTH-1) = OSIF_CMD_SEM_POST report "*** ERROR: DCR command read mismatch! Expected OSIF_CMD_SEM_POST (SST line 15)." severity WARNING;
-- OSIF_READ(OSIF_REG_DATA, dummy);
-- assert dummy = X"00000001" report "*** ERROR: DCR data read mismatch (SST line 15)! ***" severity WARNING;
-- OSIF_READ(OSIF_REG_DATAX, dummy);
-- wait for 1000 ns;
-- read semaphore 00000000 wait
-- OSIF_READ(OSIF_REG_COMMAND, dummy);
-- assert dummy(0 to C_OSIF_CMD_WIDTH-1) = OSIF_CMD_SEM_WAIT report "*** ERROR: DCR command read mismatch! Expected OSIF_CMD_SEM_WAIT (SST line 19)." severity WARNING;
-- OSIF_READ(OSIF_REG_DATA, dummy);
-- assert dummy = X"00000000" report "*** ERROR: DCR data read mismatch (SST line 19)! ***" severity WARNING;
-- OSIF_READ(OSIF_REG_DATAX, dummy);
-- wait for 500 ns;
-- write unlock
-- OSIF_WRITE(OSIF_REG_COMMAND, OSIF_CMD_UNBLOCK & X"000000");
-- OSIF_WRITE(OSIF_REG_DATA, X"00000000");
-- OSIF_WRITE(OSIF_REG_DONE, OSIF_CMDNEW);
-- wait for 1000 ns;
-- read semaphore 00000001 post
-- OSIF_READ(OSIF_REG_COMMAND, dummy);
-- assert dummy(0 to C_OSIF_CMD_WIDTH-1) = OSIF_CMD_SEM_POST report "*** ERROR: DCR command read mismatch! Expected OSIF_CMD_SEM_POST (SST line 25)." severity WARNING;
-- OSIF_READ(OSIF_REG_DATA, dummy);
-- assert dummy = X"00000001" report "*** ERROR: DCR data read mismatch (SST line 25)! ***" severity WARNING;
-- OSIF_READ(OSIF_REG_DATAX, dummy);
-- wait for 1000 ns;
-- %%%SST_TESTBENCH_END%%%
-- end of sst-generated code
wait for 1 us;
wait;
end process;
-- simulate RAM
burst_ram_i : entity burst_ram_v2_01_a.burst_ram
generic map (
G_PORTA_AWIDTH => 12,
G_PORTA_DWIDTH => 32,
G_PORTA_PORTS => 1,
G_PORTB_AWIDTH => 11,
G_PORTB_DWIDTH => 64,
G_PORTB_USE_BE => 1
)
port map (
addra => task2burst_Addr,
addrax => C_GND_TASK_ADDR,
addrb => burstAddr(0 to 10), -- RAM is addressing 64Bit values
clka => task_clk,
clkax => '0',
clkb => task_clk,
dina => task2burst_Data,
dinax => C_GND_TASK_DATA,
dinb => burstWrData,
douta => burst2task_Data,
doutax => open,
doutb => burstRdData,
wea => task2burst_WE,
weax => '0',
web => burstWE,
ena => '1',
enax => '0',
enb => '1',
beb => burstBE
);
-- simulate FIFOs
fifo_left : entity work.fifo
port map (
clk => fifo_clk,
din => fifo_read_datain,
rd_en => fifo_read_remove,
rst => fifo_reset,
wr_en => fifo_read_add,
dout => fifo_read_data,
empty => fifo_read_empty,
full => fifo_read_full,
valid => fifo_read_valid);
fifo_read_ready <= (not fifo_read_empty) or fifo_read_valid ;
fifo_right : entity work.fifo
port map (
clk => fifo_clk,
din => fifo_write_data,
rd_en => fifo_write_remove,
rst => fifo_reset,
wr_en => fifo_write_add,
dout => fifo_write_dataout,
empty => fifo_write_empty,
full => fifo_write_full,
valid => fifo_write_valid);
fifo_write_ready <= not(fifo_write_full);
fifo_fill : process(fifo_clk, fifo_reset)
variable counter : std_logic_vector(0 to C_FIFO_DWIDTH-1);
begin
if fifo_reset = '1' then
counter := (others => '0');
fifo_read_add <= '0';
fifo_read_datain <= (others => '0');
elsif rising_edge(fifo_clk) then
fifo_read_add <= '0';
-- only write on every second clock
if fifo_read_full = '0' and fifo_read_add = '0' and counter < 16 then
fifo_read_datain <= counter;
counter := counter + 1;
fifo_read_add <= '1';
end if;
end if;
end process;
-- infer latch for local busy signal
-- needed for asynchronous communication between thread and OSIF
busy_local_gen : process(task_reset, task_task2os.request, task_os2task.ack)
begin
if task_reset = '1' then
busy_local <= '0';
elsif task_task2os.request = '1' then
busy_local <= '1';
elsif task_os2task.ack = '1' then
busy_local <= '0';
end if;
end process;
end architecture testbench;
|
gpl-3.0
|
3a08ba263b61f47b97b2d31524cad4c2
| 0.496788 | 3.881722 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/rom/synth/rom.vhd
| 1 | 13,993 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_arch OF rom IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF rom_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF rom_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF rom_arch : ARCHITECTURE IS "rom,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF rom_arch: ARCHITECTURE IS "rom,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=rom.mif,C_INIT_FILE=rom.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=30720,C_READ_DEPTH_A=30720,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=30720,C_READ_DEPTH_B=30720,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.252613 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "rom.mif",
C_INIT_FILE => "rom.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 30720,
C_READ_DEPTH_A => 30720,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 30720,
C_READ_DEPTH_B => 30720,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.252613 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END rom_arch;
|
mit
|
7e2012a1d486181933b24e741692fbb3
| 0.622883 | 3.012487 | false | false | false | false |
twlostow/dsi-shield
|
hdl/top/rev2/rev2_top.vhd
| 1 | 39,796 |
--
-- DSI Shield
-- Copyright (C) 2013-2014 twl <[email protected]>
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 3 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- rev2_top.vhd - top level for rev 2.2. PCB FPGA
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
library unisim;
use unisim.vcomponents.all;
-- Table 1: PLL Settings for the supported displays.
-- Display Type Refresh Mul Sys_Div Phy_Div PHY_Freq Clock period
-- Droid DNA 48 Hz 26 7 1 650 MHz 1538 ps
-- Optimus P880 60 Hz 30 8 2 375 MHz 2666 ps
-- Iphone 4 60 Hz 31 8 2 387.5 MHz 2580 ps
entity rev2_top is
generic (
g_with_hdmi : boolean := true;
-- DDR clock-to-data delay
g_data_delay : integer := 0; --70;
-- DDR data-to-DQs delay
g_dqs_delay : integer := 40; --140; --75 - 45;
g_clock_delay : integer := 40; --70;
g_addr_delay : integer := 0; --70;
-- PLL configuration:
-- Fsys = 25 MHz * g_pll_mul / g_pll_sys_div
-- Fphy = 25 MHz * g_pll_mul / g_pll_phy_div
-- PLL multiplier
g_pll_mul : integer := 31;
-- System clock PLL divider
g_pll_sys_div : integer := 8;
-- DSI PHY clock PLL divider
g_pll_phy_div : integer := 2;
-- DSI PHY clock period, in picoseconds
g_clock_period_ps : integer := 1538;
g_simulation : boolean := false
);
port (
clk_25m_i : in std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- HDMI
-------------------------------------------------------------------------------
hdmi_rx_p_i : in std_logic_vector(3 downto 0);
hdmi_rx_n_i : in std_logic_vector(3 downto 0);
hdmi_scl_b : inout std_logic;
hdmi_sda_b : inout std_logic;
hdmi_hpd_o : out std_logic;
hdmi_p5v_notif_i : in std_logic;
-------------------------------------------------------------------------------
-- SDRAM
-------------------------------------------------------------------------------
sdram_clk_p : out std_logic;
sdram_clk_n : out std_logic;
sdram_cke : out std_logic;
sdram_cs_n : out std_logic;
sdram_we_n : out std_logic;
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_adr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_dm : out std_logic_vector(1 downto 0);
sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dqs : inout std_logic_vector(1 downto 0);
-------------------------------------------------------------------------------
-- DSI ports
-------------------------------------------------------------------------------
dsi_clk_p_o : out std_logic;
dsi_clk_n_o : out std_logic;
dsi_clk_lp_p_o : out std_logic;
dsi_clk_lp_n_o : out std_logic;
dsi_hs_p_o : out std_logic_vector(3 downto 0);
dsi_hs_n_o : out std_logic_vector(3 downto 0);
dsi_lp_p_o : out std_logic_vector(3 downto 0);
dsi_lp_n_o : out std_logic_vector(3 downto 0);
dsi_resetb_o : out std_logic;
dsi_gpio0_o : out std_logic;
dsi_gpio1_o : out std_logic;
lcd_pwren_o : out std_logic;
bl_dim_o : out std_logic;
vid_resetn_o : out std_logic;
-- SPI Flash interface (bit-banged)
spi_cs_n_rst_b : inout std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
spi_sck_o : out std_logic;
dbg_o : out std_logic_vector(3 downto 0)
);
end rev2_top;
architecture rtl of rev2_top is
constant c_fml_depth : integer := 25;
component dsi_core is
generic(
g_pixels_per_clock : integer := 2;
g_lanes : integer := 4;
g_fifo_size : integer := 4096;
g_invert_lanes : integer := 5; -- lanes 0 and 2 inverted IP4
g_invert_clock : integer := 0;
--g_invert_lanes : integer := 5; -- lanes 0 and 2 inverted E980
--g_invert_clock : integer := 1; -- clock inverted
g_clock_period_ps : integer := 2000
);
port(
clk_sys_i : in std_logic;
clk_dsi_i : in std_logic;
clk_phy_i : in std_logic;
clk_dsi_shifted_i : in std_logic;
clk_phy_shifted_i : in std_logic;
rst_n_i : in std_logic;
pll_locked_i : in std_logic;
pix_almost_full_o : out std_logic;
pix_i : in std_logic_vector (24 * g_pixels_per_clock-1 downto 0) := (others => '0');
pix_wr_i : in std_logic;
pix_vsync_i : in std_logic;
pix_next_frame_o : out std_logic;
dsi_clk_p_o : out std_logic;
dsi_clk_n_o : out std_logic;
dsi_clk_lp_p_o : out std_logic;
dsi_clk_lp_n_o : out std_logic;
dsi_clk_lp_oe_o : out std_logic;
dsi_hs_p_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_hs_n_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_p_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_n_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_oe_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_reset_n_o : out std_logic;
dsi_gpio_o : out std_logic_vector(2 downto 0);
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic
);
end component;
component fml_wb_bridge
generic (
sdram_depth : integer := 26);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
fml_adr : out std_logic_vector(sdram_depth-1 downto 0);
fml_stb : out std_logic;
fml_we : out std_logic;
fml_ack : in std_logic;
fml_sel : out std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
fml_do : out std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic
);
end component;
component fmlarb
generic(
fml_depth : integer;
fml_width : integer);
port (
sys_clk : in std_logic;
sys_rst : in std_logic;
-- Interface 0 has higher priority than the others
m0_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m0_stb : in std_logic := '0';
m0_we : in std_logic := '0';
m0_ack : out std_logic;
m0_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m0_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m0_do : out std_logic_vector(fml_width-1 downto 0);
m1_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m1_stb : in std_logic := '0';
m1_we : in std_logic := '0';
m1_ack : out std_logic;
m1_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m1_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m1_do : out std_logic_vector(fml_width-1 downto 0);
m2_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m2_stb : in std_logic := '0';
m2_we : in std_logic := '0';
m2_ack : out std_logic;
m2_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m2_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m2_do : out std_logic_vector(fml_width-1 downto 0);
m3_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m3_stb : in std_logic := '0';
m3_we : in std_logic := '0';
m3_ack : out std_logic;
m3_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m3_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m3_do : out std_logic_vector(fml_width-1 downto 0);
m4_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m4_stb : in std_logic := '0';
m4_we : in std_logic := '0';
m4_ack : out std_logic;
m4_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m4_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m4_do : out std_logic_vector(fml_width-1 downto 0);
m5_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m5_stb : in std_logic := '0';
m5_we : in std_logic := '0';
m5_ack : out std_logic;
m5_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m5_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m5_do : out std_logic_vector(fml_width-1 downto 0);
s_adr : out std_logic_vector(fml_depth-1 downto 0);
s_stb : out std_logic;
s_we : out std_logic;
s_eack : in std_logic;
s_sel : out std_logic_vector(fml_width/8-1 downto 0);
s_di : in std_logic_vector(fml_width-1 downto 0);
s_do : out std_logic_vector(fml_width-1 downto 0)
);
end component;
component hpdmc
generic (
csr_addr : integer := 0;
sdram_depth : integer := 25;
sdram_columndepth : integer := 10;
data_delay : integer := 0;
dqs_delay : integer := 0;
clock_delay : integer := 0;
addr_delay : integer := 0
);
port (
sys_clk : in std_logic;
sys_clk_n : in std_logic;
sys_rst : in std_logic;
csr_a : in std_logic_vector(13 downto 0);
csr_we : in std_logic;
csr_di : in std_logic_vector(31 downto 0);
csr_do : out std_logic_vector(31 downto 0);
fml_adr : in std_logic_vector(sdram_depth-1 downto 0);
fml_stb : in std_logic;
fml_we : in std_logic;
fml_eack : out std_logic;
fml_sel : in std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
fml_do : out std_logic_vector(31 downto 0);
sdram_clk_p : out std_logic;
sdram_clk_n : out std_logic;
sdram_cke : out std_logic;
sdram_cs_n : out std_logic;
sdram_we_n : out std_logic;
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_adr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_dm : out std_logic_vector(1 downto 0);
sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dqs : inout std_logic_vector(1 downto 0)
);
end component;
component reset_gen is
port (
clk_sys_i : in std_logic;
spi_cs_n_rst_i : in std_logic;
mask_reset_i : in std_logic;
rst_sys_n_o : out std_logic);
end component reset_gen;
component pll_drp_sequencer
port (
clk_sys_i : in std_logic;
clk_reconf_i : in std_logic;
r_pll_ctl0_i : in std_logic_vector(31 downto 0);
r_pll_ctl1_i : in std_logic_vector(31 downto 0);
r_pll_status_o : out std_logic_vector(31 downto 0);
pll_locked_i : in std_logic;
pll_rst_o : out std_logic;
pll_di_o : out std_logic_vector(15 downto 0);
pll_do_i : in std_logic_vector(15 downto 0);
pll_drdy_i : in std_logic;
pll_daddr_o : out std_logic_vector(4 downto 0);
pll_den_o : out std_logic;
pll_dwe_o : out std_logic;
busy_o : out std_logic
);
end component;
component fml_framebuffer
generic (
g_fml_depth : integer
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pix_almost_full_i : in std_logic;
pix_wr_o : out std_logic;
pix_o : out std_logic_vector(47 downto 0);
pix_vsync_o : out std_logic;
pix_next_frame_i : in std_logic;
fml_adr : out std_logic_vector(g_fml_depth-1 downto 0);
fml_stb : out std_logic;
fml_we : out std_logic;
fml_ack : in std_logic;
fml_sel : out std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
r_fb_enable_i : in std_logic;
r_fb_pix32_i : in std_logic;
r_fb_addr_i : in std_logic_vector(g_fml_depth-1 downto 0);
r_fb_size_i : in std_logic_vector(g_fml_depth-1 downto 0)
);
end component;
component sysctl_regs
generic (
g_fml_depth : integer;
g_default_pll_mul : integer;
g_default_pll_sys_div : integer
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic;
r_fb_enable_o : out std_logic;
r_fb_pix32_o : out std_logic;
r_fb_addr_o : out std_logic_vector(g_fml_depth-1 downto 0);
r_fb_size_o : out std_logic_vector(g_fml_depth-1 downto 0);
r_mixer_ctl_i : in std_logic_vector(7 downto 0);
r_mixer_ctl_o : out std_logic_vector(7 downto 0);
r_edid_addr_o : out std_logic_vector(7 downto 0);
r_edid_data_o : out std_logic_vector(7 downto 0);
r_edid_wr_o : out std_logic;
r_pwm_ctl_o : out std_logic_vector(7 downto 0);
r_pll_ctl0_o : out std_logic_vector(31 downto 0);
r_pll_ctl1_o : out std_logic_vector(31 downto 0);
r_pll_status_i : in std_logic_vector(31 downto 0);
r_gpio_o : out std_logic_vector(31 downto 0);
r_gpio_i : in std_logic_vector(31 downto 0)
);
end component;
component dvi_decoder
port (
tmdsclk_p : in std_logic;
tmdsclk_n : in std_logic;
blue_p : in std_logic;
blue_n : in std_logic;
green_p : in std_logic;
green_n : in std_logic;
red_p : in std_logic;
red_n : in std_logic;
exrst : in std_logic;
pclk : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
de : out std_logic;
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0);
green_vld : out std_logic;
pixel : out std_logic_vector(47 downto 0);
pixel_valid : out std_logic;
link_up : out std_logic
);
end component;
component edid_eeprom is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
scl_b : inout std_logic;
sda_b : inout std_logic;
edid_en_i : in std_logic;
scl_master_i : in std_logic;
sda_master_i : in std_logic;
sda_master_o : out std_logic;
hdmi_p5v_notif_i : in std_logic;
hdmi_hpd_en_o : out std_logic;
addr_i : in std_logic_vector(7 downto 0);
data_i : in std_logic_vector(7 downto 0);
wr_i : in std_logic);
end component;
component video_mixer is
port(
clk_sys_i : in std_logic;
clk_dvi_i : in std_logic;
rst_n_i : in std_logic;
fb_almost_full_o : out std_logic;
fb_wr_i : in std_logic;
fb_pixel_i : in std_logic_vector(47 downto 0);
fb_vsync_i : in std_logic;
fb_next_frame_o : out std_logic;
dvi_de_i : in std_logic;
dvi_hsync_i : in std_logic;
dvi_vsync_i : in std_logic;
dvi_pixel_i : in std_logic_vector(47 downto 0);
dvi_valid_i : in std_logic;
dvi_link_up_i : in std_logic;
dsif_almost_full_i : in std_logic;
dsif_wr_o : out std_logic;
dsif_pix_o : out std_logic_vector(47 downto 0);
dsif_vsync_o : out std_logic;
dsif_next_frame_i : in std_logic;
mixer_ctl_i : in std_logic_vector(7 downto 0);
mixer_ctl_o : out std_logic_vector(7 downto 0)
);
end component;
constant c_cnx_slave_ports : integer := 1;
constant c_cnx_master_ports : integer := 6;
constant c_master_cpu_i : integer := 0;
constant c_slave_dpram : integer := 0;
constant c_slave_uart : integer := 1;
constant c_slave_dsi : integer := 2;
constant c_slave_ddram_csr : integer := 3;
constant c_slave_csr : integer := 4;
constant c_slave_ddram_mem : integer := 5;
signal cnx_slave_in : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(0 => x"00000000", -- 64KB of fpga memory
1 => x"c0010000",
2 => x"c0020000",
3 => x"c0030000",
4 => x"c0040000",
5 => x"80000000"); -- DDR
constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(0 => x"ffff0000",
1 => x"ffff0000",
2 => x"ffff0000",
3 => x"ffff0000",
4 => x"ffff0000",
5 => x"c0000000");
signal cpu_iwb_out : t_wishbone_master_out;
signal cpu_iwb_in : t_wishbone_master_in;
signal rst_n_sys, rst_sys, rst_n_dsi, clk_phy, clk_sys, clk_dsi, clk_sys_n, pll_locked_n, dsi_wr : std_logic;
signal dsi_lp_p_int, dsi_lp_n_int, dsi_lp_oe : std_logic_vector(3 downto 0);
signal dsi_clk_lp_p, dsi_clk_lp_n, dsi_clk_lp_oe : std_logic;
attribute keep : string;
attribute keep of clk_phy : signal is "true";
attribute keep of clk_sys : signal is "true";
attribute keep of clk_sys_n : signal is "true";
attribute keep of clk_dsi : signal is "true";
signal csr_we : std_logic;
signal dsi_wr_sync : std_logic_vector(7 downto 0);
signal pll_clk_in, pll_clk_fb, pll_clk_dsi : std_logic;
signal pll_clk_sys, pll_clk_sys_n : std_logic;
signal dsif_almost_full : std_logic;
signal dsif_wr : std_logic;
signal dsif_pix : std_logic_vector(47 downto 0);
signal dsif_vsync : std_logic;
signal dsif_next_frame : std_logic;
signal fb_almost_full : std_logic;
signal fb_wr : std_logic;
signal fb_pix : std_logic_vector(47 downto 0);
signal fb_vsync : std_logic;
signal fb_next_frame : std_logic;
type t_fml_link is record
adr : std_logic_vector(24 downto 0);
stb, we, ack, eack : std_logic;
d_m2s : std_logic_vector(31 downto 0);
d_s2m : std_logic_vector(31 downto 0);
sel : std_logic_vector(3 downto 0);
end record;
signal ddrc, fwb, frameb : t_fml_link;
signal hdmi_link_up, hdmi_pclk, hdmi_vsync, hdmi_hsync, hdmi_de, hdmi_valid : std_logic;
signal hdmi_pixel : std_logic_vector(47 downto 0);
signal r_mixer_ctl_tomix, r_mixer_ctl_tocsr : std_logic_vector(7 downto 0);
signal r_edid_addr, r_edid_data : std_logic_vector(7 downto 0);
signal r_edid_wr : std_logic;
signal r_fb_pix32, r_fb_enable : std_logic;
signal r_fb_addr, r_fb_size : std_logic_vector(c_fml_depth-1 downto 0);
signal r_gpio_in, r_gpio_out : std_logic_vector(31 downto 0);
signal r_pll_ctl1, r_pll_ctl0, r_pll_status : std_logic_vector(31 downto 0);
signal r_pwm_ctl : std_logic_vector(7 downto 0);
signal dsi_gpio : std_logic_vector(2 downto 0);
signal pwm_prescaler : unsigned(6 downto 0);
signal pwm_count : unsigned(4 downto 0); -- 100 MHz / 4096 = 5 kHz
component xurv_core is
generic (
g_internal_ram_size : integer;
g_internal_ram_init_file : string;
g_simulation : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
cpu_rst_i : in std_logic := '0';
irq_i : in std_logic_vector(7 downto 0) := x"00";
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
host_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
host_slave_o : out t_wishbone_slave_out);
end component xurv_core;
component chipscope_icon is
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component chipscope_icon;
component chipscope_ila is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(7 downto 0));
end component chipscope_ila;
signal CONTROL : std_logic_vector(35 downto 0);
signal TRIG0 : std_logic_vector(7 downto 0);
signal uart_txd_int : std_logic;
signal clk_phy_shifted : std_logic;
signal clk_dsi_shifted : std_logic;
signal pll_clk_dsi_shifted : std_logic;
signal pll_sys_clk_sel, pll_clk_sys_buf : std_logic;
signal pll_rst : std_logic;
signal pll_do : std_logic_vector(15 downto 0);
signal pll_den : std_logic;
signal pll_dwe : std_logic;
signal pll_daddr : std_logic_vector(4 downto 0);
signal pll_di : std_logic_vector(15 downto 0);
signal pll_drdy : std_logic;
signal pll_locked : std_logic;
signal backlight_pwm : std_logic;
signal dcm_clk_sys, dcm_clk_sys_n : std_logic;
signal pll_locked_synced : std_logic;
signal pll_locked_n_masked : std_logic;
signal pll_reconfiguring : std_logic;
signal pll_clk_in_bufio : std_logic;
signal pll_clk_in_reconf : std_logic;
signal mask_reset_input : std_logic;
signal rst_n_sys_pre : std_logic;
begin -- rtl
uart_txd_o <= uart_txd_int;
rst_sys <= not rst_n_sys;
U_Sync_DSI_Reset : gc_sync_ffs
port map (
clk_i => clk_dsi,
rst_n_i => '1',
data_i => rst_n_sys,
synced_o => rst_n_dsi);
--BUFIO2_1: BUFIO2
-- generic map (
-- DIVIDE_BYPASS => true,
-- DIVIDE => 1,
-- I_INVERT => false,
-- USE_DOUBLER => false)
-- port map (
-- DIVCLK => pll_clk_in,
-- IOCLK => open,
-- SERDESSTROBE => open,
-- I => clk_25m_i);
U_IbufG_CLKIn : IBUFG
port map (
I => clk_25m_i,
O => pll_clk_in
);
-- U_IbufG_CLKIn: BUFG
-- port map (
-- I => pll_clk_in,
-- O => pll_clk_in_reconf
-- );
pll_clk_in_reconf <= pll_clk_in;
U_PLL : PLL_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => g_pll_mul,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => g_pll_phy_div,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => g_pll_phy_div,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => g_pll_phy_div * 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => g_pll_phy_div * 8,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DIVIDE => g_pll_sys_div,
CLKOUT4_PHASE => 0.000,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DIVIDE => g_pll_sys_div,
CLKOUT5_PHASE => 180.000,
CLKOUT5_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 40.000,
CLKIN2_PERIOD => 40.000,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map (
CLKIN1 => pll_clk_in,
CLKIN2 => '0',
CLKINSEL => '1', -- select CLKIN1
CLKFBOUT => pll_clk_fb,
CLKOUT0 => clk_phy,
CLKOUT1 => clk_phy_shifted,
CLKOUT2 => open,
CLKOUT3 => pll_clk_dsi,
CLKOUT4 => pll_clk_sys,
CLKOUT5 => pll_clk_sys_n,
LOCKED => pll_locked,
RST => pll_rst,
CLKFBIN => pll_clk_fb,
DO => pll_do,
DI => pll_di,
DRDY => pll_drdy,
DADDR => pll_daddr,
DCLK => pll_clk_in_reconf,
DEN => pll_den,
DWE => pll_dwe,
REL => '0'
);
U_PLL_Reconf : pll_drp_sequencer
port map (
clk_sys_i => clk_sys,
clk_reconf_i => pll_clk_in_reconf,
r_pll_ctl0_i => r_pll_ctl0,
r_pll_ctl1_i => r_pll_ctl1,
r_pll_status_o => r_pll_status,
pll_locked_i => pll_locked,
pll_rst_o => pll_rst,
pll_di_o => pll_di,
pll_do_i => pll_do,
pll_drdy_i => pll_drdy,
pll_daddr_o => pll_daddr,
pll_den_o => pll_den,
pll_dwe_o => pll_dwe,
busy_o => pll_reconfiguring);
pll_locked_n <= not pll_locked;
U_BufG_CLK_DSI : BUFG
port map (
I => pll_clk_dsi,
O => clk_dsi);
--U_BufG_CLK_DSI_Shifted: BUFG
-- port map (
-- I => pll_clk_dsi_shifted,
-- O => clk_dsi_shifted);
U_BufG_CLK_SYS : BUFG
port map (
I => pll_clk_sys,
O => clk_sys);
--U_BufG_CLK_SYS : BUFGCE
-- port map (
-- O => clk_sys,
-- I => pll_clk_sys,
-- CE => pll_reconfiguring);
--U_BufG_CLK_SYS_N : BUFGCE
-- port map (
-- O => clk_sys_n,
-- I => pll_clk_sys_n,
-- CE => pll_reconfiguring);
--U_BufG_CLK_DSI : BUFGMUX
-- port map (
-- O => clk_dsi,
-- I0 => pll_clk_dsi,
-- I1 => '0',
-- S => pll_reconfiguring);
U_BufG_CLK_SYS_N : BUFG
port map (
I => pll_clk_sys_n,
O => clk_sys_n);
pll_locked_n_masked <= pll_locked_n or pll_rst;
--dbg_o(0) <= clk_sys_div2;
--dbg_o(1) <= clk_sys_sh_div2;
--dbg_o(2) <= clk_dsi_div2;
--dbg_o(3) <= rst_n_sys;
dbg_o <= (others => '0');
U_Sync_PLL_Lock : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => pll_locked,
synced_o => pll_locked_synced);
U_Reset_Gen : reset_gen
port map (
clk_sys_i => clk_sys,
mask_reset_i => mask_reset_input,
spi_cs_n_rst_i => spi_cs_n_rst_b,
rst_sys_n_o => rst_n_sys_pre);
rst_n_sys <= rst_n_sys_pre and pll_locked_synced; -- and rst_n_sys_pre;
U_Intercon : xwb_crossbar
generic map (
g_num_masters => c_cnx_slave_ports,
g_num_slaves => c_cnx_master_ports,
g_registered => true,
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_CPU : xurv_core
generic map (
g_internal_ram_size => 32768,
g_internal_ram_init_file => "",
g_simulation => g_simulation)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
cpu_rst_i => rst_sys,
irq_i => x"00",
dwb_o => cnx_slave_in(0),
dwb_i => cnx_slave_out(0)
);
U_UART : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_slave_uart),
slave_o => cnx_master_in(c_slave_uart),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_int);
csr_we <= cnx_master_out(c_slave_ddram_csr).cyc and cnx_master_out(c_slave_ddram_csr).stb and
cnx_master_out(c_slave_ddram_csr).we;
U_DDR_Controller : hpdmc
generic map (
data_delay => g_data_delay,
dqs_delay => g_dqs_delay,
clock_delay => g_clock_delay,
addr_delay => g_addr_delay)
port map (
sys_clk => clk_sys,
sys_clk_n => clk_sys_n,
sys_rst => rst_sys,
csr_a => cnx_master_out(c_slave_ddram_csr).adr(15 downto 2),
csr_we => csr_we,
csr_di => cnx_master_out(c_slave_ddram_csr).dat,
csr_do => cnx_master_in(c_slave_ddram_csr).dat,
fml_adr => ddrc.adr(24 downto 0),
fml_stb => ddrc.stb,
fml_we => ddrc.we,
fml_eack => ddrc.eack,
fml_sel => ddrc.sel,
fml_di => ddrc.d_m2s,
fml_do => ddrc.d_s2m,
sdram_clk_p => sdram_clk_p,
sdram_clk_n => sdram_clk_n,
sdram_cke => sdram_cke,
sdram_cs_n => sdram_cs_n,
sdram_we_n => sdram_we_n,
sdram_cas_n => sdram_cas_n,
sdram_ras_n => sdram_ras_n,
sdram_adr => sdram_adr,
sdram_ba => sdram_ba,
sdram_dm => sdram_dm,
sdram_dq => sdram_dq,
sdram_dqs => sdram_dqs);
U_FML_Arb : fmlarb
generic map (
fml_width => 32,
fml_depth => c_fml_depth)
port map (
sys_clk => clk_sys,
sys_rst => rst_sys,
m0_adr => frameb.adr,
m0_stb => frameb.stb,
m0_we => frameb.we,
m0_ack => frameb.ack,
m0_sel => frameb.sel,
m0_do => frameb.d_s2m,
m1_adr => fwb.adr,
m1_stb => fwb.stb,
m1_we => fwb.we,
m1_ack => fwb.ack,
m1_sel => fwb.sel,
m1_di => fwb.d_m2s,
m1_do => fwb.d_s2m,
s_adr => ddrc.adr,
s_stb => ddrc.stb,
s_we => ddrc.we,
s_eack => ddrc.eack,
s_sel => ddrc.sel,
s_di => ddrc.d_s2m,
s_do => ddrc.d_m2s);
U_FML_WB_Bridge : fml_wb_bridge
generic map (
sdram_depth => 25)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
fml_adr => fwb.adr,
fml_stb => fwb.stb,
fml_we => fwb.we,
fml_ack => fwb.ack,
fml_sel => fwb.sel,
fml_di => fwb.d_s2m,
fml_do => fwb.d_m2s,
wb_adr_i => cnx_master_out(c_slave_ddram_mem).adr,
wb_cyc_i => cnx_master_out(c_slave_ddram_mem).cyc,
wb_we_i => cnx_master_out(c_slave_ddram_mem).we,
wb_sel_i => cnx_master_out(c_slave_ddram_mem).sel,
wb_stb_i => cnx_master_out(c_slave_ddram_mem).stb,
wb_dat_i => cnx_master_out(c_slave_ddram_mem).dat,
wb_dat_o => cnx_master_in(c_slave_ddram_mem).dat,
wb_stall_o => cnx_master_in(c_slave_ddram_mem).stall,
wb_ack_o => cnx_master_in(c_slave_ddram_mem).ack
);
U_DSI_Core : dsi_core
generic map
(g_clock_period_ps => g_clock_period_ps)
port map (
clk_dsi_i => clk_dsi,
clk_dsi_shifted_i => clk_dsi,
clk_sys_i => clk_sys,
clk_phy_i => clk_phy,
clk_phy_shifted_i => clk_phy_shifted,
rst_n_i => rst_n_dsi,
pll_locked_i => pll_locked,
pix_i => dsif_pix,
pix_almost_full_o => dsif_almost_full,
pix_vsync_i => dsif_vsync,
pix_next_frame_o => dsif_next_frame,
pix_wr_i => dsif_wr,
dsi_clk_p_o => dsi_clk_p_o,
dsi_clk_n_o => dsi_clk_n_o,
dsi_clk_lp_n_o => dsi_clk_lp_n,
dsi_clk_lp_p_o => dsi_clk_lp_p,
dsi_clk_lp_oe_o => dsi_clk_lp_oe,
dsi_hs_p_o => dsi_hs_p_o,
dsi_hs_n_o => dsi_hs_n_o,
dsi_lp_p_o => dsi_lp_p_int,
dsi_lp_n_o => dsi_lp_n_int,
dsi_lp_oe_o => dsi_lp_oe,
dsi_reset_n_o => dsi_resetb_o,
dsi_gpio_o => dsi_gpio,
wb_adr_i => cnx_master_out(c_slave_dsi).adr,
wb_cyc_i => cnx_master_out(c_slave_dsi).cyc,
wb_we_i => cnx_master_out(c_slave_dsi).we,
wb_sel_i => cnx_master_out(c_slave_dsi).sel,
wb_stb_i => cnx_master_out(c_slave_dsi).stb,
wb_dat_i => cnx_master_out(c_slave_dsi).dat,
wb_dat_o => cnx_master_in(c_slave_dsi).dat,
wb_stall_o => cnx_master_in(c_slave_dsi).stall,
wb_ack_o => cnx_master_in(c_slave_dsi).ack
);
U_Framebuffer : fml_framebuffer
generic map (
g_fml_depth => c_fml_depth
)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
pix_almost_full_i => fb_almost_full,
pix_wr_o => fb_wr,
pix_o => fb_pix,
pix_vsync_o => fb_vsync,
pix_next_frame_i => fb_next_frame,
fml_adr => frameb.adr,
fml_stb => frameb.stb,
fml_we => frameb.we,
fml_ack => frameb.ack,
fml_sel => frameb.sel,
fml_di => frameb.d_s2m,
r_fb_addr_i => r_fb_addr,
r_fb_size_i => r_fb_size,
r_fb_pix32_i => r_fb_pix32,
r_fb_enable_i => r_fb_enable
);
U_Sysctl_Regs : sysctl_regs
generic map (
g_fml_depth => c_fml_depth,
g_default_pll_mul => g_pll_mul,
g_default_pll_sys_div => g_pll_sys_div)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
wb_adr_i => cnx_master_out(c_slave_csr).adr,
wb_cyc_i => cnx_master_out(c_slave_csr).cyc,
wb_we_i => cnx_master_out(c_slave_csr).we,
wb_sel_i => cnx_master_out(c_slave_csr).sel,
wb_stb_i => cnx_master_out(c_slave_csr).stb,
wb_dat_i => cnx_master_out(c_slave_csr).dat,
wb_dat_o => cnx_master_in(c_slave_csr).dat,
wb_stall_o => cnx_master_in(c_slave_csr).stall,
wb_ack_o => cnx_master_in(c_slave_csr).ack,
r_fb_enable_o => r_fb_enable,
r_fb_pix32_o => r_fb_pix32,
r_fb_addr_o => r_fb_addr,
r_fb_size_o => r_fb_size,
r_mixer_ctl_i => r_mixer_ctl_tocsr,
r_mixer_ctl_o => r_mixer_ctl_tomix,
r_edid_addr_o => r_edid_addr,
r_edid_data_o => r_edid_data,
r_edid_wr_o => r_edid_wr,
r_pwm_ctl_o => r_pwm_ctl,
r_pll_ctl0_o => r_pll_ctl0,
r_pll_ctl1_o => r_pll_ctl1,
r_pll_status_i => r_pll_status,
r_gpio_o => r_gpio_out,
r_gpio_i => r_gpio_in);
gen_with_hdmi_sampler : if (g_with_hdmi = true) generate
U_HDMI_RX : dvi_decoder
port map
(
tmdsclk_p => hdmi_rx_p_i(3),
tmdsclk_n => hdmi_rx_n_i(3),
blue_p => hdmi_rx_p_i(0),
blue_n => hdmi_rx_n_i(0),
green_p => hdmi_rx_p_i(1),
green_n => hdmi_rx_n_i(1),
red_p => hdmi_rx_p_i(2),
red_n => hdmi_rx_n_i(2),
exrst => rst_sys,
pclk => hdmi_pclk,
hsync => hdmi_hsync,
vsync => hdmi_vsync,
de => hdmi_de,
pixel => hdmi_pixel,
link_up => hdmi_link_up,
pixel_valid => hdmi_valid
);
end generate gen_with_hdmi_sampler;
mask_reset_input <= r_gpio_out(3);
spi_cs_n_rst_b <= r_gpio_out(4) when mask_reset_input = '1' else 'Z';
spi_sck_o <= r_gpio_out(5);
spi_mosi_o <= r_gpio_out(6);
r_gpio_in(6) <= spi_miso_i;
U_EDID_EEPROM : edid_eeprom
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
edid_en_i => r_gpio_out(0),
scl_master_i => r_gpio_out(1),
sda_master_i => r_gpio_out(2),
sda_master_o => r_gpio_in(2),
scl_b => hdmi_scl_b,
sda_b => hdmi_sda_b,
hdmi_p5v_notif_i => hdmi_p5v_notif_i,
hdmi_hpd_en_o => hdmi_hpd_o,
addr_i => r_edid_addr,
data_i => r_edid_data,
wr_i => r_edid_wr);
U_Video_Mixer : video_mixer
port map (
clk_sys_i => clk_sys,
clk_dvi_i => hdmi_pclk,
rst_n_i => rst_n_sys,
fb_almost_full_o => fb_almost_full,
fb_wr_i => fb_wr,
fb_pixel_i => fb_pix,
fb_vsync_i => fb_vsync,
fb_next_frame_o => fb_next_frame,
dvi_de_i => hdmi_de,
dvi_hsync_i => hdmi_hsync,
dvi_vsync_i => hdmi_vsync,
dvi_pixel_i => hdmi_pixel,
dvi_valid_i => hdmi_valid,
dvi_link_up_i => hdmi_link_up,
dsif_almost_full_i => dsif_almost_full,
dsif_wr_o => dsif_wr,
dsif_pix_o => dsif_pix,
dsif_vsync_o => dsif_vsync,
dsif_next_frame_i => dsif_next_frame,
mixer_ctl_i => r_mixer_ctl_tomix,
mixer_ctl_o => r_mixer_ctl_tocsr
);
gen_lp_tristates : for i in 0 to 3 generate
dsi_lp_p_o(i) <= '1' when (dsi_lp_p_int(i) = '1' and dsi_lp_oe(i) = '1') else 'Z';
dsi_lp_n_o(i) <= '1' when (dsi_lp_n_int(i) = '1' and dsi_lp_oe(i) = '1') else 'Z';
end generate gen_lp_tristates;
dsi_clk_lp_p_o <= '1' when (dsi_clk_lp_p = '1' and dsi_clk_lp_oe = '1') else 'Z';
dsi_clk_lp_n_o <= '1' when (dsi_clk_lp_n = '1' and dsi_clk_lp_oe = '1') else 'Z';
process(clk_sys)
begin
if rising_edge(clk_sys) then
cnx_master_in(c_slave_ddram_csr).ack <= cnx_master_out(c_slave_ddram_csr).stb and cnx_master_out(c_slave_ddram_csr).cyc;
end if;
end process;
cnx_master_in(c_slave_dsi).err <= '0';
cnx_master_in(c_slave_ddram_csr).stall <= '0';
cnx_master_in(c_slave_ddram_csr).err <= '0';
cnx_master_in(c_slave_ddram_mem).err <= '0';
dsi_gpio1_o <= dsi_gpio(0);
dsi_gpio0_o <= 'Z';
p_bl_pwm : process(clk_sys)
begin
if rising_edge(clk_sys) then
if rst_n_sys = '0' then
pwm_prescaler <= (others => '0');
pwm_count <= (others => '0');
bl_dim_o <= '0';
else
pwm_prescaler <= pwm_prescaler + 1;
if(pwm_prescaler = 0) then
pwm_count <= pwm_count + 1;
end if;
if(pwm_count < unsigned(r_pwm_ctl)) then
bl_dim_o <= '1';
else
bl_dim_o <= '0';
end if;
end if;
end if;
end process;
lcd_pwren_o <= '1';
vid_resetn_o <= '1';
end rtl;
|
lgpl-3.0
|
d398965214bb21da9d8b1a4d46d87cec
| 0.520429 | 2.941533 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/user_processes/uf_extract_observation.vhd
| 1 | 36,660 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N
--
--
-- The user function calcualtes a observation for a particle
-- A pointer to the input data is given. The user process can
-- ask for data at a specific address.
--
-- Thus, all needed data can be loaded into the entity. Thus,
-- the observation can be calculated via input data. When no more
-- data is needed, the observation is stored into the local ram.
--
-- If the observation is stored in the ram, the finished signal has
-- to be set to '1'.
--
------------------------------------------------------------------------------------
entity uf_extract_observation is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input/measurement data address
input_data_address : in std_logic_vector(0 to 31);
-- get data block
get_data_needed : out std_logic;
get_data_address : out std_logic_vector(0 to 31);
get_data_length : out integer;
-- receive data block
receive_data_en : in std_logic;
receive_data_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- recieved data
receive_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end uf_extract_observation;
architecture Behavioral of uf_extract_observation is
component pipelined_divider
port (
clk: in std_logic;
ce: in std_logic;
aclr: in std_logic;
sclr: in std_logic;
dividend: in std_logic_VECTOR(31 downto 0);
divisor: in std_logic_VECTOR(31 downto 0);
quot: out std_logic_VECTOR(31 downto 0);
remd: out std_logic_VECTOR(31 downto 0);
rfd: out std_logic);
end component;
type hsv_function is array ( 0 to 255) of integer;
-- GRANULARITY
constant GRAN_EXP : integer := 14;
constant GRANULARITY : integer := 2**GRAN_EXP;
constant hd_values : hsv_function := (
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9);
constant sdvd_values : hsv_function := (
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9);
-- states
type t_state is (STATE_INIT, STATE_READ_PARAMETER, STATE_INIT_HISTOGRAM,
STATE_READ_PARTICLE, STATE_ANALYZE_PARTICLE,
STATE_CALCULATE_HISTOGRAM, STATE_NORMALIZE_HISTOGRAM,
STATE_COPY_HISTOGRAM, STATE_FINISH);
signal state : t_state;
-----------------------------------------------------
-- signals needed for divider component
-----------------------------------------------------
-- clock enable
signal ce : std_logic;
-- synchronous clear
signal sclr : std_logic := '0';
-- asynchronous clear
signal aclr : std_logic := '0';
-- dividend
signal dividend : std_logic_vector(31 downto 0) := (others => '0');
-- divisor
signal divisor : std_logic_vector(31 downto 0) := "00000000000000000000000000000001";
-- quotient
signal quotient : std_logic_vector(31 downto 0) := (others => '0');
-- remainder
signal remainder : std_logic_vector(31 downto 0) := (others => '0');
-- ready for data
signal rfd : std_logic;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- HSV signals
signal H : std_logic_vector(0 to 7) := (others => '0');
signal S : std_logic_vector(0 to 7) := (others => '0');
signal V : std_logic_vector(0 to 7) := (others => '0');
constant S_THRESH : integer := 25;
constant V_THRESH : integer := 50;
signal hd : natural range 0 to 9 := 0;
signal sd : natural range 0 to 9 := 0;
signal vd : natural range 0 to 9 := 0;
signal value : natural := 0;
-- copy histogram
signal copy_histo_en : std_logic := '0'; -- handshake signal
signal copy_histo_done : std_logic := '0'; -- handshake signal
signal copy_histo_addr : std_logic_vector(C_TASK_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal copy_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr
signal copy_histo_data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- update histogram
signal update_histo_en : std_logic := '0'; -- handshake signal
signal update_histo_done : std_logic := '0'; -- handshake signal
signal update_histo_addr : std_logic_vector(C_TASK_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal update_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr
-- calculate histogram
signal calculate_histo_en : std_logic := '0'; -- handshake signal
signal calculate_histo_done : std_logic := '0'; -- handshake signal
-- clear histogram
signal clear_histo_en : std_logic := '0'; -- handshake signal
signal clear_histo_done : std_logic := '0'; -- handshake signal
signal clear_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr
-- normalize histogram
signal normalize_histo_en : std_logic := '0'; -- handshake signal
signal normalize_histo_done : std_logic := '0'; -- handshake signal
signal normalize_histo : std_logic := '0'; -- set histo_ram value
signal normalize_histo_value : std_logic_vector(31 downto 0) := (others=>'0'); -- new normalized histo value
signal normalize_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr
-- read particle data
signal read_particle_en : std_logic := '0'; -- handshake signal
signal read_particle_done : std_logic := '0'; -- handshake signal
signal read_particle_addr : std_logic_vector(C_TASK_BURST_AWIDTH-1 downto 0) := (others=>'0');
-- read parameter
signal read_parameter_en : std_logic := '0'; -- handshake signal
signal read_parameter_done : std_logic := '0'; -- handshake signal
signal read_parameter_addr : std_logic_vector(C_TASK_BURST_AWIDTH-1 downto 0) := (others=>'0');
-- analyze particle
signal analyze_particle_en : std_logic := '0'; -- handshake signal
signal analyze_particle_done : std_logic := '0'; -- handshake signal
-- prefetch line
signal prefetch_line_en : std_logic := '0'; -- handshake signal
signal prefetch_line_done : std_logic := '0'; -- handshake signal
signal prefetch_line_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- histogram
type t_ram is array (109 downto 0) of std_logic_vector(31 downto 0);
signal histo_ram : t_ram; -- histogram memory
signal histo_bucket : std_logic_vector(6 downto 0); -- current histogram bucket
signal histo_inc : std_logic := '0'; -- enables incrementing
signal histo_clear : std_logic := '0'; -- enables setting to zero
signal histo_value : std_logic_vector(31 downto 0); -- value of current bucket
-- particle data
signal x : integer := 0;
signal y : integer := 0;
signal scale : integer := 0;
signal width : integer := 0;
signal height : integer := 0;
-- input data
-- left upper corner
signal x1 : integer := 0;
signal y1 : integer := 0;
-- right bottom corner
signal x2 : integer := 0;
signal y2 : integer := 2;
-- current pixel
signal px : integer := 0;
signal py : integer := 0;
-- frame values
signal size_x : integer := 480;
signal size_y : integer := 360;
-- temporary signals
signal temp_x : integer := 0;
signal temp_y : integer := 0;
signal temp : integer := 0;
-- input data offset
signal get_data_offset : integer := 0;
-- number of lines
signal number_of_lines : integer := 0;
-- length of line
signal line_length : integer := 0;
-- sum of histogram
signal sum : integer := 0;
-- signal for counter
signal i : integer := 0;
signal j : integer := 0;
begin
divider : pipelined_divider
port map ( clk => clk, ce => ce, aclr => aclr, sclr => sclr, dividend => dividend,
divisor => divisor, quot => quotient, remd => remainder, rfd => rfd);
-- burst ram interface
o_RAMClk <= clk;
ce <= enable;
-- histogram memory is basically a single port ram with
-- asynchronous read. the current bucket is incremented each
-- clock cycle when histo_inc is high, or set to zero when
-- histo_clear is high.
-- @author: Andreas Agne, changed by Markus Happe
histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
histo_ram_proc : process(clk)
begin
if rising_edge(clk) then
-- TRY: CLOCKED VERSION
--histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
if histo_inc = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= histo_ram(CONV_INTEGER(histo_bucket)) + 1;
elsif histo_clear = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= (others=>'0');
elsif normalize_histo = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= normalize_histo_value;
end if;
end if;
end process;
-- calculate histogram. Prefetch line. Parallel execution of
-- line prefetching (framwork) and histogram calculation (user proc.)
calc_histo_proc : process(clk, reset, calculate_histo_en)
variable step : natural range 0 to 5;
begin
if reset = '1' or calculate_histo_en = '0' then
step := 0;
prefetch_line_en <= '0';
update_histo_en <= '0';
calculate_histo_done <= '0';
elsif rising_edge(clk) then
case step is
-- (i) prefetch 1st line
-- (ii) prefetch next line and update histogram for current line
-- (iii) update histogram for last line
when 0 =>
-- prefetch first line
prefetch_line_en <= '1';
update_histo_en <= '0';
number_of_lines <= 1 + y2 - y1;
py <= y1;
step := step + 1;
when 1 =>
-- prefetch first line completed
if (prefetch_line_done = '1') then
prefetch_line_en <= '0';
number_of_lines <= number_of_lines - 1;
step := step + 1;
end if;
when 2 =>
-- update histogram start
update_histo_en <= '1';
step := step + 1;
when 3 =>
-- update histogram stop
if (update_histo_done = '1') then
update_histo_en <= '0';
step := step + 1;
end if;
when 4 =>
-- more lines?
if (number_of_lines <= 0) then
step := step + 1;
else
step := step - 3;
prefetch_line_en <= '1';
py <= py + 1;
end if;
-- when 2 =>
-- -- start parallel execution, or start last update
-- if (number_of_lines <= 0) then
-- -- last line allready prefetched
-- update_histo_en <= '1';
-- prefetch_line_en <= '0';
-- step := step + 2;
-- else
-- -- more lines to go
-- prefetch_line_en <= '1';
-- update_histo_en <= '1';
-- py <= py + 1;
-- step := step + 1;
-- end if;
--
-- when 3 =>
-- -- parallel execution completed
-- if (prefetch_line_done = '1' and update_histo_done = '1') then
-- prefetch_line_en <= '0';
-- update_histo_en <= '0';
-- number_of_lines <= number_of_lines - 1;
-- step := step - 1;
-- end if;
--
-- when 4 =>
-- -- last line
-- if (update_histo_done = '1') then
-- update_histo_en <= '0';
-- step := step + 1;
-- end if;
when 5 =>
-- finished
calculate_histo_done <= '1';
end case;
end if;
end process;
-- prefetch pixel line for histogram calculation
prefetch_line_proc : process(clk, reset, prefetch_line_en)
variable step : natural range 0 to 5;
begin
if reset = '1' or prefetch_line_en = '0' then
step := 0;
prefetch_line_done <= '0';
--receive_data_ack <= '0';
get_data_needed <= '0';
get_data_length <= 0;
elsif rising_edge(clk) then
case step is
-- (i) calculate get data address, length
-- (ii) ask framework for data
when 0 =>
receive_data_ack <= '0';
get_data_needed <= '0';
-- calculate get_data_offset (1 of 3)
get_data_offset <= py * 1024;
step := step + 1;
when 1 =>
-- calculate get_data_offset (2 of 3)
get_data_offset <= get_data_offset + x1;
line_length <= 1 + x2;
step := step + 1;
when 2 =>
-- calculate get_data_offset (3 of 3)
get_data_offset <= get_data_offset * 4;
line_length <= line_length - x1;
step := step + 1;
when 3 =>
-- get data by framework, ask framework for data
get_data_address <= input_data_address + get_data_offset;
get_data_length <= line_length * 4;
get_data_needed <= '1';
step := step + 1;
when 4 =>
-- receive answer from framework
if (receive_data_en = '1') then
receive_data_ack <= '1';
get_data_needed <= '0';
prefetch_line_address <= receive_data_address;
step := step + 1;
end if;
when 5 =>
-- finished
receive_data_ack <= '1';
prefetch_line_done <= '1';
end case;
end if;
end process;
-- update histogram for one line, stored in cache
update_histogramm : process(clk, reset, update_histo_en, enable)
variable step : natural range 0 to 7;
variable my_step : natural range 0 to 7;
begin
if reset = '1' or update_histo_en = '0' then
step := 0;
my_step := 0;
histo_inc <= '0';
update_histo_addr <= (others => '0');
update_histo_done <= '0';
update_histo_bucket <= (others => '0');
elsif rising_edge(clk) then
if enable = '0' then
-- framework maybe interrupted
step := 7;
histo_inc <= '0';
else
case step is
-- (i) load first pixel
-- (ii) update histogram for current pixel and load next one (if needed)
when 0 =>
-- start to read 1st pixel
update_histo_addr <= prefetch_line_address;
px <= x1;
step := step + 1;
my_step := 1;
when 1 =>
-- wait one cycle (for local ram data to become valid)
step := step + 1;
my_step := 2;
when 2 =>
-- update histogram (1 of 2)
-- extract H, S, V values
H(0 to 7) <= i_RamData( 24 to 31);
S(0 to 7) <= i_RamData( 16 to 23);
V(0 to 7) <= i_RamData( 8 to 15);
-- do not increment histogram in this step
histo_inc <= '0';
-- get next pixel
update_histo_addr <= update_histo_addr + 1;
step := step + 1;
my_step := 3;
when 3 =>
-- update histogram (2 of 2)
-- calculate histogram bucket for current pixel and update
if( S_THRESH <= S and V_THRESH <= V) then
update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED(((10
* sdvd_values(TO_INTEGER(UNSIGNED(S))))
+ hd_values(TO_INTEGER(UNSIGNED(H)))), 7));
else
update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED((100
+ sdvd_values(TO_INTEGER(UNSIGNED(V)))), 7));
end if;
-- increment histogram value at update_histo_bucket
histo_inc <= '1';
-- update current pixel position
px <= px + 1;
-- more pixels in line?
if (x2 <= px) then
-- no more pixels
step := step + 1;
my_step := 4;
else
-- more pixels to go
step := step - 1;
my_step := 2;
end if;
when 4 =>
-- updating finished
histo_inc <= '0';
update_histo_done <= '1';
my_step := 4;
when 5 =>
-- additional wait cycle for step 2
step := step - 3;
when 6 =>
-- additional wait cycle for step 3
step := step - 3;
when 7 =>
if (my_step = 1) then
step := 0;
elsif (my_step = 2) then
step := 5;
elsif (my_step = 3) then
step := 6;
else
step := my_step;
end if;
histo_inc <= '0';
end case;
end if;
end if;
end process;
-- signals and processes related to copying the histogram to
-- burst-ram
-- @author: Andreas Agne
copy_histogram : process(clk, reset, copy_histo_en)
variable step : natural range 0 to 7;
begin
if reset = '1' or copy_histo_en = '0' then
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
copy_histo_done <= '0';
o_RAMWE <= '0';
copy_histo_data <= (others => '0');
step := 0;
elsif rising_edge(clk) then
case step is
when 0 => -- set histogram and burst ram addresses to 0
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
step := step + 1;
when 1 => -- copy first word
copy_histo_addr <= (others => '0');
copy_histo_bucket <= copy_histo_bucket + 1;
o_RAMWE <= '1';
copy_histo_data <= histo_value;
step := step + 1;
when 2 => -- copy remaining histogram buckets to burst ram
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_bucket <= copy_histo_bucket + 1;
o_RAMWE <= '1';
copy_histo_data <= histo_value;
if (108 <= copy_histo_bucket) then
step := step + 1;
end if;
when 3 => -- wait (1 of 2)
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= histo_value;
step := step + 1;
when 4 => -- wait (2 of 2)
o_RAMWE <= '1';
step := step + 1;
when 5 => -- write n
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(110, 32));
step := step + 1;
when 6 => -- write dummy
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(0, 32));
step := step + 1;
when 7 => -- all buckets copied -> set handshake signal
copy_histo_done <= '1';
copy_histo_bucket <= (others => '0');
o_RAMWE <= '0';
end case;
end if;
end process;
-- signals and processes related to clearing the histogram
-- @author: Andreas Agne
clear_histogram_proc : process(clk, reset, clear_histo_en)
variable step : natural range 0 to 3;
begin
if reset = '1' or clear_histo_en = '0' then
step := 0;
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '0';
elsif rising_edge(clk) then
case step is
when 0 => -- enable bucket zeroing
clear_histo_bucket <= (others => '0');
histo_clear <= '1';
step := step + 1;
when 1 => -- visit every bucket
clear_histo_bucket <= clear_histo_bucket + 1;
if 108 <= clear_histo_bucket then
step := step + 1;
end if;
when 2 =>
step := step + 1;
when 3 => -- set handshake signal
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '1';
end case;
end if;
end process;
-- signals and processes related to normalizing the histograme
normalize_histogram_proc : process(clk, reset, normalize_histo_en, ce)
variable step : natural range 0 to 7;
begin
if reset = '1' or normalize_histo_en = '0' then
step := 0;
normalize_histo_bucket <= (others => '0');
normalize_histo_done <= '0';
elsif ce = '0' then
elsif rising_edge(clk) then
case step is
when 0 =>
-- init sum calculation
i <= 0;
sum <= 0;
step := step + 1;
when 1 =>
-- calculate sum
sum <= sum + CONV_INTEGER(histo_ram(i));
if (i < 109) then
i <= i + 1;
else
step := step + 1;
end if;
-- init
when 2 =>
normalize_histo_bucket <= (others => '0');
normalize_histo <= '0';
i <= 0;
step := step + 1;
-- modify histo_values (histo_value * GRANULARITY) and sum up histogram
-- first histo_value
when 3 =>
normalize_histo <= '1';
-- modify value: value * GRANULARITY
normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000";
i <= 1;
step := step + 1;
-- other histo_values
when 4 =>
normalize_histo <= '1';
-- modify value: value * GRANULARITY
normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000";
if (i < 109) then
i <= i + 1;
end if;
if (normalize_histo_bucket < 109) then
normalize_histo_bucket <= normalize_histo_bucket + 1;
else
step := step + 1;
end if;
when 5 =>
-- start division
normalize_histo <= '0';
normalize_histo_bucket <= (others => '0');
divisor <= STD_LOGIC_VECTOR(TO_SIGNED(sum, 32));
i <= 0;
step := step + 1;
when 6 =>
-- put all 110 histogram values into pipelined divider.
-- pipelined divider has a latency of 36 clock cycles
-- 36 = 32 (width of dividend) + 4 (see: coregen datasheed)
-- one clock cycle per division
if (i<110) then
-- put histogram values to pipeline
dividend <= histo_ram(i);
i <= i + 1;
end if;
if (i > 36) then
-- collect division results
normalize_histo <= '1';
normalize_histo_value <= quotient;
if (normalize_histo_bucket < 109 and i > 37) then
normalize_histo_bucket <= normalize_histo_bucket + 1;
elsif (109 <= normalize_histo_bucket) then
step := step + 1;
end if;
end if;
when 7 =>
-- set handshake signal;
normalize_histo <= '0';
normalize_histo_bucket <= (others => '0');
normalize_histo_done <= '1';
end case;
end if;
end process;
-- reads parameter
read_parameter_proc: process (clk, reset, read_parameter_en)
variable step : natural range 0 to 4;
begin
if reset = '1' or read_parameter_en = '0' then
step := 0;
read_parameter_done <= '0';
parameter_loaded_ack <= '0';
elsif rising_edge(clk) then
case step is
when 0 =>
--! read parameter values
read_parameter_addr <= local_ram_start_address_if;
parameter_loaded_ack <= '0';
step := step + 1;
when 1 =>
--! wait one cycle
read_parameter_addr <= local_ram_start_address_if + 1;
step := step + 1;
when 2 =>
--! read size_x
size_x <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 3 =>
--! read size_y
size_y <= TO_INTEGER(SIGNED(i_RAMData));
parameter_loaded_ack <= '1';
step := step + 1;
when 4 =>
if (parameter_loaded = '0') then
read_parameter_done <= '1';
parameter_loaded_ack <= '0';
end if;
end case;
end if;
end process;
-- reads particle data needed for histogram calculation
read_particle_proc: process (clk, reset, read_particle_en, ce)
variable step : natural range 0 to 8;
begin
if reset = '1' or read_particle_en = '0' then
step := 0;
read_particle_done <= '0';
--local_ram_address_if <= local_ram_start_address_if;
elsif ce = '0' then
elsif rising_edge(clk) and ce = '1' then
case step is
when 0 =>
--! increment local ram address to get x value
local_ram_address_if <= local_ram_start_address_if + 1;
step := step + 1;
when 1 =>
--! read particle values
read_particle_addr <= local_ram_address_if;
local_ram_address_if <= local_ram_address_if + 1;
step := step + 1;
when 2 =>
--! wait one cycle
local_ram_address_if <= local_ram_address_if + 1;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 3 =>
--! read x
x <= TO_INTEGER(SIGNED(i_RAMData));
local_ram_address_if <= local_ram_address_if + 6;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 4 =>
--! read y
y <= TO_INTEGER(SIGNED(i_RAMData));
local_ram_address_if <= local_ram_address_if + 1;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 5 =>
--! read scale
scale <= TO_INTEGER(SIGNED(i_RAMData));
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 6 =>
--! read width
width <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 7 =>
--! read height
height <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 8 =>
read_particle_done <= '1';
end case;
end if;
end process;
-- analyzes particle data needed for histogram calculation
analyze_particle_proc: process (clk, reset, analyze_particle_en, ce)
variable step : natural range 0 to 13;
begin
if reset = '1' or analyze_particle_en = '0' then
step := 0;
analyze_particle_done <= '0';
elsif ce = '0' then
elsif rising_edge(clk) and ce = '1' then
case step is
when 0 =>
--! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece
temp_x <= width - 1;
temp_y <= height - 1;
step := step + 1;
when 1 =>
--! calculate (x1, y1) and (x2, y2)
temp_x <= temp_x / 2;
step := step + 1;
when 2 =>
--! calculate (x1, y1) and (x2, y2)
temp_y <= temp_y / 2;
step := step + 1;
when 3 =>
--! calculate (x1, y1) and (x2, y2)
temp_x <= temp_x * scale;
step := step + 1;
when 4 =>
--! calculate (x1, y1) and (x2, y2)
temp_y <= temp_y * scale;
step := step + 1;
when 5 =>
--! calculate (x1, y1) and (x2, y2)
x1 <= x - temp_x;
step := step + 1;
when 6 =>
--! calculate (x1, y1) and (x2, y2)
x2 <= x + temp_x;
step := step + 1;
when 7 =>
--! calculate (x1, y1) and (x2, y2)
y1 <= y - temp_y;
step := step + 1;
when 8 =>
--! calculate (x1, y1) and (x2, y2)
y2 <= y + temp_y;
step := step + 1;
when 9 =>
--! calculate (x1, y1) and (x2, y2)
x1 <= x1 / GRANULARITY;
step := step + 1;
when 10 =>
--! calculate (x1, y1) and (x2, y2)
y1 <= y1 / GRANULARITY;
if (x1 > size_x-1) then
x1 <= size_x - 1;
elsif (x1 < 0) then
x1 <= 0;
end if;
step := step + 1;
when 11 =>
--! calculate (x1, y1) and (x2, y2)
x2 <= x2 / GRANULARITY;
if (y1 > size_y-1) then
y1 <= size_y - 1;
elsif (y1 < 0) then
y1 <= 0;
end if;
step := step + 1;
when 12 =>
--! calculate (x1, y1) and (x2, y2)
y2 <= y2 / GRANULARITY;
if (x2 > size_x-1) then
x2 <= size_x - 1;
elsif (x2 < 0) then
x2 <= 0;
end if;
step := step + 1;
when 13 =>
--! finished
if (y2 > size_y-1) then
y2 <= size_y - 1;
elsif (y2 < 0) then
y2 <= 0;
end if;
if (y2 < y1) then
if (y2 > 0) then
y1 <= y2;
else
y1 <= 0;
end if;
end if;
if (x2 < x1) then
x1 <= x2;
end if;
analyze_particle_done <= '1';
end case;
end if;
end process;
-- histogram ram mux
-- @author: Andreas Agne
-- updated
mux_proc: process(update_histo_en, copy_histo_en, clear_histo_en, normalize_histo_en,
read_particle_en, read_particle_addr, normalize_histo_bucket,
update_histo_addr, update_histo_bucket,
copy_histo_addr, copy_histo_bucket, clear_histo_bucket,
copy_histo_data, read_parameter_en, read_parameter_addr)
variable addr : std_logic_vector(C_TASK_BURST_AWIDTH - 1 downto 0);
variable data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
variable bucket : std_logic_vector(6 downto 0);
begin
if update_histo_en = '1' then
addr := update_histo_addr;
bucket := update_histo_bucket;
data := (others => '0');
elsif copy_histo_en = '1' then
addr := copy_histo_addr;
bucket := copy_histo_bucket;
data := copy_histo_data;
elsif clear_histo_en = '1' then
addr := (others => '0');
bucket := clear_histo_bucket;
data := (others => '0');
elsif normalize_histo_en = '1' then
addr := (others => '0');
bucket := normalize_histo_bucket;
data := (others => '0');
elsif read_particle_en = '1' then
addr := read_particle_addr;
bucket := (others => '0');
data := (others => '0');
elsif read_parameter_en = '1' then
addr := read_parameter_addr;
bucket := (others => '0');
data := (others => '0');
else
addr := (others => '0');
bucket := (others => '0');
data := (others => '0');
end if;
o_RAMData <= data;
o_RAMAddr <= addr(C_TASK_BURST_AWIDTH - 1 downto 0);
histo_bucket <= bucket;
end process;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- --
-- 1) initialize histogram, finished = '0' (if new_particle = '1') --
-- --
-- 2) read particle data --
-- --
-- 3) extract needed information --
-- --
-- 4) calculate histogram --
-- --
-- 5) normalize histogram --
-- --
-- 6) write histogram into local ram --
-- --
-- 7) finshed = '1', wait for new_particle = '1' --
-- --
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
state_proc : process(clk, reset)
begin
if (reset = '1') then
state <= STATE_INIT;
new_particle_ack <= '0';
finished <= '0';
elsif rising_edge(clk) then
if init = '1' then
state <= STATE_INIT;
new_particle_ack <= '0';
clear_histo_en <= '0';
read_particle_en <= '0';
analyze_particle_en <= '0';
calculate_histo_en <= '0';
normalize_histo_en <= '0';
copy_histo_en <= '0';
finished <= '0';
elsif enable = '1' then
case state is
when STATE_INIT =>
--! init data
finished <= '0';
calculate_histo_en <= '0';
copy_histo_en <= '0';
read_particle_en <= '0';
analyze_particle_en <= '0';
normalize_histo_en <= '0';
if (new_particle = '1') then
new_particle_ack <= '1';
clear_histo_en <= '1';
state <= STATE_INIT_HISTOGRAM;
elsif (parameter_loaded = '1') then
read_parameter_en <= '1';
state <= STATE_READ_PARAMETER;
end if;
when STATE_READ_PARAMETER =>
--! init histogram
if (read_parameter_done = '1') then
read_parameter_en <= '0';
state <= STATE_INIT;
end if;
when STATE_INIT_HISTOGRAM =>
--! init histogram
if (clear_histo_done = '1') then
new_particle_ack <= '0';
clear_histo_en <= '0';
read_particle_en <= '1';
state <= STATE_READ_PARTICLE;
end if;
when STATE_READ_PARTICLE =>
--! read particle values
if (read_particle_done = '1') then
analyze_particle_en <= '1';
read_particle_en <= '0';
state <= STATE_ANALYZE_PARTICLE;
end if;
when STATE_ANALYZE_PARTICLE =>
--! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece
if (analyze_particle_done = '1') then
analyze_particle_en <= '0';
calculate_histo_en <= '1';
state <= STATE_CALCULATE_HISTOGRAM;
end if;
when STATE_CALCULATE_HISTOGRAM =>
-- get next pixel for histogram calculation
if (calculate_histo_done = '1') then
calculate_histo_en <= '0';
normalize_histo_en <= '1';
state <= STATE_NORMALIZE_HISTOGRAM;
end if;
when STATE_NORMALIZE_HISTOGRAM =>
--! normalize histogram
if (normalize_histo_done = '1') then
normalize_histo_en <= '0';
copy_histo_en <= '1';
state <= STATE_COPY_HISTOGRAM;
end if;
when STATE_COPY_HISTOGRAM =>
--! normalize histogram
if (copy_histo_done = '1') then
copy_histo_en <= '0';
state <= STATE_FINISH;
end if;
when STATE_FINISH =>
--! write finished signal
finished <= '1';
if (new_particle = '1') then
state <= STATE_INIT;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
2833c504a520dd8a42f89b2ed2296174
| 0.509329 | 3.371655 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_core_v2_03_a/hdl/vhdl/command_decoder.vhd
| 2 | 41,852 |
--!
--! \file command_decoder.vhd
--!
--! Handles commands coming from the HW thread and their return values
--!
--! \author Enno Luebbers <[email protected]>
--! \date 04.07.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 04.07.2007 Enno Luebbers File created
-- 11.07.2007 Enno Luebbers added mutex commands
-- 27.07.2007 Enno Luebbers added condvar commands
-- 25.09.2007 Enno Luebbers added mbox commands
-- 15.10.2007 Enno Luebbers added hardware mbox routing
-- 09.02.2008 Enno Luebbers added thread_exit() call
-- 19.04.2008 Enno Luebbers added handshaking between command_decoder
-- and HW thread
-- 23.04.2008 Enno Luebbers streamlined handshaking
--
------------------------------------------------------------------------------
--
-- Handshaking description between command_decoder and hardware threads:
--
-- To allow the command decoder to block the hardware thread's FSM, the
-- busy or blocking signal must arrive at the hardware thread before the
-- next step of its FSM is executed. This was previously (up to around
-- rev. 570) done by clocking the command decoder on the falling edge.
-- This introduced timing difficulties, especially when using partial
-- reconfiguration.
-- Now, the command_decoder ist again clocked on the rising edge of the
-- clock. Therefore, the hardware thread's FSM must wait one cycle at
-- every request to allow a possible busy/blocking signal to be
-- synchronously asserted by the command decoder, trading performance
-- for relaxed timing constraints. This is achieved by latching the
-- busy signal on an incoming request inside the thread (hw_task.vhd),
-- until an ack arrives from the command decoder.
-- The request_seen signal doubles as the acknowledge signal to the thread.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity command_decoder is
generic (
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_FIFO_DWIDTH : integer := 32;
C_BURSTLEN_WIDTH : integer := 12
);
port (
i_clk : in std_logic;
i_reset : in std_logic;
i_osif : in osif_task2os_t;
o_osif : out osif_os2task_t;
--o_step : out natural range 0 to C_MAX_MULTICYCLE_STEPS-1;
o_sw_request : out std_logic;
i_request_blocking : in std_logic;
i_release_blocking : in std_logic;
i_init_data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- bus_master interface
o_bm_my_addr : out std_logic_vector(0 to C_AWIDTH-1);
o_bm_target_addr : out std_logic_vector(0 to C_AWIDTH-1);
o_bm_read_req : out std_logic; -- single word
o_bm_write_req : out std_logic; -- single word
o_bm_burst_read_req : out std_logic; -- n x 64Bit burst
o_bm_burst_write_req : out std_logic; -- n x 64Bit burst
o_bm_burst_length : out std_logic_vector(0 to C_BURSTLEN_WIDTH-1); -- number of burst beats (n)
i_bm_busy : in std_logic;
i_bm_read_done : in std_logic;
i_bm_write_done : in std_logic;
-- slave registers interface
i_slv_busy : in std_logic;
i_slv_bus2osif_command : in std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
i_slv_bus2osif_data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
i_slv_bus2osif_shm : in std_logic_vector(0 to C_DWIDTH-1);
o_slv_osif2bus_command : out std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
o_slv_osif2bus_data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
o_slv_osif2bus_datax : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
o_slv_osif2bus_shm : out std_logic_vector(0 to C_DWIDTH-1);
o_hwthread_signature : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) ;
-- fifo manager interface
o_fifo_read_remove : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_wait : in std_logic;
o_fifo_write_add : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_wait : in std_logic;
-- fifo handles
i_fifo_read_handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
i_fifo_write_handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- yield/resume interface
i_resume : in std_logic;
i_yield : in std_logic; -- OS requests yield
o_yield : out std_logic; -- thread yields
o_saved_state_enc : out reconos_state_enc_t;
o_saved_step_enc : out reconos_step_enc_t;
i_resume_state_enc : in reconos_state_enc_t;
i_resume_step_enc : in reconos_step_enc_t
);
end command_decoder;
architecture behavioral of command_decoder is
signal step_enable : std_logic := '0';
signal step_clear : std_logic := '0';
signal step : natural range 0 to C_MAX_MULTICYCLE_STEPS-1 := 0;
signal blocking : std_logic := '1';
signal busy : std_logic := '0';
signal request_seen : std_logic := '0';
signal failure : std_logic := '0';
-- fifo routing
signal fifo_local : std_logic := '0';
begin
o_osif.step <= step;
o_osif.busy <= busy or i_slv_busy or i_bm_busy;-- or i_osif.request;
o_osif.blocking <= blocking;
o_osif.ack <= request_seen;
o_osif.req_yield <= i_yield;
o_osif.command <= i_slv_bus2osif_command;
o_saved_state_enc <= reconos_state_enc_t(i_osif.saved_state_enc);
o_saved_step_enc <= reconos_step_enc_t(TO_UNSIGNED(step, C_OSIF_STEP_ENC_WIDTH));
o_fifo_write_data <= i_osif.data;
retval_mux : process(i_osif, step,
i_slv_bus2osif_shm, i_slv_bus2osif_data,
i_init_data,
i_fifo_read_data,
i_fifo_read_wait,
i_fifo_write_wait)
begin
-- default assignment
o_osif.data <= X"AFFE1010"; -- for debugging purposes
o_osif.valid <= '0';
case i_osif.command is
when OSIF_CMD_READ =>
if step = 1 then
o_osif.data <= i_slv_bus2osif_shm;
o_osif.valid <= '1';
end if;
when OSIF_CMD_GET_INIT_DATA =>
if step = 1 then
o_osif.data <= i_init_data;
o_osif.valid <= '1';
end if;
when OSIF_CMD_MUTEX_LOCK =>
if step = 1 then
o_osif.data <= i_slv_bus2osif_data;
o_osif.valid <= '1';
end if;
when OSIF_CMD_MUTEX_TRYLOCK =>
if step = 1 then
o_osif.data <= i_slv_bus2osif_data;
o_osif.valid <= '1';
end if;
when OSIF_CMD_MBOX_GET =>
if step = 2 then
if fifo_local = '1' then
-- local hardware FIFO access
if i_fifo_read_wait = '1' or failure = '1' then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= i_fifo_read_data;
o_osif.valid <= '1';
end if;
else
-- global software FIFO access
if i_slv_bus2osif_data = C_RECONOS_FAILURE then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= i_slv_bus2osif_data;
o_osif.valid <= '1';
end if;
end if;
end if;
-- identical to MBOX_GET!
when OSIF_CMD_MBOX_TRYGET =>
if step = 2 then
if fifo_local = '1' then
-- local hardware FIFO access
if i_fifo_read_wait = '1' or failure = '1' then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= i_fifo_read_data;
o_osif.valid <= '1';
end if;
else
-- global software FIFO access
if i_slv_bus2osif_data = C_RECONOS_FAILURE then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= i_slv_bus2osif_data;
o_osif.valid <= '1';
end if;
end if;
end if;
when OSIF_CMD_MBOX_PUT =>
if step = 2 then
if fifo_local = '1' then
-- local hardware FIFO access
if i_fifo_write_wait = '1' or failure = '1' then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= C_RECONOS_SUCCESS;
o_osif.valid <= '1';
end if;
else
-- global software FIFO access
if i_slv_bus2osif_data = C_RECONOS_FAILURE then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= C_RECONOS_SUCCESS;
o_osif.valid <= '1';
end if;
end if;
end if;
when OSIF_CMD_MQ_SEND =>
if step = 2 then
if i_slv_bus2osif_data = C_RECONOS_FAILURE then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= C_RECONOS_SUCCESS;
o_osif.valid <= '1';
end if;
end if;
when OSIF_CMD_MQ_RECEIVE =>
if step = 2 then
if i_slv_bus2osif_data = C_RECONOS_FAILURE then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= i_slv_bus2osif_data;
o_osif.valid <= '1';
end if;
end if;
-- identical to MBOX_PUT!
when OSIF_CMD_MBOX_TRYPUT =>
if step = 2 then
if fifo_local = '1' then
-- local hardware FIFO access
if i_fifo_write_wait = '1' or failure = '1' then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= C_RECONOS_SUCCESS;
o_osif.valid <= '1';
end if;
else
-- global software FIFO access
if i_slv_bus2osif_data = C_RECONOS_FAILURE then
o_osif.data <= C_RECONOS_FAILURE;
o_osif.valid <= '0';
else
o_osif.data <= C_RECONOS_SUCCESS;
o_osif.valid <= '1';
end if;
end if;
end if;
when OSIF_CMD_THREAD_RESUME =>
if step = 1 then
if i_resume = '1' then
o_osif.data <= i_resume_state_enc & X"000000";
o_osif.valid <= '1';
else
o_osif.data <= (others => '0');
o_osif.valid <= '0';
end if;
end if;
when others => null;
end case;
end process;
sync_decode : process(i_clk, i_reset)
begin
if i_reset = '1' then
o_bm_my_addr <= (others => '0');
o_bm_target_addr <= (others => '0');
step <= 0;
o_bm_read_req <= '0';
o_bm_write_req <= '0';
o_bm_burst_read_req <= '0';
o_bm_burst_write_req <= '0';
o_bm_burst_length <= (others => '0');
o_slv_osif2bus_command <= (others => '0');
o_slv_osif2bus_data <= (others => '0');
o_slv_osif2bus_datax <= (others => '0');
o_slv_osif2bus_shm <= (others => '0');
o_sw_request <= '0';
o_fifo_read_remove <= '0';
o_fifo_write_add <= '0';
busy <= '0';
blocking <= '1';
request_seen <= '0';
failure <= '0';
fifo_local <= '0';
o_yield <= '0';
elsif rising_edge(i_clk) then
-- default signal assignments
o_bm_read_req <= '0';
o_bm_write_req <= '0';
o_bm_burst_read_req <= '0';
o_bm_burst_write_req <= '0';
o_sw_request <= '0';
o_fifo_read_remove <= '0';
o_fifo_write_add <= '0';
busy <= '0';
if i_osif.request = '0' and request_seen = '1' then
-- reset request_seen after request went away
request_seen <= '0';
elsif i_osif.request = '1' and request_seen = '0' then
-- mark request as seen
request_seen <= '1';
-- retain yield flag
o_yield <= i_osif.yield;
case i_osif.command is
----------
-- single memory read
----------
when OSIF_CMD_READ =>
case step is
when 0 =>
o_bm_read_req <= '1';
-- o_bm_my_addr <= C_BASEADDR;
o_bm_target_addr <= i_osif.data;
busy <= '1'; -- busy until read completion
step <= 1;
when 1 =>
-- o_osif.data <= i_slv_bus2osif_shm; -- this has to be done before step 1 (see retval_mux)
step <= 0; -- last step.
when others => null;
end case; -- CMD_READ
----------
-- single memory write
----------
when OSIF_CMD_WRITE =>
case step is
when 0 =>
-- o_bm_my_addr <= C_BASEADDR;
o_bm_target_addr <= i_osif.data;
step <= 1;
when 1 =>
o_slv_osif2bus_shm <= i_osif.data;
o_bm_write_req <= '1';
busy <= '1'; -- busy until write completion
step <= 0;
when others => null;
end case;
----------
-- burst memory read with specified length
----------
when OSIF_CMD_READ_BURST =>
case step is
when 0 =>
o_bm_my_addr <= i_osif.data;
step <= 1;
when 1 =>
o_bm_target_addr <= i_osif.data;
step <= 2;
when 2 =>
o_bm_burst_read_req <= '1';
o_bm_burst_length <= i_osif.data(C_OSIF_DATA_WIDTH-C_BURSTLEN_WIDTH to C_OSIF_DATA_WIDTH-1);
busy <= '1'; -- busy until read completion
step <= 0;
when others => null;
end case;
----------
-- burst memory write with specified length
----------
when OSIF_CMD_WRITE_BURST =>
case step is
when 0 =>
o_bm_my_addr <= i_osif.data;
step <= 1;
when 1 =>
o_bm_target_addr <= i_osif.data;
step <= 2;
when 2 =>
o_bm_burst_write_req <= '1';
o_bm_burst_length <= i_osif.data(C_OSIF_DATA_WIDTH-C_BURSTLEN_WIDTH to C_OSIF_DATA_WIDTH-1);
busy <= '1'; -- busy until write completion
step <= 0;
when others => null;
end case;
----------
-- get thread data
----------
when OSIF_CMD_GET_INIT_DATA =>
case step is
when 0 =>
-- data is put on o_osif.data in the retval mux above
-- so we don't need to do anything here
step <= 1;
when 1 =>
-- or here
step <= 0;
when others => null;
end case;
----------
-- mutex lock
----------
when OSIF_CMD_MUTEX_LOCK =>
case step is
when 0 =>
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
o_slv_osif2bus_datax <= (others => '0');
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
step <= 1;
when 1 =>
-- data is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
----------
-- mutex trylock
----------
when OSIF_CMD_MUTEX_TRYLOCK =>
case step is
when 0 =>
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
o_slv_osif2bus_datax <= (others => '0');
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
step <= 1;
when 1 =>
-- data is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
----------
-- condvar wait
----------
when OSIF_CMD_COND_WAIT =>
case step is
when 0 =>
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
o_slv_osif2bus_datax <= (others => '0');
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
step <= 1;
when 1 =>
-- data is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
----------
-- mbox get
-- in case of hardware FIFO access, this blocking call
-- does not use the 'busy' or 'blocking' signals, but
-- keeps looping inside the same multi-cycle step.
-- this is similar to polling, but since it is done
-- locally, it's not as bad.
-- because of the local hardware FIFO access,
-- this needs to be a two-cycle-command because we need to
-- wait one cycle to wait for the wait line to assert
-- after reading the last value. It also simplifies the
-- return value transmission
----------
when OSIF_CMD_MBOX_GET =>
case step is
when 0 =>
-- local hardware FIFO
if i_osif.data = i_fifo_read_handle then
fifo_local <= '1';
-- if read FIFO is available, read data from it
if i_fifo_read_wait = '0' then
o_fifo_read_remove <= '1';
step <= 1;
-- if FIFO is busy, keep trying
else
step <= 0;
end if;
else
-- global software FIFO
fifo_local <= '0';
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
o_slv_osif2bus_datax <= (others => '0');
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
step <= 2; -- skip step 1
end if;
when 1 => -- wait state for hardware FIFO access
step <= 2;
when 2 =>
fifo_local <= '0';
failure <= '0';
-- data is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
----------
-- mbox tryget
-- because of the local hardware FIFO access,
-- this needs to be a two-cycle-command because we need to
-- wait one cycle to wait for the wait line to assert
-- after reading the last value. It also simplifies the
-- return value transmission
----------
when OSIF_CMD_MBOX_TRYGET =>
case step is
when 0 =>
-- local hardware FIFO
if i_osif.data = i_fifo_read_handle then
fifo_local <= '1';
-- if read FIFO is available, read data from it
if i_fifo_read_wait = '0' then
o_fifo_read_remove <= '1';
step <= 1;
else
failure <= '1';
step <= 2; -- skip waiting
end if;
else
-- global software FIFO
fifo_local <= '0';
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
o_slv_osif2bus_datax <= (others => '0');
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
step <= 2; -- skip step 1
end if;
when 1 => -- wait state for hardware FIFO access
step <= 2;
when 2 =>
fifo_local <= '0';
failure <= '0';
-- data is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
----------
-- mbox put
-- in case of hardware FIFO access, this blocking call
-- does not use the 'busy' or 'blocking' signals, but
-- keeps looping inside the same multi-cycle step.
-- this is similar to polling, but since it is done
-- locally, it's not as bad
----------
when OSIF_CMD_MBOX_PUT =>
case step is
when 0 =>
if i_osif.data = i_fifo_write_handle then
-- local hardware FIFO access
fifo_local <= '1';
-- if FIFO is busy, keep trying
if i_fifo_write_wait = '1' then
step <= 0;
else
step <= 1;
end if;
else
-- global software FIFO access
fifo_local <= '0';
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
step <= 1;
end if;
when 1 =>
if fifo_local = '1' then
-- local hardware FIFO access
-- if FIFO is busy, keep trying
if i_fifo_write_wait = '0' then
o_fifo_write_add <= '1';
step <= 2;
else
step <= 1;
end if;
else
-- global software FIFO access
o_slv_osif2bus_datax <= i_osif.data;
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
step <= 2;
end if;
when 2 =>
fifo_local <= '0';
failure <= '0';
-- return value is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
-------
-- mq send
----------
when OSIF_CMD_MQ_SEND =>
case step is
when 0 =>
fifo_local <= '0';
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
step <= 1;
when 1 =>
o_slv_osif2bus_datax <= i_osif.data;
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
step <= 2;
when 2 =>
fifo_local <= '0';
failure <= '0';
-- return value is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
-------
-- mq receive
----------
when OSIF_CMD_MQ_RECEIVE =>
case step is
when 0 =>
fifo_local <= '0';
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
step <= 1;
when 1 =>
-- global software FIFO access
o_slv_osif2bus_datax <= i_osif.data;
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
step <= 2;
when 2 =>
fifo_local <= '0';
failure <= '0';
-- return value is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
----------
-- mbox tryput
----------
when OSIF_CMD_MBOX_TRYPUT =>
case step is
when 0 =>
if i_osif.data = i_fifo_write_handle then
-- local hardware FIFO access
fifo_local <= '1';
if i_fifo_write_wait = '1' then
failure <= '1';
step <= 2;
else
step <= 1;
end if;
else
-- global software FIFO access
fifo_local <= '0';
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
step <= 1;
end if;
when 1 =>
if fifo_local = '1' then
-- local hardware FIFO access
if i_fifo_write_wait = '0' then
o_fifo_write_add <= '1';
else
failure <= '1';
end if;
else
-- global software FIFO access
o_slv_osif2bus_datax <= i_osif.data;
o_sw_request <= '1';
busy <= '1';
blocking <= '1';
end if;
step <= 2;
when 2 =>
fifo_local <= '0';
failure <= '0';
-- return value is put on o_osif.data in the retval mux above
step <= 0;
when others => null;
end case;
----------
-- get thread resume state
----------
when OSIF_CMD_THREAD_RESUME =>
case step is
when 0 =>
-- data is put on o_osif.data in the retval mux above
-- so we don't need to do anything here
step <= 1;
when 1 =>
step <= 0;
if (i_resume = '1') then
-- block since we are always resuming in or after
-- a blocking call
blocking <= '1';
-- if we resume inside a multi-cycle command (step /= 0),
-- we need to insert a resume step for reaquiring handshake
-- between thread FSM and retval mux
if i_resume_step_enc /= "00" then
step <= C_STEP_RESUME;
end if;
end if;
when others => null;
end case;
----------
-- thread_yield
----------
when OSIF_CMD_THREAD_YIELD =>
if i_yield = '1' then
blocking <= '1';
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data; -- this is the encoded saved state
o_slv_osif2bus_datax <= (others => '0');
o_sw_request <= '1';
busy <= '1';
end if;
----------
-- other commands (all single-cycle and software-handled)
-- this includes:
-- OSIF_CMD_SEM_POST
-- OSIF_CMD_SEM_WAIT
-- OSIF_CMD_MUTEX_UNLOCK
-- OSIF_CMD_MUTEX_RELEASE
-- OSIF_CMD_COND_SIGNAL
-- OSIF_CMD_COND_BROADCAST
-- OSIF_CMD_THREAD_EXIT
-- OSIF_CMD_THREAD_DELAY
----------
when others => -- software-handled single-cycle requests do not need special handling
-- blocking?
if i_osif.command(C_OSIF_CMD_BLOCKING_BITPOS) = '1' then
blocking <= '1';
end if;
o_slv_osif2bus_command <= i_osif.command;
o_slv_osif2bus_data <= i_osif.data;
o_slv_osif2bus_datax <= (others => '0');
o_sw_request <= '1';
busy <= '1';
end case;
-- implement wait step for resuming
if step = C_STEP_RESUME then
step <= natural(TO_INTEGER(unsigned(i_resume_step_enc)));
end if;
end if; -- request = '1'
-- FIXME: check for races between i_request_blocking (from SW) and i_osif.request (from HW).
if i_request_blocking = '1' then
blocking <= '1';
elsif i_release_blocking = '1' then
blocking <= '0';
end if;
end if; -- reset
end process;
------------------------------------------------
-- get_signature: retrieve signature from hardware thread
-- and output it to DCR registers
--
-- NOTE: this works also (in fact, only) during a reset
-- reset needs to be high for several cycles in order for the signature
-- data to propagate through any synchronous bus macros. This is done
-- in osif_core which manages the thread reset
------------------------------------------------
get_signature : process( i_clk, i_reset )
begin
if rising_edge(i_clk) then
if i_reset = '1' then -- task is in reset state
o_hwthread_signature <= i_osif.data;
end if;
end if;
end process ; -- get_signature
end behavioral;
|
gpl-3.0
|
e5cbdda7d58458ef07739e4b2b2455bd
| 0.339339 | 5.366329 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/data/hw/src/hwt_data.vhd
| 1 | 15,078 |
--
-- threadA.vhd
-- measurement thread
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 18.02.2008
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2008.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hwt_data is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- external timebase
i_timeBase : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
);
end hwt_data;
architecture Behavioral of hwt_data is
-- timer address (FIXME: hardcoded!)
constant TIMER_ADDR : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"50004000";
-- ReconOS resources used by this thread
constant C_MB_TRANSFER : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_RESULT : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (
STATE_INIT, -- load configuration address
STATE_READ_SRC, -- load source address
STATE_READ_DST, -- load destination address
STATE_READ_BLKSIZE, -- load transfer size
STATE_WAIT, -- wait (not used)
STATE_READTIME_START, -- measure start time
STATE_READ_MBOX, -- read data from mbox
STATE_INC_ADDR,
STATE_READ_MEM_SINGLE, -- read data from memory (single word)
STATE_READ_MEM_BURST, -- read data from memory (burst)
STATE_READTIME_STOP,
STATE_WRITE_MBOX, -- write data to mbox
STATE_WRITE_MEM_SINGLE, -- write data to memory (single word)
STATE_WRITE_MEM_BURST, -- write data to memory (burst)
STATE_WRITETIME_STOP, -- measure stop time
STATE_POST_READTIME_1, -- post times
STATE_POST_READTIME_2,
STATE_POST_WRITETIME_1,
STATE_POST_WRITETIME_2,
STATE_EXIT
);
signal state : t_state := STATE_INIT;
-- address of data in main memory
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- o_RAMWE <= '0';
-- o_RAMData <= (others => '0');
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1; -- transfer 128 bytes at once
variable trans_counter : natural range 0 to 8192/4 - 1; -- transfer 4 bytes at once
-- addresses
variable conf_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable src_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable dst_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- timing values
variable readtime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable readtime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable writetime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
variable writetime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
variable burstlen_bytes : natural range 1 to 128;
variable burstlen_cycles : natural range 1 to 16;
variable bursts : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
src_address := (others => '0');
dst_address := (others => '0');
state <= STATE_INIT;
o_RAMWE <= '0';
o_RAMData <= (others => '0');
burst_counter := 0;
trans_counter := 0;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read init data (address of configuration struct)
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, conf_address);
if done then
state <= STATE_READ_SRC;
end if;
-- read source address (0 means mbox)
when STATE_READ_SRC =>
reconos_read(done, o_osif, i_osif, conf_address, src_address);
if done then
state <= STATE_READ_DST;
end if;
-- read destination address (0 means mbox)
when STATE_READ_DST =>
reconos_read(done, o_osif, i_osif, conf_address, dst_address);
if done then
state <= STATE_READ_BLKSIZE;
end if;
-- read block size (in bytes)
when STATE_READ_BLKSIZE =>
reconos_read(done, o_osif, i_osif, conf_address, block_size);
if done then
state <= STATE_WAIT;
end if;
-- wait
when STATE_WAIT =>
burst_counter := 0;
state <= STATE_READTIME_START;
-- get start time of burst transfer, decide on mechanism (single, mbox, burst)
when STATE_READTIME_START =>
readtime_1 := i_timeBase;
if src_address = X"0000_0000" then
-- read from mailbox
state <= STATE_READ_MBOX;
else
if block_size = 4 then
RAMAddr <= (others => '0');
state <= STATE_READ_MEM_SINGLE;
else
if block_size < 128 then
burstlen_bytes := conv_integer(block_size);
bursts <= 1;
else
burstlen_bytes := 128;
bursts := conv_integer(block_size)/8;
end if;
burstlen_cycles := burstlen_bytes/8;
state <= STATE_READ_MEM_BURST;
end if;
end if;
-- read single word into burst ram
when STATE_READ_MEM_SINGLE =>
reconos_thread_exit(o_osif, i_osif, X"0000_0001");
-- reconos_read_s(done, o_osif, i_osif, src_address, o_RAMData);
-- if done then
-- o_RAMWE <= '1';
-- state <= STATE_READTIME_STOP;
-- end if;
-- read data from main memory into local burst RAM.
when STATE_READ_MEM_BURST =>
reconos_thread_exit(o_osif, i_osif, X"0000_0002");
-- reconos_read_burst_l (done,
-- o_osif,
-- i_osif,
-- std_logic_vector(TO_UNSIGNED(burst_counter*burstlen_bytes, C_OSIF_DATA_WIDTH)),
-- src_address+(burst_counter*burstlen_bytes),
-- burstlen_cycles
-- );
-- if done then
-- if burst_counter = bursts - 1 then
-- trans_counter := 0;
-- RAMAddr <= (others => '0');
-- state <= STATE_READTIME_STOP;
-- else
-- burst_counter := burst_counter + 1;
-- end if;
-- end if;
-- read data from mbox into local burst RAM
when STATE_READ_MBOX =>
reconos_thread_exit(o_osif, i_osif, X"0000_0003");
-- o_RAMWE <= '0';
-- reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_TRANSFER, o_RAMData);
-- if done and success then
-- o_RAMWE <= '1';
-- if trans_counter = conv_integer(block_size)/4 - 1 then
-- burst_counter := 0;
-- state <= STATE_READTIME_STOP;
-- else
-- state <= STATE_INC_ADDR;
-- trans_counter := trans_counter + 1;
-- end if;
-- end if;
-- increment RAM address for writing to BRAM
when STATE_INC_ADDR =>
o_RAMWE <= '0';
RAMAddr <= RAMAddr + 1; -- note that this is delayed by one clock cycle
state <= STATE_READ_MBOX;
-- get stop time of burst transfer
when STATE_READTIME_STOP =>
o_RAMWE <= '0';
RAMAddr <= (others => '0');
readtime_2 := i_timeBase;
writetime_1 := readtime_2; -- nach der Messung ist vor der Messung :)
if dst_address = X"0000_0000" then
-- write from mailbox
state <= STATE_WRITE_MBOX;
else
if block_size = 4 then
RAMAddr <= (others => '0');
state <= STATE_WRITE_MEM_SINGLE;
else
if block_size < 128 then
burstlen_bytes := conv_integer(block_size);
bursts := 1;
else
burstlen_bytes := 128;
bursts := conv_integer(block_size)/8;
end if;
burstlen_cycles := burstlen_bytes/8;
state <= STATE_WRITE_MEM_BURST;
end if;
end if;
-- transfer data across mailbox
-- this state also hides the RAM access timing, since this is a multi-cycle
-- command, and the "data" parameter is only transferred in the second cycle.
when STATE_WRITE_MBOX =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_TRANSFER, i_RAMData);
if done and success then
if trans_counter = conv_integer(block_size)/4 - 1 then
state <= STATE_WRITETIME_STOP;
else
RAMAddr <= RAMAddr + 1;
trans_counter := trans_counter + 1;
end if;
end if;
-- write single word from burst ram to memory
when STATE_WRITE_MEM_SINGLE =>
reconos_write(done, o_osif, i_osif, dst_address, i_RAMData);
if done then
o_RAMWE <= '1';
state <= STATE_WRITETIME_STOP;
end if;
-- write data from burst RAM into main memory
when STATE_WRITE_MEM_BURST =>
reconos_write_burst_l (done,
o_osif,
i_osif,
std_logic_vector(TO_UNSIGNED(burst_counter*burstlen_bytes, C_OSIF_DATA_WIDTH)),
dst_address+(burst_counter*burstlen_bytes),
burstlen_cycles
);
if done then
if burst_counter = bursts - 1 then
trans_counter := 0;
RAMAddr <= (others => '0');
state <= STATE_READTIME_STOP;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- get stop time of FIFO transfer
when STATE_WRITETIME_STOP =>
writetime_2 := i_timeBase;
state <= STATE_POST_READTIME_1;
-- write read time to mailbox
when STATE_POST_READTIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_RESULT, readtime_1);
if done and success then
state <= STATE_POST_READTIME_2;
end if;
when STATE_POST_READTIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_RESULT, readtime_2);
if done and success then
state <= STATE_POST_WRITETIME_1;
end if;
-- write transfer time to mailbox
when STATE_POST_WRITETIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_RESULT, writetime_1);
if done and success then
state <= STATE_POST_WRITETIME_2;
end if;
when STATE_POST_WRITETIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_RESULT, writetime_2);
if done and success then
state <= STATE_EXIT;
end if;
when STATE_EXIT =>
reconos_thread_exit( o_osif, i_osif, X"0000_1111" );
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
74a83249ec471deefbc50e0c0c23bb31
| 0.456161 | 4.608191 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/v6_emac_v1_4.vhd
| 1 | 20,027 |
-------------------------------------------------------------------------------
-- Title : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : v6_emac_v1_4.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
-- Description: This wrapper file instantiates the full Virtex-6 Embedded
-- Tri-Mode Ethernet MAC (EMAC) primitive, where:
--
-- * all unused input ports on the primitive are tied to the
-- appropriate logic level;
--
-- * all unused output ports on the primitive are left
-- unconnected;
--
-- * the attributes are set based on the options selected
-- from CORE Generator;
--
-- * only used ports are connected to the ports of this
-- wrapper file.
--
-- This simplified wrapper should therefore be used as the
-- instantiation template for the EMAC primitive in customer
-- designs.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration for the primitive-level wrapper
--------------------------------------------------------------------------------
entity v6_emac_v1_4 is
port(
-- Client Receiver Interface
EMACCLIENTRXCLIENTCLKOUT : out std_logic;
CLIENTEMACRXCLIENTCLKIN : in std_logic;
EMACCLIENTRXD : out std_logic_vector(7 downto 0);
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXDVLDMSW : out std_logic;
EMACCLIENTRXGOODFRAME : out std_logic;
EMACCLIENTRXBADFRAME : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client Transmitter Interface
EMACCLIENTTXCLIENTCLKOUT : out std_logic;
CLIENTEMACTXCLIENTCLKIN : in std_logic;
CLIENTEMACTXD : in std_logic_vector(7 downto 0);
CLIENTEMACTXDVLD : in std_logic;
CLIENTEMACTXDVLDMSW : in std_logic;
EMACCLIENTTXACK : out std_logic;
CLIENTEMACTXFIRSTBYTE : in std_logic;
CLIENTEMACTXUNDERRUN : in std_logic;
EMACCLIENTTXCOLLISION : out std_logic;
EMACCLIENTTXRETRANSMIT : out std_logic;
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC Control Interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- Clock Signals
GTX_CLK : in std_logic;
PHYEMACTXGMIIMIICLKIN : in std_logic;
EMACPHYTXGMIIMIICLKOUT : out std_logic;
-- SGMII Interface
RXDATA : in std_logic_vector(7 downto 0);
TXDATA : out std_logic_vector(7 downto 0);
MMCM_LOCKED : in std_logic;
AN_INTERRUPT : out std_logic;
SIGNAL_DETECT : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
ENCOMMAALIGN : out std_logic;
LOOPBACKMSB : out std_logic;
MGTRXRESET : out std_logic;
MGTTXRESET : out std_logic;
POWERDOWN : out std_logic;
SYNCACQSTATUS : out std_logic;
RXCLKCORCNT : in std_logic_vector(2 downto 0);
RXBUFSTATUS : in std_logic;
RXCHARISCOMMA : in std_logic;
RXCHARISK : in std_logic;
RXDISPERR : in std_logic;
RXNOTINTABLE : in std_logic;
RXREALIGN : in std_logic;
RXRUNDISP : in std_logic;
TXBUFERR : in std_logic;
TXCHARDISPMODE : out std_logic;
TXCHARDISPVAL : out std_logic;
TXCHARISK : out std_logic;
-- Asynchronous Reset
RESET : in std_logic
);
end v6_emac_v1_4;
architecture WRAPPER of v6_emac_v1_4 is
----------------------------------------------------------------------------
-- Attribute declarations
----------------------------------------------------------------------------
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of WRAPPER : architecture is "v6_emac_v1_4, Coregen 12.1";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of WRAPPER : architecture is "v6_emac_v1_4,v6_emac_v1_4,{c_has_mii=false,c_has_gmii=false,c_has_rgmii_v1_3=false,c_has_rgmii_v2_0=false,c_has_sgmii=true,c_has_gpcs=false,c_tri_speed=false,c_speed_10=false,c_speed_100=false,c_speed_1000=true,c_has_host=false,c_has_dcr=false,c_has_mdio=false,c_client_16=false,c_add_filter=false,c_has_clock_enable=false,c_serial_mode_switch_en=false,c_overclocking_rate_2000mbps=false,c_overclocking_rate_2500mbps=false,}";
-- Configure the PCS/PMA logic
-- PCS/PMA reset is not asserted
constant EMAC_PHYRESET : boolean := FALSE;
-- PCS/PMA Auto-Negotiation is not enabled
constant EMAC_PHYINITAUTONEG_ENABLE : boolean := TRUE;
-- PCS/PMA isolate is not enabled
constant EMAC_PHYISOLATE : boolean := FALSE;
-- PCS/PMA is not held in powerdown mode
constant EMAC_PHYPOWERDOWN : boolean := FALSE;
-- PCS/PMA loopback is not enabled
constant EMAC_PHYLOOPBACKMSB : boolean := FALSE;
-- GT loopback is not enabled
constant EMAC_GTLOOPBACK : boolean := FALSE;
-- Do not allow transmission without having established a valid link
constant EMAC_UNIDIRECTION_ENABLE : boolean := FALSE;
constant EMAC_LINKTIMERVAL : bit_vector := x"032";
-- Do not ignore the MDIO broadcast address
constant EMAC_MDIO_IGNORE_PHYADZERO : boolean := FALSE;
-- Configure the EMAC operating mode
-- MDIO is enabled
constant EMAC_MDIO_ENABLE : boolean := TRUE;
-- Speed is defaulted to 1000 Mb/s
constant EMAC_SPEED_LSB : boolean := FALSE;
constant EMAC_SPEED_MSB : boolean := TRUE;
-- Clock Enable advanced clocking is not in use
constant EMAC_USECLKEN : boolean := FALSE;
-- Byte PHY advanced clocking is not supported. Do not modify.
constant EMAC_BYTEPHY : boolean := FALSE;
-- RGMII physical interface is not in use
constant EMAC_RGMII_ENABLE : boolean := FALSE;
-- SGMII physical interface is in use
constant EMAC_SGMII_ENABLE : boolean := TRUE;
constant EMAC_1000BASEX_ENABLE : boolean := FALSE;
-- The host interface is not enabled
constant EMAC_HOST_ENABLE : boolean := FALSE;
-- The Tx-side 8-bit client data interface is used
constant EMAC_TX16BITCLIENT_ENABLE : boolean := FALSE;
-- The Rx-side 8-bit client data interface is used
constant EMAC_RX16BITCLIENT_ENABLE : boolean := FALSE;
-- The address filter is not enabled
constant EMAC_ADDRFILTER_ENABLE : boolean := FALSE;
-- EMAC configuration defaults
-- Rx Length/Type checking enabled
constant EMAC_LTCHECK_DISABLE : boolean := FALSE;
-- Rx control frame length checking is enabled
constant EMAC_CTRLLENCHECK_DISABLE : boolean := FALSE;
-- Rx flow control is not enabled
constant EMAC_RXFLOWCTRL_ENABLE : boolean := FALSE;
-- Tx flow control is not enabled
constant EMAC_TXFLOWCTRL_ENABLE : boolean := FALSE;
-- Transmitter is not held in reset
constant EMAC_TXRESET : boolean := FALSE;
-- Transmitter Jumbo frames are not enabled
constant EMAC_TXJUMBOFRAME_ENABLE : boolean := FALSE;
-- Transmitter in-band FCS is not enabled
constant EMAC_TXINBANDFCS_ENABLE : boolean := FALSE;
-- Transmitter is enabled
constant EMAC_TX_ENABLE : boolean := TRUE;
-- Transmitter VLAN frames are not enabled
constant EMAC_TXVLAN_ENABLE : boolean := FALSE;
-- Transmitter full-duplex mode is enabled
constant EMAC_TXHALFDUPLEX : boolean := FALSE;
-- Transmitter IFG Adjust is not enabled
constant EMAC_TXIFGADJUST_ENABLE : boolean := FALSE;
-- Receiver is not held in reset
constant EMAC_RXRESET : boolean := FALSE;
-- Receiver Jumbo frames are not enabled
constant EMAC_RXJUMBOFRAME_ENABLE : boolean := FALSE;
-- Receiver in-band FCS is not enabled
constant EMAC_RXINBANDFCS_ENABLE : boolean := FALSE;
-- Receiver is enabled
constant EMAC_RX_ENABLE : boolean := TRUE;
-- Receiver VLAN frames are not enabled
constant EMAC_RXVLAN_ENABLE : boolean := FALSE;
-- Receiver full-duplex mode is enabled
constant EMAC_RXHALFDUPLEX : boolean := FALSE;
-- Configure the EMAC addressing
-- Set the PAUSE address default
constant EMAC_PAUSEADDR : bit_vector := x"FFEEDDCCBBAA";
-- Do not set the unicast address (address filter is unused)
constant EMAC_UNICASTADDR : bit_vector := x"000000000000";
-- Do not set the DCR base address (DCR is unused)
constant EMAC_DCRBASEADDR : bit_vector := X"00";
----------------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------------
signal gnd_v48_i : std_logic_vector(47 downto 0);
signal client_rx_data_i : std_logic_vector(15 downto 0);
signal client_tx_data_i : std_logic_vector(15 downto 0);
signal client_tx_data_valid_i : std_logic;
signal client_tx_data_valid_msb_i : std_logic;
signal rxbufstatus_i : std_logic_vector(1 downto 0);
----------------------------------------------------------------------------
-- Main body of code
----------------------------------------------------------------------------
begin
gnd_v48_i <= "000000000000000000000000000000000000000000000000";
rxbufstatus_i <= RXBUFSTATUS & '0';
-- Use the 8-bit client data interface
EMACCLIENTRXD <= client_rx_data_i(7 downto 0);
client_tx_data_i <= "00000000" & CLIENTEMACTXD after 4 ns;
client_tx_data_valid_i <= CLIENTEMACTXDVLD after 4 ns;
client_tx_data_valid_msb_i <= '0';
-- Instantiate the Virtex-6 Embedded Tri-Mode Ethernet MAC
v6_emac : TEMAC_SINGLE
generic map (
EMAC_1000BASEX_ENABLE => EMAC_1000BASEX_ENABLE,
EMAC_ADDRFILTER_ENABLE => EMAC_ADDRFILTER_ENABLE,
EMAC_BYTEPHY => EMAC_BYTEPHY,
EMAC_DCRBASEADDR => EMAC_DCRBASEADDR,
EMAC_GTLOOPBACK => EMAC_GTLOOPBACK,
EMAC_HOST_ENABLE => EMAC_HOST_ENABLE,
EMAC_LINKTIMERVAL => EMAC_LINKTIMERVAL(3 to 11),
EMAC_LTCHECK_DISABLE => EMAC_LTCHECK_DISABLE,
EMAC_MDIO_ENABLE => EMAC_MDIO_ENABLE,
EMAC_PAUSEADDR => EMAC_PAUSEADDR,
EMAC_PHYINITAUTONEG_ENABLE => EMAC_PHYINITAUTONEG_ENABLE,
EMAC_PHYISOLATE => EMAC_PHYISOLATE,
EMAC_PHYLOOPBACKMSB => EMAC_PHYLOOPBACKMSB,
EMAC_PHYPOWERDOWN => EMAC_PHYPOWERDOWN,
EMAC_PHYRESET => EMAC_PHYRESET,
EMAC_RGMII_ENABLE => EMAC_RGMII_ENABLE,
EMAC_RX16BITCLIENT_ENABLE => EMAC_RX16BITCLIENT_ENABLE,
EMAC_RXFLOWCTRL_ENABLE => EMAC_RXFLOWCTRL_ENABLE,
EMAC_RXHALFDUPLEX => EMAC_RXHALFDUPLEX,
EMAC_RXINBANDFCS_ENABLE => EMAC_RXINBANDFCS_ENABLE,
EMAC_RXJUMBOFRAME_ENABLE => EMAC_RXJUMBOFRAME_ENABLE,
EMAC_RXRESET => EMAC_RXRESET,
EMAC_RXVLAN_ENABLE => EMAC_RXVLAN_ENABLE,
EMAC_RX_ENABLE => EMAC_RX_ENABLE,
EMAC_SGMII_ENABLE => EMAC_SGMII_ENABLE,
EMAC_SPEED_LSB => EMAC_SPEED_LSB,
EMAC_SPEED_MSB => EMAC_SPEED_MSB,
EMAC_TX16BITCLIENT_ENABLE => EMAC_TX16BITCLIENT_ENABLE,
EMAC_TXFLOWCTRL_ENABLE => EMAC_TXFLOWCTRL_ENABLE,
EMAC_TXHALFDUPLEX => EMAC_TXHALFDUPLEX,
EMAC_TXIFGADJUST_ENABLE => EMAC_TXIFGADJUST_ENABLE,
EMAC_TXINBANDFCS_ENABLE => EMAC_TXINBANDFCS_ENABLE,
EMAC_TXJUMBOFRAME_ENABLE => EMAC_TXJUMBOFRAME_ENABLE,
EMAC_TXRESET => EMAC_TXRESET,
EMAC_TXVLAN_ENABLE => EMAC_TXVLAN_ENABLE,
EMAC_TX_ENABLE => EMAC_TX_ENABLE,
EMAC_UNICASTADDR => EMAC_UNICASTADDR,
EMAC_UNIDIRECTION_ENABLE => EMAC_UNIDIRECTION_ENABLE,
EMAC_USECLKEN => EMAC_USECLKEN,
EMAC_MDIO_IGNORE_PHYADZERO => EMAC_MDIO_IGNORE_PHYADZERO,
EMAC_CTRLLENCHECK_DISABLE => EMAC_CTRLLENCHECK_DISABLE
)
port map (
RESET => RESET,
EMACCLIENTRXCLIENTCLKOUT => EMACCLIENTRXCLIENTCLKOUT,
CLIENTEMACRXCLIENTCLKIN => CLIENTEMACRXCLIENTCLKIN,
EMACCLIENTRXD => client_rx_data_i,
EMACCLIENTRXDVLD => EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW => EMACCLIENTRXDVLDMSW,
EMACCLIENTRXGOODFRAME => EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME => EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP => EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS => EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD => EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD => EMACCLIENTRXSTATSBYTEVLD,
EMACCLIENTTXCLIENTCLKOUT => EMACCLIENTTXCLIENTCLKOUT,
CLIENTEMACTXCLIENTCLKIN => CLIENTEMACTXCLIENTCLKIN,
CLIENTEMACTXD => client_tx_data_i,
CLIENTEMACTXDVLD => client_tx_data_valid_i,
CLIENTEMACTXDVLDMSW => client_tx_data_valid_msb_i,
EMACCLIENTTXACK => EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE => CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN => CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION => EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT => EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY => CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS => EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD => EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD => EMACCLIENTTXSTATSBYTEVLD,
CLIENTEMACPAUSEREQ => CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL => CLIENTEMACPAUSEVAL,
PHYEMACGTXCLK => GTX_CLK,
PHYEMACTXGMIIMIICLKIN => PHYEMACTXGMIIMIICLKIN,
EMACPHYTXGMIIMIICLKOUT => EMACPHYTXGMIIMIICLKOUT,
PHYEMACRXCLK => '0',
PHYEMACMIITXCLK => '0',
PHYEMACRXD => RXDATA,
PHYEMACRXDV => RXREALIGN,
PHYEMACRXER => '0',
EMACPHYTXCLK => open,
EMACPHYTXD => TXDATA,
EMACPHYTXEN => open,
EMACPHYTXER => open,
PHYEMACCOL => '0',
PHYEMACCRS => '0',
CLIENTEMACDCMLOCKED => MMCM_LOCKED,
EMACCLIENTANINTERRUPT => AN_INTERRUPT,
PHYEMACSIGNALDET => SIGNAL_DETECT,
PHYEMACPHYAD => PHYAD,
EMACPHYENCOMMAALIGN => ENCOMMAALIGN,
EMACPHYLOOPBACKMSB => LOOPBACKMSB,
EMACPHYMGTRXRESET => MGTRXRESET,
EMACPHYMGTTXRESET => MGTTXRESET,
EMACPHYPOWERDOWN => POWERDOWN,
EMACPHYSYNCACQSTATUS => SYNCACQSTATUS,
PHYEMACRXCLKCORCNT => RXCLKCORCNT,
PHYEMACRXBUFSTATUS => rxbufstatus_i,
PHYEMACRXCHARISCOMMA => RXCHARISCOMMA,
PHYEMACRXCHARISK => RXCHARISK,
PHYEMACRXDISPERR => RXDISPERR,
PHYEMACRXNOTINTABLE => RXNOTINTABLE,
PHYEMACRXRUNDISP => RXRUNDISP,
PHYEMACTXBUFERR => TXBUFERR,
EMACPHYTXCHARDISPMODE => TXCHARDISPMODE,
EMACPHYTXCHARDISPVAL => TXCHARDISPVAL,
EMACPHYTXCHARISK => TXCHARISK,
EMACPHYMCLKOUT => open,
PHYEMACMCLKIN => '0',
PHYEMACMDIN => '1',
EMACPHYMDOUT => open,
EMACPHYMDTRI => open,
EMACSPEEDIS10100 => open,
HOSTCLK => '0',
HOSTOPCODE => gnd_v48_i(1 downto 0),
HOSTREQ => '0',
HOSTMIIMSEL => '0',
HOSTADDR => gnd_v48_i(9 downto 0),
HOSTWRDATA => gnd_v48_i(31 downto 0),
HOSTMIIMRDY => open,
HOSTRDDATA => open,
DCREMACCLK => '0',
DCREMACABUS => gnd_v48_i(9 downto 0),
DCREMACREAD => '0',
DCREMACWRITE => '0',
DCREMACDBUS => gnd_v48_i(31 downto 0),
EMACDCRACK => open,
EMACDCRDBUS => open,
DCREMACENABLE => '0',
DCRHOSTDONEIR => open
);
end WRAPPER;
|
gpl-3.0
|
2ecdf76ecd1853cecdaa7155afd13183
| 0.582414 | 4.762663 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/user_processes/uf_prediction.vhd
| 1 | 16,541 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : P R E D I C T I O N
--
--
-- The particles are loaded into the local RAM by the Framework.
-- The 8kb local RAM is filled with as many particles as possible.
-- There will not be any space between the particles.
--
-- The user of the framework knows how a particle is defined and
-- he defines here, how the next state is going to be predicted.
-- In the end the user has to overwrite every particle with the
-- sampled particle.
--
-- If this has be done for every particle, the finshed signal
-- has to be set to '1'. A new run of the prediction will be
-- started if new particles are loaded to the local RAM and
-- the signal particles_loaded is equal to '1'.
--
-- Because this function depends on parameter, additional
-- parameter can be given to the framework, which copies
-- them into the first 128 byte of the local RAM.
--
------------------------------------------------------------------------------------
entity uf_prediction is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the prediction user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- size of one particle
particle_size : in integer;
-- if every particle is sampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_prediction;
architecture Behavioral of uf_prediction is
component pseudo_random is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
load : in STD_LOGIC;
seed : in STD_LOGIC_VECTOR(31 downto 0);
pseudoR : out STD_LOGIC_VECTOR(31 downto 0));
end component;
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- factors for prediction fucntion
constant A1: integer := 2;
constant A2: integer := -1;
constant B0: integer := 1;
-- local RAM read/write address
signal local_ram_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal particle_start_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- signals for new values
signal x_new : integer := 0;
signal y_new : integer := 0;
signal s_new : integer := 0;
-- particle data
signal x : integer := 0;
signal y : integer := 0;
signal s : integer := 0;
signal x_old : integer := 0;
signal y_old : integer := 0;
signal s_old : integer := 0;
signal x0 : integer := -1;
signal y0 : integer := -1;
-- parameters
signal SIZE_X : integer := 480;
signal SIZE_Y : integer := 360;
signal TRANS_X_STD : integer := 16384;
signal TRANS_Y_STD : integer := 8192;
signal TRANS_S_STD : integer := 16;
-- temporary signals
signal tmp1 : integer := 0;
signal tmp2 : integer := 0;
signal tmp3 : integer := 0;
signal tmp4 : integer := 0;
signal tmp5 : integer := 0;
signal tmp6 : integer := 0;
-- states
type t_state is (STATE_INIT,
STATE_LOAD_PARAMETER_1, STATE_LOAD_PARAMETER_2, STATE_LOAD_SIZE_X,
STATE_LOAD_SIZE_Y, STATE_LOAD_TRANS_X_STD, STATE_LOAD_TRANS_Y_STD,
STATE_LOAD_TRANS_S_STD, STATE_SAMPLING, STATE_LOAD_PARTICLE_DECISION,
STATE_LOAD_PARTICLE_1, STATE_LOAD_PARTICLE_2,
STATE_LOAD_X, STATE_LOAD_Y, STATE_LOAD_S,
STATE_LOAD_XP, STATE_LOAD_YP, STATE_LOAD_YP_2, STATE_LOAD_SP,
STATE_LOAD_SP_2, STATE_LOAD_X0, STATE_LOAD_Y0,
STATE_CALCULATE_NEW_DATA_1, STATE_CALCULATE_NEW_DATA_2, STATE_CALCULATE_NEW_DATA_3,
STATE_CALCULATE_NEW_DATA_4, STATE_CALCULATE_NEW_DATA_5, STATE_CALCULATE_NEW_DATA_6,
STATE_CALCULATE_NEW_DATA_7, STATE_WRITE_X, STATE_WRITE_Y, STATE_WRITE_S,
STATE_WRITE_XP, STATE_WRITE_YP, STATE_WRITE_SP,
STATE_FINISH);
-- current state
signal state : t_state := STATE_INIT;
-- needed for pseudo random entity
signal enable_pseudo : std_logic := '0';
signal load : std_logic := '0';
signal seed : std_logic_vector(31 downto 0) := (others => '0');
signal pseudoR : std_logic_vector(31 downto 0) := (others => '0');
-- pseudo number as integer;
signal pseudo : integer := 0;
begin
pseudo_r : pseudo_random
port map (reset=>reset, clk=>clk, enable=>enable_pseudo, load=>load, seed=>seed, pseudoR=>pseudoR);
-- burst ram interface
o_RAMClk <= clk;
state_proc : process(clk, reset)
begin
if (reset = '1') then
seed <= X"7A3E0426";
load <= '1';
enable_pseudo <= '1';
state <= STATE_INIT;
finished <= '0';
x0 <= -1;
elsif rising_edge(clk) then
enable_pseudo <= enable;
load <= '0';
if init = '1' then
state <= STATE_INIT;
finished <= '0';
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
o_RAMAddr <= (others => '0');
elsif enable = '1' then
case state is
--! init data
when STATE_INIT =>
local_ram_address <= (others => '0');
counter <= 0;
finished <= '0';
o_RAMWE <= '0';
if (particles_loaded = '1') then
-- TODO: C H A N G E !!! (3 of 3)
-- CHANGE BACK !!! (2 of 2)
state <= STATE_LOAD_PARAMETER_1;
--state <= STATE_SAMPLING;
end if;
--! load parameter 1/2
when STATE_LOAD_PARAMETER_1 =>
o_RAMWE <= '0';
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_PARAMETER_2;
--! load parameter 2/2
when STATE_LOAD_PARAMETER_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_SIZE_X;
--! load parameter SIZE_X
when STATE_LOAD_SIZE_X =>
SIZE_X <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_SIZE_Y;
--! load parameter SIZE_Y
when STATE_LOAD_SIZE_Y =>
SIZE_Y <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_TRANS_X_STD;
--! load parameter TRANS_X_STD
when STATE_LOAD_TRANS_X_STD =>
TRANS_X_STD <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_TRANS_Y_STD;
--! load parameter TRANS_Y_STD
when STATE_LOAD_TRANS_Y_STD =>
TRANS_Y_STD <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_LOAD_TRANS_S_STD;
--! load parameter TRANS_S_STD
when STATE_LOAD_TRANS_S_STD =>
TRANS_S_STD <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_SAMPLING;
when STATE_SAMPLING =>
-- first 32 are saved for parameter, the 33th is the first weight
-- => 33 - the first x value
local_ram_address <= "000000100001";
particle_start_address <= "000000100001";
o_RAMWE <= '0';
finished <= '0';
counter <= 0;
--x0 <= -1;
state <= STATE_LOAD_PARTICLE_DECISION;
--! decision if another particle has to be sampled
when STATE_LOAD_PARTICLE_DECISION =>
o_RAMWE <= '0';
if (counter < number_of_particles) then
state <= STATE_LOAD_PARTICLE_1;
local_ram_address <= particle_start_address;
else
state <= STATE_FINISH;
end if;
--! load particle data 1/2
when STATE_LOAD_PARTICLE_1 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_PARTICLE_2;
--! load particle data 2/2
when STATE_LOAD_PARTICLE_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_X;
--! load particle data: x
when STATE_LOAD_X =>
x <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_Y;
--! load particle data: y
when STATE_LOAD_Y =>
y <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_S;
--! load particle data: s
when STATE_LOAD_S =>
s <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
pseudo <= TO_INTEGER(SIGNED(pseudoR));
state <= STATE_LOAD_XP;
--! load particle data: xp
when STATE_LOAD_XP =>
x_old <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
pseudo <= pseudo / 16;
state <= STATE_LOAD_YP;
--! load particle data: yp
when STATE_LOAD_YP =>
y_old <= TO_INTEGER(SIGNED(i_RAMData));
pseudo <= TO_INTEGER(SIGNED(pseudoR));
--tmp2 <= pseudo mod 16384;
----tmp2 <= pseudo mod 65536;
tmp2 <= pseudo mod 32768;
state <= STATE_LOAD_YP_2;
--! load particle data: yp
when STATE_LOAD_YP_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
--tmp2 <= tmp2 - 8192;
----tmp2 <= tmp2 - 32768;
tmp2 <= tmp2 - 16384;
state <= STATE_LOAD_SP;
--! load particle data: sp
when STATE_LOAD_SP =>
s_old <= TO_INTEGER(SIGNED(i_RAMData));
pseudo <= TO_INTEGER(SIGNED(pseudoR));
----tmp4 <= pseudo mod 8192;
tmp4 <= pseudo mod 32768;
--tmp4 <= pseudo mod 16384;
state <= STATE_LOAD_SP_2;
--! load particle data: sp
when STATE_LOAD_SP_2 =>
----tmp4 <= tmp4 - 4096;
tmp4 <= tmp4 - 16384;
--tmp4 <= tmp4 - 8192;
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
if (x0 > -1 ) then
-- x0, y0 loaded before
state <= STATE_CALCULATE_NEW_DATA_1;
else
-- x0, y0 not loaded yet
state <= STATE_LOAD_X0;
end if;
--! load particle data: x0
when STATE_LOAD_X0 =>
x0 <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_LOAD_Y0;
--! load particle data: y0
when STATE_LOAD_Y0 =>
y0 <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_CALCULATE_NEW_DATA_1;
--! calculate new data (1/7)
--
-- x_new = A1 * (x - x0) + A2 * (x_old - x0)
-- + B0 * pseudo_gaussian (TRANS_X_STD) + p->x0;
--
-- y_new and s_new are calculated in a similar way
-- this equation is splitted up into four states
--
-- A 6th and 7th state is used for correction
--
when STATE_CALCULATE_NEW_DATA_1 =>
-- calculate new x
x_new <= x - x0;
tmp1 <= x_old - x0;
--tmp2 <= (pseudo mod 16384) - 8192; -- calculated with different pseudonumber
-- calcualte new y
y_new <= y - y0;
tmp3 <= y_old - y0;
--tmp4 <= (pseudo mod 8192) - 4096; -- calculated with different pseudonumber
-- calculate new s
s_new <= s - GRANULARITY;
tmp5 <= s_old - GRANULARITY;
tmp6 <= pseudo mod 16;
--tmp6 <= pseudo mod 64;
state <= STATE_CALCULATE_NEW_DATA_2;
--! calculate new data (2/7)
when STATE_CALCULATE_NEW_DATA_2 =>
tmp6 <= tmp6 - 8;
--tmp6 <= tmp6 - 32;
state <= STATE_CALCULATE_NEW_DATA_3;
--! calculate new data (3/7)
when STATE_CALCULATE_NEW_DATA_3 =>
-- calculate new x
x_new <= A1 * x_new;
tmp1 <= A2 * tmp1;
tmp2 <= - B0 * tmp2;
-- calculate new y
y_new <= A1 * y_new;
tmp3 <= A2 * tmp3;
tmp4 <= B0 * tmp4;
-- calculate new s
s_new <= A1 * s_new;
tmp5 <= A2 * tmp5;
tmp6 <= B0 * tmp6;
state <= STATE_CALCULATE_NEW_DATA_4;
--! calculate new data (4/7)
when STATE_CALCULATE_NEW_DATA_4 =>
-- calcualte new x
x_new <= x_new + tmp1;
tmp2 <= tmp2 + x0;
-- calcualte new y
y_new <= y_new + tmp3;
tmp4 <= tmp4 + y0;
-- calcualte new s
s_new <= s_new + tmp5;
tmp6 <= tmp6 + GRANULARITY;
state <= STATE_CALCULATE_NEW_DATA_5;
--! calculate new data (5/7)
when STATE_CALCULATE_NEW_DATA_5 =>
-- calculate new x
x_new <= x_new + tmp2;
-- calculate new y
y_new <= y_new + tmp4;
-- calculate new s
s_new <= s_new + tmp6;
state <= STATE_CALCULATE_NEW_DATA_6;
--! calculate new data (6/7): correction
when STATE_CALCULATE_NEW_DATA_6 =>
-- correct new x
if (x_new < 0) then
x_new <= 0;
elsif ((SIZE_X * GRANULARITY) <= x_new) then
x_new <= SIZE_X * GRANULARITY;
end if;
-- correct new y
if (y_new < 0) then
y_new <= 0;
elsif ((SIZE_Y * GRANULARITY) <= y_new) then
y_new <= SIZE_Y * GRANULARITY;
end if;
-- correct new s
if (s_new < 0) then
s_new <= 0;
elsif (s_new <= (GRANULARITY / 8)) then
s_new <= GRANULARITY / 8;
elsif ((8*GRANULARITY) <= s_new) then
s_new <= 8 * GRANULARITY;
end if;
state <= STATE_CALCULATE_NEW_DATA_7;
--! calculate new data (7/7): correction
when STATE_CALCULATE_NEW_DATA_7 =>
-- correct new x
if (x_new = (SIZE_X * GRANULARITY)) then
x_new <= x_new - 1;
end if;
-- correct new y
if (y_new = (SIZE_Y * GRANULARITY)) then
y_new <= y_new - 1;
end if;
state <= STATE_WRITE_X;
--! write sampled particle: x
when STATE_WRITE_X =>
o_RAMWE <= '1';
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(x_new, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address;
state <= STATE_WRITE_Y;
--! write sampled particle: y
when STATE_WRITE_Y =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(y_new, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 1;
state <= STATE_WRITE_S;
--! write sampled particle: s
when STATE_WRITE_S =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(s_new, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 2;
state <= STATE_WRITE_XP;
--! write sampled particle: xp
when STATE_WRITE_XP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(x, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 3;
state <= STATE_WRITE_YP;
--! write sampled particle: yp
when STATE_WRITE_YP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(y, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 4;
state <= STATE_WRITE_SP;
--! write sampled particle: sp
when STATE_WRITE_SP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(s, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 5;
particle_start_address <= particle_start_address + particle_size;
counter <= counter + 1;
state <= STATE_LOAD_PARTICLE_DECISION;
-- write finished signal
when STATE_FINISH =>
o_RAMWE <= '0';
finished <= '1';
if (particles_loaded = '1') then
state <= STATE_SAMPLING;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
e24450352e441843dfc5d8f2c33f2653
| 0.546823 | 3.443889 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lipif_mst_pipeliner.vhd
| 1 | 5,772 |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_mst_pipeliner
-- Architectures: lipif_mst_pipeliner_rtl
-- Description:
--
-- Dependencies:
--
-- Revision:
-- 25.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity lipif_mst_pipeliner is
generic (
C_NUM_WIDTH : integer := 5
);
port(
clk : in std_logic;
reset : in std_logic;
xfer_num_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
xfer_adv_i : in std_logic;
xfer_nxt_i : in std_logic;
xfer_req_i : in std_logic;
xfer_ack_i : in std_logic;
xfer_rdy_o : out std_logic;
prim_valid_o : out std_logic;
prim_last_o : out std_logic;
prim_ack_o : out std_logic;
prim_nburst_o : out std_logic;
pipe_nburst_o : out std_logic
);
end lipif_mst_pipeliner;
architecture lipif_mst_pipeliner_rtl of lipif_mst_pipeliner is
signal num_prim : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal num_prim_n : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal num_sec : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal num_sec_n : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal num_tri : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal xfer_last : std_logic;
signal xfer_last_n : std_logic;
signal xfer_comp : std_logic;
signal valid_prim : std_logic;
signal valid_sec : std_logic;
signal valid_tri : std_logic;
signal ack_prim : std_logic;
signal ack_sec : std_logic;
begin
-- Connect ports to internal signals
xfer_rdy_o <= not valid_tri;
xfer_comp <= xfer_nxt_i;
prim_valid_o <= valid_prim;
prim_last_o <= xfer_last;
prim_ack_o <= ack_prim;
-- Next xfer last state calculated from next value of primary burst counter
xfer_last_n <= '1' when (num_prim_n(C_NUM_WIDTH-1 downto 1)=0) else '0';
-- Pipelined next burst signal should only be asserted if a transfer is actually pipelined
-- Don't need to check for a new transfer being pipelined this cycle: it can't have been
-- acknowledged yet!
pipe_nburst_o <= '0' when (num_sec_n(C_NUM_WIDTH-1 downto 1)=0) else valid_sec;
prim_nburst_o <= not xfer_last_n;
-- Generate next counts for primary and secondary stages
process(xfer_comp, valid_prim, valid_sec, valid_tri, xfer_adv_i, xfer_num_i, num_prim, num_sec, num_tri) begin
-- Primary Stage
if(xfer_comp='1' or valid_prim='0') then
if(valid_sec='0') then
num_prim_n <= xfer_num_i;
else
num_prim_n <= num_sec;
end if;
elsif(xfer_adv_i='1') then
-- NOTE: This is synthesized into both a subtractor and down-counter.
-- May save a few slices if the down-counter is removed.
num_prim_n <= num_prim - 1;
else
num_prim_n <= num_prim;
end if;
-- Secondary Stage
if(xfer_comp='1' or valid_sec='0') then
if(valid_tri='0') then
num_sec_n <= xfer_num_i;
else
num_sec_n <= num_tri;
end if;
else
num_sec_n <= num_sec;
end if;
end process;
-- Latch next counter values for all three stages
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
num_prim <= (others=>'0');
num_sec <= (others=>'0');
num_tri <= (others=>'0');
else
-- Primary and secondary stages have next value calculated externally
num_prim <= num_prim_n;
num_sec <= num_sec_n;
-- Trinary Stage
if(xfer_comp='1' or valid_tri='0') then
num_tri <= xfer_num_i;
end if;
-- Last indicator can also be latched
xfer_last <= xfer_last_n;
end if;
end if;
end process;
-- Generate ack state signals for first two pipeline stages
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
ack_prim <= '0';
ack_sec <= '0';
else
-- Primary Stage
if(xfer_comp='1' or ack_prim='0') then
ack_prim <= ack_sec or xfer_ack_i;
end if;
-- Secondary Stage
if(xfer_comp='1' or ack_sec='0') then
ack_sec <= xfer_ack_i and ack_prim and (not xfer_comp or ack_sec);
end if;
end if;
end if;
end process;
-- Generate valid signals for each pipeline stage
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
valid_prim <= '0';
valid_sec <= '0';
valid_tri <= '0';
else
-- Primary Stage
if(xfer_comp='1' or valid_prim='0') then
valid_prim <= valid_sec or xfer_req_i;
end if;
-- Secondary Stage
if(xfer_comp='1' or valid_sec='0') then
valid_sec <= valid_tri or (xfer_req_i and valid_prim and (valid_sec or not xfer_comp));
end if;
-- Trinary Stage
if(xfer_comp='1' or valid_tri='0') then
valid_tri <= xfer_req_i and valid_sec and not xfer_comp;
end if;
end if;
end if;
end process;
end lipif_mst_pipeliner_rtl;
|
gpl-3.0
|
cf3ebaa51780ccf567c03f76fbdbe526
| 0.537249 | 3.55857 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_timing.vhd
| 7 | 6,089 |
-------------------------------------------------------------------------------
-- Filename: ac97_timing.vhd
--
-- Description: Provides the primary timing signals for the AC97 protocol.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- This module is approximately 14 slices
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end entity ac97_timing;
library unisim;
use unisim.all;
architecture IMP of ac97_timing is
signal slotnum_i : natural range 0 to 12 := 0;
signal bitnum_i : natural range 0 to 19 := 0;
signal sync_i : std_logic := '0';
signal frame_end_i : std_logic := '0';
signal slot_end_i : std_logic;
signal init_sync : std_logic;
signal reset_sync :std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
--
-- This module will generate the timing signals for the AC97 core. This
-- module will sequence through the timing of a complete AC97 frame. All
-- timing signals are syncronized to the input Bit_Clk. The Bit_Clk is driven
-- externally (from the AC97 Codec) at a frequency of 12.288 Mhz.
--
-- The AC97 frame is 256 clock cycles and is organized as follows:
--
-- 16 cycles for Slot 0
-- 20 cycles each for slots 1-12
--
-- The total frame time is 16 + 12*20 = 256 cycles. With a Bit_Clk frequency
-- of 12.288 MHz, the frame frequency is 48,000 and the frame period is
-- 20.83 us.
--
-- The signals created in this module are:
--
-- Sync: Provides the AC97 Sync signal for slot 0
-- Frame_End: Signals the last cycle of the AC97 frame.
-- Slot_Num: Indicates the current slot number
-- Slot_End: Indicates the end of the current slot
-- Bit_Num: Indicates current bit of current slot
--
-- All signals transition on the rising clock edge of Bit_Clk
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Sync
--
-- A low to high transition on Sync signals to the AC97 codec that a
-- new frame is about to begin. This signal is first asserted during the
-- *last* cycle of the frame. The signal transitions on the rising
-- edge of bit_clk and is sampled by the CODEC on the rising edge of
-- the next clock (it will sample the signal one cycle later or during
-- the first cycle of the next frame).
--
-- Sync is asserted for 16 bit clks.
--
-----------------------------------------------------------------------------
-- Slot end occurs at bit 15 for slot 0 and cycle 19 for the others
slot_end_i <= '1' when ((slotnum_i = 0 and bitnum_i = 15) or
bitnum_i = 19)
else '0';
Slot_End <= slot_end_i;
-- The sync signal needs to be asserted during the last cycle of the
-- frame (slot 12, bit 19). This signal is asserted one cycle
-- earlier so the sync signal can be registered.
init_sync <= '1' when (slotnum_i = 12 and bitnum_i = 18)
else '0';
-- The last cycle of the sync signal occurs during bit 14 of slot 0.
-- This signal is asserted during this cycle to insure sync is
-- cleared during bit 15 of slot 0
reset_sync <= '1' when slotnum_i = 0 and bitnum_i = 14
else '0';
process (Bit_Clk) is
begin
if Reset = '1' then
sync_i <= '0';
elsif Bit_Clk'event and Bit_Clk = '1' then -- rising clock edge
if sync_i = '0' and init_sync = '1' then
sync_i <= '1';
elsif sync_i = '1' and reset_sync = '1' then
sync_i <= '0';
end if;
end if;
end process;
Sync <= sync_i;
-----------------------------------------------------------------------------
-- New_frame
--
-- New_frame is asserted for one clock cycle during the *last* clock cycles
-- of the current frame. New_frame is asserted during the first
-- cycle that sync is asserted.
--
-----------------------------------------------------------------------------
process (Bit_Clk) is
begin
if Reset = '1' then
frame_end_i <= '0';
elsif Bit_Clk'event and Bit_Clk = '1' then -- rising clock edge
if frame_end_i = '0' and init_sync = '1' then
frame_end_i <= '1';
else
frame_end_i <= '0';
end if;
end if;
end process;
Frame_End <= frame_end_i;
-----------------------------------------------------------------------------
-- Provide a counter for the slot number and current bit number.
-----------------------------------------------------------------------------
process (Bit_Clk) is
begin
if Reset = '1' then
bitnum_i <= 0;
slotnum_i <= 0;
elsif Bit_Clk'event and Bit_Clk = '1' then -- rising clock edge
if slot_end_i = '1' then
bitnum_i <= 0;
if slotnum_i = 12 then
slotnum_i <= 0;
else
slotnum_i <= slotnum_i + 1;
end if;
else
bitnum_i <= bitnum_i + 1;
end if;
end if;
end process;
Slot_Num <= slotnum_i;
Bit_Num <= bitnum_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
|
gpl-3.0
|
767a2824b6e3f8ca4e0b7cc90af52492
| 0.472656 | 4.421932 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_core_v2_03_a/hdl/vhdl/mmu.vhd
| 1 | 13,383 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.proc_common_pkg.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library osif_core_v2_03_a;
use osif_core_v2_03_a.all;
entity mmu is
generic
(
--C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_MMU_STAT_REGS : boolean := false;
C_TLB_TAG_WIDTH : integer := 20;
C_TLB_DATA_WIDTH : integer := 21
);
port
(
clk : in std_logic;
rst : in std_logic;
-- incoming memory interface
i_swrq : in std_logic;
i_srrq : in std_logic;
i_bwrq : in std_logic;
i_brrq : in std_logic;
i_addr : in std_logic_vector(C_AWIDTH - 1 downto 0);
i_laddr : in std_logic_vector(C_AWIDTH - 1 downto 0);
o_data : out std_logic_vector(C_AWIDTH - 1 downto 0);
o_busy : out std_logic;
o_rdone : out std_logic;
o_wdone : out std_logic;
-- outgoing memory interface
o_swrq : out std_logic;
o_srrq : out std_logic;
o_bwrq : out std_logic;
o_brrq : out std_logic;
o_addr : out std_logic_vector(C_AWIDTH - 1 downto 0);
o_laddr : out std_logic_vector(C_AWIDTH - 1 downto 0);
i_data : in std_logic_vector(C_AWIDTH - 1 downto 0);
i_busy : in std_logic;
i_rdone : in std_logic;
i_wdone : in std_logic;
-- configuration interface
i_cfg : in std_logic_vector(C_AWIDTH - 1 downto 0);
i_repeat : in std_logic;
i_setpgd : in std_logic;
-- status registers
o_state_fault : out std_logic;
o_state_access_violation : out std_logic;
-- tlb interface
i_tlb_match : in std_logic;
i_tlb_busy : in std_logic;
--i_tlb_wdone : in std_logic;
o_tlb_we : out std_logic;
o_tlb_request : out std_logic;
i_tlb_data : in std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
o_tlb_data : out std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
o_tlb_tag : out std_logic_vector(C_TLB_TAG_WIDTH - 1 downto 0);
-- diagnosis registers
o_tlb_miss_count : out std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
o_tlb_hit_count : out std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
o_page_fault_count : out std_logic_vector(C_DCR_DWIDTH - 1 downto 0)
);
end entity;
architecture imp of mmu is
type state_t is (
STATE_FETCH_REQUEST,
STATE_TLB_LOOKUP_1,
STATE_TLB_LOOKUP_2,
STATE_READ_PGDE,
STATE_SAVE_PGDE,
STATE_READ_PTE,
STATE_SAVE_PTE,
STATE_TLB_STORE_1,
STATE_TLB_STORE_2,
STATE_WAIT_FOR_BUSY,
STATE_DONE,
STATE_FAULT,
STATE_ACCESS_VIOLATION
);
signal rq : std_logic;
signal busy : std_logic;
signal active : std_logic;
signal pgd : std_logic_vector(C_AWIDTH - 1 downto 0);
signal srrq : std_logic;
signal data : std_logic_vector(C_AWIDTH - 1 downto 0);
signal request : std_logic_vector(3 downto 0);
signal step : state_t;
signal tlb_miss_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
signal tlb_hit_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
signal page_fault_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
begin
enable_mmu_stat_regs : if C_MMU_STAT_REGS generate
o_tlb_miss_count <= tlb_miss_count;
o_tlb_hit_count <= tlb_hit_count;
o_page_fault_count <= page_fault_count;
end generate;
disable_mmu_stat_regs : if not C_MMU_STAT_REGS generate
o_tlb_miss_count <= (others => '0');
o_tlb_hit_count <= (others => '0');
o_page_fault_count <= (others => '0');
end generate;
rq <= i_swrq or i_srrq or i_bwrq or i_brrq;
memory_interface_mux : process(active, busy, srrq, i_laddr, i_busy, i_rdone, i_wdone, request, data, i_data)
begin
if active = '1' then
o_laddr <= (others => '0');--C_BASEADDR;
o_data <= data;
o_busy <= busy;
o_rdone <= '0';
o_wdone <= '0';
o_srrq <= srrq;
o_swrq <= '0';
o_brrq <= '0';
o_bwrq <= '0';
else
o_laddr <= i_laddr;
o_data <= i_data;
o_busy <= i_busy or busy;
o_rdone <= i_rdone;
o_wdone <= i_wdone;
o_srrq <= request(3);
o_swrq <= request(2);
o_brrq <= request(1);
o_bwrq <= request(0);
end if;
end process;
mmu_configuration : process(clk, rst, i_setpgd)
begin
if rst = '1' then
pgd <= (others => '0');
elsif rising_edge(clk) then
if i_setpgd = '1' then
pgd <= i_cfg;
end if;
end if;
end process;
handle_rq : process(clk, rst, rq)
variable vaddr : std_logic_vector(31 downto 0);
variable pte : std_logic_vector(31 downto 0);
variable writable : std_logic;
variable waiting : std_logic;
begin
if rst = '1' then
step <= STATE_FETCH_REQUEST;
active <= '1';
waiting := '0';
busy <= '0';
srrq <= '0';
request <= (others => '0');
o_state_fault <= '0';
o_state_access_violation <= '0';
data <= X"DADADADA";
tlb_miss_count <= (others => '0');
tlb_hit_count <= (others => '0');
page_fault_count <= (others => '0');
o_tlb_we <= '0';
o_tlb_request <= '0';
elsif rising_edge(clk) then
if rq = '1' or waiting = '1' then
case step is
when STATE_FETCH_REQUEST => -- 0
request <= i_srrq & i_swrq & i_brrq & i_bwrq;
vaddr := i_addr; -- save virtual address
busy <= '1';
waiting := '1';
o_tlb_request <= '1';
step <= STATE_TLB_LOOKUP_1;
when STATE_TLB_LOOKUP_1 =>
o_tlb_tag <= vaddr(31 downto 12);
if i_tlb_busy = '0' then
step <= STATE_TLB_LOOKUP_2;
end if;
when STATE_TLB_LOOKUP_2 =>
o_tlb_request <= '0';
if i_tlb_match = '1' then
o_addr <= i_tlb_data(20 downto 1) & vaddr(11 downto 0);
if C_MMU_STAT_REGS then tlb_hit_count <= tlb_hit_count + 1; end if;
if i_tlb_data(0) = '0' and (request(0) = '1' or request(2) = '1') then
step <= STATE_ACCESS_VIOLATION;
else
active <= '0'; -- release memory interface
step <= STATE_WAIT_FOR_BUSY;
end if;
else
if C_MMU_STAT_REGS then tlb_miss_count <= tlb_miss_count + 1; end if;
step <= STATE_READ_PGDE;
end if;
when STATE_READ_PGDE =>
-- read pgd entry
srrq <= '1';
o_addr <= pgd(31 downto 12) & vaddr(31 downto 22) & b"00";
step <= STATE_SAVE_PGDE;
when STATE_SAVE_PGDE => --1
-- save pgd entry
srrq <= '0';
if i_rdone = '1' then
--pgde := i_data;
if i_data(10) = '0' then
--page_fault_count <= page_fault_count + 1;
step <= STATE_FAULT;
else
o_addr <= i_data(31 downto 12) & vaddr(21 downto 12) & b"00";
step <= STATE_READ_PTE;
end if;
end if;
when STATE_READ_PTE => -- 2
-- read pte
srrq <= '1';
step <= STATE_SAVE_PTE;
when STATE_SAVE_PTE => -- 3
-- save pte
srrq <= '0';
if i_rdone = '1' then
pte := i_data;
writable := pte(8);
o_addr <= pte(31 downto 12) & vaddr(11 downto 0);
if pte(1) = '0' then -- page not present
step <= STATE_FAULT;
elsif writable = '0' and (request(0) = '1' or request(2) = '1') then
step <= STATE_ACCESS_VIOLATION;
else
o_tlb_request <= '1';
step <= STATE_TLB_STORE_1;
end if;
end if;
when STATE_TLB_STORE_1 =>
if i_tlb_busy = '0' then
o_tlb_we <= '1';
o_tlb_tag <= vaddr(31 downto 12);
o_tlb_data <= pte(31 downto 12) & writable;
step <= STATE_TLB_STORE_2;
end if;
when STATE_TLB_STORE_2 =>
o_tlb_we <= '0';
o_tlb_request <= '0';
if writable = '0' and (request(0) = '1' or request(2) = '1') then
step <= STATE_ACCESS_VIOLATION;
else
active <= '0';
step <= STATE_WAIT_FOR_BUSY;
end if;
when STATE_WAIT_FOR_BUSY => -- 4
request <= (others => '0');
if i_busy = '1' then
busy <= '0'; -- at this point o_busy is generated by the memory controller
step <= STATE_DONE;
end if;
when STATE_DONE => -- 5
if i_busy = '0' and (i_rdone = '1' or i_wdone = '1') then -- i_done stays '1' for exactly one clock cycle after request finishes
data <= i_data;
active <= '1'; -- claim memory interface
waiting := '0';
step <= STATE_FETCH_REQUEST;
end if;
when STATE_FAULT => -- 6
if i_repeat = '1' then
o_state_fault <= '0';
if C_MMU_STAT_REGS then page_fault_count <= page_fault_count + 1; end if;
step <= STATE_READ_PGDE;
else
o_state_fault <= '1';
data <= vaddr;
end if;
-- when a writable page is first mapped into ram its PTE may be marked read-only in
-- order to create a page fault at the first write access (the page can then be marked dirty.
-- by the OS). If that is the case, we repeat the address lookup.
when STATE_ACCESS_VIOLATION =>
if i_repeat = '1' then
o_state_access_violation <= '0';
if C_MMU_STAT_REGS then page_fault_count <= page_fault_count + 1; end if;
step <= STATE_READ_PGDE;
else
o_state_access_violation <= '1';
data <= vaddr;
end if;
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
19634a68959e72df9308af2791ec19eb
| 0.398715 | 4.266178 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_eth/pcores/multibus_v2_01_a/hdl/vhdl/multibus.vhd
| 1 | 9,165 |
-- Implementation of a multibus for three hardware threads
-- (due to lack of better knowledge we did not use generics...).
-- The bus assumes that an arbiter decides which thread is allowed to send
-- and simply connects the corresponding threads.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multibus is
generic (
C_NR_SLOTS : integer := 3 -- it is not a "real" generic, e.g., we still have to adapt the number of ports and the number of signals manually
);
port (
i_grant_0 : in std_logic_vector(0 to C_NR_SLOTS - 1); --grant vector to thread NR 0. (element 0 = 1 => allowed to talk to thread 0)
i_grant_1 : in std_logic_vector(0 to C_NR_SLOTS - 1); --grant vector to thread NR 1. (element 0 = 1 => allowed to talk to thread 0)
i_grant_2 : in std_logic_vector(0 to C_NR_SLOTS - 1); --grant vector to thread Nr 2. (element 0 = 1 => allowed to talk to thread 0)
o_busdata_0 : out std_logic_vector(0 to 32 - 1); -- these are the outgoing signals (data goes to slot 0)
o_busdata_1 : out std_logic_vector(0 to 32 - 1);
o_busdata_2 : out std_logic_vector(0 to 32 - 1);
o_bussof_0 : out std_logic; -- these are the outgoing signals (data goes to slot 0)
o_bussof_1 : out std_logic;
o_bussof_2 : out std_logic;
o_buseof_0 : out std_logic; -- these are the outgoing signals (data goes to slot 0)
o_buseof_1 : out std_logic;
o_buseof_2 : out std_logic;
i_data_0 : in std_logic_vector(0 to C_NR_SLOTS * 32 - 1); --data that comes from thread 0, first 32 bit go to thread 0, second 32 bit go to thread 1, etc
i_data_1 : in std_logic_vector(0 to C_NR_SLOTS * 32 - 1);
i_data_2 : in std_logic_vector(0 to C_NR_SLOTS * 32 - 1);
i_sof_0 : in std_logic_vector(0 to C_NR_SLOTS - 1);
i_sof_1 : in std_logic_vector(0 to C_NR_SLOTS - 1);
i_sof_2 : in std_logic_vector(0 to C_NR_SLOTS - 1);
i_eof_0 : in std_logic_vector(0 to C_NR_SLOTS - 1);
i_eof_1 : in std_logic_vector(0 to C_NR_SLOTS - 1);
i_eof_2 : in std_logic_vector(0 to C_NR_SLOTS - 1);
i_src_rdy_0 : in std_logic_vector(0 to C_NR_SLOTS - 1);
i_src_rdy_1 : in std_logic_vector(0 to C_NR_SLOTS - 1);
i_src_rdy_2 : in std_logic_vector(0 to C_NR_SLOTS - 1);
o_dst_rdy_0 : out std_logic_vector(0 to C_NR_SLOTS - 1);
o_dst_rdy_1 : out std_logic_vector(0 to C_NR_SLOTS - 1);
o_dst_rdy_2 : out std_logic_vector(0 to C_NR_SLOTS - 1);
i_bus_dst_rdy_0 : in std_logic;
i_bus_dst_rdy_1 : in std_logic;
i_bus_dst_rdy_2 : in std_logic;
o_bus_src_rdy_0 : out std_logic;
o_bus_src_rdy_1 : out std_logic;
o_bus_src_rdy_2 : out std_logic;
clk : in std_logic;
reset : in std_logic
);
end multibus;
architecture Behavioral of multibus is
signal grant_for_thread_0 : std_logic_vector(0 to C_NR_SLOTS -1); -- grant signals for talking with thread 0
signal grant_for_thread_1 : std_logic_vector(0 to C_NR_SLOTS -1); -- element 0 = 1 => thread 0 is allowed to talk to thread 1
signal grant_for_thread_2 : std_logic_vector(0 to C_NR_SLOTS -1);
signal data_for_thread_0 : std_logic_vector(0 to C_NR_SLOTS * 32 - 1); --the data that goes to slot 0
signal data_for_thread_1 : std_logic_vector(0 to C_NR_SLOTS * 32 - 1); --first 32 bit from thread 0, second 32 bit from thread 1, third 32 bit from thread 2
signal data_for_thread_2 : std_logic_vector(0 to C_NR_SLOTS * 32 - 1);
signal sof_for_thread_0 : std_logic_vector(0 to C_NR_SLOTS -1); -- grant signals for talking with thread 0
signal sof_for_thread_1 : std_logic_vector(0 to C_NR_SLOTS -1); -- element 0 = 1 => thread 0 is allowed to talk to thread 1
signal sof_for_thread_2 : std_logic_vector(0 to C_NR_SLOTS -1);
signal eof_for_thread_0 : std_logic_vector(0 to C_NR_SLOTS -1); -- grant signals for talking with thread 0
signal eof_for_thread_1 : std_logic_vector(0 to C_NR_SLOTS -1); -- element 0 = 1 => thread 0 is allowed to talk to thread 1
signal eof_for_thread_2 : std_logic_vector(0 to C_NR_SLOTS -1);
signal src_rdy_for_thread_0 : std_logic_vector(0 to C_NR_SLOTS -1); --the source is ready to send data to thread 0 (for flow control)
signal src_rdy_for_thread_1 : std_logic_vector(0 to C_NR_SLOTS -1); --the source is ready to send data to thread 0 (for flow control)
signal src_rdy_for_thread_2 : std_logic_vector(0 to C_NR_SLOTS -1); --the source is ready to send data to thread 0 (for flow control)
begin
-- how could this be done less ugly?...
grant_for_thread_0(0) <= i_grant_0(0);
grant_for_thread_1(0) <= i_grant_0(1);
grant_for_thread_2(0) <= i_grant_0(2);
grant_for_thread_0(1) <= i_grant_1(0);
grant_for_thread_1(1) <= i_grant_1(1);
grant_for_thread_2(1) <= i_grant_1(2);
grant_for_thread_0(2) <= i_grant_2(0);
grant_for_thread_1(2) <= i_grant_2(1);
grant_for_thread_2(2) <= i_grant_2(2);
sof_for_thread_0(0) <= i_sof_0(0);
sof_for_thread_1(0) <= i_sof_0(1);
sof_for_thread_2(0) <= i_sof_0(2);
sof_for_thread_0(1) <= i_sof_1(0);
sof_for_thread_1(1) <= i_sof_1(1);
sof_for_thread_2(1) <= i_sof_1(2);
sof_for_thread_0(2) <= i_sof_2(0);
sof_for_thread_1(2) <= i_sof_2(1);
sof_for_thread_2(2) <= i_sof_2(2);
eof_for_thread_0(0) <= i_eof_0(0);
eof_for_thread_1(0) <= i_eof_0(1);
eof_for_thread_2(0) <= i_eof_0(2);
eof_for_thread_0(1) <= i_eof_1(0);
eof_for_thread_1(1) <= i_eof_1(1);
eof_for_thread_2(1) <= i_eof_1(2);
eof_for_thread_0(2) <= i_eof_2(0);
eof_for_thread_1(2) <= i_eof_2(1);
eof_for_thread_2(2) <= i_eof_2(2);
data_for_thread_0(0 to 32 -1) <= i_data_0(0 to 32 - 1);
data_for_thread_0(32 to 64 -1) <= i_data_1(0 to 32 - 1);
data_for_thread_0(64 to 96 -1) <= i_data_2(0 to 32 - 1);
data_for_thread_1(0 to 32 -1) <= i_data_0(32 to 64 -1);
data_for_thread_1(32 to 64 -1) <= i_data_1(32 to 64 -1);
data_for_thread_1(64 to 96 -1) <= i_data_2(32 to 64 -1);
data_for_thread_2(0 to 32 -1) <= i_data_0(64 to 96 -1);
data_for_thread_2(32 to 64 -1) <= i_data_1(64 to 96 -1);
data_for_thread_2(64 to 96 -1) <= i_data_2(64 to 96 -1);
src_rdy_for_thread_0(0) <= i_src_rdy_0(0);
src_rdy_for_thread_1(0) <= i_src_rdy_0(1);
src_rdy_for_thread_2(0) <= i_src_rdy_0(2);
src_rdy_for_thread_0(1) <= i_src_rdy_1(0);
src_rdy_for_thread_1(1) <= i_src_rdy_1(1);
src_rdy_for_thread_2(1) <= i_src_rdy_1(2);
src_rdy_for_thread_0(2) <= i_src_rdy_2(0);
src_rdy_for_thread_1(2) <= i_src_rdy_2(1);
src_rdy_for_thread_2(2) <= i_src_rdy_2(2);
o_dst_rdy_0(0) <= i_bus_dst_rdy_0;
o_dst_rdy_1(0) <= i_bus_dst_rdy_0;
o_dst_rdy_2(0) <= i_bus_dst_rdy_0;
o_dst_rdy_0(1) <= i_bus_dst_rdy_1;
o_dst_rdy_1(1) <= i_bus_dst_rdy_1;
o_dst_rdy_2(1) <= i_bus_dst_rdy_1;
o_dst_rdy_0(2) <= i_bus_dst_rdy_2;
o_dst_rdy_1(2) <= i_bus_dst_rdy_2;
o_dst_rdy_2(2) <= i_bus_dst_rdy_2;
bus_0 : process(data_for_thread_0, grant_for_thread_0, sof_for_thread_0, eof_for_thread_0, src_rdy_for_thread_0)
variable low : natural;
variable high : natural;
begin
o_busdata_0 <= (others => '0');
o_bussof_0 <= '0';
o_buseof_0 <= '0';
o_bus_src_rdy_0 <= '0';
for i in grant_for_thread_0'range loop
if (grant_for_thread_0(i) = '1') then
low := i * 32;
high := (i + 1) * 32;
o_busdata_0 <= data_for_thread_0(low to high - 1);
o_bussof_0 <= sof_for_thread_0(i);
o_buseof_0 <= eof_for_thread_0(i);
o_bus_src_rdy_0 <= src_rdy_for_thread_0(i);
end if;
end loop;
end process;
--hard coded slot 0 to slot 1
-- o_busdata_1 <= data_for_thread_1(0 to 31);
-- o_bussof_1 <= sof_for_thread_1(0);
-- o_buseof_1 <= eof_for_thread_1(0);
-- o_bus_src_rdy_1 <= src_rdy_for_thread_1(0);
--alternate version in case the for loop version does not work
-- o_busdata_1 <= data_for_thread_1(0 to 31) when grant_for_thread_1 = "100" else
-- data_for_thread_1(32 to 63) when grant_for_thread_1 = "010" else
-- data_for_thread_1(64 to 95) when grant_for_thread_1 = "001" else
-- (others => '0');
bus_1 : process(data_for_thread_1, grant_for_thread_1, sof_for_thread_1, eof_for_thread_1, src_rdy_for_thread_1)
variable low : natural;
variable high : natural;
begin
o_busdata_1 <= (others => '0');
o_bussof_1 <= '0';
o_buseof_1 <= '0';
o_bus_src_rdy_1 <= '0';
for i in grant_for_thread_1'range loop
if (grant_for_thread_1(i) = '1') then
low := i * 32;
high := (i + 1) * 32;
o_busdata_1 <= data_for_thread_1(low to high - 1);
o_bussof_1 <= sof_for_thread_1(i);
o_buseof_1 <= eof_for_thread_1(i);
o_bus_src_rdy_1 <= src_rdy_for_thread_1(i);
end if;
end loop;
end process;
bus_2 : process(data_for_thread_2, grant_for_thread_2,sof_for_thread_2, eof_for_thread_2, src_rdy_for_thread_2)
variable low : natural;
variable high : natural;
begin
o_busdata_2 <= (others => '0');
o_bussof_2 <= '0';
o_buseof_2 <= '0';
o_bus_src_rdy_2 <= '0';
for i in grant_for_thread_2'range loop
if (grant_for_thread_2(i) = '1') then
low := i * 32;
high := (i + 1) * 32;
o_busdata_2 <= data_for_thread_2(low to high - 1);
o_bussof_2 <= sof_for_thread_2(i);
o_buseof_2 <= eof_for_thread_2(i);
o_bus_src_rdy_2 <= src_rdy_for_thread_2(i);
end if;
end loop;
end process;
end Behavioral;
|
gpl-3.0
|
c3468d6cbdcf1355e76d3f6418f0bdd7
| 0.634152 | 2.31381 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/others/fft_transform.vhd
| 1 | 17,668 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- -- --
-- FFT TRANSFORMATION OF 2048 SAMPLES (16 bit wide, signed) --
-- OUTPUT: 2048 FFT VALUES --
-- - real component (16 bit wide) --
-- - imaginary component (16 bit wide) --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity fft_transform is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end fft_transform;
architecture Behavioral of fft_transform is
-- fft component (uses radix-4 algorithm)
component xfft_v5_0
port (
clk : IN std_logic;
ce : IN std_logic;
sclr : IN std_logic;
start : IN std_logic;
xn_re : IN std_logic_vector(15 downto 0);
xn_im : IN std_logic_vector(15 downto 0);
fwd_inv : IN std_logic;
fwd_inv_we : IN std_logic;
scale_sch : IN std_logic_vector(13 downto 0);
scale_sch_we : IN std_logic;
rfd : OUT std_logic;
xn_index : OUT std_logic_vector(6 downto 0);
busy : OUT std_logic;
edone : OUT std_logic;
done : OUT std_logic;
dv : OUT std_logic;
xk_index : OUT std_logic_vector(6 downto 0);
xk_re : OUT std_logic_vector(15 downto 0);
xk_im : OUT std_logic_vector(15 downto 0));
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- signals for fft core
-- incoming signals
signal ce : std_logic := '0';
signal sclr : std_logic := '0';
signal start : std_logic := '0';
signal xn_re : std_logic_vector(15 downto 0) := (others => '0');
signal xn_im : std_logic_vector(15 downto 0) := (others => '0');
signal fwd_inv : std_logic := '1';
signal fwd_inv_we : std_logic := '0';
signal scale_sch : std_logic_vector(13 downto 0) := "01101010101010";
signal scale_sch_we : std_logic := '0';
--outgoing signals
signal rfd : std_logic;
signal xn_index : std_logic_vector(6 downto 0);
signal busy : std_logic;
signal edone : std_logic;
signal done : std_logic;
signal dv : std_logic;
signal xk_index : std_logic_vector(6 downto 0);
signal xk_re : std_logic_vector(15 downto 0);
signal xk_im : std_logic_vector(15 downto 0);
-- states
type t_state is
(
init,
wait_for_message,
wait_for_message_2,
read_input,
read_input_2,
read_input_3,
read_input_4,
read_input_5,
read_input_6,
read_input_dec,
make_fft,
write_output,
write_output_2,
write_output_3,
write_output_4,
write_output_5,
write_output_6,
write_output_dec,
write_output_get,
write_output_wait,
write_output_write,
write_output_write_done,
send_message
);
-- current state
signal state : t_state := init;
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal input_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal output_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal current_input_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal current_output_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_in : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_out : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal counter : std_logic_vector(0 to 6) := (others => '0');
signal my_xn_index : std_logic_vector(6 downto 0);
signal address : std_logic_vector(0 to C_BURST_AWIDTH-1);
signal local_ram_address_in_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal fft_en : std_logic := '0'; -- handshake signals
signal fft_done : std_logic := '0';
signal o_RAMAddr_fft : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_fsm : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMData_fft : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
signal o_RAMData_fsm : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
signal o_RAMWE_fft : std_logic := '0';
signal o_RAMWE_fsm : std_logic := '0';
-- 1st 16 bits: real component, 2nd 16 bits: imaginary component
--type t_ram is array (1023 downto 0) of std_logic_vector(31 downto 0);
--signal fft_ram : t_ram; -- samples memory
begin
-- fft core
my_fft_core : xfft_v5_0
port map (
clk => clk,
ce => ce,
sclr => sclr,
start => start,
xn_re => xn_re,
xn_im => xn_im,
fwd_inv => fwd_inv,
fwd_inv_we => fwd_inv_we,
scale_sch => scale_sch,
scale_sch_we => scale_sch_we,
rfd => rfd,
xn_index => xn_index,
busy => busy,
edone => edone,
done => done,
dv => dv,
xk_index => xk_index,
xk_re => xk_re,
xk_im => xk_im
);
-- clock for burst ram
o_RAMClk <= clk;
-- switch for o_RAMAddr
o_RAMAddr <= o_RAMAddr_fft(0 to C_BURST_AWIDTH-2) & not o_RAMAddr_fft(C_BURST_AWIDTH-1)
when (fft_en = '1') else o_RAMAddr_fsm(0 to C_BURST_AWIDTH-2) & not o_RAMAddr_fsm(C_BURST_AWIDTH-1);
o_RAMData <= o_RAMData_fft when (fft_en = '1') else o_RAMData_fsm;
o_RAMWE <= o_RAMWE_fft when (fft_en = '1') else o_RAMWE_fsm;
fft_proc : process(clk, reset, fft_en)
variable step : natural range 0 to 9;
begin
if (reset='1' or fft_en='0') then
fft_done <= '0';
start <= '0';
o_RAMWE_fft <= '0';
xn_im <= (others=>'0');
xn_re <= (others=>'0');
ce <= '0';
fwd_inv <= '1';
sclr <= '1';
step := 0;
elsif (rising_edge(clk)) then
case step is
-- fill fft core with data
when 0 => -- set start signal
sclr <= '0';
ce <= '1';
fwd_inv <= '1';
fwd_inv_we <= '1';
o_RAMWE_fft <= '0';
o_RAMAddr_fft <= (others => '0');
address <= (others => '0');
xn_im <= (others=>'0');
step := step + 1;
when 1 => -- set start signal
start <= '1';
fwd_inv_we <= '0';
o_RAMWE_fft <= '0';
--if (rfd = '1') then
my_xn_index <= xn_index;
step := step + 1;
--end if;
when 2 => -- start filling the incoming data pipeline
-- (read left sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(16)&i_RAMData(17)&i_RAMData(18)&i_RAMData(19)&i_RAMData(20)&i_RAMData(21)&i_RAMData(22)&i_RAMData(23)&i_RAMData(24)&i_RAMData(25)&i_RAMData(26)&i_RAMData(27)&i_RAMData(28)&i_RAMData(29)&i_RAMData(30)&i_RAMData(31);
o_RAMAddr_fft <= address + 1;
address <= address + 1;
step := step + 1;
when 3 => -- start filling the incoming data pipeline
-- (read right sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(0)&i_RAMData(1)&i_RAMData(2)&i_RAMData(3)&i_RAMData(4)&i_RAMData(5)&i_RAMData(6)&i_RAMData(7)&i_RAMData(8)&i_RAMData(9)&i_RAMData(10)&i_RAMData(11)&i_RAMData(12)&i_RAMData(13)&i_RAMData(14)&i_RAMData(15);
my_xn_index <= xn_index + 1;
step := step + 1;
when 4 => -- samples are arriving (read left sample (16 of 32 bits))
start <= '0';
xn_re(15 downto 0) <= i_RAMData(16)&i_RAMData(17)&i_RAMData(18)&i_RAMData(19)&i_RAMData(20)&i_RAMData(21)&i_RAMData(22)&i_RAMData(23)&i_RAMData(24)&i_RAMData(25)&i_RAMData(26)&i_RAMData(27)&i_RAMData(28)&i_RAMData(29)&i_RAMData(30)&i_RAMData(31);
my_xn_index <= xn_index + 1;
o_RAMAddr_fft <= address + 1;
address <= address + 1;
step := step + 1;
when 5 => -- samples are arriving (read right sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(0)&i_RAMData(1)&i_RAMData(2)&i_RAMData(3)&i_RAMData(4)&i_RAMData(5)&i_RAMData(6)&i_RAMData(7)&i_RAMData(8)&i_RAMData(9)&i_RAMData(10)&i_RAMData(11)&i_RAMData(12)&i_RAMData(13)&i_RAMData(14)&i_RAMData(15);
if (busy='0') then
my_xn_index <= xn_index + 1;
step := step - 1;
else
step := step + 1;
end if;
-- wait for results
when 6 =>
if (edone = '1') then
o_RAMAddr_fft <= address - 1;
address <= address - 1;
start <= '1';
o_RAMWE_fft <= '0';
step := step + 1;
end if;
-- get data and write them back
when 7 =>
--o_RAMData_fft(0 to 31) <= xk_re(15 downto 0) & xk_im(15 downto 0);
o_RAMData_fft(0 to 31) <= xk_re(15)&xk_re(14)&xk_re(13)&xk_re(12)&xk_re(11)&xk_re(10)&xk_re(9)&xk_re(8)&xk_re(7)&xk_re(6)&xk_re(5)&xk_re(4)&xk_re(3)&xk_re(2)&xk_re(1)&xk_re(0)&xk_im(15)&xk_im(14)&xk_im(13)&xk_im(12)&xk_im(11)&xk_im(10)&xk_im(9)&xk_im(8)&xk_im(7)&xk_im(6)&xk_im(5)&xk_im(4)&xk_im(3)&xk_im(2)&xk_im(1)&xk_im(0);
--o_RAMAddr_fft(0 to 11) <= "0" & xk_index(10 downto 0);
o_RAMAddr_fft(0 to 11) <= "00000"&xk_index(6)&xk_index(5)&xk_index(4)&xk_index(3)&xk_index(2)&xk_index(1)&xk_index(0);
o_RAMWE_fft <= '1';
if (busy='1') then
step := step + 1;
end if;
when 8 =>
--o_RAMData_fft(0 to 31) <= xk_re(15 downto 0) & xk_im(15 downto 0);
o_RAMData_fft(0 to 31) <= xk_re(15)&xk_re(14)&xk_re(13)&xk_re(12)&xk_re(11)&xk_re(10)&xk_re(9)&xk_re(8)&xk_re(7)&xk_re(6)&xk_re(5)&xk_re(4)&xk_re(3)&xk_re(2)&xk_re(1)&xk_re(0)&xk_im(15)&xk_im(14)&xk_im(13)&xk_im(12)&xk_im(11)&xk_im(10)&xk_im(9)&xk_im(8)&xk_im(7)&xk_im(6)&xk_im(5)&xk_im(4)&xk_im(3)&xk_im(2)&xk_im(1)&xk_im(0);
--o_RAMAddr_fft(0 to 11) <= "0" & xk_index(10 downto 0);
o_RAMAddr_fft(0 to 11) <= "00000"&xk_index(6)&xk_index(5)&xk_index(4)&xk_index(3)&xk_index(2)&xk_index(1)&xk_index(0);
--o_RAMWE_fft <= '1';
if (dv='0') then
o_RAMWE_fft <= '0';
step := step + 1;
else
o_RAMWE_fft <= '1';
end if;
-- finish fft process
when 9 =>
o_RAMWE_fft <= '0';
start <= '0';
sclr <= '1';
fft_done <= '1';
end case;
end if;
end process;
-----------------------------------------------------------------------------
--
-- ReconOS State Machine for Observation:
--
-----------------------------------------------------------------------------
fsm_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
variable success : boolean;
variable next_state : t_state := wait_for_message;
begin
if (reset = '1') then
reconos_reset( o_osif, i_osif );
state <= init;
o_RAMAddr_fsm <= (others=>'0');
o_RAMWE_fsm <= '0';
next_state := wait_for_message;
done := false;
elsif (rising_edge(clk)) then
reconos_begin( o_osif, i_osif );
if (reconos_ready( i_osif )) then
-- Transition to next state
case (state) is
-- 1. read information struct
when init =>
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
next_state := wait_for_message;
-- 2. wait for messages (input/output addresses) (do a fft)
when wait_for_message =>
reconos_mbox_get_s(done,success,o_osif,i_osif,C_MB_START,input_address);
counter <= (others => '0');
local_ram_address_in <= (others=>'0');
local_ram_address_out <= (others=>'0');
local_ram_address_in_if <= (others=>'0');
next_state := wait_for_message_2;
when wait_for_message_2 =>
reconos_mbox_get_s(done,success,o_osif,i_osif,C_MB_START,output_address);
current_input_address <= input_address;
next_state := read_input;
-- 3. read input samples from input_address (only real components expected)
when read_input =>
--reconos_read_burst(done,o_osif,i_osif,local_ram_address_in,current_input_address);
--next_state := read_input_dec;
next_state := read_input_2;
when read_input_2 =>
reconos_read_s(done,o_osif,i_osif,current_input_address,ram_data);
next_state := read_input_3;
when read_input_3 =>
-- wait
next_state := read_input_4;
when read_input_4 =>
-- wait
next_state := read_input_5;
when read_input_5 =>
-- write value to local ram
o_RAMWE_fsm <= '1';
o_RAMData_fsm <= ram_data;
o_RAMAddr_fsm <= local_ram_address_in_if;
next_state := read_input_6;
when read_input_6 =>
-- wait
o_RAMWE_fsm <= '0';
--local_ram_address_in <= local_ram_address_in + 4;
current_input_address <= current_input_address + 4;
local_ram_address_in_if <= local_ram_address_in_if + 1;
if (counter < 63) then
counter <= counter + 1;
next_state := read_input_2;
else
fft_en <= '1';
next_state := make_fft;
-- TODO: CHANGE CHANGE CHANGE: Remove again
--counter <= (others => '0');
--current_output_address <= output_address;
--next_state := write_output;
end if;
when read_input_dec =>
if (counter < 3) then
counter <= counter + 1;
local_ram_address_in <= local_ram_address_in + 128;
current_input_address <= current_input_address + 128;
next_state := read_input;
else
next_state := make_fft;
fft_en <= '1';
-- CHANGE CHANGE CHANGE - DEBUG
--counter <= (others => '0');
--current_output_address <= output_address;
--next_state := write_output;
end if;
--next_state := read_input_2;
-- 4. make fft for samples
when make_fft =>
if (fft_done = '1') then -- TODO CHANGE CHANGE CHANGE
current_output_address <= output_address;
local_ram_address_if <= (others => '0');
fft_en <= '0';
counter <= (others => '0');
next_state := write_output;
end if;
-- 5. write fft results to output_address
when write_output =>
--reconos_write_burst(done,o_osif,i_osif,local_ram_address_out,current_output_address);
--next_state := write_output_dec;
next_state := write_output_2;
when write_output_dec =>
if (counter < 3) then
counter <= counter + 1;
current_output_address <= current_output_address + 128;
local_ram_address_out <= local_ram_address_out + 128;
next_state := write_output;
else
next_state := send_message;
end if;
--next_state := write_output_2;
when write_output_2 =>
o_RAMAddr_fsm <= (others=>'0');
next_state := write_output_3;
when write_output_3 =>
-- wait
next_state := write_output_4;
when write_output_4 =>
reconos_write(done,o_osif,i_osif,current_output_address, i_RAMData);
next_state := write_output_5;
when write_output_5 =>
-- wait
next_state := write_output_6;
when write_output_6 =>
if (counter < 127) then
o_RAMAddr_fsm <= o_RAMAddr_fsm + 1;
counter <= counter + 1;
current_output_address <= current_output_address + 4;
next_state := write_output_3;
else
next_state := send_message;
end if;
-- 6. send message (work done)
when send_message =>
reconos_mbox_put(done,success,o_osif,i_osif,C_MB_DONE,input_address);
next_state := wait_for_message;
when others =>
next_state := wait_for_message;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
39e10155d5c8d74475ec324ab14ed50d
| 0.522357 | 2.958473 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_if.vhd
| 7 | 11,332 |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
entity ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_Vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end entity ac97_if;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
library unisim;
use unisim.all;
architecture IMP of ac97_if is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
--
CODEC_RDY : out std_logic
);
end component ac97_core;
component ac97_command_rom is
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end component ac97_command_rom;
signal pcm_playback_accept_ac97clk : std_logic;
signal pcm_playback_accept_ClkIn_0 : std_logic;
signal pcm_playback_accept_ClkIn_1 : std_logic;
signal pcm_playback_accept_ClkIn : std_logic;
signal pcm_record_valid_ac97clk, pcm_record_valid_ClkIn_0, pcm_record_valid_ClkIn_1 : std_logic;
signal pcm_record_valid_ClkIn : std_logic;
signal command_addr : std_logic_vector(6 downto 0);
signal write_data : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal codec_rdy : std_logic;
signal debug_i : std_logic_vector(3 downto 0);
signal reg_write_strobe_ac97, reg_busy_ac97, reg_error_ac97 : std_logic;
signal get_next_command : std_logic;
signal valid_command : std_logic;
signal command_num : unsigned(3 downto 0) := "0000";
type read_access_states is (AC97_READY, WARM_START,
REVIEW_COMMAND,ISSUE_COMMAND,
WAIT_COMMAND, NEXT_COMMAND,
READ_COMMAND, DONE);
signal command_SM : read_access_states;
signal reset_counter : unsigned(10 downto 0) := (others => '0');
signal AC97Reset_n_i : std_logic := '0';
signal rom_data : std_logic_vector(24 downto 0);
signal command_addr_i : std_logic_Vector(3 downto 0);
signal start_frame_delay : natural range 0 to 3 := 0;
attribute rom_style: string;
--attribute rom_style of ac97_command_rom: entity is "distributed";
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Command loading
-----------------------------------------------------------------------------
load_commands_SM_PROCESS : process (AC97clk) is
begin
if AC97clk'event and AC97clk = '1' then
if Reset = '1' then
command_SM <= AC97_READY;
command_num <= "0000";
else
case command_SM is
-- Issue some reset?
when AC97_READY =>
-- wait until codec is ready
if codec_rdy = '1' then
command_SM <= REVIEW_COMMAND;
start_frame_delay <= 0;
end if;
when WARM_START =>
if pcm_playback_accept_ac97clk = '1' then
if start_frame_delay = 3 then
command_SM <= REVIEW_COMMAND;
else
start_frame_delay <= start_frame_delay + 1;
end if;
end if;
when REVIEW_COMMAND =>
-- if command is valid, go on to issue command. otherwise, go to
-- end state.
if valid_command = '1' then
command_SM <= ISSUE_COMMAND;
else
command_SM <= DONE;
end if;
when ISSUE_COMMAND =>
-- strobe is issued in output forming logic
command_SM <= WAIT_COMMAND;
when WAIT_COMMAND =>
if reg_busy_ac97 = '0' then
command_SM <= NEXT_COMMAND;
end if;
-- error processing?
when NEXT_COMMAND =>
command_SM <= READ_COMMAND;
command_num <= command_num + 1;
when READ_COMMAND =>
command_SM <= REVIEW_COMMAND;
when DONE =>
-- do nothing
when others => NULL;
end case;
end if;
end if;
end process;
reg_write_strobe_ac97 <= '1' when command_SM = ISSUE_COMMAND else
'0';
get_next_command <= '1' when command_SM = NEXT_COMMAND else
'0';
-- ClkIn processes
-- The AC97 reset signal needs to be driven by ClkIn
-- (AC97 clock does not operate when reset asserted)
reset_process : process (ClkIn) is
begin
if Reset = '1' then
reset_counter <= (others => '0');
AC97Reset_n_i <= '0';
elsif ClkIn'event and ClkIn='1' then
if reset_counter(10) = '1' then
AC97Reset_n_i <= '1';
else
reset_counter <= reset_counter+1;
AC97Reset_n_i <= '0';
end if;
end if;
end process;
AC97Reset_n <= AC97Reset_n_i;
process (ClkIn)
begin
if ClkIn'event and ClkIn='1' then
pcm_playback_accept_ClkIn_0 <= pcm_playback_accept_ac97clk; -- async
pcm_playback_accept_ClkIn_1 <= pcm_playback_accept_ClkIn_0;
pcm_playback_accept_ClkIn <= pcm_playback_accept_ClkIn_0 and not pcm_playback_accept_ClkIn_1;
end if;
end process;
PCM_Playback_Accept <= pcm_playback_accept_ClkIn;
process (ClkIn)
begin
if ClkIn'event and ClkIn='1' then
pcm_record_valid_ClkIn_0 <= pcm_record_valid_ac97clk; -- async
pcm_record_valid_ClkIn_1 <= pcm_record_valid_ClkIn_0;
pcm_record_valid_ClkIn <= pcm_record_valid_ClkIn_0 and not pcm_record_valid_ClkIn_1;
end if;
end process;
PCM_Record_Valid <= pcm_record_valid_ClkIn;
-----------------------------------------------------------------------------
-- Command ROM
-----------------------------------------------------------------------------
ROM : ac97_command_rom
port map (
ClkIn => AC97Clk,
ROMAddr => command_addr_i,
ROMData => rom_data
);
command_addr_i <= CONV_STD_LOGIC_VECTOR(command_num, 4);
write_data <= rom_data(15 downto 0);
command_addr <= rom_data(22 downto 16);
valid_command <= rom_data(24);
-- debug_i(0) <= codec_rdy;
-- debug_i(1) <= '1' when command_SM = DONE else
-- '0';
-- debug_i(2) <= AC97Reset_n_i;
-- debug_i(3) <= reg_error_ac97;
debug_i <= command_addr_i;
debug <= debug_i;
-----------------------------------------------------------------------------
-- Instantiating the core
-----------------------------------------------------------------------------
ac97_core_I : ac97_core
port map (
Reset => Reset,
AC97_Bit_Clk => AC97Clk,
AC97_Sync => Sync,
AC97_SData_Out => SData_Out,
AC97_SData_In => SData_In,
AC97_Reg_Addr => command_addr,
AC97_Reg_Write_Data => write_data,
AC97_Reg_Read_Data => open, -- No reading from AC97
AC97_Reg_Read_Strobe => '0', -- No reading from AC97
AC97_Reg_Write_Strobe => reg_write_strobe_ac97, -- do
AC97_Reg_Busy => reg_busy_ac97, -- do
AC97_Reg_Error => reg_error_ac97, -- do
AC97_Reg_Read_Data_Valid => open, -- No reading from AC97
PCM_Playback_Left => PCM_Playback_Left, -- async
PCM_Playback_Right => PCM_Playback_right, -- async
PCM_Playback_Left_Valid => '1',
PCM_Playback_Right_Valid => '1',
PCM_Playback_Left_Accept => pcm_playback_accept_ac97clk,
PCM_Playback_Right_Accept => open, -- use left_accept
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => pcm_record_valid_ac97clk,
PCM_Record_Right_Valid => open, -- use left_valid
CODEC_RDY => codec_rdy
);
-- leds(3) <= not codec_rdy; -- and (command_SM = DONE);
-- leds(2) <= '0' when command_SM = INIT else '1';
-- leds(1) <= '0';
-- leds(0) <= AC97Clk; -- '0' when command_SM = DONE else '1';
end architecture IMP;
|
gpl-3.0
|
c70f91ae96d2a0f42ab8e951b96aa96d
| 0.52868 | 3.710544 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/imports/new/Prng.vhd
| 1 | 901 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Seeded PRNG (linear feedback shift register)
-- Thanks wikipedia for the consept and explaination
entity Prng is
Generic
(
BITS : integer := 32
);
Port
(
seed : in std_logic_vector (BITS-1 downto 0);
seed_en : in std_logic;
clk : in std_logic;
rnd : out std_logic_vector (BITS-1 downto 0)
);
end Prng;
architecture Behavioral of Prng is
begin
process (clk)
variable tmp_a : std_logic_vector(BITS-1 downto 0) := ('1', '0', '1', others => '0');
variable tmp_b : std_logic := '0';
begin
if rising_edge(clk) then
if seed_en = '1' then
tmp_a := seed;
else
tmp_b := tmp_a(BITS-1) xor tmp_a(BITS-2);
tmp_a := tmp_a(BITS-2 downto 0) & tmp_b;
rnd <= tmp_a;
end if;
end if;
end process;
end Behavioral;
|
mit
|
35e593d966ddf5c0d53f66454ddae601
| 0.556049 | 3.264493 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a.robert/simulation/test_mutex.vhd
| 1 | 3,169 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_mutex is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_mutex;
architecture Behavioral of test_mutex is
constant C_MY_MUTEX : std_logic_vector(0 to 31) := X"00000000";
type t_state is (STATE_INIT, STATE_HALLO, STATE_LOCK, STATE_READ, STATE_WRITE, STATE_UNLOCK);
signal state : t_state := STATE_INIT;
signal in_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal out_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
out_value <= in_value + 1;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_write(done, o_osif, i_osif, X"10000000", X"AFFEDEAD");
--reconos_get_init_data_s (done, o_osif, i_osif, init_data);
if done then
state <= STATE_HALLO;
end if;
when STATE_HALLO =>
reconos_write(done, o_osif, i_osif, X"10000000", X"AFFEDEAD");
if done then
state <= STATE_LOCK;
end if;
when STATE_LOCK =>
reconos_mutex_lock (done, success, o_osif, i_osif, C_MY_MUTEX);
if done and success then
state <= STATE_READ;
end if;
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, init_data, in_value);
if done then
state <= STATE_WRITE;
end if;
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, init_data, out_value);
if done then
state <= STATE_UNLOCK;
end if;
when STATE_UNLOCK =>
reconos_mutex_unlock (o_osif, i_osif, C_MY_MUTEX);
state <= STATE_LOCK;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
7770c88c912c91d82a6e5624debeb6de
| 0.569265 | 3.403867 | false | false | false | false |
luebbers/reconos
|
tests/automated/condvar/hw/hwthreads/condvar/hwt_condvar.vhd
| 1 | 2,817 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_condvar is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_condvar is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_MUTEX_A : std_logic_vector(31 downto 0) := X"00000000";
constant C_CONDVAR_A : std_logic_vector(31 downto 0) := X"00000001";
constant C_MUTEX_B : std_logic_vector(31 downto 0) := X"00000002";
constant C_CONDVAR_B : std_logic_vector(31 downto 0) := X"00000003";
type t_state is ( STATE_MUTEX_A_LOCK,
STATE_CONDVAR_A_WAIT,
STATE_MUTEX_A_UNLOCK,
STATE_MUTEX_B_LOCK,
STATE_CONDVAR_B_SIGNAL,
STATE_MUTEX_B_UNLOCK);
signal state : t_state;
begin
state_proc: process( clk, reset )
variable done: boolean;
variable success: boolean;
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(31 downto 0);
variable counter : integer range 0 to 25000001;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_MUTEX_A_LOCK;
done := false;
success := false;
counter := 0;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_MUTEX_A_LOCK =>
reconos_mutex_lock(done, success, o_osif, i_osif, C_MUTEX_A);
if done then state <= STATE_CONDVAR_A_WAIT; end if;
when STATE_CONDVAR_A_WAIT =>
reconos_cond_wait(done, success, o_osif, i_osif, C_CONDVAR_A);
if done then state <= STATE_MUTEX_A_UNLOCK; end if;
when STATE_MUTEX_A_UNLOCK =>
reconos_mutex_unlock(o_osif, i_osif, C_MUTEX_A);
state <= STATE_MUTEX_B_LOCK;
when STATE_MUTEX_B_LOCK =>
reconos_mutex_lock(done, success, o_osif, i_osif, C_MUTEX_B);
if done then state <= STATE_CONDVAR_B_SIGNAL; end if;
when STATE_CONDVAR_B_SIGNAL =>
reconos_cond_signal(o_osif, i_osif, C_CONDVAR_B);
state <= STATE_MUTEX_B_UNLOCK;
when STATE_MUTEX_B_UNLOCK =>
reconos_mutex_unlock(o_osif, i_osif, C_MUTEX_B);
state <= STATE_MUTEX_A_LOCK;
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
95fd2c61984184ef9628958438fbc757
| 0.642882 | 2.943574 | false | false | false | false |
five-elephants/hw-neural-sampling
|
test_lfsr.vhdl
| 1 | 2,169 |
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
entity test_lfsr is
end test_lfsr;
architecture behave of test_lfsr is
constant num_rng : integer := 4;
constant width : integer := 8;
type state_array_t is array(1 to num_rng) of
std_logic_vector(width-1 downto 0);
subtype state_uns_t is unsigned(width+2-1 downto 0);
type state_uns_array_t is array(1 to num_rng) of
state_uns_t;
constant seeds : state_array_t := (
1 => "11111111",
2 => "00001111",
3 => "11110000",
4 => "00000001"
);
signal clk, reset : std_ulogic;
signal rand_out : state_array_t;
signal rng : state_uns_array_t;
signal sum : state_uns_t;
signal ctr : integer range 1 to width;
begin
clock_generation: process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
gen_rngs: for rng_i in 1 to num_rng generate
uut : entity work.lfsr
generic map (
width => width
)
port map (
clk => clk,
reset => reset,
seed => seeds(rng_i),
poly => "10111000",
rand_out => rand_out(rng_i)
);
rng(rng_i) <= "00" & unsigned(rand_out(rng_i));
end generate gen_rngs;
process (clk, reset)
begin
if reset = '1' then
ctr <= 1;
elsif rising_edge(clk) then
if ctr < width then
ctr <= ctr + 1;
else
ctr <= 1;
end if;
end if;
end process;
sum <= (rng(1) + rng(2)) + (rng(3) + rng(4)) when ctr = 1
else sum;
stimulus: process
variable l : line;
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait until clk'event and clk = '1';
write(l, string'("releasing reset"));
writeline(output, l);
for i in 0 to 19 loop
write(l, string'("rand_out = "));
for rng_i in 1 to num_rng loop
hwrite(l, rand_out(rng_i));
write(l, string'(" "));
end loop;
write(l, string'(" sum="));
write(l, std_logic_vector(sum));
writeline(output, l);
wait until rising_edge(clk);
end loop;
wait;
end process;
end behave;
|
apache-2.0
|
edde6fe7c43dd70c0e9e44a4d6ec3228
| 0.566621 | 3.256757 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/user_processes/uf_likelihood.vhd
| 1 | 13,314 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : L I K E L I H O O D
--
--
-- One observation and the reference data are loaded into the
-- local RAM by the framework. The start addresses of this
-- observations will be set as input from the Framework.
--
-- The user of the framework knows how a observation is defined.
-- The user defines how to calculate the likelihood between the
-- observation and the reference data.
--
-- If the likelihood is calculated, the finished signal has to
-- be set to '1' and the likelihood value has to be set as ouput.
--
------------------------------------------------------------------------------------
entity uf_likelihood is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the likelihood user process
observation_loaded : in std_logic;
-- address of reference data
ref_data_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- address of observation
observation_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- size of one observation
observation_size : in integer;
-- if the likelihood is calculated, this signal has to be set to '1'
finished : out std_logic;
likelihood_value : out integer
);
end uf_likelihood;
architecture Behavioral of uf_likelihood is
component square_root_component
port (
x_in : in std_logic_VECTOR(31 downto 0);
nd : in std_logic;
x_out : out std_logic_VECTOR(16 downto 0);
rdy : out std_logic;
rfd : out std_logic;
clk : in std_logic;
ce : in std_logic);
end component;
-- GRANULARITY
constant GRANULARITY : integer := 16384;
-- type for likelihood look up table
type likelihood_function is array ( 0 to 128) of integer;
-- likelihood look up table
-- constant likelihood_values : likelihood_function := (
-- 1, 1, 1, 1, 1, 1, 2, 2, 2, 3,
-- 3, 3, 4, 5, 5, 6, 7, 8, 9, 10,
-- 12, 13, 15, 17, 20, 22, 25, 29, 33, 37,
-- 42, 48, 54, 61, 70, 79, 90, 102, 115, 130,
-- 148, 168, 190, 215, 244, 277, 314, 356, 403, 457,
-- 518, 586, 665, 753, 854, 967, 1096, 1242, 1408, 1595,
-- 1808, 2048, 2321, 2630, 2980, 3377, 3827, 4337, 4914, 5569,
-- 6310, 7150, 8103, 9181, 10404, 11789, 13359, 15138, 17154, 19438,
-- 22026, 24959, 28282, 32048, 36315, 41150, 46630, 52838, 59874, 67846,
-- 76879, 87116, 98715, 111859, 126753, 143630, 162754, 184425, 208981, 236806,
-- 268337, 304065, 344551, 390428, 442413, 501320, 568070, 643707, 729416, 826537,
-- 936589, 1061294, 1202604, 1362729, 1544174, 1749778, 1982759, 2246760, 2545913, 2884897,
-- 3269017, 3704281, 4197501, 4756392, 5389698, 6107328, 6920509, 7841965, 8886110);
constant likelihood_values : likelihood_function := (
1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
2, 2, 2, 2, 3, 3, 3, 4, 4, 4,
5, 5, 6, 6, 7, 8, 8, 9, 10, 11,
12, 13, 14, 15, 17, 18, 20, 21, 23, 25,
28, 30, 33, 35, 39, 42, 46, 50, 54, 59,
64, 70, 76, 82, 90, 97, 106, 115, 125, 136,
148, 161, 175, 190, 207, 225, 244, 265, 289, 314,
341, 371, 403, 438, 476, 518, 563, 611, 665, 722,
785, 854, 928, 1008, 1096, 1191, 1295, 1408, 1530, 1663,
1808, 1965, 2135, 2321, 2523, 2742, 2980, 3240, 3521, 3827,
4160, 4521, 4914, 5341, 5806, 6310, 6859, 7455, 8103, 8807,
9572, 10404, 11308, 12291, 13359, 14520, 15782, 17154, 18644, 20265,
22026, 23940, 26021, 28282, 30740, 33411, 36315, 39471, 42901 );
-- LAMBDA
--constant LAMBDA : integer := 16.0;
-- local RAM addresses
signal current_ref_data_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal current_observation_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- signals for histogram values
signal ref_value : integer := 0;
signal observation_value : integer := 0;
-- sum of all values
signal sum : integer := 0;
-- root of sum
signal sum_root : integer := 0;
--signal pow : integer := 0;
signal sum_update : integer := 0;
signal likelihood : integer := 0;
-- states
type t_state is (STATE_INIT, STATE_LOAD_VALUES_DECISION, STATE_LOAD_VALUES_1,
STATE_LOAD_VALUES_2, STATE_LOAD_HIST_1, STATE_LOAD_HIST_2,
STATE_CALCULATE_SUM_UPDATE_1, STATE_CALCULATE_SUM_UPDATE_2,
STATE_CALCULATE_SUM_UPDATE_3, STATE_CALCULATE_SUM_UPDATE_4,
STATE_CALCULATE_SUM_UPDATE_5, STATE_CALCULATE_SUM_UPDATE_6,
STATE_UPDATE_SUM, STATE_CALCULATE_LIKELIHOOD_1,
STATE_CALCULATE_LIKELIHOOD_2, STATE_CALCULATE_LIKELIHOOD_3,
STATE_CALCULATE_LIKELIHOOD_4, STATE_CALCULATE_LIKELIHOOD_5,
STATE_CALCULATE_LIKELIHOOD_6, STATE_CALCULATE_LIKELIHOOD_7,
STATE_FINISH);
-- current state
signal state : t_state := STATE_INIT;
-- signals for square root component
signal x_in2 : natural := 0;
signal x_in3 : natural := 0;
signal x_in : std_logic_vector(31 downto 0) := (others => '0');
signal x_out : std_logic_vector(16 downto 0) := (others => '0');
signal x_out2: natural := 0;
signal x_out3: natural := 0;
signal nd : std_logic := '0';
signal rdy : std_logic := '1';
signal rfd : std_logic := '1';
signal ce : std_logic := '1';
begin
--! square root calculation
square_root: square_root_component
port map (x_in => x_in, nd => nd, x_out => x_out,
rdy => rdy, rfd => rfd, clk => clk, ce => ce);
-- burst ram interface
o_RAMWE <= '0';
o_RAMClk <= clk;
--
-- Likelihood calculation
--
-- 0) i = 0;
-- sum = 0.0;
--
-- 1) if ( i < 110 ) then
-- go to step 2
-- else
-- go to step 6
-- end if
--
-- 2) hist1 = reference_histogram[i]
--
-- 3) hist2 = observation_histogram[i]
--
-- 4) sum_update = sqrt ((hist1 * hist2) / GRANULARITY)
--
-- 5) sum += sum_update
-- i++
-- go to step 1
--
-- 6) likelihood = exp (- LAMBDA * (1.0 - sum))
--
ce <= enable;
state_proc : process(clk, reset)
begin
if (reset = '1') then
state <= STATE_INIT;
finished <= '0';
elsif rising_edge(clk) then
if init = '1' then
state <= STATE_INIT;
finished <= '0';
o_RAMData <= (others=>'0');
o_RAMAddr <= (others => '0');
elsif enable = '1' then
case state is
--! init data
when STATE_INIT =>
counter <= 0;
finished <= '0';
current_ref_data_address <= ref_data_address;
--sum <= 0.0;
sum <= 0;
current_observation_address <= observation_address;
if (observation_loaded = '1') then
state <= STATE_LOAD_VALUES_DECISION;
end if;
--! if not all histogram values are loaded and calculated, then do it.
-- Else calculate likelihood
when STATE_LOAD_VALUES_DECISION =>
if (counter < observation_size) then
state <= STATE_LOAD_VALUES_1;
else
state <= STATE_CALCULATE_LIKELIHOOD_1;
end if;
--! load histogram value 1 of 2
when STATE_LOAD_VALUES_1 =>
o_RAMAddr <= current_ref_data_address;
state <= STATE_LOAD_VALUES_2;
--! load histogram value 2 of 2
when STATE_LOAD_VALUES_2 =>
o_RAMAddr <= current_observation_address;
state <= STATE_LOAD_HIST_1;
--! load reference histogram value
when STATE_LOAD_HIST_1 =>
ref_value <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_LOAD_HIST_2;
--! load observation histogram value
when STATE_LOAD_HIST_2 =>
observation_value <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_CALCULATE_SUM_UPDATE_1;
--! calculate sum update (1 of 6): product = ref_hist * observation_hist
when STATE_CALCULATE_SUM_UPDATE_1 =>
--sum_update <= ref_value * observation_value;
--state <= STATE_UPDATE_SUM;
--! TODO: CHANGE BACK (1 of 1)
ref_value <= ref_value * observation_value;
state <= STATE_CALCULATE_SUM_UPDATE_2;
--! calculate sum update (2 of 6): sum_update = product
when STATE_CALCULATE_SUM_UPDATE_2 =>
--sum_update <= real(ref_value);
--sum_update <= ref_value;
x_in2 <= ref_value;
--if (rfd = '1') then
state <= STATE_CALCULATE_SUM_UPDATE_3;
--end if;
--! calculate sum update (3 of 6): get sqrt (1/3)
when STATE_CALCULATE_SUM_UPDATE_3 =>
--sum_update <= sum_update / GRANULARITY;
--sum_update <= sum_update / 512;
--state <= STATE_UPDATE_SUM;
x_in <= STD_LOGIC_VECTOR(TO_UNSIGNED(x_in2, 32));
nd <= '1';
state <= STATE_CALCULATE_SUM_UPDATE_4;
--! calculate sum update (4 of 6): get sqrt (2/3)
when STATE_CALCULATE_SUM_UPDATE_4 =>
--sum_update <= sqrt(sum_update);
nd <= '0';
if (rdy = '1') then
state <= STATE_CALCULATE_SUM_UPDATE_5;
end if;
--! calculate sum update (5 of 6): get sqrt (3/3)
when STATE_CALCULATE_SUM_UPDATE_5 =>
--sum_update <= sqrt(sum_update);
x_out2 <= TO_INTEGER(UNSIGNED(x_out));
state <= STATE_CALCULATE_SUM_UPDATE_6;
--! calculate sum update (6 of 6): sum_update = sqrt (ref_value * observation_value)
when STATE_CALCULATE_SUM_UPDATE_6 =>
--sum_update <= sqrt(sum_update);
-- needs correction
--sum_update <= ref_value;
-- CHANGE BACK (5 of 6) !!!
sum_update <= x_out2;
state <= STATE_UPDATE_SUM;
--! update sum (+= sum_update) and update counter and current addresses
when STATE_UPDATE_SUM =>
--sum <= sum + sum_update;
sum <= sum + sum_update;
counter <= counter + 1;
current_ref_data_address <= current_ref_data_address + 1;
current_observation_address <= current_observation_address + 1;
state <= STATE_LOAD_VALUES_DECISION;
--! calculate likelihood (1 of 7):
when STATE_CALCULATE_LIKELIHOOD_1 =>
x_in3 <= sum;
--pow <= sum / 2048;
--CHANGE BACK (6 of 6) !!!
--pow <= sum / 32;
state <= STATE_CALCULATE_LIKELIHOOD_2;
--! calculate likelihood (2 of 7):
when STATE_CALCULATE_LIKELIHOOD_2 =>
-------likelihood <= - LAMBDA * likelihood;
x_in <= STD_LOGIC_VECTOR(TO_UNSIGNED(x_in3, 32));
nd <= '1';
-- if (pow > 20) then
-- pow <= 20;
-- elsif (pow < 0) then
-- pow <= 0;
-- end if;
-- likelihood <= 1;
state <= STATE_CALCULATE_LIKELIHOOD_3;
--! calculate likelihood (3 of 7):
when STATE_CALCULATE_LIKELIHOOD_3 =>
nd <= '0';
if (rdy = '1') then
state <= STATE_CALCULATE_LIKELIHOOD_4;
end if;
-- if (pow > 0) then
--
-- likelihood <= likelihood * 3;
-- pow <= pow - 1;
-- else
--
-- state <= STATE_FINISH;
-- end if;
--likelihood <= exp(likelihood);
--likelihood <= 3**(likelihood/2048);
--state <= STATE_FINISH;
--! calculate likelihood (4 of 7):
when STATE_CALCULATE_LIKELIHOOD_4 =>
x_out3 <= TO_INTEGER(UNSIGNED(x_out));
state <= STATE_CALCULATE_LIKELIHOOD_5;
--! calculate likelihood (5 of 7):
when STATE_CALCULATE_LIKELIHOOD_5 =>
sum_root <= x_out3;
state <= STATE_CALCULATE_LIKELIHOOD_6;
--! calculate likelihood (6 of 7):
when STATE_CALCULATE_LIKELIHOOD_6 =>
if (sum_root > 128) then
sum_root <= 128;
elsif (sum_root < 0) then
sum_root <= 0;
end if;
state <= STATE_CALCULATE_LIKELIHOOD_7;
--! calculate likelihood (7 of 7):
when STATE_CALCULATE_LIKELIHOOD_7 =>
likelihood <= likelihood_values(sum_root);
state <= STATE_FINISH;
--! write finished signal and likelihood value
when STATE_FINISH =>
finished <= '1';
--likelihood_value <= integer(GRANULARITY * likelihood);
likelihood_value <= likelihood;
--likelihood_value <= 12;
if (observation_loaded = '1') then
state <= STATE_INIT;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
15ea2c32e9424e9e869a4d35bf138cc6
| 0.556632 | 3.444761 | false | false | false | false |
makestuff/vhdl
|
dpimfifo/fifo_generator_v5_1.vhd
| 1 | 5,731 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_generator_v5_1.vhd when simulating
-- the core, fifo_generator_v5_1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_generator_v5_1 IS
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END fifo_generator_v5_1;
ARCHITECTURE fifo_generator_v5_1_a OF fifo_generator_v5_1 IS
-- synthesis translate_off
component wrapped_fifo_generator_v5_1
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_generator_v5_1 use entity XilinxCoreLib.fifo_generator_v5_1(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 0,
c_implementation_type => 0,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_msgon_val => 1,
c_rd_depth => 1024,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 10,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 1,
c_rd_pntr_width => 10,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 10,
c_enable_rlocs => 0,
c_wr_pntr_width => 10,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 10,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 1021,
c_wr_depth => 1024,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 1022,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "1kx18",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_generator_v5_1
port map (
clk => clk,
din => din,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full);
-- synthesis translate_on
END fifo_generator_v5_1_a;
|
gpl-3.0
|
f1b16f0616de37d50b4d49c831801a62
| 0.548246 | 3.473333 | false | false | false | false |
luebbers/reconos
|
core/pcores/plb_osif_v2_03_a/hdl/vhdl/mem_plb34.vhd
| 1 | 13,813 |
--!
--! \file mem_plb34.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 08.12.2008 Enno Luebbers File created.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library plb_osif_v2_03_a;
use plb_osif_v2_03_a.all;
entity mem_plb34 is
generic
(
C_SLAVE_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_BURST_BASEADDR : std_logic_vector := X"00004000"; -- system memory base address for burst ram access
C_BURSTLEN_WIDTH : integer := 5
);
port
(
clk : in std_logic;
reset : in std_logic;
-- data interface ---------------------------
-- burst mem interface
o_burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_burstData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
i_burstData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
o_burstWE : out std_logic;
o_burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- single word data input/output
i_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- osif2bus
o_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- bus2osif
-- control interface ------------------------
-- addresses for master transfers
i_localAddr : in std_logic_vector(0 to C_AWIDTH-1);
i_targetAddr : in std_logic_vector(0 to C_AWIDTH-1);
-- single word transfer requests
i_singleRdReq : in std_logic;
i_singleWrReq : in std_logic;
-- burst transfer requests
i_burstRdReq : in std_logic;
i_burstWrReq : in std_logic;
i_burstLen : in std_logic_vector(0 to C_BURSTLEN_WIDTH-1); -- number of burst beats (n x 64 bits)
-- status outputs
o_busy : out std_logic;
o_rdDone : out std_logic;
o_wrDone : out std_logic;
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH - 1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_DataX : in std_logic_vector(C_DWIDTH to C_PLB_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_DataX : out std_logic_vector(C_DWIDTH to C_PLB_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity mem_plb34;
architecture arch of mem_plb34 is
---------
-- read/write acknowledge
---------
signal ram_IP2Bus_RdAck : std_logic;
signal ram_IP2Bus_WrAck : std_logic;
signal slv_IP2Bus_RdAck : std_logic;
signal slv_IP2Bus_WrAck : std_logic;
signal slv_rddata : std_logic_vector(0 to C_DWIDTH-1);
begin
-----------------------------------------------------------------------
-- bus_master_inst: bus master instantiation
--
-- The bus_master module is responsible for initiating a bus read or
-- write transaction through the IPIF master services. The actual
-- transaction will appear like a bus initiated slave request at the
-- IPIF slave attachment and is therefore handled by bus_slave_regs
-- or the bus2burst process.
-----------------------------------------------------------------------
bus_master_inst : entity plb_osif_v2_03_a.bus_master
generic map (
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_SLAVE_BASEADDR => C_SLAVE_BASEADDR,
C_BURST_BASEADDR => C_BURST_BASEADDR,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH
)
port map (
clk => clk,
reset => reset,
-- PLB bus master signals
Bus2IP_MstError => Bus2IP_MstError,
Bus2IP_MstLastAck => Bus2IP_MstLastAck,
Bus2IP_MstRdAck => Bus2IP_MstRdAck,
Bus2IP_MstWrAck => Bus2IP_MstWrAck,
Bus2IP_MstRetry => Bus2IP_MstRetry,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut,
IP2Bus_Addr => IP2Bus_Addr,
IP2Bus_MstBE => IP2Bus_MstBE,
IP2Bus_MstBurst => IP2Bus_MstBurst,
IP2Bus_MstBusLock => IP2Bus_MstBusLock,
IP2Bus_MstNum => IP2Bus_MstNum,
IP2Bus_MstRdReq => IP2Bus_MstRdReq,
IP2Bus_MstWrReq => IP2Bus_MstWrReq,
IP2IP_Addr => IP2IP_Addr,
-- user interface
i_target_addr => i_targetAddr,
i_my_addr => i_localAddr,
i_read_req => i_singleRdReq,
i_write_req => i_singleWrReq,
i_burst_read_req => i_burstRdReq,
i_burst_write_req => i_burstWrReq,
i_burst_length => i_burstLen,
o_busy => o_busy,
o_read_done => o_rdDone,
o_write_done => o_wrDone
);
-----------------------------------------------------------------------
-- bus_slave_regs_inst: PLB bus slave instatiation
--
-- Handles access to the shared memory register
-- Used for single word memory accesses
-- (e.g. reconos_read() and reconos_write())
-----------------------------------------------------------------------
bus_slave_regs_inst : entity plb_osif_v2_03_a.bus_slave_regs
generic map (
C_DWIDTH => C_DWIDTH,
C_NUM_REGS => C_NUM_CE-1
)
port map (
clk => Bus2IP_Clk,
reset => Bus2IP_Reset,
-- bus slave signals
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE(0 to (C_DWIDTH/8)-1),
Bus2IP_RdCE => Bus2IP_RdCE(0 to C_NUM_CE-2),
Bus2IP_WrCE => Bus2IP_WrCE(0 to C_NUM_CE-2),
IP2Bus_Data => slv_RdData,
IP2Bus_RdAck => slv_IP2Bus_RdAck,
IP2Bus_WrAck => slv_IP2Bus_WrAck,
-- user registers
slv_osif2bus_shm => i_singleData,
slv_bus2osif_shm => o_singleData
);
-- read/write acknowledge
IP2Bus_RdAck <= slv_IP2Bus_RdAck or ram_IP2Bus_RdAck;
IP2Bus_WrAck <= slv_IP2Bus_WrAck or ram_IP2Bus_WrAck;
-- no error handling / retry / timeout
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
-- multiplex data, if PLB connected
IP2Bus_Data <= i_burstData(0 to C_DWIDTH-1) when ram_IP2Bus_RdAck = '1' else slv_RdData;
IP2Bus_DataX <= i_burstData(C_DWIDTH to C_PLB_DWIDTH-1);
o_burstData <= Bus2IP_Data & Bus2IP_DataX;
-- burstWE <= ram_IP2Bus_WrAck and Bus2IP_WrReq;
o_burstBE <= Bus2IP_BE;
-------------------------------------------------------------------
-- bus2burst: handles bus accesses to burst memory
--
-- supports both single and burst accesses
-------------------------------------------------------------------
bus2burst : process(Bus2IP_Clk, Bus2IP_Reset)
type ram_state_t is (IDLE, BURST_READ, BURST_WRITE, SINGLE_READ);
variable ram_state : ram_state_t;
variable start_addr : std_logic_vector(0 to C_BURST_AWIDTH-1);
variable counter : natural := 0;
begin
if Bus2IP_Reset = '1' then
ram_state := IDLE;
start_addr := (others => '0');
counter := 0;
ram_IP2Bus_RdAck <= '0';
ram_IP2Bus_WrAck <= '0';
o_burstAddr <= (others => '0');
o_burstWE <= '0';
elsif rising_edge(Bus2IP_Clk) then
case ram_state is
when IDLE =>
counter := 0;
o_burstWE <= '0';
ram_IP2Bus_RdAck <= '0';
ram_IP2Bus_WrAck <= '0';
-- if Bus2IP_RdReq = '1' then
if Bus2IP_RdCE(1) = '1' and Bus2IP_RdReq = '1' then
if Bus2IP_Burst = '1' then
start_addr := Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1); -- get burst start address
o_burstAddr <= start_addr + counter*8;
ram_state := BURST_READ;
else
o_burstAddr <= Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1);
ram_state := SINGLE_READ;
end if;
-- elsif Bus2IP_WrReq = '1' then
elsif Bus2IP_WrCE(1) = '1'and Bus2IP_WrReq = '1' then
if Bus2IP_Burst = '1' then
start_addr := Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1); -- get burst start address
o_burstAddr <= start_addr + counter*8;
ram_IP2Bus_WrAck <= '1';
o_burstWE <= '1';
ram_state := BURST_WRITE;
else
o_burstAddr <= Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1);
ram_IP2Bus_WrAck <= '1';
o_burstWE <= '1';
ram_state := IDLE;
end if;
end if;
when BURST_READ =>
ram_IP2Bus_RdAck <= '1';
counter := counter + 1;
if Bus2IP_Burst = '0' then -- Bus2IP_Burst is deasserted at the second to last data beat
ram_IP2Bus_RdAck <= '0';
ram_state := IDLE;
end if;
o_burstAddr <= start_addr + counter*8;
when BURST_WRITE =>
counter := counter + 1;
if Bus2IP_Burst = '0' then -- Bus2IP_Burst is deasserted at the second to last data beat
ram_IP2Bus_WrAck <= '0';
o_burstWE <= '0';
ram_state := IDLE;
end if;
o_burstAddr <= start_addr + counter*8;
when SINGLE_READ =>
ram_IP2Bus_RdAck <= '1';
ram_state := IDLE;
end case;
end if;
end process;
end arch;
|
gpl-3.0
|
65c4e00aebc3379ace0364e4667925a5
| 0.482516 | 3.915249 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/TWICtl.vhd
| 1 | 19,962 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: TWIUtils - Package
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-- Description: This package provides enumeration types for TWI (Two-Wire
-- Interface) bus status and error conditions.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
package TWIUtils is
type busState_type is (busUnknown, busBusy, busFree);
type error_type is (errArb, errNAck);
end TWIUtils;
package body TWIUtils is
end TWIUtils;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: TWICtl - Behavioral
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-- Description: TWICtl is a reusabled Master Controller implementation of the
-- TWI protocol. It uses 7-bit addressing and was tested in STANDARD I2C mode.
-- FAST mode should also be theoretically possible, although it has not been
-- tested. It adheres to arbitration rules, thus supporting multi-master TWI
-- buses. Slave-wait is also supported.
--
--
-- Dependencies: digilent.TWIUtils package - TWICtl.vhd
--
-- Revision:
-- Revision 1.02 - Added bus unblock function
-- Revision 1.01 - Bugfix: stop condition might be prevented device read
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
-- Use the package defined above
use work.TWIUtils.ALL;
entity TWICtl is
----------------------------------------------------------------------------------
-- Title : Mode of operation
-- Description: The controller can be instructed to initiate/continue/stop a
-- data transfer using the strobe (STB_I, MSG_I) signals. Data flow management is
-- provided by the done (DONE_O) and error (ERR_O, ERRTYPE_O) signals. Output
-- signals are synchronous to CLK and input signals must also be synchronous to
-- CLK. Signals are active-high.
-- Fast-track instructions (single byte transfer):
-- -put the TWI address on A_I
-- -if data is written put it on D_I
-- -assert STB_I
-- -when DONE_O pulse arrives, read data is present on D_O, if any
-- -repeat, or deassert STB_I
-- Detailed data transfer flow:
-- -when DONE_O is low, the controller is ready to accept commands
-- -data transfer can be initiated by putting a TWI slave address on the A_I
-- bus and providing a strobe (STB_I)
-- -the direction of data transfer (read/write) is determined by the LSB of the
-- address (0-write, 1-read)
-- -in case of a 'write' the data byte should also be present on the D_I bus
-- prior to the arrival of the strobe (STB_I)
-- -once the data byte gets read/written, DONE_I pulses high for one CLK cycle
-- -in case of an error, ERR_O will pulse high together with DONE_I; ERR_O low
-- together with DONE_I high indicates success
-- -after DONE_I pulses high there is a 1/4 TWI period time frame when the next
-- strobe can be sent; this is useful, when multiple bytes are sent/received
-- in a single transfer packet; for ex. for write transfers, a new byte can
-- be put on the D_I and STB_I provided;
-- -if no new strobe is provided, the transfer will end
-- -if a new strobe is provided, but the address changed, the current transfer
-- will end and a new will begin
-- -starting a new transfer can be forced with the MSG_I pin; if asserted with
-- a strobe, the data byte will be written/read in a new packet; the advantage
-- of this is relevant only in multi-master buses: rather than waiting for the
-- current transfer to end and the bus to be released, a new transfer can be
-- initiated without giving up the control over the bus
----------------------------------------------------------------------------------
generic (
CLOCKFREQ : natural := 50;
ATTEMPT_SLAVE_UNBLOCK : boolean := false --setting this true will attempt
--to drive a few clock pulses for a slave to allow to finish a previous
--interrupted read transfer, otherwise the bus might remain locked up
); -- input CLK frequency in MHz
port (
MSG_I : in STD_LOGIC; --new message
STB_I : in STD_LOGIC; --strobe
A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
DONE_O : out STD_LOGIC; --done status signal
ERR_O : out STD_LOGIC; --error status
ERRTYPE_O : out error_type; --error type
CLK : in std_logic;
SRST : in std_logic;
----------------------------------------------------------------------------------
-- TWI bus signals
----------------------------------------------------------------------------------
SDA : inout std_logic; --TWI SDA
SCL : inout std_logic --TWI SCL
);
end TWICtl;
architecture Behavioral of TWICtl is
attribute fsm_encoding: string;
constant FSCL : natural := 400_000; --in Hz SCL clock frequency
constant TIMEOUT : natural := 10; --in ms TWI timeout for slave wait period
constant TSCL_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*1_000_000/FSCL)));
constant TIMEOUT_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*TIMEOUT*1_000)));
type state_type is (stIdle, stStart, stRead, stWrite, stError, stStop,
stSAck, stMAck, stMNAckStop, stMNAckStart, stStopError);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal sync_sda, sync_scl : std_logic_vector(2 downto 0);
signal dSda, ddSda, dScl : std_logic;
signal fStart, fStop : std_logic;
signal busState : busState_type := busUnknown;
signal errTypeR, errType : error_type;
signal busFreeCnt, sclCnt : natural range TSCL_CYCLES downto 0 := TSCL_CYCLES;
signal timeOutCnt : natural range TIMEOUT_CYCLES downto 0 := TIMEOUT_CYCLES;
signal slaveWait, arbLost : std_logic;
signal dataByte, loadByte, currAddr : std_logic_vector(7 downto 0); --shift register and parallel load
signal rSda, rScl : std_logic := '1';
signal subState : std_logic_vector(1 downto 0) := "00";
signal latchData, latchAddr, iDone, iErr, iSda, iScl, shiftBit, dataBitOut, rwBit, addrNData : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal int_Rst : std_logic := '0';
begin
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
SYNC_FFS: process(CLK)
begin
if Rising_Edge(CLK) then
sync_sda(0) <= SDA;
sync_sda(1) <= sync_sda(0);
sync_sda(2) <= sync_sda(1);
sync_scl(0) <= SCL;
sync_scl(1) <= sync_scl(0);
sync_scl(2) <= sync_scl(1);
end if;
end process;
dSda <= sync_sda(1);
ddSda <= sync_sda(2);
dScl <= sync_scl(1);
fStart <= dScl and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dScl and dSda and not ddSda; --if SCL high while SDA rising, stop condition
TWISTATE: process(CLK)
begin
if Rising_Edge(CLK) then
if (int_Rst = '1') then
busState <= busUnknown;
elsif (fStart = '1') then --If START condition detected, bus is busy
busState <= busBusy;
elsif (busFreeCnt = 0) then --We counted down tBUF, so it must be free
busState <= busFree;
end if;
end if;
end process;
TBUF_CNT: process(CLK)
begin
if Rising_Edge(CLK) then
if (dSCL = '0' or dSDA = '0' or int_Rst = '1') then
busFreeCnt <= TSCL_CYCLES;
elsif (dSCL = '1' and dSDA = '1') then
busFreeCnt <= busFreeCnt - 1; --counting down 1 SCL period on free bus
end if;
end if;
end process;
----------------------------------------------------------------------------------
--Slave devices can insert wait states by keeping SCL low
----------------------------------------------------------------------------------
slaveWait <= '1' when (dSCL = '0' and rScl = '1') else
'0';
----------------------------------------------------------------------------------
--If the SDA line does not correspond to the transmitted data while the SCL line
--is at the HIGH level the master lost an arbitration to another master.
----------------------------------------------------------------------------------
arbLost <= '1' when (dSCL = '1' and dSDA = '0' and rSda = '1') else
'0';
----------------------------------------------------------------------------------
-- Internal reset signal
----------------------------------------------------------------------------------
RST_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle and SRST = '0') then
int_Rst <= '0';
elsif (SRST = '1') then
int_Rst <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- SCL period counter
----------------------------------------------------------------------------------
SCL_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (sclCnt = 0 or state = stIdle) then
sclCnt <= TSCL_CYCLES/4;
elsif (slaveWait = '0') then -- clock synchronization with other masters
sclCnt <= sclCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Slave timeout to determine a locked-up bus
----------------------------------------------------------------------------------
UnblockTimeout: if ATTEMPT_SLAVE_UNBLOCK generate
TIMEOUT_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (state /= stIdle or busState = busFree or ((ddSda xor dSda) = '1')) then
timeOutCnt <= TIMEOUT_CYCLES;
else
timeOutCnt <= timeOutCnt - 1;
end if;
end if;
end process;
end generate;
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (CLK)
begin
if Rising_Edge(CLK) then
if ((latchData = '1' or latchAddr = '1') and sclCnt = 0) then
dataByte <= loadByte; --latch address/data
bitCount <= 7;
--set flag so that we know what is the byte we are sending
if (latchData = '1') then
addrNData <= '0';
else
addrNData <= '1';
end if;
elsif (shiftBit = '1' and sclCnt = 0) then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
loadByte <= A_I when latchAddr = '1' else
D_I;
dataBitOut <= dataByte(dataByte'high);
D_O <= dataByte;
----------------------------------------------------------------------------------
-- Title: Current address register
-- Description: Stores the TWI slave address
----------------------------------------------------------------------------------
CURRADDR_REG: process (CLK)
begin
if Rising_Edge(CLK) then
if (latchAddr = '1') then
currAddr <= A_I; --latch address/data
end if;
end if;
end process;
rwBit <= currAddr(0);
----------------------------------------------------------------------------------
-- Title: Substate counter
-- Description: Divides each state into 4, to respect the setup and hold times of
-- the TWI bus.
----------------------------------------------------------------------------------
SUBSTATE_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle) then
subState <= "00";
elsif (sclCnt = 0) then
subState <= subState + 1;
end if;
end if;
end process;
SYNC_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
state <= nstate;
rSda <= iSda;
rScl <= iScl;
if (int_Rst = '1') then
DONE_O <= '0';
ERR_O <= '0';
errTypeR <= errType;
else
DONE_O <= iDone;
ERR_O <= iErr;
errTypeR <= errType;
end if;
end if;
end process;
OUTPUT_DECODE: process (nstate, subState, state, errTypeR, dataByte(0),
sclCnt, bitCount, rSda, rScl, dataBitOut, arbLost, dSda, addrNData)
begin
iSda <= rSda; --no change by default
iScl <= rScl;
iDone <= '0';
iErr <= '0';
errType <= errTypeR; --keep error type
shiftBit <= '0';
latchAddr <= '0';
latchData <= '0';
if (state = stStart) then
case (subState) is
when "00" =>
iSda <= '1';
--keep SCL
when "01" =>
iSda <= '1';
iScl <= '1';
when "10" =>
iSda <= '0';
iScl <= '1';
when "11" =>
iSda <= '0';
iScl <= '0';
when others =>
end case;
end if;
if (state = stStop or state = stStopError) then
case (subState) is
when "00" =>
iSda <= '0';
--keep SCL
when "01" =>
iSda <= '0';
iScl <= '1';
when "10" =>
iSda <= '1';
iScl <= '1';
when "11" => --we will only reach this is there is an arbitration error
--keep SDA;
iScl <= '0'; --need to toggle clock
when others =>
end case;
end if;
if (state = stRead or state = stSAck) then
case (subState) is
when "00" =>
iSda <= '1'; --this will be 'Z' on SDA
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stWrite) then
case (subState) is
when "00" =>
iSda <= dataBitOut;
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMAck) then
case (subState) is
when "00" =>
iSda <= '0'; -- acknowledge by writing 0
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMNAckStop or state = stMNAckStart) then
case (subState) is
when "00" =>
iSda <= '1'; -- not acknowledge by writing 1
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stSAck and sclCnt = 0 and subState = "01") then
if (dSda = '1') then
iDone <= '1';
iErr <= '1'; --not acknowledged
errType <= errNAck;
elsif (addrNData = '0') then
--we are done only when the data is sent too after the address
iDone <= '1';
end if;
end if;
if (state = stRead and subState = "01" and sclCnt = 0 and bitCount = 0) then
iDone <= '1'; --read done
end if;
if (state = stWrite and arbLost = '1') then
iDone <= '1'; --write done
iErr <= '1'; --we lost the arbitration
errType <= errArb;
end if;
if ((state = stWrite and sclCnt = 0 and subState = "11") or --shift at end of bit
((state = stSAck or state = stRead) and subState = "01")) then --read in middle of bit
shiftBit <= '1';
end if;
if (state = stStart) then
latchAddr <= '1';
end if;
if (state = stSAck and subState = "11") then --get the data byte for the next write
latchData <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, busState, slaveWait, arbLost, STB_I, MSG_I,
SRST, subState, bitCount, int_Rst, dataByte, A_I, currAddr, rwBit, sclCnt, addrNData)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (STB_I = '1' and busState = busFree and SRST = '0') then
nstate <= stStart;
elsif (ATTEMPT_SLAVE_UNBLOCK and timeOutCnt = 0) then
nstate <= stStop;
end if;
when stStart =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (arbLost = '1') then
nstate <= stIdle;
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11" and bitCount = 0) then
nstate <= stSAck;
end if;
end if;
when stSAck =>
if (sclCnt = 0) then
if (int_Rst = '1' or (subState = "11" and dataByte(0) = '1')) then
nstate <= stStop;
elsif (subState = "11") then
if (addrNData = '1') then --if we have just sent the address, tx/rx the data too
if (rwBit = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
elsif (STB_I = '1') then
if (MSG_I = '1' or currAddr /= A_I) then
nstate <= stStart;
else
if (rwBit = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
else
nstate <= stStop;
end if;
end if;
end if;
when stStop =>
--bugfix: if device is driving SDA low (read transfer) we cannot send stop bit
--check the arbitration flag
if (subState = "10" and sclCnt = 0 and arbLost = '0') then
nstate <= stIdle;
end if;
--stay here, if stop bit cannot be sent, pulse clock an retry
when stRead =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11" and bitCount = 7) then --bitCount will underflow
if (STB_I = '1') then
if (MSG_I = '1' or currAddr /= A_I) then
nstate <= stMNAckStart;
else
nstate <= stMAck;
end if;
else
nstate <= stMNAckStop;
end if;
end if;
end if;
when stMAck =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stRead;
end if;
end if;
when stMNAckStart =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stStart;
end if;
end if;
when stMNAckStop =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stStop;
end if;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA <= 'Z' when rSDA = '1' else
'0';
SCL <= 'Z' when rSCL = '1' else
'0';
end Behavioral;
|
gpl-3.0
|
525f1e23c09b514ba49854ac95b7bcd2
| 0.525999 | 3.801562 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/inferred_sync_fifo.vhd
| 1 | 8,223 |
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo_std.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2013-11-14
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity inferred_sync_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_empty : boolean := true; -- with empty flag
g_with_full : boolean := true; -- with full flag
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false; -- with words counter
g_almost_empty_threshold : integer := 0; -- threshold for almost empty flag
g_almost_full_threshold : integer := 0; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end inferred_sync_fifo;
architecture syn of inferred_sync_fifo is
constant c_pointer_width : integer := f_log2_size(g_size);
signal rd_ptr, wr_ptr, wr_ptr_d0, rd_ptr_muxed : unsigned(c_pointer_width-1 downto 0);
signal usedw : unsigned(c_pointer_width downto 0);
signal full, empty : std_logic;
signal q_int : std_logic_vector(g_data_width-1 downto 0);
signal we_int, rd_int : std_logic;
signal guard_bit : std_logic;
signal q_reg, q_comb : std_logic_vector(g_data_width-1 downto 0);
begin -- syn
--assert g_show_ahead = false report "Show ahead mode not implemented (yet). Sorry" severity failure;
we_int <= we_i and not full;
rd_int <= rd_i and not empty;
U_FIFO_Ram : generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
wea_i => we_int,
aa_i => std_logic_vector(wr_ptr(c_pointer_width-1 downto 0)),
da_i => d_i,
clkb_i => '0',
ab_i => std_logic_vector(rd_ptr_muxed(c_pointer_width-1 downto 0)),
qb_o => q_comb);
p_output_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rd_int = '1' then
q_reg <= q_comb;
end if;
end if;
end process;
process(rd_ptr, rd_i, rd_int)
begin
if(rd_int = '1' and g_show_ahead) then
rd_ptr_muxed <= rd_ptr + 1;
elsif((rd_int = '1' and not g_show_ahead) or (g_show_ahead)) then
rd_ptr_muxed <= rd_ptr;
else
rd_ptr_muxed <= rd_ptr - 1;
end if;
end process;
-- q_o <= q_comb when g_show_ahead = true else q_reg;
q_o <= q_comb;
p_pointers : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ptr <= (others => '0');
rd_ptr <= (others => '0');
else
if(we_int = '1') then
wr_ptr <= wr_ptr + 1;
end if;
if(rd_int = '1') then
rd_ptr <= rd_ptr + 1;
end if;
end if;
end if;
end process;
gen_comb_flags_showahead : if(g_show_ahead = true) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if ((rd_ptr + 1 = wr_ptr and rd_int = '1') or (rd_ptr = wr_ptr)) then
empty <= '1';
else
empty <= '0';
end if;
end if;
end process;
full <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
end generate gen_comb_flags_showahead;
gen_comb_flags : if(g_register_flag_outputs = false and g_show_ahead = false) generate
empty <= '1' when (wr_ptr = rd_ptr and guard_bit = '0') else '0';
full <= '1' when (wr_ptr = rd_ptr and guard_bit = '1') else '0';
p_guard_bit : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
guard_bit <= '0';
elsif(wr_ptr + 1 = rd_ptr and we_int = '1') then
guard_bit <= '1';
elsif(rd_i = '1') then
guard_bit <= '0';
end if;
end if;
end process;
end generate gen_comb_flags;
gen_registered_flags : if(g_register_flag_outputs = true and g_show_ahead = false) generate
p_reg_flags : process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
full <= '0';
empty <= '1';
else
if(usedw = 1 and rd_int = '1' and we_int = '0') then
empty <= '1';
elsif(we_int = '1' and rd_int = '0') then
empty <= '0';
end if;
if(usedw = g_size-2 and we_int = '1' and rd_int = '0') then
full <= '1';
elsif(usedw = g_size-1 and rd_int = '1' and we_int = '0') then
full <= '0';
end if;
end if;
end if;
end process;
end generate gen_registered_flags;
gen_with_word_counter : if(g_with_count or g_with_almost_empty or g_with_almost_full or g_register_flag_outputs) generate
p_usedw_counter : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
usedw <= (others => '0');
else
if(we_int = '1' and rd_int = '0') then
usedw <= usedw + 1;
elsif(we_int = '0' and rd_int = '1') then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
count_o <= std_logic_vector(usedw(c_pointer_width-1 downto 0));
end generate gen_with_word_counter;
gen_with_almost_full : if(g_with_almost_full) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
almost_full_o <= '0';
else
if(usedw = g_almost_full_threshold-1) then
if(we_int = '1' and rd_int = '0') then
almost_full_o <= '1';
elsif(rd_int = '1' and we_int = '0') then
almost_full_o <= '0';
end if;
end if;
end if;
end if;
end process;
end generate gen_with_almost_full;
gen_with_almost_empty : if(g_with_almost_empty) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
almost_empty_o <= '1';
else
if(usedw = g_almost_empty_threshold+1) then
if(rd_int = '1' and we_int = '0') then
almost_empty_o <= '1';
elsif(we_int = '1' and rd_int = '0') then
almost_empty_o <= '0';
end if;
end if;
end if;
end if;
end process;
end generate gen_with_almost_empty;
full_o <= full;
empty_o <= empty;
end syn;
|
lgpl-3.0
|
e050e67307d5ffb0c9bd08447d2459a1
| 0.497872 | 3.381168 | false | false | false | false |
bzero/freezing-spice
|
src/id_pkg.vhd
| 2 | 3,968 |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.common.all;
package id_pkg is
type id_in is record
instruction : word;
end record id_in;
-- structure for decoded instruction
type id_out is record
alu_func : alu_func_t;
op2_src : std_logic;
insn_type : insn_type_t;
branch_type : branch_type_t;
load_type : load_type_t;
store_type : store_type_t;
rs1 : std_logic_vector(4 downto 0);
rs2 : std_logic_vector(4 downto 0);
rd : std_logic_vector(4 downto 0);
imm : word;
opcode : std_logic_vector(6 downto 0);
rs1_rd : std_logic;
rs2_rd : std_logic;
use_imm : std_logic;
rf_we : std_logic;
end record id_out;
constant c_decoded_reset : id_out := (alu_func => ALU_NONE,
op2_src => '0',
insn_type => OP_ILLEGAL,
branch_type => BRANCH_NONE,
load_type => LOAD_NONE,
store_type => STORE_NONE,
rs1 => "00000",
rs2 => "00000",
rd => "00000",
imm => (others => '0'),
opcode => (others => 'X'),
rs1_rd => '0',
rs2_rd => '0',
use_imm => '0',
rf_we => '0');
-- Constants
constant c_op_load : std_logic_vector(6 downto 0) := "0000011";
constant c_op_misc_mem : std_logic_vector(6 downto 0) := "0001111";
constant c_op_imm : std_logic_vector(6 downto 0) := "0010011";
constant c_op_auipc : std_logic_vector(6 downto 0) := "0010111";
constant c_op_store : std_logic_vector(6 downto 0) := "0100011";
constant c_op_reg : std_logic_vector(6 downto 0) := "0110011";
constant c_op_lui : std_logic_vector(6 downto 0) := "0110111";
constant c_op_branch : std_logic_vector(6 downto 0) := "1100011";
constant c_op_jalr : std_logic_vector(6 downto 0) := "1100111";
constant c_op_jal : std_logic_vector(6 downto 0) := "1101111";
constant c_op_system : std_logic_vector(6 downto 0) := "1110011";
procedure print_insn (insn_type : in insn_type_t);
end package id_pkg;
package body id_pkg is
procedure print_insn (insn_type : in insn_type_t) is
variable l : line;
begin
write(l, string'("Instruction type: "));
if insn_type = OP_LUI then
write(l, string'("LUI"));
writeline(output, l);
elsif insn_type = OP_AUIPC then
write(l, string'("AUIPC"));
writeline(output, l);
elsif insn_type = OP_JAL then
write(l, string'("JAL"));
writeline(output, l);
elsif insn_type = OP_JALR then
write(l, string'("JALR"));
writeline(output, l);
elsif insn_type = OP_BRANCH then
write(l, string'("BRANCH"));
writeline(output, l);
elsif insn_type = OP_LOAD then
write(l, string'("LOAD"));
writeline(output, l);
elsif insn_type = OP_STORE then
write(l, string'("STORE"));
writeline(output, l);
elsif insn_type = OP_ALU then
write(l, string'("ALU"));
writeline(output, l);
else
write(l, string'("ILLEGAL"));
writeline(output, l);
end if;
end procedure print_insn;
end package body id_pkg;
|
bsd-3-clause
|
b48ac59413078ba92c8708c1e486cc2d
| 0.456149 | 4.04898 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.vhdl
| 1 | 8,108 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sat Jun 4 16:53:15 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.vhdl
-- Design : ClockDivider
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider_ClockDivider_clk_wiz is
port (
clk : in STD_LOGIC;
clk_vga : out STD_LOGIC;
clk_cpu : out STD_LOGIC;
clk_2cpu : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ClockDivider_ClockDivider_clk_wiz : entity is "ClockDivider_clk_wiz";
end ClockDivider_ClockDivider_clk_wiz;
architecture STRUCTURE of ClockDivider_ClockDivider_clk_wiz is
signal clk_2cpu_ClockDivider : STD_LOGIC;
signal clk_ClockDivider : STD_LOGIC;
signal clk_cpu_ClockDivider : STD_LOGIC;
signal clk_vga_ClockDivider : STD_LOGIC;
signal clkfbout_ClockDivider : STD_LOGIC;
signal clkfbout_buf_ClockDivider : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ClockDivider,
O => clkfbout_buf_ClockDivider
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk,
O => clk_ClockDivider
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_vga_ClockDivider,
O => clk_vga
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_cpu_ClockDivider,
O => clk_cpu
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => clk_2cpu_ClockDivider,
O => clk_2cpu
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 54.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 120,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 60,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ClockDivider,
CLKFBOUT => clkfbout_ClockDivider,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_ClockDivider,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_vga_ClockDivider,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_cpu_ClockDivider,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => clk_2cpu_ClockDivider,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider is
port (
clk : in STD_LOGIC;
clk_vga : out STD_LOGIC;
clk_cpu : out STD_LOGIC;
clk_2cpu : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ClockDivider : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ClockDivider : entity is "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end ClockDivider;
architecture STRUCTURE of ClockDivider is
begin
inst: entity work.ClockDivider_ClockDivider_clk_wiz
port map (
clk => clk,
clk_2cpu => clk_2cpu,
clk_cpu => clk_cpu,
clk_vga => clk_vga
);
end STRUCTURE;
|
mit
|
d9dee9aabd55a4e54d874bb796b664ab
| 0.656142 | 3.543706 | false | false | false | false |
luebbers/reconos
|
tests/automated/burstlen/hw/hwthreads/burstlen/hwt_burstlen.vhd
| 1 | 5,066 |
--!
--! \file hwt_burstlen.vhd
--!
--! Automated test for variable burstlengths (reconos_burst_read_/write_l)
--!
--! \author Enno Luebbers <[email protected]>
--! \date 27.06.2008
--
-- Adapted from hwt_memcopy.vhd (Andreas Agne).
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2008. Permission to copy,
-- use, modify, sell and distribute this software is granted provided
-- this copyright notice appears in all copies. This software is
-- provided "as is" without express or implied warranty, and with no
-- claim as to its suitability for any purpose.
--
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 27.06.2008 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_burstlen is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_burstlen is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
type t_state is ( STATE_INIT,
STATE_READ_SRC,
STATE_READ_DST,
STATE_READ_SIZE,
STATE_READ_BURSTLEN,
STATE_READ_STEP,
STATE_READ_BURST,
STATE_WRITE_BURST,
STATE_DONE,
STATE_FINAL);
signal state : t_state;
begin
state_proc: process( clk, reset )
variable args : std_logic_vector(31 downto 0);
variable src : std_logic_vector(31 downto 0);
variable dst : std_logic_vector(31 downto 0);
variable size : std_logic_vector(31 downto 0);
variable burstlen_slv : std_logic_vector(31 downto 0);
variable burstlen : natural range 0 to 16;
variable step : std_logic_vector(31 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
args := (others => '0');
src := (others => '0');
dst := (others => '0');
size := (others => '0');
burstlen_slv := (others => '0');
burstlen := 0;
step := (others => '0');
tmp := (others => '0');
done := false;
success := false;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, args);
if done then state <= STATE_READ_SRC; end if;
when STATE_READ_SRC =>
reconos_read(done, o_osif, i_osif, args, src);
if done then state <= STATE_READ_DST; end if;
when STATE_READ_DST =>
reconos_read(done, o_osif, i_osif, args + 4, dst);
if done then state <= STATE_READ_SIZE; end if;
when STATE_READ_SIZE =>
reconos_read(done, o_osif, i_osif, args + 8, size);
if done then state <= STATE_READ_BURSTLEN; end if;
when STATE_READ_BURSTLEN =>
reconos_read(done, o_osif, i_osif, args + 12, burstlen_slv);
burstlen := CONV_INTEGER(UNSIGNED(burstlen_slv));
if done then state <= STATE_READ_STEP; end if;
when STATE_READ_STEP =>
reconos_read(done, o_osif, i_osif, args + 16, step);
if done then state <= STATE_READ_BURST; end if;
-------------------------------------------------------------------------
when STATE_READ_BURST =>
if (size > 0) then
reconos_read_burst_l (done, o_osif, i_osif, X"00000000", src, burstlen);
if done then
state <= STATE_WRITE_BURST;
src := src + step;
end if;
else
state <= STATE_DONE;
end if;
when STATE_WRITE_BURST =>
reconos_write_burst_l (done, o_osif, i_osif, X"00000000", dst, burstlen);
if done then
state <= STATE_READ_BURST;
dst := dst + step;
size := size - step;
end if;
when STATE_DONE =>
reconos_write(done, o_osif, i_osif, args + 8, X"00000000");
state <= STATE_FINAL;
when STATE_FINAL =>
state <= STATE_FINAL;
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
b1e8c92bfba2d51737a081dc0f04a1fe
| 0.556652 | 3.527855 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/ll_fifo_DRAM.vhd
| 1 | 9,000 |
-------------------------------------------------------------------------------
--
-- Module : ll_fifo_DRAM.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Top Level of LocalLink FIFO in Distributed RAM implementation
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.DRAM_fifo_pkg.all;
entity ll_fifo_DRAM is
generic (
DRAM_DEPTH : integer:= 16; --FIFO depth, default is
--16,allowable values are
--16, 32, 64, 128.
WR_DWIDTH : integer:= 8; --FIFO write data width,
--allowable values are
--8, 16, 32, 64, 128.
RD_DWIDTH : integer:= 8; --FIFO read data width,
--allowable values are
--8, 16, 32, 64, 128.
RD_REM_WIDTH : integer:= 1; --Width of remaining data
--to receiving side
WR_REM_WIDTH : integer:= 1; --Width of remaining data
--to transmitting side
USE_LENGTH : boolean := true;
glbtm : time:= 1 ns );
port (
-- Reset
reset: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
data_in: in std_logic_vector(WR_DWIDTH-1 downto 0);
rem_in: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
sof_in_n: in std_logic;
eof_in_n: in std_logic;
src_rdy_in_n: in std_logic;
dst_rdy_out_n: out std_logic;
data_out: out std_logic_vector(RD_DWIDTH-1 downto 0);
rem_out: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
sof_out_n: out std_logic;
eof_out_n: out std_logic;
src_rdy_out_n: out std_logic;
dst_rdy_in_n: in std_logic;
-- FIFO status signals
fifostatus_out: out std_logic_vector(3 downto 0);
-- Length Status
len_rdy_out: out std_logic;
len_out: out std_logic_vector(15 downto 0);
len_err_out: out std_logic);
end ll_fifo_DRAM;
architecture ll_fifo_DRAM_rtl of ll_fifo_DRAM is
signal rd_clk: std_logic;
signal wr_clk: std_logic;
signal rd_data: std_logic_vector(RD_DWIDTH-1 downto 0) := (others => '0');
signal wr_data: std_logic_vector(WR_DWIDTH-1 downto 0) := (others => '0');
signal rd_rem: std_logic_vector(RD_REM_WIDTH-1 downto 0) := (others => '0');
signal wr_rem: std_logic_vector(WR_REM_WIDTH-1 downto 0) := (others => '0');
signal rd_sof_n: std_logic;
signal rd_eof_n: std_logic;
signal wr_sof_n: std_logic;
signal wr_eof_n: std_logic;
signal src_rdy_i: std_logic;
signal full: std_logic;
signal empty: std_logic;
signal dst_rdy_i: std_logic;
signal empty_p: std_logic;
signal prefetch: std_logic;
signal prefetch_allow: std_logic;
signal empty_falling_edge: std_logic;
signal fifostatus: std_logic_vector(3 downto 0);
signal data_valid: std_logic;
signal len_rdy: std_logic;
signal len: std_logic_vector(15 downto 0);
signal len_err: std_logic;
signal gsr: std_logic;
begin
gsr <= reset;
rd_clk <= read_clock_in;
wr_clk <= write_clock_in;
---------------------------------------
wr_data <= data_in;
wr_rem <= rem_in;
wr_sof_n <= sof_in_n;
wr_eof_n <= eof_in_n;
src_rdy_i <= not src_rdy_in_n;
dst_rdy_out_n <= full;
----- From User ---------------------
data_out <= rd_data;
rem_out <= rd_rem;
sof_out_n <= rd_sof_n;
eof_out_n <= rd_eof_n;
dst_rdy_i <= (not dst_rdy_in_n) or prefetch;
src_rdy_out_n <= not data_valid;
----- Flow control signals -----------
fifostatus_out <= fifostatus;
len_rdy_out <= len_rdy;
len_out <= len;
len_err_out <= len_err;
-----------------------------------------------------------------------------
D_RAM_FIFO: DRAM_fifo
generic map (
DRAM_DEPTH => DRAM_DEPTH,
WR_DWIDTH => WR_DWIDTH,
RD_DWIDTH => RD_DWIDTH,
RD_REM_WIDTH => RD_REM_WIDTH,
WR_REM_WIDTH => WR_REM_WIDTH,
USE_LENGTH => USE_LENGTH,
glbtm => glbtm)
port map
(
fifo_gsr_in => gsr,
write_clock_in => wr_clk,
read_clock_in => rd_clk,
read_data_out => rd_data,
read_rem_out => rd_rem,
read_sof_out_n => rd_sof_n,
read_eof_out_n => rd_eof_n,
read_enable_in => dst_rdy_i,
write_data_in => wr_data,
write_rem_in => wr_rem,
write_sof_in_n => wr_sof_n,
write_eof_in_n => wr_eof_n,
write_enable_in => src_rdy_i,
fifostatus_out => fifostatus,
full_out => full,
empty_out => empty,
data_valid_out => data_valid,
len_out => len,
len_rdy_out => len_rdy,
len_err_out => len_err);
prefetch_proc: process (gsr, rd_clk)
begin
if (gsr = '1') then
prefetch_allow <= '1' after glbtm;
elsif (rd_clk'EVENT and rd_clk = '1') then
if dst_rdy_in_n = '0' and empty = '1' then
prefetch_allow <= '1' after glbtm;
elsif dst_rdy_in_n = '1' and empty_falling_edge = '1' then
prefetch_allow <= '0' after glbtm;
elsif dst_rdy_in_n = '0' and empty = '0' then
prefetch_allow <= '0' after glbtm; end if;
end if;
end process prefetch_proc;
empty_falling_edge <= (empty_p and (not empty));
prefetch <= empty_falling_edge and prefetch_allow;
empty_p_proc: process (gsr, rd_clk) -- Delayed empty signal
begin
if (gsr = '1') then
empty_p <= '1';
elsif (rd_clk'EVENT and rd_clk ='1') then
empty_p <= empty after glbtm;
end if;
end process empty_p_proc;
end ll_fifo_DRAM_rtl;
|
gpl-3.0
|
e31038079b1c35e530469809c84f17e6
| 0.432 | 4.253308 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/Mem/Mem_sim_netlist.vhdl
| 1 | 751,445 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Thu May 5 01:21:43 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/Mem/Mem_sim_netlist.vhdl
-- Design : Mem
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Mem_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end Mem_blk_mem_gen_mux;
architecture STRUCTURE of Mem_blk_mem_gen_mux is
signal \douta[0]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 5 downto 1 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[0]_INST_0_i_1_n_0\,
I1 => \douta[0]_INST_0_i_2_n_0\,
I2 => sel_pipe(5),
I3 => \douta[0]_INST_0_i_3_n_0\,
I4 => sel_pipe(4),
I5 => \douta[0]_INST_0_i_4_n_0\,
O => douta(0)
);
\douta[0]_INST_0_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[0]_INST_0_i_5_n_0\,
I1 => \douta[0]_INST_0_i_6_n_0\,
O => \douta[0]_INST_0_i_1_n_0\,
S => sel_pipe(3)
);
\douta[0]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(0),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(0),
O => \douta[0]_INST_0_i_10_n_0\
);
\douta[0]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
O => \douta[0]_INST_0_i_11_n_0\
);
\douta[0]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(0),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(0),
O => \douta[0]_INST_0_i_12_n_0\
);
\douta[0]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[0]_INST_0_i_7_n_0\,
I1 => \douta[0]_INST_0_i_8_n_0\,
O => \douta[0]_INST_0_i_2_n_0\,
S => sel_pipe(3)
);
\douta[0]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[0]_INST_0_i_9_n_0\,
I1 => \douta[0]_INST_0_i_10_n_0\,
O => \douta[0]_INST_0_i_3_n_0\,
S => sel_pipe(3)
);
\douta[0]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[0]_INST_0_i_11_n_0\,
I1 => \douta[0]_INST_0_i_12_n_0\,
O => \douta[0]_INST_0_i_4_n_0\,
S => sel_pipe(3)
);
\douta[0]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(0),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(0),
O => \douta[0]_INST_0_i_5_n_0\
);
\douta[0]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(0),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(0),
O => \douta[0]_INST_0_i_6_n_0\
);
\douta[0]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(0),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(0),
O => \douta[0]_INST_0_i_7_n_0\
);
\douta[0]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(0),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(0),
O => \douta[0]_INST_0_i_8_n_0\
);
\douta[0]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(0),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(0),
O => \douta[0]_INST_0_i_9_n_0\
);
\douta[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[1]_INST_0_i_1_n_0\,
I1 => \douta[1]_INST_0_i_2_n_0\,
I2 => sel_pipe(5),
I3 => \douta[1]_INST_0_i_3_n_0\,
I4 => sel_pipe(4),
I5 => \douta[1]_INST_0_i_4_n_0\,
O => douta(1)
);
\douta[1]_INST_0_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[1]_INST_0_i_5_n_0\,
I1 => \douta[1]_INST_0_i_6_n_0\,
O => \douta[1]_INST_0_i_1_n_0\,
S => sel_pipe(3)
);
\douta[1]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(1),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(1),
O => \douta[1]_INST_0_i_10_n_0\
);
\douta[1]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1),
O => \douta[1]_INST_0_i_11_n_0\
);
\douta[1]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(1),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(1),
O => \douta[1]_INST_0_i_12_n_0\
);
\douta[1]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[1]_INST_0_i_7_n_0\,
I1 => \douta[1]_INST_0_i_8_n_0\,
O => \douta[1]_INST_0_i_2_n_0\,
S => sel_pipe(3)
);
\douta[1]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[1]_INST_0_i_9_n_0\,
I1 => \douta[1]_INST_0_i_10_n_0\,
O => \douta[1]_INST_0_i_3_n_0\,
S => sel_pipe(3)
);
\douta[1]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[1]_INST_0_i_11_n_0\,
I1 => \douta[1]_INST_0_i_12_n_0\,
O => \douta[1]_INST_0_i_4_n_0\,
S => sel_pipe(3)
);
\douta[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(1),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(1),
O => \douta[1]_INST_0_i_5_n_0\
);
\douta[1]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(1),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(1),
O => \douta[1]_INST_0_i_6_n_0\
);
\douta[1]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(1),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(1),
O => \douta[1]_INST_0_i_7_n_0\
);
\douta[1]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(1),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(1),
O => \douta[1]_INST_0_i_8_n_0\
);
\douta[1]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(1),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(1),
O => \douta[1]_INST_0_i_9_n_0\
);
\douta[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[2]_INST_0_i_1_n_0\,
I1 => \douta[2]_INST_0_i_2_n_0\,
I2 => sel_pipe(5),
I3 => \douta[2]_INST_0_i_3_n_0\,
I4 => sel_pipe(4),
I5 => \douta[2]_INST_0_i_4_n_0\,
O => douta(2)
);
\douta[2]_INST_0_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[2]_INST_0_i_5_n_0\,
I1 => \douta[2]_INST_0_i_6_n_0\,
O => \douta[2]_INST_0_i_1_n_0\,
S => sel_pipe(3)
);
\douta[2]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(2),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(2),
O => \douta[2]_INST_0_i_10_n_0\
);
\douta[2]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2),
O => \douta[2]_INST_0_i_11_n_0\
);
\douta[2]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(2),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(2),
O => \douta[2]_INST_0_i_12_n_0\
);
\douta[2]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[2]_INST_0_i_7_n_0\,
I1 => \douta[2]_INST_0_i_8_n_0\,
O => \douta[2]_INST_0_i_2_n_0\,
S => sel_pipe(3)
);
\douta[2]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[2]_INST_0_i_9_n_0\,
I1 => \douta[2]_INST_0_i_10_n_0\,
O => \douta[2]_INST_0_i_3_n_0\,
S => sel_pipe(3)
);
\douta[2]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[2]_INST_0_i_11_n_0\,
I1 => \douta[2]_INST_0_i_12_n_0\,
O => \douta[2]_INST_0_i_4_n_0\,
S => sel_pipe(3)
);
\douta[2]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(2),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(2),
O => \douta[2]_INST_0_i_5_n_0\
);
\douta[2]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(2),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(2),
O => \douta[2]_INST_0_i_6_n_0\
);
\douta[2]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(2),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(2),
O => \douta[2]_INST_0_i_7_n_0\
);
\douta[2]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(2),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(2),
O => \douta[2]_INST_0_i_8_n_0\
);
\douta[2]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(2),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(2),
O => \douta[2]_INST_0_i_9_n_0\
);
\douta[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[3]_INST_0_i_1_n_0\,
I1 => \douta[3]_INST_0_i_2_n_0\,
I2 => sel_pipe(5),
I3 => \douta[3]_INST_0_i_3_n_0\,
I4 => sel_pipe(4),
I5 => \douta[3]_INST_0_i_4_n_0\,
O => douta(3)
);
\douta[3]_INST_0_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[3]_INST_0_i_5_n_0\,
I1 => \douta[3]_INST_0_i_6_n_0\,
O => \douta[3]_INST_0_i_1_n_0\,
S => sel_pipe(3)
);
\douta[3]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(3),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(3),
O => \douta[3]_INST_0_i_10_n_0\
);
\douta[3]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3),
O => \douta[3]_INST_0_i_11_n_0\
);
\douta[3]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(3),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(3),
O => \douta[3]_INST_0_i_12_n_0\
);
\douta[3]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[3]_INST_0_i_7_n_0\,
I1 => \douta[3]_INST_0_i_8_n_0\,
O => \douta[3]_INST_0_i_2_n_0\,
S => sel_pipe(3)
);
\douta[3]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[3]_INST_0_i_9_n_0\,
I1 => \douta[3]_INST_0_i_10_n_0\,
O => \douta[3]_INST_0_i_3_n_0\,
S => sel_pipe(3)
);
\douta[3]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[3]_INST_0_i_11_n_0\,
I1 => \douta[3]_INST_0_i_12_n_0\,
O => \douta[3]_INST_0_i_4_n_0\,
S => sel_pipe(3)
);
\douta[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(3),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(3),
O => \douta[3]_INST_0_i_5_n_0\
);
\douta[3]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(3),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(3),
O => \douta[3]_INST_0_i_6_n_0\
);
\douta[3]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(3),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(3),
O => \douta[3]_INST_0_i_7_n_0\
);
\douta[3]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(3),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(3),
O => \douta[3]_INST_0_i_8_n_0\
);
\douta[3]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(3),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(3),
O => \douta[3]_INST_0_i_9_n_0\
);
\douta[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[4]_INST_0_i_1_n_0\,
I1 => \douta[4]_INST_0_i_2_n_0\,
I2 => sel_pipe(5),
I3 => \douta[4]_INST_0_i_3_n_0\,
I4 => sel_pipe(4),
I5 => \douta[4]_INST_0_i_4_n_0\,
O => douta(4)
);
\douta[4]_INST_0_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_5_n_0\,
I1 => \douta[4]_INST_0_i_6_n_0\,
O => \douta[4]_INST_0_i_1_n_0\,
S => sel_pipe(3)
);
\douta[4]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(4),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(4),
O => \douta[4]_INST_0_i_10_n_0\
);
\douta[4]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4),
O => \douta[4]_INST_0_i_11_n_0\
);
\douta[4]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(4),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(4),
O => \douta[4]_INST_0_i_12_n_0\
);
\douta[4]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_7_n_0\,
I1 => \douta[4]_INST_0_i_8_n_0\,
O => \douta[4]_INST_0_i_2_n_0\,
S => sel_pipe(3)
);
\douta[4]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_9_n_0\,
I1 => \douta[4]_INST_0_i_10_n_0\,
O => \douta[4]_INST_0_i_3_n_0\,
S => sel_pipe(3)
);
\douta[4]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_11_n_0\,
I1 => \douta[4]_INST_0_i_12_n_0\,
O => \douta[4]_INST_0_i_4_n_0\,
S => sel_pipe(3)
);
\douta[4]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(4),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(4),
O => \douta[4]_INST_0_i_5_n_0\
);
\douta[4]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(4),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(4),
O => \douta[4]_INST_0_i_6_n_0\
);
\douta[4]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(4),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(4),
O => \douta[4]_INST_0_i_7_n_0\
);
\douta[4]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(4),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(4),
O => \douta[4]_INST_0_i_8_n_0\
);
\douta[4]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(4),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(4),
O => \douta[4]_INST_0_i_9_n_0\
);
\douta[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[5]_INST_0_i_1_n_0\,
I1 => \douta[5]_INST_0_i_2_n_0\,
I2 => sel_pipe(5),
I3 => \douta[5]_INST_0_i_3_n_0\,
I4 => sel_pipe(4),
I5 => \douta[5]_INST_0_i_4_n_0\,
O => douta(5)
);
\douta[5]_INST_0_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_5_n_0\,
I1 => \douta[5]_INST_0_i_6_n_0\,
O => \douta[5]_INST_0_i_1_n_0\,
S => sel_pipe(3)
);
\douta[5]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(5),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(5),
O => \douta[5]_INST_0_i_10_n_0\
);
\douta[5]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5),
O => \douta[5]_INST_0_i_11_n_0\
);
\douta[5]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(5),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(5),
O => \douta[5]_INST_0_i_12_n_0\
);
\douta[5]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_7_n_0\,
I1 => \douta[5]_INST_0_i_8_n_0\,
O => \douta[5]_INST_0_i_2_n_0\,
S => sel_pipe(3)
);
\douta[5]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_9_n_0\,
I1 => \douta[5]_INST_0_i_10_n_0\,
O => \douta[5]_INST_0_i_3_n_0\,
S => sel_pipe(3)
);
\douta[5]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_11_n_0\,
I1 => \douta[5]_INST_0_i_12_n_0\,
O => \douta[5]_INST_0_i_4_n_0\,
S => sel_pipe(3)
);
\douta[5]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(5),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(5),
O => \douta[5]_INST_0_i_5_n_0\
);
\douta[5]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(5),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(5),
O => \douta[5]_INST_0_i_6_n_0\
);
\douta[5]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(5),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(5),
O => \douta[5]_INST_0_i_7_n_0\
);
\douta[5]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(5),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(5),
O => \douta[5]_INST_0_i_8_n_0\
);
\douta[5]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(5),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(5),
O => \douta[5]_INST_0_i_9_n_0\
);
\douta[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[6]_INST_0_i_1_n_0\,
I1 => \douta[6]_INST_0_i_2_n_0\,
I2 => sel_pipe(5),
I3 => \douta[6]_INST_0_i_3_n_0\,
I4 => sel_pipe(4),
I5 => \douta[6]_INST_0_i_4_n_0\,
O => douta(6)
);
\douta[6]_INST_0_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_5_n_0\,
I1 => \douta[6]_INST_0_i_6_n_0\,
O => \douta[6]_INST_0_i_1_n_0\,
S => sel_pipe(3)
);
\douta[6]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(6),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(6),
O => \douta[6]_INST_0_i_10_n_0\
);
\douta[6]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6),
O => \douta[6]_INST_0_i_11_n_0\
);
\douta[6]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(6),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(6),
O => \douta[6]_INST_0_i_12_n_0\
);
\douta[6]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_7_n_0\,
I1 => \douta[6]_INST_0_i_8_n_0\,
O => \douta[6]_INST_0_i_2_n_0\,
S => sel_pipe(3)
);
\douta[6]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_9_n_0\,
I1 => \douta[6]_INST_0_i_10_n_0\,
O => \douta[6]_INST_0_i_3_n_0\,
S => sel_pipe(3)
);
\douta[6]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_11_n_0\,
I1 => \douta[6]_INST_0_i_12_n_0\,
O => \douta[6]_INST_0_i_4_n_0\,
S => sel_pipe(3)
);
\douta[6]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(6),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(6),
O => \douta[6]_INST_0_i_5_n_0\
);
\douta[6]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(6),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(6),
O => \douta[6]_INST_0_i_6_n_0\
);
\douta[6]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(6),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(6),
O => \douta[6]_INST_0_i_7_n_0\
);
\douta[6]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(6),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(6),
O => \douta[6]_INST_0_i_8_n_0\
);
\douta[6]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(6),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(6),
O => \douta[6]_INST_0_i_9_n_0\
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[7]_INST_0_i_1_n_0\,
I1 => \douta[7]_INST_0_i_2_n_0\,
I2 => sel_pipe(5),
I3 => \douta[7]_INST_0_i_3_n_0\,
I4 => sel_pipe(4),
I5 => \douta[7]_INST_0_i_4_n_0\,
O => douta(7)
);
\douta[7]_INST_0_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_5_n_0\,
I1 => \douta[7]_INST_0_i_6_n_0\,
O => \douta[7]_INST_0_i_1_n_0\,
S => sel_pipe(3)
);
\douta[7]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(7),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(7),
O => \douta[7]_INST_0_i_10_n_0\
);
\douta[7]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7),
O => \douta[7]_INST_0_i_11_n_0\
);
\douta[7]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(7),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(7),
O => \douta[7]_INST_0_i_12_n_0\
);
\douta[7]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_7_n_0\,
I1 => \douta[7]_INST_0_i_8_n_0\,
O => \douta[7]_INST_0_i_2_n_0\,
S => sel_pipe(3)
);
\douta[7]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_9_n_0\,
I1 => \douta[7]_INST_0_i_10_n_0\,
O => \douta[7]_INST_0_i_3_n_0\,
S => sel_pipe(3)
);
\douta[7]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_11_n_0\,
I1 => \douta[7]_INST_0_i_12_n_0\,
O => \douta[7]_INST_0_i_4_n_0\,
S => sel_pipe(3)
);
\douta[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(7),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(7),
O => \douta[7]_INST_0_i_5_n_0\
);
\douta[7]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(7),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(7),
O => \douta[7]_INST_0_i_6_n_0\
);
\douta[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(7),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(7),
O => \douta[7]_INST_0_i_7_n_0\
);
\douta[7]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(7),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(7),
O => \douta[7]_INST_0_i_8_n_0\
);
\douta[7]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(7),
I4 => sel_pipe(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(7),
O => \douta[7]_INST_0_i_9_n_0\
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(0),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(1),
Q => sel_pipe(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(2),
Q => sel_pipe(3),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(3),
Q => sel_pipe(4),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(4),
Q => sel_pipe(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem_blk_mem_gen_prim_wrapper_init is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Mem_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end Mem_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of Mem_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__6_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"000029A1C6A5F0013632373034380000532E7122B002213B054F374E58000003",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"EA2A2D13A5809A7AA580691A00BB05DC9A7A609605E8D41305A82D13A580AA65",
INIT_03 => X"AE7105A8DB3405E4A665A580EA1A05B4D971409680E660D1A5801917D320A580",
INIT_04 => X"A5A8573560BA05E0D728B51A05B44C53B76540B1D74405C8F42E00BB2D13A0A1",
INIT_05 => X"A580994ED320A5809C5ED74C05B0D325464500D734221E1105C8945EE0AAD970",
INIT_06 => X"4A61A0E59A62A580D91160A9AE65A580D83505E09546C82305D0793A20C64662",
INIT_07 => X"40DDAA65E0EAD41320C59A72A580591F409DA5801917932605F8C928371A00CB",
INIT_08 => X"05E45871A580972E60D2A5800A1BE83A2663A5801817D91105E0AE65A580D320",
INIT_09 => X"D954C09105B0D341944605B0D335994E20C6F466A580994EA0E5974E05E4D828",
INIT_0A => X"5735C0C7C71CF456A5801917937205A48E39771105E02A26D32049E1342205B4",
INIT_0B => X"D365E63205DC9426A5C8945EA5E4A665A5809466C09020EBF41845D2F41205A8",
INIT_0C => X"F1381853553A00ABCC60D85405C4D170E0AA2D53A5805953A580696AF43205B0",
INIT_0D => X"05A8CC60D854A580EA524B1DA5801822744220AA5B4505DC6A53A580D83405A8",
INIT_0E => X"F466E0AADB5D00CEAE65609A20BBC5C72A1B5367972E53133EAAD94C3A5F7411",
INIT_0F => X"2C002A0029002700260024002200200040DDB868D41320E365628A2600E32546",
INIT_10 => X"4D004A0047004500430041003F003D003B003900370036003500340031002E00",
INIT_11 => X"71006F006D006B00690067006400620060005D005A0057005400520050004E00",
INIT_12 => X"9400920090008E008C008B0087008400820080007E007C007A00780077007400",
INIT_13 => X"B800B600B500B300B100AF00AC00A900A600A300A1009F009E009B0098009600",
INIT_14 => X"E000DD00DA00D700D500D300D100CD00CA00C800C600C400C100BE00BC00BA00",
INIT_15 => X"00000000000000000000000000000000F500F200EF00ED00EB00EA00E900E400",
INIT_16 => X"0000000000000000000000000000000000000500000000000000000000000000",
INIT_17 => X"CB0B0003F700000000B80B0002F7080002000000000000000000000000000000",
INIT_18 => X"F700000200FD0B0006F702000000EE0B00000002004201D90B0005F700000200",
INIT_19 => X"00470C000AF700000200350C0009F700000000200C0008F7000000000D0C0007",
INIT_1A => X"5CF900000000710C000EF700000210640C00000000000000570C000CF7000002",
INIT_1B => X"0002AB0C00115200000002980C001052000000028F0C00F9F708000000860C00",
INIT_1C => X"00155200000002E40C009D5200000002D10C00135200000002BE0C0012520000",
INIT_1D => X"0000023E0D00185200000002220D00E252000000020E0D007C5200000002F70C",
INIT_1E => X"0D00885200084002830D001B5200084002640D001A52000840024F0D00195200",
INIT_1F => X"00084008E70D001F5200084002C50D007E5200084002B00D001D520008400299",
INIT_20 => X"4F0E002352000040082B0E002252000040020C0E00215200004002F70D008252",
INIT_21 => X"52000000029C0E00265200000002820E008C5200084008660E00245200004008",
INIT_22 => X"02020F00BB5200000002E90E006B5200000002D30E00285200000002B80E008A",
INIT_23 => X"2E52000000024C0F002D5200000002370F002C5200000002220F002B52000000",
INIT_24 => X"00029B0F00315200000008880F00985200000002740F002F5200000002610F00",
INIT_25 => X"00355200000006FD0F00B95200000002D40F00BE5200000002B90F00AC520000",
INIT_26 => X"0000064510003852000000063410003752000000062310003652000000061410",
INIT_27 => X"10003C52000000068010003B52000000066910003A5200000002541000395200",
INIT_28 => X"00000006C610003F5200000006B710003E5200000006A010003D520000000691",
INIT_29 => X"0A1100435200000006FB1000A75200000006EA1000415200000006D510004052",
INIT_2A => X"5200000006371100465200000006281100455200000006191100445200000006",
INIT_2B => X"029311000DF980000200741100C152000000025911006652000000024811005E",
INIT_2C => X"4E5200084002EA1100EF5200084002C911004C5200084002AB11008F52000840",
INIT_2D => X"40027212005152000840024A12005052000840022B12004F52000840020C1200",
INIT_2E => X"00005700408000B61200005600400000B212B4000000000000921200B2520008",
INIT_2F => X"084002491354005900508000221353000000501000021300000000400000DB12",
INIT_30 => X"130063C7084000009D1300B8D7000002008813570058205090007113594B5200",
INIT_31 => X"00C00000E7135F945200000002D2130075F980000200BE13005DF980000200AE",
INIT_32 => X"5714000063084000003B1400006000804000261461E65200000002031400005E",
INIT_33 => X"5200000002AD14000064004000018E14653252000000087214627BC700D00000",
INIT_34 => X"002F156A855200000002101500006A41480000F21400009A20C00000D614D948",
INIT_35 => X"00C200C00001711500009C20C000005C15722952000000024815680069001032",
INIT_36 => X"0600E01500009D00000300C41500A4C100810A00A515006FC104400400891500",
INIT_37 => X"00007E004000011B1600717200000600FF1573006B02101401EC150000720440",
INIT_38 => X"00400274160000762040000065167714520000000252160083F9800002002A16",
INIT_39 => X"16009FC708400000B2160080A708400000A216000078084000008C16791E5200",
INIT_3A => X"0000020020177F785200000002F61600007C00400000D9167D165200004002C4",
INIT_3B => X"6D17A220520000400855170000C9004044003B1700A5A70C4004002F1700747E",
INIT_3C => X"8500000200A61786AF520000000298170091F9800002008A170084F900000200",
INIT_3D => X"02051800008800400001E117891C5200080002D0170000DC00804200BD170000",
INIT_3E => X"008C2040000057188DC75200084002371800008A0040400024188B2752000000",
INIT_3F => X"0600C41800008F20400400A918905852000840028C18000000204000006B1800",
INIT_40 => X"954752000800021C190000D441480000FA1800000000400400E01800AEF90000",
INIT_41 => X"0800027F19000096000006006C19973052000000024719000094204000003819",
INIT_42 => X"1900679A00C00000B2199BD75200080002A219000098000006008F1999965200",
INIT_43 => X"00000201111A00709D00100600021A9EE45200000002E2196C000030409000C5",
INIT_44 => X"691AA30082005000004D1A0000A020C00000381AA100B400100400281A00C3C7",
INIT_45 => X"A700400000B81A00A6A700400000971A00B7C101400000821A0000A200400000",
INIT_46 => X"00201B0000CA044004000E1B007AA700000600FF1AA8425200000006E11A0000",
INIT_47 => X"00AC08400000751BAD6452000000025A1B000000004000003A1B0000DE004000",
INIT_48 => X"0200D41B00B6F900000200C11BD0605200000002B11B00B0F900010201951B00",
INIT_49 => X"B50F52000840020B1C00B1B200010200F71BB3005200084002E21B0000B20000",
INIT_4A => X"0006006A1C00C0C100010201561C00CDF900000200471C00A0B4000102001E1C",
INIT_4B => X"1CBC2A5200000002A81C0000B902000600911CBA345200000002811C00D6D700",
INIT_4C => X"005004000A1DBF335200000002F61C0000E000440000D31C0000BB00400000C0",
INIT_4D => X"7B1D6D6EC100108E00581DC2C95200084002471D0000C100000600211D0000BE",
INIT_4E => X"C700000200B81D00C6C700000200A41D00C5C700000200901D00C4C700000200",
INIT_4F => X"00131ECACB5200004002F51D005BC700105400E21DC89A5200000002CC1D0000",
INIT_50 => X"EAF980000000531EE000CB001032002C1ECC4A5200084002201EA981C9001032",
INIT_51 => X"0000A91ED100AF0050C000921E0000CE004000007B1ECF765200004002671E00",
INIT_52 => X"D5DC5200084002051F0000D520D00100F21E00000000400000CC1E0000D00440",
INIT_53 => X"0007005A1FD8D45200080002461F0000D7000006003A1FD393D400103200271F",
INIT_54 => X"1F00000000000400941F0000D904400600801FDA0066020014006F1F005AD700",
INIT_55 => X"02000400F31FDF175200004002E01F0087DC00400000C71FDD695200084002AB",
INIT_56 => X"4820E3DE5200000002332000BDE0004400001420E1ECCC20500000022000AADE",
INIT_57 => X"520008000296200000E4000004007520E5CE52000040025F200000E200101C00",
INIT_58 => X"0006210000E802000200DE20E9255200080002C0200000E600400000AB20E7E8",
INIT_59 => X"00EC004204004721ED00CC00500800322100EEF900010200212100EBF9800002",
INIT_5A => X"0200A7210000EF800002008D21F04D52000840027F2100F1F900020000622100",
INIT_5B => X"0000F900000200DE2100F4F900000200CC2100F3F900000200BE2100F2F98000",
INIT_5C => X"0002002B22F800000028BCF316220000F700000000042200F6F700000000F221",
INIT_5D => X"CDA629015CCE540463220049F9000002003F22FAF5F7000000002D220001F700",
INIT_5E => X"3EF846F2DEF00100042A31294E32A5A44E42977E03008210B442C242DC46B238",
INIT_5F => X"9AFA0100000027000031593B32D3E5EA2202008384F28570E329311447464CD2",
INIT_60 => X"004A3DC4456E3B1C45F2E5BA46052063261E04005C2931D93E9149E0459345F2",
INIT_61 => X"3F05498342F269EAF432020086CE878870C528319142324ADF0C30D341574704",
INIT_62 => X"3C7298CD0E632A1E03007D2831DE3B5D41FE48B297C6CE600200AB28313A416C",
INIT_63 => X"4BCC43F2A5E4483D87029226D35C0500D12731A5B0D3351934486304005942A9",
INIT_64 => X"1F63802A3911130300A94332579D524F02005C293134E90A5702000F43F342BA",
INIT_65 => X"110400E2992B1516101D111F45CD4E12201A14110400CD05F0992B48162D1E18",
INIT_66 => X"1119131C121F45CD4E12201A14110400E2992B1018111C121E45CD4E12201A14",
INIT_67 => X"991E045C2A2526120500E2992B121B131E7C1F45CD4E12201A14110400E2992B",
INIT_68 => X"752523992B1416101795E6045C2A252612040075054B992B1517761CCE1D92E6",
INIT_69 => X"130400D67CE941D67C4246E44905DC982B7C16E21CA58C0378312A1213040049",
INIT_6A => X"17150F1C171D0ACDE6665311404D4E1205006D982B181EDE1F658CC043466916",
INIT_6B => X"5D459A972B7727311A164A1A438F3C4C1D1A1E5CB99B48C24F0611040046982B",
INIT_6C => X"8748C24F06110500835D255A972B1B161917A5A82C2991001E22F41205008483",
INIT_6D => X"2B881D1D1E85D3673AE612200093120500835DEE452E972B1A17881F45D23953",
INIT_6E => X"31AC963600009E1C7700009E1C7D1E1F05C7D12CE4068619D71005008405B296",
INIT_6F => X"1E1EE5AADB5DE40B030083EE2540962B1D1C781FEAD20D1302008483EE45CB73",
INIT_70 => X"C795A4217F0D99EA10002FCB4588002A3B8D13070083EE2526962B1E131A9537",
INIT_71 => X"7CC795A4277D0D99EA10002FCB4588002A3B8D130700835CEE45CD952B447331",
INIT_72 => X"2B211382161A9537211DE5AADB5DE40B0300835CEE4598952B447331C795A420",
INIT_73 => X"EE2534952B5B953322161A953765953D27953EE5AADB5DE40B030083EE257295",
INIT_74 => X"9B0D11020083EE25FC942B8C1323161A95378C1D27953EE5AADB5DE40B030083",
INIT_75 => X"6284172D5F74120800527C0E3E6449B025EF922B12933629172918321B261C12",
INIT_76 => X"8A1D211E45ED0611A04A26110400DD922B281B6B1C251F45B10663A612A0659A",
INIT_77 => X"05F266318A162618321AD71EA5CCD44F0611A02A2A110500B005B4922BD5923C",
INIT_78 => X"0579922B05002D2516661D6B1E251F8A99181B9500192B9C7025634611070049",
INIT_79 => X"A612804D2E4D8E1306004F922B2F1E961F8A99181B95006C3A193B3C13060049",
INIT_7A => X"32922B981C6B1FA5A8CC60D8540470F45E661206004F922B2E1E981F45B10663",
INIT_7B => X"31E8162B1D981F45ED0611020016922B961C0F1D45B10663A612204514110500",
INIT_7C => X"465D191303004905EC912BBB16BB1C2A1D961F45ED061102004905FE912BA570",
INIT_7D => X"0448465D19130500397C124B64EE05B4912B31136416E49137E4913D641EA5C8",
INIT_7E => X"E59A62045C8E6E5761EA120600397C124B64EE0586912BA5913D321EA5F0CA6D",
INIT_7F => X"19130600527C0E3E197C4A44E4EE0587603125182819311DD71E7B91A0647FA5",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__6_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__6_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__5_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2BB9193F1C351D45FD4612020028912BB915B91DC11E45B10663A6124031D35C",
INIT_01 => X"163B1C3A1D3C1E45FD46120200CD902B351A3F1B3F1C341D45FD46120200CD90",
INIT_02 => X"173A18361E371F45FD46120200E0902B381CA5A4531120192A110400CD902B38",
INIT_03 => X"00AE05DF5631001191AE8F973A18658C804D2E1B97110400CD902B00D357563C",
INIT_04 => X"00CD902B3A17361D3C1E45FD46120200CD902B3B163818361A391B45FD461202",
INIT_05 => X"A5A4531120192A110400CD902B00D357563C1A361C381D3B1E401F45FD461202",
INIT_06 => X"341C401D3E1E45FD46120200CD902B3D193F1B3E1D45FD46120200E0902B3E1F",
INIT_07 => X"20192A110400CD902BA7163C17401D3F1E45FD46120200CD902B00D357563517",
INIT_08 => X"461F45FD46120200E0902B431CA5A4531120192A110400E0902BA71DA5A45311",
INIT_09 => X"461C441E45FD46120200CD902BA717451D431F45FD46120200CD902B441D421E",
INIT_0A => X"4405206346110500CD902B451C431D661E461F45FD46120200CD902B00D35756",
INIT_0B => X"BE8F3D661FA5DC26460A110300527C0E3E6409902B2A9036941E481F45E2A621",
INIT_0C => X"4AB04AEF4AB74AF2F8BA2663020049CDB74519002D535231000000B7C197471C",
INIT_0D => X"747931E28E374C1C4F1D191E4D1F6CBAD72811110300DC8999F3C7906B2831BE",
INIT_0E => X"79315817511C4E1D4D1E8F1FA5B4D9540464585D74110500F2F3F4F165838F2B",
INIT_0F => X"E28E37501A438F3C4E1D338F3E4A1FA5E4585D74110300F2F3F4F1654F8F2B74",
INIT_10 => X"31E28E374A1C4B1DEF1E0A8F3FA5E4585D74110300F2F3F4F165FB8E2B747931",
INIT_11 => X"7931E28E374C1CEE8E3D4B1E8F1FA5E4585D74110300F2F3F4F165FB8E2B7479",
INIT_12 => X"1C000000EBCB9D4A1E511F45E19A360424D335EA100500F2F3F4F165CA8E2B74",
INIT_13 => X"A78E3F0AEBB4112A002D6B14130500EBF325CA4A31000000EBCB955018511A50",
INIT_14 => X"1E4B1F0AEBB4112A002D5F74120500F3FAB645B08E2BB41A4F1B4C1CB41D4F1E",
INIT_15 => X"72105111015341F41E080052150000F3FAB645828E2BB4184F19A78E3CB41D4F",
INIT_16 => X"53259132080001002CE28D2E8AC28BE2709F7831624CAC3D72C5DF661A084097",
INIT_17 => X"002C06002DA68D2E8AC28B509F7831624CAC3D72C5DF661A0840977210511101",
INIT_18 => X"002C01002DFBE930624C473C72A5A8F168E600181BF700512F2E6B461D080004",
INIT_19 => X"2C8C8D8EE270624C0640728CA92029196B174D8A175171EA015341F41E090001",
INIT_1A => X"B87731624C06407285B10A242A63FA225371252A5C3D070006002A9C8D2B0200",
INIT_1B => X"314B167B8F3745A93713C0005513040006002A05002C05002D408D2EA68D8E50",
INIT_1C => X"9322050014002A328D2E8E1011463219AB1360B824D71D0400F3F4F2F1650D77",
INIT_1D => X"7104000A002F1C4C0E4CE34DB20DCDEA7202008F10E34632A5C46A1A1544F466",
INIT_1E => X"AC446C4D4D3E654DF265AD2E220200FC108A7931543E4D3E7278AD2E224065AE",
INIT_1F => X"CE46B47C9D3FE4EA0564902B00BC5257941CA5D02E6919130300909130997931",
INIT_20 => X"2EF4929350EA464C475B45B2D1E8D3480063E52A935300129750E4130800C37C",
INIT_21 => X"5335C10D050070932B6B1A851E45ED06110033D36DE63253110600D48C28C58C",
INIT_22 => X"2A1B12609A22D86D06005A8C284F8C2BDFB73094433E40654DB205B3D36DE632",
INIT_23 => X"6031FF46234C934CB2A5A84767020006002F9410EF5F31A6428C4572A5C4C65D",
INIT_24 => X"363017321C301DAC1FA5DC8E6E5761EA120400348C2807002A238C2B05002F06",
INIT_25 => X"4CEF43153E8C4CF205C78A2B4F05004EFA660500397C124B64EE057E61317F91",
INIT_26 => X"7E658C2046F46624040400138C2B05002C0F002DFF8B2E23002FB710E1843162",
INIT_27 => X"9842F205D2F428C9690C5C9A660500D38F2B828531481CFC8F9D467DFC8F9D29",
INIT_28 => X"30865831624CD3432A4CB2A5A197660200F68A28DC8A2E9596309F42123D043D",
INIT_29 => X"A45931DC16A49337DC1C63800D5D3413030006002C0E002DC98A2E14002F9798",
INIT_2A => X"6AF41203001E002A99FC301F8531294732259A192B495503008F7C8F3F644905",
INIT_2B => X"30CA4709413C44B225AAC7447A64030091922B60192C1C291D8A1E261F638069",
INIT_2C => X"892E02002FDFB79F506245F14672A59A12645339681A0400068A2802002F9D9E",
INIT_2D => X"A3892E1E002F9FB7A050D370319B3C21428F466D4BF225DD94630200CB8928B8",
INIT_2E => X"008E8928A1A2A3DD70576D31EA4DB3449D3FB2E5D2340153259472040000002C",
INIT_2F => X"02000A002FA410D75331F64A3285E659452E630300987231664B320DE58E6302",
INIT_30 => X"859987060200050027A58A2B9A9B9C50D4693137474D45B848C84BF265A9AE65",
INIT_31 => X"743D2849F2C7DC066120295171EA01512F2E6B461D0800A5F9303C6C31083C32",
INIT_32 => X"434432A5DC2A25260253259472050005002C05002D08002FA6A7FB50624C553C",
INIT_33 => X"B2A5C486222A002A3AF50705006C992B141FA5A4531120192A110400F2A8DD50",
INIT_34 => X"EE256B962B7E1B1E1CA5B4C82887003E4D0613050014002FF410D7425A47773E",
INIT_35 => X"A910FD4332C5AB500A59450A6204000F002F1C4C0E4CD049B251EDB461020083",
INIT_36 => X"A58C036086110300AA10C73F1C4C0E4C5249F2E5AADB5D892B176104000A002F",
INIT_37 => X"225371455DAE55D5600A00D67C4246D67CE941E4490503992B0171311617131E",
INIT_38 => X"0005002C05002D0A002FAB10624C1349E143273DF2A5E42A2AC85C07242A63FA",
INIT_39 => X"C067585F0400E37631054932A5A4D36002009B962B78186A9B88003E4D061304",
INIT_3A => X"3EEC42CD48B2A5A8955E020082892E14002FBB10FA5731204427447245AD6E42",
INIT_3B => X"1B96331F161A9537201D781EE5AADB5DE40B030076892E0A002FF910C6793185",
INIT_3C => X"32A5F0F44CCE5C0300AC10857431B14832E5AADB5D020083EE25E7952BC97631",
INIT_3D => X"947205008F7C8F3F64065A319693A36976601D658C4049341103001474312C48",
INIT_3E => X"0C8928B7DF309443BC477257F9E6560200DD101E4825487285CD2E3AE6025325",
INIT_3F => X"DF962B00009E1C771B1800009E1C7B00009E1C7E9C9ED3199728012453110500",
INIT_40 => X"0A002DFF882E0F002FC210624C3D42A747B2A5A491322A00995604008384EE45",
INIT_41 => X"D79C406AD365265604004905B3653128176B1D271E658C2069341203000A002C",
INIT_42 => X"A5A8D81C044826110400F5882B05002C0A002D14002FF9AD30624C7D47163CB2",
INIT_43 => X"31114D76475A47E13CF205B9191BB12A0128D155050083EE25B2942BD717D71F",
INIT_44 => X"743176475A47E13CB2259BF400495D3A2353570500E2882B14002FB5E4307476",
INIT_45 => X"985631006327564B1C4E1D4D1E0A8F3F6CBAD7281111030014002FF9AEE4504E",
INIT_46 => X"00D9882B19002F2D56315A477444A544B2A5E06A1B2A2A0128D1550500AEF325",
INIT_47 => X"284839F5070800AF107B6D315A477248EF3CE83CF2A5E0CA25F4280128D15505",
INIT_48 => X"5CCE5405000A002FB0F4300073311D4A4C47A642B2859911035853EA666E2B01",
INIT_49 => X"1FC5DF2A4686110300CA882E0A002FB110AB6F31DC46B33D7205AB314D062901",
INIT_4A => X"2E0F002FFB10076E31624CBA3DBB3BD546F285CD2E4FCE5403003A902B471D5E",
INIT_4B => X"0200B458312A1D2F1E2D1FA58C035CF45E4E120400BD882B06002C04002D9E88",
INIT_4C => X"58312B1D2E1E2C1FA58C035CF45E4E120400F658314540A8456448B297DED749",
INIT_4D => X"1CC71EC71FC59F8746044826110400F658314540A8456448B297DED7490200B4",
INIT_4E => X"8728BB872B02002FB210A16E317E4585457745B290D2A721D94803002F942BD7",
INIT_4F => X"002664002A14002FB3E4B4B5702475311748E13C72A5E4861E0039CC480400D1",
INIT_50 => X"44D53F1B472A45F2A5A8D335C8480300CF7131E41F658C404DAE214612040004",
INIT_51 => X"729D9ED119F2070300B95F316847B93F8244B2A5C04645020032002A447231BA",
INIT_52 => X"2FF41038450B3D7B44603BF2A5E42A2E464503000A002AF410946E31203D3F45",
INIT_53 => X"002A6A892E0A002FE8105D27317B3D32C5D3FA00495D03007787286E872B0200",
INIT_54 => X"5765D3440063E61E05000A002C05002DF910624C224072299A57498A06030014",
INIT_55 => X"19075CAA65464507005F872B4D872E0F002FE910326E31C8445F445144B2A5CC",
INIT_56 => X"3E872B05002C0A002D0F002FB6B730DC8431624C8C3E083CB2A5E0D351480580",
INIT_57 => X"02002E872E14002FB8B9BABB7051445F447265DE2A4F26328317494D571F0600",
INIT_58 => X"00315831EF3C014AFD3CB265D259450A620300EB902B4018411E441F45FD4612",
INIT_59 => X"390B28C93C050023872EBCBD302C58319B3C20442744B245AD6E42C067D84C04",
INIT_5A => X"3809284C37040017872B05002C05002D0A002FBEBF30624CE64072A5A8D35D9A",
INIT_5B => X"974E045C8E6E5761EA12060008872B0A002C0A002DC0C830624C573F7269D2D2",
INIT_5C => X"E03A06245135BC24D3340700197C4A446449EE25FD61317B91A0647CBB1FA5E5",
INIT_5D => X"3057316E42674272A5B0D365E6320300C1F4301C4C0E4C753BDF47F2A5D45257",
INIT_5E => X"108F4F31CB3E3205A2E622020049057F932BDC17DC1D658C7A38B97A4C110400",
INIT_5F => X"F71A87006A5219130500C7C6301C5131074C2B3C729CDED71C404D34630400F2",
INIT_60 => X"130500C7C8301351319D3F32A5DC9426404D346304005B8E2BFB4F31B41B85D3",
INIT_61 => X"00009CB27500009CB2785019511B501C4E1D4E8E3E511F45E19A36440520638A",
INIT_62 => X"D3693A1C242A5D861E0500CAC930576D319D3F32A5DC94260200FAF3259E4A31",
INIT_63 => X"CBCC30055231C43E544C5B4C9D3FF297D20954E6660300CA10614F31C04D3285",
INIT_64 => X"A5BE77341A15919F337EA58C630702003A6031A040F741F041113FF2D2A40100",
INIT_65 => X"00102727CDCE30EB62318440B645033FB2A5E09546C82303004905D264311C91",
INIT_66 => X"4CB279AAC95D19442663FE220500490563922B2F17AC1C658C2564D344D91004",
INIT_67 => X"B9F11A4C05406D342205000B002C04002DDA862E14002FEFCFD050624C874177",
INIT_68 => X"49054C912B19002DE46C31B9166380EA6AD82837130400368531703EE2417205",
INIT_69 => X"05002C0A002D0A002FD1D230B36C31624CEC49EE3EF93DF2A5A8C845A6210300",
INIT_6A => X"8C0330D36D2E120400D3F930FD5231C13DDB487259D5D720020005002ACA862B",
INIT_6B => X"BE55F46604007C4FEE457C4FF545E4490536513100E85256B78F9F337DCB1EA5",
INIT_6C => X"5E31664B9E3D7265D2396B07283A1E040010272AD410225131D63D3245E10601",
INIT_6D => X"E6591F6072F41E0400E810E65E31664B9E3D72A5CC3467FA00495D0400D510E6",
INIT_6E => X"10E65E31664B9E3D72A5CC3467FA009C4651790500DA10E65E31664B9E3D7293",
INIT_6F => X"0D0191525905A06AF43207005D942B9A1C9A1D63800A4D662A793A46120500D6",
INIT_70 => X"004905A88F2BCB16C8E5D9100200D710575F31154C8A421C3E153EF2A5E0192B",
INIT_71 => X"A65E76C917C11D000000EB4F9E65AA0D650E12030028002A744B3245C5C76402",
INIT_72 => X"4B32A5A8F118194CAA21D941050049EAEB450A002D984F31000000EB4F949A8F",
INIT_73 => X"EA482E130400DBE6DC50877A31324A3A48383EB245E5BA21020032002AF51074",
INIT_74 => X"F94B72A5DCEA482E035341F41E050077992B197331AC99A2E47D141EA58C035C",
INIT_75 => X"2D37002FC2C330624CDD3D7E3EB265BA6B5108249132040032002FE2DD305A47",
INIT_76 => X"E0E1704F7331624C2F493649B2A5A837570A61030023002AF5862B0F002C0A00",
INIT_77 => X"51447265DE2A4F26025341F41E050077862B06002C04002D8A862E03002FDEDF",
INIT_78 => X"0A002FE3F930916D31123DC746BC47043DF2A5C0941E0022261E0400E2105F44",
INIT_79 => X"32E59A391A0200EE932B3873311F949B2E76DC1FD7E4D1100200E98528D8852E",
INIT_7A => X"1FA5C826110200E4E5F450005E316D3D322A9E471F602AEA32040032002A833B",
INIT_7B => X"00F9E630775D313446F63C72A5E4911E0200EE05835C318C16281C321D8C1E9A",
INIT_7C => X"FA3B72A5A8DD003E51341E0400020027E88B2BBD10FF53317E4C3225C6F46602",
INIT_7D => X"E970054F316A3C3231AA0760D85C0764B401495D060019002FE710D15331F33B",
INIT_7E => X"004905AA932B6914AF166917D41CAF1E691FA5A8B14A2A130300CF852BF4E8ED",
INIT_7F => X"7131171CE21EA58C0364E6100300E9F430F84E316A3C32A5C4511D0063E61E04",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__5_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__5_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__18_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"083C72A5C0C8606072F41E0400737129EAEB30A84E31184D393C72D99C0100AE",
INIT_01 => X"3F15450C495641F2A5A1534702000F002AB5862E03002FD8D9DA50C87A31F748",
INIT_02 => X"02005985F23D6490982BD09836DE1D161F638079190D130300C5852BECED3065",
INIT_03 => X"CE7EA58C037879193711040032002ABA852B394E31323CDC3FA53DB259C1D81C",
INIT_04 => X"DC3FA53DB259C1D81C02005985F23D64B4992B197331AC99A2CE749D1CAC99A2",
INIT_05 => X"0091052B932BE814E81FA5A4462504042A1821120500AE852BEE10394E31323C",
INIT_06 => X"1106000A002C0A002D8B852EEF10624CD042164AB2A5C4514318442663FE2205",
INIT_07 => X"7CF041E491057F5A311993A1E6752E171993A1E67C58A5A6112B000A4DE66653",
INIT_08 => X"F0F130F44D317241D140944A0C42F238E3B4312A00571D524F0500947CF74194",
INIT_09 => X"C04D3285D3693A1C4CAA21D9410500F2F330A25231233E32A5F86A4AAE210300",
INIT_0A => X"002AEB862EC4C5309E6231AF3E193D722AE6991E006326320400F4F530AB4D31",
INIT_0B => X"020004002FAB4C31AD42CF440948734DF2A5DC2A1B5C05C0672E4F465B060004",
INIT_0C => X"2A8F374D1C4D1D2A8F3E4D1FA5E4585D74110300AB4C310948734D72E5AAD970",
INIT_0D => X"660200F6F730954C314148BD4572A5A86C1AF706264F9A4A0500F3F125188F2B",
INIT_0E => X"710400644C31E5426147704C8041F219AB972E0200F8F9302E3D694C72A5A8EA",
INIT_0F => X"4B316A4A7F3C7225DDEE3093620300FAFBFC50C74B3132433245E19A364065AE",
INIT_10 => X"70804D2E4D9A5E57630600FE105E4B31654D32319A1C28D94DE6320400FD109A",
INIT_11 => X"0000294B319E4BAB4672A5E54A652A00596104000000FF106C4D654D72A5C4D1",
INIT_12 => X"2200002352454F4164F705010026E3292900002A389A2B389A2E00002F304E32",
INIT_13 => X"2B752C3F2D1B2E4B2E000000000000001B4B31CC3CDA3C7225DD861E02000000",
INIT_14 => X"29EF29FB290100FFFF1D2A0000232A3D2A512A692A7F2A952AA92AAF2AB72AF9",
INIT_15 => X"0095299F2900000000B1290000000000000000F59D1A9EBD290600CB290D00D9",
INIT_16 => X"295F296B29772900000100812900000000000000000000000000000000000000",
INIT_17 => X"00000000002D29372900000000000000000000000001000700080043294F2959",
INIT_18 => X"0039279D2701286528C928000000000000000000000000000000000000000000",
INIT_19 => X"000000000009271D273127000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000512541260000000000000000000000",
INIT_1B => X"2364006400E923B400B400000000000000000000000000000000000000000000",
INIT_1C => X"01000000000000000000000000000000000000000000000000AD23B923C723D1",
INIT_1D => X"004D004E000600B40050004F005100B4000500532EB7399338DB3A102713005E",
INIT_1E => X"004D004E0050004F005100B4000B00CB00C900CB00C10004004E004A004B004C",
INIT_1F => X"000000000000000000000000000000000000000000000019008F004A004B004C",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000780000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000006400",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"9A8C9A7E9A00000500699A5A9A509A0000040000000000000000000000000000",
INIT_4A => X"00289B000002001D9B149B0E9B000004000A9B079B059B039B029B029B9D9A95",
INIT_4B => X"9B699B649B000004005E9B559B509B499B00000500459B379B339B309B000005",
INIT_4C => X"9D28006B0027000000040018001700140015001000110012001300000009006F",
INIT_4D => X"9E6400E49DD59DBC9DB09DA59D9C9D2E9D2A9D259D209D1B9D169D119D0C9D07",
INIT_4E => X"00040024000A000000B09E0500A69E0A00A09E14000000999E0F008E9E460086",
INIT_4F => X"008C0010001F008200220023002400050001001F000200820003002200040023",
INIT_50 => X"9F7D9F300031006400AC0064003200820078001F001E00820020002200210024",
INIT_51 => X"0001000300030003000300030002000200060006000100010001000100949F87",
INIT_52 => X"0004000400060006000100010001000200040004000600060001000100010001",
INIT_53 => X"0005000500040004000600060001000100010001000100030003000300020004",
INIT_54 => X"0004000400060006000100050005000500040004000400060006000100010001",
INIT_55 => X"2A00007F2A0000692A00000000512A3D2A00000000232A050005000500040004",
INIT_56 => X"9F0300EF9F0100EA9F0300E69F0100DD9F0300D99F0100D59F0000D49F050095",
INIT_57 => X"2ADD2AD52ACD2AC12A060018A001000CA0030008A0010001A00300FD9F0100F6",
INIT_58 => X"003DA0010035A003002AA0010029A0030024A001001BA00000D49F0500ED2AE5",
INIT_59 => X"002B2B1F2B172B0F2B032B05003DA0010029A003004AA0010047A0000043A005",
INIT_5A => X"2B3F2B03006AA0010029A0030060A0010058A0030052A0000050A001004BA005",
INIT_5B => X"00A8A0030098A001008DA001008AA00000D49F050079A0010029A00300532B4B",
INIT_5C => X"A00100CEA00100C4A00300B9A0010029A003007B2B772B6B2B632B0400B6A001",
INIT_5D => X"0009A1010029A00300FEA0010029A00300A12B9D2B952B8D2B0400EEA00100D8",
INIT_5E => X"2BBF2BB72BAF2B05001FA101002FA1030025A1010029A003001FA1010018A103",
INIT_5F => X"2B5B2B332BF52AEB2BE32B02004AA1010029A0030038A1010029A00300CF2BC7",
INIT_60 => X"A10100152C010072A101000B2C072C020067A1010059A10100F32BD72BA52B83",
INIT_61 => X"2C332C0200C0A10100AAA10100292C252C02009DA101008EA101001D2C010081",
INIT_62 => X"0014A2000003A20300F5A10000F1A10300452C412C0200DCA10100CFA1010037",
INIT_63 => X"2C3B2C2D2C212C192C0F2C6D2C01002AA20100652C010017A20100572C4F2C02",
INIT_64 => X"2C8F2C8B2C872C04005EA2010052A2010048A201003EA20100712C692C5F2C49",
INIT_65 => X"A20100B12CAD2CA92C03009BA201008CA2010083A20100A12C01006EA2010093",
INIT_66 => X"00EAA20000DEA20300C92CC52CC12CBD2C0400CEA20100BDA20100AFA20100A3",
INIT_67 => X"0042A3010033A301001CA3010009A30100E32CDF2CD72C0300FBA20100ECA201",
INIT_68 => X"A300006BA3030068A3000059A3030053A300004EA30300FB2CF72CF32CEF2C04",
INIT_69 => X"2C372D0100A0A301002D2D292D020085A301007AA30100192D112D092D03006F",
INIT_6A => X"A30100C7A30100BDA30100AEA301003B2D312D212DFF2CE72CCD2CB52CA52C97",
INIT_6B => X"A4010009A401006F2D6B2D020004A40100EBA301005D2D592D552D512D0400DB",
INIT_6C => X"2D040084A401006EA401005EA4010048A40100812D7D2D792D03002EA401001A",
INIT_6D => X"2DAF2DAB2DA72D0400CDA40100B9A40100ADA401009AA40100992D952D912D8D",
INIT_6E => X"A5000026A5000018A50500C92DC52DC12D03000AA50100F5A40100E2A40100B3",
INIT_6F => X"A5010058A50100E92DE12DD52D030051A5000048A503003CA5000035A5030030",
INIT_70 => X"2D732D612D112E0D2E0200ACA5010095A50100012EFD2DF92D030087A5010078",
INIT_71 => X"2E00000100A90072003F2D000001006E00D900152E052EF12DCD2DB72D9D2D85",
INIT_72 => X"2F992F8F2F7D2F732F692F5F2F412E372E2D2E0300752C000000000000BA001B",
INIT_73 => X"314931373125311331D130C7308D307B3071303F303530233019300730B52FA3",
INIT_74 => X"323132273215320332F931EF31D531CB31C131B7319D31933189317731653153",
INIT_75 => X"3399337F3365335B33513347333D33333311330733ED32DB32A9326F325D3253",
INIT_76 => X"34D134B734AD34A33491347F346D3463340134F733ED33E333D933BF33AD33A3",
INIT_77 => X"35D135BF35B535A3359935873575356B3559354F35453533350135F734ED34DB",
INIT_78 => X"36E136CF36C536AB3699368F3685367336513647363D36333621360F36F535DB",
INIT_79 => X"37E137D737CD37C337B93797378D377B3771375F37553713370937FF36F536EB",
INIT_7A => X"0189387F3875386B38613857384D38433839382F3825381B3811380738FD37F3",
INIT_7B => X"FC0102008F000000000000000100900000000000000001009100000000000000",
INIT_7C => X"00000000000101008D0000000000000001008E000000000000018E0000000000",
INIT_7D => X"FC011F0030001800FA010A008C00CA00000000018C00CA0000F3000202006700",
INIT_7E => X"F901450000000000F6018A0000000000FF018B0000000000F1011E0030001800",
INIT_7F => X"0001890000000000F701220000000000FB01220000000000FE01220000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__18_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__18_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__30_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"28914D0E0306606A3B0C24977298042328CB4D1078196B1704A0219A662700D8",
INIT_01 => X"41CD13884146808741B1BBA5C82537CC454069F1006C3A693AF1280128386A15",
INIT_02 => X"0ECA0C405D884100B800599C33830FE000805D3C1FE0C087A040808641407E88",
INIT_03 => X"5801649836AC0CB2401346488895C1C96569548895C1D05D6E588895C10000B1",
INIT_04 => X"00783A462A17042A48C265E6220A2B8904201B2029311AB51A25180120030437",
INIT_05 => X"476613410A40615723C00038630601AA112C5CEA6A792A3B198053312A0B182A",
INIT_06 => X"2446250430D36D2E122028C10491006105402A2D035835D84DE61801602A1E46",
INIT_07 => X"DC8125E0BBB2E0CA656E2A081F1430D35D2A675A0E012BDB28116498362C042C",
INIT_08 => X"A5C8854D6E5EFA140134E8523904B35138884100B000E604DC8117E00064E610",
INIT_09 => X"41A5C84561342200678A65A30E002BD95CB41A5B652104B3596887415D618841",
INIT_0A => X"4E33D3655D2D0130D379371BA111014C571FC047D7285304B34014864A401688",
INIT_0B => X"311AB905000D2E681653011837384104B240030141000001B2A8D2440B04A061",
INIT_0C => X"38466E45015CF45E4E025853F2525369A3046E14020460528405984D2E3A0A01",
INIT_0D => X"202801602A391828EA36B90D20480260D975CA05283021468603EA3A792A2000",
INIT_0E => X"04C01F20299E5E192B094C4A1D7100975ED749200C010FB3C03CA0BBA5C8050D",
INIT_0F => X"87A08A006E88418F003CA000000000000098000400A5C805636A625845102997",
INIT_10 => X"A1062029393B124FE666804D2E32D365204FCE2CC00051294B04B2E4018741E8",
INIT_11 => X"C20402A10F008C4502A0C20301A2C20210A296010D450110614596B387AAA580",
INIT_12 => X"5B4927E0EFFF8C04032D10036EC20403A10F008C4503A0EFFF8C04022D01026E",
INIT_13 => X"1820030426002D5F4601E1062D3B1C544A2533002A1E525FC0140105B3000001",
INIT_14 => X"7E1A1208602A905EA704E052F73A3204B2DC3CA07C39388897C1A5C8052BD034",
INIT_15 => X"201B0022E6006C3AD764580AF82A157891697A140105B21D008CB2E00A29AE02",
INIT_16 => X"112C28DF61240058492E037E1AB204E052F73A3204B35F5D8841B0BB45969A7A",
INIT_17 => X"9A4E0A28932627001917536DA611B3DF3CA0402A7F138895C1A5C8A56A406D8E",
INIT_18 => X"5E4E02014C0A52F7404104B3004C0D013C0DA5D4C527465DD1008A19D224A031",
INIT_19 => X"69112494322A003E5655630017F81ACA03536D0A0306062700AA526D0B2C5CF4",
INIT_1A => X"792AD349F456C03401208306C0144106B2400301410000010045963E4DA60110",
INIT_1B => X"34510118251C01289B1E86304161065DCE64184C9C26C02C8107C01BFC523401",
INIT_1C => X"E017550359290B204515BE004A5209042A008A250A04204D9A5E06549A304149",
INIT_1D => X"1C1800670E0368004105E02A792A0804603A84056C3AD119174C2A519403A604",
INIT_1E => X"254055F42A01284839B50CB3C0A3A0BBA5C8251A192B49554045E71A1228D935",
INIT_1F => X"644A2D406D6E014A521830D325530D416DF418804D2E3AE60261060027532158",
INIT_20 => X"2AAD3A57552000D9384104B2940003014100000100A5C82519AA1101289B1E06",
INIT_21 => X"059C46EA006834631A2A006C3AD1290804004B972E310C4149345101182A00FE",
INIT_22 => X"5C602A89521C182500955E09609A66AE3A485D1518331C0130D3654865F45684",
INIT_23 => X"014C9C26804D8E4DA611B3C0A3A0BB45964A520904002B115D0E450130D345CE",
INIT_24 => X"E052342E204C01644A2D602A990C002753450128955EC0140130D345CE5C204C",
INIT_25 => X"444A2D27004A520904E02A792A2700D810B245804EA040020141A5C88553511D",
INIT_26 => X"45CE5C2048E304804D8E1B3701693A1C183300CB01D800316A1530935E190306",
INIT_27 => X"000100B800979C33830FE040458841B069100D697F4EBBA5C8657234190130D3",
INIT_28 => X"381761D3152106520CC11B5C658651011840250E679A3A4104B2D90003014100",
INIT_29 => X"16380057655301B4714079204606289536C05F6A2B5224D31C8600E014A724EA",
INIT_2A => X"04933AD944142B09184029D8092764A3066007A64CAA5225002A1B2C04A71C85",
INIT_2B => X"1A58532D132C5C6A5E14016A5237005839891E2029914D462A0128D155C03461",
INIT_2C => X"35493862042A1B0B609A2AC935404914036C3A792AD24423600A39742B016069",
INIT_2D => X"2BC01F2029F71AA70440658601A106C01B3C04B3404EA040A1A0BBA5C8255D46",
INIT_2E => X"010141B2E0D8542B0038575265D9100164065C4A3D80367C04383BD75518446E",
INIT_2F => X"405E745DAA02196B5204B3557F9326597FD3265D7FDD2640A1A07B3A88410602",
INIT_30 => X"A0B2C8D82197764A0F53004955D56956011917535D4604B3B2F8934AEA2A0804",
INIT_31 => X"B210DB2E00DB984A1FE000DD5D3C1FE0013A0DF100DD8641F6006D8841FB00A1",
INIT_32 => X"9A5E0C042B00384666190164B401495D002B9222EA003E4E2A251A03312A2704",
INIT_33 => X"EE2AEA01D7292D0395667804497D3E1AD7546039001B23602D3BE6722130214D",
INIT_34 => X"C82C602A0D1BE03AAA65605284059A7A4021662D014C5767C0479C46D804804D",
INIT_35 => X"58412603975E5765602A3953EC528B176C5211182A48C261585DB52B200C012B",
INIT_36 => X"202C0154F4265E006104933A582F93222400D311B2787F9326BB4596AA1A0D03",
INIT_37 => X"000097E1006A6F432A0FE014930C10932EBB4596BF649A3A0178AA652678650D",
INIT_38 => X"41C039A0B001000097E10014725C392A07E001000097E100063E5C392A07E000",
INIT_39 => X"1B571D576DEA025779E656202801249772A0214611B240A1A040D38641405388",
INIT_3A => X"64D8442000D8102C4CD4617A4D14016C3A532D4625C05C0144D134205401602A",
INIT_3B => X"17181AAA622330D325D34892222600495371040A397403660458256601E9521C",
INIT_3C => X"48465D08036C3AB5521973255F46356500B950052753396B046A524C1D2417A0",
INIT_3D => X"025765465D0C18804D0E4F0A0F0167EE3A1503C104234C576D06010160313A0B",
INIT_3E => X"006D5C432A0FE001A10D00E95D3C1FE0BBB2E0311A1C0435004A456B045771B4",
INIT_3F => X"D2442B04B201390D4039A04014930A407F9326C03AA040060141B000000097E1",
INIT_40 => X"6A2A0734F91A2A042C28681A6905E01AAA56C604C047293A1C5C0A222E2E002B",
INIT_41 => X"6A2A07281122FA003E5E464D00332A12C10423602A1E525D19644A2D24002D1B",
INIT_42 => X"45965771B4023E36F91A6A6A2400D90057711401383BD75538042C68D4032D1B",
INIT_43 => X"0039A00000B001000097E100036D5C392A07E000000097E1003E5C432A0FE0BB",
INIT_44 => X"72201861045341F41E25007E52525D0A3D42055238782A3904B25000E8104155",
INIT_45 => X"63EA0E21575265D9001E4B3A222400D9005341A6614A0049615A1A23602D3BE6",
INIT_46 => X"3FE000390D00003AAB003A0DBBA5C8854DEE2AEA0158532A390D5C4E35192852",
INIT_47 => X"242A52144161053600312A2704B340E81041E8DD0E00DB5D3C1FE000B8003E5C",
INIT_48 => X"8B004105A052190452006C3A691A193B4104B240030141000001004596935309",
INIT_49 => X"0664D85D9A66C0002A3BDA02D870310C6115B700D2240444F466932204249446",
INIT_4A => X"F95213042B00B865A63A01052C64D364D825E01A0B604A3AF906523819193767",
INIT_4B => X"A04980A0A0BBA5C8657234012A1ED25C0803C60423645871260CA1659A622334",
INIT_4C => X"002BD93040214E473804A0179C462500D2242000693A4D1D73642104B2458037",
INIT_4D => X"465D194F9C262600D22420540160AA61FA02576586132C246A2A950253290706",
INIT_4E => X"5835585F391861045355D405002BD93040214E473804B2FB37A0CE008CBBB2C8",
INIT_4F => X"8CBBA5C8A531AE01313A1917014826010124D335EA4C23072130411A09043500",
INIT_50 => X"8E6E5761EA02E106736421042C74C205002BD93040214E473804B2FBA0A09200",
INIT_51 => X"04B256008CBBB2F811224E5B804D0E3BB70473004109237034022A3BDA16015C",
INIT_52 => X"094E346204D2242000693A4D1D84055D3801482601410A002BD93040214E4738",
INIT_53 => X"543403410E804DEE6AB416015C2A1B9C30E13A745F0A2B1728C971C000532938",
INIT_54 => X"446A1A1544F4669322C0140105B2BBA5C8451A09246A52691AC7009C4E202801",
INIT_55 => X"53C7003E66485D2E112C242A4F9A4A250039520744262B9206C044410A236001",
INIT_56 => X"043100B2D138A0A5A8F11CFA00C865D844154C4A5DEC07C0140164911E20006A",
INIT_57 => X"03320C828038A09D005B8741C800598841004596B33EAA535D0A036C3A9C46AC",
INIT_58 => X"60F91A1967C10440613422002BD93040214E473804B2038A0C00370D468037A0",
INIT_59 => X"E001000097E10008145E392A07E0BB4596D2242000693A4D1D20232A46142D01",
INIT_5A => X"005F9A563918014CAA52002BD93040214E473804B201370DB00000945E392A07",
INIT_5B => X"2704B3B00000145E392A07E001000097E10008945E392A07E0BBB2C82601A106",
INIT_5C => X"5767600039522704B2D887A0A5C8255F742D0A64581D2434014C576760003952",
INIT_5D => X"3FE0485D8841B2E0691ACD0587042D244104B34596B387AAA5800130D3611A4C",
INIT_5E => X"5E62044A470C246A3A264F14254267205881082C48B211B340558841B800065E",
INIT_5F => X"00A5C84516B248E52A0E1B0A78D3005931600039520704804D6E5E3A132C448E",
INIT_60 => X"932220280164D754201A9729793A7A148108B30000B800065E3FE0405D884100",
INIT_61 => X"4100A00D07650B45646506038A0C03280C06640C04640B00B2C46A1A1544F466",
INIT_62 => X"04206912042A300378314F8A01382F2E02D9502704B36D1B004A007FA37C6410",
INIT_63 => X"281041B000A79C33830FE04596D751FB2A585D20480230D36586460B707416C1",
INIT_64 => X"142D0160F91A190FE12AD970804D8E537129011C0328D04523245353B80CB369",
INIT_65 => X"6C3AF21AD168630453254963C0280144D110B251008A1041B2F0342A67064049",
INIT_66 => X"D728AB052029313A8B30010D200038466E01696A14036C3AD75017249A46C047",
INIT_67 => X"AC1097C1B000005B492FE0003636272FE0BBA5C8C51BDC002A1ED25C081F6104",
INIT_68 => X"14210FE00C204F8E56202C014C0A3B370E73640104E00C40212E535304B34132",
INIT_69 => X"400064104101A00D07650C038A0C03280C04640C06640B0000B2E0985E680570",
INIT_6A => X"861E204401640664D35115042B004955955E290E73642104B3791B004A007FA3",
INIT_6B => X"10414596494B20000260703A98082C648646CB00DE64185C8A4D3402743A0264",
INIT_6C => X"32AC1097C1A5C88553135C2A2B4E5B25640130D335585F2A00D7503704B35B28",
INIT_6D => X"F422C0470E1B0A245153E804260038009C4640654E5B8053B30473642104B341",
INIT_6E => X"9A7A2B0050299701EA62C52B2D13B3535388410045962A39B80D202C410E0063",
INIT_6F => X"4D9A62804D2E1E525FC0140105B2079F0C5F0034A07600C38641406588414596",
INIT_70 => X"1AB51ABE00680041056E5402043300195FFA2CC10639280148465D1903C60420",
INIT_71 => X"2A03E001340DBBB2FC4555AE02E6062029F76A08517100D02811182378314FEA",
INIT_72 => X"41B2A44A4AE625620536482267FA004A472704B3B001000097E100FFFF895F39",
INIT_73 => X"652D1464BA61B314104C4E14104A05A003043734D97100678D393104B26BC486",
INIT_74 => X"C68641459610391111B300380D03D70C4FC58641B2CC14289222B314104BA5C8",
INIT_75 => X"552A2046C605006758352804B35338884100459610391111B301380D03D70C40",
INIT_76 => X"0178196B1750D805006758352804B300C85D3C1FE0755D2B128895C1A5C8C567",
INIT_77 => X"8841B2C8AA65A0219A66270053351C28F148FA22C02B2D0367004925F45E1419",
INIT_78 => X"E805008C007FE8C8C7104100000100A5C8652A951EC205006758352804B3402B",
INIT_79 => X"3495BB00AD0000356F0002345780D3B304000773642104B2D801A000012D017F",
INIT_7A => X"46B0003F9D33830FE0C101A00000895F392A07E000349DC7914A13E0DD0E3442",
INIT_7B => X"6286414C12328897C14000344300B0004D9D33830FE0419AD7C71095C1419C7F",
INIT_7C => X"344FCD00B800877F602FE0B800CE5F3FE048628741405F8841B800CE5F3FE048",
INIT_7D => X"3648657A38F0529F2801281119D74940491403FE10B30000895F392A07E0FFFF",
INIT_7E => X"4100004596D224205C014046452000956678052029CC4C4642E10423788C4674",
INIT_7F => X"65620E4053334061B45EBA7225462604B34062864140128841CA628741465588",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__30_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__30\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__30_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__14_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"01600A6B4B5D49683904B3596387415D12884100A5C8254F0639F76811182063",
INIT_01 => X"083B3B04B37F622E5E866226620B864A40798841B2B0D335D94F06645521C82C",
INIT_02 => X"56A60449683904B3550B864A4596691A8D044000587D9402D138576546025853",
INIT_03 => X"696A1413B35B2B238897C100B2F4A20449683904B345963E5752013E66535DA6",
INIT_04 => X"28D710B36B018741405F8841B2F0B4011917133B4F2862042A1E6652D8281760",
INIT_05 => X"30EE00A6044F0CC15F97620454652A2D0FC1530734286B89002A66D945201C01",
INIT_06 => X"244F00CC1D80530D70744227003411A016B387AA0598A0658E13B2A5C8451A09",
INIT_07 => X"000100B29CA305001A2A027E3A1918A05219033E4E142451534804A016D801D2",
INIT_08 => X"4104B25C8037A06080A0A04003014100000100A596B301AA0598A0658E13B200",
INIT_09 => X"B4112C28D044C0003E5E4A5E7401D8703128C10A202C610468006C5211183738",
INIT_0A => X"D228376340258E030678515D4A16A1092324EA2A9C46736401042D0CE12A5B71",
INIT_0B => X"37384104B2788037A02F018CA5C8050D2028015C2A4F0A01A106804D6E4EFA02",
INIT_0C => X"81051853172D01544A25660C414126520118255802048066840568006C521118",
INIT_0D => X"1718201B804DAE56F426492CC10673640104E00C235C6A2B9C362328C865740A",
INIT_0E => X"172D0128F138185335092037CC49790C814D3402EA524B1D84052A1B1724AE1A",
INIT_0F => X"68006C52111837384104B28080A0A0B5008CB2E0610640250E3703042B001853",
INIT_10 => X"5761EA020678F12AF2520B6086470118EA1A40258E03A6043128C10A202C6104",
INIT_11 => X"576D8A536D040A39994E2230411AEA661818C047EA2AB20480535309235C8E6E",
INIT_12 => X"6C52B10EE00C26003E42C8691630D361EE160148465D190341057300011C6304",
INIT_13 => X"520068006C52111837384104B233008CB2E00160985E680570240244D1717900",
INIT_14 => X"0E63F42253002A39DC04A02A2A19035C660D4141265201182A00EA520D170204",
INIT_15 => X"6604192B1C5CB40A202C0148465D190301309346860BC0140105B3BBA5C8854D",
INIT_16 => X"C02801282C2920006C52D150A2659A62804DEE482E22C01BBC65A60255291903",
INIT_17 => X"41000001A5C825634635595318042B48C24F060106083C700218260C4162A621",
INIT_18 => X"640104E00C40212E535304B34B80A0A04F0037A053801B004A007FA35B000601",
INIT_19 => X"4D4E52481D8062D1380160792AF76A28042C783139D55C804D0E3BB704000773",
INIT_1A => X"030141A5D0056B343A575540654E5B460038006C3ADE649830E12A6C52376380",
INIT_1B => X"009C4E254441092328D044340026092B0049611A64A67152384104B2FEA0A040",
INIT_1C => X"59008CB2B45953D804560061052017585DB461B93801052C28D15520699206C0",
INIT_1D => X"579A30A1659A622658024C4A6149380260AA21461D84050A1A110452384104B2",
INIT_1E => X"02E106202F2A223D00A60640412602016057655301D22837633F000648465D19",
INIT_1F => X"03014100000100B0BB4596D22837639353094C4A6149380248260581051822F4",
INIT_20 => X"3C062A140204232003609A4E576D0651011837384104B2568037A05A80A0A040",
INIT_21 => X"6204495D8A53710E3900A105235C6A2B9C3684050A1A1118C0475749972E001B",
INIT_22 => X"FE37A0C0008CB2E021570130D34D535F401AEA661828C971C0003E2A57492534",
INIT_23 => X"4126022A391C182514020480668405465D06609A4E576D0651011837384104B2",
INIT_24 => X"6280A0A081008CA5C8C547C955E6026C3A311A2B092B58610E39000A538D0F41",
INIT_25 => X"258E03FE2A1B1825444105450061052318EA1A006B745E6A1B081837384104B2",
INIT_26 => X"06791861043E26AE1A1730D361EE160148465D1903410573048105D228376340",
INIT_27 => X"1D008CA5C845250E3703042B001853172D010E4900313A3C0F804D3456031CC3",
INIT_28 => X"140105B3BB45960A1A9106C028C10A232003609A4E576D0651011837384104B2",
INIT_29 => X"4100000100B2B4F95213042B0068000130D36D4645C01BFC3A2663C04B2E62C0",
INIT_2A => X"38035C66010160D935404539532704B201010D00865D3C2FE068EC86416C7F88",
INIT_2B => X"45D15DA70CB200865D3C2FE001010D6C2A88413F008CBBA5C8055F2A67A66126",
INIT_2C => X"4A4D73884111008CBBA5C8454539530704007BF4665825E02A5B2BD348204FC6",
INIT_2D => X"E052342E202C0160313A15672104B26386ED26E701A001010D4586ED26490B86",
INIT_2E => X"00BA7F4133012D000001B0C001A0B000ED5D3C1FE0BB45965865E652D56CCA04",
INIT_2F => X"2A2A620664D82C006345358405D2352B006C3A301A192858037412B3E1A5A04F",
INIT_30 => X"2B006C3AD928005F6A29B7062204B3B0005BBE2B1FE0047F0D4C5B8841A5C8A5",
INIT_31 => X"4DAE2A2A6225042204B3653888416D80A5A0B2CCD465065F6A4F14016C3AD048",
INIT_32 => X"C88846138895C1B2A893023E321A78576DC064431DD10CC11FE6000628D04580",
INIT_33 => X"289072E00C804DAE652000D900585D266326007872C6072204B2401C2A8897C1",
INIT_34 => X"38884133AB01332D33AB330100354800014202BA0B00A50DBBA5C8A56A403A0D",
INIT_35 => X"4596F83A266320280164942E2000D9006C3A691A19172108C05F6C6AAD0CB361",
INIT_36 => X"7B06072204B200E15D3C1FE09080000142A400E18641A901BA8741AE013F8841",
INIT_37 => X"6A140DA151206B8700B4605755555520530D289B465B30414A9200524A241700",
INIT_38 => X"2494460704004EEE2620459A225B00B81AED2A9530014EEE26C0000A6B5B0029",
INIT_39 => X"00296A14656304CA2B425C014846450C0440527711006445166C3A2D03672801",
INIT_3A => X"FFFFA46F0BE000010035BBB2E4854DAE65E00CB938E104E00C2029D849576349",
INIT_3B => X"42BE00ECED06C300EC8641CCED8641B001000097E100FFFF9F64392A03E03300",
INIT_3C => X"2A66991E2000584126072204B202BA0C0BEC0B10EC2E00ED5D3C1FE092000001",
INIT_3D => X"4A52B20C2C5C2A1B1C040043D35DC904234CAA520063253BE00C004348356804",
INIT_3E => X"6A5327009853F1003E5E464DE00C6072C603860D00672A02AA0DE12AD944204F",
INIT_3F => X"E306206BF50420390964A671BE005529111B20636601384666015335D904235C",
INIT_40 => X"04C047792AD754D5042204B3A5AB01A50DBBB2FCA516DE707E1A2340D35D091C",
INIT_41 => X"B359BD8641A5C8E52A6B51006BF42A5331240058617A29D704C067F83A2D5FA2",
INIT_42 => X"671850F80A25042204B3B2E44E3A1118253442092378974DBA25027846062204",
INIT_43 => X"FF9F64392A03E06D007F132A8895C1A5D0251386342413201B6A05001B203955",
INIT_44 => X"12600624AE6A1903D80012178E6CE30480262417B36F2A884101000097E100FF",
INIT_45 => X"604C5F0D072204B2B2B0D33189262360DE6040352364A516D870E02A2D1B0B78",
INIT_46 => X"417F8841BB4596B94A2A6706447A39D9552400585D74320E28D8715735992A02",
INIT_47 => X"96491DC75C0C30D3296705C047693A1028D0647E042204B35B5D8841B010866E",
INIT_48 => X"39092B64631501280D344C532D0F015734221E0101282E7B4104B36182884145",
INIT_49 => X"A0000045966C3AF148FA020D1992665808E01AAA394204B3404D884145964939",
INIT_4A => X"008C0033003549003342B000000097E1009F64432A0FE0CFB91041414EA041A5",
INIT_4B => X"47003342B800669D33830FE000000097E1009F64432A0FE05605004333BFE805",
INIT_4C => X"0000326F0001005533BFE805008C003300354900334240A5A0339504008C3396",
INIT_4D => X"0C21638A37F95213045264A32B7A4403204306B2A701030141000001B0BB00AD",
INIT_4E => X"6A0B632E1E804DAE2A2A6225042204B3639FA0E6A5A0BBA5C8A56A3C44021826",
INIT_4F => X"536E2BB70E214686572204B3EF9FA0B2E0D71919034105205374010164067831",
INIT_50 => X"96D95D0130D34DAA522029DF61BC609546C823C0440370740E21399162C04758",
INIT_51 => X"9736201B6A052029D754EA560043944680367C04B8521179A80CB38B0033A045",
INIT_52 => X"266320001822341E237C055FEA6A792A3B19405D4A02182B1134484BBE005861",
INIT_53 => X"004FCE643851341E201861042D4746352A002A1B190B0248F42E84050A1BE83A",
INIT_54 => X"B4652378314DCA5D0B78576D571401280D1C035CAA65861D610438468603410A",
INIT_55 => X"E106804D2E4D266325042204B35300003343B2A8B152AA0258412E02AA018D69",
INIT_56 => X"FE2AFB04002BD04540357B20620B2C785161342227006C3ACA2B235C6A5E1401",
INIT_57 => X"117908185300536D6A04FE325337C0474A2A37770A60905211288D30A1215A02",
INIT_58 => X"55555520530D04602AD928804D6E1B6D04B85211792804B3400033424596B852",
INIT_59 => X"2B495F995E15289A4D34034949262E5315A1112C30D355D830492CC106236057",
INIT_5A => X"E1009F64432A0FE0C133A040020141A5C8A5659A4A2029DF61BC4C460A620600",
INIT_5B => X"30D3454E21C03401208306C0144106B2C300030141000000000200B001000097",
INIT_5C => X"18810A2B5462067674011825208105696AF432204C01242A232A2B29093E4401",
INIT_5D => X"0D2100B2DCA0A05F37A04831A0A5C8255D86579A07C01BFC3A2663404D3463C0",
INIT_5E => X"2ACB28A904000D2100B25B008CA5C805636A66CA691660D95D0128EE2AAA0400",
INIT_5F => X"5338042C2453531830D335585F2029D34957652A4D5A0F2D0049531178914D6E",
INIT_60 => X"39290F804D0E1A7204384686034105204666064065E62AE72A5B5D2B18022453",
INIT_61 => X"08B28000A0A0848037A08800060141B0BB4596703A2D2F014C6A2B20471A396B",
INIT_62 => X"61E01AF4026C3A393BB162BC5C4669A305236001249A46C047C75C461D531781",
INIT_63 => X"06804D2E4D9A56C01401052C68D403696AF41A204666064049142D0130D3494A",
INIT_64 => X"61270C215F742D0A609A265349EA66C0002D3B9C30A152190323062019AA11E1",
INIT_65 => X"40020141B100005B492FE0003636272FE0BBBBA5C8050D2028810D4045471A17",
INIT_66 => X"88042A00192B3704B2E57CA00044463FE0C0A0A0C537A040A0A04537A04031A0",
INIT_67 => X"A5F8C114B2BB007C0DBBA5C845618E4E205C01649846602AEA400160691A5252",
INIT_68 => X"02017E4FE0FF8CBBA5D46552E91A95048029670BB25300A000017E507E7DAFE4",
INIT_69 => X"1A49028FC102057E4F462149028FC10C008C02037E4F49E2485E4D36420280C1",
INIT_6A => X"E04A104802480283C1A5FF8C0029373FE04A9C48028FC1B3FF8C0034373FE04A",
INIT_6B => X"E04AF13FEA3F0283C100AB006B5B491FE04A884D424D0283C195FF8C00E6363F",
INIT_6C => X"2D13B259743D028FC100AB00285B491FE04AFC4CAF4C0283C100AB00275B491F",
INIT_6D => X"098B0C01310D64FF3F028FC148FF8CBBA5C865526E3A9512017871520063251B",
INIT_6E => X"243C3FE0B0BBBBA5C8C547F96818286C1A0D016800410500232E639A222604B2",
INIT_6F => X"937AD320A02A2A01460540314915020452384104B24003014100000118FF8C00",
INIT_70 => X"58712D6B141B810A2D5F740E216346016105602D14244645002BCC60D8548405",
INIT_71 => X"00D728CD092200B272A0A0F537A0459693530960C9281178865FCE64B80C2C64",
INIT_72 => X"06235C2A1B1C30D335585F2A0067000A3A7104696A14036C3AD75017249A46C0",
INIT_73 => X"464B05204D9A622000D728CD092200B2B0BBC4A0A04737A025008CB2F0342A67",
INIT_74 => X"2FA0C0BE1041464EA000000000000000000400B0BBB2F0342A670639006C3A9C",
INIT_75 => X"54491413B207720C7300727106D600001E2300647FE7DF0001A0E3004EA06E03",
INIT_76 => X"1464783A8619804D6E1A2A023E46466306150130E6500118804DCE5FD720404D",
INIT_77 => X"015C4645A80479286204D028155F02608A26403584053800384686034105404D",
INIT_78 => X"F400C928490872003E4E144C0A1A390920468E03CC1C200067001929151B424C",
INIT_79 => X"37CC45C00051294B04B207720C0E710B72710E407F7126B0012F0DBBA5C8C527",
INIT_7A => X"390B30D34DD35D0C1840212E5373046C3AF36AD9042334485399175731D32D20",
INIT_7B => X"651404372C212BD16518182618A1016A523700CC1C34000630D3259136405D9A",
INIT_7C => X"4DB4569409B2840000A00072C27F1FE08E0002720A938001A0B0012F0DB2DCAA",
INIT_7D => X"6C2A00F91A155C2A67EA0021092B48C265EA22D825804D6E3AF22A5925236453",
INIT_7E => X"3001575265EA6693224045393BF1094065663AF22A7905002BC9212A0DE152D1",
INIT_7F => X"08205D8643C81C00572A63403523244635422801247402512F4A5FC0002D3B9C",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__14_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(13),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__14_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized12\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized12\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized12\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized12\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__29_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0ACE01A0B0009E813FE002720C07720BBBB2E0D728B51AD82526009252910101",
INIT_01 => X"4105E02A29522D04B279001E2300647FE7418001A0C0005A2300647FE74A0272",
INIT_02 => X"AE657402905219286D0477302129196B0C3B490B23644B452063FA01CC1C3400",
INIT_03 => X"647210DC8125E0404EA0C000462300647FE7B0009E813FE007720BBBA5C8854D",
INIT_04 => X"8002A0012F0D01030D01020DC800A000727FDC8127E012008C01020DC800A000",
INIT_05 => X"8603196B0F30E65001182D00D168C96D2E4D4E0BBC784929B80CB28A0001A08E",
INIT_06 => X"F818C0475939DA02AA0DA1319A5E2D03DE70200093122C2003043500495D2A4D",
INIT_07 => X"234CD46158619856244CC104000D204C01602A1E464766034A5218242A23E666",
INIT_08 => X"455D742907605735992E616A804D8E26241764006C3A2D2B9262804D2E1E524B",
INIT_09 => X"63FA0D2204B2648002A0009E813FE0948001A0B10056693FE0BBA5E44516B248",
INIT_0A => X"29C8657442E10AC01B52042C30E6504108804DCE5FD72020462E6323644B4520",
INIT_0B => X"5EB51AB219008CA5C82563D72D204D2E1E2700491D875EB2D603A040B5E00C20",
INIT_0C => X"353904B222008C0056693FE0BBB2A0030437005845C768D16C20004965C65D95",
INIT_0D => X"0D07720BBB459649655833D825202F2A0E4169D16C2A640230D325D32D232CCA",
INIT_0E => X"20295725D3702063FA69432A314F8A01B978974DBA19410F2A66A50CB3B00001",
INIT_0F => X"6D044A47662B210B804D2E4D6E112C30E6500118804DCE5FD72023344C53B765",
INIT_10 => X"647210DC8125E040001E2300647FE7C001A045964945796A97612E0179291128",
INIT_11 => X"FA0D2204B2468002A0027FE900727FDC8127E009008C04BFE8C804A0047FE900",
INIT_12 => X"C8657442E10AC01B52042C30E6504108804DCE5FD72020462E6323644B452063",
INIT_13 => X"B222008C0056693FE0BBA5C82563D72D204D2E1E2700491D875E4035E00C2029",
INIT_14 => X"0BBB459649655833D825202F2A0E4169D16C2A640230D325D32D232CCA353904",
INIT_15 => X"04B3C101A04152A0521031362FE052012D00000100B1009E813FE000010D0772",
INIT_16 => X"01BE9207720B009E813FE000000100B2C0D724205CE104202F2A426105460C22",
INIT_17 => X"04AB4402A0C2027292000000000000000004F5FF8CC20101A107014CC101A0C2",
INIT_18 => X"0D4857024101040D01026E52000043000C02511A008C4573710297C1C20302A1",
INIT_19 => X"024AC20302A1C002A0C20201A20000000000000300D2FF8C03022D0B570B0130",
INIT_1A => X"26632E01E106602D7404D7284D04B2520000282300647FE75B8007024A600011",
INIT_1B => X"40CD6E3D0264A671E02A69527C0B237892640530D37906036A524A5278040A4D",
INIT_1C => X"07024B03024B72024EC100A0003C21271FE0BBB9C80507804D8E262500B202AA",
INIT_1D => X"814DF4661818250C2204B25D6F88410000000000000000040092FF8C03022DB0",
INIT_1E => X"2C0061000B72115000428841EA0201A07CAB007C0DBB4596AA7A196453450E0F",
INIT_1F => X"0423242A1BD921A61A683AC047EE1A97565265804D4E1D232CCA353904B34700",
INIT_20 => X"3AC85C0C4446635A082D006C3A5929971101282C299153132266054045C74CBA",
INIT_21 => X"628000A0000A21271FE0CC8002720AD1007F8841D600A98641A5C805636A629A",
INIT_22 => X"4CC92527008D69B465235CEA1CF40201246A2AB931EE2EC047792AC96D4A04B2",
INIT_23 => X"2220286204B2001072A36C1BE067037292A5E04A450B288D30413A2D0F0D64B8",
INIT_24 => X"B007720BBB4596B205008CB2DC94460B045200311A0B30E60842050067536593",
INIT_25 => X"046A3913020128D0642B00B94A2A67065013600A1A720821302129183B5204B2",
INIT_26 => X"1C425C410A2E232A46140161055238D925C9006A3A0B18492C220FA0319A3679",
INIT_27 => X"B002720BBB4596B94A2A678604C01F20295731D300522918608A2640358405CC",
INIT_28 => X"7211490000004200077211C300728741C880728641CD8086A0D1007F3F8897C1",
INIT_29 => X"0B725BE3009E813FE001000097E100F080432A0FE00007725BE3000000350007",
INIT_2A => X"58530E619322005F6A53485DC04753254963403A19391B240A53955E9509B22D",
INIT_2B => X"22E618602AD064250C2204B2012E0D4500000043000C865172864EBBB2E0584D",
INIT_2C => X"B386AAA5800160B92A08194A0CC1670E53574D8A01496548555D4D9A04C01F00",
INIT_2D => X"AAA58001600A19B10E2204B2B2F8591BEA00383B405D4E266605005734632600",
INIT_2E => X"0440219312B35B5D8841B2F851652E52F5040043D334D904801947083700B386",
INIT_2F => X"18250C2204B39B0038398897C1B5C8AE350150E9044B00D9347C04D2352053EC",
INIT_30 => X"2E26001019270F7101670058790A78C928A705E02A1919D73408785755D54518",
INIT_31 => X"1A8C5ED7002A1E061A193B726A7A340130934666045839F71A08288D30A16597",
INIT_32 => X"0F816659452E63006BD4216E03C604E02A296AB46142480330E6500118232868",
INIT_33 => X"388405933A1929D725245C0178914D0E1953492029D21925002A19F1000A538D",
INIT_34 => X"994E007B060F2204B3404D8841A5C845531E2857715B00CB310334281B1C24B8",
INIT_35 => X"00010141459649213A51374F0E78311AF2520B4C4A1D5740E104001B2330D335",
INIT_36 => X"49140FE12AE7503704B2411072260E710B72710E40007126007293C07271064E",
INIT_37 => X"39372B1778F1486E0E0167536D4A05605E3A3F026406240A3BB75E1A03D9345C",
INIT_38 => X"1041031077692FE00E710C10712EBB00020141B0BBB2D0392BD1655808002B5B",
INIT_39 => X"BB45960A1A7905402D06039C4E25000A39D1342804B25B03A0C20310A28A00BE",
INIT_3A => X"026104583969082000D810B201020D7502A007034C5B800472BF0395C17D008C",
INIT_3B => X"1AAA56465D002B5763465D5908260C012BD828172909208E1952082A005771B4",
INIT_3C => X"472FE0A5B46104B2CD00A0000329482FE0560003A203AAA5940300B2BBA5F4E5",
INIT_3D => X"0FE0BBA5C8054FCE48EA023E53F414A111B2D203A07EFF8CC20303A1BB00032C",
INIT_3E => X"720B4000142300647FE7C007720AC02FA058050141B000000097E100F080432A",
INIT_3F => X"5BE30E710C10712E02720C00000097E100F080432A0FE05D030141B0007C0D02",
INIT_40 => X"23606A3B5B5DE02AE7503704B202720B530010006100729340040141B02C0B72",
INIT_41 => X"214D6604182B136BD4217852686A20297A3A79520830D34DCC290B787129EE1E",
INIT_42 => X"A5C845537E06C01BDC005845471A176123645349540A02604A614035602A8D0F",
INIT_43 => X"721158005D884100B8009E813FE02D0B725BE301000097E100F080432A0FE0BB",
INIT_44 => X"52590A2029B81A3152085CEA1CF40261049A7A53003E260613B3772C0061000B",
INIT_45 => X"80192704B34596D2354041862F220F4041262F0130D37937132C30E6004105A0",
INIT_46 => X"2C8208B35173874155128841A5C8C527F400C92849087200534126270244D171",
INIT_47 => X"8D69742A40613422804D2E678A11B35F2B238897C145961039370389520C1849",
INIT_48 => X"1B6A5E2A4DBA0480192704B34038398897C1A5C80522EE662051940126094B00",
INIT_49 => X"4FAE042330D335D94F062C6E04D9341C78062701289302140F6129AE6520002D",
INIT_4A => X"02036E07034CC20403A1C103A0400301A200000000000000000400A5C845250E",
INIT_4B => X"61000B7211C007720A4002720A40BE720640BE8646735D884100EFFF8C04032D",
INIT_4C => X"63128841A5C82563D72D0022E600E1062029E71819270224B868D413B3C02C00",
INIT_4D => X"96D91561040A39D13408249432C05F6A03E60A50302163651A4804B35FBF8741",
INIT_4E => X"00410000004F00F080432A0FE0400201410000000000000300B8001F853FE0A5",
INIT_4F => X"C000D7284D04B25A8002A000022D007FE805008C017FE8C8107226404EA04001",
INIT_50 => X"DC28C9350063E52AE7501704406526526E1F01600634D8696C1A2A00D2281761",
INIT_51 => X"6A290960D92D0160AA61FA02AA0D41537E0560727442533F0330D3619A30C11B",
INIT_52 => X"A20000000002B8002D6D3FE002720B05008C07720C02720B10722EBB45960A4F",
INIT_53 => X"03C1042378116BD45D2A635E02585D3A638A0D2204B2710001A1F501A0C20110",
INIT_54 => X"C9BF0141C101A0BBBB45960D3BD36CC04753254963000D205C0160EA6AD82837",
INIT_55 => X"A5C82529535534093E242304B34F2B884100EDFF8CC20101A107014BC5720141",
INIT_56 => X"461A6905402A0A274104B3552A884145969752E909605EFA784104B34F1C8841",
INIT_57 => X"E852AB0CB35B5D88410000A5C8652A95028308B3405288414596975209044031",
INIT_58 => X"2F9E33830FE0402A1C8897C145965839891E20006C3AD064331C016055291028",
INIT_59 => X"8841A5C82516AE340528CC542B005355F408250090522704B3592B884100B800",
INIT_5A => X"41D3598841A5C8A50B49780140941E200CC15FF904001B205DA601D810B35B23",
INIT_5B => X"092344C515AD008A191528C961EA10B38D8039026E8FC194000E874199006B88",
INIT_5C => X"30213B52006C3A793AB7022A1E8E291178D3340128CC546D006A52C0479316A1",
INIT_5D => X"3BD31C2024620546001929EF6818044A0C4145C724465D5317210F2A00195392",
INIT_5E => X"678D39710458618E4E3718F92A68043E66535DA6568630213A5B29016453490D",
INIT_5F => X"E0401C8841A5C8255D8629F709370058530E19C82D4B3901605779E656260C01",
INIT_60 => X"11B37A9E0B8693E3000C8697E3402A88410000B800579E33830FE000865D3C2F",
INIT_61 => X"47EA2A12508D0F0147264D6637030440412E4E9A00B460933AD9443A1B974D14",
INIT_62 => X"024979F4665825301C61045821CA555765D848006325632E5F060440453463C0",
INIT_63 => X"1104260CE152342E20000224AA6146627100551A3104B27C7F88410000B2A893",
INIT_64 => X"2E00A45D3C1FE000000097E100556F432A0FE0BB45965953404D944503648D39",
INIT_65 => X"0FE04596B9312E020354D2446C702529F36AA70CB35512A40A660E8841B010D2",
INIT_66 => X"2029F36AE7087100551A3104B35312A40A64168841B101000097E100556F432A",
INIT_67 => X"5012A40AA580551A3104B240388841B100000097E100556F432A0FE045965953",
INIT_68 => X"29F36AB904B20D008CB2CCB404B24A14A40A19008C459659532029F36A270EB2",
INIT_69 => X"495DB421D3003E2A57230A178108B340A08641405D88410000B0BB45966B5120",
INIT_6A => X"4062C511B3DD002A432A9644002A4383009B864188000E1C8897C10000014596",
INIT_6B => X"204306B361CEE41097C1A5C8052B0D65462A810D606A170627006700C9197719",
INIT_6C => X"9B0B199B0BA5C8C547791A194F8E0D002B94010D654602C10423787919371501",
INIT_6D => X"050067D7641860AA21D948202801289312B201000097E10002466F392A07E014",
INIT_6E => X"34281B3204B276199B0A7A168841B000023F3FE001520D4152A0BB4596F36A67",
INIT_6F => X"0140C8440734283B150AB25252A0521031362FE0149B0C199B0CBBB2E49A1601",
INIT_70 => X"00014301012A55A5C04104B26E252B8897C1B00000466F392A07E0BB8596385C",
INIT_71 => X"B0BB4596B205008CA5C8052BB2CA0101410DE54602B201BFE605008C85CEB2C8",
INIT_72 => X"34281B3204B231008CA5C8854D6E5EFA140134281B3204B254149B0A40388841",
INIT_73 => X"720063251B8D4F026455215D0D814D2E63EA2A793AC05F6A031917133B0052F4",
INIT_74 => X"199B0CBB45965953404D94450334281B3204B20000B0BB4596D949024C2A67EE",
INIT_75 => X"97E10001556F392A0BE00100024F022B9E0000000002B0521031362FE0149B0C",
INIT_76 => X"4F03930B02299E00000000022BAB2B040254C001A0000102A4816F1AE0010000",
INIT_77 => X"AB29040254C001A000010293816F1AE001000097E100016A6F392A0BE0010002",
INIT_78 => X"A0401001664600A00001764A2FE012014B14014C4803A0000000000000030029",
INIT_79 => X"4596B301AA20CC410F2D03B9312E02EA521206E02A392B0724B868D413B26003",
INIT_7A => X"6F432A0FE0CE03930A000002AB01AB440201620000000002B0BB00AD0001024F",
INIT_7B => X"60B860210F011BD110B37112930A15010E1C8897C1C087932101000097E1006A",
INIT_7C => X"2C01344C53535D0278713A265F0A112C602A26D320202801644B45A0215A5E02",
INIT_7D => X"009B930EBE2B15E0BBA5FCA521D9482034C117B257199B0A7987A0A5C8655EFA",
INIT_7E => X"41029BBBA5C8A5658E03523519648D397105201B8D03DE6020459A365804B2B0",
INIT_7F => X"BB4596D945B214930BA5C8253BF108B34914930A2EF82204B268149B0A6C9B87",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__29_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__29\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(13),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__29_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized13\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized13\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized13\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized13\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__13_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"6B6F04EA3BD1285704B36114930A5000688741B001000097E1006A6F432A0FE0",
INIT_01 => X"E85219043300D9282D04B2459649658D39F1082E780204E00C2328D265370019",
INIT_02 => X"B800935D3C1FE0BB4596497DEE52D56C2E780204E00C40615365D30114170134",
INIT_03 => X"1E61046C3AF36A0760B81C0330D335594914370148AA652037CC452B404104B3",
INIT_04 => X"E6060067483D87027E1A1270B40D41291860B8642A12B375258841A5C8855313",
INIT_05 => X"00168841A5C8253B202B0C4411178E0C414920462A03191793260454E53AA602",
INIT_06 => X"AA614E33D3655D150128D2442B04B27414930A00000097E1006A6F432A0FE051",
INIT_07 => X"C84516B260E106005E26013E46465D5000B25552A0521031362FE014930CB2A4",
INIT_08 => X"459A72201B2D13B3551A874A59128841459649658D39F10A2E782204B3B0BBB2",
INIT_09 => X"8CB2B0D34D571FB24C14930A2EF82204B240388841A5C8255F46624900191733",
INIT_0A => X"930AC000A0003221271FE0407F93264006014100000100B0BB45965953B20700",
INIT_0B => X"03609C460724D3712A00196BAC0CB214930C00000097E1006A6F432A0FE04014",
INIT_0C => X"013E2A59455552087074168108B34052A0521031362FE0BBB4E02A26D3202430",
INIT_0D => X"B101000097E100FFFF7C80392A03E051047F41555D884100000100A5C8055E26",
INIT_0E => X"00793A6601A605804D8E539115012497729809B35D010141010C6E1140388841",
INIT_0F => X"3137CC5D0778576D804D8E539115012497729809B340020141B2F034324069F1",
INIT_10 => X"020D459B68938695C14C0E1C8897C1520601414006014100000000000003B2F8",
INIT_11 => X"9B764A1FE0CF14680AC600A00068764A1FE0DC14930AC600A00093764A1FE001",
INIT_12 => X"67536DC9006C3AD755D868630A20191870B411B24A8002A040149B0AC000A000",
INIT_13 => X"235C8305D8302A00182AEA46012003183700B286AAA58006648D397105E02A57",
INIT_14 => X"1CC3064430E11A2A018D12B24C008CBB4596295E9403E10640212E63FA15A109",
INIT_15 => X"319A3619064B6C8205D830201A1401D870000D4F4C0130D3491401312A120301",
INIT_16 => X"0FE0BBA5C8050737003823EA1D1430D349262E804DCE5FD72064000A393C03B9",
INIT_17 => X"03042A00574D97222000D311B34100107F00ABC100BD93000001B800B79E3383",
INIT_18 => X"C04758536E1FB40480361C64E600EA3A551A9B06C0140130D3454E2120480220",
INIT_19 => X"1A6D04D91C405DAE4A6653A10CB3B2A8984E42006C3A2952CD0420296C1A5725",
INIT_1A => X"4100000100A5D045531E64064C9C260057947278046C3AD129080433006C3A6C",
INIT_1B => X"A5659A62265402042B003E4E14609752290E3100687C011837384104B3610301",
INIT_1C => X"000100B800C94E3FE000023F3FE0C0107F00ABC100BD93404EA040020141A5C8",
INIT_1D => X"A10479740A2891624061B471000D2045140D4131D744C0144106B24003014100",
INIT_1E => X"D349EA162106404DAE214602A6044D00574D9722404D144C8E30A165974E202C",
INIT_1F => X"283B1C03A60440216601383B60528405577937015835994608182A00792A083B",
INIT_20 => X"E60A002B34010D658E6321302117995CC410996024172029312AC74425440134",
INIT_21 => X"2000182B716ABE18A169436A0D78D300FE002A1E266AD54D46266205E01AAA56",
INIT_22 => X"F42E200093122C7CA521D301AC682515C01FC015A9682515643801605731D32D",
INIT_23 => X"07008CB2CCAA52B24A0B9E0A25C46104C9453400A604404DAE2146024105204F",
INIT_24 => X"002B8841B2F8F71A68053418035C66158108B3515D88410000B0BBA5C8A50BB2",
INIT_25 => X"466DEA0E014FAA5220393104B261009E92B0BB00AD004436272FE04C0B9E0A43",
INIT_26 => X"9E0BBBA5C8054FAA5220393104B2B00B9E0BBB4596B2009E2C471FE005B0D345",
INIT_27 => X"004436272FE0B00B9E0CBB45965861342220393104B2520B9E0A60238841B00B",
INIT_28 => X"87042D48220F605E3A2F0170B401D728115D020AB35D87A0400E8841B0BB00AD",
INIT_29 => X"5D0B9E0AA0007B87414059884100000100B000877059BE2B16E0B2E0691ACD05",
INIT_2A => X"0D193204B2B2B0D335D94F06506905204F862F01484A617E006A3A0D193204B3",
INIT_2B => X"0930D345FF1B09182D00BF78516D2E1B57336E790528CB452B00584914016A3A",
INIT_2C => X"5765CB102C600A3B7402EA5EE63BC70400678D391124EA5291222A00DE44153B",
INIT_2D => X"E04C9E7706BBA5C8052BD91C066453492A3BA82B200C0167534954025C2DC000",
INIT_2E => X"4104B35587A0B09E920EF5FF8C00015D3C2FE04B019E92B09EAB0E00775D3C1F",
INIT_2F => X"A5C885266000B387AAC08067188208B24596B2480527D3342434210F605E3A27",
INIT_30 => X"C8042344C665D364F868783AE02A2D1B17608603CC443804B300925D3C1FE000",
INIT_31 => X"0DC2027FA2400101410000000002B2B448539904201B20633A0102602A1E525F",
INIT_32 => X"41E5FF8CC20202A109008C00A20D48040043000216492FE019008C4502A001A2",
INIT_33 => X"008C017FE8C87FD02640010141000001B100280D002831482FE0C052A040E410",
INIT_34 => X"C10000A4AB01A40DA4AB00A40D477F9C2640060141000001B1009B2D007FE805",
INIT_35 => X"E60261043E4E2A251A13B207890C7E009EA0B400881041C71D1041408C698897",
INIT_36 => X"4045C740D17023285767536D5B0C214D06242E5218289222EA2CC1068053673A",
INIT_37 => X"41BBB2FCE52A193B731AC704005FCE641804001B1C78861B6A3B0C047B6CC217",
INIT_38 => X"012453010164C606204594290164B4026C3A5749D235B80CB264888906688810",
INIT_39 => X"610546009C1ED3193704B200F61CDC8117E09EAB019E0DBBB2F0F44CCE5C2028",
INIT_3A => X"9EAB009E0DBBA5C825464E72453599178B72656A1764A6714A5218289222EA40",
INIT_3B => X"91222A00DE44153B0930D345FF1BA90CB3B800C99E33830FE0009E0D4D1C1041",
INIT_3C => X"4104B240030141000001B2A837570A61204C01602A1BD3480A787129EE1EE052",
INIT_3D => X"311AEB2AD970006B545E742A7A0C0147D12CE4068619D7102A0095662000D938",
INIT_3E => X"CA0A2048A20400075C003E4E34042C644A2D0015AD30850C2A00955E09182D00",
INIT_3F => X"8CA5C80547D12C2000781A15039C1ED31917242E52B80CB2DC9EA0BBA5C8254D",
INIT_40 => X"2CC1040047D12C2048034C4A6149380270F44CCE5C206ACB65DA28A70CB22500",
INIT_41 => X"A0A596B454050740527711B34D191041500026228897C10000B0BBB2E4587120",
INIT_42 => X"062046B868D413B3B8001D5B491FE049881041B800885B491FE0491D1041ED9E",
INIT_43 => X"8841A5D4E552D56C39480240D17027680311B3A5C84516B27886470178062F01",
INIT_44 => X"8897C10000A5C88553673AE602015C2A4D1A609C460B5C6A3B977C2204B34051",
INIT_45 => X"404914132C28681A0D017412B35D173B8897C1B80072743FE0486286414C1232",
INIT_46 => X"7F602FE0B80072743FE048628741405F8841A5C8253B20295767686A550A974A",
INIT_47 => X"008E93BBA5C82529D719555D2500D95027042C28932620468A13B20000B80087",
INIT_48 => X"B800F29E33830FE04A058641408387417B0012884100B8008E5D3C1FE0008D2E",
INIT_49 => X"4A4596D9010D4DDA44602A2D03D95007043700593120459A365804B35D9C8641",
INIT_4A => X"0353357904792A924AC04C0260D9507101B386AA2584B200865D3C2FE0641A86",
INIT_4B => X"52AC042664010440005835D8441503B386AA2584B200865D3C2FE04596184E0E",
INIT_4C => X"381A6A2B1730D355464575009052B10CB34045228897C1A5C8E52A5B5D74016A",
INIT_4D => X"D1040067535D5723202F8E632D0C016BF42A6C1AC90440258E17810F20006700",
INIT_4E => X"8E632400945D742D0128C9212A0981051822F4025325C935BC2CD1342328EC1A",
INIT_4F => X"E0B000000097E100F174432A0FE0CF1F821097C1D52223241095C1000001B2C8",
INIT_50 => X"D22837639353E904002BEE5E067103042A009C462B04B2F801A0012610244A2B",
INIT_51 => X"E0B001000097E10000F174392A0BE0002710244A2BE000015B492FE0BBBB4596",
INIT_52 => X"8695C1788988418501010141C00306020195C1000000000200B800079F33830F",
INIT_53 => X"44EA1811042019EA12B3C01C864146301041C01C1F8697C148641041C01D1E13",
INIT_54 => X"C1C92223241095C175004A8841A5C8054FD465485F194F0E60B864861E204C02",
INIT_55 => X"B24A30104113008CD7D1FB2A585DB24C641041058452384104B2773064821095",
INIT_56 => X"25174A2FE0A59653659932972E2740015C7404B3E5AADB5DB207008CD2A83763",
INIT_57 => X"04B3C1020241B001000097E10000F174392A0BE0002710244A2BE05701024102",
INIT_58 => X"C1CE9C8741461D864A4A128841DA1D864A46318841459638640334686A262641",
INIT_59 => X"08B2107F6E00109CDC811BE0108E2E009C5D3C1FE0A4001D874AA900132A8897",
INIT_5A => X"00A10540299719206365262E01B287AA04008C86AA4731128897C12080671882",
INIT_5B => X"3A1A630E28D8511330D361D83520693402017807240A4D2A395B01D80C211BF4",
INIT_5C => X"2E2A01D9500704235C2A67BA6200395935D954C0002D3B9C304152776121036C",
INIT_5D => X"830FE04A30641097C1BB4104104ABBB2E49A36D97127006C3ADB287104586526",
INIT_5E => X"001988418596D9500704375CE20FB3404A8841B000409F33830FE0B0002D9F33",
INIT_5F => X"045005579412B2407F7126C67FDA26CA7F8026CE7F6E26D27FA926D67FD1267C",
INIT_60 => X"D950070420295767686AD5042029B53A114361054600F51A0D036C3A2D2B9262",
INIT_61 => X"EE2A396B150F814D0E63AE290160696A14036105002BD9444B25201BF4048105",
INIT_62 => X"173B8897C1B0008E984A1FE0108E2E009C5D3C1FE0BBB2B0D3615723260C814D",
INIT_63 => X"7FA3402988414596D901195FFA046309E02A2D5F7A650330D365262ED311B35B",
INIT_64 => X"B2E4EE06405DB868D4032A3A8D03D95007044065262E2A254104B35D9C004100",
INIT_65 => X"2704B2A5C82529D9444B25492C610D2048220920635A02D9502704B3DB109C26",
INIT_66 => X"E000B8008D984A1FE0108D2E009C5D3C1FE001A40DBB45965865262E2A01D950",
INIT_67 => X"2048220920635A02D9502704B3DB108D2640173B8897C100B800068617BE2B19",
INIT_68 => X"D80626005865262ED301D9502704B24B00AD8741A5C82529D9446B3A492C610D",
INIT_69 => X"0128C961D3016C3A3E160144EA18510FB90CB2DC036C0ABBA5C8C537F952DC28",
INIT_6A => X"04B35D068741B8009C984A1FE0109C2E008D5D3C1FE000A40DBBA5C8251BF400",
INIT_6B => X"0598A0658E13B24596D9012A1B714D6E05E02A9C56804D3A028D69742A302042",
INIT_6C => X"C024A0407FA2264006014100000100A5D02563EA1D0178515D1A13A016B387AA",
INIT_6D => X"BB45969E6A07042A0051290B0464007E4E7A016C3A2D2B926240212E535304B2",
INIT_6E => X"740B45107426FFFF234FCD56032343239540798741402C8841000024AB00240D",
INIT_6F => X"0160011CE61A080306280A3B4204B24007740A66032341B800719F33830FE007",
INIT_70 => X"41000000000200B0BB00AD0023226FB007740C0074984A1FE0BBB2A4D360205C",
INIT_71 => X"036C52D2004945192B730D20006A53C70059290B20251564384104B26A000301",
INIT_72 => X"6DF418251C01289B1E0634681AF700192BD72833042C60AA21D35C8706404914",
INIT_73 => X"174A614E1C0170342A670D20009312B2400002A140024B92BBB2B4C828970440",
INIT_74 => X"B80016384A1FE049F186414D1F8841CD000101414596B3004B2C471FE0A580A0",
INIT_75 => X"598641C100A000EB483FE040318841B80017384A1FE049F186414D1E208897C1",
INIT_76 => X"46AE6280310A04260C214D9A5E0C042B0038466601192B3304B27C5957064000",
INIT_77 => X"B04B560E00575D3C1FE0BBA5C82529CC4826013E629A3A576123644E056C0038",
INIT_78 => X"6BD45D0A0F612A9502984DEE56D8046B0061050047D12C80312A04B271578641",
INIT_79 => X"AA2584B24B864ED9F17F86A7C1B0BB008C783FE04B570E45964931461A097811",
INIT_7A => X"40020141B800A29F33830FE040458841A5C8254D9A5E0C042B0038466601B386",
INIT_7B => X"0B864AF400578641F9002B2A8897C10000B001000097E100FFFF5479392A03E0",
INIT_7C => X"136091521904E02A2D3B6A424104B35D87A0A5C8652A951EA20480312A04B34F",
INIT_7D => X"0367003401296A141D01644753690BB35F018741A5C845612E5FAA760A04E052",
INIT_7E => X"0480312A04B246002A8841C71C874ACB1D874A4596D9016C3ACC482631A3658E",
INIT_7F => X"475853EE2A380E20575265D910410500636A3A586A11014109234CAA528053B3",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__13_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__13_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized14\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized14\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized14\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized14\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__28_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"864AB0BB008C783FE0B2C44655D500C865AA655801383B2029D849F4569222C0",
INIT_01 => X"663ACC5D1464B84CD801B387AAA5800130D3611A1C0378062F01647412B26802",
INIT_02 => X"CE6457212500B287AA0598804D0E6B2A00B92A68522804B24596B24885521944",
INIT_03 => X"180A39994EC0140105B24C0021418897C1B002864BBB4596D14C8E3997023E4E",
INIT_04 => X"1C0360D1285B5D52381929154FCE042368D4032D1B6A2A6706A021535F0828F1",
INIT_05 => X"B0BB008C783FE0A5C82529CC4826013E26E60C612A95026C3A3E1601304C0101",
INIT_06 => X"45691A0D28D9202E2A693AE02A2D1B9709B210866E457F8841402B2A7F8895C1",
INIT_07 => X"0627008D69B465D10C4131461A0928926279004961DA2071008C2920280130D3",
INIT_08 => X"B24E575406000001B0BB008C783FE04596D9016C3A5355F40620294929086918",
INIT_09 => X"4100B000575D3C1FE000562E00579300535D3C1FE008008C00AD000E5311A580",
INIT_0A => X"B85EAE21C05F661A2804B2F68000A0004C793FE0FF0021A02E01548641408E88",
INIT_0B => X"C15CAA52602A3953EC520B183300C65D460F23780A72652D14783137CC457804",
INIT_0C => X"8205E93A874D14033E2A9B46C00058397101FE2A5329970141056C00925E8B30",
INIT_0D => X"D0280760D901782A951A0124463524480364583FE0482E02460A002B0D5DAA12",
INIT_0E => X"4045471B0760D85C07447A39591BEA00065018608A267900D8102C30D3612B00",
INIT_0F => X"6104C9288D042A00956620006B51002B686AF40CA1659A4A00676E060057F426",
INIT_10 => X"0027D371C05F661A0804001B8405181B9701E106804DEE2A523A9101384D261A",
INIT_11 => X"8C4B7FE84858104101210DBB4596DE700660CA450B24D71D6C521804234C9C26",
INIT_12 => X"4A52182C6E043E2A2D3BF100B85EAE21C05F661A2804B3B000552E10BFE80500",
INIT_13 => X"64D3604645756A7A140105B3B2A8D265205FB461C04C62043E3A733A1964A671",
INIT_14 => X"C14C4D4E1095C10000B2F8D74C06010128C961D34D0128D8511330D325D35D0C",
INIT_15 => X"7FE7B100000097E1005479432A0FE04F00A0004C793FE00000B1C1584B1097C1",
INIT_16 => X"5218182A006C3AF53A0D010128681A193B09043700D7284D04B340000F230064",
INIT_17 => X"0141B001000097E100FFFF5479392A03E05102014100000100A5C8255DEE006C",
INIT_18 => X"452804B3401E1F208895C10000B80017384A1FE040F1864140201E8897C14001",
INIT_19 => X"B36105864165128841CA4588410000B2B0D31DD245680AA02A2A636614012CCB",
INIT_1A => X"87414596D1646601536D0A60D534575584050A3B7C6AC05F6A276209201B2D13",
INIT_1B => X"804E602A0A17C1047C000108002BF1483A03B286AA2584B24012818897C1405D",
INIT_1C => X"282E274104B34082884100A30DD8851041000001B800865D3C2FE0BBB2A8974A",
INIT_1D => X"4939F9082500AA523704B3D3A3A0408687415600828841B29C63054055F40201",
INIT_1E => X"653734D971002B922226002A3918047200B8523701AA523704B2A5C8253B2B00",
INIT_1F => X"812EC1520146C601A00181930E810B01A30DBB4596975271014105202B6A0153",
INIT_20 => X"864A5E008781216300838841B80016384A1FE0C9A3A04C818641501F8841B010",
INIT_21 => X"1ADC00B286AA20805503CA652B00B94A2A678609B2650000420007865147001E",
INIT_22 => X"D907271801602A324C5F1903B386AA2584B2B800866C802FE04596D235004F0A",
INIT_23 => X"A3A06B868841A596B386AAC0805503CA65272C02788D13B245965503D2354039",
INIT_24 => X"2C0124CA6557148108B3B2A4CA6553039C4E2500AA523704B30E810C00A30DD7",
INIT_25 => X"8A01B8523701AA523704B369810E60A3A0638510416731884145966C3A2D7BD3",
INIT_26 => X"CA652500AA523704B3C0A3A0405D8841A5C88553511DE052342E202C0178314F",
INIT_27 => X"0AB3B8008686BE2B1BE04A868741CEA3A05181864100B2B0D345CE5C202C0124",
INIT_28 => X"86416E128841CA208841C6221E1F8895C10000A5D0E50C2B004935C864D95C02",
INIT_29 => X"B24845162A391103014C9C264045476A5904B2B0001D384A1FE0494810416A05",
INIT_2A => X"2584B26A11014A00000100B80086AB7A2FE040128841B800485B491FE0BB4596",
INIT_2B => X"00015D3C2FE049ED0141BBB2A8933225180128C9451804400038466601B201AA",
INIT_2C => X"004751499808B34086E126407588410000B0BB00AD004536272FE0B048014EB8",
INIT_2D => X"53794104B3401D864140CE10415D8988410000000002B2E05755555520534D05",
INIT_2E => X"068895C1C00C0F088895C1C00100028895C1A5C865522E3B6952880437005765",
INIT_2F => X"063718DB050043C864D9000D691844D110B35D7E8841C6132A888895C1C00705",
INIT_30 => X"97C1C8591C828895C1CF2F17298895C1D62B23338895C1B2CCD4652E4D1411E1",
INIT_31 => X"39D945EE18D520240069525E1D2548C265C86803344863602A5B11B361866E88",
INIT_32 => X"F32A5969036494016A6345539E3021468A03D800B9314E12B35F878841459658",
INIT_33 => X"09884145969A7A40254E332B00B9312E02740249295304B3570E884145963E3B",
INIT_34 => X"048D09B3555D8841A5D4455D14612428610F27380270B4118016C928E90FB359",
INIT_35 => X"630A63B40274424104B351317F048895C145961929EF500067AE06002B181BD5",
INIT_36 => X"1860905211202304B261004F8841A5C825192A394104B34B038841459678520E",
INIT_37 => X"5606601929EF502600B217008C4596B2C80010A23EB6F91A6A6A26008A4DE666",
INIT_38 => X"648D391150B3044D008D69B465D110B2E614104ABBB2E4683A193B693AE01AAA",
INIT_39 => X"D200D41041E600628841B1BBBB45964965663A5247D1013E4A2E190220030423",
INIT_3A => X"3B090440527711B2009D0D4566D906004E0D00580D00890D00117F97E307A40C",
INIT_3B => X"29072023042C24D728AD04202B556A37036A5211182A00696A14030128681A19",
INIT_3C => X"521218603A84054939891E52612E015129EB042600B931EE1EC05F6A03584914",
INIT_3D => X"4D0E3B172C516157531E24D32D271801602A190B60584DB931EE1E200C214F4A",
INIT_3E => X"3B0904603A840538519403E106A02A2A0DA12A2A62804D340266066039001B80",
INIT_3F => X"280160696A1403C104205DEE309362C000D7280D78314FCE2C4E1C0128681A19",
INIT_40 => X"B2B2A4D728ED0A2E00F82ADE5C9509B3B8004E5B491FE0BBBB4596192B972E20",
INIT_41 => X"215A5E0260B8602113B3D9A0A000029B007C0DBBA5C8E50C8026602A5B254104",
INIT_42 => X"8841B2E0985E680540258E1B030AB34F2688414596B248451679291128D044A0",
INIT_43 => X"403A1C274104B3517D228897C10000A5C84541263EE206403A1C274104B34022",
INIT_44 => X"2D2E220022F40257290D03A60440250E372304B340268841B2C8465D1903E106",
INIT_45 => X"D7042330D3554645750090525104B36505864169128841CA4588410000A5C865",
INIT_46 => X"2D015C6619030AB35B26884145966A3BFB6A185C6A2B730927006700EA3BD128",
INIT_47 => X"86AA2584B2400D87414012818897C1B2A82C39F700740218173864260CA14AFA",
INIT_48 => X"410000B800865D3C2FE0BBA5C84562A621200002648D3958056C00B8523701B2",
INIT_49 => X"654865F45625002A1B2C04B3B00015384A1FE0492288410045967412B3404888",
INIT_4A => X"2F01280D19A0654A6524005841461282050A5D74012A1E0E3B7B3A7A00FE0049",
INIT_4B => X"1FE040228841A5C84531491F60242304B34D2B238897C100004596D9010D6934",
INIT_4C => X"D1285B5D2378861B0057AE21204FCE5440491413B3402A88410000B8001C384A",
INIT_4D => X"9C466705001B0C34484B66140105B35718884100A5C8254FCE54405D54026C3A",
INIT_4E => X"004596385C01608601D1500828D045004751499808B340758841A5C8C51BDC00",
INIT_4F => X"0502136F40008C01030D48010261029500020D00000000000000000000000006",
INIT_50 => X"0605877D2BE0D8FF8CC500A00001009FE000110451E7FF8CC502044A0400054F",
INIT_51 => X"C106A0C103A0B8FF8C0600013400037FE7C33F02034112008C00030D4803A003",
INIT_52 => X"1D008C450405250400014F0000000000000000000000000600B0A93F06A006A6",
INIT_53 => X"000200B0BBE0FF8C06ADE5FF8C02AA47010641EEFF8C03AA470006410605016F",
INIT_54 => X"ABB80000027400077F51CB01A002000234000011770000A77700020715000001",
INIT_55 => X"0343CC2EA04F720241F4000342030702510200014F0000000000000000040002",
INIT_56 => X"42040003750002014F548700610001014F5C1D874AE087A0002E0D02030D4502",
INIT_57 => X"C1C86EDA710295C1C002A0C20201A200000000020003AB04032D01040D450104",
INIT_58 => X"00000000000000000000000000000000000C00B1EEBF0202A102AB4480A90297",
INIT_59 => X"91531103B203AA2584B25D01034A017F4C0404014F0300014F00000000000000",
INIT_5A => X"7D3FE001080D00062D0001517D2FE0B001034CBBB2E44A2D4200783A86291778",
INIT_5B => X"5401074198008C030B0D48000742057F767D2FE009003F7D1FE041000743073F",
INIT_5C => X"01065504060D45030643540207413D008C0A001A6F0001065503060D45020643",
INIT_5D => X"064309008CFEFF064FCD4AFFFF068FC2060706756302074327008C0A00196F00",
INIT_5E => X"48060B41CF02A00B000A6F0001005500097FE70A00186F0002065402060D4501",
INIT_5F => X"00010B55070B0DC500A0001921271FE0CE05A051060B41090B0D05008C080B0D",
INIT_60 => X"0B4177008C45080B417E80010B4100057F00247D2AE000002E272FE00000046F",
INIT_61 => X"00070D45000742079657040B4162008C00070D48090B41C6030B4170008C4502",
INIT_62 => X"557632954300070D450007420702075558050B4149008C950A95555000329543",
INIT_63 => X"D50CA00C7F767D2FE010056E42070B4125008C017F4B48060B412F008C951495",
INIT_64 => X"0000000DB800090B074D7F2AE0BB4596B20CAAA580060620462E63270CE10EB2",
INIT_65 => X"0D076107950D00134F0000000000000000000000000000000000000000000000",
INIT_66 => X"02313A193B4104B274017F4A02864BEC3F8600610000014F0107136F0F008C45",
INIT_67 => X"236A2D6A3A25001019391B2400140F8153F100191B111C6306804DEE2A9B22EA",
INIT_68 => X"7D2FE00200014F05082D01050D45010542053F7D3FE0B0017F4CBBA5C8456D2E",
INIT_69 => X"30D341C864D910B2B800AD9F33830FE04A7F86616609A001090D00062D000151",
INIT_6A => X"2584B27C000642C604A00402767D2FE04596182B314F8E562500B302AAA58001",
INIT_6B => X"4B253E00B202AAA580B205EBD4217852686AB20B008CA5A44A5E666AB24C04A0",
INIT_6C => X"0D450205435401064197008C030B0DBBB2E0CA254035047465450A4BAE01692A",
INIT_6D => X"0A00196F0001055504050D45030543540206413D008C0A001A6F000105550305",
INIT_6E => X"02050D4501054309008CFEFF054FCD4AFFFF058FC2050605756302064327008C",
INIT_6F => X"008C080B0D48060B41CF03A00B000A6F0001005500097FE70A00186F00020554",
INIT_70 => X"2FE00000176F00010B55070B0D4500192300647FE7CD04A050060B41090B0D05",
INIT_71 => X"0606003549020B415A008C45080B416180010B4100878600247D2AE000002E27",
INIT_72 => X"008C00060D7700064206964E040B4141008C00060D48090B41C6030B414F008C",
INIT_73 => X"070B4115008C01864B48060B411F008C00060D650006420602065550050B4131",
INIT_74 => X"00000000000300B8000B0686787F2AE00004984A2FE010046E1D044B0E044C42",
INIT_75 => X"392A07E04F0000420003017500077F9BE30003017506008CF0D83FE84901A000",
INIT_76 => X"000001340000003500003F7D1FE0DD000043003F7D3FE001000097E1001EEA7F",
INIT_77 => X"750002A00207019BE3000000000000030002ABB100BF9F33830FE000077F9BE3",
INIT_78 => X"64D84442005835D928F700B201AA0584001B525018600664984AD110B202014C",
INIT_79 => X"350057342A7B2A80510B40C844075C2A636E3A580520693422C00CA165465D07",
INIT_7A => X"96495D4655D5602E450360D820D720200C0167CB4580510B04602A8D1B6104D2",
INIT_7B => X"0003009FE0001101514D02034103AB0002009FE00011015100015D3C2FE0BB45",
INIT_7C => X"00647FE74B03034303000275003F7D3FE0020701510000000000000303AB03AB",
INIT_7D => X"0243B1C100322300647FE74B03A0B1C1004B2300647FE74B000343B1C1005A23",
INIT_7E => X"0D4D00014301077F51000001B1C1000A2300647FE7B1C100192300647FE74B01",
INIT_7F => X"0A9554469695625800014201077F9BE30195490001420D008C01077F9BE30001",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__28_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__28\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__28_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized15\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized15\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized15\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized15\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"00B000000097E100EA7F432A0FE096952DB001000097E1001EEA7F392A07E095",
INIT_01 => X"8F008C45020361039500030D404EA00200134F00000000000000000000000006",
INIT_02 => X"51DAFF8C002E0DC82EA04B720541578007054A5C001005660500044F0403136F",
INIT_03 => X"056C802FE000030497E15000066300647FE7D806A00603044F6B000042000705",
INIT_04 => X"BF00A00005009FE000110551CF02054AA9FF8C0003049BE100190654B5FF8C00",
INIT_05 => X"054C017F4C002E0D457205410001009FE0001105514B02054A92FF8C01010D98",
INIT_06 => X"070151000000000200B80002F07C2FE0C001A06CFF8C00056C802FE002054C01",
INIT_07 => X"0000000000000006B00004009FE0001101510007019BE3000200354100024202",
INIT_08 => X"030DC800A00010E3802FE0AC00046E06020C6E11017C80432A0FE00000000000",
INIT_09 => X"0695C10605A405041072F3BFA8046227008C4504A00404107300040D34008C02",
INIT_0A => X"09B261020341C002036101030DD6BF00A00000E3802FE000000550E43F050401",
INIT_0B => X"0103413E008CBB45963E668D39F700FE2A1B7034322B005333EA440324977298",
INIT_0C => X"1B008CBBB2F034324069F100793A6601A605804D8E539115012497729809B261",
INIT_0D => X"E1B0030C6E5BE3BB45966C3A9C460C5C8A4D34027416012497729809B25803A0",
INIT_0E => X"B1F2BF0202A14107024A461E024AC002A0C20201A2000000000200B100000197",
INIT_0F => X"03A000032D007FE805008C017FE8C807720A0172930000000000000000000005",
INIT_10 => X"56008C00BE77691FE000030D0069693FE0CA03A0D61001615ABE0141017293C5",
INIT_11 => X"36008C00030D3C0007720A4100A0000347672FE0D610D926DA14014A5E100161",
INIT_12 => X"104A4F05014A004B7201DC8125E06403014A00030D07720BC807720A4C017226",
INIT_13 => X"007FE805008C017FE84804A000052D0001A6812FE008008C000196692FE04B05",
INIT_14 => X"BF09014AC201529206008C450101A1C901A0009E813FE06E03A0F104A000042D",
INIT_15 => X"AB000162812FE0CABE01413BFF8C002F0D07720B02720C01722EEA3F06014AEF",
INIT_16 => X"4573710297C1C20302A104AB4402A0C20272920000000000000000040005AB05",
INIT_17 => X"01617904A001026E07024C428000A0001E21271FE04C0000A0000C025154008C",
INIT_18 => X"015C2DC0004955955E6904CC1C42540130D331464AFA0EE12AE7503704B27510",
INIT_19 => X"007293000098FF8C03022D01040DBBB2E058454A476603696A7401AA01582AD9",
INIT_1A => X"0251C20302A1C002A0C20201A20000000000000300B072710E0E710B40007126",
INIT_1B => X"A0000A21271FE0CB7102413F8007024A448009024A490011024A4E0000A0000C",
INIT_1C => X"531378712A29695804B24010016100A30D4581024107024B03024B72024EF200",
INIT_1D => X"0000000000000006A1FF8C03022D45964935D84D6603B302AA0584E00C40212E",
INIT_1E => X"0043000C0551E509054AE907054AC20405A106AB4405A0C20501A20000000000",
INIT_1F => X"04052D01060D07054B4502026103054B02056E5200036300647FE7CA03A05D00",
INIT_20 => X"7F432A0FE00302017402077F5101003F7D1FE000000000000000000400C8FF8C",
INIT_21 => X"64482D575537384104B25602A00202003506008C00020D4800A00000004F00EA",
INIT_22 => X"008CB3A453531C648D391118B250010241A5C04104B252008CA5C8A565D1280D",
INIT_23 => X"1C44E62A5B61B25203024127008C6596696A94035853EE2A1818B2520202413B",
INIT_24 => X"3100B2F402A0A5CC052753531C609A3A5761B24F03024313008CA5CC05275353",
INIT_25 => X"01004F00EA7F432A0FE004001E3600010255A5805765CB00495D1A250244D171",
INIT_26 => X"1B2A011929B52BB25203A0A5B84204B2BB4596586D5402B200BFE60000047400",
INIT_27 => X"722037CC45405D54026A52C01F2029313A3009B25C01034173008C65D214032D",
INIT_28 => X"3B008C69EA94035853EE2A1818C01F2029313A3009B25802034155008C25CD9A",
INIT_29 => X"63B25D03034321008CA5A453531C609A3A5761404D1428DB6D5763B258030341",
INIT_2A => X"C04DA0BB4596B2A5C8052753531C44E62A5B614041262F01344C5353016C5237",
INIT_2B => X"96B345A18E67B207008CA5A86852B24A014D41A5804945D141602AEA404104B2",
INIT_2C => X"8E560015AD2C4505201A9966BE00B211BFE6A594012897229809B20100010045",
INIT_2D => X"B2BB4596586D5402B209008CA5C8456D5402B24C01124112BFE6378CE117384F",
INIT_2E => X"6A792A3B19045C2A634612B2545E01118FC1A5A80140D35C201C01606A3B4C06",
INIT_2F => X"634612B24C2C01118FC36B008CA5A4D77C8E13B24C4A01118FC37B008CA5DCEA",
INIT_30 => X"5CD44DFA11B2546411434B008CE5AA5767536DC910B24EC811435B008CA5DC2A",
INIT_31 => X"8CA5DCEA6A792A3B190428C86D7412B25432114335008CA5DCEA6A792A3B1904",
INIT_32 => X"B257CDD331EA10B209008CE5AA5767536DC910E06A2A1BD210B2541911431F00",
INIT_33 => X"57552029792AD164C00058412613E214B26D804EA000000000020011ABBB4596",
INIT_34 => X"2A1A1918A0211A3B016884129E3021192A1D0228D1351C242A460E2662055260",
INIT_35 => X"5B30213B2D00D1286905526057552029792AD164C0005841266763047830214F",
INIT_36 => X"504CA0BB01AD006A483FE0BBA5C8C55F97628405792AD164C0000D69F80A401A",
INIT_37 => X"4505A628C1140000A700B200F6FF31480FE0BBA5D4A5696D0410691124E610B2",
INIT_38 => X"4A007FA3A59CE5144005A628C1142A184505A60020292E4141040028C1142A18",
INIT_39 => X"01196E1A12442639C86918182E003E5E46454804B28E80024D42107F6E451B00",
INIT_3A => X"DE48C02B2D030A4D0E0F416D0601E10600232E530D79B8029C46D12002289C30",
INIT_3B => X"2029311A194F2E0920468E03783A462A97092C60575D3A4F6A27A60D405EA601",
INIT_3C => X"5767536DC9009C46512D24003870232446250430D36D2E122028C1049100E106",
INIT_3D => X"0003D40A107F6E4D95B8006A483FE0BBA5C8452A2D4B036486460C784602F82A",
INIT_3E => X"410520295B39515D202A6A1D61042D1BEA1E206326120128D0642700D810B2C2",
INIT_3F => X"75002B2AF86AD403693AEB04001B002B181B1530D3454A2D2130014F2A5DFA10",
INIT_40 => X"C04F2A19E104201BE02AEA01383BD755180400077C04312A8D2801602A1B0C04",
INIT_41 => X"5327205C01601929EF5021302129E76A193BC905002B782A98092C78374FEA04",
INIT_42 => X"5303536D6A04974614290124AA2146456704194D2E632E4D0E5C4655D5484231",
INIT_43 => X"008C00E85B491FE0D57A117F93E301580D01890D019D0D014E0DBBBBB2C4465D",
INIT_44 => X"290C270C21468A132C484516380090521118404126031817594523707412B259",
INIT_45 => X"3E2A594555520854FA04A03B0B28D96936055B304121D334A80DD3006A5F0A2B",
INIT_46 => X"3FE0007C0D03B70C004E5B491FE0BBBBA5C8854DAE65FE2A5B41210527286204",
INIT_47 => X"D00E457FD026C1A40E457FA42600000000000000000400B800A9843FE0007584",
INIT_48 => X"66000043000C0251C20302A1C102A003022D0400974FC2037FA2000C6E57E3AF",
INIT_49 => X"0101A1D3FF8C01026E4800322300647FE7D014014A5406014AC20152924601A0",
INIT_4A => X"E000000097E1003E5C432A0FE000BEFF8C00026E0000976F0004BFE7DEFF8CC2",
INIT_4B => X"97E100556F432A0FE000000097E1009F64432A0FE000000097E1006D5C432A0F",
INIT_4C => X"79432A0FE000000097E1007C80432A0FE000000097E1006A6F432A0FE0000000",
INIT_4D => X"C2A5A5E68413E00000B0149B0C00000097E100466F432A0FE000000097E10054",
INIT_4E => X"602E00B302AD2584B2662B238897C10000000002B800C4A565E68413E000B800",
INIT_4F => X"39388897C1B29C0350690520296A027402181738646007A628C961D3013E2ACB",
INIT_50 => X"B84C3411B24001876140128841459638643700B302AD45850067343A0105B254",
INIT_51 => X"C10000A5C8455D547AD300B301AAC0A40264B84C296A941382053E460E270264",
INIT_52 => X"484BC067595D156090529108B2403888414596670034254104B34B2B23398895",
INIT_53 => X"10290D04201B8D13B300865D3C2FE04033884100004596B386AAC0800A3A1134",
INIT_54 => X"25003800696AF41AC027F45053092378863F0260692AEE2E4041460243048016",
INIT_55 => X"255CC1342804B34F5D588897C1008596356A8C308153CD4F0678314DCA5DCB0C",
INIT_56 => X"006105E00C802620459A36F8040057A65DAA12B35B69548897C14596EA6A4861",
INIT_57 => X"18043734D971202B101B0718002B57230A5FC1342804B340388841B2E40A62E6",
INIT_58 => X"14016A5237006C3A3E12B800D9984A1FE04010D92640020141000001B2E4CB34",
INIT_59 => X"316A1003D164D85F08246A5F06013E467A39591BEA00A604000D2028015C6A5E",
INIT_5A => X"40527711A5C8C5472E6366025735D95C2700D9006C3A733A9725620536108205",
INIT_5B => X"C13408042A00692A2000D91045965941D81CC000492553555863255CC1340804",
INIT_5C => X"9312A5C8050725000D393C4D0603575555552053AD0CA5C8252B101B0718255C",
INIT_5D => X"0022261E3400A604E01A391A200093124596312A0764B401495DC014610D2000",
INIT_5E => X"AD282515B700792A324D464A14114596B138A5154031A62E014CAA522340941E",
INIT_5F => X"AA11B900A0170D196A0553036C3ADE6064009401B4714079A051E414A7282516",
INIT_60 => X"2D2B012849676E3246020170744240532D031953891CA517B95C343A06033446",
INIT_61 => X"EA2C23092047A66140532D0FC147EE2A7B044679E414B56089322054E3061878",
INIT_62 => X"BE652063060138510C78974D06042046A661E414B2606A5219039467602A8A67",
INIT_63 => X"4900311A0D03CA2BC03779043E2A5763E414B5449456F13A8D030108C027F400",
INIT_64 => X"460141050027530161055303536D8A1C851610391903F51A0D03A6056C005957",
INIT_65 => X"0D03C92809042A18210261055313A724D3005725D37040532D03391A0D032D5F",
INIT_66 => X"EA02391A0D039A361978515D1A13A74825632602D900792A380940532D03391A",
INIT_67 => X"D564232837570A612029792AD24C9702D31045966C3A736A08782D2B01645355",
INIT_68 => X"F13818537504EA665521B80C459638146104793AB402F51A0D036605804DEE2A",
INIT_69 => X"08078105D32D8B22205CA104232C5161D901B97A4C11204FCA21D328011C0378",
INIT_6A => X"2B00F82AD564260C212AD24C0A24EA5291222D0049655349665EB404405DB92A",
INIT_6B => X"184C9C5E07242A1B6C525169A3044045C76420009312B2E4D3511554D7341818",
INIT_6C => X"2E1A0D01576DD161C01401054596F82AB52A1564B4290130D345514978041019",
INIT_6D => X"0460CA45405DB46120009312B2E06104496DE63253013E2AD920EE66D30D4121",
INIT_6E => X"393BB80440453953A70CB2E45325EE66201A197B1701935300636552C9299856",
INIT_6F => X"EE6A070453004961FA066B5108249132BC242E523804B2A8F118190452006C3A",
INIT_70 => X"0524934AC625006B545E742A7A14010545963814610B8E005861D25C4405201A",
INIT_71 => X"EE6ACC2D4025E6012A3BD869B62B7A140105B2E0017C256B087831236A5DAA7A",
INIT_72 => X"0A29290445966A39136A82173E636602A6044045C764C0009312A5C80507404D",
INIT_73 => X"9102D31045963814014C5765D34400632A2A58031817575D3A4F6A2706240A1B",
INIT_74 => X"FE2A391BA70C459638146104783A14350130D331511F2330E6005735D9281124",
INIT_75 => X"0105A5C845610601BE55F4662048A204605E2A4F2602181BF700495D8A539517",
INIT_76 => X"2A7EA10CB2E0017C25295771B472C55F2A67E678054C5765D3440063E61EC014",
INIT_77 => X"84129F00946404284412942024128A7024174596696AF4322048A204202B7119",
INIT_78 => X"235C8A4D260D415D3A4F6A27460540498601A60400129750E413A71C8516905C",
INIT_79 => X"984A202801289262405D34565D01313AFC047900D3112C30D34D53238053D104",
INIT_7A => X"140174122C60D164974AC01F602A0A03576D0A789766EE5E2A036C3ADF480664",
INIT_7B => X"9052A721D948C0140105A59C2517B4289332A3658E27022451530D035765BA4A",
INIT_7C => X"01646515B72404118B00512F2E6B461D240FD86D2417007B064B03010A538D03",
INIT_7D => X"0A1AD20966009A50C413A71CE5176C3AD05D1957430E082898468878E514B2E0",
INIT_7E => X"8A54C4109528012451390B30D3650E750A0437009E28641294480430C4118700",
INIT_7F => X"29699228410AF82A691A84055712A71C85168C4CC411912C64119A340413E012",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(16),
I3 => addra(15),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized16\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized16\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized16\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized16\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"866F0228F86A143D024094665B00EA524B1D2417A017D81B9805181B920C4145",
INIT_01 => X"201B2029F31A2A6E0264A6712D009C4E8405574529393C67E3003E7234020660",
INIT_02 => X"06617A1DD4092600791AF952553AC047D12817444A2D5B000D2999008A688411",
INIT_03 => X"E10920190D40D3448730E126E414A7644516192B07042D000A6B6B52C8044065",
INIT_04 => X"7401905211245153680B20460650CC00D81B09649736184C2A13B900BD78062F",
INIT_05 => X"5B009C4E840597668826C000D800873E204D8A17C9280918001B7C05205D865F",
INIT_06 => X"3839125EF41380390778311AEA020A1AD204405D3A6B0B30D3614E52B7020606",
INIT_07 => X"17202E63264F66010A2B2D030A3B925E3505A0212A1340119A30E414A7644516",
INIT_08 => X"6406402997298904605E461D014CAA71206B8730414DD45F6A2B2B0038471A2B",
INIT_09 => X"4D0CE10EE594B25C2A37CC5D270920468E03EA6A592F240CA1212A1340119A30",
INIT_0A => X"035C6601410A530C211A691A1B18492CE10453000A4DA621404D1444D165B804",
INIT_0B => X"D365D319B50CA5C8C567DA2807242A2A311AD754532B0130D365D31915182538",
INIT_0C => X"410500275301946720009312B2E0A104006B6E2A0C242A232A326A0206780730",
INIT_0D => X"2A2A0128D155C014610D2000931245965845691A0830D34D571F2E00D764D100",
INIT_0E => X"D16C3F00260E31003800C865D84455054045AE024925912EC0140105B2E06A1B",
INIT_0F => X"D910A5C8E51A07487A3AD9449506C014610D20009312A5C825290D19391B406D",
INIT_10 => X"AE04E02ADE5C3504459629524C052053151825009C1ED31917042A00692A2000",
INIT_11 => X"2C78265119240A6BC047EA1A7704B93A1761204FCA21D368E3062029C75D084F",
INIT_12 => X"9217792AF81823601929783A3F00194FCE300620AE562E3AAD0226092B188208",
INIT_13 => X"3823EA1DF4072A006C3AB552371901541A30D341C85520186104182B3329693A",
INIT_14 => X"2028C10411042B00F82A181B152B370378320E4F14010A5F6A03D14C6E058105",
INIT_15 => X"06042A0078292E2A0704E00C002BD9202E4D0E28682AC96D0A44D1102C244625",
INIT_16 => X"0007C053FA00495DC0140105B2A85723F850405D8A03F82AF0529F00792A0E4D",
INIT_17 => X"1401E106804DCE472500AA525705203A1451A10C4596BF30D34DD770C004C317",
INIT_18 => X"974D2A0445966A3913023E63FA02A60452642A2A10030128C961EA10B2DC6A5E",
INIT_19 => X"202F2A023E4666522E4F2A4F0E28C8545806B92C0128D944781A3703984D6E1B",
INIT_1A => X"9463A0616E474A0F0033D33440610601BE55F46620006A53C710B9C8054E261E",
INIT_1B => X"D368A30440610601BE55F4662000D311A5C8C5674E5B2E4F0664465D4C05205D",
INIT_1C => X"0B180073B461A01A3204A5C8A51A1218492CC1063100792AB221D754204FCA21",
INIT_1D => X"79520830D35D464508645831D74421300133D35D46450828EA36B9052063EA52",
INIT_1E => X"84056C3AD72811510104406D46450037D9544029B76584050A6BB4010660D319",
INIT_1F => X"0450996405240A5E46166104192BBC659A623C0C0137D9544061AA652A006A52",
INIT_20 => X"84128750E4128B24C0148016B45085160024C0144596B970F45EE610404D3463",
INIT_21 => X"B4508516B400C0139318A4129250041120138650E41000118E30C41092009F7C",
INIT_22 => X"A77445617A0A004FD465485F194F8E1CE514B45C343A06132350312A8D1CE514",
INIT_23 => X"B264A521531B91640578060FE12AD9702A003E5107184000593180660400E014",
INIT_24 => X"2E23EA3A0904E0522017691A91640578060F415DB4612B00593180660400E014",
INIT_25 => X"A5173E4FE65E8613A71C4516D9500704E02A5B2BD3482B00791AFC04315C410A",
INIT_26 => X"660A0067482D2A01311A2063D319CC004929791AD768AC04201BF4480100A71C",
INIT_27 => X"97020A1B0D5DBA2A0128D9243300384D1429D845D149C015AF280124D45DAA02",
INIT_28 => X"9C1CE514B264F83A0B604A52085C6A2B0D398D0F21295803195F6E01D1655303",
INIT_29 => X"0400E014B2202E63265637345905402546160164861E3200001CA5176C3AF31A",
INIT_2A => X"6D04D168C96D2E4D4E0BBC609A3AC8555863C0140105E594B440484704249432",
INIT_2B => X"2500AA112C44D170404D1464783A8619804D6E1A2A0E81198706C0006C3A2952",
INIT_2C => X"D1645825AA02410A804D2E670E13B2D0392BD165187831192A01A6052029F21A",
INIT_2D => X"47254E3340491413A5C8C55F743B2A002A1972040D5D34036C3AD2440B182500",
INIT_2E => X"523801646515B700D2240444F4669322042494468B6405242A662E4F0A609052",
INIT_2F => X"E516401A8900915E7952880089527111091825174596102B490A2E570A291704",
INIT_30 => X"2A00AB40E515E01ACA5F01242A23FA66785208608603AB5C2511882CE414A72C",
INIT_31 => X"977C0278B9314E020160584DD7342B00EA3A552A640D57255313201BEA320404",
INIT_32 => X"D149E015AB280164D35C0C18C01F2029F952B56A18608603F0525C062C5C6A3B",
INIT_33 => X"042497460464D35C3E03D1203402792A99566E4A940433003839125EF44BC245",
INIT_34 => X"485F19036A3B182BB74A4E062C28DB6158215D112000C9282D1B71117970D225",
INIT_35 => X"142901644A2D003947230015A8206516A83C65152A004961B44A141501285767",
INIT_36 => X"AB442515260CE12A792A0804201B2046260359290B38A515AA1461042A2B174D",
INIT_37 => X"D2242000693A4D1D2029D92817010A1A31042C54340301640628C971202B6A01",
INIT_38 => X"0118EA1A7A0C212B6A01C81D1A49C245D11DE015B224450540493A521B187100",
INIT_39 => X"2D03AE2C4505404D2E02EA520D03C60423644A2D2E68164BC245D1494015A928",
INIT_3A => X"974A2028012892626C00793AB4029C4E20468E038A13A71C45165929CB045853",
INIT_3B => X"482793224071001B6015B72404118B280160EA6AD9280B30D365585D2A4F0E28",
INIT_3C => X"A90000000000E014BD60CA652E3AC82C2028015C9A662029C9690C18521C0164",
INIT_3D => X"994E20468E0B8105FE1C3412401A8900E1060007E06A34130164D7645804E017",
INIT_3E => X"2E4DE61E2344915E590BBC78191BB30CB2C84516B21C03648D39970452000A39",
INIT_3F => X"3E12A5C8050D2028810D6F00311A004388466704AA1BC02794460718804DAE61",
INIT_40 => X"0130D331511F2340535F1924916AA3042069120437004939571F6045A6016C3A",
INIT_41 => X"2029F952181B2D006C3A2C6A67043800706A370329527A140105B2E05171EA35",
INIT_42 => X"2D53342B21093A030628D0450043944631001929EF507A1401054596382A5C3D",
INIT_43 => X"1411004E9A110039CC48047C9F1EF42E0478C114BC708517A5C805074065D854",
INIT_44 => X"010505CE9A114061B45EBA12BC44D1100024C014A7708517BC70C114C04FA64A",
INIT_45 => X"405D8A03984D6E1B974D2A04B2E00160311A1C045200984D6E1B974D0A24913A",
INIT_46 => X"60727442536B0378C70D406D060141050022F4026C3ADB45205C01240A3B683A",
INIT_47 => X"01604B39511D200C415E7401C845F4481E5F610419395525C02B2D132C24D334",
INIT_48 => X"2034014C6A53FC2A793AC047512F313A10132C605741977E04645339681A2028",
INIT_49 => X"2E2A175CF4191204804D2E1B37633A460E60B95E0A75CA05002FCA45EA02D81C",
INIT_4A => X"1441610546008A19E02AD944C00C010F2C28D265E00C2A00382B5365006BD431",
INIT_4B => X"0A78316A2B460E62001B2063FA1901609A4AAA55D8440748AA65202957250E4F",
INIT_4C => X"CA553F00A6046E00660520290D19391BC0470A533412A5C8452A2D0349610E75",
INIT_4D => X"D16DEE5620384104A71C851678522E1B5167E6329322E414B2DCAA1A55054021",
INIT_4E => X"552A640D57255313201BEA322404A0178E00905C84129F28015C6A7214248A29",
INIT_4F => X"6A3B53036C3AD319793A467265450A1B01246A3A264F147165450A036604EA3A",
INIT_50 => X"D148974E2D000A4D265D1421E6062029D319793A461A01240A6B603984050A5F",
INIT_51 => X"D17100129750E41323600A5F6A3B537F610A002BC865C85C1530D365E62A9502",
INIT_52 => X"65522E1B57551428EA2EBC28F168F4662A00B865934AC04F46022A399B5E1544",
INIT_53 => X"4596192B1360B824D71D3F00A604A021D35C0704521C0128C961EA10E594A748",
INIT_54 => X"9A3A485DB5052029196B174D0A304C5101182500192B1360B824D71D2000D311",
INIT_55 => X"1403182B3145AE21C000FE004931536D0661C047792AD754D50C01478A2B0F60",
INIT_56 => X"F352260CC11B713A204594016A3AAB052029576D141501304C058105E93A874D",
INIT_57 => X"2E4E9A30215E4655BC2C94175735994A26002E6ADF442554265E01242A4F4A1A",
INIT_58 => X"0228D9202E2A09182D005D1801248A4DAE150128933E620498310A64984A4041",
INIT_59 => X"8D2B9262C014010545962A3ACC5C0B785149EA665D5901304C058105151B1169",
INIT_5A => X"C05F661A084097721051110153259132C0140105B2E001304C01494D4E5F201B",
INIT_5B => X"2C40461DE02A3B3A1818260058790A78475F711082058C29205C01242A66584D",
INIT_5C => X"27006C3A1C644B4500670E70342A0770344D8E03D164D85F0818A0319A5E2D13",
INIT_5D => X"204D9A72302CC106443041250E4F0E78574DAE2146022A1BC85D793A4029D809",
INIT_5E => X"205C01242A66584DC05F661A084097721051110153259132C0140105B2CC9C26",
INIT_5F => X"540681050A4DCA5DAA760A24E6000624A6013E665321EA426105461082058C29",
INIT_60 => X"0E03383B260CC167552A2E0058790A28D045BC448A2B0F60D94D02606C3A796A",
INIT_61 => X"D164D85F08240A22E622C0008D69F43699302129B14AFA222500D028075C6A47",
INIT_62 => X"2A00783A462A17044029D80927006C3A1C644B4500670E70342A0770344D8E03",
INIT_63 => X"D37120471A2B1764A671E01A2A22571481082C78574DAE2146022A1BC85D793A",
INIT_64 => X"2524230445966C6AB76246006C3AB762D3191204001B2328DB344B640330D325",
INIT_65 => X"37006C3A691A193B4104A5C80527D7500704406D542A3705271801242A5D861E",
INIT_66 => X"0128C82C5500014C8E30414D34632A009C5ED71C406D0E6346024605204FF42E",
INIT_67 => X"19042A00F01A090440004A613E0881055355B40431240328936618284C37C014",
INIT_68 => X"B304283041619A364065AE71C0280128C96156000130D3216639410445964752",
INIT_69 => X"C05802048066840555034925D750C7050073344D8E030144D118610438240350",
INIT_6A => X"A5C82529E91AF400311A2E009853693A3C04B2E04A5D19043500384D8E73A207",
INIT_6B => X"38240350B304283041619A364065AE71C0280128C96145000130D32166394104",
INIT_6C => X"37376104192B972EC014410645964925D750C7050073344D8E030144D1186104",
INIT_6D => X"CC455363492CC1064D0C2163460101509930014FD465485D2E01311A37005829",
INIT_6E => X"6A2E4204B2B0D31DD245680A4045C7644E6300074029370374160105A5C82537",
INIT_6F => X"7944C047D225C01441064596192B1C5CAA65572F80322B002A2B0D1912182029",
INIT_70 => X"0E604A52481D2063EA522B04B2A45353D700311A002BEA6634346104192B972E",
INIT_71 => X"6A2B77045953004FAE652063EA522B0445962D5F740261054045C75C594DAA4A",
INIT_72 => X"A64ACE05004FCE6453533204A5C8054FCE6453531228F118181B553A804D2E1A",
INIT_73 => X"5402E91A3C634601384F6A2BB7022D73F43257255303701A370445962A1E0663",
INIT_74 => X"4106A5C8C51B9C040022341E002BEA66202918539917F25219134596792A526D",
INIT_75 => X"F9521360C9288D0B21302163EA522B0F1178513A091835006C3A693A9C0BC014",
INIT_76 => X"E61E8053112892622D004A5D9906C047D7441A39F91A152893122C60A108BC34",
INIT_77 => X"0D78D300473A11794104B2B4D954202801282C292000D900384D2663002B0D4D",
INIT_78 => X"EA520B240A5E4602312A1C1837006C3AD728117D011837384104A5C8E52A8D39",
INIT_79 => X"DA448800264F0613C0479312B2E45871265402042B00384D2A770A1C830B2063",
INIT_7A => X"79740A78715221300139391B20144106B2E05E4DD235084C9C26001FD2450860",
INIT_7B => X"C05F5904A5C8256B0D034945CE4C25242304B2CC9C263C00DE70D7191903A604",
INIT_7C => X"C81C40252E62271861042A1E0E63B44AAE0479286204551A1704204D0A616605",
INIT_7D => X"6C3A2939E7520B182614C204550061056F340120E307C0144106459693530940",
INIT_7E => X"AA7A0560AA21D95C08035529C904004FCE643851341E8405192B9C074045B401",
INIT_7F => X"2700384D6A612204459638468603015C4602BF28DD6803780728C9480057A65D",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(16),
I3 => addra(15),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized17\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized17\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized17\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized17\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__12_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0D014605403149550204523841044596EA6A192B0C30D321662A12182D006B51",
INIT_01 => X"260CA165974E002B9459A3076530612A0A27C207312801483467F4006104121B",
INIT_02 => X"190338192A060348D8342804B2E4D828202C01604A4F2E4F1449C20527700204",
INIT_03 => X"C15F2A468601F91A7A144106459678528E291744665E6A4D0E042B00B931CE5C",
INIT_04 => X"2D00381A691A1B78074C2A521903532907060033D365D31915042A0019539230",
INIT_05 => X"D40A20005735D929350079291160D124D36C21304165D864201A933AB92AA82B",
INIT_06 => X"3C042C502E6919031817193BF91A7A00532907062B5841064596383B5D51025C",
INIT_07 => X"6A2D2E01B13845050067D319B50520295765D944153B0160975271190160311A",
INIT_08 => X"6C1AAD044069D16C2A6462048D69742AC0478A4DE6669830015F34520864535D",
INIT_09 => X"9B228062D178250D602A956AA304000D2028012453150204201B840538006C3A",
INIT_0A => X"C04C01541A60C92811786A4AAE213D180140D7246530E117793AA6360124EA2A",
INIT_0B => X"0E541A648A2D0128F1184900B9314E1E01344C532D47066CC1140A19B12AD72D",
INIT_0C => X"205FA6164106B2CC9C260022E600593120459A2227003E2AD045531B220F2364",
INIT_0D => X"A5C845412E1A2046660458310663A6022A66D945C067D8715905407D46024605",
INIT_0E => X"46024605205FA61641064596EA1B12043700692A20192A016605404914414104",
INIT_0F => X"59450A62653041412E1A2046660458310663A6022A66D945C067D8715905407D",
INIT_10 => X"380058397104575D3A4F6A2706605845106911182A00783A462A1704610C6152",
INIT_11 => X"114094467E0422044596105117242E52B8046E542204A5C8A50B252823044596",
INIT_12 => X"806684058A19181B15309346C01441064596191BF504202B11441117AA010A3A",
INIT_13 => X"9426602A89521C24916AA3044D540204605284050A4DE66653016A5225500204",
INIT_14 => X"23208306C0144106B2FC2529DF614110C317795C0130D34DAA523400A605235C",
INIT_15 => X"2029E91A083B4905E02A476AB30C2C28D94DE632203991622538A30A4061B471",
INIT_16 => X"7101410A6400495D2A6706612E0CA1219A662400D9002A1E525F28062360CC1C",
INIT_17 => X"290445969353372D4204B2A8D820D7191903064C9C2679744A0F252081059752",
INIT_18 => X"8A010628C961EA70021852006C3A691A193B41044596DE7024001822341E401A",
INIT_19 => X"342E310C411AEA66180400733446747122042C48465D19036C3A9C460B78314F",
INIT_1A => X"610A3F180364B462C04C01608A5D4A2A401AEA663804B2E4D8282B5062060073",
INIT_1B => X"B86A2130411AEA661830D371342EC047792A0C0452384104A5C8E52A792A2B1C",
INIT_1C => X"9A5E401AEA6678723401C1042328D9306E1B73053D18A30440659A5E401AEA66",
INIT_1D => X"461D3D00A60428300147D170804D2E638E672B004A274045C7616E4FAE044065",
INIT_1E => X"0878D365C0144106A5C88553F71AD30C2500514DD3342804B2CCD4047105A021",
INIT_1F => X"C01441064596935389075100C6042334F952D30454005821D35C792A2D006A1B",
INIT_20 => X"EE5C740D015E2601C6042334F952D30454005821D35C792A2D006A1B0878D365",
INIT_21 => X"3870E052C95D9722A04A261901249122C0144106A5C865723471210A804D2E25",
INIT_22 => X"1524D7702D6B14030608004F5767C01B5C310663A6528217191B0A309346C000",
INIT_23 => X"BC34F95213309346C0003870E052C95D97223D1801309346C014410645962D1B",
INIT_24 => X"4106A5C8E52A2D5F7A01536D0A609C5ED74CC0474B39F700DE708A19181BB508",
INIT_25 => X"5500410A0067AE2BC047933AA109E00C461082058A19181B1530D325D371C014",
INIT_26 => X"01052C5C2A1B1C5C2A4D1A309346232003645339681A7A144106B2B4F952D304",
INIT_27 => X"0663A6528217191BAA07C0144106A5C8A56A3C440218261402042B64A32B7A14",
INIT_28 => X"68004105204DCA0A2000D90093538907C01BFC3A26633D00A6042830C11B5C31",
INIT_29 => X"014FD465485D2E01311A373CA305000D404D3463E01A5123D721C01441064596",
INIT_2A => X"FE0049418846074C4A1DC0472A1B5367972E53430148AA652A00D15C6A2B9830",
INIT_2B => X"F45E661A6104191BCA04540061050067AE2B71006A1B4806B2E0D371456D0601",
INIT_2C => X"266AC865D75425002D5F460581052D6B14030124D77034031019170166050073",
INIT_2D => X"CC35C0144106B2E01929783A2063544EA20766148108A5C80507A04A26013E5E",
INIT_2E => X"A80CA5C825634635F95213042B00185E744561048A19181BB508BC34F9521334",
INIT_2F => X"2E088105D901985331528B0B2018A10A2D5F742E810A2D6B1403786A1748D834",
INIT_30 => X"181B15184000782A9502101917010660810F4162A62120280128C9614500410A",
INIT_31 => X"0A5D74012A1E0E3B7B3A40491413A5D4254D4E1241056C1C0128D71045968A19",
INIT_32 => X"0404202957655341410445962A1B0C0435006C3A181B75062700384F6A2BB702",
INIT_33 => X"4E00386A1403195351050027D3609A36993021192A11804D6E3B910041052644",
INIT_34 => X"0A2226632E00574D97222000D3112C30D34D864A26006C3A55291C24D7282D09",
INIT_35 => X"182B1160575D3A4F6A2706609A3A5B5D5505004FEA534905004FCE48EA020124",
INIT_36 => X"A5C8A565974E202C0160D975CA0E653061450A5F9A7A7A341928D94C3A5F7401",
INIT_37 => X"41064596191BCA045434F95293076F340128DB20805311182029576553414104",
INIT_38 => X"692A081B7A1401052C1C92667A38B97A4C117A000A3A116090523106000DC014",
INIT_39 => X"1230D35D3A23E62E6C34D9716072340194794104A5C825638A03610551006C3A",
INIT_3A => X"34004605204DCA0A20144106B2A8955E20000D19EA7A41044596584DF4007E1A",
INIT_3B => X"1518610C61522E57EE22783A204FCA21D368A3046E540204605284052A565265",
INIT_3C => X"E65620009C46EA102C28CC686C1A114C2A67945D7471854D3402E606E02ADE5C",
INIT_3D => X"210F5D0581052A3BD35C0C242E52B8046E5022042C4C9C263C44021825005779",
INIT_3E => X"201441064596F81A313A1528F15C46028A69AD06250068004105204DCA0A202C",
INIT_3F => X"23092B580164A671251C4105204FF42E603A84052A56526534004605204DAA08",
INIT_40 => X"2A46015C94460B0437002A52ED07C014015C6A5E14016A52603A8405D764D168",
INIT_41 => X"4D044596D9015503101907648A5D02245153280C223001636A42D72440003819",
INIT_42 => X"4306B2E021039353E9066B510804804D2E678A29015CCA1BB7020664B84C6A1B",
INIT_43 => X"D22420006C3A575319605553974D02200330D365CE702000532907062B580120",
INIT_44 => X"663BB712B9004941D7485518C10A202C01600160DE709752094CAA522E208105",
INIT_45 => X"201B8D174106A5C8451A09042A0095662048A3083C7002182534C20423644565",
INIT_46 => X"8900915E7952880089527111530068000A4D662A793A4602014C4A1D302CC106",
INIT_47 => X"0A2917240A22064FE6025329270E000D4F0CC147792AD754D5102C2CE516401A",
INIT_48 => X"605284056A52AC04204F4A564E5B0A28F1183A1A1B042A001953720A2378314F",
INIT_49 => X"4A470724EA529122004F3467FA2801549A5E0C18251C4105204FF42E37380304",
INIT_4A => X"9A62265002042B00D81BFC52343901052C24EA1A61049353F70C8153312A7E04",
INIT_4B => X"6115B700D2240444F4669322042494468B280128D81C2000D9384104A5C8A565",
INIT_4C => X"FE006C3A9C46AB045F7023042C34F95213042B18E104406DF418004B9446310C",
INIT_4D => X"F2526B05402A0A4701606B3911114065AE7104042E700304804D341A84053800",
INIT_4E => X"0160EA520D0301309346A6082B586206804DAE21595D190338468603791A8E01",
INIT_4F => X"977C020452384104B2C8465D194F9C26C01B1C60D901384D8E670360860F2028",
INIT_50 => X"38003E66CA6916609C468B0F2130411A89004105C0676E3AC86D205C015C6A3B",
INIT_51 => X"3A01D22837635503947941044596EA520D53020452006C3A691A111825208105",
INIT_52 => X"2400792A5B5D15606B3911114065AE712404B2E0792AF76A0830935E192F0128",
INIT_53 => X"780570640330D34146023800574D9722C000785E3A732304B2E00130D325D344",
INIT_54 => X"34180140D31C5500410A40523402782D2E220428D9359C048105D22404044029",
INIT_55 => X"D344402D0603741601054596192B1C0452006C3A691A1164536DEA560043885E",
INIT_56 => X"885E204C0178861BE02A2A6327004A3AF9062063FA114596380099561830D325",
INIT_57 => X"A021461D3D00A6042830C12B311A1B1840003800384D0A612A712304A5C80543",
INIT_58 => X"CE2CC0000A4D26632E01014C8E30012FCB4508048053511D405DB4615400410A",
INIT_59 => X"A021461D2A00D55D19770118523841044596E91AAA25C209804D2E1E525F204F",
INIT_5A => X"3D00A6042830012FCB4588002A3B8D1320280128D81C20006C52D100786A3706",
INIT_5B => X"2000820A3C5803648D3919182600782D2E220404804D341A45006C3AC9288D0B",
INIT_5C => X"171852384104A5C88553F71AD30C25702204A5C8052B3B2A582A2D03782D2E22",
INIT_5D => X"2A72A2076530012FCB4588000128C961EA000D19EA280154EE66B80723781051",
INIT_5E => X"C1040007E02A191B0B30D34D535F25702304B2A897361804804D341A56003819",
INIT_5F => X"B80A200093122C5C2A1B1C30D335585F2A00672462053600C928CD00696A1403",
INIT_60 => X"49001447C609A021461D2A00465DE6076530A121461DC027D360C01401289736",
INIT_61 => X"015CAA654E19213A4204B2A89736980A204802606B3911010170342A074C4A61",
INIT_62 => X"1A78F11A6A162107804DAE61FA2A012453533804A5C825638A03015CB40A202C",
INIT_63 => X"B298EA1A804D2E4D265201182500EA520D5702046052840538002A1EE61AEA4C",
INIT_64 => X"EA66201B8D2B92624600386421042C5C6A3B17042A00EA520D57020452384104",
INIT_65 => X"11224E5B204DAA08200C0107452CC10A3300382ADB5C990B6530016BF42A0D19",
INIT_66 => X"3E4D0653011852384104B2DC6A5E1401F51A0D0306245353D7006C3AF36A1978",
INIT_67 => X"11224E5B804D8E5371152106235C6A3B17042A00EA520D57020452000D19EA00",
INIT_68 => X"F91AB5047600C6042360A108202C810F20002A39581D004FFA72A20C2C780778",
INIT_69 => X"D12DBC24D360C0144106B2E4D8282D5F74026105266037004939571FC047D138",
INIT_6A => X"DE70804D3402060AB2E458712D6B140361052564A32B4061B471406D06014945",
INIT_6B => X"9A36195C6A2BF304202B670BBE009C1ED31917182A00956652384104B2C84516",
INIT_6C => X"5C391B6453216E39931912182D0CE1179C1ED31917185200301A7C092700B931",
INIT_6D => X"4104A5C80507547025634601382ADB5C1970F44CCE5C21300147D12C04042A00",
INIT_6E => X"977C02042A48C265464F2E4F1401410AA021461DC043885E2344D14818185238",
INIT_6F => X"0A4D0A2BB70261054069A90725000D19EA048105384666112000191B155C6A3B",
INIT_70 => X"CC45536326003800782A954AC24F067123042C606B3911114065AE7104042A00",
INIT_71 => X"38466601410E002B185317019C1ED319B70C2C289B1E66063700584DAE612037",
INIT_72 => X"EA384104A5C825638A37595318042B005869D36593225C740118265402042B00",
INIT_73 => X"2C600128F118473A112502784646410A7E1A880F20280160311A1C04A065464D",
INIT_74 => X"0073342E0047D12CE4068619D7102A006B51535F20280164D754E02A182B3104",
INIT_75 => X"A61103282C29111852384104B2B4D9543D00A6045600015099308153511DC01F",
INIT_76 => X"C14820006700384C01280A3B42042C4CD44F067103042A380304A06AC01B7C45",
INIT_77 => X"7014210F31580318804D341A0067D8711960311A8B5CC130E61A64068053715D",
INIT_78 => X"01289B1E863041523953470A7E1A0804251C0170342A8730E12A792A2B1C610A",
INIT_79 => X"04042A0095662000D9384104B2A8F118473A11592106232CCB450828974A251C",
INIT_7A => X"516DD748C014A1090007405277112C44D1705400383B5248C24F0611201BEA32",
INIT_7B => X"D22837635503576DEE125F0041050067D7542648C24F06014105802B6E035853",
INIT_7C => X"0F606B3911114065AE7104042A00384686036104937AD3202000185317198405",
INIT_7D => X"2B00783A264F9A4A04244635D9448B0041050067D754D25CC0678D3912043750",
INIT_7E => X"2334F95213042B00D2283763554BC24F061120006C3A9C46912E8405191B0A04",
INIT_7F => X"81059C1ED319B70540652A569222234C4A614900DE480047D12CE4068619D710",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__12_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__12\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(16),
I3 => addra(15),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__12_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized18\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized18\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized18\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized18\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__27_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2C4C576D0601F01A0964465D0C18333003609C460B5C6A3B977C0278B9314E06",
INIT_01 => X"D335282B37632364585D74010A4F4A4A4E0F602A0A27C2094518810A20003413",
INIT_02 => X"0E63B41681082C6458712D5F740238192A72A20C2C245353D70058454E4E0230",
INIT_03 => X"9A462370CA6D40216E12B2E061065278D3202000024C9C26E0482E222B002A1E",
INIT_04 => X"5C054021D35C792A2000D9006C3A691A193B41044596556A6F0540212656C063",
INIT_05 => X"0204005F2A4F0A64CB3438042C28D349201A1401064C4A1D3000B9314E02D934",
INIT_06 => X"011837384104B2A003042A00692A4500410A7974AA0DD314A109260C21468653",
INIT_07 => X"804D4E520824D7282D09C01B1260696A14031E1A4A5B18286C1A37638405687C",
INIT_08 => X"A5C8256346016105405506610A50381AC01B52042C2453590204201B76006106",
INIT_09 => X"D32553215825202FA6613F00A6043128012831254E02E10623208306C0144106",
INIT_0A => X"5D39C10A2018810A200034132C70342A0760584DF01A0908E052342E20540130",
INIT_0B => X"1218250079190D034105A052190472004965485F194F14112C20E3093300383B",
INIT_0C => X"B2A4AA212667A60437180D49E23AC06F4635C0446105005E942BD25C0B44262B",
INIT_0D => X"6552F307C01441064596296A141D012C0E282E2DC204792C2063652651535C04",
INIT_0E => X"0A612A7D01182A48C265485D2E016106235C6A2B9C3684056800B93A17612A71",
INIT_0F => X"3D00A6044500015099302129192959254938025C3451206A7401260A804D2E4D",
INIT_10 => X"D830201A14290178914DF4661860312A12470120E307C01441064596514D5367",
INIT_11 => X"202A736AB907C0180160D71919034A5218541A1CD24508649736181825208105",
INIT_12 => X"0A22EE02A604E02AF3520804603A8405687C0178576DC01441064596191B8A07",
INIT_13 => X"6905402D062702648D3992082C24D77093538907235C2A25260253259472C067",
INIT_14 => X"8E035735D95CC0144106A5C8255D86579A0751000650381A25208105692A082B",
INIT_15 => X"2919114C2A51947701182A009266991E20140128C961404D144C9430010D4025",
INIT_16 => X"6605404914414104B2A00304804D6E1B2A3EC3054500C104540001509930E12A",
INIT_17 => X"21062328CC60D8543D1801309346C014410645966A3A12043700692A20192A01",
INIT_18 => X"204C01604A52C80E40258E178305F82A473A194C0A52F7340124EA2A396B1115",
INIT_19 => X"862BCC60D8543D00FE2A1B18400068004105204D8A0A2000D900785E3A1BA10A",
INIT_1A => X"E3093564637941044596791937016C523763C000584914510204405277112C78",
INIT_1B => X"46054052395307042544E106000DC067CB5CE907C0144106B2A48646E00C2D58",
INIT_1C => X"6A03A60A202CC104C01B5C310663A602A604450001509930212FA661804D3402",
INIT_1D => X"480AD7017E1BAA01064C4A6149380264CB341804603A84058A19181BB507C05F",
INIT_1E => X"A5C8454D4E02D15008182A00F91A1564D55D082B8917934EC0144106B2CCCE34",
INIT_1F => X"6A3A12448622C0280164D754602AEA40610536446104571DD234E807C0144106",
INIT_20 => X"861340656E1A9711B900F82A392B1104E02A471A0D0141056E14020460528405",
INIT_21 => X"8A19181B15309346C014A10A200034132C40885E205C0124AA21593901642546",
INIT_22 => X"8405E91A7C7234016C3A193B3C032A391103D1644A0255291903A6044D186104",
INIT_23 => X"8405B2484516193B783A2700CB116591A5C8854D6E2A957E0118255802048066",
INIT_24 => X"0584804D0E220E1245964A3A1904201B79008596C928092817179A7A232C9456",
INIT_25 => X"2E12610458399B4A2000D311B2A4AA1A2A1EA10E20299052110620459A365804",
INIT_26 => X"CE1BB112B2C84516543A935E8A11A5C8052B5E11A10E804D0E63A6266209402D",
INIT_27 => X"C05F6A1305842D006C3A31256E110584804DAE61BA1220B40178863FE206804D",
INIT_28 => X"9E3E531D0128D710B2A8C95C0C2493220A03610580324E1C017074122C249432",
INIT_29 => X"B52B270034118596B4508516B4284A294A294A298D13A5962B2AF86AD4036C3A",
INIT_2A => X"74122C244635205C0178515D465BF8040067AE01B5A4DA44B51A2B004A021929",
INIT_2B => X"2E29174D0E7847092328CC4826010D6912500964B84C296A943F62043E46465E",
INIT_2C => X"01223A2D0130D3793703385D8643C81C7200311AEB042328681A0D614E022A1E",
INIT_2D => X"206ACB215749260079391C036C3AEA000A39196B6F0410299304001AEA1E260C",
INIT_2E => X"301A1C062200B45073048D12A5C8455DAE4A8A2CE32A696A0464465D8C00E106",
INIT_2F => X"D36D861385964A5F0C30D3415747C02801606C1A0B30D35D6A1B110301082029",
INIT_30 => X"4A617E00A58000000000000005800000000000800000A58000000580A5800130",
INIT_31 => X"6B29804E7100A5C8256AAB46AA013E1E26531364B84CD801A5C8055E942F0148",
INIT_32 => X"A5C865528A4D3A01E106403A1C27410485969A7A202957535B25260045961929",
INIT_33 => X"0D4C4A1D406DB8281C5CAA65467140216E124596DE242051941145963446AA11",
INIT_34 => X"A5C825575265D900791A2E1ABB0CA5C845792751941145963E2AD944804D6E1B",
INIT_35 => X"201B8D134596B248C528C9016C3A192B5765D301D310B2E09A3A576149244104",
INIT_36 => X"A611A5C8E50C53002A1B115034134596696AF41A005234128596B92A68520818",
INIT_37 => X"585F074C4A1D302C01484A61270C21468A13A5C8252910290D0158798A04406D",
INIT_38 => X"6104396A585DC000D8102C283A322A00F952182892622D002D2B2A130130D335",
INIT_39 => X"4039E9042600BF28984E2434C117E02A2D2B8C6620293A3200678A012D6B5412",
INIT_3A => X"951E6104F9526B29201BEA32A0658E134596EA6AD1190B789766E63A152B5705",
INIT_3B => X"8053693A3C044596FE6653019C46D12C01344C535301D72C8053693A1C04602A",
INIT_3C => X"4847EA262304A5C8E517494DAA527968A365C0470E1B0A28974ABE0058613422",
INIT_3D => X"0908804D2E4D0A612A4502785941C85DC000D1285B5D2B00782A95023E66D364",
INIT_3E => X"590BBC78191BB30C4596586134222600593718606C3A1C272304B2E0584DF01A",
INIT_3F => X"810D6F00311A004388466704AA1BC02794460718804DAE612E4DE61E2344915E",
INIT_40 => X"5303D31045963814010B804D2E1EC71CC047D1202E2B2D1BB50CA5C8050D2028",
INIT_41 => X"03042A30E30D20468630E152342E204802242A72E656B804580058530E619322",
INIT_42 => X"94460718804DAE612E4DE61E2344915E590BBC78191BB30CA5C8652A953A0120",
INIT_43 => X"3104A5C805072560A20CA5C8050D2028810D6F00311A004388466704AA1BC027",
INIT_44 => X"782A952A23044596782A952A2304A5C845531E500950D804234C571F002BDB28",
INIT_45 => X"AA21865EB51A402D6E422000D810B2E8D4036A53C70058293703D1285B5D2B00",
INIT_46 => X"5765D848576D540FC01F2029EC2AF268B804204D4E126104D265C86D00670E60",
INIT_47 => X"261EC067585F2000D165530F014F57672634240CC1479C46983021468E036C3A",
INIT_48 => X"661B380F001B804D0E2FC108402D6E42213001226A126106A021D369A3044025",
INIT_49 => X"D91C0154464520006700C91977194062C511B2E4865E2D130160D94518785131",
INIT_4A => X"1730D361EE02017807541A242A2F2E3A4104B2CCEE04404D344503242A575265",
INIT_4B => X"2230814DF466D80C2E00384FEA5E1A01410923488E632B00FE662200B45C6A3B",
INIT_4C => X"342E4405405D3A23FA66182892628A1B202C015C0A53110DE12A984608289222",
INIT_4D => X"F40681059A7A2B0078521029074826058105AB5C054826112052374F14112051",
INIT_4E => X"58530E6193223718525D272862049A7A004F6A192A013E5E464D39004105E01A",
INIT_4F => X"804D541A4052345DC16457212400E91A9C66401A090472002A1E52672700D800",
INIT_50 => X"653A0D136105A06AB2E02A42D3106105A06AB2A8D81C00670E64066010511704",
INIT_51 => X"4596193B86136105A06AA5C80557AE116105A06A4596582913126105A06AA5C8",
INIT_52 => X"0134CC35A5C82519AA11410EA5C805226A126105A06A4596192B0D116105A06A",
INIT_53 => X"C511A5C8252957655325C2072664410520467A1501202304A5C805335347245C",
INIT_54 => X"804D0E3B3704A5C865450A5F9A7A2029935337016A5209062700C91977194062",
INIT_55 => X"6601410E260CE12ADB5D200093536904D22420480364861E20005839F71A2807",
INIT_56 => X"D23024280144D1280124EA3A7904B85211792804A5C805627904106784053846",
INIT_57 => X"0D090260103911280D608630C147F23AEB04001FE63223785741C85DD904002B",
INIT_58 => X"0A1A720520295803924A0428D0452063FA112C485212B900D81B18286D04B852",
INIT_59 => X"8D2B926246042204A5C82529D938485DB51A492C0128C84D5000B948452AB800",
INIT_5A => X"B2A42A1BD9310628974A804D2E678A25620536042204A5C82529D9648E19201B",
INIT_5B => X"5368026086072204B2B0D3355949144F420B2320030464006C3A9B4A25042204",
INIT_5C => X"5A085300384F4A3A6952C805C02B2D03F968340174122C5CAA56AA1A0164D160",
INIT_5D => X"5339774D5A0F371C0124D77034036C3A9B4A25042204B2C0C84C1830D3491455",
INIT_5E => X"873041150028DB2891302115A01758218E3608503C434104B2DC6A4E46023E26",
INIT_5F => X"6D04D168C96D2E4D4E0BBC609A3AC8555863C01401054596574DD32540491429",
INIT_60 => X"D71401288D30214686036A522063D319CC006C3AD3287104CC1CC0006C3A2952",
INIT_61 => X"BC609A3AC8555863C0140105459634672A3A196B821758530E391B182D004949",
INIT_62 => X"3B04A5C8254D9A5E0C04520058530E61932253036C3A3E02D168C96D2E4D4E0B",
INIT_63 => X"182B135E260161066C005852F448423153272028410F2E5D463320280128C851",
INIT_64 => X"8D04002BC844D5042017B428CB45241C0160195308644855585DD8254C646504",
INIT_65 => X"F4722417007B06030A3974036C3A9252A70C45962A521554D73418185200C928",
INIT_66 => X"2A3A15184000494D5767301C011C0328C865741EC1042017B44C2E2B170D814D",
INIT_67 => X"AE02182BB1659772C0140105A5C8454D8E19D225610B2370B4112C6458272A00",
INIT_68 => X"551A3104A5C8E52A523A290F07183600551A310445963800D86CD3202A000A29",
INIT_69 => X"B2E49A023E5E464D2500551A310445969C4EE02A523A097851656E3A4B252500",
INIT_6A => X"A5C8255FB46140654E5B804D4E52481D2E782204B2DC2A5FB461805397792204",
INIT_6B => X"94508412941C0428C1142A1805000000E014B2F074026C521164D84460782204",
INIT_6C => X"D95D4C65D301D15C3A23FA663804A5A8C1142A18054884129450841294508412",
INIT_6D => X"27006C3ADB28710449614E52B74A14013E2A576D0A170170F44CCE5C20280178",
INIT_6E => X"8405975666670178077871522029F952B56A7804D719BC244E5E0130D331D334",
INIT_6F => X"F76A0804804D2E37CC2D2328D1351C185300696AF41AA061265658044596CA1F",
INIT_70 => X"40256E53B77A0364861E0039CC48200C010FA5C86572F426270053357904792A",
INIT_71 => X"F40001640660592912289302F82A296AF4180160105117043348C2654865F456",
INIT_72 => X"2D1BB50DD310A5C8454DF409804D2E69114D8E300147D12C5765862B01483467",
INIT_73 => X"B2B0D34D9C5E89040027D15CAA0D41537E0640492E3F62045765595718202E2B",
INIT_74 => X"977C02042A00384FEA5E1A010A5DCA2D20006C3AB9316E0D012797726D00D311",
INIT_75 => X"2E1C014CAA654A0C213B071853009353240029526D054031661A52042C5C6A3B",
INIT_76 => X"485384051822F4023E6366024A5218082600311AEB2AD970C0480324CA5DD720",
INIT_77 => X"2B0052295804A5C845531E30D35DAA65546223600A57264614012A522D04B4B4",
INIT_78 => X"4A0CE12A55290930D365593125002A522D04B2E001289136C0006C3A8C392909",
INIT_79 => X"C9612046460A26602A380318C01F2029696AF45E1A3B4104B2E48E0C0063E50C",
INIT_7A => X"270C21468A1345969353095C6619230F07182063FA01D870201B2D13A5C8052B",
INIT_7B => X"8108A596182B713AA6022A39C86918608E3041492E03676403242E013E46465D",
INIT_7C => X"2039E62E0648B83884059A7A53000D69D20C001B1C70341E2063260267006758",
INIT_7D => X"11038952AC0CB2B4683A7A00FE00A58001600A634E028589A5C825192A39E104",
INIT_7E => X"FA0105844A0C4131D7344804B2A8D149C000FE0020805861D849792862040D1B",
INIT_7F => X"052BEE5EA602258480160D1B171180166C1A1111B2A8C9610678F1486E02B84A",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__27_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__27\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(16),
I3 => addra(15),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__27_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized19\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized19\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized19\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized19\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__11_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"905E19038952AC0CB2A4D7684C0A250005844A0C4141F4661840C869B60CA5C8",
INIT_01 => X"234C9C26002B0D1B1701B2E08A25340120803B188553111B0360B8644E092328",
INIT_02 => X"144D1A0820295765D91C250025844596691A511AEA2640000584804D0E227442",
INIT_03 => X"0A2274422500209861048A4DA6215D015853EE6AAB0CA5C805636A629A3A084F",
INIT_04 => X"20CC0260D319F96A080A4596A580810D740085842A0079192D04A5D0256B1424",
INIT_05 => X"0584002BD05D19039C460744261B2B044596C9284D08002B9B4AEA022480D800",
INIT_06 => X"341E201AD92CC000584126034596583909288D00A017F91AAA01E1062E681603",
INIT_07 => X"3B18455E06045200106937632500B2A44625E052342E202C0160556A111B0170",
INIT_08 => X"D85D1C0452002080184EAE02B2CC9C2640451039372F0160D331EA008952F100",
INIT_09 => X"001B3C0F4A0C0127D3444041F4669809A5C8056BD45D0A5F0260B8644E092364",
INIT_0A => X"1818804D0E1A7204384D26029C46270445962A19F1004105201B710101787152",
INIT_0B => X"0D1B0C544A25C000586D4E21EA02B4C8D7001817A580E106A06186019C46D134",
INIT_0C => X"3A632500A5840150A531AE6520480270341E4031661BB80C45962A3958083700",
INIT_0D => X"8016384D26029C46870980160D1B1113A5D02537CC2D20462E634E2802246A4E",
INIT_0E => X"0D1B1113B4E09A3A57614900296A14656304FE2AF91A7A64A3016A52201B2D13",
INIT_0F => X"26632500B4E09A3A57614900296A144901500567484D93224041F46698098016",
INIT_10 => X"EE52D825C047EE1A792A924A2500B2E04A4D50082B00B85237196104495D8A31",
INIT_11 => X"E60020D00370341E24280128E8522B04A5C80522E600B9316E25C1042029792A",
INIT_12 => X"3604A5C80522E600B9316E25C1042029582F93222500A5C82529736A190F0122",
INIT_13 => X"202C01240A2274422548A21A8A03181720D00364585F2D13410500636A42C869",
INIT_14 => X"1818C01F2029F21AD8252500A5C82529F21A5303D235804D6E1B2A0EE152342E",
INIT_15 => X"1C22E600410923600A634E6E21044596E91A9A090264D854204F4E2D4045F968",
INIT_16 => X"20000260535F4A0C41531E60AA61FA6E2104B2DC6A5327500364984AD1000D1B",
INIT_17 => X"9A3A084F144D7A04975271016105804DAE61E6222700384D0A6F2104B2C4D170",
INIT_18 => X"C869B60CA5C8A5614662406D0E634602A60500226A120160D028F76C2104B2E0",
INIT_19 => X"D321D344AC0CB2F0341E804D0E4D2632C0003E4E1460866743092334686A1540",
INIT_1A => X"002B0D1B1203576578523204A5C825636E01B8609546C823040433009C460730",
INIT_1B => X"A5C8051FEE02D15C6A2B1830D341465D6704192B0D11010820636E018A694D08",
INIT_1C => X"2104A5C8A521535700224E5BC034E1042A300324D37120500364984AD16C2104",
INIT_1D => X"2A00182B3129AA11B2E8D42B810D204D8E03810EE00CA0215357C000384D266E",
INIT_1E => X"050D2028C10D0022F4020164783A86192700586198663B0061047852D5289C04",
INIT_1F => X"E9066B00610579009853B765260C213B002B191B79042480F818976D2104A5C8",
INIT_20 => X"2360EA2B4A5B7804193B9703410A2700F81897015765785232044596196B0C3B",
INIT_21 => X"2D2B8D032A3948252B002A1E666A466C2104B2CCCE5437008584A052371DC104",
INIT_22 => X"B462804E23609546C82324044596574DD32542005C65185C14448E5E6705E02A",
INIT_23 => X"1C6322044596D265C86D006BD4217852686A42005835281B153B6904D348385F",
INIT_24 => X"24005861D849C047EA1A0728DD742304B2E00A634E6643092328DD0802606C3A",
INIT_25 => X"4075260445962A39D800556AEF04001B2063A602B82A8A63407526044596D728",
INIT_26 => X"D9442B048596185EA662804D8E53B7652340885E2000194FCE300660AA61E622",
INIT_27 => X"804D0E22744223244635204802785165063951252700383B0D28DD7403042A00",
INIT_28 => X"F4661828DD742304B2A446352400586D542A1778311B6A622204A5C8256BF404",
INIT_29 => X"586D542A1728DD742304B2E0953608042B006A1B1304331C01606A1B2A224041",
INIT_2A => X"2B04B4B4485384052A3918043700B931EE1E0160593140752604B2A446352400",
INIT_2B => X"6C3A1C7723044596F21AEA528B040063F4220660D3411828DD7403042A00D944",
INIT_2C => X"1C632204A5C845492E5F0178F71A1578515DE61C0160460E27500364984AD100",
INIT_2D => X"0D612204A5C8453189262700D800F21A240018226E66C3042328DD0802606C3A",
INIT_2E => X"F4661828DD00D310B2C8D7008584521C0160AA61266240754608260C012BEC1A",
INIT_2F => X"0033D3711828DD742304A5C8852991043700696A940355290918002BD0484041",
INIT_30 => X"0E4D2632C034E1040067AE6122044596572551530D130130D335D830234C9C26",
INIT_31 => X"A6606C3A1C632204B2A46A4E3A63C047EE1A792A924A2E1CC1042370341E804D",
INIT_32 => X"0228C961C950F7005835D85C4809E052F21A24480260F36A1928C94407046007",
INIT_33 => X"905E1903AA1B2A00D1190D18E02A696A0022E6005731CC645804B2A446352400",
INIT_34 => X"4075260445965829131261052700B85237019C460778B9314E762304A5C8052B",
INIT_35 => X"2378F71AF50423606C3A1C63220445966C3A733A1567830E2600A5900160D935",
INIT_36 => X"6C00A590810E40752604A5C8C51BDC00858474009C4647082A000A5D74014109",
INIT_37 => X"D32D23602A1BD961AA61220445969752710161050047D12C4430214DA6114105",
INIT_38 => X"3E2ADB65663A525F2019AA090260AA21D95C086322044596AA1B42006C3A5731",
INIT_39 => X"B5E057259372403523242A232A53B7023E460639CC48491C01648D399200A017",
INIT_3A => X"190F220445962D1B2A2DE1040067BA6202042360D7284B08804DEE2ADA4E1411",
INIT_3B => X"06282C514904B2E00A634E1A610559452E6342340178314F261A0D4D7402F818",
INIT_3C => X"2163FA361930D34DB9312E020678F71A5504A5C88553F106002B922243000160",
INIT_3D => X"6A622B005839370F2204A5C825511348EE32C034E104002B5947060F0204260C",
INIT_3E => X"120437006C3A79390D13B2F8861B20638E6727286204E91A9A110164D854001A",
INIT_3F => X"2A0079190D042D0058530E619322531F810E43006104196BB765C02801643839",
INIT_40 => X"0204232C8B1E0130D335D84D6E11A5C8256BF404740C2204B2D0392BD1655808",
INIT_41 => X"0E03610637005849140D2204A5C8255F463524000228C944470800675761D30D",
INIT_42 => X"F40C2204A5C8051FEE1201084025261E2000385F0A4FCE042360793A6A0D4125",
INIT_43 => X"234CEE32C05F1C182D18610434672A3A190B02600A3BE60EC147D148972E0073",
INIT_44 => X"91040043D3552063FA361940C869B60CB2A8CB45241801283167E6000160692A",
INIT_45 => X"370D2204A5C8657234012A42C85D79050067D76418249446C7042348D7007929",
INIT_46 => X"D1653804B2C8D7100160985EC82C212BD1655808804D0E1A77048952F100981B",
INIT_47 => X"38468A038952F11861049C46912E4E1C410F2D035765D82C002B0D1B712D212B",
INIT_48 => X"40412E025841EE6678045835C850B75606789153110F2204A5C8852991043300",
INIT_49 => X"0628D045002BD05D190F2204459649255353FC04002BDB28D1042328D04C1818",
INIT_4A => X"F818190F220445965853EE2AB804204D9A72804D2E471A2B370480160A1A1303",
INIT_4B => X"8B04002B0D69342F212BD1653804B2C8D70057555513E106206B08544A25C000",
INIT_4C => X"D05D190F22044596933AD86D2400585D1A6187028952F100C10423244635EA52",
INIT_4D => X"F13401785755D545B804A03A97110178712A2969D8042364D85D9C04201B002B",
INIT_4E => X"C104234451431804521C01601019172D212BD16558082A00396B270445968952",
INIT_4F => X"346324000228C94447082A0079190D04004BE60E2204B2C0C81CE02A8C19191F",
INIT_50 => X"EB04260C0143C864D90C2204A5C8A565465D47056C1C0130D36D46452334C848",
INIT_51 => X"0D1B1103D120EE66463579046C52B10CA5C8C5472A1B575558250022E600311A",
INIT_52 => X"A580C1042328CB4D50080067D871790820286204A590410A79000D6506098105",
INIT_53 => X"384DA61141056C00A5900160D5450B78311B6A0E220445966C3A3E2E002B9401",
INIT_54 => X"260C2163FA36197034020678F71A550445969752710161050057F42679186104",
INIT_55 => X"973A57551A2B410F1218232CCA353904A5C8254DA61141056C00B83A11038584",
INIT_56 => X"EE56F456200057250E4F142D016453495402660A002B581B75046C3A4929F700",
INIT_57 => X"0A03FE002B2A583A0D600A6BD20C220445966B5127006C3A0D3BD32D2A003E2B",
INIT_58 => X"1778072C5161D235004FCE645765530D2204A5C805670A22B4120130D335E81A",
INIT_59 => X"3E46C665536158090230D3655931972E232CCA353904B2C0C85424006C3A7139",
INIT_5A => X"1518232CCA353904B2E4865E2D13016059232330D331D35DA76A202A2A4F8A01",
INIT_5B => X"B439516D2E0A6205201BEA361918001B27005835281B153B6904193BD948CC5C",
INIT_5C => X"000000000000000000000000000000000000000038AA5C3D05CF8E22A5C82551",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_61 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_62 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_63 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_64 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_65 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_66 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_67 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_68 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_69 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_70 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_71 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_72 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_73 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_74 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_75 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_76 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_77 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_78 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_79 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__11_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(16),
I3 => addra(15),
I4 => addra(13),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__11_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__21_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000100880030001E000001880030001E00FC010200890000000000",
INIT_01 => X"060085F8301C00FE000201008600F000000000018600F00000F8000202008700",
INIT_02 => X"0E02000000FEF9021600FA001400F401590000000FFF0002590000000FF20002",
INIT_03 => X"1EFEFC0202008400000000000000010059F2F01C0FFE00020E00F0001F00F901",
INIT_04 => X"00028100C20000F400028100C20000F6000207008200000000FF000283F2301C",
INIT_05 => X"00027F30C21E00FE000280000000000000021200C20000FB00023200C20000F9",
INIT_06 => X"640011F400025D00640011F8000208006F0020001E00000101007F30C21E00F3",
INIT_07 => X"30001B00FD01210030001B00F9017A0000001200FC015D00640011FD00025D00",
INIT_08 => X"1D0000017E30C21E1DF3000202005D00340011000001190030001B00FB012D00",
INIT_09 => X"7C00F0000000000102007D000000000000007D0000000000FB0102007E00C200",
INIT_0A => X"000000007A0000001200FC0102007B00000000000000010013F2301D1EFE0002",
INIT_0B => X"7800000000FE0002020079000000000000011200000000F9000202007A000000",
INIT_0C => X"0002030075000000000000010100760000000000000101007700000000F90002",
INIT_0D => X"740000000000000001006600000000F0000264003000000000026400300000FF",
INIT_0E => X"FB013C0000000000F2010300720000000000F201010073000200000000010100",
INIT_0F => X"20001E00FF010100700000000000000001007100000000000001710000000000",
INIT_10 => X"00016D00080000FE000202006E000000000000016E00000000FE000202006F00",
INIT_11 => X"F80010FE00026B00F8001000000204006C0000000000000001006D0008000000",
INIT_12 => X"FC0102006A0000001E00000101005300F800100000015300F8001000F8015300",
INIT_13 => X"670074000000F9016800860000EF000207006900000000000001690000000000",
INIT_14 => X"3200860000F90002310084000000FA016600820000F000021600FA001400FD01",
INIT_15 => X"34000000F9015900001C00FE00026600000000F0000206001200860000FB0002",
INIT_16 => X"00FEFC02020064003000000000026400300000FF000265003400000000016500",
INIT_17 => X"0001580030000000F901580030000000FC010300630000000000FC0163000000",
INIT_18 => X"C00000F900023100C00000F80002040062000000000000000100580030000000",
INIT_19 => X"000201002AC2301D1EFE000201003100C000000000013100C00000FB00026100",
INIT_1A => X"0000000101005F00000000FE00020100600000000000000001002AC2301D1EFE",
INIT_1B => X"03005C000000000000015C00000000FE00025D0014001100FC0103005E000000",
INIT_1C => X"00000000000001002B00F000170000012B00F0001700FC012BF2F01C17FE0002",
INIT_1D => X"0300580030000000FC01580030000000000102005A0000000000000001005B00",
INIT_1E => X"001900FE0002010058003000000000011200860000FB00025900001C00FE0002",
INIT_1F => X"5400000000000001010055C0000000FE000201005600000000000001010057F0",
INIT_20 => X"00000000EF013900F4000000FB015300F00000FEF3023C0000000000F2010C00",
INIT_21 => X"F4000000F301500000000000F9013900F4000000FE01510000000000F0015200",
INIT_22 => X"0000000000004F0000001200F1014F0000001200FC014F0000001200FA013800",
INIT_23 => X"02004D0000000000FF014D0000000000F20102004EF8301C00FE000201004F00",
INIT_24 => X"000000000000310000000000000102000E00FA001F0000011CCAF0191FFE0002",
INIT_25 => X"130030001E00FA0103004A0000001B00000101004B0082000000F90101004C00",
INIT_26 => X"1EFE00020200480030001E0000010100490000000000F301490000000000F901",
INIT_27 => X"4600000000000001010013C2301D1EFE00020100470030001E00000113C2301D",
INIT_28 => X"00000000F501450000000000FB01450000000000F801450000000000F4010600",
INIT_29 => X"00FB00024400000000F9000202004500000000000000450000000000F6014500",
INIT_2A => X"00000000000102004300000000000000010017F0001C00FE0002010044000000",
INIT_2B => X"0002408610001E00000202004100000000000001010042000000000000004200",
INIT_2C => X"00000000000001003F10861E00FF0002408610001E00000202003F10861E00FF",
INIT_2D => X"02003C0000000000000101003D000000000000003D0000000000000102003E00",
INIT_2E => X"1E00F70103001600FA001400000101003B00F00013FE00023B00F00013000001",
INIT_2F => X"FB013900F4000000F90103003A000000000000013A0000001E00FD013A000000",
INIT_30 => X"37000000000000003700000000000001020038000400000000013900F4000000",
INIT_31 => X"0000010035003000000000010100360000000000000022000000000000010200",
INIT_32 => X"860000FB00023200860000F9000204003300F800150000010100340000000000",
INIT_33 => X"160000013000C0000000F801020031008600000000011200860000FA00021200",
INIT_34 => X"301C00FE000202002D0030001B00000101002E0000000000000101002F00F000",
INIT_35 => X"00FE00022AC8F00000FEFA022B00F0000000FB0103002CC2301C00FEFB022CC2",
INIT_36 => X"2800000000000000280000001E0000010200290000000000000101002AC8F000",
INIT_37 => X"0100250000000000000101002600000000000001010027C0001D00FE00020100",
INIT_38 => X"1B00F901220000000000FE0108002300F000170000010100240000001E000001",
INIT_39 => X"000000001F0030001800FA012000300018000001190030001B00FB0121003000",
INIT_3A => X"02001D0000000000000001001E000000000000001E0030001800FC011F000000",
INIT_3B => X"00FE000202001B0000000000000001001CF2F0191AFE00021CF2F0191AFEFA02",
INIT_3C => X"180000000000FB010400190030001B00000101001A00F000000000011A00F000",
INIT_3D => X"0000000000000100160000000000FD0117F0001C00FEFC02150000000000FC01",
INIT_3E => X"1200000000FF0002010013C2301D1EFE00020100140000000000000001001500",
INIT_3F => X"000101000F000000000000000100100000000000000011000000000000010200",
INIT_40 => X"0000000001000C0000000000000001000D0000000000000001000E00F0001F00",
INIT_41 => X"0000000000000100090000000000000001000A0000000000000001000B000000",
INIT_42 => X"0500000000000000010006000000000000000100070000000000000001000800",
INIT_43 => X"0100020000000000000001000300000000000000010004000000000000000100",
INIT_44 => X"37E636D8360282CB36C036B53600000000000000000001000100000000000000",
INIT_45 => X"3ED038BD386F3845411E425F380438423EDC37703756373C37C1823437293707",
INIT_46 => X"3A6B3A593A113A6344A739A2399D39B739973959393539273912392239DB3D1A",
INIT_47 => X"3C573C243C893BB641803B723B6E3B673B413B153B4240E93F0F3B883AB13A82",
INIT_48 => X"3D823EE33DC43D953D903D9F42793D4B3D473DEC3CC23C983C143F7A3C943C76",
INIT_49 => X"3F3540753FFD410B3F6E3F5F3F023FFB3EF13EED3E7B3E633E093EFF3D4A43FA",
INIT_4A => X"412F4134411441FE40CB40F837C540BE402044B840F43FB63F2A45A03F7F3F7A",
INIT_4B => X"4318431243A24287428042424234443D42324213420E42D841D441AA410D46CF",
INIT_4C => X"45304510450345ED44E2449B40B644D043A7438143784365432B434543274322",
INIT_4D => X"0000000000000000003E463646294620461B460846E645F345524530383F4534",
INIT_4E => X"0000003D41000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000004C3900000000DD38000000000000000000",
INIT_50 => X"0000003D41783B000000000000000000000000C83F0000000000000000000000",
INIT_51 => X"000000000000009A42623D000000000000A23C00000000000000000000000000",
INIT_52 => X"00E4410000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"00000000000000000000000000DA4300000000000022458C3F00000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"00633C1100000000000000000000000000000000000000000000000000000000",
INIT_57 => X"00EC3BF600A446F5004B3BF4005746F300C93BF2006441F100B43BF000C44CEF",
INIT_58 => X"00004CFE00D54DFD009D46FC00FC4CFB007143FA00AB3FF9007346F800AA41F7",
INIT_59 => X"94251700F304A594651600F404A59445160087416A93C114B90207222E2C03FF",
INIT_5A => X"00018079AA3B1900884166BB191900F50818D3171900FF04A594A51800F204A5",
INIT_5B => X"A594311A0001809597D719000180A594D71900894165BA8619000180F9AA3B19",
INIT_5C => X"1A00FB04A594691A00DF2253B9681A00FE04A594651A000180E59A391A00F804",
INIT_5D => X"80A594F91A00F10869EAF41A008B41C5C7B51A009F22DABA791A008A4157F178",
INIT_5E => X"6E1B008C411099391B00F1410D99391B00F308A594251B00EF41A594101B0001",
INIT_5F => X"0180A594AA1B000180A594A51B00F708A5F8861B00F74145C1861B000180349B",
INIT_60 => X"A8D71C000180A594D71C00A9410DBBD31C000180A594CC1C008D41A5C0C81C00",
INIT_61 => X"000180A594D91C00018059C1D81C0001809CDED71C009441A5ACD71C008222A5",
INIT_62 => X"6AD24C1D0001802AE64A1D00FB222EEB461D0001802A9EDA1C00EC4145B5D91C",
INIT_63 => X"1D00F008D9A8531D00F00885D3511D000180A5C4511D00EF0869BA4D1D00A941",
INIT_64 => X"8045A5261E00E32205A2261E00A341A5A8D91D008E2205A7D71D000180A5A4D7",
INIT_65 => X"341E00E7223ED1341E009D4105A2341E0001800EE32A1E008E4125E3261E0001",
INIT_66 => X"018038DD861E00CA222ADD861E9001C025DD861E00D522A5A83A1E008F41A5F0",
INIT_67 => X"AB931E000180A5E4911E000180A5F8891E00018058B9891E000180A5E4861E00",
INIT_68 => X"0001802AE6991E00018005C3941E0001802AC2941E000180A5C0941E00018005",
INIT_69 => X"05E3E61E00F9412ECDE61E0001800DCDE61E00018051A1E61E000180A5949D1E",
INIT_6A => X"1E00E22253C1F41E007B4165A9EE1E0001802D9BEA1E009D41059AEA1E00E922",
INIT_6B => X"80A5F8541F9201C0A5944C1F0001802A9E471F009141A5E1FA1E00DA2265F2F4",
INIT_6C => X"591F00F604A594591F00B122D3CD571F00BA2249CD571F009341A5CC571F0001",
INIT_6D => X"0180D8ECD3200001802AA6D320000180FE9AD320000180A5A8CC2000018093E6",
INIT_6E => X"C1D820000180A5A8D82000A72249EDD72000EE41C5DFD72000018059D5D72000",
INIT_6F => X"000180C8C5A62100018065BAA62100EE41A5A1D92000A941A5E4D82000018059",
INIT_70 => X"38E3AA2100018025E3AA2100018045E2A62100AD4145E1A62100B34125CFA621",
INIT_71 => X"2200018045E5BA2100F04105A2BA21009441A5CAB4210001806ACAAE21000180",
INIT_72 => X"41E5C82E2200018078AD2E2200018065AD2E2200C522E59A2A22009141659A2A",
INIT_73 => X"8B22000180A5C4862200018045ED342200964145E13422008B221CA234220095",
INIT_74 => X"AD41A5A8922200FA226ED2912200018005CF8E22000180A5C48E22000180D3AD",
INIT_75 => X"CF9A22008F22F4E69322000180CEE4932200A34152E39322009741D3C8922200",
INIT_76 => X"000180D3E5EA220001803CF2E62200018005A2E622000180E5AA9B2200984125",
INIT_77 => X"A5945923009B4145E15723000180A594552300EF2226E3FE2200994105E3F422",
INIT_78 => X"24009D418A99D224000180A594D22416FA18A594A52400018095C6C823009A41",
INIT_79 => X"226C9A5725009C41D9C44B2500B922A5A4462500F322A5C0D724009B41A5CCD2",
INIT_7A => X"CC2500018093CAC625007D4174B2C625009D41F4E6582500A841EEA2582500EA",
INIT_7B => X"A04168AAD825009F4147AAD825000180A5E4D72500018057CDD325009E41A594",
INIT_7C => X"DC942600AF412A9B9326000180A5A8922600B641A5A8DB2500B841D9D4D82500",
INIT_7D => X"000180A5D4EE2600A14105CEEE2616FA18A5CC9C2600AA4145E19A26000180A5",
INIT_7E => X"869F5227000180E5AAFE2600A241A5D4F42600018057EDEE2600A94145EDEE26",
INIT_7F => X"2900A341A594D928001E13A5E4D828001E13A594A52800CB22C5E75827000180",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__21_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__21\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__21_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized20\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized20\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized20\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized20\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__26_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_01 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_02 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_03 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_04 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_05 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_06 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_07 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_08 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_09 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_10 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_11 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_12 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_13 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_14 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_15 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_16 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_17 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_18 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_19 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_20 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_21 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_22 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_23 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_24 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_25 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_26 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_27 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_28 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_29 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_30 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_31 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_32 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_33 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_34 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_35 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_36 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_37 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_38 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_39 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_3A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_3B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_3C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_3D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_3E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_3F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_40 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_41 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_42 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_43 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_44 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_45 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_46 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_47 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_48 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_49 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_4A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_4B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_4C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_4D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_4E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_4F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_50 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_51 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_52 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_53 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_54 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_55 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_56 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_57 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_58 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_59 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_5A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_5B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_5C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_5D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_5E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_5F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_60 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_61 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_62 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_63 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_64 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_65 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_66 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_67 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_68 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_69 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_6F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_70 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_71 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_72 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_73 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_74 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_75 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_76 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_77 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_78 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_79 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_7F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__26_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__26\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(16),
I3 => addra(15),
I4 => addra(13),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__26_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized21\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized21\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized21\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized21\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__10_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_01 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_02 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_03 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_04 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_05 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_06 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_07 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_08 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_09 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_0F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_10 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_11 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_12 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_13 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_14 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_15 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_16 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_17 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_18 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_19 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_1F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_20 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_21 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_22 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_23 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_24 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_25 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_26 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_27 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_28 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_29 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2C => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2D => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2E => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_2F => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_30 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_31 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_32 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_33 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_34 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_35 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_36 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_37 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_38 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_39 => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_3A => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
INIT_3B => X"5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__10_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(16),
I3 => addra(15),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__10_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized22\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized22\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized22\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized22\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__25_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__25_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__25\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(16),
I3 => addra(15),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__25_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized23\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized23\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized23\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized23\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000002000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized24\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized24\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized24\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized24\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized25\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized25\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized25\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized25\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__9_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__9_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000200000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__9_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized26\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized26\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized26\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized26\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__24_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__24_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__24\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__24_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized27\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized27\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized27\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized27\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__8_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__8_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000200000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(13),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__8_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized28\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized28\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized28\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized28\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__23_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__23_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__23\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(13),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__23_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized29\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized29\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized29\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized29\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__7_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__7_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__7\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__7_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__17_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"220DBB3B2A00D92286CD342A00E0222ED79E29000180A5948C2900A441A5D00D",
INIT_01 => X"6C2A008D2258DF682A00A541D3B4682A00DE2251C9662A000180D1DC4A2A00A0",
INIT_02 => X"A841D3C9A62B00F022A5C46E2B00A641E5AA792A01C0A254DE742A01D1A2DBDC",
INIT_03 => X"BAB92B00BF22D8E9B62B00A9410EDDB42B00A741A5E4AE2B00F504B9AAA82B00",
INIT_04 => X"00F14153E5D82C00DF04D8E4D32C00E804A5C4D12C000180A594CA2B00AA416C",
INIT_05 => X"A5C44A2D00AF41A5A44A2D00ED042A9E4A2D00EB04A5DC462D000180E516092D",
INIT_06 => X"2D00E4040ADDCA2D00018038CDCA2D00E50453C9572D00E10445A1532D00DD41",
INIT_07 => X"41A5A4D32D00AB41A5C4D12D00EA04A5A1D12D000180EEEACC2D008C4125B7CC",
INIT_08 => X"262E00CE41A594DD2D00E204B7AAD72D000180B7AAD32D009D22A5A8D32D00AC",
INIT_09 => X"0180E5D2342E00E304259B342E00F341A5D42E2E00F622AAE5262E009822D3C9",
INIT_0A => X"E6942E000180A5A4942E000180D79C942E00AD419CC6912E00E604EAD23A2E00",
INIT_0B => X"009941A5A4972E00018045A1972E008922C99D972E00F208A594972E000180A6",
INIT_0C => X"C9B1EE2E00E904EAABEA2E00F541A5A8EA2E000180A5C0972E8501A019AB972E",
INIT_0D => X"2E00DE04E5E7F42E00C92225CFF42E00F808A5C8F42E00AE419F9EF42E00AC22",
INIT_0E => X"41A594A53000EC042A9E522F00E00445B1492F009B41A5C0482F00E704A594FE",
INIT_0F => X"DF3000018005ABD930000180A5A8D930000180A594D830000180C8C5D7300089",
INIT_10 => X"AF41A5A8DB3100CD2225CFC63100018038E3B43100EE41A594593100C241A5A8",
INIT_11 => X"A4913200F841A594853200CE41A5A83A3200C42205E3263200018037C9263200",
INIT_12 => X"00018058A1E63200EE41A59CE63200A322C8B59932008A2253A5913201C2A2A5",
INIT_13 => X"65AAEA3200C4410A9BEA32000180D3E5E63200018045E5E63200FE22D9CDE632",
INIT_14 => X"339501A045A54E33000180A5A8FA32000180A5EAF43200018069EAF43200E522",
INIT_15 => X"22BCA4D334B001C0A5A4D334000180A5D0AA34000180A5C0533300018047A54E",
INIT_16 => X"5135000180A5D44635000180A5A4463500B141A5A1D93400018005A7D33400C1",
INIT_17 => X"EE04A5A85735000180A5945735000180A5D4523500018088C6523500B24185C6",
INIT_18 => X"A49136008C41A594D935000180A594D23500D741A5A8C93500B241A594C53500",
INIT_19 => X"00C822A5A84C3700018045E19A3600ED22A594993600E341A594953600EE41A5",
INIT_1A => X"2ABB9339007E41A594A538008C41A5E4573700F041A5C4573700CE22FEB25337",
INIT_1B => X"3A00B341799A683A15FB18A594653A00F722189B553A00A141EAB8473A009341",
INIT_1C => X"41F9AA783A000180EEA2783A008C41EAEA6F3AB4B562D9C46B3A0093416ABA68",
INIT_1D => X"7B3A007E4179AA7B3A15FB18A5D0793A00018052CF793A15FB182AB9783A00D7",
INIT_1E => X"BE22A5A8C93C9701A0C5DF743B000180A594253BB5FC44A594053B00F1220EBB",
INIT_1F => X"945E4100B641A5D4523F00018038AA5C3D00A6222AAA5C3D8C01A025AA5C3D00",
INIT_20 => X"00F522AAA1D94100BA41A5E0D84100B841A5C4D14100B741A5C0C841000180A5",
INIT_21 => X"25AAC74400C241A594A54400BB4105A2744200018058ED6E4200018045AD6E42",
INIT_22 => X"44001313A5A4D344000180A5D4D244000180A5A8D04400018057A5C944000180",
INIT_23 => X"802AAE4645000180A5AC464500BC410DCDDA4400F92245B1D74400018057E5D3",
INIT_24 => X"464500B622AAE5464500B641A5D4464500BD41A5CC4645000180A5C046450001",
INIT_25 => X"0180A594C94500018057E5594500018045B1494500018058ED464500BE4145ED",
INIT_26 => X"E5D84500C641CBE9D645000180C9E9D645BF01C025B7CC4500D841A5E4CB4500",
INIT_27 => X"009441A5A8984600C241A5C09446008422A5B0934600C141A5C0884600C04153",
INIT_28 => X"05B35347000180A5A1534700C441C8DD474700EE22EAAA9C4600C341E5AA9C46",
INIT_29 => X"48000180A5C4CE4800B42205B9CC48000180D3B5C848008822D3C15747000180",
INIT_2A => X"80D1E8D34800AF222AB2D348000180A594D34800C541A5A8D048000180F4C4CE",
INIT_2B => X"D948B201A0A5A1D94800C622DBE1D8480099222A9ED748000180A594D5480001",
INIT_2C => X"C641A5E45149000180A5944549000180EEAAD948000180AAA1D948000180A7A1",
INIT_2D => X"CF9A4A0001802AE3934A00D94119AB914A00018097DED74900E622259A594900",
INIT_2E => X"00B84157A5574B00C9412A9E524B00C741A5A89B4A000180A5E59A4A00018026",
INIT_2F => X"9CDED74C00018005C7CE4C000180A5C4CE4C001F13A594A54C0001802BAAD84B",
INIT_30 => X"4E00F004A594854E000180A5E4584D001B13A594454D00BD22C5E7D84C00F222",
INIT_31 => X"13A594854F000180A594594F001A13BCE5974E001B13AAE5974E001F13A5E597",
INIT_32 => X"6B5100F408A5946B5100FA04A594655100CA410AE33E51000180A5DC3451001A",
INIT_33 => X"F704A5946A5200F908A594655200B722A594295200C441A594D15100AF41E5AA",
INIT_34 => X"94595300D32279AAEE52000180D8DDE85200CB41A5CCAA5200F908A5D0795200",
INIT_35 => X"009222F8AA935300CF22A5949353000180F4DC6A5300F608A5DC6A5314FD18A5",
INIT_36 => X"A5DCCE540001802ECFCE5400018025CFCE54000180A5A8CC5400DD0485D2F253",
INIT_37 => X"54000180CCE0D854000180B2A1D754000180E5AAD55400018025AAD354000180",
INIT_38 => X"8025153555000180A5B4D95400CE41A5A1D95400DD41A594D95400018045E5D8",
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INIT_3A => X"0180A5A8D155009A410ADDCA5500018045A1CA5500CC41A5C0C85500DD41A594",
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INIT_3C => X"00D041A5A8905600CF41A5B13A5600CE41A5B03A5600CD41A5F82656AD01A0D3",
INIT_3D => X"57F9E65600D341A5F8E65600D241A5DC9A56000180A594995600D022C9A99856",
INIT_3E => X"5700D441A5C4515700F8414AA1F45600018025CFEE5600D64105E3EA56000180",
INIT_3F => X"41A594595700D641A5B4585700AD414AE35757D1AE623AA35357D501C0A5D452",
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INIT_41 => X"0180A5D4D25C00D84145E1CE5C000180F4CCCE5C000180D3C5CE5C000180A5C4",
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INIT_5B => X"41A5A8D06400018045C5C76400018025DD94630001800DE58E6300ED4185CD8E",
INIT_5C => X"4A6500B74125CFDA6400A34145E5D864009E22A594D36400DE41A5C0D16400EE",
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INIT_75 => X"E0402B8841000005AB0300019BE100030D4502036103950501069BE1000406AB",
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INIT_77 => X"33830FE04086A04045884140010141000001B1BBB2F88603670094254104B2B1",
INIT_78 => X"392A03E000FFFF7C80392A03E001000097E100FFFF1080392A03E000B0003B98",
INIT_79 => X"5404069C57E300C8556F392A07E000286A6F392A07E001000097E100FFFFF080",
INIT_7A => X"9BE100041E540002199BE100021E5400021A9BE10004205400011A9BE1000220",
INIT_7B => X"104A00A0984A1FE0B4100D0003189BE100021C540001189BE100021D54000319",
INIT_7C => X"FF8C00952A3FE000023F3FE0107F6E7F902D047F0D01520DBB0070373FE0C803",
INIT_7D => X"1917535D06606C3A2D030A532D13B3550B8741590B8641000001000000030066",
INIT_7E => X"04B256907F6100700D007C0D00020D65012D08008C66012D480B864185963800",
INIT_7F => X"2129582F93224600B27FAA2584B285963800B3000249282FE0C5CF06280A2741",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__17_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(13),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__17_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized30\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized30\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized30\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized30\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal ram_ena : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__22\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => ram_ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__20_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"000000000000000400A5E485163800B3000249282FE0C5CF06280A23620BB930",
INIT_01 => X"4D030121045C2D01030DC804A0040500510001014F5301034303013E342FE000",
INIT_02 => X"282FE0C5CF0624D32D2063652651535C04B25C02A0B15C872DB15C862DC602A0",
INIT_03 => X"4A860161C5CF06280A274104B200700D007C0D0000010B9BB2E02103B3000249",
INIT_04 => X"A580B2C75AA0D379A0000000000245963800B3007A363FE007008C0066363FE0",
INIT_05 => X"4FB800000002773129E00007744F0206744FD301A0B05BA7A580B2C05BA059A7",
INIT_06 => X"9A365804B34022884100B10000000002B800000002773129E00009744F020874",
INIT_07 => X"954042884100B2CC9C26E052A06A80322B00791AFC04E02A2D2B8D03DE602045",
INIT_08 => X"0A5F9A7A804D2E1BAA2A37092B0052295804B35900A0001455580068283FE055",
INIT_09 => X"3C0F0718804D2E678A150128D85CAD02676C630BB35D00A0000A5558A5C86545",
INIT_0A => X"0887414E12328897C10000B2E001605355D534804DAE657412B3B2E49A02F352",
INIT_0B => X"E91ACD0C252C2304B3402C8841B800E3763FE0487E1041B0008631BE2B1BE04A",
INIT_0C => X"47235C2A636E3A181825004A5F2C04B3AB0038884100B2E00130D331CC255300",
INIT_0D => X"01383B84052D5F46014105002BC8441540D724205C0128682A585D1530D34157",
INIT_0E => X"560628F1182E1B783A00674E092360575D3A4F6A27A604202B2E012A3B976E66",
INIT_0F => X"004A5F0C5093302137CC452A00D7280B60D901FE00495DAA4A2A170128D965AA",
INIT_10 => X"3BFB6A1806802BCB042378262901648D391104C01F602A0A035329075C6A2B71",
INIT_11 => X"05B351003C884145962A1A190420462A2F0160DC3C4049145F462D00670E246A",
INIT_12 => X"4D0E5E3A026A525544201B2534022857634062C5114A0C010740699701741601",
INIT_13 => X"01B9312E025E0259452063652651537C0B2C78E71A6A02182B135E2601E10680",
INIT_14 => X"252802245353185013600A1A9208B3404D8841B4E8D403EA2A7C0B60396C0094",
INIT_15 => X"0D776F8841000001B2F8E71A6A02182B135E2601E106804D0E5E3A02D81B3C1A",
INIT_16 => X"014CCC61C024620520390617012C516157537E05804D0E462613B300700D007C",
INIT_17 => X"BE2B1BE04A0587414E3F8841A5C84561D5449122201A792A1230D3255355D229",
INIT_18 => X"2046B868D413B3572D8841459667003439E204C0479312B34F568841B000865D",
INIT_19 => X"00123BD11C6E4E06718566DA10B359338841A5C86572940452006700342D0106",
INIT_1A => X"13B3B800399A33830FE04A1D874ACE87A062132A8897C1B2DC8A63D300E10A25",
INIT_1B => X"8841B4A02E4F46521770B411B34D5D884145965771781A205CA20440250E391A",
INIT_1C => X"0318523402975ED749205C0128CC488E09B359000110ABC10099930197934038",
INIT_1D => X"4D5DD505002B5E11016058455303396AC82DCB250063251B2D13B34596495D2E",
INIT_1E => X"410A2E23EA3A0918C02F0E291503196B5204B3595D3D8897C10045962A3A782A",
INIT_1F => X"7412B3402C8841A5C84516B2480507F904A046AA25610BB3533C88414596942D",
INIT_20 => X"682AF76A4805794C1A042500C949F0523F04B36938884100B2A8681A0D010664",
INIT_21 => X"788603192B2704B3403C8841B2A8D75552116B5C2A4D9A00D928971120280178",
INIT_22 => X"0000000300B2C8AA6553009052D1046C00942DA10400274E42977E204D6E2D01",
INIT_23 => X"E10301432A2FE0000000000000030003AB0201039BE1030101432A27E0000000",
INIT_24 => X"069255580304610492947403B49454000000000000000000000503AB0201039B",
INIT_25 => X"06045404AB440100610002044F05AB0102059BE10592947493069355C602A092",
INIT_26 => X"93BFE805008C92BFE8C88FA0B100910DC691A0000000000000000004D7FF8C04",
INIT_27 => X"014FE700A00000014F04AB00120D45E703124FC54D02016102B4945401009474",
INIT_28 => X"C500A00000BFE00002014FD00103430001019BE1000103551D008C4503A00301",
INIT_29 => X"0D00000000000000000000000000000000000000000AC0FF8C0106015401040D",
INIT_2A => X"8C02BFE84802A00261666F0161656FFC818FA08F402C3FE001080D00050D0004",
INIT_2B => X"5201014319008C02BFE80501654F06008C00050D4801A066062D580102433300",
INIT_2C => X"01654F460101414A05A000032D017FE805008C01BFE80501664F65062D00080D",
INIT_2D => X"2FE04E00A000030049000083504F0003A06A018C078688BE2B2BE04C89884105",
INIT_2E => X"0AB23B018CBBA5C845297805005E2619030AB25352A04F018C00860D0788BE2B",
INIT_2F => X"19018C00070DBBA5C88566804DEE5E6A29172817179A7A201B8D03D728115D02",
INIT_30 => X"038A612584B23D00008A435B00030425000A0D018B0D45010343008B0D008A0D",
INIT_31 => X"018A41A580494DD465534927006700B2A5E0B2C5018A4119A9EF50B2A58DB2C5",
INIT_32 => X"0260B8602113B2C0000AA0C4008CBBB2E00164B84CB205BBB205008CEA9AB2C8",
INIT_33 => X"E8C808A00904656F06008C0904666FC908A0AB008CBB45960A1AD90927003864",
INIT_34 => X"744FD101034300872D09BFE805008C05BFE8C808A000862D05BFE805008C09BF",
INIT_35 => X"06744FD787A05A5D88415CFF8C8A95470B094159007C3B008FC10000004F0006",
INIT_36 => X"00ABC10009A35E5D88416201604140FF8CC5878666497C3B008FC10000004F00",
INIT_37 => X"AA04008C7BAA470C09411CFF8CC50D094AC911094A273F0A004A0009A3CA107F",
INIT_38 => X"0051007FA3CE02074102008CFE3E02074107878688BE2B2AE0010A0DA097B209",
INIT_39 => X"8C2D868D2D888E2D0B008C4507090C8895C1D50F89088895C10706009FE00011",
INIT_3A => X"00080C8895C1E7BD6F01028895C1EFBD8FA0007C0D05008C007C0D4B02074187",
INIT_3B => X"00000007C5FD8C07622A3FE0CDFD8C450A0B078895C1D7BD0506098895C1DFBD",
INIT_3C => X"0BB2DC107A616002030C6BC187072D86062D88052D0000000000000000000000",
INIT_3D => X"417B022D450C0241029BBBA5C88566804DEE5E6A29D7052700D9341C280A2362",
INIT_3E => X"03872D107A2D867B2DC8898841CC0C8741D086A002862D01882D7B032D450C03",
INIT_3F => X"A00400BFE000117F5187032D86022D85008CC504A004D1273FE04D87860B6BC1",
INIT_40 => X"A00400BFE00001AC6F5F008CC504A00401009FE000110051007FA371008CC504",
INIT_41 => X"0002A3D9890141DD02A040008CC504A00400BFE000110351D003A051008CC504",
INIT_42 => X"E000110251D0890141D402A022008CC504A00400BFE0000200510002A3D300A0",
INIT_43 => X"0004AB07872D06862D05882DC204A00400BFE00001AB6F0D008CC504A00400BF",
INIT_44 => X"A7E10A008C45090B05FFFF00000000000000000000000000000000000001000B",
INIT_45 => X"7F615970A0006164A7E1006165A7E1006166A7E100780D00680DF3FF8C000B74",
INIT_46 => X"90614B56A07C012DD77CA0521031362FE0107FA3C51B004A007FA3907F2DD590",
INIT_47 => X"362FE0107FA3C51B004A007FA300700D907F2D25008C007C0DBBC3708841477F",
INIT_48 => X"E91A95048029670BB25181A081017E507E7DAFE4A5F8C114B2BB4356A0521031",
INIT_49 => X"02017E6F35028C00700D4800810400600D00710D00800D81052DB1BBA5D46552",
INIT_4A => X"C11D008C3D3B024FCD4AEF04414E004C028FC1138202A00201DC2E2FE04C02A0",
INIT_4B => X"3BC14B0283C13D3B024FCD00017497E1EF007497E15170A05404A057C14B028F",
INIT_4C => X"020154C681A001700D05008C00700DC870A04E3D3B028FC1633D3B028FC1C82F",
INIT_4D => X"800105415E00F8000497C1658003A003031002D52D25E0C8018C81017E9BE27C",
INIT_4E => X"A05B020542463D3B2F3BC14B0780C107007E6F00020154F1F804414602054139",
INIT_4F => X"363B0783C103062D62983B363B0783C16A020543CE3D3B078FC148020541CC70",
INIT_50 => X"03014002D52D25E059018C00700D5581020543C14B007EA3E1000201544C983B",
INIT_51 => X"09020054000201560200729BE17201749BE10300749BE103042D7504A0F803A0",
INIT_52 => X"000802D52D25E00E018C0003729BE200007E70000109540002729BE200097E70",
INIT_53 => X"8000A0008002D52D27E04D00A0002002D52D27E0D77A467C3B0283C16203A003",
INIT_54 => X"7A467C3B0280C14F03A0525046008FC100007E6F000201546000814300030D86",
INIT_55 => X"00027142542F3BC14B0083C100007E6F00020154D281A0E703A0C1008CC5443B",
INIT_56 => X"6053531378D3486600EA2A1C05B25D02714199008C0203749BE10302749BE1A6",
INIT_57 => X"0D6800000142C001A001020301E82D2AE07195B1BB45960A4D2A4F0A03675C01",
INIT_58 => X"A000014002D52D25E04200EF044155008CC500A0000402D52D27E06C008C0070",
INIT_59 => X"2F017886031929F75208045300D168D3482400396A78520828D828B112B2F700",
INIT_5A => X"2FE0B1000120302FE0B1BBA5C8052B5767465D085C1428B152AA366305004626",
INIT_5B => X"006F0D019B066F2D06862D89880DCD06A0C5FD8C0102015402082DB10001F82F",
INIT_5C => X"C000A000CC353FE0C000A00065323FE0C000A00050303FE000212F3FE0C779A0",
INIT_5D => X"0403434002056705040150000005000500000000000500B0C000A0006C353FE0",
INIT_5E => X"0001000000000000000000000000000AB8000401700495C403056105030549C1",
INIT_5F => X"74ABE100010554020574ABE105040234DB02A004020056000171550000000000",
INIT_60 => X"E100007E740002015605040634FFFF8B71964781A0819504008C010201540300",
INIT_61 => X"04000574ABE1000400540005746F4F8A3B443BB34B0080C100017E6F000574AB",
INIT_62 => X"2FE04C03A003017E6FFFFF8B000A74ABE100007E74000201560A010554560081",
INIT_63 => X"363B983B0383C108007E6F000201540A008C00080D4881A03E8103A00301DC2E",
INIT_64 => X"C10E018C01020154819617015046088FC1527A467C3B0383C126018C01060D48",
INIT_65 => X"01055481955B07A0DE00A00000744FE500A0000803D52D27E0D62F3BC14B0383",
INIT_66 => X"43628000A0008003D52D27E000AB00020155000A74ABE100007E74000201560A",
INIT_67 => X"A0D200A000022003D52D25E0B9008CC57A467C3B0383C14D5046088FC1530081",
INIT_68 => X"3B983B0883C1E16140973D0883C16906A09E008CC500A0008008D52D27E0CF08",
INIT_69 => X"A06E008C00060D01AB000A74ABE100007E7400020056000201540A010554D936",
INIT_6A => X"00A0000403D52D27E0560000A0002003D52D27E0DA00A00000744F4979A04C78",
INIT_6B => X"5401040155D700A0004003D52D27E04C00A0001003D52D27E0EB06A049008CC5",
INIT_6C => X"302FE010008CC500A0000803D52D27E01D008C81028154C14B007EA3E1000201",
INIT_6D => X"000000000000000789FE8C0102015400070D03092DB10001F82F2FE0B1000120",
INIT_6E => X"040303005000007E74000201560202005000007E740002015600000000000000",
INIT_6F => X"3A0442C01027058FC31C008C00050D05062D4B3A044104037D7032008C450002",
INIT_70 => X"03058FC3A943017EA3E1CBFF8C03950500077400300455070A0556402F044340",
INIT_71 => X"8B056E2D05000574003C0656C017064306008C060C065449080642D906A0C0E8",
INIT_72 => X"25E00000004F0001744F00790D0000000000000000000000000000FFFF08A943",
INIT_73 => X"7141400003610000734F4A06A0CD03A00300744F01060DC500A000022000D52D",
INIT_74 => X"027E54D706A04002A0C50002610002734F0202744F3E000100410006734FC002",
INIT_75 => X"E10007744F0006739BE10006744FEB008C0007739BE100067E540006739BE100",
INIT_76 => X"A04002A0C50002610004734F0202744F3E000100410008734FD6008C0007739B",
INIT_77 => X"07744F0008739BE10006744F0007749BE100067E540006749BE100027E54D406",
INIT_78 => X"A00406744FB100770D4606A0C90171418D8077A091008C02710D0009739BE100",
INIT_79 => X"008C0006D82F2FE0CB06A0520504610700044F0507744F00060D04027E54C906",
INIT_7A => X"075020008C07062D487A467C3B0783C1CA200047000407505806A0B100770D5C",
INIT_7B => X"0404045421008C0006D82F2FE0407A467607A3C1527A46078FC1C88000470004",
INIT_7C => X"0D4609010594FF8C0407749BE10006749BE10004045501710D04052DAB3F05A0",
INIT_7D => X"5473822D0000749BE10000734F00000100EEFF8C000174ABE10001736FB00178",
INIT_7E => X"04000000000200B000770D02710DC500A00008734F00010077CF312AE0000177",
INIT_7F => X"AE657412B2517088410000000000000300F2FF8C029500BFE500027D70C10001",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__20_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__20\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(13),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__20_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__16_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5000027E7402020156B980E9521C0480531322620BB2B1BBB2E05355D534804D",
INIT_01 => X"79AB00790D00700DBBA5C82517B2000003ED2F2BE00003005000027E74030200",
INIT_02 => X"0049615A04B2B1BBB2E05355D534804DAE657412B25170884100000000000003",
INIT_03 => X"03ED2F2BE00003005000027E740302005000027E7402020156A5E40524977220",
INIT_04 => X"79AB00790D00700DBBB2A4D364F82A696A486C021C03788603E6062017B20000",
INIT_05 => X"05B25908A00800744F000000000000000000000000000000000000000000000B",
INIT_06 => X"0001500100AD6F0008FF35B1BB85960A4D2A4F0A03675C011C576D804E001B1C",
INIT_07 => X"A00702744F5771A0DA0103424B008C4503716303030049000001500101013402",
INIT_08 => X"4C02034163000B610002744F0B0101502F008C01052D4800076100010150CA07",
INIT_09 => X"010204B0000125322FE049000B610004744F0B02015015008C01062D48017141",
INIT_0A => X"22EA6E022893021917133B402153655361201B2D13B226008CC506A06C05A068",
INIT_0B => X"322AE0000105500B0505500A030550EA05A079FF8C01080154B1BBB2A8DF4D8C",
INIT_0C => X"0A040650EA06A0B8000525322FE00401669BE1016166A7E1D304A004000B0A2B",
INIT_0D => X"322FE00401659BE1016165A7E1D304A004000B0A2B322AE0000206500B060650",
INIT_0E => X"61B1BBA5C825295771781A4924410A2E634A5B201B2D13B259AC0841B8000625",
INIT_0F => X"01734F2B80791AFC048026201B8D13B20006053C312BE0B8002B313FE0C8907F",
INIT_10 => X"0B02095016008C00A70000094F4B00A00002725026008CA5C45165B24A09A009",
INIT_11 => X"C905A001790D0007066A3117E0C906A000027297E200000BED2F2BE000030950",
INIT_12 => X"F82A696A486C2217B200B1BBA596B20000C5312FE00002065006008C00010550",
INIT_13 => X"E1FFFF0000000003B1BBB9D48566804DEE5E6A29F7042E00D9349C00B424D364",
INIT_14 => X"17E049027141EFFF8C000373ABE10003746F0E008C4509030574822D006162A7",
INIT_15 => X"067397E10002739BE100010150D101A0000706CF3117E0C9017142000908CF31",
INIT_16 => X"01746F000001000000000004B001087397E10004739BE100020250C002A0B001",
INIT_17 => X"610000000001000000000000000000000008B80003000477312AE00002746F04",
INIT_18 => X"A03A008C01040D482F3B058FC10500014FA580B205008C00040DC804A0C10201",
INIT_19 => X"47107A614BCC43058FC120008C05A7C778A04579A00584B2C503A04807A0CB06",
INIT_1A => X"0002A3FF8C0104015400060D000008ED2F2BE0000301500802015011008C7BAA",
INIT_1B => X"005400030150020100550002015000BFE50020005500007D7000030150000000",
INIT_1C => X"0005B002A7020112322FE0A580B2C001A00000000002B8000002ED2F2BE00001",
INIT_1D => X"00627400020054000200560061626F0502826F0401826F000000000000000000",
INIT_1E => X"B0000273ABE10000627400020054000200560061626F58050461000173ABE100",
INIT_1F => X"8C04040454000001322FE00000044F000301322FE0480076610000044FD003A0",
INIT_20 => X"62ABE1000262A7E1010062ABE100010255020200540061626F0000000002C6FF",
INIT_21 => X"F53F0100610002AA6FC0030225030200560000AA4F0000000000000300B00261",
INIT_22 => X"4100000000000000000488AB8807015001832D00000100AB0000AA6F00010255",
INIT_23 => X"636F006B0D4C8000A0000063613327E0006163A7E1026C2D016B2D529B441201",
INIT_24 => X"46038FC103A7030312322FE0E703A0C597B2C00504410401634F400100410061",
INIT_25 => X"B204AAC80104412080B205008CBBA5FC0527D3342400B24F0104418B82B2459D",
INIT_26 => X"BD322AE00007744F6C058350E201A00106744F00000100B1006B0D04ABBBE597",
INIT_27 => X"4F6C068350C101A00108744F666696322FE0C800A00061646FC000A000660001",
INIT_28 => X"322FE0490100410061656FC100A00061646FC000A000650001BD322AE0000974",
INIT_29 => X"E10261016F00000000000001000000000000000700B0656596322FE0B0666696",
INIT_2A => X"000105540D008CC500A000640611362BE00604016F23008C45000204006163A7",
INIT_2B => X"0000000000080007AB01632D63072D056163ABE1DAFF8C04950595060063ABE1",
INIT_2C => X"6103A7E1006164A7E1005D0D025E2D015F2D00600D0000000000000000000000",
INIT_2D => X"02014F00AB000061332FE003BFE805008C04BFE8C804A0560201610700014F00",
INIT_2E => X"626140973D0783C1DD008C01040154E4005046088FC101600D537C3B078FC108",
INIT_2F => X"B5008C006104A7E164042DC000A0000061332FE003BFE805008C04BFE8C804A0",
INIT_30 => X"A0846A2D99008C01040154A0005046088FC102600D5369A0747A46443B0783C1",
INIT_31 => X"3B983B0783C17B008CC108A0C000A0000061332FE003BFE805008C04BFE8C804",
INIT_32 => X"A0000061332FE003BFE805008C04BFE8C804A0015D0DDC363B983B0883C16436",
INIT_33 => X"46078FC139008C45363B983B0783C144008CC500A0000407D52D27E0B1520000",
INIT_34 => X"8C07672D06692D4B69A0CE06A006022007D52D25E02A008C04600D7060A04B50",
INIT_35 => X"8C08072D01040154EFBE02016107842D076A2DC800A000008007D52D25E01300",
INIT_36 => X"C10460470661016F6C052D00000000000000000000000000000100000009E5FE",
INIT_37 => X"0160416969A06C6AA000690D676A2DC800A000008067D52D25E0D369A0566AA0",
INIT_38 => X"0A4D2A4F0A03675C0130D361D849606A740226092B180205B2C002A0626BA0E5",
INIT_39 => X"A01B008C0001A8342FE0CB07A001852DFFFF6C4FCD476CA045016041B1BB8596",
INIT_3A => X"040600750061016F004080900F3525E00C904B002010100F3525E00C904CD052",
INIT_3B => X"B20001019BE10000016F0004BFE7E4010441F004A0730260470D018C45016047",
INIT_3C => X"CD010443D8008C016101A7E1BBA5FCA516B200AA0001014F058464009C36C417",
INIT_3D => X"E1000400750061016F04082D056C2D58FFFF6C8FC18580FFFF6C8FC18C0004A0",
INIT_3E => X"342AE0ED6AA0F002A0B1002B313FE0C8907F6108042D4504A06EFF8C006101AB",
INIT_3F => X"003C3117E06A762D69752D00772D087FE805008C067FE848660161000104066F",
INIT_40 => X"0A03675C0130D361D849606A740226092B180205B2DE02A021008C01790D0000",
INIT_41 => X"010B5D351BE0DC52A0ED02A0F707A07A04A0B100690D006A0DBB85960A4D2A4F",
INIT_42 => X"D045297805005E2619030AB2B000670D00690D006A0D67592D695A2D6A5B2D00",
INIT_43 => X"00000003B000690D006A0D056C2DC3FE8C01070D4804A0B100690D006A0DBBA5",
INIT_44 => X"3529E011008C4502A0C2025292006101A7E15A692D5B6A2DFFFF6C4FCD000000",
INIT_45 => X"A00361016F000101F90F3515E04A03A00361016FEDFF8CC20202A10001010229",
INIT_46 => X"000503AB00690D006A0D5C01014F460103410361016F000101520F3515E04A03",
INIT_47 => X"8C6AA7A580B2CA5DA04578A04879A00DB98D13B202052D000000000000000000",
INIT_48 => X"464927003401B2000009086A3115E00A008C000007066A3115E04D6603611900",
INIT_49 => X"09008CA5809702B26596B2C50205415102024104AA0584B20401036F019523CC",
INIT_4A => X"0000000000000000000000000000000800A596B3D83F0102046584B245020243",
INIT_4B => X"01068E362BE006050370040100550003A4E303A0030510526C072D0261016F00",
INIT_4C => X"55000400570003A4568003A003041052E83F0405250001065D352BE0C900A000",
INIT_4D => X"5BE30000036F000100540002055677006A610000036F0002055600050D040100",
INIT_4E => X"351BE00001089BE100016A4F0000089BE100006A4F0805005500110D1200110D",
INIT_4F => X"0F3515E001852DFFFF6C4FCD400200610061016FBC3F04052507008C00010D5D",
INIT_50 => X"0004B8000101520F3515E0403871398895C14000A00061016F076C2D000101F7",
INIT_51 => X"293529E04B026C67B800018501293529E04B006C670003027400000000000000",
INIT_52 => X"0101A20000000000000000000005B800028501293529E041036C67B800008501",
INIT_53 => X"0003410002015D352BE0C900A00002018E362BE0D300A000120152DA02034140",
INIT_54 => X"4A0F008C017FE8480A014A610C014AC60B014A690501A26D0A014AC608014A4A",
INIT_55 => X"000000000003B0AABF0101A10400020129352AE0007FE805008C017FE8480801",
INIT_56 => X"352BE00005835000B0006102ABE100010354010002ABE1000103540361026F00",
INIT_57 => X"6F000000000000000000000500B80000657A352BE000068350C000A00000667A",
INIT_58 => X"042D450C04410400016F00010354C100030441080247C6020247C103A0036101",
INIT_59 => X"047F4123008C01050D480D044A04862DE0BF010441E53F00A00004764A2FE07B",
INIT_5A => X"05A001050D05008C00050D4801004100007A481FE05208024719008C00050DC8",
INIT_5B => X"4596B204AA058430204204B2B1BBA5D0E50C30204204B24D0B04415F020247E3",
INIT_5C => X"6F0000000000000378FF8CBBA5FC652AD064C417B2853F047F418A3F05A0B1BB",
INIT_5D => X"0683504D0100430061656F15008C01010DC80400470005835050010043006166",
INIT_5E => X"B265BAB24502014105A8B13A396A122858274104B2C101A002010DC504004700",
INIT_5F => X"4579A020008CA5C45165B24A02A00201744FA5E4A5050067483D87021929D725",
INIT_60 => X"A5C82517B2000003ED2F2BE0000302500302025011008C00A70000024FCB78A0",
INIT_61 => X"0004026F0300024F06008C00040DC8000342C002A00100FFFF0000000004B1BB",
INIT_62 => X"F53F030425C100016100040270000000000000000004B1F53F030425C1000161",
INIT_63 => X"014ACC02A001102D10032D146B0DC1907F61C658A000000000010000000400B1",
INIT_64 => X"01017F0F3525E05A010361FFFF6C4FCD63852D006163A7E13E008C01040D4814",
INIT_65 => X"0000430061856F000101010F3525E0000101900F3525E04A019066CE907F6100",
INIT_66 => X"48CC43008FC10000014F0106744F5078A000000104AB006B0D03102D01040D45",
INIT_67 => X"014F0108744F5078A000000100B800000001773129E00007744FB086AAA580B2",
INIT_68 => X"0000000400B800000001773129E00009744FB086AAA580B248CC43008FC10000",
INIT_69 => X"6A11362AE000010055000200570003A403120152DC6AA0C007014A0000000000",
INIT_6A => X"A00000036925362AE0000100550003A4C003A003100152DB69A0C000A0000003",
INIT_6B => X"45963E3B981E576D406AD2754612B300560D01570D00B1C16B016AC16BA0C000",
INIT_6C => X"1757551A13B301560D00B2E0933AB93A17612A014B39F710B300560D00570D00",
INIT_6D => X"394104B3B8007F55472FE049007FA20000A5C8054FD465D55D082B092CCA5D87",
INIT_6E => X"D87127003411B2ED01A000C1823FE0000001000200A5C82529691A8D173E5752",
INIT_6F => X"6E483FE0A097BF28DB65465E6E2DA604C013BE00B528D23020006A1B2A2E0134",
INIT_70 => X"EA2E0134D87127003411B20001C1821FE00045969012B3B0BA4401A04500A000",
INIT_71 => X"12B2C000A0006E483FE0A580BD7C456D2E1BF23A6B1925009E780554255F2663",
INIT_72 => X"0044463FE0BB45969012B24EB600B2A42A3A6611B3B7BBA5C8854D2E5F2663EA",
INIT_73 => X"0100480008000F0000B2A42A3A6611B345969012B347B500B2A42A3A6611B3B8",
INIT_74 => X"3819195765D3290164D55D084FE666C000783A4C1D405DAA11B20008005BE100",
INIT_75 => X"4E052057EE22781A37030660692A405DAA11B200B00070373FE0BBA5B4D97152",
INIT_76 => X"B00008005BE100FEFF008FC90008000F0070373FE0BBA5E58E4BC265C85C2A4F",
INIT_77 => X"881C455DAE4A8A2CE32A696A0464465D8C040174C51100129750E413B2110001",
INIT_78 => X"6B3A042C0516B1246504AA402516A90C2115B0442515E017C8172037CC5DBE52",
INIT_79 => X"004900010010BBA5C82529FB2A585D00678D391744D110B22CA0D31123481451",
INIT_7A => X"E413B2BBB2CCD465E652F55288003E4D26132B00496153212E12B2DA00A00008",
INIT_7B => X"054D8E0C4152882ED3112A00F01A5225E66620295765D831EA02A60400129750",
INIT_7C => X"524F201AEE2A9800BA00B200BFE600FF07008FC90001000F52B8D86DEA12A748",
INIT_7D => X"D379CB5D6A13B20000B0BBF1FF8C00BFE5000100300C008C45170105A580571D",
INIT_7E => X"4005A628C114B3BBB2E4485D97222500103B2904B34FBDBBB2C84516103B0930",
INIT_7F => X"0560DE6040218E6E80533152AD0CB3004585A628C114405D3A3A661100622E11",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__16_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__16_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__19_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"C600A0008DA3CF8DA0B8008D8EBE2B2BE04A898E41000001A5E4451691528B64",
INIT_01 => X"D9520D0197C1DF01A08C012D45078C4AC600A0008CA3CF8CA08D012D45078D4A",
INIT_02 => X"B8008C8D8EBE2B2AE0029BBBA5C8455D547AD300B201AAA58001280A274104B2",
INIT_03 => X"494D0A1ADC003E2A495F2500B286AA2584B25E0000420007865147001E864A00",
INIT_04 => X"001917536DA601970E4141861B40258E031817AA11B3B800866C802FE0BB4596",
INIT_05 => X"B20000B2B0D3554A451864B84CD801B386AA2584B2A5C84516B2240A39994E27",
INIT_06 => X"4A00B000700D007C0DBBB2DC8A63D3100130D365CE7026092B180278891E7412",
INIT_07 => X"C0806C3AB9316E2962042A5654554031D35C1903935313026A63C511B2E41E86",
INIT_08 => X"2D00B386AAA5800640C864D92C0130D3793713B266018741C687A0A596B386AA",
INIT_09 => X"36602A5B011917535D4604B2DA7F87664596D1240E391A170160691ACD058704",
INIT_0A => X"AAA5800140C864D92C0130D3793713B2E51D874A4596B387AAA5800130D32591",
INIT_0B => X"FE5E1413B30000B8004E7E3FE0A5C8251AC9214E632500B387AA05982D00B286",
INIT_0C => X"A5C865522E23EA3A0918406D8E010A1B2A5684059752B504C05F542A12787204",
INIT_0D => X"017FA30000014596385D94036C3A5803FE006C3A2D7BD300191BF1244104B300",
INIT_0E => X"610D2048220920635A02B286AA2584B2DD108666761B864A4100A00068283FE0",
INIT_0F => X"029BBB8596B201AAA580E10647384104B2401B014A029BBBB2A42A5D861E492C",
INIT_10 => X"A596B81AED2A7504B286AA0598205D861E2B009C365200FE52AA65C0404104B2",
INIT_11 => X"009FE000118651867F6EBB4596B286AA20DC0170743A4104B200000100029BBB",
INIT_12 => X"7152602ADB284D092334D8712700CB11B300B800068617BE2B19E00000B00002",
INIT_13 => X"9751B702182B911B7101E60620539300B530FA10B300A5C8C5371C609C4E1078",
INIT_14 => X"14874A4619874A00A5C8E5178D69140DA1319A22C4178016D8351928D045401A",
INIT_15 => X"61001A864A4000A00068283FE00000A596B454A516B387AA0598A0658E13B2C0",
INIT_16 => X"010F2C28D72D002B0D650601B286AA2584B200865D3C2FE079867F66C67F8666",
INIT_17 => X"E0B800479A33830FE0A5B0D3259136B209008C65BAB248867F6605A85771270C",
INIT_18 => X"B2A5C825295263932225180128D72D002B0D650601B386AA2584B200865D3C2F",
INIT_19 => X"16B7391BE000B4E09A5E2A63B42AB712B300004596B386AA0598605EFA244104",
INIT_1A => X"11254104B2B0008619BE2B1BE04A1B864A0000B8008617B7391BE00000B80086",
INIT_1B => X"2DC586A04802A00000000000000000170005004596B386AAA58061059302473A",
INIT_1C => X"0004503C000105040395C1D80203410304A44B8002A0568004A0040110728602",
INIT_1D => X"281164B84CB205ABB2C54902413481B202AA2584B26E00A0000086504A2BE000",
INIT_1E => X"02A0B00001384A2FE0B2A4D770B3A5CC9C26B207008CA5EAB248170141A580C9",
INIT_1F => X"A0000003654D11360AE00003A403128652EC02A0B2F88603670094254104B34D",
INIT_20 => X"670034254104B34596D119DB00742EA1040047D17020006C3A473A1111B3D900",
INIT_21 => X"6605E00C80262B009C36404920462A03196B5204B2DE17864AE213864A008596",
INIT_22 => X"B2A40A531111B20B864C680B864AF500A0000A8651FC0A864A4596B386AAA580",
INIT_23 => X"148108B3B2C0C8440734283B157074168108B34152A0521031362FE0C152A0BB",
INIT_24 => X"08B345965D009C4E2500B386AA2584B20B864C530B864A6017864AA5C8A50B47",
INIT_25 => X"7BA602B386AA2584B2561E864A00459667000A5311794104B3A5C8A50B471481",
INIT_26 => X"21468A13B35D0A864100B49C63050046267B4104B34596933A792A391B804E00",
INIT_27 => X"3A9204206334424104B3A5C84516B240977E0430D37926562E1C61046A52530C",
INIT_28 => X"0500675163D311B3591E864AE886A00085966700185317254104B30000459669",
INIT_29 => X"44A0211A13B3B4F893521118201B8D13B345969A7AA046AA0103285767663E42",
INIT_2A => X"96D8351928D045204F4A36D845C7645801181B1171A531AE01E60640314633D3",
INIT_2B => X"12B365867F6662001D874A67001A864AB800878613BE2B1AE04B1E864A000085",
INIT_2C => X"E4EE06405DB868D4030A4D0E033E46C621AA626A0446250E648D39F700066474",
INIT_2D => X"AA208058212E62A03A0D4F4662B287AA05C47A45D1419809B200865D3C2FE0B2",
INIT_2E => X"04B2E41D874AB2F8861B8053F1440160576D2E624045C75C4A6A733A4000B386",
INIT_2F => X"45962A1BDA2AC9003E26D7342500B387AA05982A00B9282C29804D2E671A6525",
INIT_30 => X"B3004596B2484516B386AAA5800130D36559232364552193224031D35C1913B2",
INIT_31 => X"D82817501360B8602113B35979874101870D4587A000B4F0740E615240491411",
INIT_32 => X"2500B387AAA580A105804D8E312E11B25E1C874AB2E00130D331CC25492C410A",
INIT_33 => X"C547D1612500B387AAA580A605804D8E312E11B2A5C8056BD4252A1B01703462",
INIT_34 => X"0452384104B25806104A029BBBA5D0E50C375CE20FB2CE860061007FA300A5C8",
INIT_35 => X"0D804D2E678A016700EA3BD1285704B2B0107F6EBBB2CCCE3006644A2D607294",
INIT_36 => X"3B3FE000B2E05355D534804DAE657412B300029BBBA5C8251AD92C492C026081",
INIT_37 => X"B000862DBE2B1BE040008661007FA300B4DCC6451A291570B411B30000B80089",
INIT_38 => X"007FE8C815864A00000000000003A5C82529B5523711B3C000A000EB483FE000",
INIT_39 => X"4D2E45B45DE20FB2D37F00660086A3DA7F8666598001A000012D017FE805008C",
INIT_3A => X"B225008CA5D4E50C004EEE2627380270B411B2542F88413B008CBBA5C8E50C80",
INIT_3B => X"5D3C2FE0A5C825531503210F0D78311AEA1282050D691278576D2700701A2D13",
INIT_3C => X"00073C3FE0480D8641C6F98646CAF786460386A301020D680016864AB0BB0086",
INIT_3D => X"29522D092B404104B2D87F0366A5C8054EEE262B007E1A30204204B35103A0B8",
INIT_3E => X"0584602A952E01062046B868D413B2DA0B034A4596195F6E01B303AA20806C3A",
INIT_3F => X"86AA0584E00C7B20620BB24002A04001A0B800073C3FE04596195F6E01B303AA",
INIT_40 => X"866F82050D691278576D2700701A2D13B20000A5C84553BE05402997194B00B3",
INIT_41 => X"B2FCC547C71CF4562330D341D1644F00311A33780578195FAE65E02A2D1B1760",
INIT_42 => X"00017E50460000004300017E500000000000000000000005B800865D3C2FE0BB",
INIT_43 => X"C84516B3470203050201005500000574000101500500015001007E7400040056",
INIT_44 => X"DAFF8CA580B2F1FF8C00BFE500047D700C008C450204250401005500010150B2",
INIT_45 => X"610000000002B800673B3FE00068283FE00000A5C84516B200B4210A500D29B3",
INIT_46 => X"2A3A4104B3C1520261C102A0521031362FE001A952022D007A0D007B0D487B01",
INIT_47 => X"00088651CA00A00008865100B80015384A1FE0004596B248055E2601E106202F",
INIT_48 => X"0C201A0E2915670260B8602113B2B800143F3FE04817864AC613864AB0BB00AD",
INIT_49 => X"0A4D1401EA5EE63B0718201B8D13B300B80014384A1FE0004596B386AAA58081",
INIT_4A => X"000001EE25361AE0000100550001A4E701A0010510526E87A0000001A5D02557",
INIT_4B => X"8712BE2B1AE0C0EE8741B2B4D9717900313A6B0559140105B3B1EE870DC600A0",
INIT_4C => X"ED26007FA3B000EE863BBE2B19E0CB00A00010EE504A1BE07887A00000B00086",
INIT_4D => X"04B3A5C8A5658E670344D12D2B640260B8602113B3B000ED863BBE2B19E04B00",
INIT_4E => X"97C10186A300000100B2E4B84C346D4209231C0350690580530D707442C01B52",
INIT_4F => X"6DA61D0130D3491A636604C9288D042A0059290B740E5FA1658E13B36D060186",
INIT_50 => X"812B92620007204D9A5EE60FB355058641B2E0812B9262E00C202F2A02191753",
INIT_51 => X"86664596D9414104B3497F86664596D901693A4B04B34BF70141A5C84516B260",
INIT_52 => X"2584B24E1E014AB2E001648D39170AB34B0D86414600A0001086504A2BE0D010",
INIT_53 => X"20DC010AB24C13014A4596B301AA20C8020AB24C0A014AA5C8253B7100B301AA",
INIT_54 => X"941C8412972C2404B3008596386BF30FB30045964A02381BEA10B34596B301AA",
INIT_55 => X"53274F005865E62A951A6104787274044965465D480A2E1B97569722047CE413",
INIT_56 => X"61C01B7805274C0278D8280063251B2D13B24000A00086764A2FE000B2CC5431",
INIT_57 => X"0598406D8E254104B2D71E874A004596B386AAA5800106602A5B21E2044021D3",
INIT_58 => X"B2F851652E52350F002B582FEA02B387AA2584B28596B387AA05982B00B286AA",
INIT_59 => X"284D080073F400B386AA2584B25C1E864A508086A000A5D0455DD77CEE10B300",
INIT_5A => X"3E4E141C0364C82C6072744220468A03060AB245966C3A5929975DE1042B00C9",
INIT_5B => X"272FE04596B386AA05982B00B950312A8D64057806031839535DAD52DF350803",
INIT_5C => X"C147793A6601101907608A364849C265264F064D2E04B20000B0BB00AD004636",
INIT_5D => X"6B3A27380270B411B300B0007C0D00700DBBA5C8054FAA56A6010A472A0B4A0C",
INIT_5E => X"BAB205008C65D2B2480A874AA594210F2360CA13B26087866600B59C0328D944",
INIT_5F => X"B30000B8004C9A2E490FE000B2E4B84CD86563047412B34596B387AA2080B265",
INIT_60 => X"0D60B878891E7412B34F17864A00A5C88539151800630E02574D94622061C511",
INIT_61 => X"08B3CB14864A3E001F864A00A596B386AAC0C80240884E10788D13B245964A52",
INIT_62 => X"AC8B029C4E2500B286AA2584B2521031362FE0C852A014864C45966B51471481",
INIT_63 => X"51E00C605E3A274104B3B0BBB2C0C8440734283B157074168108B24152A0BBB2",
INIT_64 => X"00B286AA2584B214864BA5C8655247148108B34B14864A711F864A000045966B",
INIT_65 => X"0C605E3A274104B3B000023F3FE0BB521031362FE04152A0BB459693029C4E25",
INIT_66 => X"531B3117804DCE1B1878071C0334686A26264104B35B1B864A0000A5C86552E0",
INIT_67 => X"D765804D2E678A11B300004596E93A8A033E67EA560063251B2D13B3B4E4A521",
INIT_68 => X"8039C70C2500B386AA2584B2581E864A62108666F786A00000000002A5D42529",
INIT_69 => X"C0C85D19249432C0246209201B2D13B3B80012433FE0A5C8E52A9B02556A6F05",
INIT_6A => X"06B26D00A00000AE0001015077040241D00202410201A48D8001A001161052B2",
INIT_6B => X"36272FE0BB45966C3A556A0F78372F0128C8441528CB60C05F6A03E60A001B5C",
INIT_6C => X"244A52196B0819532B0164462DC000D311B24200581041B8000033832FE00054",
INIT_6D => X"531E30D345D1416C34D971202B6A11410A26442B008A19D348270C814DEE1A09",
INIT_6E => X"14384A1FE000B80012433FE0B80012433FE0B00016384A1FE0BBBBB2AC516157",
INIT_6F => X"7C05402A0A7B8308B300004596696A1403740258414602B386AA2584B200B800",
INIT_70 => X"693A4D1D59140105B20000B80001A7461FE0C000A000014D461FE0004596F052",
INIT_71 => X"6C4209234CAA522500B286AA2584B2650B864A7717864A00004596B386AA2080",
INIT_72 => X"A5C8A50B2500B286AA2584B20E008CB2E40E24937AEA001817D9341C44516529",
INIT_73 => X"29482FE0B2CC4A61492C0144C621AA6259140105B3531E864A470013864AB0BB",
INIT_74 => X"A5C8C567552A2500B386AA2584B24100A0008655472FE04B0086A2DD00A00086",
INIT_75 => X"4A004596B386AAC0802A39783A005234264104B2A5C8A50B2500B386AA2584B2",
INIT_76 => X"0105B30000B5D4A516B386AAA580460A00523412B2B0008639BE2B1BE04A0A86",
INIT_77 => X"B2004596670034254104B30000B8006E9A2E490FE000B2E02103196B49095914",
INIT_78 => X"A00086764A2FE00000A5C82529392A32094E00B386AAC0806700D728115D020A",
INIT_79 => X"00459657458C690F344C5353014935D845555208197A001917535D4604B3C000",
INIT_7A => X"4104B2B2B0D335994E0047466DEA02B386AAA5800130D36D5412B25A11864A00",
INIT_7B => X"2700CB015503D028152F01062046B868D413B300004596B386AA0584406D5426",
INIT_7C => X"C01D874AC687A04100A00068283FE000A5D045531E5C46352B004A021929B52B",
INIT_7D => X"A5E0691ACD058704B24E87A02D80B286AA0584C05337632A2D0130D3793713B2",
INIT_7E => X"B3B0008613BE2B1BE04A1E864A000045962A3A592F2500B387AA0598B207008C",
INIT_7F => X"97E1009F64432A0FE06400A5A0680010BA266D00B91041004596FE6640216E12",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__19_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__19\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__19_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__4_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"175735D92C42280128D24C20006C3AD7286D04B85211792804B201A50D000000",
INIT_01 => X"04607234016C3A10511302FE00680001604A456B04D8614A2A137831192A0118",
INIT_02 => X"206365628613B3B800BA5D3C1FE002BA0C019F0DBBB2A003042A540204523803",
INIT_03 => X"2340D364001B8C0437000D19D3551864BA064304B300A5D4E552D11918184035",
INIT_04 => X"5247148108B34B0B864A638000A0000A86516B0013864A000000000245969466",
INIT_05 => X"DE0001A1620186A2B2A46A2A9512B3490C864A460086A203864B0B864BB2CCAA",
INIT_06 => X"2A9512B2B0BB02ADBB4596782A9502B286AA2584B2D302A0020E0151DA03014A",
INIT_07 => X"B34B0B864A6017864A4596B300862C472FE000C7466DEA02B286AA0584804D6E",
INIT_08 => X"2A03196B5204B2B00B864BBB4596782A9502B286AA2584B2B2CCAA5247148108",
INIT_09 => X"017FA370F88741000001004596B386AAA5806605E00C80262B009C3640492046",
INIT_0A => X"0FB3B4A4D750E72A9B02B386AA05F08517C053CD10B200866E0001A35C1B014A",
INIT_0B => X"2D13B300A5C8E50C0022AE264104B300B5B4BA11B3A5D0854DAE657E1A375CE2",
INIT_0C => X"5D3C2FE04A00ED864100B2E4482D4B0174464306B300A5D0C547D1610063251B",
INIT_0D => X"14874CBB45964935D8696C3AB92B2500B287AA2584B25C14874A6019874A0086",
INIT_0E => X"9756662B260CE152342E202C6104B387AA20C80360313A15672104B2B019874C",
INIT_0F => X"D4104100A5C8E50CE06AB4264104B3B800876212BE2B16E04B628641B2E02A1B",
INIT_10 => X"09C01B12605779E656240CA1319A4E0A78E6562700CB11B3B8004E5B491FE049",
INIT_11 => X"A596B387AAC0B401543A0FA04ABA12B2D2AD8741D687A00000B2A4EA2A1C4F26",
INIT_12 => X"E000A5C885530D5C4645E80AC047D128170AB3B800AD8617BE2B19E04B7FAD26",
INIT_13 => X"0068283FE000A5C8E50C2B00984DAE65A061BA264104B30000B800759A2E490F",
INIT_14 => X"0B008C451B874AD213874AC617874ADA0B874A00000100B800623D3FE04000A0",
INIT_15 => X"2FE0BB459653551464B84CD801B287AA2584B2DA0B874A4596670034254104B3",
INIT_16 => X"B286AA2584B253878666A5D4E50C802627380270B411B34F868761B80087984A",
INIT_17 => X"75000F875101000174008616492FE0018716492FE04596B387AA20DCE1082500",
INIT_18 => X"4A5200A00086764A2FE0B2A003501360B8602113B34D000163000A8751010001",
INIT_19 => X"C100A0007A483FE04A00A00086764A2FE04596B386AA058430204204B24E0D86",
INIT_1A => X"B1026C3AC935201B2D13B30000A5C8454D3411B300865D482FE003864B87866E",
INIT_1B => X"413FE0480A874AB0008631BE2B1BE04A08874100459658536E1FD40C25000A19",
INIT_1C => X"B300004596B387AAA580410A4021665D1A0389520C501360B8602113B2B80045",
INIT_1D => X"1903BF50452ACD780518201B8D13B30000B800753F3FE0004596670034254104",
INIT_1E => X"C087A04596F01A09043700C928770570148108B35352A000B2982A394031D35C",
INIT_1F => X"B2D610864A00A596B387AA0598350090521128930258510970B411B2C00C874A",
INIT_20 => X"2B1BE00000B0BB00AD00088651A596B386AAC080C9281728930258510970B411",
INIT_21 => X"8108B200A5D04565261A230920468A03FE2A1B2451538808B30000B0008653BE",
INIT_22 => X"0D007C0DBBB2A42A63EA2A793A2500B286AA0584E00CC0470A3A1178315DA615",
INIT_23 => X"9A2E490FE000A5D4E50C804DEE1EC10923783123A62B2370B411B30000B00070",
INIT_24 => X"01A0011E105F4A27E0B000700DA596D9341C780613B34B7CA000000100B80079",
INIT_25 => X"007C0D00700DBB45963E66485D2E01B201AA05840063EA26C900196B5204B2E3",
INIT_26 => X"537E05804D0E462613B3007C0D00700DB000700D46DE42008FC1007C7E6F7CAB",
INIT_27 => X"00A5C84561D5449122201A792A1230D3255355D229014CCC61C014012C516157",
INIT_28 => X"20CC02245361272C02788D13B2541E864A00B2C446637A6A5900693A4B04B300",
INIT_29 => X"B300B00086873FBE2B1AE0004596384D0A030A1AD20F201B2D13B3A596B386AA",
INIT_2A => X"274104B3DB11864AA5C825236A2D0A5013062B184206B3511E864A00B4D07411",
INIT_2B => X"A244000B864A7D0013864AB4E40E28D0343805270C016B2D033B18253B404126",
INIT_2C => X"D006104A05E0313A1503B286AA20A80160792A79522804B200FE423FE0790086",
INIT_2D => X"CC0A1A0D13B34596B3A5A4535397016105B20B008C05DF4655D5602E19810DB2",
INIT_2E => X"A5800128C961D3016C3A2D2B926225340228D045002753539808B2620086A2B2",
INIT_2F => X"A2000001B2CC0A1A0D13B3B2F8B94A0A60696A1403B386AA2584B24596B386AA",
INIT_30 => X"00016E10BFE805008C0D7FE8C806104A0F008C4B7FE84858104103014B410186",
INIT_31 => X"86AAA5800628D045004751499808B20000B0BB00AD005336272FE00000DEFF8C",
INIT_32 => X"86AA2584B25B1E864A0000B8002B433FE000B49CE30615274104B300004596B3",
INIT_33 => X"033E5E266A6C3A1870B411B215008C4596D835D904195F2A4DFA0A002B3401B2",
INIT_34 => X"CB01A0017F767D2FE0000001B800868777BE2B1AE00000B0BBA5C805632A2A58",
INIT_35 => X"86AA0584E018192F01289856F4562700F96834017412B2B000018613BE2B1AE0",
INIT_36 => X"4104B3B000002DBE2B1BE0007FA34D1B004A007FA30000B5F8703A95042D00B3",
INIT_37 => X"920D2D3B1C6498464900313A5C04B300A5C8054EAE655B0C814D2E4D26634738",
INIT_38 => X"509917691AED062029F82A1B64B84CEA1A27000A4D0E13B240001E864A00B4A8",
INIT_39 => X"1C182D00B386AAA5800140C864D9005765591D206145537E04D91C92222634BC",
INIT_3A => X"6C3A523A1C13B2F100A00010EE504A1BE000B000860EBE2B1BE0A5C86552D528",
INIT_3B => X"B209008C4596B286AACA86A0A580E10620299C46D1003E4646631A64B84CD801",
INIT_3C => X"00A5D045412602E606A04AFA019411B34000A00068283FE0B0BBB2CC54315327",
INIT_3D => X"4104B34F00864A5C7F866600B800868713BE2B1AE0B4B498528D13B34987A000",
INIT_3E => X"0B004A0086A36C13004A0086A3A5D0E50C301C4204B3B2E40E30D35D46714738",
INIT_3F => X"D31979520874021840250E4F0E60B81C0330D335594914030D19EA264104B3E5",
INIT_40 => X"B84CD801B286AA2584B2D50087610086A3B100870D46088741E887A0A5C8E52A",
INIT_41 => X"00B4E44E0540250E4FEE0FB340008661007FA3B100870D4596B387AA20DC0164",
INIT_42 => X"4596B386AA20806C3AD7281C70743A4104B25400864A40010041007A483FE000",
INIT_43 => X"02B386AA2584B210AB107FA3867F2DCA7CA041001E864A0000459653412613B3",
INIT_44 => X"02296AB461270067006C3A703A2D03B81AED2A7504792A924AC04C02600A6BA6",
INIT_45 => X"700DBB8596B286AAA5806105004626274104B24596D168D3482000C9289717EA",
INIT_46 => X"4A4E01A0B00000384A2FE000867E4A2FE04F17864A0000000002029B007C0D00",
INIT_47 => X"68283FE04100A00068283FE0468011864A4B0001A0B0008619BE2B1BE04A1B86",
INIT_48 => X"3A86192019AA11210F4D04B24100A00068283FE04100A00068283FE04100A000",
INIT_49 => X"34254104B3CB01A0A5C8251B6A3D0264552A391B2700D800B386AAA580016478",
INIT_4A => X"CCD46597669322C0002A3BDA026A47744F6E09201B2D13B35B7F866685966700",
INIT_4B => X"6E39F72AB90CB25B058741C000A000EB483FE00000B0BB00AD004536272FE0B4",
INIT_4C => X"18223A01B287AA2584B2691E874AB800A69A33830FE086AA2180B470F4361920",
INIT_4D => X"2D13B34596696AF432202C0160AA61E6222600FE0058397101B386AA2080D800",
INIT_4E => X"B3577F87610085966728012C8B026C3A2D7BD3009C5E2D274104B300B2CC9C5E",
INIT_4F => X"B386AAA58001282E274104B245962B2AF86AD42F0130D335D94F06282E274104",
INIT_50 => X"B49CA3057900CA65E02A5B4DC047D319F92A082451534804B300A5C8E50C2B00",
INIT_51 => X"D534804DAE657412B3B800DC5B491FE049BE1041B800BE5B491FE049DC104100",
INIT_52 => X"B2E4482D4B0174464306B300A5D0E50C605E3A274104B3C00F864A00B2E05355",
INIT_53 => X"000185964939796A4978210F80622324CA6549784106B30000B800FB3E3FE000",
INIT_54 => X"0DF2BF00A000622A3FE00B008C45000104BBB2C845165861D85440492E13B203",
INIT_55 => X"01A001861072B000868ABE2B1BE04A6FA0000000000000000000000591AB0191",
INIT_56 => X"9BBB00AD0000014F4B020241B800005B492FE0000001504D0102410201A4AC80",
INIT_57 => X"9B4000A00068283FE0B800055B492FE0C905A00500BFE00000014F5E03024102",
INIT_58 => X"03A00301014FB800005B492FE000000150CD00A00000AE000101507104024102",
INIT_59 => X"4D0B044A0401015040050241029BBBB2F88603670094254104B2029BBB03ADC7",
INIT_5A => X"0B2500B204AA2584B2029BBB03ADC703A00301014FB800005B492FE000000150",
INIT_5B => X"51A0418004104A460000502300647FE74F0052A0029B0004984A2FE0BBA5C8A5",
INIT_5C => X"E30679740A50B3044D186104182B135E2601E106002BD8511324893A0105B2EE",
INIT_5D => X"4104B2B800EA9A33830FE04000A00068283FE0029BBBA5C865522E23EA3A091C",
INIT_5E => X"720A004FD465485D2E01181B555208285813B30000029BBBB2F8860367009425",
INIT_5F => X"459A365804B3B4E0010AB3C700A0001086504A2BE0CC10866600B2E453496A53",
INIT_60 => X"B2D000864A0000B800FE9A2E490FE000008596933A1929D725C0003E56556320",
INIT_61 => X"B4F8311A57676612B30000B000865DBE2B1BE04596B386AA0584E01A8A274104",
INIT_62 => X"0D3B9C0423404847A0658E13B300004596B386AA0598A06A204D8E7B4104B200",
INIT_63 => X"D910B300A5D0A535AD318C31F75ED718C610B30045964A5F1928922220468E03",
INIT_64 => X"000000000004B800A7463FE04056A0C000A0004D463FE000B4A8C86D57612400",
INIT_65 => X"1019F1000D65AE168108B27152A0027FE957BFE805008C01BFE8C801A0000000",
INIT_66 => X"283FE0BBB2A8FA32C000FE00536546256205C0470A3AD1052200B25951A04596",
INIT_67 => X"044A047FA310AA5352104603104C4505104A01020D03104BC803104A009B0068",
INIT_68 => X"A00003009FE000111051CE02A0047FA34156A04501A0BB04AA20DC6104B2491B",
INIT_69 => X"4AC10410610004009FE0001110510B008CBB03ADC803A0030B1051CF02A04100",
INIT_6A => X"008C01BFE8C801A0400010A2DF52A000000100B00003009FE000110451411B04",
INIT_6B => X"205C01280A3B0260D91CC0479312B3B800FFFF0110554728E0017FE957BFE805",
INIT_6C => X"01502D000000000000000000000545966A525700EA6245531E24D3102C40D724",
INIT_6D => X"0B01514904A0040E0151C903014A5903A04100A00005009FE0000901514E03A0",
INIT_6E => X"6DF456BE00B25114014A3880B201AAC0940105B26503A058008C04ADC704A004",
INIT_6F => X"00B25414014A01AAA58CB200AD0003496F32008C4596B2E597B9312E026C3AC9",
INIT_70 => X"E0BFCC9772804D4E1DBE00B24D00014A11008CE597B9312E026C3AC96DF456BE",
INIT_71 => X"97B205AAA5800128C9615953BE00B2521B054AD605A0057FA35C03A00068283F",
INIT_72 => X"0000000000000006B80003020155472AE0400001A2C000A0000129482FE0BBE5",
INIT_73 => X"B2C584B24503A06584B20B008C00040DC804A0C20302A1400201A20000000001",
INIT_74 => X"C105A0CE3F02A003022D00050D01060D08008C02052D4806A04B05A002AA0598",
INIT_75 => X"A200000000000000000000000000000000000000000AB00005984A2FE04106A0",
INIT_76 => X"017FABC10001A301060D01050D00070D05008C451B074AC907A0077FA3410401",
INIT_77 => X"4A41008C457F046148008C01090D4807046159008C4504A05F008C010A0D4800",
INIT_78 => X"A0000429482FE000060DBB08ADC80E044AF108A0080E0451F803044A3C800704",
INIT_79 => X"04A100050DC500A000000204554729E0500004A25400A0000900510004A3DE00",
INIT_7A => X"0755472AE0039579000007A27E8007A0828009A05C04A0C20401A2A5FF8CC204",
INIT_7B => X"A0000E0451CA03044A4E0AA0578007044A5C008C45040704A7C16C008C000302",
INIT_7C => X"00050D039500030D45000342C900A0000301EC472BE0D805A0ED0E044A480000",
INIT_7D => X"95CC00A0000429482FE0550004A219008C00030204C9462AE000030D45000342",
INIT_7E => X"C20141000000000200B1C106A0C105A07BFF8CC20404A10003020455472AE003",
INIT_7F => X"4D7F0161A5F465510067D8619322002B5763465D59055238192931528809B35D",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__4_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__3_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0E13B2540A014A00AD0002496F48000243C0520146A5976C3AFE5E06394104B3",
INIT_01 => X"30D32591362500B301AA2584B2521E014AA097D801B301AAA580410A804D2E67",
INIT_02 => X"0B014AC10C014AC007014A00000100A597783A264F1401B301AA2584B2A580BD",
INIT_03 => X"B303B40C076D0C019C0D419CA0415E01118FC1110111744F014F74000001B1C1",
INIT_04 => X"2417235C4611E106005FAA62AE7140218E6E4045C725DA4C0E64984AD100D310",
INIT_05 => X"510000000002B9C8252B17291844663A0B045300585D1A1BEA66242C01409446",
INIT_06 => X"C114B200B0BA00C1823FE00000B0000D0197E3000231482FE040000243020D01",
INIT_07 => X"DA4EA000000000000001000400B040F84D144E0083C100017E4F7E7DAFE4A5F8",
INIT_08 => X"E0C001A0CF11864AB1BB45961929EF500067AE06002B181BD5048D09B2C001A0",
INIT_09 => X"A3400B004A0086A34913004A0086A34000A00068283FE0B1BB00AD004536272F",
INIT_0A => X"09B2F301A07895006300000474007F16492FE0048616492FE04C807F00660086",
INIT_0B => X"41052037CC4537003E46C621AA626A04B25E969562A5F8DB28CD0C2500C95091",
INIT_0C => X"76674B0263027F0A492FE0715D8841029BBB4596B205008CB2CCD4652E4D1411",
INIT_0D => X"C928371A0033D3351978D34866006C3A2952ED0FB25B00046300647FE7044A02",
INIT_0E => X"00660086A3DB7F866600B000865D482FE00068283FE003864B7F866EB1BBB4F8",
INIT_0F => X"B2D00B004A0086A3D77F8666B1BB4596B286AA20806C3AFE5E065DE20FB2D47F",
INIT_10 => X"4A4D0301A200000000000003B000866E007FA3B1BBA5C8A50B2500B286AA2584",
INIT_11 => X"954700024A4B9001615E0201A20000000000000302ABF7BF0303A10295C40003",
INIT_12 => X"46000001B800000374000F0151E6BF0202A103000374000216492FE00C008C03",
INIT_13 => X"36272FE086AA01ADB4E00164B84CD801B386AA2584B2508C69548895C157F786",
INIT_14 => X"008C4596B202AAA580E6064D0094254104B2D501A00000000002B0BB00AD0048",
INIT_15 => X"00000000000100000006B0BB45962A22AE291B186C34D9714D0094254104B215",
INIT_16 => X"060451461B044A52062D047FA300032D017FE805008C007FE8C806014A000000",
INIT_17 => X"104AB100040543492BE0CA05016A4E03A0B100040543492BE04A05A04D03A005",
INIT_18 => X"000B01514A12014AB100040543492BE0CA05016ACE060541D205A0D503A05806",
INIT_19 => X"17182B0058491401B204AA2584B25C1B044A604EA0E306104AE703A0B1BB00AD",
INIT_1A => X"1031362FE001102D017F6E05008C01046EC805A0BBBBB2A8973618045200192B",
INIT_1B => X"9A015765D84D0E3B0105B2EF51A06F0000502300647FE7780052A07C0006A052",
INIT_1C => X"8CBBA5D045531E245353D700311A00636A42D724205C01600A3B74026C3A915D",
INIT_1D => X"61213B11034A5F0C30D34157476500B45073048D12B24000A00068283FE03F00",
INIT_1E => X"A0B000229B33830FE0058DB205008C00AA007FA34A1B004A007FA3A580010820",
INIT_1F => X"111051007C0DBB45960A19B102F01A09184000496D54424104B259047F415D52",
INIT_20 => X"01606A1B2A02B37FAA2584B2D27F04214101106100015D482FE00002009FE000",
INIT_21 => X"492FE0C002A0020110244A2BE0000000000200B00044463FE0C102A045966800",
INIT_22 => X"0100610003026FC00403250400024F000000000000000004029B4100A000025B",
INIT_23 => X"0004B8000189BE2B1BE0016F2D00000100AB0000026F00010354C0040361F53F",
INIT_24 => X"00B80000030211362AE000010055000200570003A40312015200000000000000",
INIT_25 => X"0003B80000030125362AE0000100550003A4C003A00305025200000000000003",
INIT_26 => X"66000001B1F3BF0303A103ABC40403414802036AC003A0C20301A20000000000",
INIT_27 => X"0000000300B0F73F7F0161C001A00101A300000100B8001001504A2BE0C11001",
INIT_28 => X"E53F01006100010350EE3F0500410003A403021072C0A8026202021073000000",
INIT_29 => X"41000001007AAB107A2D017B2D000001B0020B019BE312014B000000000202AB",
INIT_2A => X"B4012A3B8D0346055400292A6E015355540F37006C3A691A193B4104B2400301",
INIT_2B => X"5C00595D48616500B2DD9CA0459697520964935E0B242A5D861EC03461040A6B",
INIT_2C => X"EA384104B240030141000001B0BBA5C82563EA520B044050A2659A6200274645",
INIT_2D => X"D828202C0164585D74010108002746455C1483050A6BB4012A3B8D030124D335",
INIT_2E => X"A58431009C26D3713F00A6044D000A6BB4014105E02AF35208289302D3112C64",
INIT_2F => X"00000000000300B0BBB2DCE619C047B9312E62B20D008CB2CCAA52B24A0BEB0A",
INIT_30 => X"4A40238841B0BB0B014B02AD07008C00AD004436272FE04D0B014A582B884100",
INIT_31 => X"2704B3405D388897C10000B0BB00AD004436272FE00A008C0B014C03AD4A0B01",
INIT_32 => X"664E62874140F88641401A884100B2A46A2A191B0B78515D1A29D8050027D750",
INIT_33 => X"023E36CC3525006A2A8E790D44264F2A11B37B87A0B800779B33830FE04A7F87",
INIT_34 => X"030D6BF72C0164D3702700D9341C285763570012178E286204492553499222EA",
INIT_35 => X"DC10410000A596B387AAA580A6054A0CC128C9010A39B30CB2B2B4D971402A2D",
INIT_36 => X"403C884159BE1041459638002A3BD35C0C242E52B8046E502204B3403C884159",
INIT_37 => X"9408B35B3C538897C1700F1041459638002A3BD35C0C242E52B8046E542204B3",
INIT_38 => X"5C0C64B84CD8392304B3B2E42546861340656E1A9711B9009878C41098003E4E",
INIT_39 => X"6C523804B3593C5D8897C100B2E0C10D40656E1A970174160105B345962A3BD3",
INIT_3A => X"521804E01AAA254104B3554D88414596FE5C464D61144109000757140124D71D",
INIT_3B => X"280A274104B3A5C825299C46912E49248108B34F3D8841A5C885531324D71D6C",
INIT_3C => X"5D02788D13B3533C884162C9C1CB1095C10000A5C80507205DEE309362C04F06",
INIT_3D => X"1097C14480B44F1097C1B00098174A2FE0408B8841A5D4054FCE5C8704204D6E",
INIT_3E => X"0007001B9C08B3B2E45871202C21092B188208B34F4A10416C3C88413D805051",
INIT_3F => X"41A5C845619A362000D95CE20FB3A5C84516B24885320628594F4E020664583F",
INIT_40 => X"A5D4854DAE654A52185C1424D345E704405D8600B46001648D39170AB35F3C88",
INIT_41 => X"01512F2E6B461DC014012858532D04B34D00388841B0009A174A2FE0498B8841",
INIT_42 => X"04E00CE01A2A22251082052A3B8D034965D319B50431000A6BB401D138934614",
INIT_43 => X"222B8897C1A5C8C537391A8A033E2A525DB92B602AEA400164584B005F6A7214",
INIT_44 => X"984A1FE0BBB2F4A2048053693A3C04B2B800CB5B491FE0490BEB0A604F104177",
INIT_45 => X"00196B5204B3401C88414596384CE106202B6C0580530D280A27610BB3B800EB",
INIT_46 => X"053000313A5C04B3592D8841B80099174A2FE0498B8841000045966C3A903E49",
INIT_47 => X"0264585D740101280A7B4104B3573C88414596933A1929D725C0007E39485578",
INIT_48 => X"2C01484A61004388465235201801606A3A3504B3404D8841A5C8052BEA66204C",
INIT_49 => X"49406DCA45EA1C0164B84C3411B3401E1F208895C1000045966C3A574B574B49",
INIT_4A => X"4088410000000000000300A5D04545C760D854D2390160D319796A5406015445",
INIT_4B => X"0D02862D86872D12880D87022D543B8841B0BB00AD004736272FE04C228841C0",
INIT_4C => X"4101030DC502A087022D0B008C00030D86022D4BED8641C6EE86411C008C0003",
INIT_4D => X"7FA302862D05008C02872DC803A000025D3C2FE0485D128897C1ED020D51EE02",
INIT_4E => X"0102666D87A0C9870161F401A0F00003A0F4005D128897C100010DC51B014A01",
INIT_4F => X"2FE0BB4596B201AA05842A009266991E205C01283125BA02067074160105B2E9",
INIT_50 => X"00B287AAA58041056C00181A2A662104B2ECEC8741F087A0B001866E00865D3C",
INIT_51 => X"EC0A46007FEC26B800025D3C2FE0BBB2F85165C6254A4A0E602A1B9756662B26",
INIT_52 => X"532704B3ECED0EDA00EC92B800EC984A1FE0BBB2F4A204404539532704B2D50B",
INIT_53 => X"F82A6C3A8B043500B83A11672104B345965765862B0144512F8053B304404539",
INIT_54 => X"0D1F0160D534575584052A66991E205C010AB36587A0685D88416CEC86464596",
INIT_55 => X"96F82A6C3A8B043500B83A11672104B3A5C825192A63D30167000A1A19245153",
INIT_56 => X"0105B2E301A000ED5D3C1FE05500313F8897C14596FE6640216E12B3CB03A045",
INIT_57 => X"04B2B001ED2EBB4596B201AA05842A009266991E205C01283125BA0206707416",
INIT_58 => X"BB45963E2AD9384949D2015865E652D56CCA04E052342E202C0160313A156721",
INIT_59 => X"B41A5B190160311A1C0452005835D84415672104B2407F8841B800ED5D3C1FE0",
INIT_5A => X"01430D502B238897C100B800ED5D3C1FE0BBA5C8C5472A1B2E29523A002BD95C",
INIT_5B => X"783137CC45B8048053693A3C04B36743A06A388841B800BD9BA89BEBFD4A10E0",
INIT_5C => X"1041548919228895C1A5C8C55F792A8053311A2B008D69742A57286204D73C06",
INIT_5D => X"B359CB104105A80A3B4204B240398841B0001D384A1FE0B0001E384A1FE049CB",
INIT_5E => X"0226092B580164A671B3B2E4585D74010660E91A9C663C00465D065C46450818",
INIT_5F => X"933926003E269A46E02AEA01383BD7553804B2616F88410000A5C8652A0D650E",
INIT_60 => X"450A670E78934AEA2A0804C0479312B35D3A88417CAB007C0DBBB2E8D403EA52",
INIT_61 => X"1019391B27380270B411B361E9864165132A8897C1459619296B29C04F260E60",
INIT_62 => X"2D0128F118530352295804B3A5963823EA1D1444C65D2A1BB205795CAE62C000",
INIT_63 => X"004436272FE0CC42A0796988410000B2E0D95DAE624061AA652D0019195765D3",
INIT_64 => X"2029D819B704202B101B2704B300E3984A1FE001420DE4E50EE2E30EB0BB00AD",
INIT_65 => X"B0BB00AD004436272FE04C42A05900548841A5C8252FA6612028015434036105",
INIT_66 => X"52395307042B00495D8A53B104202B101B2704B200E5984A1FE0E2E50EE4E30E",
INIT_67 => X"157074168108B24152A0521031362FE0C152A000420DBB459679190D03410540",
INIT_68 => X"2A6D000164A604202B101B2704B359E58741C6E58641B0BBB2C0C8440734283B",
INIT_69 => X"C047EA6A486125008A192804B340E5E38697C1405D8841B2CCCE3408042A0069",
INIT_6A => X"7CAB007C0D0006EB4E1FE04D6F884100B2CCCE34480AD701610520295365D82C",
INIT_6B => X"6345356007A648AE010D19EA264104B35D107F00ABC100BD93405D132A8895C1",
INIT_6C => X"32201B2704B2BB0004EB4E1FE00000B800C94E3FE0A5C8854D2E3A0A01410A00",
INIT_6D => X"C84516B278861B2700382F2E1A0140484D2428012C4B5F08030178E704001FE6",
INIT_6E => X"0F008C45010104000001B00044463FE00000005B4927E0004136272FE0BBBBB2",
INIT_6F => X"11B3C0A1A0457F5A108FC1406D88410000B0BBEEFF8CBBB4D44A718B000000B2",
INIT_70 => X"4978C10420530D78576D2500312A2704B3595D88410000A5C8854D340D814D2E",
INIT_71 => X"5EFA00B287AA2584B25E1A874A4C8087A050006D8841CB6E8841A5C8652AD064",
INIT_72 => X"CD0C2500312A2704B353018741B800875D3C2FE0BBB2A44A6A7852A804260078",
INIT_73 => X"61884145960A4F2A4FCE0C2500312A07043300D9282D04B3B2B4485379052053",
INIT_74 => X"E0BBB2A42A1B9756662B25180144511D2000385214652104B200865D3C2FE06E",
INIT_75 => X"C82877052053CD0C2500312A2704B3406D8841B800725C3FE00000725C392A07",
INIT_76 => X"A5C8252953553409291801242A5D861E2E009853693A3C04B35B2B884100B2B4",
INIT_77 => X"3304B3405D884100004596535514609C26D3712000D028F7244104B3402A8841",
INIT_78 => X"4100B2A46A53525D497861049752090437004925491DD2013E564A252360D119",
INIT_79 => X"3B100437384104B29300030141000001B2C0C85C0804356463254104B3402288",
INIT_7A => X"5D20295803532907062B180228F118B90C2C2858530D28D9351C042A00533528",
INIT_7B => X"0454006105002746457614830589524B055238D95CA62AB702610AC047792A48",
INIT_7C => X"274645C02B533A0D01F01AA90C2C24D7705573014C4A614938220A005E2601C6",
INIT_7D => X"62B3B2CCAA52B3470BEB0A25C40170344D8E7F0118255402042B18014C9C2600",
INIT_7E => X"401E8841B80017384A1FE0494986414D1E884140010141B2DCE619C047B9312E",
INIT_7F => X"3688414001014100000100A5C8657234710160D7191903743A0105B340498641",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__3_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Mem_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__15_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"8553F71A87000128C961D311B240B1864140228841CA151D8697C148898841D4",
INIT_01 => X"4D1DC047C75CB42BD30158613422690061049C5ED71C20005765531D0160861C",
INIT_02 => X"9A4A974E4A0F2500C928CD286204F01AA904791C01245353D7102C68D403693A",
INIT_03 => X"786A175C2A4F0A01383BA0319A5E2D132C642E023E668D39F70C615E6A1B0860",
INIT_04 => X"602A8952FC07C0140148465D19030130D34DD3549830411AEA661828C971C000",
INIT_05 => X"2C446A4E3A03F01A0918400038192A720218204DD42BC70423282C39F764942E",
INIT_06 => X"820593399806C0146104D719205C0130D36586466B048A25EE1E20006A53C710",
INIT_07 => X"49652A56922230008A25EE1E4F54C3041903B471407920468600A0173819EA12",
INIT_08 => X"2664831301242A632A472306405D3A4F6A2706609A46EE2AD504201BEA32C000",
INIT_09 => X"63D72D2000B2C90000A0000800490001001049DD2A63464241042C28CC5C9A22",
INIT_0A => X"097200181B15508D030A532D132C788C46EE6600129750E41320280164D75420",
INIT_0B => X"65465D0C4C6A2B7A000A1AF92A696A2B00495DA62AB7260264584B4031C95DE7",
INIT_0C => X"1BF7180144D141980420632A033E2A576D0A03313A1C1C03285767536DC90057",
INIT_0D => X"12947C24172D005869D3659322C033343A3703905C84129F04E114A750C55F6A",
INIT_0E => X"0049652A56922225180164E57FF45077112A00E91ADF712404A0178E380440E4",
INIT_0F => X"008CBB2597B25C2A63461252286C6A89040174C5118E380440E412947C241737",
INIT_10 => X"E0BBA59C4516EA3A552A640D57255313201BEA322404A017905C84129F00B220",
INIT_11 => X"4A1FE04022884100B2F8DB28CD0C25242304B3402B238897C100B80000E6361F",
INIT_12 => X"66013E2A57230A170128D820C037955E3904B340C28641405D884100B8001D38",
INIT_13 => X"3B110437384104B21F01030141000000000000034596311A1C042B00494D2A63",
INIT_14 => X"020480668405B24A809FA025E346016105C01BFC523401A6042830010D804D6E",
INIT_15 => X"9752094C2A51940329527A5C0130D34DAA522029D5349817B852117908182550",
INIT_16 => X"008CA58C814DEE2A392B1120AE6594018A4DE66618289262254401289B1E6604",
INIT_17 => X"1C042B006C3A5765594500392D530C286C1A37632D24034C2A5194036604B233",
INIT_18 => X"40022D23A8D820C037955E1918B26584593718242A3A6626620536446104192B",
INIT_19 => X"9426A01A37035355540F40250E2B0730D3791130FA02C604B2600BB70AE402A0",
INIT_1A => X"B70A37008CA5C8252B6A110164260DA01A37035D00C604B2D802A050008CB2DC",
INIT_1B => X"2AEE523400C604B21D008CB2E44A2D2400D9240354E666602A956AC304B2580B",
INIT_1C => X"128841CA5D884140060141B0BB459668004105E02A792A080437004C5F201A79",
INIT_1D => X"00B1000031481FE011004F7400F0513FE00086E0512FE048C2864640C2874140",
INIT_1E => X"EBFF8CC20202A10002E0512FE0480002A203024BC102A0C20201A20000000002",
INIT_1F => X"F0512FE0480002A203000374000C025103AB4402A0C20201A200000000C20003",
INIT_20 => X"C11041512B238897C1B000B72BBE2B17E04A6988410000E4FF8CC20202A10002",
INIT_21 => X"39171840295804B35F0BB70A68C110416C518841B800E39BCD9B86FD4A20E04D",
INIT_22 => X"97C140481041B2F4020AB34596182B135E26010230D3255321582551003E2B10",
INIT_23 => X"0BB70A5B238841A5C8456DF41833004941884625242304B3D30BB70A572B8588",
INIT_24 => X"36272FE0402B238897C145961822341A01600A5311252304B30BB70C03B70CD7",
INIT_25 => X"1A312A0854D2242600F01A091837384104B35D00030141000001B0BB00AD0044",
INIT_26 => X"6B14036105C01B3C72E622C01861042D5F74720178862BCC60D8543D00A605E0",
INIT_27 => X"172106A04AE602D1644A0255291903460540523953070425500204605284052D",
INIT_28 => X"D55C3904B203B70B0BB70CC003B70A400BB70A4002014145962A1EE6482E2253",
INIT_29 => X"A5C8253B804DEE5EE6006A524A52185C46352718610459371860AA61E6226900",
INIT_2A => X"8CA5CC9C26B24ACB1041A58038192A025E4DD2352804B2403888410000B0BBBB",
INIT_2B => X"B2DF017FA2000001A5C84545C71CD24508609052D1042324D770B3A5EAB20500",
INIT_2C => X"460101A1B1BB459646250E24E600A6042029691A8D173E57520155036C3A9411",
INIT_2D => X"A6712D3402541A648A254104B2CB9BCB9B03B70CC70BB70A4D7FA426D10001A1",
INIT_2E => X"00D55C3904B2489B440BB70ADB40A000B1BB45966C3AFE5E0601EA6245531E64",
INIT_2F => X"440069884100B1BBB2F88603670094254104B2B100B7984A1FE0BBB2F4A20469",
INIT_30 => X"6C3AFE6637286204B34596B3C540A0A5E4CB452B007E1BAA19A30480693704B2",
INIT_31 => X"253BA065464DEA003E3BD7449A29F73A7A0049212E53130627640328D0642B00",
INIT_32 => X"3A5B5D1564AA5E060101246A531230D36DA611B3ED40A0800058658897C1A5C8",
INIT_33 => X"465D0C18A0658E13B24596D319CC6403289B4A2B40230F204D6E1D61043E629A",
INIT_34 => X"466DEA0E010D20280128C961404D740520299B4A25004C5F200C215F742D0A64",
INIT_35 => X"984A1FE007B70CBBA5C8E5523401D55C197402182A4803013E633A010130D345",
INIT_36 => X"4978C104C06F4635C0474A2A3777AA0480693704B35D5D884140AB01400D00B7",
INIT_37 => X"691704A065464D57255313B349800BB70A4E0040A05200518841B2A4CA5DD720",
INIT_38 => X"044C5F2028015C6A5E14010154F4262700D8102C5C9426A01A37035D00A60480",
INIT_39 => X"A04021884145965C397B062029D1286852E806861940219316210DA01A370361",
INIT_3A => X"78D95D266A4C5DD7690328C865741E6104D9612700D810B343800BB70A480040",
INIT_3B => X"63270C4145C764972E92225327420F2D035735D95C8405D9012D1B6A5E2A4D1A",
INIT_3C => X"AA5E0601C83146020660B8646E0F27000A53B56A780BB34596D319CC00551B21",
INIT_3D => X"100266000000000200B8007271DC5317E000B800D9DADC5317E0409DA000B5E4",
INIT_3E => X"B245960D19EA1241056C6403606C3A1C03B302AA2584B258020166405D884140",
INIT_3F => X"000100B0BB4596D92D410A2045B42541042C64B4714565AE714600B201AA2584",
INIT_40 => X"B2E4D84566522E1BF82A7B5208182A000D691264B84CD8612204B2636F884100",
INIT_41 => X"DA0B4C8000A0004B21271FE0560010DA26C0D9DA06A2000101417CAB007C0DBB",
INIT_42 => X"BA190124EA2A6C1A2344915E3904B34110D926EC9B0BD953E3D9DA0E1DDA0C0E",
INIT_43 => X"6C054075460F302CC10640358405935646714200F82A9B22EA0E2129D938D149",
INIT_44 => X"0D2129F21AD8252344915E3904B2039C0BD953E34010D926B2E8D4370124D35D",
INIT_45 => X"289A4D3403D15C3A679A01E106402D2E0A620A3C54235CF45E2A5F0160577114",
INIT_46 => X"AB019D0D1DDA0B0EDA0C10DA2E4BD9DA0654020141B0BB45963846F466202801",
INIT_47 => X"9DAB019D0D0E9C0BD953E31DDA0B0EDA0C10DA2E4BD9DA0602D90C5D0301419D",
INIT_48 => X"006C3A5263EA023E42C8697604F83A19632204B202D90B6710D9265900040141",
INIT_49 => X"0B5466DA061E008C249C0BD953E34BD9DA06BB45960A4D2663804D2E37CC2DC0",
INIT_4A => X"510501419DAB009D0D3B9C0BD953E308008C249C0BD953E3D9DA0E1DDA0C0EDA",
INIT_4B => X"97C1B0BB00AD000BD9114A3888414001A0B0007C0D02D90B4000212300647FE7",
INIT_4C => X"BC017F3F8897C100D96C801FE023025D582A8895C1CAD98741C686A0497F3F88",
INIT_4D => X"0F61520E6B6B52E8062019AA090260AA21D95C08632204B26F7FDA2673DA8641",
INIT_4E => X"302C4204B262DAD98697C1B0D9DA0E02D90BBBA5C845750604002BD064602A2D",
INIT_4F => X"B26A7F8841A5C8C5470A3A716A460067186104195F6E01B386AA0584202B6C05",
INIT_50 => X"0160AA21D92023242A1BD32597520878F118F01A525D2500B4712344915E3904",
INIT_51 => X"0E19970D2169F456C047576DF40A2500B4712344915E3904B229008C86AAA580",
INIT_52 => X"E06600DA6EA98695C16E0000142300647FE725AF8E010160B92A0819C0475853",
INIT_53 => X"CA2540352344915E195C945684053E3A974DBA650360D9282600B200865D3C2F",
INIT_54 => X"18183758013B0960D820D72042180128CC34F7525235201AF32A793A7A4C0160",
INIT_55 => X"9D0D0002009FE00011D91100D95D3C1FE0BBA5C885510B40C844075C2A636E3A",
INIT_56 => X"1B186453495402610A804D4E1D2324D300B210866E5E00DA6EA98695C19DAB01",
INIT_57 => X"80C1042344F4669322E052B446030B200CE10E2C40C81C79009853B76523242A",
INIT_58 => X"2529D828B1029052F10A002B3401AA112C5C94460B042B0038466601B286AAA5",
INIT_59 => X"26036C3AD94C4E3A17612E0119531204804D6E1BED0A2600B2B002D90BBBA5C8",
INIT_5A => X"7D5D588897C1B800865D3C2FE0BBA5C8253B006746013E467A292A3223602A63",
INIT_5B => X"2B13404847E02A392B87640530D365535F6C040A198B043700383B15632204B3",
INIT_5C => X"B3402A8841A5C8254F0A2106609A5EE65CE6005735D95CC05C016445492E03B9",
INIT_5D => X"021403FE2A5B11B3774D8841B2A857675831C04FBA12016406608D6926622204",
INIT_5E => X"08370CC15F264F4A3AB14A144D3A0C2330D33559491403D81B180B200053658B",
INIT_5F => X"7AE01AAA25010B200C010FB340428841C09DA0A5C845696C521944E66A396B4C",
INIT_60 => X"3A1504804DEE5C3A632E01D311B267585D8897C1403EA0C00BAE0A000045969A",
INIT_61 => X"DB281104A0658E13B21E008CBBB2A42A1A6A2BB7046A006604586D46452A002A",
INIT_62 => X"B35725884100B1013E0D07AE0CBB45964945466DEA16410DC00C21299B4A002B",
INIT_63 => X"3C2FE00002563FE0641C8841A5C80507002BDB2811340515A94C2516AE380105",
INIT_64 => X"04B26A278841B8003F9C33830FE0B2CC571F002BDB283104B34D10866600865D",
INIT_65 => X"BB4596182B121840654E5B804D0E1A7204696AF41A002BDB2811044045196B57",
INIT_66 => X"0002563FE0403EA0BBA5C8454D3411B24A5888415B585D8897C1B00002563FE0",
INIT_67 => X"00586D46452A002A3A1504A065464D57255313B3403EA040518841B1415D8841",
INIT_68 => X"000A4DB4046A006104586D464520000A1B2A2AF704001B84056C3AD95C0C1825",
INIT_69 => X"0141B007AE0B403EA04902014100000100B2F0CA6D33004945462193223718CC",
INIT_6A => X"1C0130D3255353F76A1864585D7401A6052330D35D4645081837384104B24003",
INIT_6B => X"527A140105B2BB650BAE0AA5C8A5659A62002746455C14830558250E03311A52",
INIT_6C => X"BBDE3EA021008CA5C805636A42D72440006C3A692A082B69046C3AD95C0C4CAA",
INIT_6D => X"000100B0BB4596696AF432200002246A2A191B0B78515D1A29580DC0140105B2",
INIT_6E => X"8105EA1B1204E01A6A02687C011837384104B240030141B007AE0C4602014100",
INIT_6F => X"C710B2640BAE0ABBB2F8D94D0E391B28D9384949D201E1066F003E638E672E20",
INIT_70 => X"A040008CA5C8653A804DEE6AB402B9312E4E1A37410D602A956AA30427006A53",
INIT_71 => X"00A60427006A53C710B229008CA5C8854D2E1B9701A60427006A53C710B2D63D",
INIT_72 => X"00B0BBA5C805223402584DF460985E8817691ABC44514318182D00494188466A",
INIT_73 => X"2C04B3003D0D52391041694E8841B0007AAE85BE2B15E04B7A87414F2B884100",
INIT_74 => X"858841B2A8C9614F4C210F002234264104B3408F1041B2A40A2234160128D95C",
INIT_75 => X"964941884653170128D95C2C04B3013D0D547A8741583910414900AE86414E00",
INIT_76 => X"6A27680311B24596384C0140884620000D19EA264104B3537A8741578F104145",
INIT_77 => X"C14596105111040022AE264104B34F5C8841A596B387AAC0B4410DC000105171",
INIT_78 => X"9100AEFD4A18E04D9C3FE806008C499C3FE8494A104155803DA064002B238897",
INIT_79 => X"6105930238466601586D46452A002A3AB50CB26A3EA0ED4A1041750BAE0A0011",
INIT_7A => X"2304B3B014390CB014390B10902E013E0DBB4596696AF432202CC1042019AA11",
INIT_7B => X"04356463018308B351140043000F865140AE8741401288414596494188462528",
INIT_7C => X"182B135E260101086A00A106002B9401B386AA2584B239864E45966C3AD95C0C",
INIT_7D => X"202A736A19042B005503101907648A2D0128F11849004304B20045969C46EA00",
INIT_7E => X"44451041BBBBA5C8050D20776A02610500678A65034CAA7135006C3A9439E104",
INIT_7F => X"10B2407F6E263F005D884100A79B403810413A9B443C1041429B443F1041439B",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__15_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__15\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(15),
I3 => addra(16),
I4 => addra(14),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__15_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem_blk_mem_gen_prim_width is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Mem_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end Mem_blk_mem_gen_prim_width;
architecture STRUCTURE of Mem_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.Mem_blk_mem_gen_prim_wrapper_init
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized10\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized11\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized12\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized12\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized13\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized13\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized14\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized14\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized15\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized15\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized15\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized16\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized16\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized17\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized17\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized18\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized18\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized19\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized19\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized20\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized20\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized21\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized21\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized21\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized22\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized22\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized22\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized22\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized22\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized23\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized23\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized23\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized23\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized23\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized24\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized24\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized24\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized24\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized24\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized25\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized25\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized25\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized25\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized25\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized26\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized26\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized26\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized26\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized26\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized27\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized27\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized27\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized27\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized27\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized28\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized28\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized28\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized28\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized28\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized29\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized29\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized29\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized29\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized29\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized30\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized30\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized30\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized30\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized30\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized4\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized5\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized6\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized7\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized8\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_blk_mem_gen_prim_width__parameterized9\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \Mem_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \Mem_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\Mem_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Mem_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end Mem_blk_mem_gen_generic_cstr;
architecture STRUCTURE of Mem_blk_mem_gen_generic_cstr is
signal ram_douta : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \ramloop[10].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[24].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[24].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[24].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[24].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[24].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[24].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[24].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[24].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[25].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[25].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[25].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[25].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[25].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[25].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[25].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[25].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[26].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[26].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[26].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[26].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[26].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[26].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[26].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[26].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[27].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[27].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[27].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[27].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[27].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[27].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[27].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[27].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[28].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[28].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[28].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[28].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[28].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[28].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[28].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[28].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[29].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[29].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[29].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[29].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[29].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[29].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[29].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[29].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[30].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[30].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[30].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[30].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[30].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[30].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[30].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[30].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[31].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[31].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[31].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[31].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[31].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[31].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[31].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[31].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_7\ : STD_LOGIC;
begin
\has_mux_a.A\: entity work.Mem_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[2].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[2].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[2].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[2].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[2].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[2].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[1].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[1].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[1].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[1].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7 downto 0) => ram_douta(7 downto 0),
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(7) => \ramloop[15].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(6) => \ramloop[15].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(5) => \ramloop[15].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(4) => \ramloop[15].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(3) => \ramloop[15].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(2) => \ramloop[15].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(1) => \ramloop[15].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(0) => \ramloop[15].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(7) => \ramloop[14].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(6) => \ramloop[14].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(5) => \ramloop[14].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(4) => \ramloop[14].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(3) => \ramloop[14].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(2) => \ramloop[14].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(1) => \ramloop[14].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(0) => \ramloop[14].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(7) => \ramloop[13].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(6) => \ramloop[13].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(5) => \ramloop[13].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(4) => \ramloop[13].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(3) => \ramloop[13].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(2) => \ramloop[13].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(1) => \ramloop[13].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(0) => \ramloop[13].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(7) => \ramloop[12].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(6) => \ramloop[12].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(5) => \ramloop[12].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(4) => \ramloop[12].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(3) => \ramloop[12].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(2) => \ramloop[12].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(1) => \ramloop[12].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(0) => \ramloop[12].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(7) => \ramloop[19].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(6) => \ramloop[19].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(5) => \ramloop[19].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(4) => \ramloop[19].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(3) => \ramloop[19].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(2) => \ramloop[19].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(1) => \ramloop[19].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(0) => \ramloop[19].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(7) => \ramloop[18].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(6) => \ramloop[18].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(5) => \ramloop[18].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(4) => \ramloop[18].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(3) => \ramloop[18].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(2) => \ramloop[18].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(1) => \ramloop[18].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(0) => \ramloop[18].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(7) => \ramloop[17].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(6) => \ramloop[17].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(5) => \ramloop[17].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(4) => \ramloop[17].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(3) => \ramloop[17].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(2) => \ramloop[17].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(1) => \ramloop[17].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(0) => \ramloop[17].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(7) => \ramloop[16].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(6) => \ramloop[16].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(5) => \ramloop[16].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(4) => \ramloop[16].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(3) => \ramloop[16].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(2) => \ramloop[16].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(1) => \ramloop[16].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(0) => \ramloop[16].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(7) => \ramloop[23].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(6) => \ramloop[23].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(5) => \ramloop[23].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(4) => \ramloop[23].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(3) => \ramloop[23].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(2) => \ramloop[23].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(1) => \ramloop[23].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(0) => \ramloop[23].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(7) => \ramloop[22].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(6) => \ramloop[22].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(5) => \ramloop[22].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(4) => \ramloop[22].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(3) => \ramloop[22].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(2) => \ramloop[22].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(1) => \ramloop[22].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(0) => \ramloop[22].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6) => \ramloop[7].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5) => \ramloop[7].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4) => \ramloop[7].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3) => \ramloop[7].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2) => \ramloop[7].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1) => \ramloop[7].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[7].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(7) => \ramloop[21].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(6) => \ramloop[21].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(5) => \ramloop[21].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(4) => \ramloop[21].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(3) => \ramloop[21].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(2) => \ramloop[21].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(1) => \ramloop[21].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(0) => \ramloop[21].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(7) => \ramloop[20].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(6) => \ramloop[20].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(5) => \ramloop[20].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(4) => \ramloop[20].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(3) => \ramloop[20].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(2) => \ramloop[20].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(1) => \ramloop[20].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(0) => \ramloop[20].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(7) => \ramloop[27].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(6) => \ramloop[27].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(5) => \ramloop[27].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(4) => \ramloop[27].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(3) => \ramloop[27].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(2) => \ramloop[27].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(1) => \ramloop[27].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(0) => \ramloop[27].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(7) => \ramloop[26].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(6) => \ramloop[26].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(5) => \ramloop[26].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(4) => \ramloop[26].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(3) => \ramloop[26].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(2) => \ramloop[26].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(1) => \ramloop[26].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(0) => \ramloop[26].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(7) => \ramloop[25].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(6) => \ramloop[25].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(5) => \ramloop[25].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(4) => \ramloop[25].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(3) => \ramloop[25].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(2) => \ramloop[25].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(1) => \ramloop[25].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(0) => \ramloop[25].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(7) => \ramloop[24].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(6) => \ramloop[24].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(5) => \ramloop[24].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(4) => \ramloop[24].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(3) => \ramloop[24].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(2) => \ramloop[24].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(1) => \ramloop[24].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(0) => \ramloop[24].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(7) => \ramloop[31].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(6) => \ramloop[31].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(5) => \ramloop[31].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(4) => \ramloop[31].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(3) => \ramloop[31].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(2) => \ramloop[31].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(1) => \ramloop[31].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(0) => \ramloop[31].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(7) => \ramloop[30].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(6) => \ramloop[30].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(5) => \ramloop[30].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(4) => \ramloop[30].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(3) => \ramloop[30].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(2) => \ramloop[30].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(1) => \ramloop[30].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(0) => \ramloop[30].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(7) => \ramloop[29].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(6) => \ramloop[29].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(5) => \ramloop[29].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(4) => \ramloop[29].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(3) => \ramloop[29].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(2) => \ramloop[29].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(1) => \ramloop[29].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(0) => \ramloop[29].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(7) => \ramloop[28].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(6) => \ramloop[28].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(5) => \ramloop[28].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(4) => \ramloop[28].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(3) => \ramloop[28].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(2) => \ramloop[28].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(1) => \ramloop[28].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(0) => \ramloop[28].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(7) => \ramloop[11].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(6) => \ramloop[11].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(5) => \ramloop[11].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(4) => \ramloop[11].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(3) => \ramloop[11].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(2) => \ramloop[11].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(1) => \ramloop[11].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(0) => \ramloop[11].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(7) => \ramloop[10].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(6) => \ramloop[10].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(5) => \ramloop[10].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(4) => \ramloop[10].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(3) => \ramloop[10].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(2) => \ramloop[10].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(1) => \ramloop[10].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(0) => \ramloop[10].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(7) => \ramloop[9].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(6) => \ramloop[9].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(5) => \ramloop[9].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(4) => \ramloop[9].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(3) => \ramloop[9].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(2) => \ramloop[9].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(1) => \ramloop[9].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(0) => \ramloop[9].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(7) => \ramloop[8].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(6) => \ramloop[8].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(5) => \ramloop[8].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(4) => \ramloop[8].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(3) => \ramloop[8].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(2) => \ramloop[8].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(1) => \ramloop[8].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(0) => \ramloop[8].ram.r_n_7\,
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
addra(4 downto 0) => addra(16 downto 12),
clka => clka,
douta(7 downto 0) => douta(7 downto 0),
ena => ena
);
\ramloop[0].ram.r\: entity work.Mem_blk_mem_gen_prim_width
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7 downto 0) => ram_douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
\ramloop[10].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized9\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[10].ram.r_n_0\,
\douta[7]\(6) => \ramloop[10].ram.r_n_1\,
\douta[7]\(5) => \ramloop[10].ram.r_n_2\,
\douta[7]\(4) => \ramloop[10].ram.r_n_3\,
\douta[7]\(3) => \ramloop[10].ram.r_n_4\,
\douta[7]\(2) => \ramloop[10].ram.r_n_5\,
\douta[7]\(1) => \ramloop[10].ram.r_n_6\,
\douta[7]\(0) => \ramloop[10].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[11].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized10\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[11].ram.r_n_0\,
\douta[7]\(6) => \ramloop[11].ram.r_n_1\,
\douta[7]\(5) => \ramloop[11].ram.r_n_2\,
\douta[7]\(4) => \ramloop[11].ram.r_n_3\,
\douta[7]\(3) => \ramloop[11].ram.r_n_4\,
\douta[7]\(2) => \ramloop[11].ram.r_n_5\,
\douta[7]\(1) => \ramloop[11].ram.r_n_6\,
\douta[7]\(0) => \ramloop[11].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[12].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized11\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[12].ram.r_n_0\,
\douta[7]\(6) => \ramloop[12].ram.r_n_1\,
\douta[7]\(5) => \ramloop[12].ram.r_n_2\,
\douta[7]\(4) => \ramloop[12].ram.r_n_3\,
\douta[7]\(3) => \ramloop[12].ram.r_n_4\,
\douta[7]\(2) => \ramloop[12].ram.r_n_5\,
\douta[7]\(1) => \ramloop[12].ram.r_n_6\,
\douta[7]\(0) => \ramloop[12].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[13].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized12\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[13].ram.r_n_0\,
\douta[7]\(6) => \ramloop[13].ram.r_n_1\,
\douta[7]\(5) => \ramloop[13].ram.r_n_2\,
\douta[7]\(4) => \ramloop[13].ram.r_n_3\,
\douta[7]\(3) => \ramloop[13].ram.r_n_4\,
\douta[7]\(2) => \ramloop[13].ram.r_n_5\,
\douta[7]\(1) => \ramloop[13].ram.r_n_6\,
\douta[7]\(0) => \ramloop[13].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[14].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized13\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[14].ram.r_n_0\,
\douta[7]\(6) => \ramloop[14].ram.r_n_1\,
\douta[7]\(5) => \ramloop[14].ram.r_n_2\,
\douta[7]\(4) => \ramloop[14].ram.r_n_3\,
\douta[7]\(3) => \ramloop[14].ram.r_n_4\,
\douta[7]\(2) => \ramloop[14].ram.r_n_5\,
\douta[7]\(1) => \ramloop[14].ram.r_n_6\,
\douta[7]\(0) => \ramloop[14].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[15].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized14\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[15].ram.r_n_0\,
\douta[7]\(6) => \ramloop[15].ram.r_n_1\,
\douta[7]\(5) => \ramloop[15].ram.r_n_2\,
\douta[7]\(4) => \ramloop[15].ram.r_n_3\,
\douta[7]\(3) => \ramloop[15].ram.r_n_4\,
\douta[7]\(2) => \ramloop[15].ram.r_n_5\,
\douta[7]\(1) => \ramloop[15].ram.r_n_6\,
\douta[7]\(0) => \ramloop[15].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[16].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized15\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[16].ram.r_n_0\,
\douta[7]\(6) => \ramloop[16].ram.r_n_1\,
\douta[7]\(5) => \ramloop[16].ram.r_n_2\,
\douta[7]\(4) => \ramloop[16].ram.r_n_3\,
\douta[7]\(3) => \ramloop[16].ram.r_n_4\,
\douta[7]\(2) => \ramloop[16].ram.r_n_5\,
\douta[7]\(1) => \ramloop[16].ram.r_n_6\,
\douta[7]\(0) => \ramloop[16].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[17].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized16\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[17].ram.r_n_0\,
\douta[7]\(6) => \ramloop[17].ram.r_n_1\,
\douta[7]\(5) => \ramloop[17].ram.r_n_2\,
\douta[7]\(4) => \ramloop[17].ram.r_n_3\,
\douta[7]\(3) => \ramloop[17].ram.r_n_4\,
\douta[7]\(2) => \ramloop[17].ram.r_n_5\,
\douta[7]\(1) => \ramloop[17].ram.r_n_6\,
\douta[7]\(0) => \ramloop[17].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[18].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized17\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[18].ram.r_n_0\,
\douta[7]\(6) => \ramloop[18].ram.r_n_1\,
\douta[7]\(5) => \ramloop[18].ram.r_n_2\,
\douta[7]\(4) => \ramloop[18].ram.r_n_3\,
\douta[7]\(3) => \ramloop[18].ram.r_n_4\,
\douta[7]\(2) => \ramloop[18].ram.r_n_5\,
\douta[7]\(1) => \ramloop[18].ram.r_n_6\,
\douta[7]\(0) => \ramloop[18].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[19].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized18\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[19].ram.r_n_0\,
\douta[7]\(6) => \ramloop[19].ram.r_n_1\,
\douta[7]\(5) => \ramloop[19].ram.r_n_2\,
\douta[7]\(4) => \ramloop[19].ram.r_n_3\,
\douta[7]\(3) => \ramloop[19].ram.r_n_4\,
\douta[7]\(2) => \ramloop[19].ram.r_n_5\,
\douta[7]\(1) => \ramloop[19].ram.r_n_6\,
\douta[7]\(0) => \ramloop[19].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized0\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[1].ram.r_n_0\,
\douta[7]\(6) => \ramloop[1].ram.r_n_1\,
\douta[7]\(5) => \ramloop[1].ram.r_n_2\,
\douta[7]\(4) => \ramloop[1].ram.r_n_3\,
\douta[7]\(3) => \ramloop[1].ram.r_n_4\,
\douta[7]\(2) => \ramloop[1].ram.r_n_5\,
\douta[7]\(1) => \ramloop[1].ram.r_n_6\,
\douta[7]\(0) => \ramloop[1].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[20].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized19\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[20].ram.r_n_0\,
\douta[7]\(6) => \ramloop[20].ram.r_n_1\,
\douta[7]\(5) => \ramloop[20].ram.r_n_2\,
\douta[7]\(4) => \ramloop[20].ram.r_n_3\,
\douta[7]\(3) => \ramloop[20].ram.r_n_4\,
\douta[7]\(2) => \ramloop[20].ram.r_n_5\,
\douta[7]\(1) => \ramloop[20].ram.r_n_6\,
\douta[7]\(0) => \ramloop[20].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[21].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized20\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[21].ram.r_n_0\,
\douta[7]\(6) => \ramloop[21].ram.r_n_1\,
\douta[7]\(5) => \ramloop[21].ram.r_n_2\,
\douta[7]\(4) => \ramloop[21].ram.r_n_3\,
\douta[7]\(3) => \ramloop[21].ram.r_n_4\,
\douta[7]\(2) => \ramloop[21].ram.r_n_5\,
\douta[7]\(1) => \ramloop[21].ram.r_n_6\,
\douta[7]\(0) => \ramloop[21].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[22].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized21\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[22].ram.r_n_0\,
\douta[7]\(6) => \ramloop[22].ram.r_n_1\,
\douta[7]\(5) => \ramloop[22].ram.r_n_2\,
\douta[7]\(4) => \ramloop[22].ram.r_n_3\,
\douta[7]\(3) => \ramloop[22].ram.r_n_4\,
\douta[7]\(2) => \ramloop[22].ram.r_n_5\,
\douta[7]\(1) => \ramloop[22].ram.r_n_6\,
\douta[7]\(0) => \ramloop[22].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[23].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized22\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[23].ram.r_n_0\,
\douta[7]\(6) => \ramloop[23].ram.r_n_1\,
\douta[7]\(5) => \ramloop[23].ram.r_n_2\,
\douta[7]\(4) => \ramloop[23].ram.r_n_3\,
\douta[7]\(3) => \ramloop[23].ram.r_n_4\,
\douta[7]\(2) => \ramloop[23].ram.r_n_5\,
\douta[7]\(1) => \ramloop[23].ram.r_n_6\,
\douta[7]\(0) => \ramloop[23].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[24].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized23\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[24].ram.r_n_0\,
\douta[7]\(6) => \ramloop[24].ram.r_n_1\,
\douta[7]\(5) => \ramloop[24].ram.r_n_2\,
\douta[7]\(4) => \ramloop[24].ram.r_n_3\,
\douta[7]\(3) => \ramloop[24].ram.r_n_4\,
\douta[7]\(2) => \ramloop[24].ram.r_n_5\,
\douta[7]\(1) => \ramloop[24].ram.r_n_6\,
\douta[7]\(0) => \ramloop[24].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[25].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized24\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[25].ram.r_n_0\,
\douta[7]\(6) => \ramloop[25].ram.r_n_1\,
\douta[7]\(5) => \ramloop[25].ram.r_n_2\,
\douta[7]\(4) => \ramloop[25].ram.r_n_3\,
\douta[7]\(3) => \ramloop[25].ram.r_n_4\,
\douta[7]\(2) => \ramloop[25].ram.r_n_5\,
\douta[7]\(1) => \ramloop[25].ram.r_n_6\,
\douta[7]\(0) => \ramloop[25].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[26].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized25\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[26].ram.r_n_0\,
\douta[7]\(6) => \ramloop[26].ram.r_n_1\,
\douta[7]\(5) => \ramloop[26].ram.r_n_2\,
\douta[7]\(4) => \ramloop[26].ram.r_n_3\,
\douta[7]\(3) => \ramloop[26].ram.r_n_4\,
\douta[7]\(2) => \ramloop[26].ram.r_n_5\,
\douta[7]\(1) => \ramloop[26].ram.r_n_6\,
\douta[7]\(0) => \ramloop[26].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[27].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized26\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[27].ram.r_n_0\,
\douta[7]\(6) => \ramloop[27].ram.r_n_1\,
\douta[7]\(5) => \ramloop[27].ram.r_n_2\,
\douta[7]\(4) => \ramloop[27].ram.r_n_3\,
\douta[7]\(3) => \ramloop[27].ram.r_n_4\,
\douta[7]\(2) => \ramloop[27].ram.r_n_5\,
\douta[7]\(1) => \ramloop[27].ram.r_n_6\,
\douta[7]\(0) => \ramloop[27].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[28].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized27\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[28].ram.r_n_0\,
\douta[7]\(6) => \ramloop[28].ram.r_n_1\,
\douta[7]\(5) => \ramloop[28].ram.r_n_2\,
\douta[7]\(4) => \ramloop[28].ram.r_n_3\,
\douta[7]\(3) => \ramloop[28].ram.r_n_4\,
\douta[7]\(2) => \ramloop[28].ram.r_n_5\,
\douta[7]\(1) => \ramloop[28].ram.r_n_6\,
\douta[7]\(0) => \ramloop[28].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[29].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized28\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[29].ram.r_n_0\,
\douta[7]\(6) => \ramloop[29].ram.r_n_1\,
\douta[7]\(5) => \ramloop[29].ram.r_n_2\,
\douta[7]\(4) => \ramloop[29].ram.r_n_3\,
\douta[7]\(3) => \ramloop[29].ram.r_n_4\,
\douta[7]\(2) => \ramloop[29].ram.r_n_5\,
\douta[7]\(1) => \ramloop[29].ram.r_n_6\,
\douta[7]\(0) => \ramloop[29].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized1\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[2].ram.r_n_0\,
\douta[7]\(6) => \ramloop[2].ram.r_n_1\,
\douta[7]\(5) => \ramloop[2].ram.r_n_2\,
\douta[7]\(4) => \ramloop[2].ram.r_n_3\,
\douta[7]\(3) => \ramloop[2].ram.r_n_4\,
\douta[7]\(2) => \ramloop[2].ram.r_n_5\,
\douta[7]\(1) => \ramloop[2].ram.r_n_6\,
\douta[7]\(0) => \ramloop[2].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[30].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized29\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[30].ram.r_n_0\,
\douta[7]\(6) => \ramloop[30].ram.r_n_1\,
\douta[7]\(5) => \ramloop[30].ram.r_n_2\,
\douta[7]\(4) => \ramloop[30].ram.r_n_3\,
\douta[7]\(3) => \ramloop[30].ram.r_n_4\,
\douta[7]\(2) => \ramloop[30].ram.r_n_5\,
\douta[7]\(1) => \ramloop[30].ram.r_n_6\,
\douta[7]\(0) => \ramloop[30].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[31].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized30\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[31].ram.r_n_0\,
\douta[7]\(6) => \ramloop[31].ram.r_n_1\,
\douta[7]\(5) => \ramloop[31].ram.r_n_2\,
\douta[7]\(4) => \ramloop[31].ram.r_n_3\,
\douta[7]\(3) => \ramloop[31].ram.r_n_4\,
\douta[7]\(2) => \ramloop[31].ram.r_n_5\,
\douta[7]\(1) => \ramloop[31].ram.r_n_6\,
\douta[7]\(0) => \ramloop[31].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized2\
port map (
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized3\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[4].ram.r_n_0\,
\douta[7]\(6) => \ramloop[4].ram.r_n_1\,
\douta[7]\(5) => \ramloop[4].ram.r_n_2\,
\douta[7]\(4) => \ramloop[4].ram.r_n_3\,
\douta[7]\(3) => \ramloop[4].ram.r_n_4\,
\douta[7]\(2) => \ramloop[4].ram.r_n_5\,
\douta[7]\(1) => \ramloop[4].ram.r_n_6\,
\douta[7]\(0) => \ramloop[4].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized4\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[5].ram.r_n_0\,
\douta[7]\(6) => \ramloop[5].ram.r_n_1\,
\douta[7]\(5) => \ramloop[5].ram.r_n_2\,
\douta[7]\(4) => \ramloop[5].ram.r_n_3\,
\douta[7]\(3) => \ramloop[5].ram.r_n_4\,
\douta[7]\(2) => \ramloop[5].ram.r_n_5\,
\douta[7]\(1) => \ramloop[5].ram.r_n_6\,
\douta[7]\(0) => \ramloop[5].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized5\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[6].ram.r_n_0\,
\douta[7]\(6) => \ramloop[6].ram.r_n_1\,
\douta[7]\(5) => \ramloop[6].ram.r_n_2\,
\douta[7]\(4) => \ramloop[6].ram.r_n_3\,
\douta[7]\(3) => \ramloop[6].ram.r_n_4\,
\douta[7]\(2) => \ramloop[6].ram.r_n_5\,
\douta[7]\(1) => \ramloop[6].ram.r_n_6\,
\douta[7]\(0) => \ramloop[6].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized6\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[7].ram.r_n_0\,
\douta[7]\(6) => \ramloop[7].ram.r_n_1\,
\douta[7]\(5) => \ramloop[7].ram.r_n_2\,
\douta[7]\(4) => \ramloop[7].ram.r_n_3\,
\douta[7]\(3) => \ramloop[7].ram.r_n_4\,
\douta[7]\(2) => \ramloop[7].ram.r_n_5\,
\douta[7]\(1) => \ramloop[7].ram.r_n_6\,
\douta[7]\(0) => \ramloop[7].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[8].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized7\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[8].ram.r_n_0\,
\douta[7]\(6) => \ramloop[8].ram.r_n_1\,
\douta[7]\(5) => \ramloop[8].ram.r_n_2\,
\douta[7]\(4) => \ramloop[8].ram.r_n_3\,
\douta[7]\(3) => \ramloop[8].ram.r_n_4\,
\douta[7]\(2) => \ramloop[8].ram.r_n_5\,
\douta[7]\(1) => \ramloop[8].ram.r_n_6\,
\douta[7]\(0) => \ramloop[8].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
\ramloop[9].ram.r\: entity work.\Mem_blk_mem_gen_prim_width__parameterized8\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[7]\(7) => \ramloop[9].ram.r_n_0\,
\douta[7]\(6) => \ramloop[9].ram.r_n_1\,
\douta[7]\(5) => \ramloop[9].ram.r_n_2\,
\douta[7]\(4) => \ramloop[9].ram.r_n_3\,
\douta[7]\(3) => \ramloop[9].ram.r_n_4\,
\douta[7]\(2) => \ramloop[9].ram.r_n_5\,
\douta[7]\(1) => \ramloop[9].ram.r_n_6\,
\douta[7]\(0) => \ramloop[9].ram.r_n_7\,
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Mem_blk_mem_gen_top : entity is "blk_mem_gen_top";
end Mem_blk_mem_gen_top;
architecture STRUCTURE of Mem_blk_mem_gen_top is
begin
\valid.cstr\: entity work.Mem_blk_mem_gen_generic_cstr
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem_blk_mem_gen_v8_3_1_synth is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Mem_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end Mem_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of Mem_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.Mem_blk_mem_gen_top
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 16 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of Mem_blk_mem_gen_v8_3_1 : entity is 17;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of Mem_blk_mem_gen_v8_3_1 : entity is 17;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of Mem_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of Mem_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of Mem_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of Mem_blk_mem_gen_v8_3_1 : entity is "32";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of Mem_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of Mem_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of Mem_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of Mem_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 2.5485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of Mem_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of Mem_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of Mem_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of Mem_blk_mem_gen_v8_3_1 : entity is "Mem.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of Mem_blk_mem_gen_v8_3_1 : entity is "Mem.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of Mem_blk_mem_gen_v8_3_1 : entity is 131072;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of Mem_blk_mem_gen_v8_3_1 : entity is 131072;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of Mem_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of Mem_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of Mem_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of Mem_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of Mem_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of Mem_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of Mem_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of Mem_blk_mem_gen_v8_3_1 : entity is 131072;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of Mem_blk_mem_gen_v8_3_1 : entity is 131072;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of Mem_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of Mem_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of Mem_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of Mem_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of Mem_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Mem_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of Mem_blk_mem_gen_v8_3_1 : entity is "yes";
end Mem_blk_mem_gen_v8_3_1;
architecture STRUCTURE of Mem_blk_mem_gen_v8_3_1 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.Mem_blk_mem_gen_v8_3_1_synth
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of Mem : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of Mem : entity is "Mem,blk_mem_gen_v8_3_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of Mem : entity is "Mem,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Mem.mif,C_INIT_FILE=Mem.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=131072,C_READ_DEPTH_A=131072,C_ADDRA_WIDTH=17,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=131072,C_READ_DEPTH_B=131072,C_ADDRB_WIDTH=17,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=32,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.5485 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of Mem : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of Mem : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end Mem;
architecture STRUCTURE of Mem is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 17;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 17;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "32";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.5485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "Mem.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "Mem.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 131072;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 131072;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 131072;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 131072;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.Mem_blk_mem_gen_v8_3_1
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => B"00000000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => B"00000000",
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(16 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(16 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(16 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(16 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
mit
|
00f936a3ca785c7372cbc320b827957a
| 0.731641 | 2.945561 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_time.vhd
| 3 | 2,038 |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use work.time_pkg.all;
entity vhdl_time is
port(a : out std_logic;
b : in std_logic;
tout : out time;
tin : in time);
end vhdl_time;
architecture test of vhdl_time is
signal time_sig : time_subtype := 100 ns;
begin
tout <= 140 ns;
process(b)
variable time_var : time;
begin
if(rising_edge(b)) then
time_var := 100 ns;
time_sig := 500 ns;
a := '0';
wait for 50 ns;
a := '1';
wait for time_sig; -- signal
a := '0';
wait for time_const; -- constant
a := '1';
wait for time_var; -- variable
a := '0';
wait for (time_sig + time_const + time_var);
a := '1';
-- Modify variable & signal values
time_var := 10 ns;
wait for time_var;
a := '0';
time_sig := 20 ns;
wait for time_sig;
a := '1';
-- Test time read from port
wait for tin;
a := '0';
end if;
end process;
end test;
|
gpl-2.0
|
13155d3cf0ec431ba81e648b5f4e334d
| 0.568695 | 3.996078 | false | true | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/opb_ac97.vhd
| 4 | 10,259 |
-------------------------------------------------------------------------------
-- $Id: opb_ac97.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- opb_ac97.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ac97
--
-- Description: Provides an OPB interface to the ac97 fifo controller
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_fifo
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity opb_ac97 is
generic (
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_8000";
C_HIGHADDR : std_logic_vector := X"FFFF_80FF";
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
-- C_GPOUT_DWIDTH : integer := 1;
-- value of 0,1,2,3,4
-- 0 = No Interrupt
-- 1 = empty
-- 2 = halfempty
-- 3 = halffull
-- 4 = full
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
-- GPIO signals (Beep, reset, etc.)
-- AC97_GPOUT : out std_logic_vector(0 to C_GPOUT_DWIDTH-1);
-- Interrupt signals
Interrupt : out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_BASEADDR : constant is "0x100";
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_ac97;
-- library proc_common_v1_00_b;
-- use proc_common_v1_00_b.proc_common_pkg.all;
-- library ipif_common_v1_00_c;
-- use ipif_common_v1_00_c.ipif_pkg.all;
-- library opb_ipif_v3_00_a;
-- use opb_ipif_v3_00_a.all;
library Common_v1_00_a;
use Common_v1_00_a.pselect;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
library unisim;
use unisim.all;
architecture IMP of opb_ac97 is
component ac97_fifo is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLAYBACK : integer := 1;
C_RECORD : integer := 0;
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
-- IP Interface
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Interrupt: out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
end component ac97_fifo;
component FDR is
port (Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component pselect is
generic (
C_AB : integer;
C_AW : integer;
C_BAR : std_logic_vector);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
ps : out std_logic);
end component pselect;
function Addr_Bits (x, y : std_logic_vector(0 to C_OPB_AWIDTH-1)) return integer is
variable addr_nor : std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_OPB_AWIDTH-1 loop
if addr_nor(i) = '1' then return i;
end if;
end loop;
return(C_OPB_AWIDTH);
end function Addr_Bits;
constant C_AB : integer := Addr_Bits(C_HIGHADDR, C_BASEADDR);
signal ac97_CS : std_logic;
signal ac97_CS_1 : std_logic; -- Active as long as AC97_CS is active
signal ac97_CS_2 : std_logic; -- Active only 1 clock cycle during an
signal ac97_CS_3 : std_logic; -- Active only 1 clock cycle during an
signal xfer_Ack : std_logic;
signal opb_RNW_1 : std_logic;
signal opb_rdce : std_logic;
signal opb_wrce : std_logic;
signal iSln_DBus : std_logic_vector(0 to 31);
signal interrupt_i : std_logic;
begin
Interrupt <= interrupt_i;
-- Do the OPB address decoding
pselect_I : pselect
generic map (
C_AB => C_AB, -- [integer]
C_AW => C_OPB_AWIDTH, -- [integer]
C_BAR => C_BASEADDR) -- [std_logic_vector]
port map (
A => OPB_ABus, -- [in std_logic_vector(0 to C_AW-1)]
AValid => OPB_select, -- [in std_logic]
ps => ac97_CS); -- [out std_logic]
ac97_CS_1_DFF : FDR
port map (
Q => ac97_CS_1, -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
D => ac97_CS, -- [in std_logic]
R => xfer_Ack); -- [in std_logic]
ac97_CS_2_DFF: process (OPB_Clk, OPB_Rst) is
begin -- process uart_CS_2_DFF
if OPB_Rst = '1' then -- asynchronous reset (active high)
ac97_CS_2 <= '0';
ac97_CS_3 <= '0';
opb_RNW_1 <= '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
ac97_CS_2 <= ac97_CS_1 and not ac97_CS_2 and not ac97_CS_3;
ac97_CS_3 <= ac97_CS_2;
opb_RNW_1 <= OPB_RNW;
end if;
end process ac97_CS_2_DFF;
opb_rdce <= ac97_CS_2 and OPB_RNW_1;
opb_wrce <= ac97_CS_2 and (not OPB_RNW_1);
XFER_Control : process (OPB_Clk, OPB_Rst) is
begin -- process XFER_Control
if OPB_Rst = '1' then -- asynchronous reset (active high)
xfer_Ack <= '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
xfer_Ack <= ac97_CS_2;
end if;
end process XFER_Control;
Sln_errAck <= '0';
Sln_retry <= '0';
Sln_toutSup <= '0';
sln_xferAck <= xfer_Ack;
OPB_rdDBus_DFF : for I in iSln_DBus'range generate
OPB_rdBus_FDRE : FDRE
port map (
Q => Sln_DBus(I), -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
CE => ac97_CS_2, -- [in std_logic]
D => iSln_Dbus(I), -- [in std_logic]
R => xfer_Ack); -- [in std_logic]
end generate OPB_rdDBus_DFF;
AC97_FIFO_I : ac97_fifo
generic map (
C_PLAYBACK => C_PLAYBACK,
C_RECORD => C_RECORD,
C_INTR_LEVEL => C_INTR_LEVEL,
C_USE_BRAM => C_USE_BRAM
)
port map (
-- IP Interface
Bus2IP_Clk => OPB_Clk,
Bus2IP_Reset => OPB_Rst,
Bus2IP_Addr => OPB_ABus,
Bus2IP_Data => OPB_Dbus,
Bus2IP_BE => OPB_BE,
Bus2IP_RdCE => opb_rdce,
Bus2IP_WrCE => opb_wrce,
IP2Bus_Data => iSln_DBus,
Interrupt => interrupt_i,
-- CODEC signals
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In,
AC97Reset_n => AC97Reset_n
);
end architecture IMP;
|
gpl-3.0
|
ae896f34ffcd6920179f9c0c7e86e02d
| 0.454723 | 3.519383 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/framework/observation.vhd
| 1 | 43,554 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity observation is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- CHANGE 1 OF 7
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
-- END CHANGE
);
end observation;
architecture Behavioral of observation is
component uf_extract_observation is
Port(
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input data address
input_data_address : in std_logic_vector(0 to 31);
input_data_needed : out std_logic;
-- get word data
word_data_en : in std_logic;
word_address : out std_logic_vector(0 to 31);
word_data : in std_logic_vector(0 to 31);
word_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end component;
-- -------------------------------------------------------------------
-- --
-- -- ICON core component declaration
-- --
-- -------------------------------------------------------------------
-- component icon
-- port
-- (
-- control0 : out std_logic_vector(35 downto 0)
-- );
-- end component;
--
-- -------------------------------------------------------------------
-- --
-- -- ILA core component declaration
-- --
-- -------------------------------------------------------------------
-- component ila
-- port
-- (
-- control : in std_logic_vector(35 downto 0);
-- clk : in std_logic;
-- data : in std_logic_vector(31 downto 0);
-- trig0 : in std_logic_vector(31 downto 0)
-- );
-- end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (initialize, read_particle_address, read_number_of_particles,
read_particle_size, read_block_size, read_observation_size,
needed_bursts, needed_bursts_2, calculate_last_burst_length,
calculate_last_burst_length_2, read_observation_address,
read_input_data_link_address, read_parameter_size,
read_parameter_address, copy_parameter,
copy_parameter_2, copy_parameter_3,
copy_parameter_ack, wait_for_message,
calculate_remaining_observations_1, calculate_remaining_observations_2,
calculate_remaining_observations_3, calculate_remaining_observations_4,
calculate_remaining_observations_5, calculate_remaining_observations_6,
calculate_remaining_observations_7, calculate_remaining_observations_8,
calculate_remaining_observations_9,
read_input_data_address, read_next_particle, read_next_particle_2,
read_next_particle_3, read_next_particle_4, read_next_particle_5,
read_next_particle_6, read_next_particle_7,
start_extract_observation, start_extract_observation_wait,
extract_observation,
get_input_data, cache_hit, cache_miss, cache_miss_2,
cache_miss_3, cache_miss_4, cache_miss_5, cache_miss_6,
cache_miss_7, cache_miss_8,
load_word, load_word_2,
write_word_back, write_word_ack,
write_observation, write_observation_2,
write_observation_3, write_observation_4,
write_observation_5, write_observation_6,
more_particles, more_particles_2, send_message,
send_measurement_1, send_measurement_2 );
-- current state
signal state : t_state := initialize;
-- particle array
signal particle_array_start_address:std_logic_vector(0 to C_OSIF_DATA_WIDTH-1):="00010000000000000000000000000000";
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--local RAM cache addresses
signal local_ram_cache_address:std_logic_vector(0 to C_OSIF_DATA_WIDTH-1):="00000000000000000001111110000000";
signal current_local_ram_cache_address:std_logic_vector(0 to C_OSIF_DATA_WIDTH-1):=(others => '0');
signal local_ram_cache_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := "111111100000";
signal current_local_ram_cache_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal cache_min : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal cache_max : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- lin/pointer to memory word, where the input address is stored
signal input_data_link_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of observations
signal remaining_observations : integer := 2;
-- number of needed bursts
signal number_of_bursts : integer := 3;
-- number of reads
signal number_of_reads : integer := 0;
-- read counter
signal read_counter : integer := 0;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 3;
-- length of last burst
signal length_of_last_burst : integer := 7;
-- size of a particle
signal particle_size : integer := 32;
-- number of particles
signal N : integer := 20;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal cache_offset : integer := 0;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 2;
-- current particle data
signal particle_data : integer := 0;
-- parameter address
signal parameter_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter size
signal parameter_size : integer := 0;
-- parameter loaded
signal parameter_loaded : std_logic := '0';
-- parameters acknowledged by user process
signal parameter_loaded_ack : std_logic; -- := '0';
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
signal counter : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- new particle loaded
signal new_particle : std_logic := '0';
-- new particle loaded - ackowledgement
signal new_particle_ack : std_logic := '1';
-- input data address
signal input_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- input data needed signal
signal input_data_needed : std_logic := '0';
-- word data enable
signal word_data_en : std_logic := '0';
-- word data address
signal word_data : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- word address
signal word_address : std_logic_vector(0 to 31) := (others => '0');
-- word_ack
signal word_data_ack : std_logic := '0';
-- if the observation is extracted, this signal is set to '1'
signal finished : std_logic := '1';
--current address
signal current_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- for switch 1: corrected local ram address. the least bit is inverted,
-- because else the local ram will be used incorrect
signal o_RAMAddrExtractObservation : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this observation thread
signal o_RAMAddrObservation : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEExtractObservation : std_logic := '0';
-- for switch 2: Write enable, observation
signal o_RAMWEObservation : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataExtractObservation : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, observation
signal o_RAMDataObservation : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- -------------------------------------------------------------------
-- --
-- -- ICON core signal declarations
-- --
-- -------------------------------------------------------------------
-- signal control0 : std_logic_vector(35 downto 0);
--
--
-- -------------------------------------------------------------------
-- --
-- -- ILA core signal declarations
-- --
-- -------------------------------------------------------------------
-- signal data : std_logic_vector(31 downto 0);
signal trig0 : std_logic_vector(31 downto 0);
begin
-- -------------------------------------------------------------------
-- --
-- -- ICON core instance
-- --
-- -------------------------------------------------------------------
-- i_icon : icon
-- port map
-- (
-- control0 => control0
-- );
--
--
-- -------------------------------------------------------------------
-- --
-- -- ILA core instance
-- --
-- -------------------------------------------------------------------
-- i_ila : ila
-- port map
-- (
-- control => control0,
-- clk => clk,
-- data => data,
-- trig0 => trig0
-- );
--
-- data <= trig0;
-------------------------------------------------------------------
--
-- User Process
--
-------------------------------------------------------------------
user_process : uf_extract_observation
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrExtractObservation,
o_RAMData=>o_RAMDataExtractObservation, i_RAMData=>i_RAMData,
o_RAMWE=>o_RAMWEExtractObservation, o_RAMClk=>o_RAMClk,
parameter_loaded=>parameter_loaded, parameter_loaded_ack=>parameter_loaded_ack,
new_particle=>new_particle, new_particle_ack=>new_particle_ack,
input_data_address=>input_data_address, input_data_needed=>input_data_needed,
word_data_en=>word_data_en, word_address=>word_address,
word_data=>word_data, word_data_ack=>word_data_ack,
init=>init, enable=>enable,
finished=>finished);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrExtractObservation(0 to C_BURST_AWIDTH-2) & not o_RAMAddrExtractObservation(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrObservation(0 to C_BURST_AWIDTH-2) & not o_RAMAddrObservation(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEExtractObservation when enable = '1' else o_RAMWEObservation;
-- switch 3: output ram data
o_RAMData <= o_RAMDataExtractObservation when enable = '1' else o_RAMDataObservation;
-----------------------------------------------------------------------------
--
-- ReconOS State Machine for Observation:
--
-----------------------------------------------------------------------------
--
-- (1) read data from information struct
--
-- (2) receive message m
--
-- (3) set current address for input data
--
-- (4) load current particle (into local ram, starting address (others=>'0'))
--
-- (5) start user process for observation extraction
--
-- (6) wait for finished signal of user process
--
-- (7) write observation into main memory (from local ram, starting address (others=>'0'))
--
-- (8) if more particle need to be processed
-- go to step 4
-- else
-- go to step 9
--
-- (9) send message m
--
-- (9*) send measurement
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable parameter_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= initialize;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case (state) is
when initialize =>
--! init state, receive information struct
trig0 <= X"00000000";
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
if done then
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
new_particle <= '0';
-- CHANGE CHANGE CHANGE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
state <= read_particle_address;
--state <= wait_for_message;
-- END OF CHANGE CHANGE CHANGE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- CHANGE 2 OF 7!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--state <= needed_bursts;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- END CHANGE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ INFORMATION_STRUCT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when read_particle_address =>
trig0 <= X"00000001";
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= read_number_of_particles;
end if;
when read_number_of_particles =>
trig0 <= X"00000002";
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= read_particle_size;
end if;
when read_particle_size =>
trig0 <= X"00000003";
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= read_block_size;
end if;
when read_block_size =>
trig0 <= X"00000004";
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= read_observation_size;
end if;
when read_observation_size =>
trig0 <= X"00000005";
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= needed_bursts;
end if;
when needed_bursts =>
trig0 <= X"00000006";
--! calculate needed bursts
--number_of_bursts_remember <= observation_size / 128;
state <= calculate_last_burst_length;
when calculate_last_burst_length =>
trig0 <= X"00000007";
--! calculate number of reads (1 of 2)
--length_of_last_burst <= observation_size mod 128;
state <= calculate_last_burst_length_2;
when calculate_last_burst_length_2 =>
trig0 <= X"00000008";
--! calculate number of reads (2 of 2)
--length_of_last_burst <= length_of_last_burst / 8;
number_of_reads <= observation_size / 4;
state <= read_observation_address;
-- CHANGE 3 OF 7
--state <= wait_for_message;
-- END CHANGE
when read_observation_address =>
trig0 <= X"00000009";
--! read observation array address
reconos_read_s (done,o_osif,i_osif,information_struct+20,observation_array_start_address);
if done then
state <= read_input_data_link_address;
end if;
when read_input_data_link_address =>
trig0 <= X"0000000A";
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+24, input_data_link_address);
if done then
--state <= wait_for_message;
state <= read_parameter_size;
end if;
when read_parameter_size =>
trig0 <= X"0000000B";
--! read parameter size
reconos_read (done, o_osif, i_osif, information_struct+28, parameter_size_var);
if done then
parameter_size <= TO_INTEGER(SIGNED(parameter_size_var));
state <= read_parameter_address;
end if;
when read_parameter_address =>
trig0 <= X"0000000C";
--! read parameter size
reconos_read_s (done, o_osif, i_osif, information_struct+32, parameter_address);
if done then
state <= copy_parameter;
local_ram_address_if <= local_ram_start_address_if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ PARAMETERS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when copy_parameter =>
trig0 <= X"0000000D";
--! read parameter size
o_RAMWEObservation <= '0';
if (parameter_size > 0) then
parameter_size <= parameter_size - 1;
state <= copy_parameter_2;
else
state <= copy_parameter_ack;
parameter_loaded <= '1';
enable <= '1';
init <= '0';
end if;
when copy_parameter_2 =>
trig0 <= X"0000000E";
--! read parameter size
reconos_read_s (done, o_osif, i_osif, parameter_address, ram_data);
if done then
state <= copy_parameter_3;
end if;
when copy_parameter_3 =>
trig0 <= X"0000000F";
--! read parameter size
parameter_address <= parameter_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
enable <= '0';
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
o_RAMDataObservation <= ram_data;
state <= copy_parameter;
when copy_parameter_ack =>
trig0 <= X"00000010";
--! read parameter size
if (parameter_loaded_ack = '1') then
enable <= '0';
init <= '1';
parameter_loaded <= '0';
state <= wait_for_message;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 2: WAIT FOR MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when wait_for_message =>
trig0 <= X"00000011";
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
enable <= '0';
init <= '1';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
--N <= 100; -- TODO: ONLY FOR SIMULATION
--number_of_reads <= 130; -- TODO: ONLY FOR SIMULATION
--block_size <= 10; -- TODO: ONLY FOR SIMULATION
--particle_size <= 32; -- TODO: ONLY FOR SIMULATION
--observation_size <= 520; -- TODO: ONLY FOR SIMULATION
--particle_array_start_address <= X"10000000"; -- TODO: ONLY FOR SIMULATION
--observation_array_start_address <= X"20000000"; -- TODO: ONLY FOR SIMULATION
state <= calculate_remaining_observations_1;
end if;
when calculate_remaining_observations_1 =>
trig0 <= X"00000012";
--! calculates particle array address and number of particles to sample
message2 <= message-1;
state <= calculate_remaining_observations_2;
when calculate_remaining_observations_2 =>
trig0 <= X"00000013";
--! calculates particle array address and number of particles to sample
temp <= message2 * block_size;
state <= calculate_remaining_observations_3;
when calculate_remaining_observations_3 =>
trig0 <= X"00000014";
--! wait
state <= calculate_remaining_observations_4;
when calculate_remaining_observations_4 =>
trig0 <= X"00000015";
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
state <= calculate_remaining_observations_5;
when calculate_remaining_observations_5 =>
trig0 <= X"00000016";
--! wait
state <= calculate_remaining_observations_6;
when calculate_remaining_observations_6 =>
trig0 <= X"00000017";
temp3 <= temp * observation_size;
state <= calculate_remaining_observations_7;
when calculate_remaining_observations_7 =>
trig0 <= X"00000018";
--! wait
state <= calculate_remaining_observations_8;
when calculate_remaining_observations_8 =>
trig0 <= X"00000019";
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= calculate_remaining_observations_9;
when calculate_remaining_observations_9 =>
trig0 <= X"0000001A";
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
end if;
state <= read_input_data_address;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 3: READ CURRENT INPUT DATA ADDRESS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when read_input_data_address =>
trig0 <= X"0000001B";
--! read reference data address
reconos_read_s (done, o_osif, i_osif, input_data_link_address, input_data_address);
if done then
current_local_ram_cache_address <= (others=>'0');
current_local_ram_cache_address_if <= (others=>'0');
state <= read_next_particle;
-- TODO: CHANGE CHANGE CHANGE
--state <= read_next_particle_2;
end if;
-- CHANGE 5 of 7
-- input data address: 0x20000000
--input_data_address <= "00100000000000000000000000000000";
-- the particle array address: 0x10000000
--particle_array_address <= "00010000000000000000000000000000";
-- the observation array address: 0x11000000
--observation_array_address <= "00010001000000000000000000000000";
--state <= read_next_particle;
-- END CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 4: WRITE PARTICLE INTO CURRENT RAM
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when read_next_particle =>
trig0 <= X"0000001C";
--! read next particle to local ram (writing the first 128 bytes to the local ram)
-- CHANGE CHANGE CHANGE
--reconos_read_burst(done,o_osif,i_osif,local_ram_start_address,particle_array_address);
--if done then
--particle_array_address <= particle_array_address + particle_size;
-- CHANGE CHANGE CHANGE
--state <= start_extract_observation;
local_ram_address_if <= (others => '0');
read_counter <= particle_size / 4;
state <= read_next_particle_2;
--state <= write_observation;
-- END OF CHANGE CHANGE CHANGE
--end if;
-- END OF CHANGE CHANGE CHANGE
when read_next_particle_2 =>
trig0 <= X"0000001D";
--! checks, if more reads are needed
if (read_counter > 0) then
read_counter <= read_counter - 1;
state <= read_next_particle_3;
else
-- no more reads: start user process
--particle_array_address <= particle_array_address + particle_size;
state <= start_extract_observation;
-- CHANGE CHANGE CHANGE - TODO REMOVE
--state <= write_observation;
--state <= send_message;
--state <= more_particles;
end if;
when read_next_particle_3 =>
trig0 <= X"0000001E";
--! read 4 bytes
reconos_read_s(done, o_osif, i_osif, particle_array_address, ram_data);
if done then
state <= read_next_particle_4;
end if;
when read_next_particle_4 =>
trig0 <= X"0000001F";
--! wait
state <= read_next_particle_5;
when read_next_particle_5 =>
trig0 <= X"00000020";
--! write 4 bytes to local ram
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
o_RAMDataObservation <= ram_data;
state <= read_next_particle_6;
when read_next_particle_6 =>
trig0 <= X"00000021";
--! wait
o_RAMWEObservation <= '0';
particle_array_address <= particle_array_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
state <= read_next_particle_7;
when read_next_particle_7 =>
trig0 <= X"00000022";
--! wait
state <= read_next_particle_2;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 5: START OBSERVATION EXTRACTION
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
when start_extract_observation =>
trig0 <= X"00000023";
--! start the user process
init <= '0';
enable <= '1';
new_particle <= '1';
state <= start_extract_observation_wait;
when start_extract_observation_wait =>
trig0 <= X"00000024";
--! user process needs to start the execution
-- CHANGE CHANGE CHANGE
if new_particle_ack = '1' then
new_particle <= '0';
state <= extract_observation;
end if;
-- END OF CHANGE CHANGE CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 6: WAIT FOR OBSERVATION EXTRACTION TO FINISH / ANSWER DATA CALLS INBETWEEN
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when extract_observation =>
trig0 <= X"00000025";
--! check if observation is finished, or it input data is needed (from cache)
if finished = '1' then
-- observation finished
enable <= '0';
init <= '1';
new_particle <= '0';
state <= write_observation;
elsif input_data_needed = '1' then
state <= get_input_data;
end if;
when get_input_data =>
trig0 <= X"00000026";
--! get input data at word_address (and write it into word_data)
--enable <= '0';
--cache_offset <= 0;
--if (cache_min <= word_address) and (word_address < cache_max) then
-- -- cache hit
-- state <= cache_hit;
-- --current_address <= cache_min;
-- current_address <= word_address - cache_min;
--else
-- -- cache miss
state <= cache_miss;
--end if;
-- when cache_hit =>
-- trig0 <= X"00000027";
-- --! calculate the correct position in the local ram
-- cache_offset <= TO_INTEGER(UNSIGNED(current_address)) / 4;
-- state <= load_word;
--
-- when cache_miss =>
-- trig0 <= X"00000028";
-- --! check if word address is double aligned
-- if (word_address(29) = '0') then
-- -- word address is double-word aligned (needed for read bursts)
-- cache_min <= word_address;
-- cache_max <= word_address + 128;
-- cache_offset <= 0;
-- else
-- -- word address is NOT double-word aligned => cache_min has to be adjusted
-- cache_min <= word_address - 4;
-- cache_max <= word_address + 124;
-- cache_offset <= 1;
-- end if;
-- state <= cache_miss_2;
-- -- TODO: CHANGE CHANGE CHANGE
-- --cache_min <= word_address;
-- --cache_max <= word_address + 128;
-- --cache_offset <= 0;
-- --current_local_ram_cache_address <= word_address;
-- --current_local_ram_cache_address_if <= local_ram_cache_address_if;
-- --read_counter <= 0;
-- --state <= cache_miss_3;
--
--
-- when cache_miss_2 =>
-- trig0 <= X"00000029";
-- --! reads 128 byte input burst into local ram cache
-- reconos_read_burst(done, o_osif, i_osif, local_ram_cache_address, cache_min);
-- if done then
-- state <= load_word;
-- end if;
--
-- when cache_miss_3 =>
-- trig0 <= X"0000002A";
-- --! checks, if more reads are needed
-- if (read_counter < 31) then
-- read_counter <= read_counter + 1;
-- state <= cache_miss_4;
-- else
-- state <= load_word;
-- end if;
--
-- when cache_miss_4 =>
-- trig0 <= X"0000002B";
-- --! read 4 bytes
-- reconos_read_s(done, o_osif, i_osif, current_local_ram_cache_address, ram_data);
-- if done then
-- state <= cache_miss_5;
-- end if;
--
-- when cache_miss_5 =>
-- trig0 <= X"0000002C";
-- --! wait
-- state <= cache_miss_6;
--
-- when cache_miss_6 =>
-- trig0 <= X"0000002D";
-- --! write 4 bytes to local ram
-- o_RAMWEObservation <= '1';
-- o_RAMAddrObservation <= current_local_ram_cache_address_if;
-- o_RAMDataObservation <= ram_data;
-- state <= cache_miss_7;
--
-- when cache_miss_7 =>
-- trig0 <= X"0000002E";
-- --! wait
-- o_RAMWEObservation <= '0';
-- current_local_ram_cache_address <= current_local_ram_cache_address + 4;
-- current_local_ram_cache_address_if <= current_local_ram_cache_address_if + 1;
-- state <= cache_miss_8;
--
-- when cache_miss_8 =>
-- trig0 <= X"0000002F";
-- --! wait
-- state <= cache_miss_3;
--
-- when load_word =>
-- trig0 <= X"00000030";
-- --! load word data
-- o_RAMAddrObservation <= local_ram_cache_address_if + cache_offset;
-- state <= load_word_2;
--
-- when load_word_2 =>
-- trig0 <= X"00000031";
-- --! load word data (wait one cycle)
---- state <= load_word_3;
----
---- when load_word_3 =>
---- trig0 <= X"00000032";
---- --! load word data (get word)
---- word_data <= i_RAMData;
-- state <= write_word_back;
when cache_miss =>
--! wait
state <= cache_miss_2;
when cache_miss_2 =>
reconos_read_s(done, o_osif, i_osif, word_address, word_data);
if done then
state <= cache_miss_3;
end if;
when cache_miss_3 =>
--! wait
state <= cache_miss_4;
when cache_miss_4 =>
--! wait
state <= write_word_back;
when write_word_back =>
trig0 <= X"00000033";
--! activate user process and transfer the word
enable <= '1';
word_data_en <= '1';
--word_data <= i_RAMData;
state <= write_word_ack;
when write_word_ack =>
trig0 <= X"00000034";
--! wait for acknowledgement
-- TODO CHANGE CHANGE CHANGE - BACK
--if word_data_ack = '1' then
word_data_en <= '0';
state <= extract_observation;
--end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 7: WRITE OBSERVATION TO MAIN MEMORY
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when write_observation =>
trig0 <= X"00000035";
--! init write process
counter <= 0;
local_ram_address_if <= (others=>'0');
state <= write_observation_2;
when write_observation_2 =>
trig0 <= X"00000036";
--! more writing to do?
if (counter < number_of_reads) then
counter <= counter + 1;
state <= write_observation_3;
else
-- writing finished
state <= more_particles;
-- TODO: CHANGE CHANGE CHANGE: REMOVE
--state <= send_message;
end if;
when write_observation_3 =>
trig0 <= X"00000037";
--! get local ram data
o_RAMAddrObservation <= local_ram_address_if;
state <= write_observation_4;
when write_observation_4 =>
trig0 <= X"00000038";
--! wait (needed to receive local ram data -> offset)
state <= write_observation_5;
when write_observation_5 =>
trig0 <= X"00000039";
--! write
reconos_write(done, o_osif, i_osif, observation_array_address, i_RAMData);
if done then
observation_array_address <= observation_array_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
state <= write_observation_6;
end if;
when write_observation_6 =>
trig0 <= X"0000003A";
--! wait
state <= write_observation_2;
---- when write_observation =>
---- --! write observation (init)
---- number_of_bursts <= number_of_bursts_remember;
---- local_ram_address <= local_ram_start_address;
---- --write_histo_en <= '1';
---- state <= write_observation_2;
----
---- when write_observation_2 =>
---- --! write observation (check burst number)
---- if number_of_bursts > 0 then
---- -- more full bursts needed
---- state <= write_observation_3;
---- number_of_bursts <= number_of_bursts - 1;
---- elsif length_of_last_burst > 0 then
---- -- last burst needed (not full)
---- temp4 <= length_of_last_burst * 8;
---- state <= write_observation_4;
---- else
---- -- no last burst needed (which is not full)
---- state <= more_particles;
---- end if;
----
---- when write_observation_3 =>
---- --! write observation (write bursts)
---- reconos_write_burst(done, o_osif, i_osif, local_ram_address, observation_array_address);
---- if done then
---- observation_array_address <= observation_array_address + 128;
---- local_ram_address <= local_ram_address + 128;
---- state <= write_observation_2;
---- end if;
----
---- when write_observation_4 =>
---- --! write observation (write last burst)
---- reconos_write_burst_l(done,o_osif,i_osif,local_ram_address,
---- observation_array_address, length_of_last_burst);
---- if done then
---- observation_array_address <= observation_array_address + temp4;
---- local_ram_address <= local_ram_address + temp4;
---- state <= more_particles;
---- end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 8: MORE PARTICLES?
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when more_particles =>
trig0 <= X"0000003B";
--! check if more particles need an observation
remaining_observations <= remaining_observations - 1;
state <= more_particles_2;
when more_particles_2 =>
trig0 <= X"0000003C";
--! check if more particles need an observation
if (remaining_observations > 0) then
state <= read_next_particle;
else
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= send_message;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9: SEND MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when send_message =>
trig0 <= X"0000003D";
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE,
--input_data_address);
STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
--state <= send_measurement_1;
state <= wait_for_message;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9*: SEND MEASURMENT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
-- when send_measurement_1 =>
-- trig0 <= X"00000000";
-- --! sends time measurement to message box
-- -- send only, if time start < time stop. Else ignore this measurement
-- --if (time_start < time_stop) then
-- --time_measurement <= time_stop - time_start;
-- --state <= send_measurement_2;
-- --else
-- state <= wait_for_message;
-- --end if;
--
-- when send_measurement_2 =>
-- trig0 <= X"00000000";
-- --! sends time measurement to message box
-- --reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- --STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- --if (done and success) then
-- state <= wait_for_message;
-- --end if;
when others =>
trig0 <= X"00000000";
state <= wait_for_message;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
2a82b3eba89b97e1e866678458402724
| 0.511572 | 3.807501 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/generic_async_fifo.vhd
| 2 | 6,023 |
-------------------------------------------------------------------------------
-- Title : Parametrizable asynchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_async_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component inferred_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_rd_empty : boolean;
g_with_rd_full : boolean;
g_with_rd_almost_empty : boolean;
g_with_rd_almost_full : boolean;
g_with_rd_count : boolean;
g_with_wr_empty : boolean;
g_with_wr_full : boolean;
g_with_wr_almost_empty : boolean;
g_with_wr_almost_full : boolean;
g_with_wr_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
begin -- syn
U_Inferred_FIFO : inferred_async_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_rd_empty => g_with_rd_empty,
g_with_rd_full => g_with_rd_full,
g_with_rd_almost_empty => g_with_rd_almost_empty,
g_with_rd_almost_full => g_with_rd_almost_full,
g_with_rd_count => g_with_rd_count,
g_with_wr_empty => g_with_wr_empty,
g_with_wr_full => g_with_wr_full,
g_with_wr_almost_empty => g_with_wr_almost_empty,
g_with_wr_almost_full => g_with_wr_almost_full,
g_with_wr_count => g_with_wr_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold)
port map (
rst_n_i => rst_n_i,
clk_wr_i => clk_wr_i,
d_i => d_i,
we_i => we_i,
wr_empty_o => wr_empty_o,
wr_full_o => wr_full_o,
wr_almost_empty_o => wr_almost_empty_o,
wr_almost_full_o => wr_almost_full_o,
wr_count_o => wr_count_o,
clk_rd_i => clk_rd_i,
q_o => q_o,
rd_i => rd_i,
rd_empty_o => rd_empty_o,
rd_full_o => rd_full_o,
rd_almost_empty_o => rd_almost_empty_o,
rd_almost_full_o => rd_almost_full_o,
rd_count_o => rd_count_o);
end syn;
|
lgpl-3.0
|
ded99f5e8c66ae30eba224df87366f72
| 0.49394 | 3.37423 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/sram_cell.vhd
| 3 | 613 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_cell IS
GENERIC(width : positive);
PORT(
SEL, WE : IN std_logic;
D_IN : IN std_logic_vector(width-1 DOWNTO 0);
D_OUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END sram_cell;
ARCHITECTURE primitive OF sram_cell IS
SIGNAL B : std_logic_vector(width-1 DOWNTO 0);
BEGIN
behav: PROCESS(SEL,WE,D_IN)
BEGIN
IF SEL='1' THEN
IF WE='1' THEN
B <= D_IN;
D_OUT <= (OTHERS => 'Z');
ELSE
D_OUT <= B;
END IF;
ELSE
D_OUT <= (OTHERS => 'Z');
end IF;
END PROCESS;
END primitive;
|
bsd-3-clause
|
7439f89ed426d11321cf194a73a5e733
| 0.574225 | 3.004902 | false | false | false | false |
makestuff/vhdl
|
memctrl/memctrl/memctrl_tb.vhdl
| 1 | 4,310 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.memctrl_pkg.all;
use work.hexutil.all;
entity memctrl_tb is
end memctrl_tb;
architecture behavioural of memctrl_tb is
signal mcRst : std_logic;
signal mcClk : std_logic;
signal mcOp : MCOpType;
signal mcAddr : std_logic_vector(21 downto 0);
signal mcData_in : std_logic_vector(15 downto 0);
signal mcData_out : std_logic_vector(15 downto 0);
signal mcBusy : std_logic;
signal ramCmd : std_logic_vector(2 downto 0);
signal ramClk : std_logic;
signal ramRAS : std_logic;
signal ramCAS : std_logic;
signal ramWE : std_logic;
signal ramAddr : std_logic_vector(11 downto 0);
signal ramData_io : std_logic_vector(15 downto 0);
signal ramBank_out : std_logic_vector(1 downto 0);
signal ramLDQM : std_logic;
signal ramUDQM : std_logic;
begin
-- Instantiate the unit under test
uut: memctrl
generic map(
INIT_COUNT => "0" & x"004"
)
port map(
mcRst_in => mcRst,
mcClk_in => mcClk,
mcOp_in => mcOp,
mcAddr_in => mcAddr,
mcData_in => mcData_in,
mcData_out => mcData_out,
mcBusy_out => mcBusy,
ramRAS_out => ramRAS,
ramCAS_out => ramCAS,
ramWE_out => ramWE,
ramAddr_out => ramAddr,
ramData_io => ramData_io,
ramBank_out => ramBank_out,
ramLDQM_out => ramLDQM,
ramUDQM_out => ramUDQM
);
ramCmd <= ramRAS & ramCAS & ramWE;
-- Drive the unit under test. Read stimulus from stimulus.txt and write results to results.txt
process
variable inLine, outLine : line;
variable outData : std_logic;
file inFile : text open read_mode is "stimulus.txt";
file outFile : text open write_mode is "results.txt";
function to_op(c : character) return MCOpType is begin
case c is
when 'R' =>
return MC_RD;
when 'W' =>
return MC_WR;
when others =>
return MC_NOP;
end case;
end function;
begin
mcClk <= '0';
ramClk <= '0';
mcRst <= '1';
mcOp <= MC_NOP;
mcAddr <= (others => 'X');
mcData_in <= (others => 'X');
ramData_io <= (others => 'X');
wait for 10 ns;
ramClk <= '1';
wait for 4 ns;
mcClk <= '1';
wait for 6 ns;
ramClk <= '0';
wait for 4 ns;
mcRst <= '0';
while ( not endfile(inFile) ) loop
mcClk <= '0';
wait for 6 ns;
ramClk <= '1';
wait for 4 ns;
mcClk <= '1';
readline(inFile, inLine);
while ( inLine.all(1) = '#' ) loop
readline(inFile, inLine);
end loop;
mcOp <= to_op(inLine.all(1));
mcAddr <= to_2(inLine.all(3)) & to_4(inLine.all(4)) & to_4(inLine.all(5)) & to_4(inLine.all(6)) & to_4(inLine.all(7)) & to_4(inLine.all(8));
mcData_in <= to_4(inLine.all(10)) & to_4(inLine.all(11)) & to_4(inLine.all(12)) & to_4(inLine.all(13));
ramData_io <= to_4(inLine.all(15)) & to_4(inLine.all(16)) & to_4(inLine.all(17)) & to_4(inLine.all(18));
wait for 6 ns;
outData := mcBusy;
ramClk <= '0';
wait for 4 ns;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait;
--assert false report "NONE. End of simulation." severity failure;
end process;
process
begin
loop
ramData_io <= (others => 'Z');
wait until ramRAS = '1' and ramCAS = '0' and ramWE = '1' and mcClk = '1';
wait until mcClk = '0';
wait until mcClk = '1';
wait until mcClk = '0';
wait until mcClk = '1';
wait for 6 ns;
ramData_io <= x"CAFE";
wait until mcClk = '0';
wait until mcClk = '1';
wait for 3 ns;
end loop;
end process;
end architecture;
|
gpl-3.0
|
1a96d2a6b1e1e1bd583fb5c3228fea87
| 0.627842 | 3.026685 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/user_processes/uf_likelihood.vhd
| 1 | 12,873 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : L I K E L I H O O D
--
--
-- One observation and the reference data are loaded into the
-- local RAM by the framework. The start addresses of this
-- observations will be set as input from the Framework.
--
-- The user of the framework knows how a observation is defined.
-- The user defines how to calculate the likelihood between the
-- observation and the reference data.
--
-- If the likelihood is calculated, the finished signal has to
-- be set to '1' and the likelihood value has to be set as ouput.
--
------------------------------------------------------------------------------------
entity uf_likelihood is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the likelihood user process
observation_loaded : in std_logic;
-- address of reference data
ref_data_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- address of observation
observation_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- size of one observation
observation_size : in integer;
-- if the likelihood is calculated, this signal has to be set to '1'
finished : out std_logic;
likelihood_value : out integer
);
end uf_likelihood;
architecture Behavioral of uf_likelihood is
component square_root_component
port (
x_in : in std_logic_VECTOR(31 downto 0);
nd : in std_logic;
x_out : out std_logic_VECTOR(16 downto 0);
rdy : out std_logic;
--rfd : out std_logic;
clk : in std_logic;
ce : in std_logic);
end component;
-- GRANULARITY
constant GRANULARITY : integer := 16384;
-- signals for likelihood values
signal likelihood : integer := 0;
signal old_likelihood : integer := 0;
-- states
type t_state is (initialize,
no_tracking_needed,
calc_likelihood,
load_old_likelihood,
finish
);
-- current state
signal state : t_state := initialize;
-- handshake signals
signal calc_likelihood_en : std_logic := '0';
signal calc_likelihood_done : std_logic := '0';
signal no_tracking_needed_en : std_logic := '0';
signal no_tracking_needed_done : std_logic := '0';
signal load_old_likelihood_en : std_logic := '0';
signal load_old_likelihood_done : std_logic := '0';
-- signals for square root component
signal x_in2 : natural := 0;
signal x_in : std_logic_vector(31 downto 0) := (others => '0');
signal x_out : std_logic_vector(16 downto 0) := (others => '0');
signal x_out2: natural := 0;
signal nd : std_logic := '0';
signal rdy : std_logic := '1';
--signal rfd : std_logic := '1';
signal ce : std_logic := '1';
signal current_observation_address : std_logic_vector(0 to C_BURST_AWIDTH-1);
signal max_frequency : integer := 0;
signal max_amplitude : integer := 0;
signal amplitude : integer := 0;
signal tmp_im : integer := 0;
signal tmp_re : integer := 0;
signal re : integer := 0;
signal im : integer := 0;
signal counter : integer := 0;
signal length1 : integer := 0;
-- '1' if no tracking is required, '0' else
signal no_tracking_is_needed : std_logic := '0';
signal no_tracking_needed_data : integer := 0;
-- burst ram connectors for processes
signal o_RAMAddr_calc : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_tracking : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_load : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- step for simulation
signal the_step : integer := 0;
begin
--! square root calculation
square_root: square_root_component
port map (x_in => x_in, nd => nd, x_out => x_out,
rdy => rdy, --rfd => rfd,
clk => clk, ce => ce);
-- burst ram interface
o_RAMClk <= clk;
o_RAMWE <= '0';
o_RAMData <= (others=>'0');
--! multiplexer for local ram address (outgoing signal)
mux_proc : process(calc_likelihood_en, no_tracking_needed_en, load_old_likelihood_en,
o_RAMAddr_calc, o_RAMAddr_tracking, o_RAMAddr_load
)
begin
if (calc_likelihood_en='1') then
o_RAMAddr <= o_RAMAddr_calc;
elsif (no_tracking_needed_en='1') then
o_RAMAddr <= o_RAMAddr_tracking;
elsif (load_old_likelihood_en='1') then
o_RAMAddr <= o_RAMAddr_load;
else
o_RAMAddr <= (others=>'0');
end if;
end process;
-- checks, if tracker is in no_tracking_needed
no_tracking_needed_proc : process(clk, reset, no_tracking_needed_en)
variable step : natural range 0 to 5;
variable current_observation_address2 : std_logic_vector(0 to C_BURST_AWIDTH-1);
--variable no_tracking_needed_data : integer;
begin
if reset = '1' or no_tracking_needed_en = '0' then
no_tracking_needed_done <= '0';
o_RAMAddr_tracking <= (others=>'0');
--the_step <= 0;
step := 0;
elsif rising_edge(clk) then
if (enable = '1') then
--the_step <= step;
case step is
when 0 =>
--! set address
current_observation_address2 := observation_address + observation_size;
step := step + 1;
when 1 =>
o_RAMAddr_tracking <= current_observation_address2 - 1;
step := step + 1;
when 2 =>
--! wait one cycle
step := step + 1;
when 3 =>
--! no tracking needed information
no_tracking_needed_data <= to_integer(signed(i_RAMData));
step := step + 1;
when 4 =>
--! set no_tracking_needed signal
if (no_tracking_needed_data > 0) then
no_tracking_is_needed <= '1';
else
no_tracking_is_needed <= '0';
end if;
step := step + 1;
when 5 =>
--! finished
no_tracking_needed_done <= '1';
end case;
end if;
end if;
end process;
--! loads old likelihood
load_old_likelihood_proc : process(clk, reset, load_old_likelihood_en)
variable step : natural range 0 to 4;
variable current_observation_address2 : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
if reset = '1' or load_old_likelihood_en = '0' then
load_old_likelihood_done <= '0';
o_RAMAddr_load <= (others=>'0');
step := 0;
elsif rising_edge(clk) then
if (enable = '1') then
case step is
when 0 =>
--! load observation length
current_observation_address2 := observation_address + observation_size;
step := step + 1;
when 1 =>
--! get initial phase data
o_RAMAddr_load <= current_observation_address2 - 2;
step := step + 1;
when 2 =>
--! wait one cycle
step := step + 1;
when 3 =>
--! read real and imaginary value
old_likelihood <= to_integer(signed(i_RAMData));
step := step + 1;
when 4 =>
--! finished
load_old_likelihood_done <= '1';
end case;
end if;
end if;
end process;
-- calculates likelihood
calc_likelihood_proc : process(clk, reset, calc_likelihood_en)
variable step : natural range 0 to 20;
begin
if (reset = '1' or calc_likelihood_en = '0') then
calc_likelihood_done <= '0';
o_RAMAddr_calc <= (others=>'0');
step := 0;
the_step <= step;
elsif (rising_edge(clk)) then
if (enable = '1') then
the_step <= step;
case step is
when 0 =>
--! load observation length
current_observation_address <= observation_address;
length1 <= observation_size - 2;
max_amplitude <= 0;
max_frequency <= 0;
counter <= 0;
step := step + 1;
when 1 =>
--! get next fft value
o_RAMAddr_calc <= current_observation_address;
step := step + 1;
when 2 =>
--! wait one cycle
step := step + 1;
when 3 =>
--! read real and imaginary value
re <= to_integer(signed(i_RAMData( 0 to 15)));
im <= to_integer(signed(i_RAMData(16 to 31)));
step := step + 1;
when 4 =>
--! wait
step := step + 1;
when 5 =>
--! square real values
tmp_re <= re * re;
step := step + 1;
when 6 =>
--! wait a state between two multiplications
step := step + 1;
when 7 =>
--! wait a state between two multiplications
step := step + 1;
when 8 =>
--! square imaginary values
tmp_im <= im * im;
step := step + 1;
when 9 =>
--! wait a state between before the result is needed
step := step + 1;
when 10 =>
--! wait a state between before the result is needed
step := step + 1;
when 11 =>
--! add tmp results (= squared amplitude)
amplitude <= tmp_re + tmp_im;
step := step + 1;
when 12 =>
--! wait a state between before the result is needed
step := step + 1;
when 13 =>
--! calc squareroot, more fft values?
if (amplitude > max_amplitude) then
max_amplitude <= amplitude;
max_frequency <= counter;
end if;
if (counter < length1 - 1) then
-- load next value
current_observation_address <= current_observation_address + 1;
counter <= counter + 1;
step := 1;
else
step := step + 1;
end if;
when 14 =>
--! set likelihood
if ((max_frequency > 0) and (max_frequency < 29)) then --for length1=128
-- calculate sqrt
x_in2 <= max_amplitude;
step := step + 1;
else
likelihood <= 5;
step := step + 6;
end if;
when 15 =>
-- put value into sqrt component
x_in <= std_logic_vector(to_unsigned(x_in2, 32));
nd <= '1';
step := step + 1;
when 16 =>
-- wait for result
nd <= '0';
if (rdy='1') then
step := step + 1;
end if;
when 17 =>
-- put result to likelihood
x_out2 <= to_integer(unsigned(x_out));
step := step + 1;
when 18 =>
-- wait
step := step + 1;
when 19 =>
-- likelihood = sqrt(max_amplitude)
likelihood <= x_out2;
step := step + 1;
-- when 13 =>
-- --! set likelihood
-- if ((max_frequency > 0) and (max_frequency < 29)) then
-- likelihood <= max_amplitude;
-- else
-- likelihood <= 5;
-- end if;
-- step := 15;
--
-- when 14 =>
-- step := step + 1;
--
-- when 15 =>
-- step := step + 1;
--
-- when 16 =>
-- step := step + 1;
--
-- when 17 =>
-- step := step + 1;
-- -- end debug
when 20 =>
--! finished
calc_likelihood_done <= '1';
end case;
end if;
end if;
end process;
----------------------------------------------------------------------
----------------------------------------------------------------------
--
-- Likelihood calculation
--
-- (1) Initialize
--
-- (2) check, if Beat tracker is needs to track (calc likelihood)
-- yes: go to step 3
-- no: go to step 4
--
-- (3) calculate likelihood, go to step 5
--
-- (4) load old likelihood value
--
-- (5) give back likelihood value, finish
--
----------------------------------------------------------------------
----------------------------------------------------------------------
ce <= enable;
state_proc : process(clk, reset)
begin
if (reset = '1') then
state <= initialize;
finished <= '0';
elsif rising_edge(clk) then
if init = '1' then
finished <= '0';
state <= initialize;
elsif enable = '1' then
case state is
when initialize =>
--! initialize
finished <= '0';
if (observation_loaded = '1') then
no_tracking_needed_en <= '1';
state <= no_tracking_needed;
end if;
when no_tracking_needed =>
--! check if tracker is in initial state
if (no_tracking_needed_done = '1') then
no_tracking_needed_en <= '0';
if (no_tracking_is_needed='1') then
load_old_likelihood_en <= '1';
state <= load_old_likelihood;
else
calc_likelihood_en <= '1';
state <= calc_likelihood;
end if;
end if;
when calc_likelihood =>
--! calculate likelihood
if (calc_likelihood_done = '1') then
calc_likelihood_en <= '0';
likelihood_value <= likelihood;
state <= finish;
end if;
when load_old_likelihood =>
--! load old likelihood
if (load_old_likelihood_done = '1') then
load_old_likelihood_en <= '0';
likelihood_value <= old_likelihood;
state <= finish;
end if;
when finish =>
--! write finished signal and likelihood value
finished <= '1';
if (observation_loaded = '1') then
state <= initialize;
end if;
when others =>
state <= initialize;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
9cbf1126c90b9c32935bee7c37edadf8
| 0.578109 | 3.225507 | false | false | false | false |
luebbers/reconos
|
demos/pr_demo/src/sub.vhd
| 1 | 3,524 |
--!
--! \file sub.vhd
--!
--! Demo thread for partial reconfiguration
--!
--! \author Enno Luebbers <[email protected]>
--! \date 27.01.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 27.01.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sub is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 1 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end sub;
architecture Behavioral of sub is
-- OS synchronization state machine states
type t_state is (STATE_INIT, STATE_READ, STATE_WRITE, STATE_EXIT);
signal state : t_state := STATE_INIT;
-- address of data to process in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal result : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- calculate result in parallel
result <= data + 1 when C_SUB_NADD = 0 else data - 1;
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable next_state : t_state := STATE_INIT;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"12345678");
state <= STATE_INIT;
next_state := STATE_INIT;
done := false;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read target address from init data
when STATE_INIT =>
reconos_get_init_data_s(done, o_osif, i_osif, address);
next_state := STATE_READ;
-- read data from target address
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, address, data);
next_state := STATE_WRITE;
-- write result to target address
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, address, result);
next_state := STATE_EXIT;
-- terminate
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, C_RECONOS_SUCCESS);
when others =>
next_state := STATE_INIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
bef0f42cfaaea7b28f1e6500a38b651b
| 0.55874 | 3.625514 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/FPGAMonitor.vhd
| 1 | 7,103 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 17:18:33 02/21/2014
-- Design Name:
-- Module Name: FPGAMonitor - Behavioral
-- Project Name: Nexys4 User Demo
-- Target Devices:
-- Tool versions:
-- Description:
-- This module measures the FPGA temperature using the FPGA internal
-- XADC temperature monitor
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity FPGAMonitor is
Generic (CLOCKFREQ : natural := 100); -- input CLK frequency in MHz
Port ( CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
TEMP_O : out STD_LOGIC_VECTOR (11 downto 0));
end FPGAMonitor;
architecture Behavioral of FPGAMonitor is
component LocalRst
Generic ( RESET_PERIOD : natural := 4);
Port ( RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SRST_O : out STD_LOGIC);
end component;
constant DADDR_TEMP : std_logic_vector(6 downto 0) := "0000000";
constant DELAY : NATURAL := 10; --us
constant DELAY_CYCLES : NATURAL :=
natural(ceil(real(DELAY*CLOCKFREQ)));
type state_type is (stIdle, stReadRequest, stReadWait, stRead);
signal state, nstate : state_type := stIdle;
signal x_den, x_drdy, x_drdy_r : std_logic;
signal x_do, x_do_r : std_logic_vector(15 downto 0);
signal waitCnt : natural range 0 to DELAY_CYCLES := DELAY_CYCLES;
signal waitCntEn, SysRst : std_logic;
begin
----------------------------------------------------------------------------------
-- Sync Reset
----------------------------------------------------------------------------------
Sync_Reset : LocalRst
port map (
RST_I => RST_I,
CLK_I => CLK_I,
SRST_O => SysRst
);
----------------------------------------------------------------------------------
-- Instantiate XADC primitive, single channel (temperature), continuous mode
----------------------------------------------------------------------------------
XADC_INST : XADC
generic map(
INIT_40 => X"1000", -- config reg 0
INIT_41 => X"3f3f", -- config reg 1
INIT_42 => X"0400", -- config reg 2
INIT_48 => X"0100", -- Sequencer channel selection
INIT_49 => X"0000", -- Sequencer channel selection
INIT_4A => X"0000", -- Sequencer Average selection
INIT_4B => X"0000", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"b5ed", -- Temp alarm trigger
INIT_51 => X"57e4", -- Vccint upper alarm limit
INIT_52 => X"a147", -- Vccaux upper alarm limit
INIT_53 => X"ca33", -- Temp alarm OT upper
INIT_54 => X"a93a", -- Temp alarm reset
INIT_55 => X"52c6", -- Vccint lower alarm limit
INIT_56 => X"9555", -- Vccaux lower alarm limit
INIT_57 => X"ae4e", -- Temp alarm OT reset
INIT_58 => X"5999", -- Vbram upper alarm limit
INIT_5C => X"5111", -- Vbram lower alarm limit
SIM_DEVICE => "7SERIES"
)
port map (
CONVST => '0',
CONVSTCLK => '0',
DADDR(6 downto 0) => DADDR_TEMP,
DCLK => CLK_I,
DEN => x_den,
DI(15 downto 0) => x"0000",
DWE => '0',
RESET => '0',
VAUXN(15 downto 0) => x"0000",
VAUXP(15 downto 0) => x"0000",
ALM => open,
BUSY => open,
CHANNEL => open,
DO(15 downto 0) => x_do,
DRDY => x_drdy,
EOC => open,
EOS => open,
JTAGBUSY => open,
JTAGLOCKED => open,
JTAGMODIFIED => open,
OT => open,
MUXADDR => open,
VN => '0',
VP => '0'
);
----------------------------------------------------------------------------------
-- Register Temperature
----------------------------------------------------------------------------------
process(CLK_I)
begin
if Rising_Edge(CLK_I) then
if (x_drdy_r = '1') then
TEMP_O <= x_do_r(15 downto 4);
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Register XADC outputs
----------------------------------------------------------------------------------
process(CLK_I)
begin
if Rising_Edge(CLK_I) then
x_do_r <= x_do;
x_drdy_r <= x_drdy;
end if;
end process;
----------------------------------------------------------------------------------
-- Delay Counter
----------------------------------------------------------------------------------
Wait_CNT: process (CLK_I)
begin
if Rising_Edge(CLK_I) then
if (waitCntEn = '0') then
waitCnt <= DELAY_CYCLES;
else
waitCnt <= waitCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Continuous temperature read FSM
----------------------------------------------------------------------------------
SYNC_PROC: process (CLK_I)
begin
if Rising_Edge(CLK_I) then
if (SysRst = '1') then
state <= stIdle;
else
state <= nstate;
end if;
end if;
end process;
OUTPUT_DECODE: process (state)
begin
x_den <= '0';
waitCntEn <= '0';
case (state) is
when stIdle =>
waitCntEn <= '1';
when stReadRequest =>
x_den <= '1';
when others =>
end case;
end process;
NEXT_STATE_DECODE: process (state)
begin
--declare default state for nstate to avoid latches
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (waitCnt = 0 and x_drdy_r = '0') then
nstate <= stReadRequest;
end if;
when stReadRequest =>
nstate <= stReadWait;
when stReadWait =>
if (x_drdy_r = '1') then
nstate <= stIdle;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
gpl-3.0
|
2bd642654151df72c1c9f92fe6391f2f
| 0.448402 | 4.341687 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/timebase.vhd
| 4 | 1,368 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accumulated
-- are equal to a specified parameter
entity TimeBase is
generic (N: in Natural := 12; VALUE: Natural := 1999);
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (N-1 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
signal RunningCounter : std_logic_vector(N-1 downto 0); -- this is the N bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= (others => '0');
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
|
gpl-2.0
|
9906d93edeada51a1ea4831836721d7f
| 0.658626 | 3.908571 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/bram_fifo.vhd
| 4 | 6,641 |
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BRAM_FIFO is
generic (
C_DATA_BITS : integer := 32;
C_ADDR_BITS : integer := 9
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Level : out std_logic_vector(0 to C_ADDR_BITS);
Full : out std_logic;
HalfFull : out std_logic;
HalfEmpty : out std_logic;
Overflow : out std_logic;
Underflow : out std_logic;
Empty : out std_logic
);
end entity BRAM_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of BRAM_FIFO is
component RAMB16_S36_S36
port(
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(8 downto 0);
ADDRB : in std_logic_vector(8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal in_address, out_address : unsigned(9 downto 0) := (others => '0');
signal addra, addrb : std_logic_vector(9 downto 0);
signal addr_diff : unsigned(9 downto 0);
signal overflow_i, underflow_i : std_logic;
signal empty_i, full_i : std_logic;
begin -- architecture IMP
addra <= CONV_STD_LOGIC_VECTOR(in_address,in_address'length);
addrb <= CONV_STD_LOGIC_VECTOR(out_address,out_address'length);
U1: RAMB16_S36_S36
port map(
DOA => open,
DOB => Data_Out,
DOPA => open,
DOPB => open,
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
CLKA => Clk,
CLKB => Clk,
DIA => Data_In,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => Reset,
SSRB => Reset,
WEA => FIFO_Write,
WEB => '0'
);
in_address_PROCESS: process (Clk,FIFO_Write)
begin
if Reset = '1' then
in_address <= (others => '0');
elsif (Clk'event and Clk='1') then
if (FIFO_Write = '1' and Clear_FIFO = '0') then
in_address <= in_address + 1;
elsif (Clear_FIFO = '1') then
in_address <= (others => '0');
end if;
end if;
end process;
out_address_PROCESS: process (Clk)
begin
if Reset = '1' then
out_address <= (others => '1');
elsif (Clk'event and Clk='1') then
if (FIFO_Read = '1' and Clear_FIFO = '0') then
out_address <= out_address + 1;
elsif (Clear_FIFO = '1') then
out_address <= (others => '1');
end if;
end if;
end process;
overflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
overflow_i <= '0';
elsif Full_i = '1' and FIFO_Write = '1' then
overflow_i <= '1';
end if;
end if;
end process;
overflow <= overflow_i;
underflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
underflow_i <= '0';
elsif Empty_i = '1' and FIFO_Read = '1' then
underflow_i <= '1';
end if;
end if;
end process;
underflow <= underflow_i;
addr_diff <= in_address - out_address - 1;
FIFO_Level <= CONV_STD_LOGIC_VECTOR(addr_diff,addr_diff'length);
HalfFull <= addr_diff(8);
HalfEmpty <= not addr_diff(8);
Empty_i <= '1' when addr_diff = 0 else '0';
Full_i <= '1' when (addr_diff = 512) else '0';
Empty <= Empty_i;
Full <= Full_i;
end architecture IMP;
|
gpl-3.0
|
91e59336acee5e042d8a16f0a2f778fc
| 0.4415 | 3.777588 | false | false | false | false |
luebbers/reconos
|
core/pcores/burst_ram_v2_01_a/hdl/vhdl/bram_wrapper.vhd
| 1 | 8,795 |
--
-- \file bram_wrapper.vhd
--
-- Parametrizable BRAM wrapper for use in burst_ram.vhd
--
-- Instantiates RAMB16_Sn_Sm blocks based on generics.
-- The genrics G_PORTA_AWIDTH and G_PORTB_AWIDTH must be set so that together
-- with the selected data width the RAM will hold 16384 bits. That is,
-- the following equations must be true:
--
-- G_PORTA_DWIDTH = 2**(14-G_PORTA_AWIDTH);
-- G_PORTB_DWIDTH = 2**(14-G_PORTB_AWIDTH);
--
-- See table below for address width (in parentheses).
--
-- Currently supported generic combinations:
--
-- G_PORTA_DWIDTH (AWIDTH) | G_PORTB_DWIDTH (AWIDTH) | instantiated BRAM
-- ---------------------------------------------------------------------
-- 1 (14) | 2 (13) | RAMB16_S1_S2
-- 2 (13) | 4 (12) | RAMB16_S2_S4
-- 4 (12) | 8 (11) | RAMB16_S4_S9
-- 8 (11) | 16 (10) | RAMB16_S9_S18
-- 16 (10) | 32 (9) | RAMB16_S18_S36
--
-- 1 (14) | 1 (14) | RAMB16_S1_S1
-- 2 (13) | 2 (13) | RAMB16_S2_S2
-- 4 (12) | 4 (12) | RAMB16_S4_S4
-- 8 (11) | 8 (11) | RAMB16_S9_S9
-- 16 (10) | 16 (10) | RAMB16_S18_S18
-- 32 (9) | 32 (9) | RAMB16_S36_S36
--
-- RAMB16 generics are left at their defaults. No parity bits are supported.
--
-- \author Enno Luebbers <[email protected]>
-- \date 09.05.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bram_wrapper is
generic (
G_PORTA_DWIDTH : natural := 8;
G_PORTB_DWIDTH : natural := 16;
G_PORTA_AWIDTH : natural := 11;
G_PORTB_AWIDTH : natural := 10
);
port (
DOA : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
DOB : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
ADDRA : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
ADDRB : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
DIB : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic;
WEB : in std_logic
);
end bram_wrapper;
architecture Behavioral of bram_wrapper is
-- derived constants
constant C_PORTA_DWIDTH : natural := 2**(14-G_PORTA_AWIDTH);
constant C_PORTB_DWIDTH : natural := 2**(14-G_PORTB_AWIDTH);
begin
-- check generics
assert C_PORTA_DWIDTH = G_PORTA_DWIDTH
report "PORTA parameters don't match"
severity failure;
assert C_PORTB_DWIDTH = G_PORTB_DWIDTH
report "PORTB parameters don't match"
severity failure;
-- instantiate BRAM
s1_s2: if (G_PORTA_DWIDTH = 1) and (G_PORTB_DWIDTH = 2) generate
bram_inst : RAMB16_S1_S2
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s2_s4: if (G_PORTA_DWIDTH = 2) and (G_PORTB_DWIDTH = 4) generate
bram_inst : RAMB16_S2_S4
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s4_s9: if (G_PORTA_DWIDTH = 4) and (G_PORTB_DWIDTH = 8) generate
bram_inst : RAMB16_S4_S9
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPB => "0" );
end generate;
s9_s18: if (G_PORTA_DWIDTH = 8) and (G_PORTB_DWIDTH = 16) generate
bram_inst : RAMB16_S9_S18
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "0", DIPB => "00" );
end generate;
s18_s36: if (G_PORTA_DWIDTH = 16) and (G_PORTB_DWIDTH = 32) generate
bram_inst : RAMB16_S18_S36
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "00", DIPB => "0000" );
end generate;
s1_s1: if (G_PORTA_DWIDTH = 1) and (G_PORTB_DWIDTH = 1) generate
bram_inst : RAMB16_S1_S1
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s2_s2: if (G_PORTA_DWIDTH = 2) and (G_PORTB_DWIDTH = 2) generate
bram_inst : RAMB16_S2_S2
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s4_s4: if (G_PORTA_DWIDTH = 4) and (G_PORTB_DWIDTH = 4) generate
bram_inst : RAMB16_S4_S4
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s9_s9: if (G_PORTA_DWIDTH = 8) and (G_PORTB_DWIDTH = 8) generate
bram_inst : RAMB16_S9_S9
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "0", DIPB => "0" );
end generate;
s18_s18: if (G_PORTA_DWIDTH = 16) and (G_PORTB_DWIDTH = 16) generate
bram_inst : RAMB16_S18_S18
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "00", DIPB => "00" );
end generate;
s36_s36: if (G_PORTA_DWIDTH = 32) and (G_PORTB_DWIDTH = 32) generate
bram_inst : RAMB16_S36_S36
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "0000", DIPB => "0000" );
end generate;
end Behavioral;
|
gpl-3.0
|
a8927bc1a32128483945c6837f960324
| 0.497442 | 3.670701 | false | false | false | false |
BenBoZ/realtimestagram
|
src/vignette.vhd
| 2 | 6,292 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
--! <!------------------------------------------------------------------------------>
--! <!------------------------------------------------------------------------------>
--! \class vignette
--! \brief Creates a faded vignette around the image
--!
--! \image html vignette.png
--!
--! \dot
--! digraph vignette{
--!
--! graph [rankdir=LR, splines=ortho, sep=5];
--! edge [penwidth=2.2, arrowsize=.5]
--! node [height=0.25, style=filled, fontname=sans]
--!
--! /* single or multibit registers */
--!
--!
--! subgraph inputs {
--! node [fontcolor=white, fontname=serif, fillcolor=gray32, shape=box, tailport=e]
--! rank=same; clk rst enable hcount vcount pixel_i
--! }
--!
--! subgraph cluster_component {
--!
--! color=gray64
--! label="vignette";
--! fontcolor=black;
--! fontname=sans;
--!
--! subgraph operators{
--! node [ shape=circle, fillcolor=white, fontcolor=black, labelloc=c, fixedsize=true, tailport=e]
--! and0 [label="&"]
--!
--! mult0 [label="x"]
--! mult1 [label="x"]
--! }
--!
--! subgraph registers{
--! node [fontcolor=white, fontname=serif, fillcolor=gray32, shape=box, headport=w]
--! pixel_i_reg0 [label="p0"]
--! pixel_i_reg1 [label="p1"]
--! }
--!
--! subgraph function_blocks{
--! node [ height=1, shape=box, fillcolor=gray96, fontcolor=black, headport=w, tailport=e]
--! lut_x [label="lut x"]
--! lut_y [label="lut y"]
--! }
--! }
--!
--! subgraph output{
--! node [fontcolor=white, fontname=serif, fillcolor=gray32, shape=box, headport=w]
--! rank=same; pixel_o
--! }
--!
--! clk -> and0
--! enable -> and0
--! rst -> and0 [arrowhead=odot, arrowsize=0.6]
--!
--! and0 -> lut_x
--! hcount -> lut_x -> mult0
--!
--! and0 -> lut_y
--! vcount -> lut_y -> mult0
--!
--! pixel_i -> pixel_i_reg0 -> pixel_i_reg1 -> mult1
--! mult0 -> mult1 -> pixel_o
--! }
--! \enddot
--!
--! <!------------------------------------------------------------------------------>
--! <!------------------------------------------------------------------------------>
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_cunt port width
use ieee.math_real.all;
use work.curves_pkg.all;
--============================================================================--
--!
--!
--!
--!
entity vignette is
generic (
wordsize: integer; --! input image wordsize in bits
width: integer; --! width of input image
height: integer; --! height of input image
lut_x: array_pixel; --! pre generated lookup table
lut_y: array_pixel --! pre generated lookup table
);
port (
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
--! x-coordinate of input pixel
h_count: in std_logic_vector((integer(ceil(log2(real(width))))-1) downto 0);
--! y-coordinate of input pixel
v_count: in std_logic_vector((integer(ceil(log2(real(height))))-1) downto 0);
pixel_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_o: out std_logic_vector((wordsize-1) downto 0) --! the output pixel
);
end entity;
--============================================================================--
architecture behavioural of vignette is
-- signal declarations
signal lut_value_x: std_logic_vector((wordsize-1) downto 0); --! Value from LUT_x
signal lut_value_y: std_logic_vector((wordsize-1) downto 0); --! Value from LUT_y
signal lut_x_lut_y: natural range 0 to 2**(2*wordsize); --! LUT_x * LUT_y
signal p0: natural range 0 to 2**(wordsize); --! buffered pix_in
signal p1: natural range 0 to 2**(wordsize); --! buffered pix_in
begin
--! \brief clocked process that adds an vignette to an image using precalculated LUTs
--! \param[in] clk clock
--! \param[in] rst asynchronous reset
curve_adjustment : process(clk, rst)
variable pixel_o_slv : std_logic_vector(3*wordsize-1 downto 0) := (others => '0');
begin
if rst = '1' then
lut_value_x <= (others => '0');
lut_value_y <= (others => '0');
lut_x_lut_y <= 0;
p0 <= 0;
p1 <= 0;
pixel_o <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
p0 <= to_integer(unsigned(pixel_i));
lut_value_x <= lut_x(to_integer(unsigned(h_count)));
lut_value_y <= lut_y(to_integer(unsigned(v_count)));
p1 <= p0;
lut_x_lut_y <= to_integer(unsigned(lut_value_x)) * to_integer(unsigned(lut_value_y));
pixel_o_slv := std_logic_vector(to_unsigned(lut_x_lut_y * p1, 3*wordsize));
pixel_o <= pixel_o_slv(3*wordsize-1 downto 2*wordsize);
else
pixel_o <= (others => '0');
end if; -- end if enable = '1'
end if; -- end if rst = '1'
end process;
end architecture;
--============================================================================--
|
gpl-2.0
|
b1ad43fc87138296611844dfda63b6e1
| 0.500318 | 3.820279 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/physical/v6_gtxwizard_top.vhd
| 1 | 13,796 |
-------------------------------------------------------------------------------
-- Title : Top-level GTX wrapper for Ethernet MAC
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : v6_gtxwizard_top.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------
-- Description: This is the top-level GTX wrapper. It
-- instantiates the lower-level wrappers produced by
-- the Virtex-6 FPGA GTX Wrapper Wizard.
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity v6_gtxwizard_top is
port (
RESETDONE : out std_logic;
ENMCOMMAALIGN : in std_logic;
ENPCOMMAALIGN : in std_logic;
LOOPBACK : in std_logic;
POWERDOWN : in std_logic;
RXUSRCLK2 : in std_logic;
RXRESET : in std_logic;
TXCHARDISPMODE : in std_logic;
TXCHARDISPVAL : in std_logic;
TXCHARISK : in std_logic;
TXDATA : in std_logic_vector (7 downto 0);
TXUSRCLK2 : in std_logic;
TXRESET : in std_logic;
RXCHARISCOMMA : out std_logic;
RXCHARISK : out std_logic;
RXCLKCORCNT : out std_logic_vector (2 downto 0);
RXDATA : out std_logic_vector (7 downto 0);
RXDISPERR : out std_logic;
RXNOTINTABLE : out std_logic;
RXRUNDISP : out std_logic;
RXBUFERR : out std_logic;
TXBUFERR : out std_logic;
PLLLKDET : out std_logic;
TXOUTCLK : out std_logic;
RXELECIDLE : out std_logic;
TXN : out std_logic;
TXP : out std_logic;
RXN : in std_logic;
RXP : in std_logic;
CLK_DS : in std_logic;
PMARESET : in std_logic
);
end v6_gtxwizard_top;
architecture wrapper of v6_gtxwizard_top is
component V6_GTXWIZARD
generic
(
-- Simulation attributes
WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 1
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
GTX0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
GTX0_RXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
GTX0_TXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
GTX0_RXCHARISCOMMA_OUT : out std_logic;
GTX0_RXCHARISK_OUT : out std_logic;
GTX0_RXDISPERR_OUT : out std_logic;
GTX0_RXNOTINTABLE_OUT : out std_logic;
GTX0_RXRUNDISP_OUT : out std_logic;
------------------- Receive Ports - Clock Correction Ports -----------------
GTX0_RXCLKCORCNT_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
GTX0_RXENMCOMMAALIGN_IN : in std_logic;
GTX0_RXENPCOMMAALIGN_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
GTX0_RXRECCLK_OUT : out std_logic;
GTX0_RXRESET_IN : in std_logic;
GTX0_RXUSRCLK2_IN : in std_logic;
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GTX0_RXBUFRESET_IN : in std_logic;
GTX0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GTX0_RXELECIDLE_OUT : out std_logic;
GTX0_RXN_IN : in std_logic;
GTX0_RXP_IN : in std_logic;
------------------------ Receive Ports - RX PLL Ports ----------------------
GTX0_GTXRXRESET_IN : in std_logic;
GTX0_MGTREFCLKRX_IN : in std_logic;
GTX0_PLLRXRESET_IN : in std_logic;
GTX0_RXPLLLKDET_OUT : out std_logic;
GTX0_RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GTX0_TXCHARDISPMODE_IN : in std_logic;
GTX0_TXCHARDISPVAL_IN : in std_logic;
GTX0_TXCHARISK_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
GTX0_TXOUTCLK_OUT : out std_logic;
GTX0_TXRESET_IN : in std_logic;
GTX0_TXUSRCLK2_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
GTX0_TXN_OUT : out std_logic;
GTX0_TXP_OUT : out std_logic;
------------- Transmit Ports - TX Buffering and Phase Alignment ------------
GTX0_TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTX0_GTXTXRESET_IN : in std_logic;
GTX0_TXRESETDONE_OUT : out std_logic
);
end component;
----------------------------------------------------------------------
-- Signal declarations for GTX
----------------------------------------------------------------------
signal GND_BUS : std_logic_vector (55 downto 0);
signal RXBUFSTATUS_float : std_logic_vector(1 downto 0);
signal TXBUFSTATUS_float : std_logic;
signal clk_ds_i : std_logic;
signal pma_reset_i : std_logic;
signal reset_r : std_logic_vector(3 downto 0);
attribute ASYNC_REG : string;
attribute ASYNC_REG of reset_r : signal is "TRUE";
signal resetdone_tx_i : std_logic;
signal resetdone_tx_r : std_logic;
signal resetdone_rx_i : std_logic;
signal resetdone_rx_r : std_logic;
signal resetdone_i : std_logic;
begin
GND_BUS(55 downto 0) <= (others => '0');
--------------------------------------------------------------------
-- GTX PMA reset circuitry
--------------------------------------------------------------------
-- Locally buffer the output of the IBUFDS_GTXE1 for reset logic
bufr_clk_ds : BUFR port map (
I => CLK_DS,
O => clk_ds_i,
CE => '1',
CLR => '0'
);
process(PMARESET, clk_ds_i)
begin
if (PMARESET = '1') then
reset_r <= "1111";
elsif clk_ds_i'event and clk_ds_i = '1' then
reset_r <= reset_r(2 downto 0) & PMARESET;
end if;
end process;
pma_reset_i <= reset_r(3);
----------------------------------------------------------------------
-- Instantiate the Virtex-6 GTX
----------------------------------------------------------------------
-- Direct from the GTX Wizard output
v6_gtxwizard_inst : V6_GTXWIZARD
generic map (
WRAPPER_SIM_GTXRESET_SPEEDUP => 1
)
port map (
---------------------- Loopback and Powerdown Ports ----------------------
GTX0_LOOPBACK_IN(2 downto 1) => "00",
GTX0_LOOPBACK_IN(0) => LOOPBACK,
GTX0_RXPOWERDOWN_IN(0) => POWERDOWN,
GTX0_RXPOWERDOWN_IN(1) => POWERDOWN,
GTX0_TXPOWERDOWN_IN(0) => POWERDOWN,
GTX0_TXPOWERDOWN_IN(1) => POWERDOWN,
--------------------- Receive Ports - 8b10b Decoder ----------------------
GTX0_RXCHARISCOMMA_OUT => RXCHARISCOMMA,
GTX0_RXCHARISK_OUT => RXCHARISK,
GTX0_RXDISPERR_OUT => RXDISPERR,
GTX0_RXNOTINTABLE_OUT => RXNOTINTABLE,
GTX0_RXRUNDISP_OUT => RXRUNDISP,
----------------- Receive Ports - Clock Correction Ports -----------------
GTX0_RXCLKCORCNT_OUT => RXCLKCORCNT,
------------- Receive Ports - Comma Detection and Alignment --------------
GTX0_RXENMCOMMAALIGN_IN => ENMCOMMAALIGN,
GTX0_RXENPCOMMAALIGN_IN => ENPCOMMAALIGN,
----------------- Receive Ports - RX Data Path interface -----------------
GTX0_RXDATA_OUT => RXDATA,
GTX0_RXRECCLK_OUT => open,
GTX0_RXRESET_IN => RXRESET,
GTX0_RXUSRCLK2_IN => RXUSRCLK2,
------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GTX0_RXBUFRESET_IN => RXRESET,
GTX0_RXBUFSTATUS_OUT(2) => RXBUFERR,
GTX0_RXBUFSTATUS_OUT(1 downto 0) => RXBUFSTATUS_float,
----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GTX0_RXELECIDLE_OUT => RXELECIDLE,
GTX0_RXN_IN => RXN,
GTX0_RXP_IN => RXP,
-------------------- Receive Ports - RX PLL Ports ------------------------
GTX0_GTXRXRESET_IN => pma_reset_i,
GTX0_MGTREFCLKRX_IN => CLK_DS,
GTX0_PLLRXRESET_IN => pma_reset_i,
GTX0_RXPLLLKDET_OUT => PLLLKDET,
GTX0_RXRESETDONE_OUT => resetdone_rx_i,
-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GTX0_TXCHARDISPMODE_IN => TXCHARDISPMODE,
GTX0_TXCHARDISPVAL_IN => TXCHARDISPVAL,
GTX0_TXCHARISK_IN => TXCHARISK,
---------------- Transmit Ports - TX Data Path interface -----------------
GTX0_TXDATA_IN => TXDATA,
GTX0_TXOUTCLK_OUT => TXOUTCLK,
GTX0_TXRESET_IN => TXRESET,
GTX0_TXUSRCLK2_IN => TXUSRCLK2,
------------- Transmit Ports - TX Driver and OOB signalling --------------
GTX0_TXN_OUT => TXN,
GTX0_TXP_OUT => TXP,
----------- Transmit Ports - TX Buffering and Phase Alignment ------------
GTX0_TXBUFSTATUS_OUT(1) => TXBUFERR,
GTX0_TXBUFSTATUS_OUT(0) => TXBUFSTATUS_float,
-------------------- Transmit Ports - TX PLL Ports -----------------------
GTX0_GTXTXRESET_IN => pma_reset_i,
GTX0_TXRESETDONE_OUT => resetdone_tx_i
);
-- Register the Tx and Rx resetdone signals, and AND them to provide a
-- single RESETDONE output
process(TXUSRCLK2, TXRESET)
begin
if (TXRESET = '1') then
resetdone_tx_r <= '0';
elsif TXUSRCLK2'event and TXUSRCLK2 = '1' then
resetdone_tx_r <= resetdone_tx_i;
end if;
end process;
process(RXUSRCLK2, RXRESET)
begin
if (RXRESET = '1') then
resetdone_rx_r <= '0';
elsif RXUSRCLK2'event and RXUSRCLK2 = '1' then
resetdone_rx_r <= resetdone_rx_i;
end if;
end process;
resetdone_i <= resetdone_tx_r and resetdone_rx_r;
RESETDONE <= resetdone_i;
end wrapper;
|
gpl-3.0
|
b6b0ab0d296445052c2cad136cd98b9b
| 0.510003 | 4.505552 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_model.vhd
| 4 | 11,266 |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core
generic (
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Data_Valid : out std_logic;
AC97_Reg_Read : in std_logic;
AC97_Reg_Write : in std_logic;
AC97_Reg_Ready : out std_logic;
PCM_Playback_Left: in std_logic_vector(0 to 15);
PCM_Playback_Right: in std_logic_vector(0 to 15);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Record_Left: out std_logic_vector(0 to 15);
PCM_Record_Right: out std_logic_vector(0 to 15);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
New_Frame : out std_logic;
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_ready : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15);
signal PCM_Playback_Right: std_logic_vector(0 to 15);
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
uut_1 : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
generic map (
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Data_Valid => reg_read_data_valid,
AC97_Reg_Read => reg_read,
AC97_Reg_Write => reg_write,
AC97_Reg_Ready => reg_ready,
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
New_Frame => New_Frame,
CODEC_RDY => CODEC_RDY
);
-- simulate a reset
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
test_process: process
begin
test_no <= 0;
-- set default values
reg_addr <= (others => '0');
reg_write_data <= (others => '0');
reg_read <= '0';
reg_write <= '0';
PCM_Playback_Left <= (others => '0');
PCM_Playback_Right <= (others => '0');
PCM_Playback_Left_Valid <= '0';
PCM_Playback_Right_Valid <= '0';
-- 1. Wait until CODEC ready before doing anything
wait until CODEC_RDY='1' and clk'event and clk='1';
-- skip some time slots before performing a bus cycle
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Start at first sync pulse
wait until Sync'event and Sync='1';
--wait until clk'event and clk='1';
wait until clk'event and clk='1';
test_no <= 1;
-- send some playback data
PCM_Playback_Left <= X"8001";
PCM_Playback_Right <= X"0180";
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
wait until New_Frame'event and New_Frame='0';
test_no <= 2;
PCM_Playback_Left <= X"4002";
PCM_Playback_Right <= X"0240";
wait until New_Frame'event and New_Frame='0';
test_no <= 3;
-- send a read command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_read <= '1';
wait until New_Frame'event and New_Frame='0';
reg_read <= '0';
wait;
-- send a write command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_write_data <= X"5A5A";
reg_write <= '1';
wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
gpl-3.0
|
0491e05819857b2a6ad332f88d4d8951
| 0.517664 | 3.364994 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/vector_heater_a_v1_00_a/hdl/vhdl/user_logic.vhd
| 1 | 15,906 |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Feb 28 11:50:03 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
library vector_heater_a_v1_00_a;
use vector_heater_a_v1_00_a.big_register;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
C_REGISTER_LENGTH : integer := 10000;
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 8
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
--component big_register is
--generic
--(
-- C_REGISTER_LENGTH : integer := 10000
--);
--port
--(
-- clk : in std_logic;
-- rst : in std_logic;
-- ce : in std_logic; -- clock enable
-- xor_sig : out std_logic -- xor of all register bits
-- );
--end component;
-- signal vector : std_logic_vector(0 to C_VECTOR_LENGTH-1);
-- signal vector_ones : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signal vector_xor : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signal heater_active : std_logic;
signal ce : std_logic;
signal xor_sig : std_logic;
signal register_xor : std_logic_vector(0 to C_SLV_DWIDTH-1);
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg7 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 7);
signal slv_reg_read_sel : std_logic_vector(0 to 7);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
-- -- for active heater: invert vector and write number of 1s vector into output signal
-- change_vector : process (Bus2IP_Reset, Bus2IP_Clk) is
-- --variable result_temp : integer;
-- variable bit_temp : std_logic;
-- begin
-- if Bus2IP_Reset = '1' then
-- --vector <= (others=>'0');
-- --vector(0) <= '1';
-- --vector_ones <= (others=>'0');
-- --vector_xor <= (others=>'0');
-- elsif rising_edge(Bus2IP_Clk) then
-- if heater_active = '1' then
-- --vector <= not vector;
-- --result_temp := 0;
-- --bit_temp := '0';
-- --for i in 0 to C_VECTOR_LENGTH-1 loop
-- -- bit_temp := bit_temp xor vector(i);
-- -- --if (vector(i)='1') then
-- -- -- result_temp := result_temp + 1;
-- -- --end if;
-- --end loop;
-- --vector_xor <= (others=>'0');
-- --vector_xor(0) <= bit_temp;
-- ----vector_ones <= std_logic_vector(to_unsigned(result_temp, C_SLV_DWIDTH));
-- end if;
-- end if;
-- end process;
--big_register_1 : component big_register
big_register_1 : entity vector_heater_a_v1_00_a.big_register
generic map ( C_REGISTER_LENGTH => C_REGISTER_LENGTH )
port map ( clk => Bus2IP_Clk, rst => Bus2IP_Reset, ce => ce, xor_sig => xor_sig );
-- activate heater only when 0x1 is written in registor 0
activate_heater : process (Bus2IP_Reset, Bus2IP_Clk) is
begin
if Bus2IP_Reset = '1' then
ce <= '0';
elsif rising_edge(Bus2IP_Clk) then
if slv_reg0 = X"00000001" then
ce <= '1';
else
ce <= '0';
end if;
end if;
end process;
register_xor(0 to C_SLV_DWIDTH-2) <= (others=>'0');
register_xor(C_SLV_DWIDTH-1) <= xor_sig;
-- for the active heater: invert vector at each clock cycle
-- change_vector : process (Bus2IP_Reset, Bus2IP_Clk) is
-- begin
-- if Bus2IP_Reset = '1' then
-- vector <= (others=>'0');
-- elsif rising_edge(Bus2IP_Clk) then
-- if heater_active = '1' then
-- vector <= not vector;
-- end if;
-- end if;
-- end process;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 7);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 7);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7 ) is
begin
case slv_reg_read_sel is
when "10000000" => slv_ip2bus_data <= slv_reg0;
when "01000000" => slv_ip2bus_data <= slv_reg1;
when "00100000" => slv_ip2bus_data <= slv_reg2;
when "00010000" => slv_ip2bus_data <= slv_reg3;
when "00001000" => slv_ip2bus_data <= slv_reg4;
when "00000100" => slv_ip2bus_data <= slv_reg5;
when "00000010" => slv_ip2bus_data <= slv_reg6;
when "00000001" => slv_ip2bus_data <= register_xor; --vector_ones; --slv_reg7;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
gpl-3.0
|
df687d6b751f1c361d1f40372b73bc87
| 0.49912 | 3.73819 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/Ram2Ddr.vhd
| 1 | 23,669 |
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : ram2ddr.vhd
-- MODULE NAME : RAM to DDR2 Interface Converter with internal XADC
-- instantiation
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-02-04 Mihaita Nagy Created
-- 1.1 2014-04-04 Mihaita Nagy Fixed double registering write bug
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements a simple Static RAM to DDR2 interface
-- converter designed to be used with Digilent Nexys4-DDR board
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity Ram2Ddr is
port (
-- Common
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
ram_a : in std_logic_vector(26 downto 0);
ram_dq_i : in std_logic_vector(15 downto 0);
ram_dq_o : out std_logic_vector(15 downto 0);
ram_cen : in std_logic;
ram_oen : in std_logic;
ram_wen : in std_logic;
ram_ub : in std_logic;
ram_lb : in std_logic;
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end Ram2Ddr;
architecture Behavioral of Ram2Ddr is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component ddr
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
init_calib_complete : out std_logic);
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (stIdle, stPreset, stSendData, stSetCmdRd, stSetCmdWr,
stWaitCen);
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- ddr commands
constant CMD_WRITE : std_logic_vector(2 downto 0) := "000";
constant CMD_READ : std_logic_vector(2 downto 0) := "001";
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- state machine
signal cState, nState : state_type;
-- global signals
signal mem_ui_clk : std_logic;
signal mem_ui_rst : std_logic;
signal rst : std_logic;
signal rstn : std_logic;
signal sreg : std_logic_vector(1 downto 0);
-- ram internal signals
signal ram_a_int : std_logic_vector(26 downto 0);
signal ram_dq_i_int : std_logic_vector(15 downto 0);
signal ram_cen_int : std_logic;
signal ram_oen_int : std_logic;
signal ram_wen_int : std_logic;
signal ram_ub_int : std_logic;
signal ram_lb_int : std_logic;
-- ddr user interface signals
signal mem_addr : std_logic_vector(26 downto 0); -- address for current request
signal mem_cmd : std_logic_vector(2 downto 0); -- command for current request
signal mem_en : std_logic; -- active-high strobe for 'cmd' and 'addr'
signal mem_rdy : std_logic;
signal mem_wdf_rdy : std_logic; -- write data FIFO is ready to receive data (wdf_rdy = 1 & wdf_wren = 1)
signal mem_wdf_data : std_logic_vector(127 downto 0);
signal mem_wdf_end : std_logic; -- active-high last 'wdf_data'
signal mem_wdf_mask : std_logic_vector(15 downto 0);
signal mem_wdf_wren : std_logic;
signal mem_rd_data : std_logic_vector(127 downto 0);
signal mem_rd_data_end : std_logic; -- active-high last 'rd_data'
signal mem_rd_data_valid : std_logic; -- active-high 'rd_data' valid
signal calib_complete : std_logic; -- active-high calibration complete
------------------------------------------------------------------------
-- Signal attributes (debugging)
------------------------------------------------------------------------
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of cState : signal is "GRAY";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sreg : signal is "TRUE";
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Registering the active-low reset for the MIG component
------------------------------------------------------------------------
RSTSYNC: process(clk_200MHz_i)
begin
if rising_edge(clk_200MHz_i) then
sreg <= sreg(0) & rst_i;
rstn <= not sreg(1);
end if;
end process RSTSYNC;
------------------------------------------------------------------------
-- DDR controller instance
------------------------------------------------------------------------
Inst_DDR: ddr
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Inputs
sys_clk_i => clk_200MHz_i,
sys_rst => rstn,
-- user interface signals
app_addr => mem_addr,
app_cmd => mem_cmd,
app_en => mem_en,
app_wdf_data => mem_wdf_data,
app_wdf_end => mem_wdf_end,
app_wdf_mask => mem_wdf_mask,
app_wdf_wren => mem_wdf_wren,
app_rd_data => mem_rd_data,
app_rd_data_end => mem_rd_data_end,
app_rd_data_valid => mem_rd_data_valid,
app_rdy => mem_rdy,
app_wdf_rdy => mem_wdf_rdy,
app_sr_req => '0',
app_sr_active => open,
app_ref_req => '0',
app_ref_ack => open,
app_zq_req => '0',
app_zq_ack => open,
ui_clk => mem_ui_clk,
ui_clk_sync_rst => mem_ui_rst,
device_temp_i => device_temp_i,
init_calib_complete => calib_complete);
------------------------------------------------------------------------
-- Registering all inputs of the state machine to 'mem_ui_clk' domain
------------------------------------------------------------------------
REG_IN: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
ram_a_int <= ram_a;
ram_dq_i_int <= ram_dq_i;
ram_cen_int <= ram_cen;
ram_oen_int <= ram_oen;
ram_wen_int <= ram_wen;
ram_ub_int <= ram_ub;
ram_lb_int <= ram_lb;
end if;
end process REG_IN;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Register states
SYNC_PROCESS: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst = '1' then
cState <= stIdle;
else
cState <= nState;
end if;
end if;
end process SYNC_PROCESS;
-- Next state logic
NEXT_STATE_DECODE: process(cState, calib_complete, ram_cen_int,
mem_rdy, mem_wdf_rdy)
begin
nState <= cState;
case(cState) is
-- If calibration is done successfully and CEN is
-- deasserted then start a new transaction
when stIdle =>
if ram_cen_int = '0' and
calib_complete = '1' then
nState <= stPreset;
end if;
-- In this state we store the address and data to
-- be written or the address to read from. We need
-- this additional state to make sure that all input
-- transitions are fully settled and registered
when stPreset =>
if ram_wen_int = '0' then
nState <= stSendData;
elsif ram_oen_int = '0' then
nState <= stSetCmdRd;
end if;
-- In a write transaction the data it written first
-- giving higher priority to 'mem_wdf_rdy' frag over
-- 'mem_rdy'
when stSendData =>
if mem_wdf_rdy = '1' then
nState <= stSetCmdWr;
end if;
-- Sending the read command and wait for the 'mem_rdy'
-- frag to be asserted (in case it's not)
when stSetCmdRd =>
if mem_rdy = '1' then
nState <= stWaitCen;
end if;
-- Sending the write command after the data has been
-- written to the controller FIFO and wait ro the
-- 'mem_rdy' frag to be asserted (in case it's not)
when stSetCmdWr =>
if mem_rdy = '1' then
nState <= stWaitCen;
end if;
-- After sending all the control signals and data, we
-- wait for the external CEN to signal transaction
-- end
when stWaitCen =>
if ram_cen_int = '1' then
nState <= stIdle;
end if;
when others => nState <= stIdle;
end case;
end process;
------------------------------------------------------------------------
-- Generating the FIFO control and command signals according to the
-- current state of the FSM
------------------------------------------------------------------------
MEM_WR_CTL: process(cState)
begin
if cState = stSendData then
mem_wdf_wren <= '1';
mem_wdf_end <= '1';
else
mem_wdf_wren <= '0';
mem_wdf_end <= '0';
end if;
end process MEM_WR_CTL;
MEM_CTL: process(cState)
begin
if cState = stSetCmdRd then
mem_en <= '1';
mem_cmd <= CMD_READ;
elsif cState = stSetCmdWr then
mem_en <= '1';
mem_cmd <= CMD_WRITE;
else
mem_en <= '0';
mem_cmd <= (others => '0');
end if;
end process MEM_CTL;
------------------------------------------------------------------------
-- Decoding the least significant 3 bits of the address and creating
-- accordingly the 'mem_wdf_mask'
------------------------------------------------------------------------
WR_DATA_MSK: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
case(ram_a_int(3 downto 1)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111111101";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111111110";
else -- 16-bit
mem_wdf_mask <= "1111111111111100";
end if;
when "001" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111110111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111111011";
else -- 16-bit
mem_wdf_mask <= "1111111111110011";
end if;
when "010" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111011111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111101111";
else -- 16-bit
mem_wdf_mask <= "1111111111001111";
end if;
when "011" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111101111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111110111111";
else -- 16-bit
mem_wdf_mask <= "1111111100111111";
end if;
when "100" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111110111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111011111111";
else -- 16-bit
mem_wdf_mask <= "1111110011111111";
end if;
when "101" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111011111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111101111111111";
else -- 16-bit
mem_wdf_mask <= "1111001111111111";
end if;
when "110" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1101111111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1110111111111111";
else -- 16-bit
mem_wdf_mask <= "1100111111111111";
end if;
when "111" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "0111111111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1011111111111111";
else -- 16-bit
mem_wdf_mask <= "0011111111111111";
end if;
when others => null;
end case;
end if;
end if;
end process WR_DATA_MSK;
------------------------------------------------------------------------
-- Registering write data and read/write address
------------------------------------------------------------------------
WR_DATA_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
mem_wdf_data <= ram_dq_i_int & ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int;
end if;
end if;
end process WR_DATA_ADDR;
WR_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
mem_addr <= ram_a_int(26 downto 4) & "0000";
end if;
end if;
end process WR_ADDR;
------------------------------------------------------------------------
-- Mask and output the read data from the FIFO
------------------------------------------------------------------------
RD_DATA: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stWaitCen and mem_rd_data_valid = '1' and
mem_rd_data_end = '1' then
case(ram_a_int(3 downto 1)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(15 downto 8) &
mem_rd_data(15 downto 8);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(7 downto 0) &
mem_rd_data(7 downto 0);
else -- 16-bit
ram_dq_o <= mem_rd_data(15 downto 0);
end if;
when "001" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(31 downto 24) &
mem_rd_data(31 downto 24);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(23 downto 16) &
mem_rd_data(23 downto 16);
else -- 16-bit
ram_dq_o <= mem_rd_data(31 downto 16);
end if;
when "010" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(47 downto 40) &
mem_rd_data(47 downto 40);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(39 downto 32) &
mem_rd_data(39 downto 32);
else -- 16-bit
ram_dq_o <= mem_rd_data(47 downto 32);
end if;
when "011" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(63 downto 56) &
mem_rd_data(63 downto 56);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(55 downto 48) &
mem_rd_data(55 downto 48);
else -- 16-bit
ram_dq_o <= mem_rd_data(63 downto 48);
end if;
when "100" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(79 downto 72) &
mem_rd_data(79 downto 72);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(71 downto 64) &
mem_rd_data(71 downto 64);
else -- 16-bit
ram_dq_o <= mem_rd_data(79 downto 64);
end if;
when "101" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(95 downto 88) &
mem_rd_data(95 downto 88);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(87 downto 80) &
mem_rd_data(87 downto 80);
else -- 16-bit
ram_dq_o <= mem_rd_data(95 downto 80);
end if;
when "110" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(111 downto 104) &
mem_rd_data(111 downto 104);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(103 downto 96) &
mem_rd_data(103 downto 96);
else -- 16-bit
ram_dq_o <= mem_rd_data(111 downto 96);
end if;
when "111" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(127 downto 120) &
mem_rd_data(127 downto 120);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(119 downto 112) &
mem_rd_data(119 downto 112);
else -- 16-bit
ram_dq_o <= mem_rd_data(127 downto 112);
end if;
when others => null;
end case;
end if;
end if;
end process RD_DATA;
end Behavioral;
|
gpl-3.0
|
adcedb92ef0c854f638902f0748d47d3
| 0.419156 | 4.134323 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/mq/hw/pcores/hw_task_v1_01_b/hdl/vhdl/hwt_mq.vhd
| 1 | 10,041 |
--!
--! \file hwt_mq.vhd
--!
--! POSIX message queue through MMIO'd burst RAM benchmark
--!
--! \author Enno Luebbers <[email protected]>
--! \date 24.11.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 24.11.2008 Enno Luebbers File adapted from mq automated test by Andreas
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_mq is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
o_inv_RAM : out std_logic; -- inverts the RAM output on the OSIF side
i_timebase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end entity;
architecture Behavioral of hwt_mq is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_MEM_PAD : std_logic_vector(C_BURST_AWIDTH-1 downto 0) := (others => '0');
constant C_MEM_SIZE : std_logic_vector(31 downto 0) := X"00000000" + ('1' & C_MEM_PAD);
constant C_DELAY : std_logic_vector(31 downto 0) := X"00002000"; -- 8192 cycles
type t_state is (
STATE_INIT,
STATE_FILL,
STATE_FILL_2,
STATE_FILL_3,
STATE_GET_STARTTIME_RECV,
STATE_MQ_RECEIVE,
STATE_GET_STOPTIME_RECV,
STATE_MQ_SEND,
STATE_GET_STOPTIME_SEND,
STATE_DELAY,
STATE_SEND_STARTTIME_RECV,
STATE_SEND_STOPTIME_RECV,
STATE_SEND_STARTTIME_SEND,
STATE_SEND_STOPTIME_SEND,
STATE_ERROR
);
constant C_MQ_A : std_logic_vector(31 downto 0) := X"00000000";
constant C_MQ_B : std_logic_vector(31 downto 0) := X"00000001";
constant C_MBOX_TIMES : std_logic_vector(31 downto 0) := X"00000002";
signal state : t_state;
signal counter : std_logic_vector(31 downto 0);
signal starttime_recv : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal stoptime_recv : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal starttime_send : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal stoptime_send : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
begin
o_RAMAddr <= counter(C_BURST_AWIDTH - 1 downto 1) & not counter(0);
--o_RAMData <= (others => '0');
o_RAMData(C_BURST_DWIDTH - C_BURST_AWIDTH to C_BURST_DWIDTH - 1) <= counter;
o_RAMClk <= clk;
state_proc: process( clk, reset )
variable done : boolean;
variable success : boolean;
variable errno : natural range 0 to 255;
variable len : std_logic_vector(31 downto 0);
variable tmp : std_logic_vector(31 downto 0);
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
counter <= (others => '0');
done := false;
success := false;
len := X"deadbeef";
o_inv_RAM <= '0';
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
counter <= (others => '0');
state <= STATE_FILL;
when STATE_FILL =>
-- clear burst RAM
counter <= counter + 1;
o_RAMWe <= '0';
state <= STATE_FILL_2;
when STATE_FILL_2 =>
if counter = C_MEM_SIZE then
state <= STATE_GET_STARTTIME_RECV;
counter <= (others => '0');
else
state <= STATE_FILL_3;
end if;
when STATE_FILL_3 =>
o_RAMWe <= '1';
state <= STATE_FILL;
when STATE_GET_STARTTIME_RECV =>
starttime_recv <= i_timebase;
state <= STATE_MQ_RECEIVE;
-- receive data from C_MQ_A
when STATE_MQ_RECEIVE =>
reconos_mq_receive(done,success,o_osif, i_osif,
C_MQ_A, X"00000000", len);
if done then
if success then
state <= STATE_GET_STOPTIME_RECV;
else
errno := 1;
state <= STATE_ERROR;
end if;
end if;
when STATE_GET_STOPTIME_RECV =>
stoptime_recv <= i_timebase;
starttime_send <= i_timebase;
state <= STATE_MQ_SEND;
-- send data to C_MQ_B
when STATE_MQ_SEND =>
o_inv_RAM <= '1'; -- invert the received data
reconos_mq_send(done,success,o_osif, i_osif,
C_MQ_B, X"00000000", len);
if done then
if success then
state <= STATE_GET_STOPTIME_SEND;
o_inv_RAM <= '0';
else
errno := 2;
state <= STATE_ERROR;
end if;
end if;
when STATE_GET_STOPTIME_SEND =>
stoptime_send <= i_timebase;
state <= STATE_DELAY;
when STATE_DELAY =>
-- wait so that we don't disturb the mq_receive in software
if counter >= C_DELAY then
counter <= (others => '0');
state <= STATE_SEND_STARTTIME_RECV;
else
counter <= counter + 1;
end if;
when STATE_SEND_STARTTIME_RECV =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_TIMES, starttime_recv);
if done then
if success then
state <= STATE_SEND_STOPTIME_RECV;
else
errno := 3;
state <= STATE_ERROR;
end if;
end if;
when STATE_SEND_STOPTIME_RECV =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_TIMES, stoptime_recv);
if done then
if success then
state <= STATE_SEND_STARTTIME_SEND;
else
errno := 3;
state <= STATE_ERROR;
end if;
end if;
when STATE_SEND_STARTTIME_SEND =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_TIMES, starttime_send);
if done then
if success then
state <= STATE_SEND_STOPTIME_SEND;
else
errno := 3;
state <= STATE_ERROR;
end if;
end if;
when STATE_SEND_STOPTIME_SEND =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_TIMES, stoptime_send);
if done then
if success then
state <= STATE_INIT;
else
errno := 3;
state <= STATE_ERROR;
end if;
end if;
when STATE_ERROR =>
reconos_thread_exit(o_osif, i_osif, STD_LOGIC_VECTOR(CONV_UNSIGNED(errno, C_OSIF_DATA_WIDTH)));
when others =>
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
bdb8f1c7a3f85bf1eb4fc149d8a8656d
| 0.388905 | 4.922059 | false | false | false | false |
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