repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
dries007/Basys3
|
VGA/VGA.srcs/sources_1/new/vga.vhd
| 1 | 5,005 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.math_real.all;
entity vga is
Port (
CLK_I : in STD_LOGIC;
VGA_HS_O : out STD_LOGIC;
VGA_VS_O : out STD_LOGIC;
VGA_RED_O : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE_O : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN_O : out STD_LOGIC_VECTOR (3 downto 0);
Y : out natural range 0 to 1280;
X : out natural range 0 to 1024;
R : in natural range 0 to 15;
G : in natural range 0 to 15;
B : in natural range 0 to 15
);
end vga;
architecture Behavioral of vga is
component clk_wiz_0
port
(
clk_in1 : in std_logic;
clk_out1 : out std_logic
);
end component;
--***1280x1024@60Hz***--
constant FRAME_WIDTH : natural := 1280;
constant FRAME_HEIGHT : natural := 1024;
constant H_FP : natural := 48; --H front porch width (pixels)
constant H_PW : natural := 112; --H sync pulse width (pixels)
constant H_MAX : natural := 1688; --H total period (pixels)
constant V_FP : natural := 1; --V front porch width (lines)
constant V_PW : natural := 3; --V sync pulse width (lines)
constant V_MAX : natural := 1066; --V total period (lines)
constant H_POL : std_logic := '1';
constant V_POL : std_logic := '1';
-- Pixel clock, in this case 108 MHz
signal pxl_clk : std_logic;
-- The active signal is used to signal the active region of the screen (when not blank)
signal active : std_logic;
-- Horizontal and Vertical counters
signal h_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
signal v_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
-- Pipe Horizontal and Vertical Counters
-- signal h_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0');
-- signal v_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0');
-- Horizontal and Vertical Sync
signal h_sync_reg : std_logic := not(H_POL);
signal v_sync_reg : std_logic := not(V_POL);
-- Pipe Horizontal and Vertical Sync
-- signal h_sync_reg_dly : std_logic := not(H_POL);
-- signal v_sync_reg_dly : std_logic := not(V_POL);
signal vga_red_reg : std_logic_vector(3 downto 0) := (others =>'0');
signal vga_green_reg : std_logic_vector(3 downto 0) := (others =>'0');
signal vga_blue_reg : std_logic_vector(3 downto 0) := (others =>'0');
begin
pixel_clock : clk_wiz_0 port map (clk_in1 => CLK_I, clk_out1 => pxl_clk);
-- Horizontal counter
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_cntr_reg = (H_MAX - 1)) then
h_cntr_reg <= (others =>'0');
else
h_cntr_reg <= h_cntr_reg + 1;
end if;
end if;
end process;
-- Vertical counter
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if ((h_cntr_reg = (H_MAX - 1)) and (v_cntr_reg = (V_MAX - 1))) then
v_cntr_reg <= (others =>'0');
elsif (h_cntr_reg = (H_MAX - 1)) then
v_cntr_reg <= v_cntr_reg + 1;
end if;
end if;
end process;
-- Horizontal sync
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_cntr_reg >= (H_FP + FRAME_WIDTH - 1)) and (h_cntr_reg < (H_FP + FRAME_WIDTH + H_PW - 1)) then
h_sync_reg <= H_POL;
else
h_sync_reg <= not(H_POL);
end if;
end if;
end process;
-- Vertical sync
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (v_cntr_reg >= (V_FP + FRAME_HEIGHT - 1)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT + V_PW - 1)) then
v_sync_reg <= V_POL;
else
v_sync_reg <= not(V_POL);
end if;
end if;
end process;
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_cntr_reg < FRAME_WIDTH and v_cntr_reg < FRAME_HEIGHT) then
X <= conv_integer(h_cntr_reg);
Y <= conv_integer(v_cntr_reg);
vga_red_reg <= conv_std_logic_vector(R, 4);
vga_green_reg <= conv_std_logic_vector(G, 4);
vga_blue_reg <= conv_std_logic_vector(B, 4);
else
vga_red_reg <= "0000";
vga_green_reg <= "0000";
vga_blue_reg <= "0000";
end if;
-- v_sync_reg_dly <= v_sync_reg;
-- h_sync_reg_dly <= h_sync_reg;
end if;
end process;
VGA_HS_O <= h_sync_reg;
VGA_VS_O <= v_sync_reg;
VGA_RED_O <= vga_red_reg;
VGA_GREEN_O <= vga_green_reg;
VGA_BLUE_O <= vga_blue_reg;
end Behavioral;
|
mit
|
7de6dd8d95e465d3802d0834e1d0b56f
| 0.519481 | 3.37037 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/IcapCTRL_v1_00_d/ise/icap/dcr_if.vhd
| 2 | 2,760 |
------------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.std_logic_arith.all;
------------------------------------------------------------------------------
-- Module and Port Declaration
------------------------------------------------------------------------------
entity dcr_if is
generic (
C_ON_INIT : std_logic_vector(31 downto 0) := X"0000_0000";
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := B"10_0000_0000"
);
port (
clk : in std_logic;
rst : in std_logic;
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
-- Registers
ctrl_reg : out std_logic_vector(31 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of clk : signal is "Clk";
attribute SIGIS of rst : signal is "Rst";
end entity dcr_if;
architecture IMP of dcr_if is
------------------------------------------------------------------------------
-- Signal Declaration
------------------------------------------------------------------------------
signal dcr_addr_hit : std_logic;
signal dcr_base_addr : std_logic_vector(9 downto 0);
signal dcr_read_access : std_logic;
signal read_data : std_logic_vector(31 downto 0);
signal Sl_dcrAck_sig : std_logic;
signal ctrl_reg_sig : std_logic_vector(31 downto 0);
begin
dcr_base_addr <= C_DCR_BASEADDR;
-- if the address specified by dcr_base_addr is the sane as the address received on DCR -> hit
dcr_addr_hit <= '1' when ( DCR_ABus(9 downto 1) = dcr_base_addr(9 downto 1) ) else '0';
DCR_1 : process(clk) is
begin
if clk'event and clk = '1' then
dcr_read_access <= DCR_Read and dcr_addr_hit;
Sl_dcrAck_sig <= (DCR_Read or DCR_Write) and dcr_addr_hit;
end if;
end process DCR_1;
DCR_2 : process(clk) is
begin
if clk'event and clk = '1' then
if (rst='1') then
ctrl_reg_sig <= C_ON_INIT;
elsif ( (DCR_Write = '1') and (Sl_dcrAck_sig = '0') and (dcr_addr_hit= '1') ) then
ctrl_reg_sig <= DCR_Sl_DBus;
end if;
end if;
end process DCR_2;
DCR_3 : process(clk) is
begin
if clk'event and clk = '1' then
if ( (DCR_Read = '1') and (Sl_dcrAck_sig = '0') and (dcr_addr_hit= '1') ) then
read_data <= ctrl_reg_sig;
end if;
end if;
end process DCR_3;
Sl_dcrDBus <= read_data when dcr_read_access = '1' else DCR_Sl_DBus;
Sl_dcrAck <= Sl_dcrAck_sig;
ctrl_reg <= ctrl_reg_sig;
end architecture IMP;
|
gpl-3.0
|
36507be5bd2a9d666936200bb7906eb1
| 0.525 | 3.22807 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/Stack/sim/Stack.vhd
| 1 | 5,755 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_9;
USE dist_mem_gen_v8_0_9.dist_mem_gen_v8_0_9;
ENTITY Stack IS
PORT (
a : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Stack;
ARCHITECTURE Stack_arch OF Stack IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Stack_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_9 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_9;
BEGIN
U0 : dist_mem_gen_v8_0_9
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 10,
C_DEFAULT_DATA => "0",
C_DEPTH => 1024,
C_HAS_CLK => 1,
C_HAS_D => 1,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 1,
C_MEM_INIT_FILE => "no_coe_file_loaded",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 1,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 0,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 16,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => d,
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
clk => clk,
we => we,
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END Stack_arch;
|
mit
|
e370289d0294827e3d419fcbe8a9fcf8
| 0.623805 | 3.41543 | false | false | false | false |
luebbers/reconos
|
support/threads/shared/line_addr_generator.vhd
| 1 | 5,725 |
--
-- \file line_addr_generator.vhd
--
-- Address generator for 3x3 kernel threads
--
-- \author Andreas Agne <[email protected]>
-- \date 21.11.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity line_addr_generator is
generic (
C_PIX_PER_LINE : integer := 320;
C_LINES_PER_FRAME : integer := 240;
C_PIX_AWIDTH : integer := 9;
C_LINE_AWIDTH : integer := 9;
C_BRAM_AWIDTH : integer := 11
);
Port (
rst : in std_logic;
next_line : in std_logic;
line_sel : in std_logic_vector (1 downto 0);
pix_sel : in std_logic_vector (C_PIX_AWIDTH - 1 downto 0);
frame_offset : out std_logic_vector (C_PIX_AWIDTH + C_LINE_AWIDTH - 1 downto 0);
bram_addr : out std_logic_vector(C_BRAM_AWIDTH - 1 downto 0);
last_line : out std_logic;
ready : out std_logic
);
end line_addr_generator;
architecture Behavioral of line_addr_generator is
constant C_FRAME_AWIDTH : integer := C_PIX_AWIDTH + C_LINE_AWIDTH;
constant C_LINE_INVALID : integer := 3;
signal last_line_dup : std_logic;
signal line_number : integer range 0 to C_LINES_PER_FRAME;
type t_state is ( LINE_INIT_A,
LINE_INIT_B,
LINE_INIT_C,
LINE_REPLACE_A,
LINE_REPLACE_B,
LINE_REPLACE_C );
signal state : t_state;
function get_local_line(lstate : t_state;
lsel : std_logic_vector (1 downto 0)) return integer is
begin
case lstate is
when LINE_REPLACE_A =>
case lsel is
when B"00" => return 0;
when B"01" => return 1;
when B"10" => return 2;
when others => return C_LINE_INVALID;
end case;
when LINE_REPLACE_B =>
case lsel is
when B"00" => return 1;
when B"01" => return 2;
when B"10" => return 0;
when others => return C_LINE_INVALID;
end case;
when LINE_REPLACE_C =>
case lsel is
when B"00" => return 2;
when B"01" => return 0;
when B"10" => return 1;
when others => return C_LINE_INVALID;
end case;
when others => return C_LINE_INVALID;
end case;
return C_LINE_INVALID;
end function;
function get_line_to_replace(lstate : t_state) return integer is
begin
case lstate is
when LINE_REPLACE_A => return 0;
when LINE_INIT_A => return 0;
when LINE_REPLACE_B => return 1;
when LINE_INIT_B => return 1;
when LINE_REPLACE_C => return 2;
when LINE_INIT_C => return 2;
end case;
return C_LINE_INVALID;
end function;
function get_ready(lstate : t_state)
return std_logic is
begin
case lstate is
when LINE_INIT_A => return '0';
when LINE_INIT_B => return '0';
when LINE_INIT_C => return '0';
when others => return '1';
end case;
return '0';
end function;
function get_next_state(lstate : t_state)
return t_state is
begin
case lstate is
when LINE_INIT_A => return LINE_INIT_B;
when LINE_INIT_B => return LINE_INIT_C;
when LINE_INIT_C => return LINE_REPLACE_A;
when LINE_REPLACE_A => return LINE_REPLACE_B;
when LINE_REPLACE_B => return LINE_REPLACE_C;
when LINE_REPLACE_C => return LINE_REPLACE_A;
end case;
end function;
procedure get_bram_addr(lstate : in t_state; writing : in std_logic;
lsel : in std_logic_vector (1 downto 0);
psel : in std_logic_vector (C_PIX_AWIDTH - 1 downto 0);
signal result : out std_logic_vector(C_BRAM_AWIDTH - 1 downto 0)) is
variable tmp : integer;
begin
if writing = '1' then
tmp := get_line_to_replace(lstate)*C_PIX_PER_LINE + CONV_INTEGER(psel);
result <= conv_std_logic_vector(tmp,C_BRAM_AWIDTH);
else
tmp := get_local_line(lstate, lsel)*C_PIX_PER_LINE + CONV_INTEGER(psel);
result <= conv_std_logic_vector(tmp,C_BRAM_AWIDTH);
end if;
end procedure;
begin
frame_offset <= conv_std_logic_vector(line_number*C_PIX_PER_LINE, C_FRAME_AWIDTH);
last_line <= last_line_dup;
ready <= get_ready(state) or last_line_dup;
get_bram_addr(state, next_line, line_sel, pix_sel,bram_addr);
state_proc_falling: process(next_line, rst)
begin
if rst = '1' then
last_line_dup <= '0';
state <= LINE_INIT_A;
line_number <= 0;
elsif falling_edge(next_line) then
if line_number = C_LINES_PER_FRAME - 1 then
last_line_dup <= '1';
state <= LINE_INIT_A;
else
last_line_dup <= '0';
state <= get_next_state(state);
end if;
if last_line_dup = '1' then
line_number <= 0;
else
line_number <= line_number + 1;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
9bf1cad5c516aab34d6a49869daa9ac5
| 0.628821 | 3.123295 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/user_processes/uf_extract_observation.vhd
| 1 | 25,751 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N
--
--
-- The user function calcualtes a observation for a particle
-- A pointer to the input data is given. The user process can
-- ask for data at a specific address.
--
-- Thus, all needed data can be loaded into the entity. Thus,
-- the observation can be calculated via input data. When no more
-- data is needed, the observation is stored into the local ram.
--
-- If the observation is stored in the ram, the finished signal has
-- to be set to '1'.
--
------------------------------------------------------------------------------------
entity uf_extract_observation is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input data address
input_data_address : in std_logic_vector(0 to 31);
input_data_needed : out std_logic;
-- get word data
word_data_en : in std_logic;
word_address : out std_logic_vector(0 to 31);
word_data : in std_logic_vector(0 to 31);
word_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end uf_extract_observation;
architecture Behavioral of uf_extract_observation is
-- fft component (uses radix-4 algorithm)
component xfft_v5_0
port (
clk : in std_logic;
ce : in std_logic;
sclr : in std_logic;
start : in std_logic;
xn_re : in std_logic_vector(15 downto 0);
xn_im : in std_logic_vector(15 downto 0);
fwd_inv : in std_logic;
fwd_inv_we : in std_logic;
scale_sch : in std_logic_vector(13 downto 0);
scale_sch_we : in std_logic;
rfd : out std_logic;
xn_index : out std_logic_vector(6 downto 0);
busy : out std_logic;
edone : out std_logic;
done : out std_logic;
dv : out std_logic;
xk_index : out std_logic_vector(6 downto 0);
xk_re : out std_logic_vector(15 downto 0);
xk_im : out std_logic_vector(15 downto 0)
);
end component;
-- signals for fft core
-- incoming signals
signal ce : std_logic := '0';
signal sclr : std_logic := '0';
signal start : std_logic := '0';
signal xn_re : std_logic_vector(15 downto 0) := (others => '0');
signal xn_im : std_logic_vector(15 downto 0) := (others => '0');
signal fwd_inv : std_logic := '1';
signal fwd_inv_we : std_logic := '0';
signal scale_sch : std_logic_vector(13 downto 0) := "01101010101010";
signal scale_sch_we : std_logic := '0';
--outgoing signals
signal rfd : std_logic;
signal xn_index : std_logic_vector(6 downto 0);
signal busy : std_logic;
signal edone : std_logic;
signal done : std_logic;
signal dv : std_logic;
signal xk_index : std_logic_vector(6 downto 0);
signal xk_re : std_logic_vector(15 downto 0);
signal xk_im : std_logic_vector(15 downto 0);
-- additional signals for fft
signal my_xn_index : std_logic_vector(6 downto 0);
signal address : std_logic_vector(0 to C_BURST_AWIDTH-1);
-- states
type t_state is (initialize,
load_parameter,
initial_phase,
interval,
calc_start_index,
get_measurement,
calc_fft,
write_no_tracking_needed,
finish
);
signal state : t_state := initialize;
-- is a new observation required
signal is_in_initial_phase : std_logic := '0';
signal is_in_interval : std_logic := '1';
signal no_tracking_is_needed : std_logic := '0';
-- handshake signals
signal initial_phase_en : std_logic := '0';
signal initial_phase_done : std_logic := '0';
signal interval_en : std_logic := '0';
signal interval_done : std_logic := '0';
signal calc_start_index_en : std_logic := '0';
signal calc_start_index_done : std_logic := '0';
signal get_measurement_en : std_logic := '0';
signal get_measurement_done : std_logic := '0';
signal calc_fft_en : std_logic := '0';
signal calc_fft_done : std_logic := '0';
signal write_no_tracking_needed_en : std_logic := '0';
signal write_no_tracking_needed_done : std_logic := '0';
signal load_parameter_en : std_logic := '0';
signal load_parameter_done : std_logic := '0';
-- burst ram access for processes
signal o_RAMAddr_initial : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_interval : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_get : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_fft : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_write : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_param : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMData_get : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
signal o_RAMData_fft : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
signal o_RAMData_write : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
signal o_RAMWE_get : std_logic := '0';
signal o_RAMWE_fft : std_logic := '0';
signal o_RAMWE_write : std_logic := '0';
signal observation_size : integer := 130;
signal measurement_size : integer := 8192;
signal start_index : integer := 0;
signal old_likelihood : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
signal interval_min : std_logic_vector(0 to 31) := (others => '0');
signal interval_max : std_logic_vector(0 to 31) := (others => '0');
signal next_beat : std_logic_vector(0 to 31) := (others => '0');
begin
-- fft core
my_fft_core : xfft_v5_0
port map (
clk => clk,
ce => ce,
sclr => sclr,
start => start,
xn_re => xn_re,
xn_im => xn_im,
fwd_inv => fwd_inv,
fwd_inv_we => fwd_inv_we,
scale_sch => scale_sch,
scale_sch_we => scale_sch_we,
rfd => rfd,
xn_index => xn_index,
busy => busy,
edone => edone,
done => done,
dv => dv,
xk_index => xk_index,
xk_re => xk_re,
xk_im => xk_im
);
-- burst ram interface
o_RAMClk <= clk;
--o_RAMWE <= o_RAMWE_write when (write_no_tracking_needed_en='1') else o_RAMWE_fft;
--o_RAMData <= o_RAMData_write when (write_no_tracking_needed_en='1') else o_RAMData_fft;
--ce <= enable;
--! multiplexer for local ram address (outgoing signals)
mux_proc : process(calc_fft_en, initial_phase_en, interval_en, write_no_tracking_needed_en,
get_measurement_en, load_parameter_en, o_RAMAddr_get, o_RAMAddr_param,
o_RAMAddr_initial, o_RAMAddr_interval, o_RAMAddr_fft, o_RAMAddr_write,
o_RAMWE_get, o_RAMWE_fft, o_RAMWE_write, o_RAMData_get, o_RAMData_fft, o_RAMData_write
)
begin
if (calc_fft_en='1') then
o_RAMAddr <= o_RAMAddr_fft;
o_RAMData <= o_RAMData_fft;
o_RAMWE <= o_RAMWE_fft;
elsif (get_measurement_en='1') then
o_RAMAddr <= o_RAMAddr_get;
o_RAMData <= o_RAMData_get;
o_RAMWE <= o_RAMWE_get;
elsif (initial_phase_en='1') then
o_RAMAddr <= o_RAMAddr_initial;
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
elsif (interval_en='1') then
o_RAMAddr <= o_RAMAddr_interval;
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
elsif (write_no_tracking_needed_en='1') then
o_RAMAddr <= o_RAMAddr_write;
o_RAMData <= o_RAMData_write;
o_RAMWE <= o_RAMWE_write;
elsif (load_parameter_en='1') then
o_RAMAddr <= o_RAMAddr_param;
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
else
o_RAMAddr <= (others=>'0');
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
end if;
end process;
-- (2) loads parameter: observation size
load_parameter_proc : process(clk, reset, load_parameter_en)
variable step : natural range 0 to 6;
begin
if reset = '1' or load_parameter_en = '0' then
load_parameter_done <= '0';
o_RAMAddr_param <= (others=>'0');
step := 0;
elsif rising_edge(clk) then
case step is
when 0 =>
--! get size parameter
o_RAMAddr_param <= (others=>'0');
step := step + 1;
when 1 =>
--! wait one cycle
o_RAMAddr_param <= o_RAMAddr_param + 1;
step := step + 1;
when 2 =>
--! read real and imaginary value
measurement_size <= to_integer(signed(i_RAMData));
step := step + 1;
when 3 =>
--! read real and imaginary value
observation_size <= to_integer(signed(i_RAMData));
step := step + 1;
when 4 =>
measurement_size <= measurement_size / 4;
step := step + 1;
when 5 =>
observation_size <= observation_size / 4;
step := step + 1;
when 6 =>
--! finished
load_parameter_done <= '1';
end case;
end if;
end process;
-- (3) checks, if tracker is in initial phase
initial_phase_proc : process(clk, reset, initial_phase_en)
variable step : natural range 0 to 5;
variable initial_phase_data : integer := 0;
variable current_particle_address2 : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
if reset = '1' or initial_phase_en = '0' then
initial_phase_done <= '0';
o_RAMAddr_initial <= (others=>'0');
step := 0;
elsif rising_edge(clk) then
case step is
when 0 =>
--! set address
current_particle_address2 := (others=>'0');
step := step + 1;
when 1 =>
--!
o_RAMAddr_initial <= current_particle_address2 + 5;
step := step + 1;
when 2 =>
--! wait one cycle
step := step + 1;
when 3 =>
--! get data
initial_phase_data := to_integer(signed(i_RAMData));
step := step + 1;
when 4 =>
--! set initial phase signal
if (initial_phase_data > 0) then
is_in_initial_phase <= '1';
else
is_in_initial_phase <= '0';
end if;
step := step + 1;
when 5 =>
--! finished
initial_phase_done <= '1';
end case;
end if;
end process;
-- (4) checks, if tracker is in interval
interval_proc : process(clk, reset, interval_en)
variable step : natural range 0 to 9;
begin
if reset = '1' or interval_en = '0' then
interval_done <= '0';
o_RAMAddr_interval <= (others=>'0');
step := 0;
elsif rising_edge(clk) then
case step is
when 0 =>
--! set address
o_RAMAddr_interval <= (others=>'0');
step := step + 1;
when 1 =>
--!
o_RAMAddr_interval <= o_RAMAddr_interval + 1;
step := step + 1;
when 2 =>
--! wait one cycle
o_RAMAddr_interval <= o_RAMAddr_interval + 1;
step := step + 1;
when 3 =>
--! get old likelihood
old_likelihood(0 to 31) <= i_RAMData(0 to 31);
o_RAMAddr_interval <= o_RAMAddr_interval + 4;
step := step + 1;
when 4 =>
--! get data
o_RAMAddr_interval <= o_RAMAddr_interval + 1;
next_beat(0 to 31) <= i_RAMData(0 to 31);
step := step + 1;
when 5 =>
--! get data
interval_min(0 to 31) <= i_RAMData(0 to 31);
step := step + 1;
when 6 =>
--! get data
interval_max(0 to 31) <= i_RAMData(0 to 31);
step := step + 1;
when 7 =>
--! check interval boundaries: min
if (interval_min <= next_beat) then
step := step + 1;
else
is_in_interval <= '0';
step := step + 2;
end if;
when 8 =>
--! check interval boundaries: max
if (next_beat <= interval_max) then
is_in_interval <= '1';
else
is_in_interval <= '0';
end if;
step := step + 1;
when 9 =>
--! finished
interval_done <= '1';
end case;
end if;
end process;
-- (5) calculates start index for measurement
calc_start_index_proc : process(clk, reset, calc_start_index_en)
variable step : natural range 0 to 7;
variable difference : std_logic_vector(0 to 31);
variable start_max : integer;
begin
if reset = '1' or calc_start_index_en = '0' then
calc_start_index_done <= '0';
step := 0;
elsif rising_edge(clk) then
case step is
when 0 =>
--! calcualte difference
difference(0 to 31) := std_logic_vector(unsigned(next_beat) - unsigned(interval_min));
step := step + 1;
when 1 =>
--! wait
step := step + 1;
when 2 =>
--! convert to integer
start_index <= to_integer(unsigned(difference(0 to 31)));
step := step + 1;
when 3 =>
--! wait
step := step + 1;
when 4 =>
--! convert to integer
start_index <= start_index / 4;
step := step + 1;
when 5 =>
--! convert to integer
if (start_index < 0) then
start_index <= 0;
end if;
start_max := measurement_size - 64; -- fft expects 128 values a 2 bytes = 64*4 bytes
step := step + 1;
when 6 =>
--! convert to integer
if (start_index > start_max) then --
start_index <= start_max;
end if;
step := step + 1;
when 7 =>
--! finished
calc_start_index_done <= '1';
end case;
end if;
end process;
-- (6) gets measurement and writes it into local ram (starting at "100000000000")
get_measurement_proc : process(clk, reset, get_measurement_en)
variable step : natural range 0 to 11;
variable i : natural;
variable address2 : std_logic_vector(0 to 31);
variable address_offset : natural;
begin
if reset = '1' or get_measurement_en = '0' then
word_data_ack <= '0';
o_RAMWE_get <= '0';
input_data_needed <= '0';
get_measurement_done <= '0';
step := 0;
elsif rising_edge(clk) then
case step is
when 0 =>
--! init
i := 0;
o_RAMWE_get <= '0';
word_data_ack <= '0';
input_data_needed <= '0';
address_offset := 4*start_index;
step := step + 1;
when 1 =>
step := step + 1;
when 2 =>
address2 := input_data_address + address_offset;
step := step + 1;
when 3 =>
--! init
if (i < 64) then -- 128 samples a 2 byte = 64 * 4 bytes
step := step + 1;
else
-- done
step := 11;
end if;
when 4 =>
--! start loop body
-- ask framework for data
-- TODO (1/2): CHANGE CHANGE CHANGE - BACK
address_offset := 4*i;
step := step + 1;
when 5 =>
step := step + 1;
when 6 =>
input_data_needed <= '1';
word_address <= address2 + address_offset;
step := step + 1;
when 7 =>
--! wait for data
-- TODO (2/2): CHANGE CHANGE CHANGE - BACK
if (word_data_en='1') then
input_data_needed <= '0';
step := step + 1;
end if;
when 8 =>
--! wait
step := step + 1;
when 9 =>
--! write date to local ram and acknowledge data
o_RAMWE_get <= '1';
o_RAMAddr_get <= "100000000000" + i;
-- reverse byte order
o_RAMData_get(0 to 31) <= word_data(8 to 15)&word_data(0 to 7)&
word_data(24 to 31)&word_data(16 to 23);
-- TODO: CHANGE CHANGE CHANGE - BACK
--o_RAMAddr_get <= "000000000000" + i;
--o_RAMData_get(0 to 31) <= word_data(0 to 31);
word_data_ack <= '1';
step := step + 1;
when 10 =>
--! end of loop body
word_data_ack <= '0';
o_RAMWE_get <= '0';
i := i + 1;
step := 1;
when 11 =>
--! finished
get_measurement_done <= '1';
end case;
end if;
end process;
-- (7) calculates fast fourier transformation
-- fast fourier transformation (fft) of '128' samples (format: 16 bit wide, signed)
-- output: '128' FFT VALUES
-- - real component (format: 16 bit wide, signed (?))
-- - imaginary component (format: 16 bit wide, signed (?))
calc_fft_proc : process(clk, reset, calc_fft_en)
variable step : natural range 0 to 9;
begin
if reset = '1' or calc_fft_en = '0' then
calc_fft_done <= '0';
start <= '0';
o_RAMWE_fft <= '0';
xn_im <= (others=>'0');
xn_re <= (others=>'0');
ce <= '0';
fwd_inv <= '1';
sclr <= '1'; -- TRY THIS
step := 0;
elsif rising_edge(clk) then
case step is
when 0 =>
--! fill fft core with data
-- set start signal
sclr <= '0';
ce <= '1';
fwd_inv <= '1';
fwd_inv_we <= '1';
o_RAMWE_fft <= '0';
o_RAMAddr_fft <= "100000000000";
address <= "100000000000";
xn_im <= (others=>'0');
step := step + 1;
when 1 =>
--! set start signal
start <= '1';
fwd_inv_we <= '0';
o_RAMWE_fft <= '0';
my_xn_index <= xn_index;
step := step + 1;
when 2 =>
--! start filling the incoming data pipeline
-- (read left sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(16)&i_RAMData(17)&i_RAMData(18)&i_RAMData(19)&i_RAMData(20)&i_RAMData(21)&i_RAMData(22)&i_RAMData(23)&i_RAMData(24)&i_RAMData(25)&i_RAMData(26)&i_RAMData(27)&i_RAMData(28)&i_RAMData(29)&i_RAMData(30)&i_RAMData(31);
o_RAMAddr_fft <= address + 1;
address <= address + 1;
step := step + 1;
when 3 =>
--! start filling the incoming data pipeline
-- (read right sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(0)&i_RAMData(1)&i_RAMData(2)&i_RAMData(3)&i_RAMData(4)&i_RAMData(5)&i_RAMData(6)&i_RAMData(7)&i_RAMData(8)&i_RAMData(9)&i_RAMData(10)&i_RAMData(11)&i_RAMData(12)&i_RAMData(13)&i_RAMData(14)&i_RAMData(15);
my_xn_index <= xn_index + 1;
step := step + 1;
when 4 =>
--! samples are arriving (read left sample (16 of 32 bits))
start <= '0';
xn_re(15 downto 0) <= i_RAMData(16)&i_RAMData(17)&i_RAMData(18)&i_RAMData(19)&i_RAMData(20)&i_RAMData(21)&i_RAMData(22)&i_RAMData(23)&i_RAMData(24)&i_RAMData(25)&i_RAMData(26)&i_RAMData(27)&i_RAMData(28)&i_RAMData(29)&i_RAMData(30)&i_RAMData(31);
my_xn_index <= xn_index + 1;
o_RAMAddr_fft <= address + 1;
address <= address + 1;
step := step + 1;
when 5 =>
--! samples are arriving (read right sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(0)&i_RAMData(1)&i_RAMData(2)&i_RAMData(3)&i_RAMData(4)&i_RAMData(5)&i_RAMData(6)&i_RAMData(7)&i_RAMData(8)&i_RAMData(9)&i_RAMData(10)&i_RAMData(11)&i_RAMData(12)&i_RAMData(13)&i_RAMData(14)&i_RAMData(15);
if (busy='0') then
my_xn_index <= xn_index + 1;
step := step - 1;
else
step := step + 1;
end if;
when 6 =>
--! wait for results
if (edone = '1') then
o_RAMAddr_fft <= address - 1;
address <= address - 1;
start <= '1';
o_RAMWE_fft <= '0';
step := step + 1;
end if;
when 7 =>
--! get data and write them back
--o_RAMData_fft(0 to 31) <= xk_re(15 downto 0) & xk_im(15 downto 0);
o_RAMData_fft(0 to 31) <= xk_re(15)&xk_re(14)&xk_re(13)&xk_re(12)&xk_re(11)&xk_re(10)&xk_re(9)&xk_re(8)&xk_re(7)&xk_re(6)&xk_re(5)&xk_re(4)&xk_re(3)&xk_re(2)&xk_re(1)&xk_re(0)&xk_im(15)&xk_im(14)&xk_im(13)&xk_im(12)&xk_im(11)&xk_im(10)&xk_im(9)&xk_im(8)&xk_im(7)&xk_im(6)&xk_im(5)&xk_im(4)&xk_im(3)&xk_im(2)&xk_im(1)&xk_im(0);
--o_RAMAddr_fft(0 to 11) <= "0" & xk_index(10 downto 0);
o_RAMAddr_fft(0 to 11) <= "00000"&xk_index(6)&xk_index(5)&xk_index(4)&xk_index(3)&xk_index(2)&xk_index(1)&xk_index(0);
o_RAMWE_fft <= '1';
if (busy='1') then
step := step + 1;
end if;
when 8 =>
--o_RAMData_fft(0 to 31) <= xk_re(15 downto 0) & xk_im(15 downto 0);
o_RAMData_fft(0 to 31) <= xk_re(15)&xk_re(14)&xk_re(13)&xk_re(12)&xk_re(11)&xk_re(10)&xk_re(9)&xk_re(8)&xk_re(7)&xk_re(6)&xk_re(5)&xk_re(4)&xk_re(3)&xk_re(2)&xk_re(1)&xk_re(0)&xk_im(15)&xk_im(14)&xk_im(13)&xk_im(12)&xk_im(11)&xk_im(10)&xk_im(9)&xk_im(8)&xk_im(7)&xk_im(6)&xk_im(5)&xk_im(4)&xk_im(3)&xk_im(2)&xk_im(1)&xk_im(0);
--o_RAMAddr_fft(0 to 11) <= "0" & xk_index(10 downto 0);
o_RAMAddr_fft(0 to 11) <= "00000"&xk_index(6)&xk_index(5)&xk_index(4)&xk_index(3)&xk_index(2)&xk_index(1)&xk_index(0);
if (dv='0') then
o_RAMWE_fft <= '0';
step := step + 1;
else
o_RAMWE_fft <= '1';
end if;
when 9 =>
--! finish fft process
o_RAMWE_fft <= '0';
start <= '0';
sclr <= '1';
calc_fft_done <= '1';
end case;
end if;
end process;
-- (8) writes no_tracking_needed information
write_no_tracking_needed_proc : process(clk, reset, write_no_tracking_needed_en)
variable step : natural range 0 to 4;
variable current_observation_address : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
if reset = '1' or write_no_tracking_needed_en = '0' then
write_no_tracking_needed_done <= '0';
o_RAMAddr_write <= (others=>'0');
o_RAMWE_write <= '0';
step := 0;
elsif rising_edge(clk) then
case step is
when 0 =>
--! init
current_observation_address := (others=>'0');
o_RAMWE_write <= '0';
step := step + 1;
when 1 =>
--! calc address
current_observation_address := current_observation_address + observation_size;
step := step + 1;
when 2 =>
--! write old likelihood
o_RAMWE_write <= '1';
o_RAMAddr_write <= current_observation_address - 2;
o_RAMData_write <= old_likelihood;
step := step + 1;
when 3 =>
--! write no tracking is needed information
o_RAMWE_write <= '1';
o_RAMAddr_write <= current_observation_address - 1;
o_RAMData_write <= "0000000000000000000000000000000"&no_tracking_is_needed;
step := step + 1;
when 4 =>
--! finished
o_RAMWE_write <= '0';
write_no_tracking_needed_done <= '1';
end case;
end if;
end process;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
--
-- (1) initialize, finished = '0' (if new_particle = '1')
--
-- (2) load parameter (observation size)
--
-- (3) check, if tracker in initial phase
-- yes: no tracking needed go to step 7
-- no: go to step 4
--
-- (4) check, if estimated beat in current interval
-- yes: go to step 5
-- no: no tracking needed go to step 7
--
-- (5) calculate start index
--
-- (6) get measurement
--
-- (7) calculate fft
--
-- (8) write information: no_tracking_is_needed (0/no or 1/yes)
--
-- (9) finished = '1', wait for new_particle = '1'
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
main_proc : process(clk, reset)
begin
if (reset = '1') then
new_particle_ack <= '0';
finished <= '0';
state <= initialize;
elsif rising_edge(clk) then
if init = '1' then
state <= initialize;
no_tracking_is_needed <= '0';
finished <= '0';
elsif enable = '1' then
case state is
when initialize =>
--! (1) init data
finished <= '0';
parameter_loaded_ack <= '0';
no_tracking_is_needed <= '0';
if (new_particle = '1') then
new_particle_ack <= '1';
initial_phase_en <= '1';
state <= initial_phase;
elsif (parameter_loaded = '1') then
load_parameter_en <= '1';
state <= load_parameter;
end if;
when load_parameter =>
--! (2) calculates start index position in measurement
if (load_parameter_done = '1') then
parameter_loaded_ack <= '1';
load_parameter_en <= '0';
state <= initialize;
end if;
when initial_phase =>
--! (3) check if tracker is in initial phase
new_particle_ack <= '0';
if (initial_phase_done = '1') then
initial_phase_en <= '0';
if (is_in_initial_phase='1') then
no_tracking_is_needed <= '1';
write_no_tracking_needed_en <= '1';
state <= write_no_tracking_needed;
else
no_tracking_is_needed <= '0';
interval_en <= '1';
state <= interval;
end if;
end if;
when interval =>
--! (4) check if tracker is in current interval
if (interval_done = '1') then
interval_en <= '0';
if (is_in_interval='1') then
no_tracking_is_needed <= '0';
calc_start_index_en <= '1';
state <= calc_start_index;
else
no_tracking_is_needed <= '1';
write_no_tracking_needed_en <= '1';
state <= write_no_tracking_needed;
end if;
end if;
when calc_start_index =>
--! (5) calculates start index position in measurement
if (calc_start_index_done = '1') then
calc_start_index_en <= '0';
get_measurement_en <= '1';
state <= get_measurement;
--calc_fft_en <= '1';
--state <= calc_fft;
end if;
when get_measurement =>
--! (6) gets needed part of measurement via framework
if (get_measurement_done = '1') then
get_measurement_en <= '0';
--write_no_tracking_needed_en <= '1';
--state <= write_no_tracking_needed;
calc_fft_en <= '1';
state <= calc_fft;
end if;
when calc_fft =>
--! (7) calculates fft from framework
if (calc_fft_done = '1') then
calc_fft_en <= '0';
write_no_tracking_needed_en <= '1';
state <= write_no_tracking_needed;
end if;
when write_no_tracking_needed =>
--! (8) writes no_tracking_need_information into observation
if (write_no_tracking_needed_done = '1') then
write_no_tracking_needed_en <= '0';
state <= finish;
end if;
when finish =>
--! (9) write finished signal
finished <= '1';
if (new_particle = '1') then
state <= initialize;
end if;
when others =>
state <= initialize;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
0bc70ae8ff2ef590bcb060bdb914c803
| 0.573104 | 2.856461 | false | false | false | false |
makestuff/vhdl
|
analyzer/toplevel.vhdl
| 1 | 9,363 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity toplevel is
port(
ifclk_in : in std_logic;
-- Data & control from the FX2
fifoData_io : inout std_logic_vector(7 downto 0);
gotData_in : in std_logic; -- FLAGC=EF (active-low), so '1' when there's data
gotRoom_in : in std_logic; -- FLAGB=FF (active-low), so '1' when there's room
-- Control to the FX2
sloe_out : out std_logic; -- PA2
slrd_out : out std_logic;
slwr_out : out std_logic;
fifoAddr_out : out std_logic_vector(1 downto 0); -- PA4 & PA5
pktEnd_out : out std_logic; -- PA6
-- Onboard peripherals
sseg_out : out std_logic_vector(7 downto 0);
anode_out : out std_logic_vector(3 downto 0);
led_out : out std_logic_vector(7 downto 0);
async_in : in std_logic
);
end toplevel;
architecture behavioural of toplevel is
type StateType is (
STATE_IDLE,
STATE_GET_COUNT0,
STATE_GET_COUNT1,
STATE_GET_COUNT2,
STATE_GET_COUNT3,
STATE_BEGIN_WRITE,
STATE_WRITE,
STATE_END_WRITE_ALIGNED,
STATE_END_WRITE_NONALIGNED,
STATE_READ
);
signal state, state_next : StateType := STATE_IDLE;
signal count, count_next : unsigned(31 downto 0); -- Read/Write count
signal addr, addr_next : std_logic_vector(1 downto 0);
signal isWrite, isWrite_next : std_logic;
signal isAligned, isAligned_next : std_logic;
signal checksum, checksum_next : std_logic_vector(15 downto 0) := x"0000";
signal r0, r1, r0_next, r1_next : std_logic_vector(7 downto 0) := x"00";
signal r2, r3, r2_next, r3_next : std_logic_vector(7 downto 0) := x"00";
signal fifoOp : std_logic_vector(2 downto 0);
signal fifoDataIn, fifoDataOut : std_logic_vector(7 downto 0);
signal fifoReadEnable : std_logic;
signal fifoWriteEnable : std_logic;
signal fifoEmpty, fifoFull : std_logic;
signal triggerProducer, alarm : std_logic;
constant FIFO_READ : std_logic_vector(2 downto 0) := "100"; -- assert slrd_out & sloe_out
constant FIFO_WRITE : std_logic_vector(2 downto 0) := "011"; -- assert slwr_out
constant FIFO_NOP : std_logic_vector(2 downto 0) := "111"; -- assert nothing
constant OUT_FIFO : std_logic_vector(1 downto 0) := "10"; -- EP6OUT
constant IN_FIFO : std_logic_vector(1 downto 0) := "11"; -- EP8IN
begin
process(ifclk_in)
begin
if ( rising_edge(ifclk_in) ) then
state <= state_next;
count <= count_next;
addr <= addr_next;
isWrite <= isWrite_next;
isAligned <= isAligned_next;
checksum <= checksum_next;
r0 <= r0_next;
r1 <= r1_next;
r2 <= r2_next;
r3 <= r3_next;
end if;
end process;
-- Next state logic
process(
state, fifoData_io, gotData_in, gotRoom_in, count, isAligned, isWrite, addr,
r0, r1, r2, r3, checksum, fifoEmpty, fifoDataOut)
begin
state_next <= state;
count_next <= count;
addr_next <= addr;
isWrite_next <= isWrite;
isAligned_next <= isAligned; -- does this FIFO write end on a block (512-byte) boundary?
checksum_next <= checksum;
r0_next <= r0;
r1_next <= r1;
r2_next <= r2;
r3_next <= r3;
fifoData_io <= (others => 'Z'); -- Tristated unless explicitly driven
fifoOp <= FIFO_READ; -- read the FX2LP FIFO by default
pktEnd_out <= '1'; -- inactive: FPGA does not commit a short packet.
fifoReadEnable <= '0';
triggerProducer <= '0';
case state is
when STATE_IDLE =>
fifoAddr_out <= OUT_FIFO; -- Reading from FX2LP
if ( gotData_in = '1' ) then
-- The read/write flag and a seven-bit register address will be available on the
-- next clock edge.
addr_next <= fifoData_io(1 downto 0);
isWrite_next <= fifoData_io(7);
state_next <= STATE_GET_COUNT0;
end if;
when STATE_GET_COUNT0 =>
fifoAddr_out <= OUT_FIFO; -- Reading from FX2LP
if ( gotData_in = '1' ) then
-- The count high word high byte will be available on the next clock edge.
count_next(31 downto 24) <= unsigned(fifoData_io);
state_next <= STATE_GET_COUNT1;
end if;
when STATE_GET_COUNT1 =>
fifoAddr_out <= OUT_FIFO; -- Reading from FX2LP
if ( gotData_in = '1' ) then
-- The count high word low byte will be available on the next clock edge.
count_next(23 downto 16) <= unsigned(fifoData_io);
state_next <= STATE_GET_COUNT2;
end if;
when STATE_GET_COUNT2 =>
fifoAddr_out <= OUT_FIFO; -- Reading from FX2LP
if ( gotData_in = '1' ) then
-- The count low word high byte will be available on the next clock edge.
count_next(15 downto 8) <= unsigned(fifoData_io);
state_next <= STATE_GET_COUNT3;
end if;
when STATE_GET_COUNT3 =>
fifoAddr_out <= OUT_FIFO; -- Reading from FX2LP
if ( gotData_in = '1' ) then
-- The count low word low byte will be available on the next clock edge.
count_next(7 downto 0) <= unsigned(fifoData_io);
if ( isWrite = '1' ) then
state_next <= STATE_BEGIN_WRITE;
else
state_next <= STATE_READ;
end if;
end if;
when STATE_BEGIN_WRITE =>
fifoAddr_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
isAligned_next <= not(count(0) or count(1) or count(2) or count(3) or count(4) or count(5) or count(6) or count(7) or count(8));
triggerProducer <= '1';
state_next <= STATE_WRITE;
when STATE_WRITE =>
fifoAddr_out <= IN_FIFO; -- Writing to FX2LP
if ( gotRoom_in = '1' and (addr /= "00" or fifoEmpty = '0') ) then
fifoOp <= FIFO_WRITE;
case addr is
when "00" =>
fifoData_io <= fifoDataOut;
fifoReadEnable <= '1';
when "01" =>
fifoData_io <= r1;
count_next <= count - 1;
when "10" =>
fifoData_io <= r2;
count_next <= count - 1;
when others =>
fifoData_io <= r3;
count_next <= count - 1;
end case;
count_next <= count - 1;
if ( count = 1 ) then
if ( isAligned = '1' ) then
state_next <= STATE_END_WRITE_ALIGNED; -- don't assert pktEnd
else
state_next <= STATE_END_WRITE_NONALIGNED; -- assert pktEnd to commit small packet
end if;
end if;
else
fifoOp <= FIFO_NOP;
end if;
when STATE_END_WRITE_ALIGNED =>
fifoAddr_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
state_next <= STATE_IDLE;
when STATE_END_WRITE_NONALIGNED =>
fifoAddr_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
pktEnd_out <= '0'; -- Active: FPGA commits the packet.
state_next <= STATE_IDLE;
when STATE_READ =>
fifoAddr_out <= OUT_FIFO; -- Reading from FX2LP
if ( gotData_in = '1' ) then
-- A data byte will be available on the next clock edge
case addr is
when "00" =>
r0_next <= fifoData_io;
checksum_next <= std_logic_vector(
unsigned(checksum) + unsigned(fifoData_io)); -- Update R0 checksum
when "01" =>
r1_next <= fifoData_io; -- Writing a '1' to bit 0 of R1 clears R0 cksum
if ( fifoData_io(0) = '1' ) then
checksum_next <= (others => '0');
end if;
when "10" =>
r2_next <= fifoData_io;
when others =>
r3_next <= fifoData_io;
end case;
count_next <= count - 1;
if ( count = 1 ) then
state_next <= STATE_IDLE;
end if;
end if;
end case;
end process;
-- Breakout fifoOp
sloe_out <= fifoOp(0);
slrd_out <= fifoOp(1);
slwr_out <= fifoOp(2);
-- LEDs and 7-seg display
led_out <= r0;
sseg_out(7) <= alarm; -- Decimal point off
sevenseg : entity work.sevenseg
port map(
clk_in => ifclk_in,
data_in => checksum,
segs_out => sseg_out(6 downto 0),
anodes_out => anode_out
);
-- Producer of FIFO data
producer : entity work.producer
port map (
clk_in => ifclk_in,
data_out => fifoDataIn,
write_out => fifoWriteEnable,
full_in => fifoFull,
trigger_in => triggerProducer,
count_in => count,
alarm_out => alarm,
ch_in => async_in
);
-- FIFO generator
fifogen : entity work.fifogen
port map(
clk => ifclk_in,
-- Putting stuff into the FIFO:
din => fifoDataIn,
wr_en => fifoWriteEnable,
full => fifoFull,
-- Taking stuff out of the FIFO:
rd_en => fifoReadEnable,
dout => fifoDataOut,
empty => fifoEmpty
);
end behavioural;
|
gpl-3.0
|
ba8d740b2823327a166faf3434be9055
| 0.59906 | 3.149344 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/test/testbench/Tester/src/verilog/TESTER_pkg.vhd
| 1 | 7,354 |
---------------------------------------------------------------------
--
-- File Name: TESTER_pkg.vhd
-- Project: LL FIFO
-- Version: 1.2
-- Date: 2005-06-29
--
-- Company: Xilinx, Inc.
-- Contributors: Wen Ying Wei, Davy Huang
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
---------------------------------------------------------------------
--
-- Tester Package
-- Author: Davy Huang
--
-- Description:
-- This package file is created for mixed language simulation
-- using Aurora tester for LL FIFO.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package TESTER_pkg is
component OUTPUT_TESTER IS
GENERIC (
-- Parameter Declarations ********************************************
GLOBALDLY : integer := 1;
LL_DAT_BIT_WIDTH : integer := 16;
LL_REM_BIT_WIDTH : integer := 1;
FIFO_DEPTH : integer := 256);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
RX_D : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
RX_REM : IN std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
RX_SOF_N : IN std_logic;
RX_EOF_N : IN std_logic;
RX_SRC_RDY_N : IN std_logic;
UFC_RX_DATA : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
UFC_RX_REM : IN std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
UFC_RX_SOF_N : IN std_logic;
UFC_RX_EOF_N : IN std_logic;
UFC_RX_SRC_RDY_N : IN std_logic;
RX_SOF_N_REF : IN std_logic;
RX_EOF_N_REF : IN std_logic;
RX_REM_REF : IN std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
RX_DATA_REF : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
RX_SRC_RDY_N_REF : IN std_logic;
UFC_RX_DATA_REF : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
UFC_RX_REM_REF : IN std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
UFC_RX_SOF_N_REF : IN std_logic;
UFC_RX_EOF_N_REF : IN std_logic;
UFC_RX_SRC_RDY_N_REF : IN std_logic;
WORKING : OUT std_logic;
COMPARING : OUT std_logic;
OVERFLOW : OUT std_logic;
RESULT_GOOD : OUT std_logic;
RESULT_GOOD_PDU : OUT std_logic;
RESULT_GOOD_UFC : OUT std_logic);
END COMPONENT;
component OUTPUT_TESTER_8_BIT IS
GENERIC (
-- Parameter Declarations ********************************************
GLOBALDLY : integer := 1;
LL_DAT_BIT_WIDTH : integer := 8;
LL_REM_BIT_WIDTH : integer := 0;
FIFO_DEPTH : integer := 256);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
RX_D : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
RX_REM : IN std_logic;
RX_SOF_N : IN std_logic;
RX_EOF_N : IN std_logic;
RX_SRC_RDY_N : IN std_logic;
UFC_RX_DATA : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
UFC_RX_REM : IN std_logic;
UFC_RX_SOF_N : IN std_logic;
UFC_RX_EOF_N : IN std_logic;
UFC_RX_SRC_RDY_N : IN std_logic;
RX_SOF_N_REF : IN std_logic;
RX_EOF_N_REF : IN std_logic;
RX_REM_REF : IN std_logic;
RX_DATA_REF : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
RX_SRC_RDY_N_REF : IN std_logic;
UFC_RX_DATA_REF : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
UFC_RX_REM_REF : IN std_logic;
UFC_RX_SOF_N_REF : IN std_logic;
UFC_RX_EOF_N_REF : IN std_logic;
UFC_RX_SRC_RDY_N_REF : IN std_logic;
WORKING : OUT std_logic;
COMPARING : OUT std_logic;
OVERFLOW : OUT std_logic;
RESULT_GOOD : OUT std_logic;
RESULT_GOOD_PDU : OUT std_logic;
RESULT_GOOD_UFC : OUT std_logic);
END COMPONENT;
COMPONENT FILEREAD_TESTER IS
GENERIC (
-- Parameter Declarations ********************************************
GLOBALDLY : integer := 1;
TV_WIDTH : integer := 8;
CV_WIDTH : integer := 4;
LL_DAT_BIT_WIDTH : integer := 16;
LL_REM_BIT_WIDTH : integer := 1;
REM_VECTOR_WIDTH : integer := 3);
PORT (
CLK : IN std_logic;
TV : IN std_logic_vector(0 TO TV_WIDTH - 1);
TX_SOF_N : OUT std_logic;
TX_EOF_N : OUT std_logic;
TX_D : OUT std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
TX_REM : OUT std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
TX_SRC_RDY_N : OUT std_logic;
NFC_NB : OUT std_logic_vector(0 TO 3);
NFC_REQ_N : OUT std_logic;
UFC_TX_REQ_N : OUT std_logic;
UFC_TX_MS : OUT std_logic_vector(0 TO 3);
CTRL : OUT std_logic_vector(0 TO CV_WIDTH -1));
END COMPONENT;
end TESTER_pkg;
------------------------------------------------------------------------
-- History:
-- DH 8/22/03 -- Initial design
------------------------------------------------------------------------
-- $Revision: 1.2 $
-- $Date: 2004/12/27 18:12:18 $
|
gpl-3.0
|
3b4fea2fd92afddadceb35054cba3b4d
| 0.435273 | 4.085556 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/sSegDemo.vhd
| 1 | 11,979 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 09:53:08 03/07/2013
-- Design Name:
-- Module Name: sSegDemo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the Seven-Segment display demo
-- that displays a moving pattern on the 8-digit seven segment display
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity sSegDemo is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
seg_o : out std_logic_vector(7 downto 0);
an_o : out std_logic_vector(7 downto 0)
);
end sSegDemo;
architecture Behavioral of sSegDemo is
-- Seven-Segment display multiplexer
component sSegDisplay is
port(
ck : in std_logic; -- 100Mhz system clock
number : in std_logic_vector(63 downto 0); -- eght digit hex data to be displayed, active-low
seg : out std_logic_vector(7 downto 0); -- display cathodes
an : out std_logic_vector(7 downto 0)); -- display anodes (active-low, due to transistor complementing)
end component;
-- Clock division constant
-- The pattern will move on the seven-segment display at
-- a frequency of 100MHz/8000000 = 12.5Hz
constant CLK_DIV : integer := 8000000;
-- Clock divider counter and signal
signal clkCnt : integer := 0;
signal slowClk : std_logic;
-- dispVal represents the pattern to be displayed
-- The pattern changes i.e. moves according to the value of slowCnt
signal dispVal : std_logic_vector(63 downto 0);
signal slowCnt : integer := 0;
begin
-- Seven-Segment display multiplexer instantiation
Disp: sSegDisplay
port map(
ck => clk_i,
number => dispVal, -- 64-bit
seg => seg_o,
an => an_o);
-- clock prescaler
Prescaler: process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
clkCnt <= 0;
elsif clkCnt = CLK_DIV-1 then
clkCnt <= 0;
else
clkCnt <= clkCnt + 1;
end if;
end if;
end process Prescaler;
slowClk <= '1' when clkCnt = CLK_DIV-1 else '0';
-- slow counter
ProcCnt: process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
slowCnt <= 0;
elsif slowClk = '1' then
if slowCnt = 98 then
slowCnt <= 15;
else
slowCnt <= slowCnt + 1;
end if;
end if;
end if;
end process ProcCnt;
-- create the 64-bit memory that holds the pattern for dispVal
with slowCnt select
dispVal <= x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"fe" when 0,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"fe" & x"fe" when 1,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"fe" & x"fe" & x"fe" when 2,
x"ff" & x"ff" & x"ff" & x"ff" & x"fe" & x"fe" & x"fe" & x"fe" when 3,
x"ff" & x"ff" & x"ff" & x"fe" & x"fe" & x"fe" & x"fe" & x"fe" when 4,
x"ff" & x"ff" & x"fe" & x"fe" & x"fe" & x"fe" & x"fe" & x"ff" when 5,
x"ff" & x"fe" & x"fe" & x"fe" & x"fe" & x"fe" & x"ff" & x"ff" when 6,
x"fe" & x"fe" & x"fe" & x"fe" & x"fe" & x"ff" & x"ff" & x"ff" when 7,
x"de" & x"fe" & x"fe" & x"fe" & x"ff" & x"ff" & x"ff" & x"ff" when 8,
x"ce" & x"fe" & x"fe" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 9,
x"86" & x"fe" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 10,
x"86" & x"77" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 11,
x"87" & x"77" & x"77" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 12,
x"67" & x"77" & x"77" & x"77" & x"ff" & x"ff" & x"ff" & x"ff" when 13,
x"77" & x"77" & x"77" & x"77" & x"77" & x"ff" & x"ff" & x"ff" when 14,
x"ff" & x"77" & x"77" & x"77" & x"77" & x"77" & x"ff" & x"ff" when 15,
x"ff" & x"ff" & x"77" & x"77" & x"77" & x"77" & x"77" & x"ff" when 16,
x"ff" & x"ff" & x"ff" & x"77" & x"77" & x"77" & x"77" & x"77" when 17,
x"ff" & x"ff" & x"ff" & x"ff" & x"77" & x"77" & x"77" & x"73" when 18,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"77" & x"77" & x"71" when 19,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"77" & x"70" when 20,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"50" when 21,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"c8" when 22,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"f7" & x"cc" when 23,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"e7" & x"ce" when 24,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"c7" & x"cf" when 25,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"fe" & x"c7" & x"ef" when 26,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"de" & x"c7" & x"ff" when 27,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ce" & x"cf" & x"ff" when 28,
x"ff" & x"ff" & x"ff" & x"ff" & x"f7" & x"ce" & x"df" & x"ff" when 29,
x"ff" & x"ff" & x"ff" & x"ff" & x"e7" & x"ce" & x"ff" & x"ff" when 30,
x"ff" & x"ff" & x"ff" & x"ff" & x"c7" & x"cf" & x"ff" & x"ff" when 31,
x"ff" & x"ff" & x"ff" & x"fe" & x"c7" & x"ef" & x"ff" & x"ff" when 32,
x"ff" & x"ff" & x"ff" & x"de" & x"c7" & x"ff" & x"ff" & x"ff" when 33,
x"ff" & x"ff" & x"ff" & x"ce" & x"cf" & x"ff" & x"ff" & x"ff" when 34,
x"ff" & x"ff" & x"f7" & x"ce" & x"df" & x"ff" & x"ff" & x"ff" when 35,
x"ff" & x"ff" & x"e7" & x"ce" & x"ff" & x"ff" & x"ff" & x"ff" when 36,
x"ff" & x"ff" & x"c7" & x"cf" & x"ff" & x"ff" & x"ff" & x"ff" when 37,
x"ff" & x"fe" & x"c7" & x"ef" & x"ff" & x"ff" & x"ff" & x"ff" when 38,
x"ff" & x"de" & x"c7" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 39,
x"ff" & x"ce" & x"cf" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 40,
x"f7" & x"ce" & x"df" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 41,
x"e7" & x"ce" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 42,
x"a7" & x"cf" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 43,
x"a7" & x"af" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 44,
x"a7" & x"bf" & x"bf" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 45,
x"af" & x"bf" & x"bf" & x"bf" & x"ff" & x"ff" & x"ff" & x"ff" when 46,
x"bf" & x"bf" & x"bf" & x"bf" & x"bf" & x"ff" & x"ff" & x"ff" when 47,
x"ff" & x"bf" & x"bf" & x"bf" & x"bf" & x"bf" & x"ff" & x"ff" when 48,
x"ff" & x"ff" & x"bf" & x"bf" & x"bf" & x"bf" & x"bf" & x"ff" when 49,
x"ff" & x"ff" & x"ff" & x"bf" & x"bf" & x"bf" & x"bf" & x"bf" when 50,
x"ff" & x"ff" & x"ff" & x"ff" & x"bf" & x"bf" & x"bf" & x"bd" when 51,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"bf" & x"bf" & x"bc" when 52,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"be" & x"bc" when 53,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"fe" & x"fe" & x"bc" when 54,
x"ff" & x"ff" & x"ff" & x"ff" & x"fe" & x"fe" & x"fe" & x"fc" when 55,
x"ff" & x"ff" & x"ff" & x"fe" & x"fe" & x"fe" & x"fe" & x"fe" when 56,
x"ff" & x"ff" & x"fe" & x"fe" & x"fe" & x"fe" & x"fe" & x"ff" when 57,
x"ff" & x"fe" & x"fe" & x"fe" & x"fe" & x"fe" & x"ff" & x"ff" when 58,
x"fe" & x"fe" & x"fe" & x"fe" & x"fe" & x"ff" & x"ff" & x"ff" when 59,
x"de" & x"fe" & x"fe" & x"fe" & x"ff" & x"ff" & x"ff" & x"ff" when 60,
x"ce" & x"fe" & x"fe" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 61,
x"c6" & x"fe" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 62,
x"c2" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 63,
x"c1" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 64,
x"e1" & x"fe" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 65,
x"f1" & x"fc" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 66,
x"f9" & x"f8" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 67,
x"fd" & x"f8" & x"f7" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 68,
x"ff" & x"f8" & x"f3" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 69,
x"ff" & x"f9" & x"f1" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 70,
x"ff" & x"fb" & x"f1" & x"fe" & x"ff" & x"ff" & x"ff" & x"ff" when 71,
x"ff" & x"ff" & x"f1" & x"fc" & x"ff" & x"ff" & x"ff" & x"ff" when 72,
x"ff" & x"ff" & x"f9" & x"f8" & x"ff" & x"ff" & x"ff" & x"ff" when 73,
x"ff" & x"ff" & x"fd" & x"f8" & x"f7" & x"ff" & x"ff" & x"ff" when 74,
x"ff" & x"ff" & x"ff" & x"f8" & x"f3" & x"ff" & x"ff" & x"ff" when 75,
x"ff" & x"ff" & x"ff" & x"f9" & x"f1" & x"ff" & x"ff" & x"ff" when 76,
x"ff" & x"ff" & x"ff" & x"fb" & x"f1" & x"fe" & x"ff" & x"ff" when 77,
x"ff" & x"ff" & x"ff" & x"ff" & x"f1" & x"fc" & x"ff" & x"ff" when 78,
x"ff" & x"ff" & x"ff" & x"ff" & x"f9" & x"f8" & x"ff" & x"ff" when 79,
x"ff" & x"ff" & x"ff" & x"ff" & x"fd" & x"f8" & x"f7" & x"ff" when 80,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"f8" & x"f3" & x"ff" when 81,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"f9" & x"f1" & x"ff" when 82,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"fb" & x"f1" & x"fe" when 83,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"f1" & x"fc" when 84,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"f9" & x"bc" when 85,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"bd" & x"bc" when 86,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"bf" & x"bf" & x"bc" when 87,
x"ff" & x"ff" & x"ff" & x"ff" & x"bf" & x"bf" & x"bf" & x"bd" when 88,
x"ff" & x"ff" & x"ff" & x"bf" & x"bf" & x"bf" & x"bf" & x"bf" when 89,
x"ff" & x"ff" & x"bf" & x"bf" & x"bf" & x"bf" & x"bf" & x"ff" when 90,
x"ff" & x"bf" & x"bf" & x"bf" & x"bf" & x"bf" & x"ff" & x"ff" when 91,
x"bf" & x"bf" & x"bf" & x"bf" & x"bf" & x"ff" & x"ff" & x"ff" when 92,
x"af" & x"bf" & x"bf" & x"bf" & x"ff" & x"ff" & x"ff" & x"ff" when 93,
x"27" & x"bf" & x"bf" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 94,
x"27" & x"37" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 95,
x"27" & x"77" & x"77" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when 96,
x"67" & x"77" & x"77" & x"77" & x"ff" & x"ff" & x"ff" & x"ff" when 97,
x"77" & x"77" & x"77" & x"77" & x"77" & x"ff" & x"ff" & x"ff" when 98,
x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" & x"ff" when others;
end Behavioral;
|
gpl-3.0
|
6125b49a2f23837a941531d253069f66
| 0.391769 | 2.344686 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/sdb_rom.vhd
| 1 | 3,450 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity sdb_rom is
generic(
g_layout : t_sdb_record_array;
g_bus_end : unsigned(63 downto 0));
port(
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end sdb_rom;
architecture rtl of sdb_rom is
alias c_layout : t_sdb_record_array(g_layout'length downto 1) is g_layout;
-- The ROM must describe all slaves, the crossbar itself and the optional information records
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_words : natural := c_sdb_device_length / c_wishbone_data_width;
constant c_rom_words : natural := c_rom_entries * c_sdb_words;
constant c_rom_depth : natural := f_ceil_log2(c_rom_words);
constant c_rom_lowbits : natural := f_ceil_log2(c_wishbone_data_width / 8);
type t_rom is array(c_rom_words-1 downto 0) of t_wishbone_data;
function f_build_rom
return t_rom
is
variable res : t_rom := (others => (others => '0'));
variable sdb_device : std_logic_vector(c_sdb_device_length-1 downto 0) := (others => '0');
variable sdb_component : t_sdb_component;
begin
sdb_device(511 downto 480) := x"5344422D" ; -- sdb_magic
sdb_device(479 downto 464) := std_logic_vector(to_unsigned(c_used_entries, 16)); -- sdb_records
sdb_device(463 downto 456) := x"01"; -- sdb_version
sdb_device(455 downto 448) := x"00"; -- sdb_bus_type = sdb_wishbone
sdb_device( 7 downto 0) := x"00"; -- record_type = sdb_interconnect
sdb_component.addr_first := (others => '0');
sdb_component.addr_last := std_logic_vector(g_bus_end);
sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
sdb_component.product.device_id := x"e6a542c9";
sdb_component.product.version := x"00000002";
sdb_component.product.date := x"20120511";
sdb_component.product.name := "WB4-Crossbar-GSI ";
sdb_device(447 downto 8) := f_sdb_embed_component(sdb_component, (others => '0'));
for i in 0 to c_sdb_words-1 loop
res(c_sdb_words-1-i) :=
sdb_device((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
end loop;
for slave in 1 to c_used_entries-1 loop
sdb_device(511 downto 0) := c_layout(slave);
for i in 0 to c_sdb_words-1 loop
res((slave+1)*c_sdb_words-1-i) :=
sdb_device((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
end loop;
end loop;
return res;
end f_build_rom;
signal rom : t_rom := f_build_rom;
signal adr_reg : unsigned(c_rom_depth-1 downto 0);
begin
-- Simple ROM; ignore we/sel/dat
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.stall <= '0';
slave_o.int <= '0'; -- Tom sucks! This should not be here.
slave_o.dat <= rom(to_integer(adr_reg));
slave_clk : process(clk_sys_i)
begin
if (rising_edge(clk_sys_i)) then
adr_reg <= unsigned(slave_i.adr(c_rom_depth+c_rom_lowbits-1 downto c_rom_lowbits));
slave_o.ack <= slave_i.cyc and slave_i.stb;
end if;
end process;
end rtl;
|
lgpl-3.0
|
bb685c19c872437893aeeeefe982e92c
| 0.597681 | 3.150685 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/sram_control.vhd
| 3 | 892 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_control IS
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT_ALL : OUT std_logic
);
END sram_control;
ARCHITECTURE primitive OF sram_control IS
SIGNAL reset_on : std_logic;
BEGIN
reset_logic: PROCESS
BEGIN
reset_on <= '0';
WAIT UNTIL RESET='1';
WAIT UNTIL falling_edge(CLK);
reset_on <= '1';
WAIT UNTIL rising_edge(CLK);
END PROCESS;
SELECT_ALL <= reset_on;
WE <= (NOT CLK) AND (reset_on OR (NOT C_READ));
CS <= (NOT CLK) AND (C_WRITE OR C_READ);
TO_DATA_IN <= (OTHERS => '0') WHEN reset_on='1'
ELSE DATA_IN;
END primitive;
|
bsd-3-clause
|
5bbae76246aade3de2be3fb88a6344ec
| 0.600897 | 3.129825 | false | false | false | false |
luebbers/reconos
|
support/pcores/message_manager_v1_00_a/hdl/vhdl/infer_bram_dual_port.vhd
| 1 | 3,324 |
-- *************************************************************************
-- File: infer_bram_dual_port.vhd
-- Date: 06/22/05
-- Purpose: File used to instantiate an inferred BRAM (dual port),
-- According to Xilinx, this will only work with 7.1 b/c of shared variables.
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- Comment out for simulation
--library Unisim;
--use Unisim.all;
--library Unisim;
--use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram_dual_port;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram_dual_port is
-- Constant declarations
constant BRAM_SIZE : integer := 2**ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
gpl-3.0
|
d208093a3d44a520ab288965d583dd5a
| 0.450361 | 4.283505 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_test7.vhd
| 2 | 629 |
--
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy is
port (
input : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
L: process(input)
variable tmp : std_logic_vector(7 downto 0);
begin
tmp := input; -- use multiple assignments to the same variable
tmp := (7 => input(7), others => '1'); -- inluding slices in a process
output <= tmp;
end process;
end;
|
gpl-2.0
|
c13ffaa7adc617965b75cdf645929e30
| 0.599364 | 3.594286 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/varray1.vhd
| 4 | 4,463 |
library ieee;
use ieee.std_logic_1164.all;
package diq_pkg is
component Add_Synth
generic (n: integer);
port (a,b: in std_logic_vector (n-1 downto 0);
cin: in std_logic;
comp : out std_logic;
sum : out std_logic_vector (n-1 downto 0) );
end component;
component Inc_Synth
generic (n: integer);
port (a: in std_logic_vector (n-1 downto 0);
sum : out std_logic_vector (n-1 downto 0) );
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use work.diq_pkg.all;
entity diq_array is
generic (width: integer := 8; size: integer := 7);
port (clk,reset: in std_logic;
din,bin,xin: in std_logic_vector (width-1 downto 0);
lin: in std_logic_vector (2 downto 0);
lout: out std_logic_vector (2 downto 0);
dout,bout,xout: out std_logic_vector (width-1 downto 0) );
end diq_array;
architecture systolic of diq_array is
component diq
generic (n: integer );
port (clk,reset: in std_logic;
lin: in std_logic_vector (2 downto 0);
din,bin,xin: in std_logic_vector (n-1 downto 0);
lout: out std_logic_vector (2 downto 0);
dout,bout,xout: out std_logic_vector (n-1 downto 0) );
end component;
type path is array (0 to size) of std_logic_vector (width-1 downto 0);
type l_path is array (0 to size) of std_logic_vector (2 downto 0);
signal x_path, d_path, b_path: path;
signal l_int: l_path;
begin
gen_arrays: for i in 0 to size-1 generate
each_array: diq generic map (n => width)
port map (clk => clk, din => d_path(i), bin => b_path(i), reset => reset,
xin => x_path(i), lin => l_int(i),
dout => d_path(i+1), bout => b_path(i+1),
xout => x_path(i+1), lout => l_int(i+1) );
end generate;
d_path(0) <= din;
b_path(0) <= bin;
x_path(0) <= xin;
l_int(0) <= lin;
dout <= d_path(size);
bout <= b_path(size);
xout <= x_path(size);
lout <= l_int(size);
end systolic;
library ieee;
use ieee.std_logic_1164.all;
use work.diq_pkg.all;
entity diq is
generic (n: integer := 8);
port (clk, reset: in std_logic;
din,bin,xin: in std_logic_vector (n-1 downto 0);
lin: in std_logic_vector (2 downto 0);
dout,bout,xout: out std_logic_vector (n-1 downto 0);
lout: out std_logic_vector (2 downto 0) );
end diq;
architecture diq_wordlevel of diq is
signal b_int, d_int, x_int, x_inv: std_logic_vector (n-1 downto 0);
signal l_int, l_inc: std_logic_vector (2 downto 0);
signal sel: std_logic;
signal zero,uno: std_logic;
begin
d_reg: process(clk,reset)
begin
if reset = '1' then
d_int <= (others => '0');
elsif (clk'event and clk = '1') then
d_int <= din;
end if;
end process;
l_reg: process(clk,reset)
begin
if reset = '1' then
l_int <= (others => '0');
elsif (clk'event and clk = '1') then
l_int <= lin;
end if;
end process;
b_reg: process(clk,reset)
begin
if reset = '1' then
b_int <= (others => '0');
elsif (clk'event and clk = '1') then
b_int <= bin;
end if;
end process;
x_reg: process(clk,reset)
begin
if reset = '1' then
x_int <= (others => '0');
elsif (clk'event and clk = '1') then
x_int <= xin;
end if;
end process;
zero <= '0';
uno <= '1';
addition: Add_Synth generic map (n => n)
port map (a => b_int, b => d_int, cin => zero, comp => open, sum => bout);
x_inv <= not x_int;
comparison: Add_Synth generic map (n => n)
port map (a => b_int, b => x_inv, cin => uno, comp => sel, sum => open);
incrementer: Inc_Synth generic map (n => 3)
port map (a => l_int, sum => l_inc);
-- outputs
lout <= l_inc when (sel = '1') else l_int;
dout <= d_int;
xout <= x_int;
end diq_wordlevel;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Inc_Synth is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end Inc_Synth;
architecture compact_inc of Inc_Synth is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + '1';
sum <= cx (n-1 downto 0);
end compact_inc;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Add_Synth is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic;
comp: out std_logic );
end Add_Synth;
architecture compact of Add_Synth is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + ('0' & b) + cin;
sum <= cx (n-1 downto 0);
comp <= cx(n-1);
end compact;
|
gpl-2.0
|
e11b98d3613470a553c415a9a41cd56a
| 0.621779 | 2.749846 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/LogoDisplay.vhd
| 1 | 2,927 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 15:40:47 03/15/2013
-- Design Name:
-- Module Name: logo_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LogoDisplay is
Generic (
X_START : integer range 2 to (Integer'high) := 40;
Y_START : integer := 512
);
Port ( CLK_I : in STD_LOGIC;
H_COUNT_I : in STD_LOGIC_VECTOR(11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR(11 downto 0);
RED_O : out STD_LOGIC_VECTOR(3 downto 0);
BLUE_O : out STD_LOGIC_VECTOR(3 downto 0);
GREEN_O : out STD_LOGIC_VECTOR(3 downto 0));
end LogoDisplay;
architecture Behavioral of LogoDisplay is
constant SZ_LOGO_WIDTH : natural := 335; -- Width of the logo frame
constant SZ_LOGO_HEIGHT : natural := 280; -- Height of the logo frame
COMPONENT BRAM_1
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
signal addr_reg : std_logic_vector(16 downto 0) := (others => '0');
signal douta : std_logic_vector(11 downto 0);
signal rst : std_logic;
signal en : std_logic;
begin
-- BRAM containing the logo data,
-- content in the BRAM_1.ngc file
Inst_BRAM_1 : BRAM_1
PORT MAP (
clka => CLK_I,
addra => addr_reg,
douta => douta
);
-- Restart Address Counter when Vcount arrives to the beginning of the Logo frame
rst <= '1' when (H_COUNT_I = 0 and V_COUNT_I = Y_START-1) else '0';
-- Increment Address counter only inside the frame
en <= '1' when (H_COUNT_I > X_START-2 and H_COUNT_I < X_START + SZ_LOGO_WIDTH - 1
and V_COUNT_I > Y_START and V_COUNT_I < Y_START + SZ_LOGO_HEIGHT -1 )
else '0';
-- Address counter
process (CLK_I, rst, en)
begin
if(rising_edge(CLK_I))then
if(rst = '1') then
addr_reg <= (others => '0');
elsif(en = '1') then
addr_reg <= addr_reg + 1;
end if;
end if;
end process;
-- Assign Outputs
RED_O <= douta(11 downto 8);
BLUE_O <= douta(3 downto 0);
GREEN_O <= douta(7 downto 4);
end Behavioral;
|
gpl-3.0
|
19ba20e78ae9737ce9660c9688171579
| 0.57465 | 3.49284 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/framework/resampling.vhd
| 1 | 22,708 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity resampling is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end resampling;
architecture Behavioral of resampling is
component uf_resampling
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
Port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the resampling user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- number of particles in total
number_of_particles_in_total : in integer;
-- index of first particles (the particles are sorted increasingly)
start_particle_index : in integer;
-- resampling function init
U_init : in integer;
-- address of the last 128 byte burst in local RAM
write_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- information if a write burst has been handled by the Framework
write_burst_done : in std_logic;
-- this signal has to be set to '1', if the Framework should write
-- the last burst from local RAM into Maim Memory
write_burst : out std_logic;
-- write burst done acknowledgement
write_burst_done_ack : out std_logic;
-- number of currently written particles
written_values : out integer;
-- if every particle is resampled, this signal has to be set to '1'
finished : out std_logic
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (initialize, read_particle_address, read_indexes_address,
read_n, read_particle_size, read_max_number_of_particles,
read_block_size, read_u_function,
wait_for_message, calculate_remaining_particles_1,
calculate_remaining_particles_2, calculate_remaining_particles_3,
calculate_remaining_particles_4, calculate_remaining_particles_5,
load_u_init, load_weights_to_local_ram_1,
load_weights_to_local_ram_2, write_to_ram,
write_burst_decision, write_burst_decision_2, write_burst,
write_burst_decision, read, write,
write_burst_done_ack, send_message,
send_measurement_1, send_measurement_2
);
-- current state
signal state : t_state := initialize;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- index array
signal index_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"10000000";
signal index_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- resampling function U array
signal U_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"10000000";
signal U_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_if_write : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_address_if_read : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- local RAM write_address
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like N, particle size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- message (received from message box). The number in the message says,
-- which particle block has to be sampled
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- block size, is the number of particles in a particle block
signal block_size : integer := 10;
-- local RAM data (particle weight)
signal weight_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 18;
-- number of particles still to resample
signal remaining_particles : integer := 0;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- size of a particle
signal particle_size : integer := 8;
-- temp variable
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
-- number of particles to resample
signal number_of_particles_to_resample : integer := 9;
-- write counter
signal write_counter : integer := 0;
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- start index
signal start_index : integer := 3;
-- temporary variables
signal offset : integer := 1;
signal offset2 : integer := 1;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for resampling user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the resampling user process
signal particles_loaded : std_logic := '0';
-- number of particles in local RAM
signal number_of_particles : integer := 18;
-- number of particles in total
signal number_of_particles_in_total : integer := 18;
-- index of first particles (the particles are sorted increasingly)
signal start_particle_index : integer := 0;
-- resampling function init
signal U_init : integer := 2000;
-- address of the last 128 byte burst in local RAM
signal write_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- information if a write burst has been handled by the Framework
signal write_burst_done : std_logic := '0';
-- the last burst from local RAM into Maim Memory
signal write_burst : std_logic := '0';
-- number of currently written index values
signal written_values : integer := 0;
-- if every particle is resampled, this signal has to be set to '1'
signal finished : std_logic := '0';
-- for switch 1: corrected local ram address. the least bit is inverted,
-- because else the local ram will be used incorrect
signal o_RAMAddrUserProcess : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrResampling : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEUserProcess : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEResampling : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataUserProcess : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataResampling : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- write burst done acknowledgement
signal write_burst_done_ack : std_logic := '0';
begin
-- entity of user process
user_process : uf_resampling
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrUserProcess, o_RAMData=>o_RAMDataUserProcess,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWEUserProcess, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, particles_loaded=>particles_loaded,
number_of_particles=>number_of_particles,
number_of_particles_in_total => number_of_particles_in_total,
start_particle_index=>start_particle_index,
U_init=>U_init, write_address=>write_address,
write_burst_done=>write_burst_done, write_burst=>write_burst,
write_burst_done_ack=>write_burst_done_ack, written_values=>written_values,
finished=>finished
);
-- burst ram interface
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrUserProcess(0 to C_BURST_AWIDTH-2) & not o_RAMAddrUserProcess(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrResampling(0 to C_BURST_AWIDTH-2) & not o_RAMAddrResampling(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEUserProcess when enable = '1' else o_RAMWEResampling;
-- switch 3: output ram data
o_RAMData <= o_RAMDataUserProcess when enable = '1' else o_RAMDataResampling;
number_of_particles_in_total <= N;
write_address <= "11111100000";
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Resampling:
--
-- (1) The index array adress, the number of particles (N) and
-- the particle size is received by message boxes
--
--
-- (2) Waiting for Message m (Start of a Resampling run)
-- Resample particles of m-th block
--
--
-- (3) calcualte the number of particles, which have to be resampled
--
--
-- (4) Copy the weight of the particles to the local RAM
--
--
-- (5) The user resampling process is started
--
--
-- (6) Every time the user process demands to make a write burst into
-- the index array, it is done by the Framework
--
--
-- (7) If the user process is finished go to step 8
--
--
-- (8) Send Message m (Stop of a Resampling run)
-- Particles of m-th block are resampled
--
------------------------------------------------------------------------------
fsm_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and max number of particles which fit in the local RAM
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable U_init_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= initialize;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when initialize =>
--! init state, receive particle array address
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK !!! (1 of 3)
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_address);
enable <= '0';
init <= '1';
if done then
state <= read_particle_address;
-- CHANGE BACK !!! (2 of 3)
--state <= wait_for_message;
end if;
when read_particle_address =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= read_indexes_address;
end if;
when read_indexes_address =>
--! read index array address
reconos_read_s (done, o_osif, i_osif, information_struct+4, index_array_start_address);
if done then
state <= read_n;
end if;
when read_n =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+8, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= read_particle_size;
end if;
when read_particle_size =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= read_block_size;
end if;
when read_block_size =>
--! read number of particles to resample
reconos_read (done, o_osif, i_osif, information_struct+16, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= read_u_function;
end if;
when read_u_function =>
--! read start index of first particle to resample
reconos_read_s (done, o_osif, i_osif, information_struct+20, U_array_start_address);
if done then
state <= wait_for_message;
end if;
when wait_for_message =>
--! wait for Message, that starts resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
--remaining_particles <= number_of_particles_to_resample;
--index_array_address <= index_array_address;
--particle_array_address <= particle_array_address;
local_ram_address <= (others=>'0');
local_ram_address_if_read <= (others=>'0');
local_ram_address_if_write <= (others=>'0');
init <= '1';
enable <= '0';
particles_loaded <= '0';
state <= calculate_remaining_particles_1;
--time_start <= TO_INTEGER(SIGNED(i_timebase));
-- CHANGE BACK !!! (3 of 3)
--state <= STATE_NEEDED_BURSTS_1;
end if;
when calculate_remaining_particles_1 =>
--! calcualte remaining particles
message2 <= message - 1;
state <= calculate_remaining_particles_2;
when calculate_remaining_particles_2 =>
--! calcualte remaining particles
offset <= message2 * block_size;
temp2 <= message2 * 4;
state <= calculate_remaining_particles_3;
when calculate_remaining_particles_3 =>
--! calcualte remaining particles
temp3 <= offset * 8;
state <= calculate_remaining_particles_4;
when calculate_remaining_particles_4 =>
--! calcualte remaining particles
remaining_particles <= N - offset;
index_array_address <= index_array_start_address + temp3;
start_index <= offset;
start_particle_index <= offset;
temp4 <= offset * particle_size;
U_array_address <= U_array_start_address + temp2;
state <= calculate_remaining_particles_5;
when calculate_remaining_particles_5 =>
--! calcualte remaining particles
if (remaining_particles > block_size) then
number_of_particles_to_resample <= block_size;
remaining_particles <= block_size;
else
number_of_particles_to_resample <= remaining_particles;
end if;
particle_array_address <= particle_array_start_address + temp4;
state <= load_u_init;
when load_u_init =>
--! load U_init
reconos_read (done, o_osif, i_osif, U_array_address, U_init_var);
if done then
U_init <= TO_INTEGER(SIGNED(U_init_var));
state <= load_weights_to_local_ram_1;
number_of_particles <= remaining_particles;
end if;
when load_weights_to_local_ram_1 =>
--! load weights to local ram, if this is done start the resampling
o_RAMWEResampling<= '0';
if (remaining_particles > 0) then
remaining_particles <= remaining_particles - 1;
state <= load_weights_to_local_ram_2;
else
enable <= '1';
particles_loaded <= '1';
init <= '0';
state <= write_burst_decision;
end if;
when load_weights_to_local_ram_2 =>
--! load weights to local ram
reconos_read_s (done, o_osif, i_osif, particle_array_address, weight_data);
if done then
state <= write_to_ram;
particle_array_address <= particle_array_address + particle_size;
end if;
when write_to_ram =>
--! write value to ram
o_RAMWEResampling<= '1';
o_RAMAddrResampling <= local_ram_address_if_read;
o_RAMDataResampling <= weight_data;
local_ram_address_if_read <= local_ram_address_if_read + 1;
state <= load_weights_to_local_ram_1;
when write_burst_decision =>
--! if write burst is demanded by user process, it will be done
write_burst_done <= '0';
if (finished = '1') then
-- everything is finished
state <= send_message;
enable <= '0';
particles_loaded <= '0';
--time_stop <= TO_INTEGER(SIGNED(i_timebase));
--init <= '1';
elsif (write_burst = '1') then
--state <= write_burst;
state <= write_burst_decision_2;
end if;
when write_burst_decision_2 =>
--! decides if there will be a burst or there will be several writes
-- NO MORE BURSTS
--if (written_values = 16) then
-- write only burst, if the burst is full
--state <= write_burst;
--else
local_ram_address_if_write <= write_address;
write_counter <= 2 * written_values;
enable <= '0';
state <= write_burst_decision;
--end if;
when write_burst =>
--! write bursts from local ram into index array
reconos_write_burst(done,o_osif,i_osif,(local_ram_start_address+8064),index_array_address);
if done then
write_burst_done <= '1';
index_array_address <= index_array_address + 128;
state <= write_burst_done_ack;
end if;
when write_burst_decision =>
-- decides if there is still something to write
if (write_counter > 0) then
o_RAMAddrResampling <= local_ram_address_if_write;
state <= read;
else
write_burst_done <= '1';
enable <= '1';
state <= write_burst_done_ack;
end if;
when read =>
--! read index values
state <= write;
when write =>
--! write data to index array
reconos_write(done, o_osif, i_osif, index_array_address, i_RAMData);
if done then
index_array_address <= index_array_address + 4;
local_ram_address_if_write <= local_ram_address_if_write + 1;
write_counter <= write_counter - 1;
state <= write_burst_decision;
end if;
when write_burst_done_ack =>
--! write bursts from local ram into index array
if (write_burst_done_ack = '1') then
write_burst_done <= '0';
state <= write_burst_decision;
end if;
when send_message =>
--! send Message (resampling is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE,
STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
particles_loaded <= '0';
state <= send_measurement_1;
end if;
when send_measurement_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
--time_measurement <= time_stop - time_start;
--state <= send_measurement_2;
--else
state <= wait_for_message;
--end if;
-- when send_measurement_2 =>
-- --! sends time measurement to message box
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
-- state <= wait_for_message;
-- end if;
when others =>
state <= wait_for_message;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
8d4de8261e68cbbd2f3755339e04056b
| 0.582658 | 3.59247 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/plbv46_dcr_bridge_v9_00_a/hdl/vhdl/plbv46_dcr_bridge.vhd
| 7 | 24,559 |
-------------------------------------------------------------------------------
-- plbv46_dcr_bridge - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2004, 2005, 2006, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: plbv46_dcr_bridge.vhd
-- Version: v1.01.a
-- Description: Top level of plbv46_dcr Bridge core
-- Instantiates plbv46_dcr_bridge_core and plbv46_slave_single v1.01.a
-- as Component and interfacing
--
-------------------------------------------------------------------------------
-- Structure:
-- plbv46_dcr_bridge.vhd
-- -- plbv46_dcr_bridge_core.vhd
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Author : SK
-- History :
-- ~~~~~~
-- SK 2006/09/19 -- Initial version.
-- ^^^^^^
-- ~~~~~~
-- SK 2008/12/15 -- Updated version v1_01_a, based upon v1_00_a core.
-- -- updated proc_common_v3_00_a and plbv46_slave_
-- -- single_v1_01_a core libraries.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Short Description of the plbv46_dcr_bridge.vhd code.
-- This file includes the interfacing of plbv46_dcr_bridge.vhd and
-- plbv46_single_slave_v1_00_a signals.
-------------------------------------------------------------------------------
-- Generic & Port Declarations
-------------------------------------------------------------------------------
------------------------------------------
-- == Definition of Generics ==
------------------------------------------
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_SPLB_AWIDTH -- PLBv46 address bus width
-- C_SPLB_DWIDTH -- PLBv46 data bus width
-- C_FAMILY -- Default family
-- C_SPLB_P2P -- Selects point-to-point or shared plb topology
-- C_SPLB_MID_WIDTH -- PLB Master ID Bus Width
-- C_SPLB_NUM_MASTERS -- Number of PLB Masters
-- C_SPLB_NATIVE_DWIDTH -- Width of the slave data bus
-- C_SPLB_SUPPORT_BURSTS -- Burst support
-- Definition of Ports:
-- ==
------------------------------------------
-- PLB_ABus -- Each master is required to provide a valid 32-bit
-- -- address when its request signal is asserted. The PLB
-- -- will then arbitrate the requests and allow the highest
-- -- priority masters address to be gated onto the PLB_ABus
-- PLB_PAValid -- This signal is asserted by the PLB arbiter in response
-- -- to the assertion of Mn_request and to indicate
-- -- that there is a valid primary address and transfer
-- -- qualifiers on the PLB outputs
-- PLB_masterID -- These signals indicate to the slaves the identification
-- -- of the master of the current transfer
-- PLB_RNW -- This signal is driven by the master and is used to
-- -- indicate whether the request is for a read or a write
-- -- transfer
-- PLB_BE -- These signals are driven by the master. For a non-line
-- -- and non-burst transfer they identify which
-- -- bytes of the target being addressed are to be read
-- -- from or written to. Each bit corresponds to a byte
-- -- lane on the read or write data bus
-- PLB_size -- The PLB_size(0:3) signals are driven by the master
-- -- to indicate the size of the requested transfer.
-- PLB_type -- The Mn_type signals are driven by the master and are
-- -- used to indicate to the slave, via the PLB_type
-- -- signals, the type of transfer being requested
-- PLB_wrDBus -- This data bus is used to transfer data between a
-- -- master and a slave during a PLB write transfer
------------------------------------------
-- == SLAVE DCR BRIDGE RESPONSE SIGNALS ==
------------------------------------------
-- Sl_addrAck -- This signal is asserted to indicate that the
-- -- slave has acknowledged the address and will
-- -- latch the address
-- Sl_SSize -- The Sl_SSize(0:1) signals are outputs of all
-- -- non 32-bit PLB slaves. These signals are
-- -- activated by the slave with the assertion of
-- -- PLB_PAValid or SAValid and a valid slave
-- -- address decode and must remain negated at
-- -- all other times.
-- Sl_wait -- This signal is asserted to indicate that the
-- -- slave has recognized the PLB address as a valid address
-- Sl_rearbitrate -- This signal is asserted to indicate that the
-- -- slave is unable to perform the currently
-- -- requested transfer and require the PLB arbiter
-- -- to re-arbitrate the bus
-- Sl_wrDAck -- This signal is driven by the slave for a write
-- -- transfer to indicate that the data currently on the
-- -- PLB_wrDBus bus is no longer required by the slave
-- -- i.e. data is latched
-- Sl_wrComp -- This signal is asserted by the slave to
-- -- indicate the end of the current write transfer.
-- Sl_rdDBus -- Slave read bus
-- Sl_rdDAck -- This signal is driven by the slave to indicate
-- -- that the data on the Sl_rdDBus bus is valid and
-- -- must be latched at the end of the current clock cycle
-- Sl_rdComp -- This signal is driven by the slave and is used
-- -- to indicate to the PLB arbiter that the read
-- -- transfer is either complete, or will be complete
-- -- by the end of the next clock cycle
-- Sl_MBusy -- These signals are driven by the slave and
-- -- are used to indicate that the slave is either
-- -- busy performing a read or a write transfer, or
-- -- has a read or write transfer pending
-- Sl_MWrErr -- These signals are driven by the slave and
-- -- are used to indicate that the slave has encountered an
-- -- error during a write transfer that was initiated
-- -- by this master
-- Sl_MRdErr -- These signals are driven by the slave and are
-- -- used to indicate that the slave has encountered an
-- -- error during a read transfer that was initiated
-- -- by this master
------------------------------------------
-- == SIGNALS FROM PLBV46DCR_CORE TO THE DCR SLAVE DEVICE -- ==
------------------------------------------
-- DCR_plbAck -- DCR Slave ACK in
-- DCR_plbDBusIn -- DCR to PLB data bus in
-- PLB_dcrRead -- PLB to DCR read out to slave
-- PLB_dcrWrite -- PLB to DCR write out to slave
-- PLB_dcrABus -- PLB to DCR address bus out to slave
-- PLB_dcrDBusOut -- PLB to DCR data bus out to slave
-- PLB_dcrClk -- DCR clock for the slave devices
-- PLB_dcrRst -- DCR reset for the slave devices
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.ipif_pkg.SLV64_ARRAY_TYPE;
use proc_common_v3_00_a.ipif_pkg.INTEGER_ARRAY_TYPE;
use proc_common_v3_00_a.ipif_pkg.calc_num_ce;
library plbv46_slave_single_v1_01_a;
library plbv46_dcr_bridge_v9_00_a;
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity plbv46_dcr_bridge is
generic (
C_FAMILY : STRING := "virtex5";
C_BASEADDR : STD_LOGIC_VECTOR := X"FFFFFFFF";
C_HIGHADDR : STD_LOGIC_VECTOR := X"00000000";
-- PLBv46 slave single block generics
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 32;
C_SPLB_P2P : integer range 0 to 1 := 0;
C_SPLB_MID_WIDTH : integer range 0 to 4 := 1;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 1;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32;
C_SPLB_SUPPORT_BURSTS : integer range 0 to 1 := 0
);
port (
--PLBv46 SLAVE SINGLE INTERFACE
-- system signals
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
-- Bus slave signals
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
--slave DCR Bridge response signals
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Unused Bus slave signals
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
-- Unused Slave Response Signals
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- signals from plbv46_dcr_core to DCR slaves
DCR_plbAck : in STD_LOGIC;
DCR_plbDBusIn : in STD_LOGIC_VECTOR(0 to C_SPLB_NATIVE_DWIDTH-1);
PLB_dcrRead : out STD_LOGIC;
PLB_dcrWrite : out STD_LOGIC;
PLB_dcrABus : out STD_LOGIC_VECTOR(0 to 9);
PLB_dcrDBusOut : out STD_LOGIC_VECTOR(0 to C_SPLB_NATIVE_DWIDTH-1);
PLB_dcrClk : out STD_LOGIC;
PLB_dcrRst : out STD_LOGIC
);
--fan-out attributes for XST
--fan-out attributes for MPD
-----------------------------------------------------------------------------
ATTRIBUTE CORE_STATE : string;
ATTRIBUTE CORE_STATE of plbv46_dcr_bridge : entity is "ACTIVE";
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of plbv46_dcr_bridge : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of plbv46_dcr_bridge : entity is "BRIDGE";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of plbv46_dcr_bridge : entity is "HDL";
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of SPLB_Clk : signal is "10000";
ATTRIBUTE MAX_FANOUT of SPLB_Rst : signal is "10000";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of SPLB_Clk : signal is "Clk";
ATTRIBUTE SIGIS of SPLB_Rst : signal is "Rst";
ATTRIBUTE SIGIS of PLB_dcrClk : signal is "Clk";
ATTRIBUTE SIGVAL : string;
ATTRIBUTE SIGVAL of DCR_plbAck : signal is "DCR_Ack";
ATTRIBUTE SIGVAL of DCR_plbDBusIn : signal is "DCR_M_DBus";
ATTRIBUTE SIGVAL of PLB_dcrRead : signal is "M_dcrRead";
ATTRIBUTE SIGVAL of PLB_dcrWrite : signal is "M_dcrWrite";
ATTRIBUTE SIGVAL of PLB_dcrABus : signal is "M_dcrABus";
ATTRIBUTE SIGVAL of PLB_dcrDBusOut : signal is "M_dcrDBus";
ATTRIBUTE BUSIF : string;
ATTRIBUTE BUSIF of SPLB_Clk : signal is "SPLB";
ATTRIBUTE BUSIF of DCR_plbAck : signal is "MDCR";
ATTRIBUTE BUSIF of DCR_plbDBusIn : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrRead : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrWrite : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrABus : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrDBusOut : signal is "MDCR";
ATTRIBUTE BRIDGE_TO : string;
ATTRIBUTE BRIDGE_TO of C_BASEADDR : constant is "MDCR";
-----------------------------------------------------------------------------
end entity plbv46_dcr_bridge;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture implementation of plbv46_dcr_bridge is
-------------------------------------------------------------------------------
-- Constant Declarations
constant ZERO_PADS : std_logic_vector(0 to 31) := X"00000000";
-- Decoder address range definition constants starts
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_PADS & C_BASEADDR,
ZERO_PADS & C_HIGHADDR
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1
);
-- Decoder address range definition constants ends
-------------------------------------------------------------------------------
-- local signal declaration goes here
--bus2ip signals
signal bus2IP_Clk : std_logic;
signal bus2IP_Reset : std_logic;
signal bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1 );
signal bus2IP_BE : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8 - 1 );
signal bus2IP_CS : std_logic_vector(0 to (ARD_ADDR_RANGE_ARRAY'LENGTH/2)-1);
signal bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2IP_Data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH - 1 );
signal bus2IP_RNW : std_logic;
-- ip2bus signals
signal ip2Bus_Data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH - 1 );
signal ip2Bus_WrAck : std_logic;
signal ip2Bus_RdAck : std_logic;
signal ip2Bus_Error : std_logic;
-- end of local signal declaration
begin -- architecture implementation
----------------------------------
-- INSTANTIATE PLBv46 SLAVE SINGLE
----------------------------------
PLBv46_IPIF_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_BUS2CORE_CLK_RATIO => 1,
C_INCLUDE_DPHASE_TIMER => 1,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
-- System signals ---------------------------------------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
-- Bus Slave signals ------------------------------------------------
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
-- Slave Response Signals -------------------------------------------
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
-- IP Interconnect (IPIC) port signals ------------------------------
IP2Bus_Data => ip2Bus_Data,
IP2Bus_WrAck => ip2Bus_WrAck,
IP2Bus_RdAck => ip2Bus_RdAck,
IP2Bus_Error => ip2Bus_Error,
Bus2IP_Addr => bus2IP_Addr,
Bus2IP_Data => bus2IP_Data,
Bus2IP_RNW => bus2IP_RNW,
Bus2IP_BE => bus2IP_BE,
Bus2IP_CS => bus2IP_CS,
Bus2IP_RdCE => bus2IP_RdCE,
Bus2IP_WrCE => bus2IP_WrCE,
Bus2IP_Clk => bus2IP_Clk,
Bus2IP_Reset => bus2IP_Reset
);
-- component plbv46_dcr_bridge_core interface starts here
plbv46_dcr_bridge_core_1 : entity plbv46_dcr_bridge_v9_00_a.plbv46_dcr_bridge_core
port map (
-- IP Interconnect (IPIC) port signals ----
Bus2IP_Clk => bus2IP_Clk,
Bus2IP_Reset => bus2IP_Reset,
Bus2IP_Addr => bus2IP_Addr,
Bus2IP_Data => bus2IP_Data,
Bus2IP_BE => bus2IP_BE,
Bus2IP_CS => bus2IP_CS(0),
Bus2IP_RdCE => bus2IP_RdCE(0),
Bus2IP_WrCE => bus2IP_WrCE(0),
IP2Bus_RdAck => ip2Bus_RdAck,
IP2Bus_WrAck => ip2Bus_WrAck,
IP2Bus_Error => ip2Bus_Error,
IP2Bus_Data => ip2Bus_Data,
-- signals from plbv46dcr_core --
DCR_plbDBusIn => DCR_plbDBusIn,
DCR_plbAck => DCR_plbAck,
PLB_dcrABus => PLB_dcrABus,
PLB_dcrDBusOut => PLB_dcrDBusOut,
PLB_dcrRead => PLB_dcrRead,
PLB_dcrWrite => PLB_dcrWrite,
PLB_dcrRst => PLB_dcrRst,
PLB_dcrClk => PLB_dcrClk
);
-- component interfacing ends here.
end architecture implementation;
|
gpl-3.0
|
fed86811cfa29567143846bf3cd7b5d4
| 0.483204 | 4.479117 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/framework/sampling.vhd
| 1 | 33,206 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity sampling is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end sampling;
architecture Behavioral of sampling is
component uf_prediction is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the prediction user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- size of one particle
particle_size : in integer;
-- if every particle is sampled, this signal has to be set to '1'
finished : out std_logic);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
constant C_MB_EXIT : std_logic_vector(0 to 31) := X"00000003";
-- states
type state_t is (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLES_ADDRESS,
STATE_READ_N,
STATE_READ_PARTICLE_SIZE,
STATE_READ_MAX_NUMBER_OF_PARTICLES,
STATE_READ_BLOCK_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_PARTICLES_1,
STATE_CALCULATE_REMAINING_PARTICLES_2,
STATE_CALCULATE_REMAINING_PARTICLES_3,
STATE_CALCULATE_REMAINING_PARTICLES_4,
STATE_NEEDED_BURSTS_1,
STATE_NEEDED_BURSTS_2,
STATE_NEEDED_BURSTS_3,
STATE_NEEDED_BURSTS_4,
STATE_COPY_PARTICLE_BURST_DECISION,
STATE_COPY_PARTICLE_BURST,
STATE_COPY_PARTICLE_BURST_2,
STATE_COPY_PARTICLE_BURST_3,
STATE_COPY_PARTICLE_BURST_4,
STATE_PREDICTION,
STATE_PREDICTION_DONE,
STATE_WRITE_BURST_DECISION,
STATE_WRITE_BURST,
STATE_CALCULATE_WRITES_1,
STATE_CALCULATE_WRITES_2,
STATE_CALCULATE_WRITES_3,
STATE_CALCULATE_WRITES_4,
STATE_WRITE_DECISION,
STATE_READ,
STATE_WRITE,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_SEND_INFO_1,
STATE_SEND_INFO_2,
STATE_EXIT
);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07",
X"08",
X"09",
X"0A",
X"0B",
X"0C",
X"0D",
X"0E",
X"0F",
X"10",
X"11",
X"12",
X"13",
X"14",
X"15",
X"16",
X"17",
X"18",
X"19",
X"1A",
X"1B",
X"1C",
X"1D",
X"1E",
X"1F",
X"20",
X"21",
X"22",
X"23",
X"24",
X"25",
X"26",
X"27",
X"28",
X"29"
);
constant decode : decode_t := (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLES_ADDRESS,
STATE_READ_N,
STATE_READ_PARTICLE_SIZE,
STATE_READ_MAX_NUMBER_OF_PARTICLES,
STATE_READ_BLOCK_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_PARTICLES_1,
STATE_CALCULATE_REMAINING_PARTICLES_2,
STATE_CALCULATE_REMAINING_PARTICLES_3,
STATE_CALCULATE_REMAINING_PARTICLES_4,
STATE_NEEDED_BURSTS_1,
STATE_NEEDED_BURSTS_2,
STATE_NEEDED_BURSTS_3,
STATE_NEEDED_BURSTS_4,
STATE_COPY_PARTICLE_BURST_DECISION,
STATE_COPY_PARTICLE_BURST,
STATE_COPY_PARTICLE_BURST_2,
STATE_COPY_PARTICLE_BURST_3,
STATE_COPY_PARTICLE_BURST_4,
STATE_PREDICTION,
STATE_PREDICTION_DONE,
STATE_WRITE_BURST_DECISION,
STATE_WRITE_BURST,
STATE_CALCULATE_WRITES_1,
STATE_CALCULATE_WRITES_2,
STATE_CALCULATE_WRITES_3,
STATE_CALCULATE_WRITES_4,
STATE_WRITE_DECISION,
STATE_READ,
STATE_WRITE,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_SEND_INFO_1,
STATE_SEND_INFO_2,
STATE_EXIT
);
-- current state
signal state : state_t := STATE_INIT;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal current_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter array address
signal parameter_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM write_address
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like N, particle size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 4;
-- number of particles still to resample
signal remaining_particles : integer := 4;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered (for writing back)
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 48;
-- temp variable
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal offset : integer := 0;
-- start particle index
signal start_particle_index : integer := 0;
-- maximum number of particles, which fit into the local RAM (minus 128 byte)
signal max_number_of_particles : integer := 168;
-- number of bytes, which are not written with valid particle data
signal diff : integer := 0;
-- number of writes
signal number_of_writes : integer := 0;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_address_if_read : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_address_if_write : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- message (received from message box). The number in the message says,
-- which particle block has to be sampled
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- block size, is the number of particles in a particle block
signal block_size : integer := 10;
signal parameter_size : integer := 32;
-- time values for start, stop and the difference of both
--signal time_start : integer := 0;
--signal time_stop : integer := 0;
--signal time_measurement : integer := 0;
signal particle_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for prediction user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the resampling user process
signal particles_loaded : std_logic := '0';
-- number of particles in local RAM
signal number_of_particles : integer := 4;
-- size of one particle
signal particle_size_2 : integer := 0;
-- if every particle is resampled, this signal has to be set to '1'
signal finished : std_logic := '0';
-- corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrPrediction : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrSampling : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEPrediction : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWESampling : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataPrediction : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataSampling : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_prediction
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrPrediction, o_RAMData=>o_RAMDataPrediction,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWEPrediction, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, particles_loaded=>particles_loaded,
number_of_particles=>number_of_particles,
particle_size=>particle_size_2, finished=>finished);
-- burst ram interface
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrPrediction(0 to C_BURST_AWIDTH-2) & not o_RAMAddrPrediction(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrSampling(0 to C_BURST_AWIDTH-2) & not o_RAMAddrSampling(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEPrediction when enable = '1' else o_RAMWESampling;
-- switch 3: output ram data
o_RAMData <= o_RAMDataPrediction when enable = '1' else o_RAMDataSampling;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Sampling:
--
-- 1) The Parameter are copied to the first 128 bytes of the local RAM
-- Other information are set
--
--
-- 2) Waiting for Message m (Start of a Sampling run)
-- Message m: sample particles of m-th particle block
--
--
-- 3) The number of needed bursts is calculated to fill the local RAM
-- The number only differs from 63, if it is for the last particles,
-- which fit into the local ram.
--
--
-- 4) The particles are copied into the local RAM by burst reads
--
--
-- 5) The user prediction process is run
--
--
-- 6) After prediction the particles are written back to Main Memory.
-- Since there can be several sampling threads, there has to be
-- special treatment for the last 128 byte, which are written
-- in 4 byte blocks and not in a 128 byte burst.
--
--
-- 7) If the user process is finished and more particle need to be
-- sampled, then go to step 3 else to step 8
--
--
-- 8) Send message m (Stop of a Sampling run)
-- Particles of m-th particle block are sampled
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
variable success : boolean;
-- signals for N, particle_size and max number of particles which fit in the local RAM
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable max_number_of_particles_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable resume_state_enc : reconos_state_enc_t := (others => '0');
--variable preempted : boolean;
begin
if reset = '1' then
enable <= '0';
init <= '1';
reconos_reset(o_osif, i_osif);
resume_state_enc := (others => '0');
done := false;
success := false;
--preempted := false;
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
--if success then
-- -- preempted thread
-- preempted := true;
-- state <= decode(to_integer(unsigned(resume_state_enc)));
--else
-- unpreempted
state <= STATE_INIT;
--end if;
end if;
when STATE_INIT =>
--! init state, receive particle array address
-- TODO: C H A N G E !!! (1 of 3)
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
if done then
local_ram_address <= (others => '0');
local_ram_start_address <= (others => '0');
particles_loaded <= '0';
-- TODO: C H A N G E !!! (2 of 3)
state <= STATE_READ_PARTICLES_ADDRESS;
--state <= STATE_SEND_INFO_1;
--state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_SEND_INFO_1 =>
-- send particles array address
--reconos_mbox_put(done,success,o_osif,i_osif,C_MB_MEASUREMENT,information_struct);
--if (done and success) then
state <= STATE_READ_PARTICLES_ADDRESS;
--end if;
when STATE_READ_PARTICLES_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_N;
-- TODO: CHANGE CHANGE CHANGE
--state <= STATE_SEND_INFO_2;
end if;
when STATE_SEND_INFO_2 =>
-- send particles array address
--reconos_mbox_put(done,success,o_osif,i_osif,C_MB_MEASUREMENT, particle_array_start_address);
--if (done and success) then
state <= STATE_READ_N;
--end if;
when STATE_READ_N =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_MAX_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_MAX_NUMBER_OF_PARTICLES =>
--! read max number of particles, which fit into 63 bursts (128 bytes per burst)
reconos_read (done, o_osif, i_osif, information_struct+12, max_number_of_particles_var);
if done then
particle_size_2 <= particle_size / 4;
max_number_of_particles <= TO_INTEGER(SIGNED(max_number_of_particles_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read bock size, this is the size of how many particles are in one block.
-- A message sends the block number
reconos_read (done, o_osif, i_osif, information_struct+16, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
--state <= STATE_WAIT_FOR_MESSAGE;
-- CHANGE BACK !!! (1 of 2)
state <= STATE_READ_PARAMETER_ADDRESS;
end if;
when STATE_READ_PARAMETER_ADDRESS =>
--! read parameter array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, parameter_array_address);
if done then
parameter_size <= 32;
local_ram_address_if <= (others=>'0');
state <= STATE_COPY_PARAMETER;
end if;
when STATE_COPY_PARAMETER =>
--!
o_RAMWESampling <= '0';
if (parameter_size > 0) then
parameter_size <= parameter_size - 1;
state <= STATE_COPY_PARAMETER_2;
else
--if preempted then
-- preempted := false;
-- state <= STATE_CALCULATE_REMAINING_PARTICLES_1;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
end if;
when STATE_COPY_PARAMETER_2 =>
--!
reconos_read_s (done, o_osif, i_osif, parameter_array_address, ram_data);
if done then
state <= STATE_COPY_PARAMETER_3;
end if;
when STATE_COPY_PARAMETER_3 =>
--!
parameter_array_address <= parameter_array_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
o_RAMWESampling <= '1';
o_RAMAddrSampling <= local_ram_address_if;
o_RAMDataSampling <= ram_data;
state <= STATE_COPY_PARAMETER;
-- when STATE_READ_PARAMETER =>
-- --! copy all parameter in one burst
-- reconos_read_burst(done, o_osif, i_osif, local_ram_start_address, parameter_array_address);
-- if done then
-- state <= STATE_CHECK;
-- end if;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for message, that starts Sampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
--reconos_flag_yield(o_osif, i_osif, encode(STATE_WAIT_FOR_MESSAGE));
if done then
if success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
particles_loaded <= '0';
enable <= '0';
init <= '1';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
--if preempted then
-- state <= STATE_INIT;
--else
state <= STATE_CALCULATE_REMAINING_PARTICLES_1;
--end if;
else
state <= STATE_EXIT;
end if;
end if;
when STATE_CALCULATE_REMAINING_PARTICLES_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
state <= STATE_CALCULATE_REMAINING_PARTICLES_2;
when STATE_CALCULATE_REMAINING_PARTICLES_2 =>
--! calculates particle array address and number of particles to sample
remaining_particles <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_PARTICLES_3;
when STATE_CALCULATE_REMAINING_PARTICLES_3 =>
--! calculates particle array address and number of particles to sample
remaining_particles <= N - remaining_particles;
particle_array_address <= particle_array_start_address;
state <= STATE_CALCULATE_REMAINING_PARTICLES_4;
when STATE_CALCULATE_REMAINING_PARTICLES_4 =>
--! calculates particle array address and number of particles to sample
if (remaining_particles > block_size) then
remaining_particles <= block_size;
end if;
current_particle_array_address <= particle_array_start_address;
state <= STATE_NEEDED_BURSTS_1;
when STATE_NEEDED_BURSTS_1 =>
--! decision how many bursts are needed
local_ram_address <= local_ram_start_address + 128;
local_ram_address_if_read <= local_ram_start_address_if + 32;
particles_loaded <= '0';
enable <= '0';
init <= '1';
--start_particle_index <= N - remaining_particles;
start_particle_index <= message2 * block_size;
if (remaining_particles <= 0) then
state <= STATE_SEND_MESSAGE;
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
else
temp <= remaining_particles * particle_size;
state <= STATE_NEEDED_BURSTS_2;
end if;
when STATE_NEEDED_BURSTS_2 =>
--! decision how many bursts are needed
offset <= start_particle_index * particle_size;
state <= STATE_NEEDED_BURSTS_3;
when STATE_NEEDED_BURSTS_3 =>
--! decision how many bursts are needed
current_particle_array_address <= particle_array_start_address + offset;
particle_array_address <= particle_array_start_address + offset;
if (temp >= 8064) then --8064 = 63*128
--copy as much particles as possible
number_of_bursts <= 63;
number_of_bursts_remember <= 63;
number_of_particles <= max_number_of_particles;
state <= STATE_COPY_PARTICLE_BURST_DECISION;
else
-- copy only remaining particles
number_of_bursts <= temp / 128;
number_of_bursts_remember <= temp / 128;
number_of_particles <= remaining_particles;
state <= STATE_NEEDED_BURSTS_4;
end if;
when STATE_NEEDED_BURSTS_4 =>
--! decision how many bursts are needed
number_of_bursts <= number_of_bursts + 1;
number_of_bursts_remember <= number_of_bursts_remember + 1;
state <= STATE_COPY_PARTICLE_BURST_DECISION;
when STATE_COPY_PARTICLE_BURST_DECISION =>
--! check if another burst is needed
if (number_of_bursts > 63) then
number_of_bursts <= 63;
elsif (number_of_bursts > 0) then
number_of_bursts <= number_of_bursts - 1;
state <= STATE_COPY_PARTICLE_BURST;
elsif (remaining_particles <= 0) then
-- check it
state <= STATE_SEND_MESSAGE;
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
else
remaining_particles <= remaining_particles - number_of_particles;
state <= STATE_PREDICTION;
enable <= '1';
particles_loaded <= '1';
init <= '0';
end if;
when STATE_COPY_PARTICLE_BURST =>
--! read another burst
-- NO MORE BURSTS
temp3 <= 32;
state <= STATE_COPY_PARTICLE_BURST_2;
--reconos_read_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
--if done then
-- state <= STATE_COPY_PARTICLE_BURST_DECISION;
-- --if (local_ram_address < 8064) then
-- local_ram_address <= local_ram_address + 128;
-- --end if;
-- current_particle_array_address <= current_particle_array_address + 128;
--end if;
when STATE_COPY_PARTICLE_BURST_2 =>
--! read another burst
-- NO MORE BURSTS
enable <= '0';
o_RAMWESampling<= '0';
if (temp3 > 0) then
state <= STATE_COPY_PARTICLE_BURST_3;
temp3 <= temp3 - 1;
else
state <= STATE_COPY_PARTICLE_BURST_DECISION;
end if;
when STATE_COPY_PARTICLE_BURST_3 =>
--! read another burst
-- NO MORE BURSTS
--! load data to local ram
reconos_read_s (done, o_osif, i_osif, particle_array_address, particle_data);
if done then
state <= STATE_COPY_PARTICLE_BURST_4;
particle_array_address <= particle_array_address + 4;
end if;
when STATE_COPY_PARTICLE_BURST_4 =>
--! write particle data to local ram
o_RAMWESampling<= '1';
o_RAMAddrSampling <= local_ram_address_if_read;
o_RAMDataSampling <= particle_data;
local_ram_address_if_read <= local_ram_address_if_read + 1;
state <= STATE_COPY_PARTICLE_BURST_2;
when STATE_PREDICTION =>
--! start prediction user process and wait until prediction is finished
init <= '0';
enable <= '1';
particles_loaded <= '0';
if (finished = '1') then
state <= STATE_PREDICTION_DONE;
end if;
when STATE_PREDICTION_DONE =>
--! start prediction user process and wait until it is finished
init <= '1';
enable <= '0';
particles_loaded <= '0';
current_particle_array_address <= particle_array_address;
local_ram_address <= local_ram_start_address + 128;
local_ram_address_if_write <= local_ram_start_address_if + 32;
number_of_bursts <= number_of_bursts_remember;
state <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_BURST_DECISION =>
--! if write burst is demanded by user process, it will be done
--if (number_of_bursts > 63) then
-- number_of_bursts <= 63;
----else
-- -- NO MORE BURSTS
--elsif (number_of_bursts > 1) then
-- state <= STATE_WRITE_BURST;
--elsif (number_of_bursts <= 1) then
number_of_bursts <= 0;
state <= STATE_CALCULATE_WRITES_1;
--diff <= (number_of_bursts_remember * 128);
--end if;
when STATE_WRITE_BURST =>
--! write bursts from local ram into index array
-- TODO: FIXME!!! WRITES COMMENTED OUT --- CHANGE CHANGE CHANGE
--reconos_write_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
--if done then
local_ram_address <= local_ram_address + 128;
local_ram_address_if_write <= local_ram_address_if_write + 32;
current_particle_array_address <= current_particle_array_address + 128;
number_of_bursts <= number_of_bursts - 1;
state <= STATE_WRITE_BURST_DECISION;
--end if;
when STATE_CALCULATE_WRITES_1 =>
--! calculates number of writes (1/4)
temp2 <= number_of_particles * particle_size;
state <= STATE_CALCULATE_WRITES_4;
-- NO MORE BURSTS
--state <= STATE_CALCULATE_WRITES_2;
when STATE_CALCULATE_WRITES_2 =>
--! calculates number of writes (2/4)
diff <= diff - temp2;
state <= STATE_CALCULATE_WRITES_3;
when STATE_CALCULATE_WRITES_3 =>
--! calculates number of writes (3/4)
number_of_writes <= 128 - diff;
state <= STATE_CALCULATE_WRITES_4;
when STATE_CALCULATE_WRITES_4 =>
--! calculates number of writes (4/4)
-- NO MORE BURSTS
--number_of_writes <= number_of_writes / 4;
number_of_writes <= temp2 / 4;
state <= STATE_WRITE_DECISION;
when STATE_WRITE_DECISION =>
--! decide if a reconos write is needed
if (number_of_writes <= 0) then
state <= STATE_NEEDED_BURSTS_1;
else
-- read local ram data
state <= STATE_READ;
o_RAMAddrSampling <= local_ram_address_if_write;
end if;
when STATE_READ =>
--! read 4 byte from local RAM
number_of_writes <= number_of_writes - 1;
--local_ram_address_if <= local_ram_address_if + 1;
o_RAMAddrSampling <= local_ram_address_if_write;
state <= STATE_WRITE;
when STATE_WRITE =>
--! write 4 byte to particle array in main memory
-- TODO: FIXME!!! WRITES COMMENTED OUT --- CHANGE CHANGE CHANGE
reconos_write(done, o_osif, i_osif, current_particle_array_address, i_RAMData);
if done then
local_ram_address_if_write <= local_ram_address_if_write + 1;
current_particle_array_address <= current_particle_array_address + 4;
if (number_of_writes <= 0) then
state <= STATE_NEEDED_BURSTS_1;
else
o_RAMAddrSampling <= local_ram_address_if_write;
state <= STATE_READ;
end if;
end if;
when STATE_SEND_MESSAGE =>
--! send message i (sampling is finished)
reconos_mbox_put(done,success,o_osif,i_osif,C_MB_DONE,STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
particles_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! check, if thread shall exit
reconos_mbox_tryget(done, success, o_osif, i_osif, C_MB_EXIT, message_var);
if done then
if success then
state <= STATE_EXIT;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
-- state <= STATE_WAIT_FOR_MESSAGE;
--end if;
-- when STATE_SEND_MEASUREMENT_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
-- state <= STATE_WAIT_FOR_MESSAGE;
-- end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
24969db8f385b101a46f35dfc0caeaed
| 0.548576 | 3.833083 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/dist_mem_gen_0/sim/dist_mem_gen_0.vhd
| 1 | 5,775 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_9;
USE dist_mem_gen_v8_0_9.dist_mem_gen_v8_0_9;
ENTITY dist_mem_gen_0 IS
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0)
);
END dist_mem_gen_0;
ARCHITECTURE dist_mem_gen_0_arch OF dist_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dist_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_9 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(1023 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_9;
BEGIN
U0 : dist_mem_gen_v8_0_9
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 12,
C_DEFAULT_DATA => "0",
C_DEPTH => 4096,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "dist_mem_gen_0.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 1024,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1024)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END dist_mem_gen_0_arch;
|
mit
|
feb57963cb3adf283c5095097b3adf98
| 0.626147 | 3.383128 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/RgbLed.vhd
| 1 | 10,368 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 18:48:32 03/05/2013
-- Design Name:
-- Module Name: rgbLed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the controller for the RGB Leds. It uses three PWM components
-- to generate the sweeping RGB colors and four debouncers for the incoming buttons
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity RgbLed is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
-- Command button signals
btnl_i : in std_logic;
btnc_i : in std_logic;
btnr_i : in std_logic;
btnd_i : in std_logic;
-- LD16 PWM output signals
pwm1_red_o : out std_logic;
pwm1_green_o : out std_logic;
pwm1_blue_o : out std_logic;
-- LD17 PWM output signals
pwm2_red_o : out std_logic;
pwm2_green_o : out std_logic;
pwm2_blue_o : out std_logic;
-- R, G and B signals connecting to the VGA controller
-- to be displayed on the screen
RED_OUT : out std_logic_vector(7 downto 0);
GREEN_OUT : out std_logic_vector(7 downto 0);
BLUE_OUT : out std_logic_vector(7 downto 0)
);
end RgbLed;
architecture Behavioral of RgbLed is
----------------------------------------------------------------------------------
-- Component Declarations
----------------------------------------------------------------------------------
-- Pwm generator
component Pwm is
port(
clk_i : in std_logic;
data_i : in std_logic_vector(7 downto 0);
pwm_o : out std_logic);
end component;
-- Debouncer for the buttons
component Dbncr is
generic(
NR_OF_CLKS : integer := 4095);
port(
clk_i : in std_logic;
sig_i : in std_logic;
pls_o : out std_logic);
end component;
-- Clock divider, will determine the frequency at which
-- the color components will increase/decrease
-- 100MHz/10000000 = 10Hz
constant CLK_DIV : integer := 10000000;
--Clock divider counter and signal
signal clkCnt : integer := 0;
signal slowClk : std_logic;
-- colorCnt will determine the PWM values to be sent to the RGB Led color components
-- colorCnt(9 downto 5) will be increasing and colorCnt(4 downto 0) will be decreasing
signal colorCnt : std_logic_vector(9 downto 0) := "0000011111";
-- specCnt determines which color components are swept
-- 0: decrease Red, increase Green
-- 1: decrease Green, increase Blue
-- 2: decrease Blue, increase Red
signal specCnt : integer range 0 to 2 := 0;
-- Red, Green and Blue data signals
signal red, green, blue : std_logic_vector(7 downto 0);
-- PWM Red, Green and BLue signals going to the RGB Leds
signal pwm_red, pwm_green, pwm_blue : std_logic;
-- Debounced button signals
signal btnl, btnc, btnr, btnd : std_logic;
-- Signals that turn off LD16 and/or LD17
signal fLed2Off, fLed1Off : std_logic;
-- State machine states definition
type state_type is (stIdle, -- Both Leds are on, show sweeping color
stRed, -- Show Red color only
stGreen, -- Show Green color only
stBlue, -- Show Blue color only
stLed2Off, -- Turn off Ld17
stLed1Off, -- Turn off Ld16
stLed12Off -- Turn off both Leds
);
-- State machine signal definitions
signal state, nState : state_type;
begin
-- Assign outputs
pwm1_red_o <= pwm_red when fLed1Off = '0' else '0';
pwm1_green_o <= pwm_green when fLed1Off = '0' else '0';
pwm1_blue_o <= pwm_blue when fLed1Off = '0' else '0';
pwm2_red_o <= pwm_red when fLed2Off = '0' else '0';
pwm2_green_o <= pwm_green when fLed2Off = '0' else '0';
pwm2_blue_o <= pwm_blue when fLed2Off = '0' else '0';
RegisterOutputs: process(clk_i, red, green, blue)
begin
if rising_edge(clk_i) then
RED_OUT <= red;
GREEN_OUT <= green;
BLUE_OUT <= blue;
end if;
end process RegisterOutputs;
-- PWM generators:
PwmRed: Pwm
port map(
clk_i => clk_i,
data_i => red,
pwm_o => pwm_red);
PwmGreen: Pwm
port map(
clk_i => clk_i,
data_i => green,
pwm_o => pwm_green);
PwmBlue: Pwm
port map(
clk_i => clk_i,
data_i => blue,
pwm_o => pwm_blue);
-- Button Debouncers:
Btn1: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btnl_i,
pls_o => btnl);
Btn2: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btnc_i,
pls_o => btnc);
Btn3: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btnr_i,
pls_o => btnr);
Btn4: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btnd_i,
pls_o => btnd);
-- State machine registerred process
SYNC_PROC: process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
state <= stIdle;
else
state <= nState;
end if;
end if;
end process;
-- Next State decode process
NEXT_STATE_DECODE: process(state, btnl, btnc, btnr, btnd)
begin
nState <= state; -- Default: Stay in the current state
case state is
when stIdle => -- show sweeping color
if btnl = '1' then
nState <= stRed;
elsif btnc = '1' then
nState <= stGreen;
elsif btnr = '1' then
nState <= stBlue;
elsif btnd = '1' then
nState <= stLed2Off;
end if;
when stRed => -- show red only
if btnc = '1' then
nState <= stGreen;
elsif btnr = '1' then
nState <= stBlue;
elsif btnd = '1' then
nState <= stIdle;
end if;
when stGreen => -- show green only
if btnl = '1' then
nState <= stRed;
elsif btnr = '1' then
nState <= stBlue;
elsif btnd = '1' then
nState <= stIdle;
end if;
when stBlue => -- show blue only
if btnl = '1' then
nState <= stRed;
elsif btnc = '1' then
nState <= stGreen;
elsif btnd = '1' then
nState <= stIdle;
end if;
when stLed2Off => -- turn off Ld17
if btnd = '1' then
nState <= stLed1Off;
end if;
when stLed1Off => -- turn off Ld16
if btnd = '1' then
nState <= stLed12Off;
end if;
when stLed12Off => -- turn off both Ld16 and Ld17
if btnd = '1' then
nState <= stIdle;
end if;
when others => nState <= stIdle;
end case;
end process;
-- clock prescaler
Prescaller: process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
clkCnt <= 0;
elsif clkCnt = CLK_DIV-1 then
clkCnt <= 0;
else
clkCnt <= clkCnt + 1;
end if;
end if;
end process Prescaller;
slowClk <= '1' when clkCnt = CLK_DIV-1 else '0';
process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
colorCnt <= b"0000011111";
specCnt <= 0;
elsif slowClk = '1' then
if colorCnt = b"1111000001" then -- at the end of the color sweeping,
colorCnt <= b"0000011111"; -- start over and change the colors which are swept
if specCnt = 2 then
specCnt <= 0;
else
specCnt <= specCnt + 1;
end if;
else -- colorCnt (9 downto 5) will be increasing
-- and colorCnt(4 downto 0) will be decreasing
colorCnt <= colorCnt + b"0000011111";
end if;
end if;
end if;
end process;
process(state, colorCnt, specCnt, btnl, btnc, btnr)
begin
if state = stRed then
red <= b"000" & b"11111";
green <= b"0000" & b"0000";
blue <= b"0000" & b"0000";
elsif state = stGreen then
red <= b"0000" & b"0000";
green <= b"000" & b"11111";
blue <= b"0000" & b"0000";
elsif state = stBlue then
red <= b"0000" & b"0000";
green <= b"0000" & b"0000";
blue <= b"000" & b"11111";
else
case specCnt is
when 0 =>
red <= b"000" & colorCnt(4 downto 0); -- Decrease Red, increase Green
green <= b"000" & colorCnt(9 downto 5);
blue <= b"0000" & b"0000";
when 1 =>
red <= b"0000" & b"0000";
green <= b"000" & colorCnt(4 downto 0); -- Decrease Green, increase Blue
blue <= b"000" & colorCnt(9 downto 5);
when 2 =>
red <= b"000" & colorCnt(9 downto 5); -- Decrease Blue, increase Red
green <= b"0000" & b"0000";
blue <= b"000" & colorCnt(4 downto 0);
when others =>
red <= b"0000" & b"0000";
green <= b"0000" & b"0000";
blue <= b"0000" & b"0000";
end case;
end if;
if state = stLed2Off then
fLed2Off <= '1';
fLed1Off <= '0';
elsif state = stLed1Off then
fLed2Off <= '0';
fLed1Off <= '1';
elsif state = stLed12Off then
fLed2Off <= '1';
fLed1Off <= '1';
else
fLed2Off <= '0';
fLed1Off <= '0';
end if;
end process;
end Behavioral;
|
gpl-3.0
|
b3fa448a63d2560d515f98fb7a5bae4d
| 0.499518 | 3.908029 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/irq_gen_v1_1/f141c1dc/hdl/vhdl/address_decoder.vhd
| 2 | 21,990 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v1.01.a
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library my_ipif;
use my_ipif.proc_common_pkg.clog2;
use my_ipif.ipif_pkg.SLV64_ARRAY_TYPE;
use my_ipif.ipif_pkg.INTEGER_ARRAY_TYPE;
use my_ipif.ipif_pkg.calc_num_ce;
use my_ipif.ipif_pkg.calc_start_ce_index;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity work.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity work.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
gpl-2.0
|
c422742d9d4b04b084d8e3421c6d3ec0
| 0.459254 | 4.464975 | false | false | false | false |
luebbers/reconos
|
demos/sort_demo_thermal/hw/src/bubble_sorter_tb.vhd
| 2 | 5,451 |
--
-- bubble_sorter_tb.vhd
-- Simulation testbench for bubble_sorter.vhd
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all; -- for UNIFORM, TRUNC
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bubble_sorter_tb is
generic (
G_MAX_SIMULATION_RUNS : integer := 1;
G_LEN : integer := 2048;
G_AWIDTH : integer := 11;
G_DWIDTH : integer := 32
);
end bubble_sorter_tb;
architecture testbench of bubble_sorter_tb is
component burst_ram
port (
addra : in std_logic_vector(10 downto 0);
addrb : in std_logic_vector(9 downto 0);
clka : in std_logic;
clkb : in std_logic;
dina : in std_logic_vector(31 downto 0);
dinb : in std_logic_vector(63 downto 0);
douta : out std_logic_vector(31 downto 0);
doutb : out std_logic_vector(63 downto 0);
wea : in std_logic;
web : in std_logic
);
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
-- as seen from RAM perspective
signal addr_ram : std_logic_vector(0 to G_AWIDTH-1);
signal datain_ram : std_logic_vector(0 to G_DWIDTH-1);
signal dataout_ram : std_logic_vector(0 to G_DWIDTH-1);
signal we_ram : std_logic;
signal addr_stim : std_logic_vector(0 to G_AWIDTH-1);
signal datain_stim : std_logic_vector(0 to G_DWIDTH-1);
signal dataout_stim : std_logic_vector(0 to G_DWIDTH-1);
signal we_stim : std_logic;
signal addr_sort : std_logic_vector(0 to G_AWIDTH-1);
signal datain_sort : std_logic_vector(0 to G_DWIDTH-1);
signal dataout_sort : std_logic_vector(0 to G_DWIDTH-1);
signal we_sort : std_logic;
signal start : std_logic := '0';
signal done : std_logic := '0';
signal sel : std_logic;
begin
burst_ram_i : burst_ram
port map (
addrb => (others => '0'),
addra => addr_ram,
clkb => '0',
clka => clk,
dinb => (others => '0'),
dina => datain_ram,
doutb => open,
douta => dataout_ram,
web => '0',
wea => we_ram
);
sorter : entity work.bubble_sorter
generic map (
G_LEN => G_LEN,
G_AWIDTH => G_AWIDTH,
G_DWIDTH => G_DWIDTH
)
port map (
clk => clk,
reset => reset,
o_RAMAddr => addr_sort,
o_RAMData => datain_sort,
i_RAMData => dataout_sort,
o_RAMWE => we_sort,
start => start,
done => done
);
addr_ram <= addr_stim when sel = '0' else addr_sort;
datain_ram <= datain_stim when sel = '0' else datain_sort;
we_ram <= we_stim when sel <= '0' else we_sort;
dataout_stim <= dataout_ram;
dataout_sort <= dataout_ram;
-- generate clock
process
begin
clk <= not clk;
wait for 5 ns;
end process;
-- generate reset
reset <= '1', '0' after 55 ns;
-- init RAM with a few values
process
-- Seed values for random generator
variable seed1, seed2 : positive;
-- Random real-number value in range 0 to 1.0
variable rand : real;
-- Random integer value in range 0..2^32-1
variable int_rand : integer;
variable addr : std_logic_vector(0 to G_AWIDTH-1);
variable data : std_logic_vector(0 to G_DWIDTH-1);
variable a : std_logic_vector(0 to G_DWIDTH-1);
variable b : std_logic_vector(0 to G_DWIDTH-1);
variable simulation_runs : natural := 0;
begin
sel <= '0';
start <= '0';
addr := (others => '1');
data := std_logic_vector(to_unsigned(G_LEN, data'length));
wait for 101 ns;
assert false report "*** New simulation run. Generating random data. ***" severity note;
for i in 0 to G_LEN-1 loop
UNIFORM(seed1, seed2, rand);
-- get a 32 bit random value
int_rand := integer(TRUNC(rand*100000000.0));
addr := addr + 1;
data := std_logic_vector(to_unsigned(int_rand, data'length));
-- data := data - 1;
datain_stim <= data;
addr_stim <= addr;
we_stim <= '1';
wait for 10 ns;
end loop;
we_stim <= '0';
wait for 50 ns;
assert false report "*** Starting sort process. ***" severity note;
sel <= '1';
start <= '1';
wait for 10 ns;
start <= '0';
wait until done = '1';
wait for 3 ns;
sel <= '0';
addr := (others => '0');
addr_stim <= addr;
wait for 10 ns;
assert false report "*** Verifying sorted data. ***" severity note;
-- verify
for i in 0 to G_LEN-2 loop
a := dataout_stim;
addr := addr + 1;
addr_stim <= addr;
wait for 10 ns;
b := dataout_stim;
assert a <= b report "Data sort check FAILED!" severity note;
end loop;
simulation_runs := simulation_runs + 1;
assert simulation_runs < G_MAX_SIMULATION_RUNS report "*** Simulation finished. This is not an error. ***" severity failure;
end process;
end testbench;
|
gpl-3.0
|
9bdee5557f488cbc17c60044ca9ff338
| 0.581178 | 3.439117 | false | false | false | false |
luebbers/reconos
|
tools/fsmLanguage/fpga_scripts/pr_scripts/top.vhd
| 1 | 139,858 |
-----------------------------------------------------
--
-- Reconfigurable PLB Peripheral Demo
--
--
-- Tobias Becker
--
-- Imperial College London
--
-- 25 Aug 2006
--
-----------------------------------------------------
--
-- This file is modified version of the auto-generated
-- system.vhd file.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top is
port (
fpga_0_RS232_Uart_1_RX_pin : in std_logic;
fpga_0_RS232_Uart_1_TX_pin : out std_logic;
fpga_0_SysACE_CompactFlash_SysACE_CLK_pin : in std_logic;
fpga_0_SysACE_CompactFlash_SysACE_MPA_pin : out std_logic_vector(6 downto 0);
fpga_0_SysACE_CompactFlash_SysACE_MPD_pin : inout std_logic_vector(15 downto 0);
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin : out std_logic;
fpga_0_SysACE_CompactFlash_SysACE_OEN_pin : out std_logic;
fpga_0_SysACE_CompactFlash_SysACE_WEN_pin : out std_logic;
fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin : in std_logic;
fpga_0_LEDs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
fpga_0_PushButtons_5Bit_GPIO_IO_pin : inout std_logic_vector(0 to 4);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin : out std_logic_vector(0 to 2);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin : out std_logic_vector(0 to 2);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin : out std_logic_vector(0 to 12);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin : out std_logic_vector(0 to 1);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin : out std_logic;
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin : out std_logic;
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin : out std_logic;
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin : out std_logic_vector(0 to 7);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin : inout std_logic_vector(0 to 7);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin : inout std_logic_vector(0 to 63);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin : out std_logic_vector(0 to 1);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin : out std_logic_vector(0 to 1);
fpga_0_net_gnd_pin : out std_logic;
fpga_0_net_gnd_1_pin : out std_logic;
fpga_0_net_gnd_2_pin : out std_logic;
fpga_0_net_gnd_3_pin : out std_logic;
fpga_0_net_gnd_4_pin : out std_logic;
fpga_0_net_gnd_5_pin : out std_logic;
fpga_0_net_gnd_6_pin : out std_logic;
fpga_0_DDR_CLK_FB : in std_logic;
fpga_0_DDR_CLK_FB_OUT : out std_logic;
sys_clk_pin : in std_logic;
sys_rst_pin : in std_logic
);
end top;
architecture STRUCTURE of top is
attribute box_type : STRING;
component ppc405_0_wrapper is
port (
C405CPMCORESLEEPREQ : out std_logic;
C405CPMMSRCE : out std_logic;
C405CPMMSREE : out std_logic;
C405CPMTIMERIRQ : out std_logic;
C405CPMTIMERRESETREQ : out std_logic;
C405XXXMACHINECHECK : out std_logic;
CPMC405CLOCK : in std_logic;
CPMC405CORECLKINACTIVE : in std_logic;
CPMC405CPUCLKEN : in std_logic;
CPMC405JTAGCLKEN : in std_logic;
CPMC405TIMERCLKEN : in std_logic;
CPMC405TIMERTICK : in std_logic;
MCBCPUCLKEN : in std_logic;
MCBTIMEREN : in std_logic;
MCPPCRST : in std_logic;
PLBCLK : in std_logic;
DCRCLK : in std_logic;
C405RSTCHIPRESETREQ : out std_logic;
C405RSTCORERESETREQ : out std_logic;
C405RSTSYSRESETREQ : out std_logic;
RSTC405RESETCHIP : in std_logic;
RSTC405RESETCORE : in std_logic;
RSTC405RESETSYS : in std_logic;
C405PLBICUABUS : out std_logic_vector(0 to 31);
C405PLBICUBE : out std_logic_vector(0 to 7);
C405PLBICURNW : out std_logic;
C405PLBICUABORT : out std_logic;
C405PLBICUBUSLOCK : out std_logic;
C405PLBICUU0ATTR : out std_logic;
C405PLBICUGUARDED : out std_logic;
C405PLBICULOCKERR : out std_logic;
C405PLBICUMSIZE : out std_logic_vector(0 to 1);
C405PLBICUORDERED : out std_logic;
C405PLBICUPRIORITY : out std_logic_vector(0 to 1);
C405PLBICURDBURST : out std_logic;
C405PLBICUREQUEST : out std_logic;
C405PLBICUSIZE : out std_logic_vector(0 to 3);
C405PLBICUTYPE : out std_logic_vector(0 to 2);
C405PLBICUWRBURST : out std_logic;
C405PLBICUWRDBUS : out std_logic_vector(0 to 63);
C405PLBICUCACHEABLE : out std_logic;
PLBC405ICUADDRACK : in std_logic;
PLBC405ICUBUSY : in std_logic;
PLBC405ICUERR : in std_logic;
PLBC405ICURDBTERM : in std_logic;
PLBC405ICURDDACK : in std_logic;
PLBC405ICURDDBUS : in std_logic_vector(0 to 63);
PLBC405ICURDWDADDR : in std_logic_vector(0 to 3);
PLBC405ICUREARBITRATE : in std_logic;
PLBC405ICUWRBTERM : in std_logic;
PLBC405ICUWRDACK : in std_logic;
PLBC405ICUSSIZE : in std_logic_vector(0 to 1);
PLBC405ICUSERR : in std_logic;
PLBC405ICUSBUSYS : in std_logic;
C405PLBDCUABUS : out std_logic_vector(0 to 31);
C405PLBDCUBE : out std_logic_vector(0 to 7);
C405PLBDCURNW : out std_logic;
C405PLBDCUABORT : out std_logic;
C405PLBDCUBUSLOCK : out std_logic;
C405PLBDCUU0ATTR : out std_logic;
C405PLBDCUGUARDED : out std_logic;
C405PLBDCULOCKERR : out std_logic;
C405PLBDCUMSIZE : out std_logic_vector(0 to 1);
C405PLBDCUORDERED : out std_logic;
C405PLBDCUPRIORITY : out std_logic_vector(0 to 1);
C405PLBDCURDBURST : out std_logic;
C405PLBDCUREQUEST : out std_logic;
C405PLBDCUSIZE : out std_logic_vector(0 to 3);
C405PLBDCUTYPE : out std_logic_vector(0 to 2);
C405PLBDCUWRBURST : out std_logic;
C405PLBDCUWRDBUS : out std_logic_vector(0 to 63);
C405PLBDCUCACHEABLE : out std_logic;
C405PLBDCUWRITETHRU : out std_logic;
PLBC405DCUADDRACK : in std_logic;
PLBC405DCUBUSY : in std_logic;
PLBC405DCUERR : in std_logic;
PLBC405DCURDBTERM : in std_logic;
PLBC405DCURDDACK : in std_logic;
PLBC405DCURDDBUS : in std_logic_vector(0 to 63);
PLBC405DCURDWDADDR : in std_logic_vector(0 to 3);
PLBC405DCUREARBITRATE : in std_logic;
PLBC405DCUWRBTERM : in std_logic;
PLBC405DCUWRDACK : in std_logic;
PLBC405DCUSSIZE : in std_logic_vector(0 to 1);
PLBC405DCUSERR : in std_logic;
PLBC405DCUSBUSYS : in std_logic;
BRAMDSOCMCLK : in std_logic;
BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31);
DSARCVALUE : in std_logic_vector(0 to 7);
DSCNTLVALUE : in std_logic_vector(0 to 7);
DSOCMBRAMABUS : out std_logic_vector(8 to 29);
DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3);
DSOCMBRAMEN : out std_logic;
DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
DSOCMBUSY : out std_logic;
BRAMISOCMCLK : in std_logic;
BRAMISOCMRDDBUS : in std_logic_vector(0 to 63);
ISARCVALUE : in std_logic_vector(0 to 7);
ISCNTLVALUE : in std_logic_vector(0 to 7);
ISOCMBRAMEN : out std_logic;
ISOCMBRAMEVENWRITEEN : out std_logic;
ISOCMBRAMODDWRITEEN : out std_logic;
ISOCMBRAMRDABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
C405DCRABUS : out std_logic_vector(0 to 9);
C405DCRDBUSOUT : out std_logic_vector(0 to 31);
C405DCRREAD : out std_logic;
C405DCRWRITE : out std_logic;
DCRC405ACK : in std_logic;
DCRC405DBUSIN : in std_logic_vector(0 to 31);
EICC405CRITINPUTIRQ : in std_logic;
EICC405EXTINPUTIRQ : in std_logic;
C405JTGCAPTUREDR : out std_logic;
C405JTGEXTEST : out std_logic;
C405JTGPGMOUT : out std_logic;
C405JTGSHIFTDR : out std_logic;
C405JTGTDO : out std_logic;
C405JTGTDOEN : out std_logic;
C405JTGUPDATEDR : out std_logic;
MCBJTAGEN : in std_logic;
JTGC405BNDSCANTDO : in std_logic;
JTGC405TCK : in std_logic;
JTGC405TDI : in std_logic;
JTGC405TMS : in std_logic;
JTGC405TRSTNEG : in std_logic;
C405DBGMSRWE : out std_logic;
C405DBGSTOPACK : out std_logic;
C405DBGWBCOMPLETE : out std_logic;
C405DBGWBFULL : out std_logic;
C405DBGWBIAR : out std_logic_vector(0 to 29);
DBGC405DEBUGHALT : in std_logic;
DBGC405EXTBUSHOLDACK : in std_logic;
DBGC405UNCONDDEBUGEVENT : in std_logic;
C405TRCCYCLE : out std_logic;
C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1);
C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 to 1);
C405TRCTRACESTATUS : out std_logic_vector(0 to 3);
C405TRCTRIGGEREVENTOUT : out std_logic;
C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 10);
TRCC405TRACEDISABLE : in std_logic;
TRCC405TRIGGEREVENTIN : in std_logic
);
end component;
attribute box_type of ppc405_0_wrapper: component is "black_box";
component ppc405_1_wrapper is
port (
C405CPMCORESLEEPREQ : out std_logic;
C405CPMMSRCE : out std_logic;
C405CPMMSREE : out std_logic;
C405CPMTIMERIRQ : out std_logic;
C405CPMTIMERRESETREQ : out std_logic;
C405XXXMACHINECHECK : out std_logic;
CPMC405CLOCK : in std_logic;
CPMC405CORECLKINACTIVE : in std_logic;
CPMC405CPUCLKEN : in std_logic;
CPMC405JTAGCLKEN : in std_logic;
CPMC405TIMERCLKEN : in std_logic;
CPMC405TIMERTICK : in std_logic;
MCBCPUCLKEN : in std_logic;
MCBTIMEREN : in std_logic;
MCPPCRST : in std_logic;
PLBCLK : in std_logic;
DCRCLK : in std_logic;
C405RSTCHIPRESETREQ : out std_logic;
C405RSTCORERESETREQ : out std_logic;
C405RSTSYSRESETREQ : out std_logic;
RSTC405RESETCHIP : in std_logic;
RSTC405RESETCORE : in std_logic;
RSTC405RESETSYS : in std_logic;
C405PLBICUABUS : out std_logic_vector(0 to 31);
C405PLBICUBE : out std_logic_vector(0 to 7);
C405PLBICURNW : out std_logic;
C405PLBICUABORT : out std_logic;
C405PLBICUBUSLOCK : out std_logic;
C405PLBICUU0ATTR : out std_logic;
C405PLBICUGUARDED : out std_logic;
C405PLBICULOCKERR : out std_logic;
C405PLBICUMSIZE : out std_logic_vector(0 to 1);
C405PLBICUORDERED : out std_logic;
C405PLBICUPRIORITY : out std_logic_vector(0 to 1);
C405PLBICURDBURST : out std_logic;
C405PLBICUREQUEST : out std_logic;
C405PLBICUSIZE : out std_logic_vector(0 to 3);
C405PLBICUTYPE : out std_logic_vector(0 to 2);
C405PLBICUWRBURST : out std_logic;
C405PLBICUWRDBUS : out std_logic_vector(0 to 63);
C405PLBICUCACHEABLE : out std_logic;
PLBC405ICUADDRACK : in std_logic;
PLBC405ICUBUSY : in std_logic;
PLBC405ICUERR : in std_logic;
PLBC405ICURDBTERM : in std_logic;
PLBC405ICURDDACK : in std_logic;
PLBC405ICURDDBUS : in std_logic_vector(0 to 63);
PLBC405ICURDWDADDR : in std_logic_vector(0 to 3);
PLBC405ICUREARBITRATE : in std_logic;
PLBC405ICUWRBTERM : in std_logic;
PLBC405ICUWRDACK : in std_logic;
PLBC405ICUSSIZE : in std_logic_vector(0 to 1);
PLBC405ICUSERR : in std_logic;
PLBC405ICUSBUSYS : in std_logic;
C405PLBDCUABUS : out std_logic_vector(0 to 31);
C405PLBDCUBE : out std_logic_vector(0 to 7);
C405PLBDCURNW : out std_logic;
C405PLBDCUABORT : out std_logic;
C405PLBDCUBUSLOCK : out std_logic;
C405PLBDCUU0ATTR : out std_logic;
C405PLBDCUGUARDED : out std_logic;
C405PLBDCULOCKERR : out std_logic;
C405PLBDCUMSIZE : out std_logic_vector(0 to 1);
C405PLBDCUORDERED : out std_logic;
C405PLBDCUPRIORITY : out std_logic_vector(0 to 1);
C405PLBDCURDBURST : out std_logic;
C405PLBDCUREQUEST : out std_logic;
C405PLBDCUSIZE : out std_logic_vector(0 to 3);
C405PLBDCUTYPE : out std_logic_vector(0 to 2);
C405PLBDCUWRBURST : out std_logic;
C405PLBDCUWRDBUS : out std_logic_vector(0 to 63);
C405PLBDCUCACHEABLE : out std_logic;
C405PLBDCUWRITETHRU : out std_logic;
PLBC405DCUADDRACK : in std_logic;
PLBC405DCUBUSY : in std_logic;
PLBC405DCUERR : in std_logic;
PLBC405DCURDBTERM : in std_logic;
PLBC405DCURDDACK : in std_logic;
PLBC405DCURDDBUS : in std_logic_vector(0 to 63);
PLBC405DCURDWDADDR : in std_logic_vector(0 to 3);
PLBC405DCUREARBITRATE : in std_logic;
PLBC405DCUWRBTERM : in std_logic;
PLBC405DCUWRDACK : in std_logic;
PLBC405DCUSSIZE : in std_logic_vector(0 to 1);
PLBC405DCUSERR : in std_logic;
PLBC405DCUSBUSYS : in std_logic;
BRAMDSOCMCLK : in std_logic;
BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31);
DSARCVALUE : in std_logic_vector(0 to 7);
DSCNTLVALUE : in std_logic_vector(0 to 7);
DSOCMBRAMABUS : out std_logic_vector(8 to 29);
DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3);
DSOCMBRAMEN : out std_logic;
DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
DSOCMBUSY : out std_logic;
BRAMISOCMCLK : in std_logic;
BRAMISOCMRDDBUS : in std_logic_vector(0 to 63);
ISARCVALUE : in std_logic_vector(0 to 7);
ISCNTLVALUE : in std_logic_vector(0 to 7);
ISOCMBRAMEN : out std_logic;
ISOCMBRAMEVENWRITEEN : out std_logic;
ISOCMBRAMODDWRITEEN : out std_logic;
ISOCMBRAMRDABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
C405DCRABUS : out std_logic_vector(0 to 9);
C405DCRDBUSOUT : out std_logic_vector(0 to 31);
C405DCRREAD : out std_logic;
C405DCRWRITE : out std_logic;
DCRC405ACK : in std_logic;
DCRC405DBUSIN : in std_logic_vector(0 to 31);
EICC405CRITINPUTIRQ : in std_logic;
EICC405EXTINPUTIRQ : in std_logic;
C405JTGCAPTUREDR : out std_logic;
C405JTGEXTEST : out std_logic;
C405JTGPGMOUT : out std_logic;
C405JTGSHIFTDR : out std_logic;
C405JTGTDO : out std_logic;
C405JTGTDOEN : out std_logic;
C405JTGUPDATEDR : out std_logic;
MCBJTAGEN : in std_logic;
JTGC405BNDSCANTDO : in std_logic;
JTGC405TCK : in std_logic;
JTGC405TDI : in std_logic;
JTGC405TMS : in std_logic;
JTGC405TRSTNEG : in std_logic;
C405DBGMSRWE : out std_logic;
C405DBGSTOPACK : out std_logic;
C405DBGWBCOMPLETE : out std_logic;
C405DBGWBFULL : out std_logic;
C405DBGWBIAR : out std_logic_vector(0 to 29);
DBGC405DEBUGHALT : in std_logic;
DBGC405EXTBUSHOLDACK : in std_logic;
DBGC405UNCONDDEBUGEVENT : in std_logic;
C405TRCCYCLE : out std_logic;
C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1);
C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 to 1);
C405TRCTRACESTATUS : out std_logic_vector(0 to 3);
C405TRCTRIGGEREVENTOUT : out std_logic;
C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 10);
TRCC405TRACEDISABLE : in std_logic;
TRCC405TRIGGEREVENTIN : in std_logic
);
end component;
attribute box_type of ppc405_1_wrapper: component is "black_box";
component jtagppc_0_wrapper is
port (
TRSTNEG : in std_logic;
HALTNEG0 : in std_logic;
DBGC405DEBUGHALT0 : out std_logic;
HALTNEG1 : in std_logic;
DBGC405DEBUGHALT1 : out std_logic;
C405JTGTDO0 : in std_logic;
C405JTGTDOEN0 : in std_logic;
JTGC405TCK0 : out std_logic;
JTGC405TDI0 : out std_logic;
JTGC405TMS0 : out std_logic;
JTGC405TRSTNEG0 : out std_logic;
C405JTGTDO1 : in std_logic;
C405JTGTDOEN1 : in std_logic;
JTGC405TCK1 : out std_logic;
JTGC405TDI1 : out std_logic;
JTGC405TMS1 : out std_logic;
JTGC405TRSTNEG1 : out std_logic
);
end component;
attribute box_type of jtagppc_0_wrapper: component is "black_box";
component reset_block_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
Core_Reset_Req : in std_logic;
Chip_Reset_Req : in std_logic;
System_Reset_Req : in std_logic;
Dcm_locked : in std_logic;
Rstc405resetcore : out std_logic;
Rstc405resetchip : out std_logic;
Rstc405resetsys : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0)
);
end component;
attribute box_type of reset_block_wrapper: component is "black_box";
component plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_compress : in std_logic_vector(0 to 1);
M_guarded : in std_logic_vector(0 to 1);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_ordered : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 3);
Sl_MErr : in std_logic_vector(0 to 7);
Sl_MBusy : in std_logic_vector(0 to 7);
Sl_rdBTerm : in std_logic_vector(0 to 3);
Sl_rdComp : in std_logic_vector(0 to 3);
Sl_rdDAck : in std_logic_vector(0 to 3);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 15);
Sl_rearbitrate : in std_logic_vector(0 to 3);
Sl_SSize : in std_logic_vector(0 to 7);
Sl_wait : in std_logic_vector(0 to 3);
Sl_wrBTerm : in std_logic_vector(0 to 3);
Sl_wrComp : in std_logic_vector(0 to 3);
Sl_wrDAck : in std_logic_vector(0 to 3);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_compress : out std_logic;
PLB_guarded : out std_logic;
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_ordered : out std_logic;
PLB_pendPri : out std_logic_vector(0 to 1);
PLB_pendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic;
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic;
PLB_SaddrAck : out std_logic;
PLB_SMErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 3);
ArbAddrVldReg : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
attribute box_type of plb_wrapper: component is "black_box";
component opb_wrapper is
port (
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
M_beXfer : in std_logic_vector(0 to 0);
M_busLock : in std_logic_vector(0 to 0);
M_DBus : in std_logic_vector(0 to 31);
M_DBusEn : in std_logic_vector(0 to 0);
M_DBusEn32_63 : in std_logic_vector(0 to 0);
M_dwXfer : in std_logic_vector(0 to 0);
M_fwXfer : in std_logic_vector(0 to 0);
M_hwXfer : in std_logic_vector(0 to 0);
M_request : in std_logic_vector(0 to 0);
M_RNW : in std_logic_vector(0 to 0);
M_select : in std_logic_vector(0 to 0);
M_seqAddr : in std_logic_vector(0 to 0);
Sl_beAck : in std_logic_vector(0 to 5);
Sl_DBus : in std_logic_vector(0 to 191);
Sl_DBusEn : in std_logic_vector(0 to 5);
Sl_DBusEn32_63 : in std_logic_vector(0 to 5);
Sl_errAck : in std_logic_vector(0 to 5);
Sl_dwAck : in std_logic_vector(0 to 5);
Sl_fwAck : in std_logic_vector(0 to 5);
Sl_hwAck : in std_logic_vector(0 to 5);
Sl_retry : in std_logic_vector(0 to 5);
Sl_toutSup : in std_logic_vector(0 to 5);
Sl_xferAck : in std_logic_vector(0 to 5);
OPB_MRequest : out std_logic_vector(0 to 0);
OPB_ABus : out std_logic_vector(0 to 31);
OPB_BE : out std_logic_vector(0 to 3);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to 31);
OPB_wrDBus : out std_logic_vector(0 to 31);
OPB_DBus : out std_logic_vector(0 to 31);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to 0);
OPB_pendReq : out std_logic_vector(0 to 0);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end component;
attribute box_type of opb_wrapper: component is "black_box";
component plb2opb_wrapper is
port (
PLB_Clk : in std_logic;
OPB_Clk : in std_logic;
PLB_Rst : in std_logic;
OPB_Rst : in std_logic;
Bus_Error_Det : out std_logic;
BGI_Trans_Abort : out std_logic;
BGO_dcrAck : out std_logic;
BGO_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
BGO_addrAck : out std_logic;
BGO_MErr : out std_logic_vector(0 to 1);
BGO_MBusy : out std_logic_vector(0 to 1);
BGO_rdBTerm : out std_logic;
BGO_rdComp : out std_logic;
BGO_rdDAck : out std_logic;
BGO_rdDBus : out std_logic_vector(0 to 63);
BGO_rdWdAddr : out std_logic_vector(0 to 3);
BGO_rearbitrate : out std_logic;
BGO_SSize : out std_logic_vector(0 to 1);
BGO_wait : out std_logic;
BGO_wrBTerm : out std_logic;
BGO_wrComp : out std_logic;
BGO_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to 7);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrPrim : in std_logic;
PLB2OPB_rearb : out std_logic;
BGO_ABus : out std_logic_vector(0 to 31);
BGO_BE : out std_logic_vector(0 to 3);
BGO_busLock : out std_logic;
BGO_DBus : out std_logic_vector(0 to 31);
BGO_request : out std_logic;
BGO_RNW : out std_logic;
BGO_select : out std_logic;
BGO_seqAddr : out std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
OPB_errAck : in std_logic;
OPB_MnGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
);
end component;
attribute box_type of plb2opb_wrapper: component is "black_box";
component rs232_uart_1_wrapper is
port (
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Interrupt : out std_logic;
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
UART_DBus : out std_logic_vector(0 to 31);
UART_errAck : out std_logic;
UART_retry : out std_logic;
UART_toutSup : out std_logic;
UART_xferAck : out std_logic;
RX : in std_logic;
TX : out std_logic
);
end component;
attribute box_type of rs232_uart_1_wrapper: component is "black_box";
component sysace_compactflash_wrapper is
port (
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
OPB_ABus : in std_logic_vector(0 to 31);
OPB_DBus : in std_logic_vector(0 to 31);
Sln_DBus : out std_logic_vector(0 to 31);
OPB_select : in std_logic;
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
OPB_BE : in std_logic_vector(0 to 3);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_toutSup : out std_logic;
Sln_retry : out std_logic;
SysACE_MPA : out std_logic_vector(6 downto 0);
SysACE_CLK : in std_logic;
SysACE_MPIRQ : in std_logic;
SysACE_MPD_I : in std_logic_vector(15 downto 0);
SysACE_MPD_O : out std_logic_vector(15 downto 0);
SysACE_MPD_T : out std_logic_vector(15 downto 0);
SysACE_CEN : out std_logic;
SysACE_OEN : out std_logic;
SysACE_WEN : out std_logic;
SysACE_IRQ : out std_logic
);
end component;
attribute box_type of sysace_compactflash_wrapper: component is "black_box";
component leds_4bit_wrapper is
port (
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to 31);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_in : in std_logic_vector(0 to 3);
GPIO_d_out : out std_logic_vector(0 to 3);
GPIO_t_out : out std_logic_vector(0 to 3);
GPIO2_in : in std_logic_vector(0 to 3);
GPIO2_d_out : out std_logic_vector(0 to 3);
GPIO2_t_out : out std_logic_vector(0 to 3);
GPIO_IO_I : in std_logic_vector(0 to 3);
GPIO_IO_O : out std_logic_vector(0 to 3);
GPIO_IO_T : out std_logic_vector(0 to 3);
GPIO2_IO_I : in std_logic_vector(0 to 3);
GPIO2_IO_O : out std_logic_vector(0 to 3);
GPIO2_IO_T : out std_logic_vector(0 to 3)
);
end component;
attribute box_type of leds_4bit_wrapper: component is "black_box";
component pushbuttons_5bit_wrapper is
port (
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to 31);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_in : in std_logic_vector(0 to 4);
GPIO_d_out : out std_logic_vector(0 to 4);
GPIO_t_out : out std_logic_vector(0 to 4);
GPIO2_in : in std_logic_vector(0 to 4);
GPIO2_d_out : out std_logic_vector(0 to 4);
GPIO2_t_out : out std_logic_vector(0 to 4);
GPIO_IO_I : in std_logic_vector(0 to 4);
GPIO_IO_O : out std_logic_vector(0 to 4);
GPIO_IO_T : out std_logic_vector(0 to 4);
GPIO2_IO_I : in std_logic_vector(0 to 4);
GPIO2_IO_O : out std_logic_vector(0 to 4);
GPIO2_IO_T : out std_logic_vector(0 to 4)
);
end component;
attribute box_type of pushbuttons_5bit_wrapper: component is "black_box";
component ddr_512mb_64mx64_rank2_row13_col10_cl2_5_wrapper is
port (
PLB_Clk : in std_logic;
PLB_Clk_n : in std_logic;
Clk90_in : in std_logic;
Clk90_in_n : in std_logic;
DDR_Clk90_in : in std_logic;
DDR_Clk90_in_n : in std_logic;
PLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1);
IP2INTC_Irpt : out std_logic;
DDR_Clk : out std_logic_vector(0 to 3);
DDR_Clkn : out std_logic_vector(0 to 3);
DDR_CKE : out std_logic_vector(0 to 1);
DDR_CSn : out std_logic_vector(0 to 1);
DDR_RASn : out std_logic;
DDR_CASn : out std_logic;
DDR_WEn : out std_logic;
DDR_DM : out std_logic_vector(0 to 7);
DDR_BankAddr : out std_logic_vector(0 to 1);
DDR_Addr : out std_logic_vector(0 to 12);
DDR_DM_ECC : out std_logic;
DDR_Init_done : out std_logic;
DDR_DQ_I : in std_logic_vector(0 to 63);
DDR_DQ_O : out std_logic_vector(0 to 63);
DDR_DQ_T : out std_logic_vector(0 to 63);
DDR_DQS_I : in std_logic_vector(0 to 7);
DDR_DQS_O : out std_logic_vector(0 to 7);
DDR_DQS_T : out std_logic_vector(0 to 7);
DDR_DQ_ECC_I : in std_logic_vector(0 to 6);
DDR_DQ_ECC_O : out std_logic_vector(0 to 6);
DDR_DQ_ECC_T : out std_logic_vector(0 to 6);
DDR_DQS_ECC_I : in std_logic;
DDR_DQS_ECC_O : out std_logic;
DDR_DQS_ECC_T : out std_logic
);
end component;
attribute box_type of ddr_512mb_64mx64_rank2_row13_col10_cl2_5_wrapper: component is "black_box";
component plb_bram_if_cntlr_1_wrapper is
port (
plb_clk : in std_logic;
plb_rst : in std_logic;
plb_abort : in std_logic;
plb_abus : in std_logic_vector(0 to 31);
plb_be : in std_logic_vector(0 to 7);
plb_buslock : in std_logic;
plb_compress : in std_logic;
plb_guarded : in std_logic;
plb_lockerr : in std_logic;
plb_masterid : in std_logic_vector(0 to 0);
plb_msize : in std_logic_vector(0 to 1);
plb_ordered : in std_logic;
plb_pavalid : in std_logic;
plb_rnw : in std_logic;
plb_size : in std_logic_vector(0 to 3);
plb_type : in std_logic_vector(0 to 2);
sl_addrack : out std_logic;
sl_mbusy : out std_logic_vector(0 to 1);
sl_merr : out std_logic_vector(0 to 1);
sl_rearbitrate : out std_logic;
sl_ssize : out std_logic_vector(0 to 1);
sl_wait : out std_logic;
plb_rdprim : in std_logic;
plb_savalid : in std_logic;
plb_wrprim : in std_logic;
plb_wrburst : in std_logic;
plb_wrdbus : in std_logic_vector(0 to 63);
sl_wrbterm : out std_logic;
sl_wrcomp : out std_logic;
sl_wrdack : out std_logic;
plb_rdburst : in std_logic;
sl_rdbterm : out std_logic;
sl_rdcomp : out std_logic;
sl_rddack : out std_logic;
sl_rddbus : out std_logic_vector(0 to 63);
sl_rdwdaddr : out std_logic_vector(0 to 3);
plb_pendreq : in std_logic;
plb_pendpri : in std_logic_vector(0 to 1);
plb_reqpri : in std_logic_vector(0 to 1);
bram_rst : out std_logic;
bram_clk : out std_logic;
bram_en : out std_logic;
bram_wen : out std_logic_vector(0 to 7);
bram_addr : out std_logic_vector(0 to 31);
bram_din : in std_logic_vector(0 to 63);
bram_dout : out std_logic_vector(0 to 63)
);
end component;
attribute box_type of plb_bram_if_cntlr_1_wrapper: component is "black_box";
component plb_bram_if_cntlr_1_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 7);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 63);
BRAM_Dout_A : in std_logic_vector(0 to 63);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 7);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 63);
BRAM_Dout_B : in std_logic_vector(0 to 63)
);
end component;
attribute box_type of plb_bram_if_cntlr_1_bram_wrapper: component is "black_box";
component sysclk_inv_wrapper is
port (
Op1 : in std_logic_vector(0 to 0);
Op2 : in std_logic_vector(0 to 0);
Res : out std_logic_vector(0 to 0)
);
end component;
attribute box_type of sysclk_inv_wrapper: component is "black_box";
component clk90_inv_wrapper is
port (
Op1 : in std_logic_vector(0 to 0);
Op2 : in std_logic_vector(0 to 0);
Res : out std_logic_vector(0 to 0)
);
end component;
attribute box_type of clk90_inv_wrapper: component is "black_box";
component ddr_clk90_inv_wrapper is
port (
Op1 : in std_logic_vector(0 to 0);
Op2 : in std_logic_vector(0 to 0);
Res : out std_logic_vector(0 to 0)
);
end component;
attribute box_type of ddr_clk90_inv_wrapper: component is "black_box";
component dcm_0_wrapper is
port (
RST : in std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector(7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic
);
end component;
attribute box_type of dcm_0_wrapper: component is "black_box";
component dcm_1_wrapper is
port (
RST : in std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector(7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic
);
end component;
attribute box_type of dcm_1_wrapper: component is "black_box";
component opb_hwicap_0_wrapper is
port (
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
OPB_ABus : in std_logic_vector(0 to 31);
OPB_DBus : in std_logic_vector(0 to 31);
Sln_DBus : out std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_select : in std_logic;
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_toutSup : out std_logic;
Sln_retry : out std_logic
);
end component;
attribute box_type of opb_hwicap_0_wrapper: component is "black_box";
component opb_gpio_0_wrapper is
port (
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to 31);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_in : in std_logic_vector(0 to 7);
GPIO_d_out : out std_logic_vector(0 to 7);
GPIO_t_out : out std_logic_vector(0 to 7);
GPIO2_in : in std_logic_vector(0 to 7);
GPIO2_d_out : out std_logic_vector(0 to 7);
GPIO2_t_out : out std_logic_vector(0 to 7);
GPIO_IO_I : in std_logic_vector(0 to 7);
GPIO_IO_O : out std_logic_vector(0 to 7);
GPIO_IO_T : out std_logic_vector(0 to 7);
GPIO2_IO_I : in std_logic_vector(0 to 7);
GPIO2_IO_O : out std_logic_vector(0 to 7);
GPIO2_IO_T : out std_logic_vector(0 to 7)
);
end component;
attribute box_type of opb_gpio_0_wrapper: component is "black_box";
component math_0_wrapper is
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to 7);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrPrim : in std_logic
);
end component;
attribute box_type of math_0_wrapper: component is "black_box";
-----------------------------------------------------
-- added busmacro declaration
-----------------------------------------------------
-- For connection from bus to peripheral use async macro.
component busmacro_vector8_xc2vp_l2r_async_narrow is
port (
macro_in : in std_logic_vector(7 downto 0);
macro_out : out std_logic_vector(7 downto 0)
);
end component;
-- For connection from peripheral to bus use async macro with
-- enable. The macro should be disabled during reconfiguration
-- to avoid invalid signals on the bus.
component busmacro_vector8_xc2vp_r2l_async_enable_narrow is
port (
macro_in : in std_logic_vector(7 downto 0);
enable : in std_logic_vector(7 downto 0);
macro_out : out std_logic_vector(7 downto 0)
);
end component;
-----------------------------------------------------
component IBUF is
port (
I : in std_logic;
O : out std_logic
);
end component;
component OBUF is
port (
I : in std_logic;
O : out std_logic
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
component IBUFG is
port (
I : in std_logic;
O : out std_logic
);
end component;
component BUFG is
port (
I : in std_logic;
O : out std_logic
);
end component;
-- Internal signals
signal C405RSTCHIPRESETREQ : std_logic;
signal C405RSTCORERESETREQ : std_logic;
signal C405RSTSYSRESETREQ : std_logic;
signal RSTC405RESETCHIP : std_logic;
signal RSTC405RESETCORE : std_logic;
signal RSTC405RESETSYS : std_logic;
signal clk_90_n_s : std_logic_vector(0 to 0);
signal clk_90_s : std_logic_vector(0 to 0);
signal dcm_0_lock : std_logic;
signal dcm_1_FB : std_logic;
signal dcm_1_lock : std_logic;
signal dcm_clk_s : std_logic;
signal ddr_clk_90_n_s : std_logic_vector(0 to 0);
signal ddr_clk_90_s : std_logic_vector(0 to 0);
signal ddr_clk_feedback_out_s : std_logic;
signal ddr_feedback_s : std_logic;
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr : std_logic_vector(0 to 12);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr : std_logic_vector(0 to 1);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn : std_logic;
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE : std_logic_vector(0 to 1);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn : std_logic_vector(0 to 1);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk : std_logic_vector(0 to 2);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn : std_logic_vector(0 to 2);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM : std_logic_vector(0 to 7);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I : std_logic_vector(0 to 7);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O : std_logic_vector(0 to 7);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T : std_logic_vector(0 to 7);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I : std_logic_vector(0 to 63);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O : std_logic_vector(0 to 63);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T : std_logic_vector(0 to 63);
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn : std_logic;
signal fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn : std_logic;
signal fpga_0_LEDs_4Bit_GPIO_IO_I : std_logic_vector(0 to 3);
signal fpga_0_LEDs_4Bit_GPIO_IO_O : std_logic_vector(0 to 3);
signal fpga_0_LEDs_4Bit_GPIO_IO_T : std_logic_vector(0 to 3);
signal fpga_0_PushButtons_5Bit_GPIO_IO_I : std_logic_vector(0 to 4);
signal fpga_0_PushButtons_5Bit_GPIO_IO_O : std_logic_vector(0 to 4);
signal fpga_0_PushButtons_5Bit_GPIO_IO_T : std_logic_vector(0 to 4);
signal fpga_0_RS232_Uart_1_RX : std_logic;
signal fpga_0_RS232_Uart_1_TX : std_logic;
signal fpga_0_SysACE_CompactFlash_SysACE_CEN : std_logic;
signal fpga_0_SysACE_CompactFlash_SysACE_CLK : std_logic;
signal fpga_0_SysACE_CompactFlash_SysACE_MPA : std_logic_vector(6 downto 0);
signal fpga_0_SysACE_CompactFlash_SysACE_MPD_I : std_logic_vector(15 downto 0);
signal fpga_0_SysACE_CompactFlash_SysACE_MPD_O : std_logic_vector(15 downto 0);
signal fpga_0_SysACE_CompactFlash_SysACE_MPD_T : std_logic_vector(15 downto 0);
signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ : std_logic;
signal fpga_0_SysACE_CompactFlash_SysACE_OEN : std_logic;
signal fpga_0_SysACE_CompactFlash_SysACE_WEN : std_logic;
signal jtagppc_0_0_C405JTGTDO : std_logic;
signal jtagppc_0_0_C405JTGTDOEN : std_logic;
signal jtagppc_0_0_JTGC405TCK : std_logic;
signal jtagppc_0_0_JTGC405TDI : std_logic;
signal jtagppc_0_0_JTGC405TMS : std_logic;
signal jtagppc_0_0_JTGC405TRSTNEG : std_logic;
signal jtagppc_0_1_C405JTGTDO : std_logic;
signal jtagppc_0_1_C405JTGTDOEN : std_logic;
signal jtagppc_0_1_JTGC405TCK : std_logic;
signal jtagppc_0_1_JTGC405TDI : std_logic;
signal jtagppc_0_1_JTGC405TMS : std_logic;
signal jtagppc_0_1_JTGC405TRSTNEG : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd32 : std_logic_vector(0 to 31);
signal net_gnd4 : std_logic_vector(0 to 3);
signal net_gnd5 : std_logic_vector(0 to 4);
signal net_gnd6 : std_logic_vector(0 to 5);
signal net_gnd64 : std_logic_vector(0 to 63);
signal net_gnd7 : std_logic_vector(0 to 6);
signal net_gnd8 : std_logic_vector(0 to 7);
signal net_vcc0 : std_logic;
signal net_vcc1 : std_logic_vector(0 to 0);
signal net_vcc6 : std_logic_vector(0 to 5);
signal opb_M_ABus : std_logic_vector(0 to 31);
signal opb_M_BE : std_logic_vector(0 to 3);
signal opb_M_DBus : std_logic_vector(0 to 31);
signal opb_M_RNW : std_logic_vector(0 to 0);
signal opb_M_busLock : std_logic_vector(0 to 0);
signal opb_M_request : std_logic_vector(0 to 0);
signal opb_M_select : std_logic_vector(0 to 0);
signal opb_M_seqAddr : std_logic_vector(0 to 0);
signal opb_OPB_ABus : std_logic_vector(0 to 31);
signal opb_OPB_BE : std_logic_vector(0 to 3);
signal opb_OPB_DBus : std_logic_vector(0 to 31);
signal opb_OPB_MGrant : std_logic_vector(0 to 0);
signal opb_OPB_RNW : std_logic;
signal opb_OPB_Rst : std_logic;
signal opb_OPB_errAck : std_logic;
signal opb_OPB_retry : std_logic;
signal opb_OPB_select : std_logic;
signal opb_OPB_seqAddr : std_logic;
signal opb_OPB_timeout : std_logic;
signal opb_OPB_xferAck : std_logic;
signal opb_Sl_DBus : std_logic_vector(0 to 191);
signal opb_Sl_errAck : std_logic_vector(0 to 5);
signal opb_Sl_retry : std_logic_vector(0 to 5);
signal opb_Sl_toutSup : std_logic_vector(0 to 5);
signal opb_Sl_xferAck : std_logic_vector(0 to 5);
signal pgassign1 : std_logic_vector(0 to 3);
signal pgassign2 : std_logic_vector(0 to 3);
signal pgassign3 : std_logic_vector(0 to 0);
signal plb_M_ABus : std_logic_vector(0 to 63);
signal plb_M_BE : std_logic_vector(0 to 15);
signal plb_M_MSize : std_logic_vector(0 to 3);
signal plb_M_RNW : std_logic_vector(0 to 1);
signal plb_M_abort : std_logic_vector(0 to 1);
signal plb_M_busLock : std_logic_vector(0 to 1);
signal plb_M_compress : std_logic_vector(0 to 1);
signal plb_M_guarded : std_logic_vector(0 to 1);
signal plb_M_lockErr : std_logic_vector(0 to 1);
signal plb_M_ordered : std_logic_vector(0 to 1);
signal plb_M_priority : std_logic_vector(0 to 3);
signal plb_M_rdBurst : std_logic_vector(0 to 1);
signal plb_M_request : std_logic_vector(0 to 1);
signal plb_M_size : std_logic_vector(0 to 7);
signal plb_M_type : std_logic_vector(0 to 5);
signal plb_M_wrBurst : std_logic_vector(0 to 1);
signal plb_M_wrDBus : std_logic_vector(0 to 127);
signal plb_PLB2OPB_rearb : std_logic_vector(0 to 3);
signal plb_PLB_ABus : std_logic_vector(0 to 31);
signal plb_PLB_BE : std_logic_vector(0 to 7);
signal plb_PLB_MAddrAck : std_logic_vector(0 to 1);
signal plb_PLB_MBusy : std_logic_vector(0 to 1);
signal plb_PLB_MErr : std_logic_vector(0 to 1);
signal plb_PLB_MRdBTerm : std_logic_vector(0 to 1);
signal plb_PLB_MRdDAck : std_logic_vector(0 to 1);
signal plb_PLB_MRdDBus : std_logic_vector(0 to 127);
signal plb_PLB_MRdWdAddr : std_logic_vector(0 to 7);
signal plb_PLB_MRearbitrate : std_logic_vector(0 to 1);
signal plb_PLB_MSSize : std_logic_vector(0 to 3);
signal plb_PLB_MSize : std_logic_vector(0 to 1);
signal plb_PLB_MWrBTerm : std_logic_vector(0 to 1);
signal plb_PLB_MWrDAck : std_logic_vector(0 to 1);
signal plb_PLB_PAValid : std_logic;
signal plb_PLB_RNW : std_logic;
signal plb_PLB_Rst : std_logic;
signal plb_PLB_SAValid : std_logic;
signal plb_PLB_SMBusy : std_logic_vector(0 to 1);
signal plb_PLB_SMErr : std_logic_vector(0 to 1);
signal plb_PLB_abort : std_logic;
signal plb_PLB_busLock : std_logic;
signal plb_PLB_compress : std_logic;
signal plb_PLB_guarded : std_logic;
signal plb_PLB_lockErr : std_logic;
signal plb_PLB_masterID : std_logic_vector(0 to 0);
signal plb_PLB_ordered : std_logic;
signal plb_PLB_pendPri : std_logic_vector(0 to 1);
signal plb_PLB_pendReq : std_logic;
signal plb_PLB_rdBurst : std_logic;
signal plb_PLB_rdPrim : std_logic;
signal plb_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_PLB_size : std_logic_vector(0 to 3);
signal plb_PLB_type : std_logic_vector(0 to 2);
signal plb_PLB_wrBurst : std_logic;
signal plb_PLB_wrDBus : std_logic_vector(0 to 63);
signal plb_PLB_wrPrim : std_logic;
signal plb_Sl_MBusy : std_logic_vector(0 to 7);
signal plb_Sl_MErr : std_logic_vector(0 to 7);
signal plb_Sl_SSize : std_logic_vector(0 to 7);
signal plb_Sl_addrAck : std_logic_vector(0 to 3);
signal plb_Sl_rdBTerm : std_logic_vector(0 to 3);
signal plb_Sl_rdComp : std_logic_vector(0 to 3);
signal plb_Sl_rdDAck : std_logic_vector(0 to 3);
signal plb_Sl_rdDBus : std_logic_vector(0 to 255);
signal plb_Sl_rdWdAddr : std_logic_vector(0 to 15);
signal plb_Sl_rearbitrate : std_logic_vector(0 to 3);
signal plb_Sl_wait : std_logic_vector(0 to 3);
signal plb_Sl_wrBTerm : std_logic_vector(0 to 3);
signal plb_Sl_wrComp : std_logic_vector(0 to 3);
signal plb_Sl_wrDAck : std_logic_vector(0 to 3);
signal plb_bram_if_cntlr_1_port_BRAM_Addr : std_logic_vector(0 to 31);
signal plb_bram_if_cntlr_1_port_BRAM_Clk : std_logic;
signal plb_bram_if_cntlr_1_port_BRAM_Din : std_logic_vector(0 to 63);
signal plb_bram_if_cntlr_1_port_BRAM_Dout : std_logic_vector(0 to 63);
signal plb_bram_if_cntlr_1_port_BRAM_EN : std_logic;
signal plb_bram_if_cntlr_1_port_BRAM_Rst : std_logic;
signal plb_bram_if_cntlr_1_port_BRAM_WEN : std_logic_vector(0 to 7);
signal proc_clk_s : std_logic;
signal sys_bus_reset : std_logic_vector(0 to 0);
signal sys_clk_n_s : std_logic_vector(0 to 0);
signal sys_clk_s : std_logic_vector(0 to 0);
signal sys_rst_s : std_logic;
-----------------------------------------------------
-- Signals to connect peripheral to macro. The original
-- signals are used to connect the bus to the macros.
-----------------------------------------------------
signal plb_PLB_Rst_module : std_logic;
signal plb_Sl_addrAck_module : std_logic_vector(3 to 3);
signal plb_Sl_MBusy_module : std_logic_vector(6 to 7);
signal plb_Sl_MErr_module : std_logic_vector(6 to 7);
signal plb_Sl_rdBTerm_module : std_logic_vector(3 to 3);
signal plb_Sl_rdComp_module : std_logic_vector(3 to 3);
signal plb_Sl_rdDAck_module : std_logic_vector(3 to 3);
signal plb_Sl_rdDBus_module : std_logic_vector(192 to 255);
signal plb_Sl_rdWdAddr_module : std_logic_vector(12 to 15);
signal plb_Sl_rearbitrate_module : std_logic_vector(3 to 3);
signal plb_Sl_SSize_module : std_logic_vector(6 to 7);
signal plb_Sl_wait_module : std_logic_vector(3 to 3);
signal plb_Sl_wrBTerm_module : std_logic_vector(3 to 3);
signal plb_Sl_wrComp_module : std_logic_vector(3 to 3);
signal plb_Sl_wrDAck_module : std_logic_vector(3 to 3);
signal plb_PLB_abort_module : std_logic;
signal plb_PLB_ABus_module : std_logic_vector(0 to 31);
signal plb_PLB_BE_module : std_logic_vector(0 to 7);
signal plb_PLB_busLock_module : std_logic;
signal plb_PLB_compress_module : std_logic;
signal plb_PLB_guarded_module : std_logic;
signal plb_PLB_lockErr_module : std_logic;
signal plb_PLB_masterID_module : std_logic_vector(0 to 0);
signal plb_PLB_MSize_module : std_logic_vector(0 to 1);
signal plb_PLB_ordered_module : std_logic;
signal plb_PLB_PAValid_module : std_logic;
signal plb_PLB_pendPri_module : std_logic_vector(0 to 1);
signal plb_PLB_pendReq_module : std_logic;
signal plb_PLB_rdBurst_module : std_logic;
signal plb_PLB_rdPrim_module : std_logic;
signal plb_PLB_reqPri_module : std_logic_vector(0 to 1);
signal plb_PLB_RNW_module : std_logic;
signal plb_PLB_SAValid_module : std_logic;
signal plb_PLB_size_module : std_logic_vector(0 to 3);
signal plb_PLB_type_module : std_logic_vector(0 to 2);
signal plb_PLB_wrBurst_module : std_logic;
signal plb_PLB_wrDBus_module : std_logic_vector(0 to 63);
signal plb_PLB_wrPrim_module : std_logic;
-----------------------------------------------------
-- additional signals for macro enable
signal gpio_out : std_logic_vector(0 to 7);
signal macro_enable : std_logic_vector(0 to 7);
-- clock signal for additional buffer after DCM
signal dcm_out_clk :std_logic;
-----------------------------------------------------
begin
-- Internal assignments
plb_PLB2OPB_rearb(1 to 1) <= B"0";
plb_PLB2OPB_rearb(2 to 2) <= B"0";
plb_PLB2OPB_rearb(3 to 3) <= B"0";
pgassign3(0 to 0) <= B"0";
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk(0 to 2) <= pgassign1(0 to 2);
ddr_clk_feedback_out_s <= pgassign1(3);
fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn(0 to 2) <= pgassign2(0 to 2);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
net_gnd4(0 to 3) <= B"0000";
net_gnd5(0 to 4) <= B"00000";
net_gnd6(0 to 5) <= B"000000";
net_gnd64(0 to 63) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd7(0 to 6) <= B"0000000";
net_gnd8(0 to 7) <= B"00000000";
net_vcc0 <= '1';
net_vcc1(0 to 0) <= B"1";
net_vcc6(0 to 5) <= B"111111";
macro_enable(0) <= gpio_out(0);
macro_enable(1) <= gpio_out(0);
macro_enable(2) <= gpio_out(0);
macro_enable(3) <= gpio_out(0);
macro_enable(4) <= gpio_out(0);
macro_enable(5) <= gpio_out(0);
macro_enable(6) <= gpio_out(0);
macro_enable(7) <= gpio_out(0);
ppc405_0 : ppc405_0_wrapper
port map (
C405CPMCORESLEEPREQ => open,
C405CPMMSRCE => open,
C405CPMMSREE => open,
C405CPMTIMERIRQ => open,
C405CPMTIMERRESETREQ => open,
C405XXXMACHINECHECK => open,
CPMC405CLOCK => proc_clk_s,
CPMC405CORECLKINACTIVE => net_gnd0,
CPMC405CPUCLKEN => net_vcc0,
CPMC405JTAGCLKEN => net_vcc0,
CPMC405TIMERCLKEN => net_vcc0,
CPMC405TIMERTICK => net_vcc0,
MCBCPUCLKEN => net_vcc0,
MCBTIMEREN => net_vcc0,
MCPPCRST => net_vcc0,
PLBCLK => sys_clk_s(0),
DCRCLK => net_gnd0,
C405RSTCHIPRESETREQ => C405RSTCHIPRESETREQ,
C405RSTCORERESETREQ => C405RSTCORERESETREQ,
C405RSTSYSRESETREQ => C405RSTSYSRESETREQ,
RSTC405RESETCHIP => RSTC405RESETCHIP,
RSTC405RESETCORE => RSTC405RESETCORE,
RSTC405RESETSYS => RSTC405RESETSYS,
C405PLBICUABUS => plb_M_ABus(32 to 63),
C405PLBICUBE => plb_M_BE(8 to 15),
C405PLBICURNW => plb_M_RNW(1),
C405PLBICUABORT => plb_M_abort(1),
C405PLBICUBUSLOCK => plb_M_busLock(1),
C405PLBICUU0ATTR => plb_M_compress(1),
C405PLBICUGUARDED => plb_M_guarded(1),
C405PLBICULOCKERR => plb_M_lockErr(1),
C405PLBICUMSIZE => plb_M_MSize(2 to 3),
C405PLBICUORDERED => plb_M_ordered(1),
C405PLBICUPRIORITY => plb_M_priority(2 to 3),
C405PLBICURDBURST => plb_M_rdBurst(1),
C405PLBICUREQUEST => plb_M_request(1),
C405PLBICUSIZE => plb_M_size(4 to 7),
C405PLBICUTYPE => plb_M_type(3 to 5),
C405PLBICUWRBURST => plb_M_wrBurst(1),
C405PLBICUWRDBUS => plb_M_wrDBus(64 to 127),
C405PLBICUCACHEABLE => open,
PLBC405ICUADDRACK => plb_PLB_MAddrAck(1),
PLBC405ICUBUSY => plb_PLB_MBusy(1),
PLBC405ICUERR => plb_PLB_MErr(1),
PLBC405ICURDBTERM => plb_PLB_MRdBTerm(1),
PLBC405ICURDDACK => plb_PLB_MRdDAck(1),
PLBC405ICURDDBUS => plb_PLB_MRdDBus(64 to 127),
PLBC405ICURDWDADDR => plb_PLB_MRdWdAddr(4 to 7),
PLBC405ICUREARBITRATE => plb_PLB_MRearbitrate(1),
PLBC405ICUWRBTERM => plb_PLB_MWrBTerm(1),
PLBC405ICUWRDACK => plb_PLB_MWrDAck(1),
PLBC405ICUSSIZE => plb_PLB_MSSize(2 to 3),
PLBC405ICUSERR => plb_PLB_SMErr(1),
PLBC405ICUSBUSYS => plb_PLB_SMBusy(1),
C405PLBDCUABUS => plb_M_ABus(0 to 31),
C405PLBDCUBE => plb_M_BE(0 to 7),
C405PLBDCURNW => plb_M_RNW(0),
C405PLBDCUABORT => plb_M_abort(0),
C405PLBDCUBUSLOCK => plb_M_busLock(0),
C405PLBDCUU0ATTR => plb_M_compress(0),
C405PLBDCUGUARDED => plb_M_guarded(0),
C405PLBDCULOCKERR => plb_M_lockErr(0),
C405PLBDCUMSIZE => plb_M_MSize(0 to 1),
C405PLBDCUORDERED => plb_M_ordered(0),
C405PLBDCUPRIORITY => plb_M_priority(0 to 1),
C405PLBDCURDBURST => plb_M_rdBurst(0),
C405PLBDCUREQUEST => plb_M_request(0),
C405PLBDCUSIZE => plb_M_size(0 to 3),
C405PLBDCUTYPE => plb_M_type(0 to 2),
C405PLBDCUWRBURST => plb_M_wrBurst(0),
C405PLBDCUWRDBUS => plb_M_wrDBus(0 to 63),
C405PLBDCUCACHEABLE => open,
C405PLBDCUWRITETHRU => open,
PLBC405DCUADDRACK => plb_PLB_MAddrAck(0),
PLBC405DCUBUSY => plb_PLB_MBusy(0),
PLBC405DCUERR => plb_PLB_MErr(0),
PLBC405DCURDBTERM => plb_PLB_MRdBTerm(0),
PLBC405DCURDDACK => plb_PLB_MRdDAck(0),
PLBC405DCURDDBUS => plb_PLB_MRdDBus(0 to 63),
PLBC405DCURDWDADDR => plb_PLB_MRdWdAddr(0 to 3),
PLBC405DCUREARBITRATE => plb_PLB_MRearbitrate(0),
PLBC405DCUWRBTERM => plb_PLB_MWrBTerm(0),
PLBC405DCUWRDACK => plb_PLB_MWrDAck(0),
PLBC405DCUSSIZE => plb_PLB_MSSize(0 to 1),
PLBC405DCUSERR => plb_PLB_SMErr(0),
PLBC405DCUSBUSYS => plb_PLB_SMBusy(0),
BRAMDSOCMCLK => net_gnd0,
BRAMDSOCMRDDBUS => net_gnd32,
DSARCVALUE => net_gnd8,
DSCNTLVALUE => net_gnd8,
DSOCMBRAMABUS => open,
DSOCMBRAMBYTEWRITE => open,
DSOCMBRAMEN => open,
DSOCMBRAMWRDBUS => open,
DSOCMBUSY => open,
BRAMISOCMCLK => net_gnd0,
BRAMISOCMRDDBUS => net_gnd64,
ISARCVALUE => net_gnd8,
ISCNTLVALUE => net_gnd8,
ISOCMBRAMEN => open,
ISOCMBRAMEVENWRITEEN => open,
ISOCMBRAMODDWRITEEN => open,
ISOCMBRAMRDABUS => open,
ISOCMBRAMWRABUS => open,
ISOCMBRAMWRDBUS => open,
C405DCRABUS => open,
C405DCRDBUSOUT => open,
C405DCRREAD => open,
C405DCRWRITE => open,
DCRC405ACK => net_gnd0,
DCRC405DBUSIN => net_gnd32,
EICC405CRITINPUTIRQ => net_gnd0,
EICC405EXTINPUTIRQ => net_gnd0,
C405JTGCAPTUREDR => open,
C405JTGEXTEST => open,
C405JTGPGMOUT => open,
C405JTGSHIFTDR => open,
C405JTGTDO => jtagppc_0_0_C405JTGTDO,
C405JTGTDOEN => jtagppc_0_0_C405JTGTDOEN,
C405JTGUPDATEDR => open,
MCBJTAGEN => net_vcc0,
JTGC405BNDSCANTDO => net_gnd0,
JTGC405TCK => jtagppc_0_0_JTGC405TCK,
JTGC405TDI => jtagppc_0_0_JTGC405TDI,
JTGC405TMS => jtagppc_0_0_JTGC405TMS,
JTGC405TRSTNEG => jtagppc_0_0_JTGC405TRSTNEG,
C405DBGMSRWE => open,
C405DBGSTOPACK => open,
C405DBGWBCOMPLETE => open,
C405DBGWBFULL => open,
C405DBGWBIAR => open,
DBGC405DEBUGHALT => net_gnd0,
DBGC405EXTBUSHOLDACK => net_gnd0,
DBGC405UNCONDDEBUGEVENT => net_gnd0,
C405TRCCYCLE => open,
C405TRCEVENEXECUTIONSTATUS => open,
C405TRCODDEXECUTIONSTATUS => open,
C405TRCTRACESTATUS => open,
C405TRCTRIGGEREVENTOUT => open,
C405TRCTRIGGEREVENTTYPE => open,
TRCC405TRACEDISABLE => net_gnd0,
TRCC405TRIGGEREVENTIN => net_gnd0
);
ppc405_1 : ppc405_1_wrapper
port map (
C405CPMCORESLEEPREQ => open,
C405CPMMSRCE => open,
C405CPMMSREE => open,
C405CPMTIMERIRQ => open,
C405CPMTIMERRESETREQ => open,
C405XXXMACHINECHECK => open,
CPMC405CLOCK => net_gnd0,
CPMC405CORECLKINACTIVE => net_gnd0,
CPMC405CPUCLKEN => net_vcc0,
CPMC405JTAGCLKEN => net_vcc0,
CPMC405TIMERCLKEN => net_vcc0,
CPMC405TIMERTICK => net_vcc0,
MCBCPUCLKEN => net_vcc0,
MCBTIMEREN => net_vcc0,
MCPPCRST => net_vcc0,
PLBCLK => net_gnd0,
DCRCLK => net_gnd0,
C405RSTCHIPRESETREQ => open,
C405RSTCORERESETREQ => open,
C405RSTSYSRESETREQ => open,
RSTC405RESETCHIP => net_gnd0,
RSTC405RESETCORE => net_gnd0,
RSTC405RESETSYS => net_gnd0,
C405PLBICUABUS => open,
C405PLBICUBE => open,
C405PLBICURNW => open,
C405PLBICUABORT => open,
C405PLBICUBUSLOCK => open,
C405PLBICUU0ATTR => open,
C405PLBICUGUARDED => open,
C405PLBICULOCKERR => open,
C405PLBICUMSIZE => open,
C405PLBICUORDERED => open,
C405PLBICUPRIORITY => open,
C405PLBICURDBURST => open,
C405PLBICUREQUEST => open,
C405PLBICUSIZE => open,
C405PLBICUTYPE => open,
C405PLBICUWRBURST => open,
C405PLBICUWRDBUS => open,
C405PLBICUCACHEABLE => open,
PLBC405ICUADDRACK => net_gnd0,
PLBC405ICUBUSY => net_gnd0,
PLBC405ICUERR => net_gnd0,
PLBC405ICURDBTERM => net_gnd0,
PLBC405ICURDDACK => net_gnd0,
PLBC405ICURDDBUS => net_gnd64,
PLBC405ICURDWDADDR => net_gnd4,
PLBC405ICUREARBITRATE => net_gnd0,
PLBC405ICUWRBTERM => net_gnd0,
PLBC405ICUWRDACK => net_gnd0,
PLBC405ICUSSIZE => net_gnd2,
PLBC405ICUSERR => net_gnd0,
PLBC405ICUSBUSYS => net_gnd0,
C405PLBDCUABUS => open,
C405PLBDCUBE => open,
C405PLBDCURNW => open,
C405PLBDCUABORT => open,
C405PLBDCUBUSLOCK => open,
C405PLBDCUU0ATTR => open,
C405PLBDCUGUARDED => open,
C405PLBDCULOCKERR => open,
C405PLBDCUMSIZE => open,
C405PLBDCUORDERED => open,
C405PLBDCUPRIORITY => open,
C405PLBDCURDBURST => open,
C405PLBDCUREQUEST => open,
C405PLBDCUSIZE => open,
C405PLBDCUTYPE => open,
C405PLBDCUWRBURST => open,
C405PLBDCUWRDBUS => open,
C405PLBDCUCACHEABLE => open,
C405PLBDCUWRITETHRU => open,
PLBC405DCUADDRACK => net_gnd0,
PLBC405DCUBUSY => net_gnd0,
PLBC405DCUERR => net_gnd0,
PLBC405DCURDBTERM => net_gnd0,
PLBC405DCURDDACK => net_gnd0,
PLBC405DCURDDBUS => net_gnd64,
PLBC405DCURDWDADDR => net_gnd4,
PLBC405DCUREARBITRATE => net_gnd0,
PLBC405DCUWRBTERM => net_gnd0,
PLBC405DCUWRDACK => net_gnd0,
PLBC405DCUSSIZE => net_gnd2,
PLBC405DCUSERR => net_gnd0,
PLBC405DCUSBUSYS => net_gnd0,
BRAMDSOCMCLK => net_gnd0,
BRAMDSOCMRDDBUS => net_gnd32,
DSARCVALUE => net_gnd8,
DSCNTLVALUE => net_gnd8,
DSOCMBRAMABUS => open,
DSOCMBRAMBYTEWRITE => open,
DSOCMBRAMEN => open,
DSOCMBRAMWRDBUS => open,
DSOCMBUSY => open,
BRAMISOCMCLK => net_gnd0,
BRAMISOCMRDDBUS => net_gnd64,
ISARCVALUE => net_gnd8,
ISCNTLVALUE => net_gnd8,
ISOCMBRAMEN => open,
ISOCMBRAMEVENWRITEEN => open,
ISOCMBRAMODDWRITEEN => open,
ISOCMBRAMRDABUS => open,
ISOCMBRAMWRABUS => open,
ISOCMBRAMWRDBUS => open,
C405DCRABUS => open,
C405DCRDBUSOUT => open,
C405DCRREAD => open,
C405DCRWRITE => open,
DCRC405ACK => net_gnd0,
DCRC405DBUSIN => net_gnd32,
EICC405CRITINPUTIRQ => net_gnd0,
EICC405EXTINPUTIRQ => net_gnd0,
C405JTGCAPTUREDR => open,
C405JTGEXTEST => open,
C405JTGPGMOUT => open,
C405JTGSHIFTDR => open,
C405JTGTDO => jtagppc_0_1_C405JTGTDO,
C405JTGTDOEN => jtagppc_0_1_C405JTGTDOEN,
C405JTGUPDATEDR => open,
MCBJTAGEN => net_vcc0,
JTGC405BNDSCANTDO => net_gnd0,
JTGC405TCK => jtagppc_0_1_JTGC405TCK,
JTGC405TDI => jtagppc_0_1_JTGC405TDI,
JTGC405TMS => jtagppc_0_1_JTGC405TMS,
JTGC405TRSTNEG => jtagppc_0_1_JTGC405TRSTNEG,
C405DBGMSRWE => open,
C405DBGSTOPACK => open,
C405DBGWBCOMPLETE => open,
C405DBGWBFULL => open,
C405DBGWBIAR => open,
DBGC405DEBUGHALT => net_gnd0,
DBGC405EXTBUSHOLDACK => net_gnd0,
DBGC405UNCONDDEBUGEVENT => net_gnd0,
C405TRCCYCLE => open,
C405TRCEVENEXECUTIONSTATUS => open,
C405TRCODDEXECUTIONSTATUS => open,
C405TRCTRACESTATUS => open,
C405TRCTRIGGEREVENTOUT => open,
C405TRCTRIGGEREVENTTYPE => open,
TRCC405TRACEDISABLE => net_gnd0,
TRCC405TRIGGEREVENTIN => net_gnd0
);
jtagppc_0 : jtagppc_0_wrapper
port map (
TRSTNEG => net_vcc0,
HALTNEG0 => net_vcc0,
DBGC405DEBUGHALT0 => open,
HALTNEG1 => net_vcc0,
DBGC405DEBUGHALT1 => open,
C405JTGTDO0 => jtagppc_0_0_C405JTGTDO,
C405JTGTDOEN0 => jtagppc_0_0_C405JTGTDOEN,
JTGC405TCK0 => jtagppc_0_0_JTGC405TCK,
JTGC405TDI0 => jtagppc_0_0_JTGC405TDI,
JTGC405TMS0 => jtagppc_0_0_JTGC405TMS,
JTGC405TRSTNEG0 => jtagppc_0_0_JTGC405TRSTNEG,
C405JTGTDO1 => jtagppc_0_1_C405JTGTDO,
C405JTGTDOEN1 => jtagppc_0_1_C405JTGTDOEN,
JTGC405TCK1 => jtagppc_0_1_JTGC405TCK,
JTGC405TDI1 => jtagppc_0_1_JTGC405TDI,
JTGC405TMS1 => jtagppc_0_1_JTGC405TMS,
JTGC405TRSTNEG1 => jtagppc_0_1_JTGC405TRSTNEG
);
reset_block : reset_block_wrapper
port map (
Slowest_sync_clk => sys_clk_s(0),
Ext_Reset_In => sys_rst_s,
Aux_Reset_In => net_gnd0,
Core_Reset_Req => C405RSTCORERESETREQ,
Chip_Reset_Req => C405RSTCHIPRESETREQ,
System_Reset_Req => C405RSTSYSRESETREQ,
Dcm_locked => dcm_1_lock,
Rstc405resetcore => RSTC405RESETCORE,
Rstc405resetchip => RSTC405RESETCHIP,
Rstc405resetsys => RSTC405RESETSYS,
Bus_Struct_Reset => sys_bus_reset(0 to 0),
Peripheral_Reset => open
);
plb : plb_wrapper
port map (
PLB_Clk => sys_clk_s(0),
SYS_Rst => sys_bus_reset(0),
PLB_Rst => plb_PLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_M_ABus,
M_BE => plb_M_BE,
M_RNW => plb_M_RNW,
M_abort => plb_M_abort,
M_busLock => plb_M_busLock,
M_compress => plb_M_compress,
M_guarded => plb_M_guarded,
M_lockErr => plb_M_lockErr,
M_MSize => plb_M_MSize,
M_ordered => plb_M_ordered,
M_priority => plb_M_priority,
M_rdBurst => plb_M_rdBurst,
M_request => plb_M_request,
M_size => plb_M_size,
M_type => plb_M_type,
M_wrBurst => plb_M_wrBurst,
M_wrDBus => plb_M_wrDBus,
Sl_addrAck => plb_Sl_addrAck,
Sl_MErr => plb_Sl_MErr,
Sl_MBusy => plb_Sl_MBusy,
Sl_rdBTerm => plb_Sl_rdBTerm,
Sl_rdComp => plb_Sl_rdComp,
Sl_rdDAck => plb_Sl_rdDAck,
Sl_rdDBus => plb_Sl_rdDBus,
Sl_rdWdAddr => plb_Sl_rdWdAddr,
Sl_rearbitrate => plb_Sl_rearbitrate,
Sl_SSize => plb_Sl_SSize,
Sl_wait => plb_Sl_wait,
Sl_wrBTerm => plb_Sl_wrBTerm,
Sl_wrComp => plb_Sl_wrComp,
Sl_wrDAck => plb_Sl_wrDAck,
PLB_ABus => plb_PLB_ABus,
PLB_BE => plb_PLB_BE,
PLB_MAddrAck => plb_PLB_MAddrAck,
PLB_MBusy => plb_PLB_MBusy,
PLB_MErr => plb_PLB_MErr,
PLB_MRdBTerm => plb_PLB_MRdBTerm,
PLB_MRdDAck => plb_PLB_MRdDAck,
PLB_MRdDBus => plb_PLB_MRdDBus,
PLB_MRdWdAddr => plb_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_PLB_MRearbitrate,
PLB_MWrBTerm => plb_PLB_MWrBTerm,
PLB_MWrDAck => plb_PLB_MWrDAck,
PLB_MSSize => plb_PLB_MSSize,
PLB_PAValid => plb_PLB_PAValid,
PLB_RNW => plb_PLB_RNW,
PLB_SAValid => plb_PLB_SAValid,
PLB_abort => plb_PLB_abort,
PLB_busLock => plb_PLB_busLock,
PLB_compress => plb_PLB_compress,
PLB_guarded => plb_PLB_guarded,
PLB_lockErr => plb_PLB_lockErr,
PLB_masterID => plb_PLB_masterID(0 to 0),
PLB_MSize => plb_PLB_MSize,
PLB_ordered => plb_PLB_ordered,
PLB_pendPri => plb_PLB_pendPri,
PLB_pendReq => plb_PLB_pendReq,
PLB_rdBurst => plb_PLB_rdBurst,
PLB_rdPrim => plb_PLB_rdPrim,
PLB_reqPri => plb_PLB_reqPri,
PLB_size => plb_PLB_size,
PLB_type => plb_PLB_type,
PLB_wrBurst => plb_PLB_wrBurst,
PLB_wrDBus => plb_PLB_wrDBus,
PLB_wrPrim => plb_PLB_wrPrim,
PLB_SaddrAck => open,
PLB_SMErr => plb_PLB_SMErr,
PLB_SMBusy => plb_PLB_SMBusy,
PLB_SrdBTerm => open,
PLB_SrdComp => open,
PLB_SrdDAck => open,
PLB_SrdDBus => open,
PLB_SrdWdAddr => open,
PLB_Srearbitrate => open,
PLB_Sssize => open,
PLB_Swait => open,
PLB_SwrBTerm => open,
PLB_SwrComp => open,
PLB_SwrDAck => open,
PLB2OPB_rearb => plb_PLB2OPB_rearb,
ArbAddrVldReg => open,
Bus_Error_Det => open
);
opb : opb_wrapper
port map (
OPB_Clk => sys_clk_s(0),
OPB_Rst => opb_OPB_Rst,
SYS_Rst => sys_bus_reset(0),
Debug_SYS_Rst => net_gnd0,
WDT_Rst => net_gnd0,
M_ABus => opb_M_ABus,
M_BE => opb_M_BE,
M_beXfer => net_gnd1(0 to 0),
M_busLock => opb_M_busLock(0 to 0),
M_DBus => opb_M_DBus,
M_DBusEn => net_gnd1(0 to 0),
M_DBusEn32_63 => net_vcc1(0 to 0),
M_dwXfer => net_gnd1(0 to 0),
M_fwXfer => net_gnd1(0 to 0),
M_hwXfer => net_gnd1(0 to 0),
M_request => opb_M_request(0 to 0),
M_RNW => opb_M_RNW(0 to 0),
M_select => opb_M_select(0 to 0),
M_seqAddr => opb_M_seqAddr(0 to 0),
Sl_beAck => net_gnd6,
Sl_DBus => opb_Sl_DBus,
Sl_DBusEn => net_vcc6,
Sl_DBusEn32_63 => net_vcc6,
Sl_errAck => opb_Sl_errAck,
Sl_dwAck => net_gnd6,
Sl_fwAck => net_gnd6,
Sl_hwAck => net_gnd6,
Sl_retry => opb_Sl_retry,
Sl_toutSup => opb_Sl_toutSup,
Sl_xferAck => opb_Sl_xferAck,
OPB_MRequest => open,
OPB_ABus => opb_OPB_ABus,
OPB_BE => opb_OPB_BE,
OPB_beXfer => open,
OPB_beAck => open,
OPB_busLock => open,
OPB_rdDBus => open,
OPB_wrDBus => open,
OPB_DBus => opb_OPB_DBus,
OPB_errAck => opb_OPB_errAck,
OPB_dwAck => open,
OPB_dwXfer => open,
OPB_fwAck => open,
OPB_fwXfer => open,
OPB_hwAck => open,
OPB_hwXfer => open,
OPB_MGrant => opb_OPB_MGrant(0 to 0),
OPB_pendReq => open,
OPB_retry => opb_OPB_retry,
OPB_RNW => opb_OPB_RNW,
OPB_select => opb_OPB_select,
OPB_seqAddr => opb_OPB_seqAddr,
OPB_timeout => opb_OPB_timeout,
OPB_toutSup => open,
OPB_xferAck => opb_OPB_xferAck
);
plb2opb : plb2opb_wrapper
port map (
PLB_Clk => sys_clk_s(0),
OPB_Clk => sys_clk_s(0),
PLB_Rst => plb_PLB_Rst,
OPB_Rst => opb_OPB_Rst,
Bus_Error_Det => open,
BGI_Trans_Abort => open,
BGO_dcrAck => open,
BGO_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
BGO_addrAck => plb_Sl_addrAck(0),
BGO_MErr => plb_Sl_MErr(0 to 1),
BGO_MBusy => plb_Sl_MBusy(0 to 1),
BGO_rdBTerm => plb_Sl_rdBTerm(0),
BGO_rdComp => plb_Sl_rdComp(0),
BGO_rdDAck => plb_Sl_rdDAck(0),
BGO_rdDBus => plb_Sl_rdDBus(0 to 63),
BGO_rdWdAddr => plb_Sl_rdWdAddr(0 to 3),
BGO_rearbitrate => plb_Sl_rearbitrate(0),
BGO_SSize => plb_Sl_SSize(0 to 1),
BGO_wait => plb_Sl_wait(0),
BGO_wrBTerm => plb_Sl_wrBTerm(0),
BGO_wrComp => plb_Sl_wrComp(0),
BGO_wrDAck => plb_Sl_wrDAck(0),
PLB_abort => plb_PLB_abort,
PLB_ABus => plb_PLB_ABus,
PLB_BE => plb_PLB_BE,
PLB_busLock => plb_PLB_busLock,
PLB_compress => plb_PLB_compress,
PLB_guarded => plb_PLB_guarded,
PLB_lockErr => plb_PLB_lockErr,
PLB_masterID => plb_PLB_masterID(0 to 0),
PLB_MSize => plb_PLB_MSize,
PLB_ordered => plb_PLB_ordered,
PLB_PAValid => plb_PLB_PAValid,
PLB_rdBurst => plb_PLB_rdBurst,
PLB_rdPrim => plb_PLB_rdPrim,
PLB_RNW => plb_PLB_RNW,
PLB_SAValid => plb_PLB_SAValid,
PLB_size => plb_PLB_size,
PLB_type => plb_PLB_type,
PLB_wrBurst => plb_PLB_wrBurst,
PLB_wrDBus => plb_PLB_wrDBus,
PLB_wrPrim => plb_PLB_wrPrim,
PLB2OPB_rearb => plb_PLB2OPB_rearb(0),
BGO_ABus => opb_M_ABus,
BGO_BE => opb_M_BE,
BGO_busLock => opb_M_busLock(0),
BGO_DBus => opb_M_DBus,
BGO_request => opb_M_request(0),
BGO_RNW => opb_M_RNW(0),
BGO_select => opb_M_select(0),
BGO_seqAddr => opb_M_seqAddr(0),
OPB_DBus => opb_OPB_DBus,
OPB_errAck => opb_OPB_errAck,
OPB_MnGrant => opb_OPB_MGrant(0),
OPB_retry => opb_OPB_retry,
OPB_timeout => opb_OPB_timeout,
OPB_xferAck => opb_OPB_xferAck
);
rs232_uart_1 : rs232_uart_1_wrapper
port map (
OPB_Clk => sys_clk_s(0),
OPB_Rst => opb_OPB_Rst,
Interrupt => open,
OPB_ABus => opb_OPB_ABus,
OPB_BE => opb_OPB_BE,
OPB_RNW => opb_OPB_RNW,
OPB_select => opb_OPB_select,
OPB_seqAddr => opb_OPB_seqAddr,
OPB_DBus => opb_OPB_DBus,
UART_DBus => opb_Sl_DBus(0 to 31),
UART_errAck => opb_Sl_errAck(0),
UART_retry => opb_Sl_retry(0),
UART_toutSup => opb_Sl_toutSup(0),
UART_xferAck => opb_Sl_xferAck(0),
RX => fpga_0_RS232_Uart_1_RX,
TX => fpga_0_RS232_Uart_1_TX
);
sysace_compactflash : sysace_compactflash_wrapper
port map (
OPB_Clk => sys_clk_s(0),
OPB_Rst => opb_OPB_Rst,
OPB_ABus => opb_OPB_ABus,
OPB_DBus => opb_OPB_DBus,
Sln_DBus => opb_Sl_DBus(32 to 63),
OPB_select => opb_OPB_select,
OPB_RNW => opb_OPB_RNW,
OPB_seqAddr => opb_OPB_seqAddr,
OPB_BE => opb_OPB_BE,
Sln_xferAck => opb_Sl_xferAck(1),
Sln_errAck => opb_Sl_errAck(1),
Sln_toutSup => opb_Sl_toutSup(1),
Sln_retry => opb_Sl_retry(1),
SysACE_MPA => fpga_0_SysACE_CompactFlash_SysACE_MPA,
SysACE_CLK => fpga_0_SysACE_CompactFlash_SysACE_CLK,
SysACE_MPIRQ => fpga_0_SysACE_CompactFlash_SysACE_MPIRQ,
SysACE_MPD_I => fpga_0_SysACE_CompactFlash_SysACE_MPD_I,
SysACE_MPD_O => fpga_0_SysACE_CompactFlash_SysACE_MPD_O,
SysACE_MPD_T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T,
SysACE_CEN => fpga_0_SysACE_CompactFlash_SysACE_CEN,
SysACE_OEN => fpga_0_SysACE_CompactFlash_SysACE_OEN,
SysACE_WEN => fpga_0_SysACE_CompactFlash_SysACE_WEN,
SysACE_IRQ => open
);
leds_4bit : leds_4bit_wrapper
port map (
OPB_ABus => opb_OPB_ABus,
OPB_BE => opb_OPB_BE,
OPB_Clk => sys_clk_s(0),
OPB_DBus => opb_OPB_DBus,
OPB_RNW => opb_OPB_RNW,
OPB_Rst => opb_OPB_Rst,
OPB_select => opb_OPB_select,
OPB_seqAddr => opb_OPB_seqAddr,
Sln_DBus => opb_Sl_DBus(64 to 95),
Sln_errAck => opb_Sl_errAck(2),
Sln_retry => opb_Sl_retry(2),
Sln_toutSup => opb_Sl_toutSup(2),
Sln_xferAck => opb_Sl_xferAck(2),
IP2INTC_Irpt => open,
GPIO_in => net_gnd4,
GPIO_d_out => open,
GPIO_t_out => open,
GPIO2_in => net_gnd4,
GPIO2_d_out => open,
GPIO2_t_out => open,
GPIO_IO_I => fpga_0_LEDs_4Bit_GPIO_IO_I,
GPIO_IO_O => fpga_0_LEDs_4Bit_GPIO_IO_O,
GPIO_IO_T => fpga_0_LEDs_4Bit_GPIO_IO_T,
GPIO2_IO_I => net_gnd4,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
pushbuttons_5bit : pushbuttons_5bit_wrapper
port map (
OPB_ABus => opb_OPB_ABus,
OPB_BE => opb_OPB_BE,
OPB_Clk => sys_clk_s(0),
OPB_DBus => opb_OPB_DBus,
OPB_RNW => opb_OPB_RNW,
OPB_Rst => opb_OPB_Rst,
OPB_select => opb_OPB_select,
OPB_seqAddr => opb_OPB_seqAddr,
Sln_DBus => opb_Sl_DBus(96 to 127),
Sln_errAck => opb_Sl_errAck(3),
Sln_retry => opb_Sl_retry(3),
Sln_toutSup => opb_Sl_toutSup(3),
Sln_xferAck => opb_Sl_xferAck(3),
IP2INTC_Irpt => open,
GPIO_in => net_gnd5,
GPIO_d_out => open,
GPIO_t_out => open,
GPIO2_in => net_gnd5,
GPIO2_d_out => open,
GPIO2_t_out => open,
GPIO_IO_I => fpga_0_PushButtons_5Bit_GPIO_IO_I,
GPIO_IO_O => fpga_0_PushButtons_5Bit_GPIO_IO_O,
GPIO_IO_T => fpga_0_PushButtons_5Bit_GPIO_IO_T,
GPIO2_IO_I => net_gnd5,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
ddr_512mb_64mx64_rank2_row13_col10_cl2_5 : ddr_512mb_64mx64_rank2_row13_col10_cl2_5_wrapper
port map (
PLB_Clk => sys_clk_s(0),
PLB_Clk_n => sys_clk_n_s(0),
Clk90_in => clk_90_s(0),
Clk90_in_n => clk_90_n_s(0),
DDR_Clk90_in => ddr_clk_90_s(0),
DDR_Clk90_in_n => ddr_clk_90_n_s(0),
PLB_Rst => plb_PLB_Rst,
PLB_ABus => plb_PLB_ABus,
PLB_PAValid => plb_PLB_PAValid,
PLB_SAValid => plb_PLB_SAValid,
PLB_rdPrim => plb_PLB_rdPrim,
PLB_wrPrim => plb_PLB_wrPrim,
PLB_masterID => plb_PLB_masterID(0 to 0),
PLB_abort => plb_PLB_abort,
PLB_busLock => plb_PLB_busLock,
PLB_RNW => plb_PLB_RNW,
PLB_BE => plb_PLB_BE,
PLB_MSize => plb_PLB_MSize,
PLB_size => plb_PLB_size,
PLB_type => plb_PLB_type,
PLB_compress => plb_PLB_compress,
PLB_guarded => plb_PLB_guarded,
PLB_ordered => plb_PLB_ordered,
PLB_lockErr => plb_PLB_lockErr,
PLB_wrDBus => plb_PLB_wrDBus,
PLB_wrBurst => plb_PLB_wrBurst,
PLB_rdBurst => plb_PLB_rdBurst,
PLB_pendReq => plb_PLB_pendReq,
PLB_pendPri => plb_PLB_pendPri,
PLB_reqPri => plb_PLB_reqPri,
Sl_addrAck => plb_Sl_addrAck(1),
Sl_SSize => plb_Sl_SSize(2 to 3),
Sl_wait => plb_Sl_wait(1),
Sl_rearbitrate => plb_Sl_rearbitrate(1),
Sl_wrDAck => plb_Sl_wrDAck(1),
Sl_wrComp => plb_Sl_wrComp(1),
Sl_wrBTerm => plb_Sl_wrBTerm(1),
Sl_rdDBus => plb_Sl_rdDBus(64 to 127),
Sl_rdWdAddr => plb_Sl_rdWdAddr(4 to 7),
Sl_rdDAck => plb_Sl_rdDAck(1),
Sl_rdComp => plb_Sl_rdComp(1),
Sl_rdBTerm => plb_Sl_rdBTerm(1),
Sl_MBusy => plb_Sl_MBusy(2 to 3),
Sl_MErr => plb_Sl_MErr(2 to 3),
IP2INTC_Irpt => open,
DDR_Clk => pgassign1,
DDR_Clkn => pgassign2,
DDR_CKE => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE,
DDR_CSn => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn,
DDR_RASn => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn,
DDR_CASn => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn,
DDR_WEn => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn,
DDR_DM => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM,
DDR_BankAddr => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr,
DDR_Addr => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr,
DDR_DM_ECC => open,
DDR_Init_done => open,
DDR_DQ_I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I,
DDR_DQ_O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O,
DDR_DQ_T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T,
DDR_DQS_I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I,
DDR_DQS_O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O,
DDR_DQS_T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T,
DDR_DQ_ECC_I => net_gnd7,
DDR_DQ_ECC_O => open,
DDR_DQ_ECC_T => open,
DDR_DQS_ECC_I => net_gnd0,
DDR_DQS_ECC_O => open,
DDR_DQS_ECC_T => open
);
plb_bram_if_cntlr_1 : plb_bram_if_cntlr_1_wrapper
port map (
plb_clk => sys_clk_s(0),
plb_rst => plb_PLB_Rst,
plb_abort => plb_PLB_abort,
plb_abus => plb_PLB_ABus,
plb_be => plb_PLB_BE,
plb_buslock => plb_PLB_busLock,
plb_compress => plb_PLB_compress,
plb_guarded => plb_PLB_guarded,
plb_lockerr => plb_PLB_lockErr,
plb_masterid => plb_PLB_masterID(0 to 0),
plb_msize => plb_PLB_MSize,
plb_ordered => plb_PLB_ordered,
plb_pavalid => plb_PLB_PAValid,
plb_rnw => plb_PLB_RNW,
plb_size => plb_PLB_size,
plb_type => plb_PLB_type,
sl_addrack => plb_Sl_addrAck(2),
sl_mbusy => plb_Sl_MBusy(4 to 5),
sl_merr => plb_Sl_MErr(4 to 5),
sl_rearbitrate => plb_Sl_rearbitrate(2),
sl_ssize => plb_Sl_SSize(4 to 5),
sl_wait => plb_Sl_wait(2),
plb_rdprim => plb_PLB_rdPrim,
plb_savalid => plb_PLB_SAValid,
plb_wrprim => plb_PLB_wrPrim,
plb_wrburst => plb_PLB_wrBurst,
plb_wrdbus => plb_PLB_wrDBus,
sl_wrbterm => plb_Sl_wrBTerm(2),
sl_wrcomp => plb_Sl_wrComp(2),
sl_wrdack => plb_Sl_wrDAck(2),
plb_rdburst => plb_PLB_rdBurst,
sl_rdbterm => plb_Sl_rdBTerm(2),
sl_rdcomp => plb_Sl_rdComp(2),
sl_rddack => plb_Sl_rdDAck(2),
sl_rddbus => plb_Sl_rdDBus(128 to 191),
sl_rdwdaddr => plb_Sl_rdWdAddr(8 to 11),
plb_pendreq => plb_PLB_pendReq,
plb_pendpri => plb_PLB_pendPri,
plb_reqpri => plb_PLB_reqPri,
bram_rst => plb_bram_if_cntlr_1_port_BRAM_Rst,
bram_clk => plb_bram_if_cntlr_1_port_BRAM_Clk,
bram_en => plb_bram_if_cntlr_1_port_BRAM_EN,
bram_wen => plb_bram_if_cntlr_1_port_BRAM_WEN,
bram_addr => plb_bram_if_cntlr_1_port_BRAM_Addr,
bram_din => plb_bram_if_cntlr_1_port_BRAM_Din,
bram_dout => plb_bram_if_cntlr_1_port_BRAM_Dout
);
plb_bram_if_cntlr_1_bram : plb_bram_if_cntlr_1_bram_wrapper
port map (
BRAM_Rst_A => plb_bram_if_cntlr_1_port_BRAM_Rst,
BRAM_Clk_A => plb_bram_if_cntlr_1_port_BRAM_Clk,
BRAM_EN_A => plb_bram_if_cntlr_1_port_BRAM_EN,
BRAM_WEN_A => plb_bram_if_cntlr_1_port_BRAM_WEN,
BRAM_Addr_A => plb_bram_if_cntlr_1_port_BRAM_Addr,
BRAM_Din_A => plb_bram_if_cntlr_1_port_BRAM_Din,
BRAM_Dout_A => plb_bram_if_cntlr_1_port_BRAM_Dout,
BRAM_Rst_B => net_gnd0,
BRAM_Clk_B => net_gnd0,
BRAM_EN_B => net_gnd0,
BRAM_WEN_B => net_gnd8,
BRAM_Addr_B => net_gnd32,
BRAM_Din_B => open,
BRAM_Dout_B => net_gnd64
);
sysclk_inv : sysclk_inv_wrapper
port map (
Op1 => sys_clk_s(0 to 0),
Op2 => net_gnd1(0 to 0),
Res => sys_clk_n_s(0 to 0)
);
clk90_inv : clk90_inv_wrapper
port map (
Op1 => clk_90_s(0 to 0),
Op2 => net_gnd1(0 to 0),
Res => clk_90_n_s(0 to 0)
);
ddr_clk90_inv : ddr_clk90_inv_wrapper
port map (
Op1 => ddr_clk_90_s(0 to 0),
Op2 => net_gnd1(0 to 0),
Res => ddr_clk_90_n_s(0 to 0)
);
dcm_0 : dcm_0_wrapper
port map (
RST => net_gnd0,
CLKIN => dcm_clk_s,
CLKFB => sys_clk_s(0),
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSCLK => net_gnd0,
DSSEN => net_gnd0,
CLK0 => dcm_out_clk,
CLK90 => clk_90_s(0),
CLK180 => open,
CLK270 => open,
CLKDV => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => proc_clk_s,
CLKFX180 => open,
STATUS => open,
LOCKED => dcm_0_lock,
PSDONE => open
);
dcm_1 : dcm_1_wrapper
port map (
RST => dcm_0_lock,
CLKIN => ddr_feedback_s,
CLKFB => dcm_1_FB,
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSCLK => net_gnd0,
DSSEN => net_gnd0,
CLK0 => dcm_1_FB,
CLK90 => ddr_clk_90_s(0),
CLK180 => open,
CLK270 => open,
CLKDV => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
STATUS => open,
LOCKED => dcm_1_lock,
PSDONE => open
);
opb_hwicap_0 : opb_hwicap_0_wrapper
port map (
OPB_Clk => sys_clk_s(0),
OPB_Rst => opb_OPB_Rst,
OPB_ABus => opb_OPB_ABus,
OPB_DBus => opb_OPB_DBus,
Sln_DBus => opb_Sl_DBus(128 to 159),
OPB_BE => opb_OPB_BE,
OPB_select => opb_OPB_select,
OPB_RNW => opb_OPB_RNW,
OPB_seqAddr => opb_OPB_seqAddr,
Sln_xferAck => opb_Sl_xferAck(4),
Sln_errAck => opb_Sl_errAck(4),
Sln_toutSup => opb_Sl_toutSup(4),
Sln_retry => opb_Sl_retry(4)
);
opb_gpio_0 : opb_gpio_0_wrapper
port map (
OPB_ABus => opb_OPB_ABus,
OPB_BE => opb_OPB_BE,
OPB_Clk => sys_clk_s(0),
OPB_DBus => opb_OPB_DBus,
OPB_RNW => opb_OPB_RNW,
OPB_Rst => opb_OPB_Rst,
OPB_select => opb_OPB_select,
OPB_seqAddr => opb_OPB_seqAddr,
Sln_DBus => opb_Sl_DBus(160 to 191),
Sln_errAck => opb_Sl_errAck(5),
Sln_retry => opb_Sl_retry(5),
Sln_toutSup => opb_Sl_toutSup(5),
Sln_xferAck => opb_Sl_xferAck(5),
IP2INTC_Irpt => open,
GPIO_in => net_gnd8,
GPIO_d_out => gpio_out,
GPIO_t_out => open,
GPIO2_in => net_gnd8,
GPIO2_d_out => open,
GPIO2_t_out => open,
GPIO_IO_I => net_gnd8,
GPIO_IO_O => open,
GPIO_IO_T => open,
GPIO2_IO_I => net_gnd8,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
-----------------------------------------------------
-- Connect peripheral to macro signals. The signals are
-- internal to module and have "_module" appended to the
-- original name.
-----------------------------------------------------
-- old instantiation:
-- math_0 : math_0_wrapper
-- port map (
-- PLB_Clk => sys_clk_s(0),
-- PLB_Rst => plb_PLB_Rst,
-- Sl_addrAck => plb_Sl_addrAck(3),
-- Sl_MBusy => plb_Sl_MBusy(6 to 7),
-- Sl_MErr => plb_Sl_MErr(6 to 7),
-- Sl_rdBTerm => plb_Sl_rdBTerm(3),
-- Sl_rdComp => plb_Sl_rdComp(3),
-- Sl_rdDAck => plb_Sl_rdDAck(3),
-- Sl_rdDBus => plb_Sl_rdDBus(192 to 255),
-- Sl_rdWdAddr => plb_Sl_rdWdAddr(12 to 15),
-- Sl_rearbitrate => plb_Sl_rearbitrate(3),
-- Sl_SSize => plb_Sl_SSize(6 to 7),
-- Sl_wait => plb_Sl_wait(3),
-- Sl_wrBTerm => plb_Sl_wrBTerm(3),
-- Sl_wrComp => plb_Sl_wrComp(3),
-- Sl_wrDAck => plb_Sl_wrDAck(3),
-- PLB_abort => plb_PLB_abort,
-- PLB_ABus => plb_PLB_ABus,
-- PLB_BE => plb_PLB_BE,
-- PLB_busLock => plb_PLB_busLock,
-- PLB_compress => plb_PLB_compress,
-- PLB_guarded => plb_PLB_guarded,
-- PLB_lockErr => plb_PLB_lockErr,
-- PLB_masterID => plb_PLB_masterID(0 to 0),
-- PLB_MSize => plb_PLB_MSize,
-- PLB_ordered => plb_PLB_ordered,
-- PLB_PAValid => plb_PLB_PAValid,
-- PLB_pendPri => plb_PLB_pendPri,
-- PLB_pendReq => plb_PLB_pendReq,
-- PLB_rdBurst => plb_PLB_rdBurst,
-- PLB_rdPrim => plb_PLB_rdPrim,
-- PLB_reqPri => plb_PLB_reqPri,
-- PLB_RNW => plb_PLB_RNW,
-- PLB_SAValid => plb_PLB_SAValid,
-- PLB_size => plb_PLB_size,
-- PLB_type => plb_PLB_type,
-- PLB_wrBurst => plb_PLB_wrBurst,
-- PLB_wrDBus => plb_PLB_wrDBus,
-- PLB_wrPrim => plb_PLB_wrPrim
-- );
-- new instantiation:
math_0 : math_0_wrapper
port map (
PLB_Clk => sys_clk_s(0),
PLB_Rst => plb_PLB_Rst_module,
Sl_addrAck => plb_Sl_addrAck_module(3),
Sl_MBusy => plb_Sl_MBusy_module(6 to 7),
Sl_MErr => plb_Sl_MErr_module(6 to 7),
Sl_rdBTerm => plb_Sl_rdBTerm_module(3),
Sl_rdComp => plb_Sl_rdComp_module(3),
Sl_rdDAck => plb_Sl_rdDAck_module(3),
Sl_rdDBus => plb_Sl_rdDBus_module(192 to 255),
Sl_rdWdAddr => plb_Sl_rdWdAddr_module(12 to 15),
Sl_rearbitrate => plb_Sl_rearbitrate_module(3),
Sl_SSize => plb_Sl_SSize_module(6 to 7),
Sl_wait => plb_Sl_wait_module(3),
Sl_wrBTerm => plb_Sl_wrBTerm_module(3),
Sl_wrComp => plb_Sl_wrComp_module(3),
Sl_wrDAck => plb_Sl_wrDAck_module(3),
PLB_abort => plb_PLB_abort_module,
PLB_ABus => plb_PLB_ABus_module,
PLB_BE => plb_PLB_BE_module,
PLB_busLock => plb_PLB_busLock_module,
PLB_compress => plb_PLB_compress_module,
PLB_guarded => plb_PLB_guarded_module,
PLB_lockErr => plb_PLB_lockErr_module,
PLB_masterID => plb_PLB_masterID_module(0 to 0),
PLB_MSize => plb_PLB_MSize_module,
PLB_ordered => plb_PLB_ordered_module,
PLB_PAValid => plb_PLB_PAValid_module,
PLB_pendPri => plb_PLB_pendPri_module,
PLB_pendReq => plb_PLB_pendReq_module,
PLB_rdBurst => plb_PLB_rdBurst_module,
PLB_rdPrim => plb_PLB_rdPrim_module,
PLB_reqPri => plb_PLB_reqPri_module,
PLB_RNW => plb_PLB_RNW_module,
PLB_SAValid => plb_PLB_SAValid_module,
PLB_size => plb_PLB_size_module,
PLB_type => plb_PLB_type_module,
PLB_wrBurst => plb_PLB_wrBurst_module,
PLB_wrDBus => plb_PLB_wrDBus_module,
PLB_wrPrim => plb_PLB_wrPrim_module
);
-----------------------------------------------------
-- added busmacro instances
-----------------------------------------------------
-- signals from bus to peripheral
macro_00 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_wrDBus(0 to 7),
macro_out => plb_PLB_wrDBus_module(0 to 7)
);
macro_01 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_wrDBus(8 to 15),
macro_out => plb_PLB_wrDBus_module(8 to 15)
);
macro_02 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_wrDBus(16 to 23),
macro_out => plb_PLB_wrDBus_module(16 to 23)
);
macro_03 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_wrDBus(24 to 31),
macro_out => plb_PLB_wrDBus_module(24 to 31)
);
macro_04 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_wrDBus(32 to 39),
macro_out => plb_PLB_wrDBus_module(32 to 39)
);
macro_05 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_wrDBus(40 to 47),
macro_out => plb_PLB_wrDBus_module(40 to 47)
);
macro_06 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_wrDBus(48 to 55),
macro_out => plb_PLB_wrDBus_module(48 to 55)
);
macro_07 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_wrDBus(56 to 63),
macro_out => plb_PLB_wrDBus_module(56 to 63)
);
macro_08 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_ABus(0 to 7),
macro_out => plb_PLB_ABus_module(0 to 7)
);
macro_09 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_ABus(8 to 15),
macro_out => plb_PLB_ABus_module(8 to 15)
);
macro_10 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_ABus(16 to 23),
macro_out => plb_PLB_ABus_module(16 to 23)
);
macro_11 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_ABus(24 to 31),
macro_out => plb_PLB_ABus_module(24 to 31)
);
macro_12 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in => plb_PLB_BE(0 to 7),
macro_out => plb_PLB_BE_module(0 to 7)
);
macro_13 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in(0) => plb_PLB_Rst,
macro_in(1) => plb_PLB_busLock,
macro_in(2) => plb_PLB_compress,
macro_in(3) => plb_PLB_guarded,
macro_in(4) => plb_PLB_lockErr,
macro_in(5) => plb_PLB_masterID(0),
macro_in(6) => plb_PLB_MSize(0),
macro_in(7) => plb_PLB_MSize(1),
macro_out(0) => plb_PLB_Rst_module,
macro_out(1) => plb_PLB_busLock_module,
macro_out(2) => plb_PLB_compress_module,
macro_out(3) => plb_PLB_guarded_module,
macro_out(4) => plb_PLB_lockErr_module,
macro_out(5) => plb_PLB_masterID_module(0),
macro_out(6) => plb_PLB_MSize_module(0),
macro_out(7) => plb_PLB_MSize_module(1)
);
macro_14 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in(0) => plb_PLB_ordered,
macro_in(1) => plb_PLB_PAValid,
macro_in(2) => plb_PLB_pendPri(0),
macro_in(3) => plb_PLB_pendPri(1),
macro_in(4) => plb_PLB_pendReq,
macro_in(5) => plb_PLB_rdBurst,
macro_in(6) => plb_PLB_rdPrim,
macro_in(7) => plb_PLB_RNW,
macro_out(0) => plb_PLB_ordered_module,
macro_out(1) => plb_PLB_PAValid_module,
macro_out(2) => plb_PLB_pendPri_module(0),
macro_out(3) => plb_PLB_pendPri_module(1),
macro_out(4) => plb_PLB_pendReq_module,
macro_out(5) => plb_PLB_rdBurst_module,
macro_out(6) => plb_PLB_rdPrim_module,
macro_out(7) => plb_PLB_RNW_module
);
macro_15 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in(0) => plb_PLB_reqPri(0),
macro_in(1) => plb_PLB_reqPri(1),
macro_in(2) => plb_PLB_SAValid,
macro_in(3) => plb_PLB_size(0),
macro_in(4) => plb_PLB_size(1),
macro_in(5) => plb_PLB_size(2),
macro_in(6) => plb_PLB_size(3),
macro_in(7) => plb_PLB_wrBurst,
macro_out(0) => plb_PLB_reqPri_module(0),
macro_out(1) => plb_PLB_reqPri_module(1),
macro_out(2) => plb_PLB_SAValid_module,
macro_out(3) => plb_PLB_size_module(0),
macro_out(4) => plb_PLB_size_module(1),
macro_out(5) => plb_PLB_size_module(2),
macro_out(6) => plb_PLB_size_module(3),
macro_out(7) => plb_PLB_wrBurst_module
);
macro_16 : busmacro_vector8_xc2vp_l2r_async_narrow
port map(
macro_in(0) => plb_PLB_type(0),
macro_in(1) => plb_PLB_type(1),
macro_in(2) => plb_PLB_type(2),
macro_in(3) => plb_PLB_wrPrim,
macro_in(4) => plb_PLB_abort,
macro_in(5) => '0',
macro_in(6) => '0',
macro_in(7) => '0',
macro_out(0) => plb_PLB_type_module(0),
macro_out(1) => plb_PLB_type_module(1),
macro_out(2) => plb_PLB_type_module(2),
macro_out(3) => plb_PLB_wrPrim_module,
macro_out(4) => plb_PLB_abort_module,
macro_out(5) => open,
macro_out(6) => open,
macro_out(7) => open
);
-- signals from peripheral to bus
macro_17 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in => plb_Sl_rdDBus_module(192 to 199),
enable => macro_enable,
macro_out => plb_Sl_rdDBus(192 to 199)
);
macro_18 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in => plb_Sl_rdDBus_module(200 to 207),
enable => macro_enable,
macro_out => plb_Sl_rdDBus(200 to 207)
);
macro_19 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in => plb_Sl_rdDBus_module(208 to 215),
enable => macro_enable,
macro_out => plb_Sl_rdDBus(208 to 215)
);
macro_20 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in => plb_Sl_rdDBus_module(216 to 223),
enable => macro_enable,
macro_out => plb_Sl_rdDBus(216 to 223)
);
macro_21 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in => plb_Sl_rdDBus_module(224 to 231),
enable => macro_enable,
macro_out => plb_Sl_rdDBus(224 to 231)
);
macro_22 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in => plb_Sl_rdDBus_module(232 to 239),
enable => macro_enable,
macro_out => plb_Sl_rdDBus(232 to 239)
);
macro_23 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in => plb_Sl_rdDBus_module(240 to 247),
enable => macro_enable,
macro_out => plb_Sl_rdDBus(240 to 247)
);
macro_24 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in => plb_Sl_rdDBus_module(248 to 255),
enable => macro_enable,
macro_out => plb_Sl_rdDBus(248 to 255)
);
macro_25 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in(0) => plb_Sl_rdWdAddr_module(12),
macro_in(1) => plb_Sl_rdWdAddr_module(13),
macro_in(2) => plb_Sl_rdWdAddr_module(14),
macro_in(3) => plb_Sl_rdWdAddr_module(15),
macro_in(4) => plb_Sl_rearbitrate_module(3),
macro_in(5) => plb_Sl_SSize_module(6),
macro_in(6) => plb_Sl_SSize_module(7),
macro_in(7) => plb_Sl_wait_module(3),
enable => macro_enable,
macro_out(0) => plb_Sl_rdWdAddr(12),
macro_out(1) => plb_Sl_rdWdAddr(13),
macro_out(2) => plb_Sl_rdWdAddr(14),
macro_out(3) => plb_Sl_rdWdAddr(15),
macro_out(4) => plb_Sl_rearbitrate(3),
macro_out(5) => plb_Sl_SSize(6),
macro_out(6) => plb_Sl_SSize(7),
macro_out(7) => plb_Sl_wait(3)
);
macro_26 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in(0) => plb_Sl_addrAck_module(3),
macro_in(1) => plb_Sl_MBusy_module(6),
macro_in(2) => plb_Sl_MBusy_module(7),
macro_in(3) => plb_Sl_MErr_module(6),
macro_in(4) => plb_Sl_MErr_module(7),
macro_in(5) => plb_Sl_rdBTerm_module(3),
macro_in(6) => plb_Sl_rdComp_module(3),
macro_in(7) => plb_Sl_rdDAck_module(3),
enable => macro_enable,
macro_out(0) => plb_Sl_addrAck(3),
macro_out(1) => plb_Sl_MBusy(6),
macro_out(2) => plb_Sl_MBusy(7),
macro_out(3) => plb_Sl_MErr(6),
macro_out(4) => plb_Sl_MErr(7),
macro_out(5) => plb_Sl_rdBTerm(3),
macro_out(6) => plb_Sl_rdComp(3),
macro_out(7) => plb_Sl_rdDAck(3)
);
macro_27 : busmacro_vector8_xc2vp_r2l_async_enable_narrow
port map(
macro_in(0) => plb_Sl_wrBTerm_module(3),
macro_in(1) => plb_Sl_wrComp_module(3),
macro_in(2) => plb_Sl_wrDAck_module(3),
macro_in(3) => '0',
macro_in(4) => '0',
macro_in(5) => '0',
macro_in(6) => '0',
macro_in(7) => '0',
enable => macro_enable,
macro_out(0) => plb_Sl_wrBTerm(3),
macro_out(1) => plb_Sl_wrComp(3),
macro_out(2) => plb_Sl_wrDAck(3),
macro_out(3) => open,
macro_out(4) => open,
macro_out(5) => open,
macro_out(6) => open,
macro_out(7) => open
);
-----------------------------------------------------
-- additional clock buffer
bufg_clk : BUFG
port map (
I => dcm_out_clk,
O => sys_clk_s(0)
);
-----------------------------------------------------
ibuf_0 : IBUF
port map (
I => fpga_0_RS232_Uart_1_RX_pin,
O => fpga_0_RS232_Uart_1_RX
);
obuf_1 : OBUF
port map (
I => fpga_0_RS232_Uart_1_TX,
O => fpga_0_RS232_Uart_1_TX_pin
);
ibuf_2 : IBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_CLK_pin,
O => fpga_0_SysACE_CompactFlash_SysACE_CLK
);
obuf_3 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPA(6),
O => fpga_0_SysACE_CompactFlash_SysACE_MPA_pin(6)
);
obuf_4 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPA(5),
O => fpga_0_SysACE_CompactFlash_SysACE_MPA_pin(5)
);
obuf_5 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPA(4),
O => fpga_0_SysACE_CompactFlash_SysACE_MPA_pin(4)
);
obuf_6 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPA(3),
O => fpga_0_SysACE_CompactFlash_SysACE_MPA_pin(3)
);
obuf_7 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPA(2),
O => fpga_0_SysACE_CompactFlash_SysACE_MPA_pin(2)
);
obuf_8 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPA(1),
O => fpga_0_SysACE_CompactFlash_SysACE_MPA_pin(1)
);
obuf_9 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPA(0),
O => fpga_0_SysACE_CompactFlash_SysACE_MPA_pin(0)
);
iobuf_10 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(15),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(15),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(15),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(15)
);
iobuf_11 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(14),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(14),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(14),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(14)
);
iobuf_12 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(13),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(13),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(13),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(13)
);
iobuf_13 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(12),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(12),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(12),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(12)
);
iobuf_14 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(11),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(11),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(11),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(11)
);
iobuf_15 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(10),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(10),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(10),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(10)
);
iobuf_16 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(9),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(9),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(9),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(9)
);
iobuf_17 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(8),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(8),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(8),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(8)
);
iobuf_18 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(7),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(7),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(7),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(7)
);
iobuf_19 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(6),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(6),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(6),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(6)
);
iobuf_20 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(5),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(5),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(5),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(5)
);
iobuf_21 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(4),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(4),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(4),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(4)
);
iobuf_22 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(3),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(3),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(3),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(3)
);
iobuf_23 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(2),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(2),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(2),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(2)
);
iobuf_24 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(1),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(1),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(1),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(1)
);
iobuf_25 : IOBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPD_O(0),
IO => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin(0),
O => fpga_0_SysACE_CompactFlash_SysACE_MPD_I(0),
T => fpga_0_SysACE_CompactFlash_SysACE_MPD_T(0)
);
obuf_26 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_CEN,
O => fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
);
obuf_27 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_OEN,
O => fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
);
obuf_28 : OBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_WEN,
O => fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
);
ibuf_29 : IBUF
port map (
I => fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin,
O => fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
);
iobuf_30 : IOBUF
port map (
I => fpga_0_LEDs_4Bit_GPIO_IO_O(0),
IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(0),
O => fpga_0_LEDs_4Bit_GPIO_IO_I(0),
T => fpga_0_LEDs_4Bit_GPIO_IO_T(0)
);
iobuf_31 : IOBUF
port map (
I => fpga_0_LEDs_4Bit_GPIO_IO_O(1),
IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(1),
O => fpga_0_LEDs_4Bit_GPIO_IO_I(1),
T => fpga_0_LEDs_4Bit_GPIO_IO_T(1)
);
iobuf_32 : IOBUF
port map (
I => fpga_0_LEDs_4Bit_GPIO_IO_O(2),
IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(2),
O => fpga_0_LEDs_4Bit_GPIO_IO_I(2),
T => fpga_0_LEDs_4Bit_GPIO_IO_T(2)
);
iobuf_33 : IOBUF
port map (
I => fpga_0_LEDs_4Bit_GPIO_IO_O(3),
IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(3),
O => fpga_0_LEDs_4Bit_GPIO_IO_I(3),
T => fpga_0_LEDs_4Bit_GPIO_IO_T(3)
);
iobuf_34 : IOBUF
port map (
I => fpga_0_PushButtons_5Bit_GPIO_IO_O(0),
IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(0),
O => fpga_0_PushButtons_5Bit_GPIO_IO_I(0),
T => fpga_0_PushButtons_5Bit_GPIO_IO_T(0)
);
iobuf_35 : IOBUF
port map (
I => fpga_0_PushButtons_5Bit_GPIO_IO_O(1),
IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(1),
O => fpga_0_PushButtons_5Bit_GPIO_IO_I(1),
T => fpga_0_PushButtons_5Bit_GPIO_IO_T(1)
);
iobuf_36 : IOBUF
port map (
I => fpga_0_PushButtons_5Bit_GPIO_IO_O(2),
IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(2),
O => fpga_0_PushButtons_5Bit_GPIO_IO_I(2),
T => fpga_0_PushButtons_5Bit_GPIO_IO_T(2)
);
iobuf_37 : IOBUF
port map (
I => fpga_0_PushButtons_5Bit_GPIO_IO_O(3),
IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(3),
O => fpga_0_PushButtons_5Bit_GPIO_IO_I(3),
T => fpga_0_PushButtons_5Bit_GPIO_IO_T(3)
);
iobuf_38 : IOBUF
port map (
I => fpga_0_PushButtons_5Bit_GPIO_IO_O(4),
IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(4),
O => fpga_0_PushButtons_5Bit_GPIO_IO_I(4),
T => fpga_0_PushButtons_5Bit_GPIO_IO_T(4)
);
obuf_39 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin(0)
);
obuf_40 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin(1)
);
obuf_41 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk(2),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin(2)
);
obuf_42 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin(0)
);
obuf_43 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin(1)
);
obuf_44 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn(2),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin(2)
);
obuf_45 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(0)
);
obuf_46 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(1)
);
obuf_47 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(2),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(2)
);
obuf_48 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(3),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(3)
);
obuf_49 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(4),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(4)
);
obuf_50 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(5),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(5)
);
obuf_51 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(6),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(6)
);
obuf_52 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(7),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(7)
);
obuf_53 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(8),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(8)
);
obuf_54 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(9),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(9)
);
obuf_55 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(10),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(10)
);
obuf_56 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(11),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(11)
);
obuf_57 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr(12),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin(12)
);
obuf_58 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin(0)
);
obuf_59 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin(1)
);
obuf_60 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn,
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin
);
obuf_61 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn,
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin
);
obuf_62 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn,
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin
);
obuf_63 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin(0)
);
obuf_64 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin(1)
);
obuf_65 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM(2),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin(2)
);
obuf_66 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM(3),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin(3)
);
obuf_67 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM(4),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin(4)
);
obuf_68 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM(5),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin(5)
);
obuf_69 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM(6),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin(6)
);
obuf_70 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM(7),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin(7)
);
iobuf_71 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O(0),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I(0),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T(0)
);
iobuf_72 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O(1),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I(1),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T(1)
);
iobuf_73 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O(2),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin(2),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I(2),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T(2)
);
iobuf_74 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O(3),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin(3),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I(3),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T(3)
);
iobuf_75 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O(4),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin(4),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I(4),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T(4)
);
iobuf_76 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O(5),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin(5),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I(5),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T(5)
);
iobuf_77 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O(6),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin(6),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I(6),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T(6)
);
iobuf_78 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_O(7),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin(7),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_I(7),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_T(7)
);
iobuf_79 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(0),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(0),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(0)
);
iobuf_80 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(1),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(1),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(1)
);
iobuf_81 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(2),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(2),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(2),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(2)
);
iobuf_82 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(3),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(3),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(3),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(3)
);
iobuf_83 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(4),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(4),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(4),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(4)
);
iobuf_84 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(5),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(5),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(5),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(5)
);
iobuf_85 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(6),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(6),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(6),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(6)
);
iobuf_86 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(7),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(7),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(7),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(7)
);
iobuf_87 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(8),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(8),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(8),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(8)
);
iobuf_88 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(9),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(9),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(9),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(9)
);
iobuf_89 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(10),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(10),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(10),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(10)
);
iobuf_90 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(11),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(11),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(11),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(11)
);
iobuf_91 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(12),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(12),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(12),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(12)
);
iobuf_92 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(13),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(13),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(13),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(13)
);
iobuf_93 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(14),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(14),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(14),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(14)
);
iobuf_94 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(15),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(15),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(15),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(15)
);
iobuf_95 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(16),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(16),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(16),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(16)
);
iobuf_96 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(17),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(17),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(17),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(17)
);
iobuf_97 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(18),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(18),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(18),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(18)
);
iobuf_98 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(19),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(19),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(19),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(19)
);
iobuf_99 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(20),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(20),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(20),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(20)
);
iobuf_100 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(21),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(21),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(21),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(21)
);
iobuf_101 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(22),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(22),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(22),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(22)
);
iobuf_102 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(23),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(23),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(23),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(23)
);
iobuf_103 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(24),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(24),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(24),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(24)
);
iobuf_104 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(25),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(25),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(25),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(25)
);
iobuf_105 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(26),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(26),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(26),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(26)
);
iobuf_106 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(27),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(27),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(27),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(27)
);
iobuf_107 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(28),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(28),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(28),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(28)
);
iobuf_108 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(29),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(29),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(29),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(29)
);
iobuf_109 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(30),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(30),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(30),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(30)
);
iobuf_110 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(31),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(31),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(31),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(31)
);
iobuf_111 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(32),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(32),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(32),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(32)
);
iobuf_112 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(33),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(33),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(33),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(33)
);
iobuf_113 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(34),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(34),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(34),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(34)
);
iobuf_114 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(35),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(35),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(35),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(35)
);
iobuf_115 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(36),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(36),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(36),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(36)
);
iobuf_116 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(37),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(37),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(37),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(37)
);
iobuf_117 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(38),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(38),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(38),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(38)
);
iobuf_118 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(39),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(39),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(39),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(39)
);
iobuf_119 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(40),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(40),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(40),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(40)
);
iobuf_120 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(41),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(41),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(41),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(41)
);
iobuf_121 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(42),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(42),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(42),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(42)
);
iobuf_122 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(43),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(43),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(43),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(43)
);
iobuf_123 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(44),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(44),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(44),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(44)
);
iobuf_124 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(45),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(45),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(45),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(45)
);
iobuf_125 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(46),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(46),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(46),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(46)
);
iobuf_126 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(47),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(47),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(47),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(47)
);
iobuf_127 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(48),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(48),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(48),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(48)
);
iobuf_128 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(49),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(49),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(49),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(49)
);
iobuf_129 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(50),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(50),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(50),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(50)
);
iobuf_130 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(51),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(51),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(51),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(51)
);
iobuf_131 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(52),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(52),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(52),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(52)
);
iobuf_132 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(53),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(53),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(53),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(53)
);
iobuf_133 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(54),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(54),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(54),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(54)
);
iobuf_134 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(55),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(55),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(55),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(55)
);
iobuf_135 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(56),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(56),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(56),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(56)
);
iobuf_136 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(57),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(57),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(57),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(57)
);
iobuf_137 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(58),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(58),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(58),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(58)
);
iobuf_138 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(59),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(59),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(59),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(59)
);
iobuf_139 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(60),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(60),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(60),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(60)
);
iobuf_140 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(61),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(61),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(61),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(61)
);
iobuf_141 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(62),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(62),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(62),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(62)
);
iobuf_142 : IOBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_O(63),
IO => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin(63),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_I(63),
T => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_T(63)
);
obuf_143 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin(0)
);
obuf_144 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin(1)
);
obuf_145 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn(0),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin(0)
);
obuf_146 : OBUF
port map (
I => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn(1),
O => fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin(1)
);
obuf_147 : OBUF
port map (
I => net_gnd0,
O => fpga_0_net_gnd_pin
);
obuf_148 : OBUF
port map (
I => net_gnd0,
O => fpga_0_net_gnd_1_pin
);
obuf_149 : OBUF
port map (
I => net_gnd0,
O => fpga_0_net_gnd_2_pin
);
obuf_150 : OBUF
port map (
I => net_gnd0,
O => fpga_0_net_gnd_3_pin
);
obuf_151 : OBUF
port map (
I => net_gnd0,
O => fpga_0_net_gnd_4_pin
);
obuf_152 : OBUF
port map (
I => net_gnd0,
O => fpga_0_net_gnd_5_pin
);
obuf_153 : OBUF
port map (
I => net_gnd0,
O => fpga_0_net_gnd_6_pin
);
ibufg_154 : IBUFG
port map (
I => fpga_0_DDR_CLK_FB,
O => ddr_feedback_s
);
obuf_155 : OBUF
port map (
I => ddr_clk_feedback_out_s,
O => fpga_0_DDR_CLK_FB_OUT
);
ibufg_156 : IBUFG
port map (
I => sys_clk_pin,
O => dcm_clk_s
);
ibuf_157 : IBUF
port map (
I => sys_rst_pin,
O => sys_rst_s
);
end architecture STRUCTURE;
|
gpl-3.0
|
3133724c00bcc7c375826600eee3425b
| 0.614888 | 2.76001 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/FrameBuffer/sim/FrameBuffer.vhd
| 1 | 13,039 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY FrameBuffer IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FrameBuffer;
ARCHITECTURE FrameBuffer_arch OF FrameBuffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FrameBuffer_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "FrameBuffer.mif",
C_INIT_FILE => "FrameBuffer.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 10240,
C_READ_DEPTH_A => 10240,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 10240,
C_READ_DEPTH_B => 10240,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.61856 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END FrameBuffer_arch;
|
mit
|
5d13965d6a4ec9f9e9b28738d69511b5
| 0.613467 | 3.241114 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/irq_gen_v1_1/f141c1dc/hdl/vhdl/pselect_f.vhd
| 2 | 12,603 |
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the user?s sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library my_ipif;
use my_ipif.family_support.native_lut_size;
use my_ipif.family_support.supported;
use my_ipif.family_support.u_muxcy;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
gpl-2.0
|
23a87799b54af4508eab34da44f97559
| 0.409585 | 5.360698 | false | false | false | false |
luebbers/reconos
|
tests/automated/semaphore/hw/hwthreads/semaphore/hwt_semaphore.vhd
| 1 | 1,611 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_semaphore is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_semaphore is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_SEMAPHORE_A : std_logic_vector(31 downto 0) := X"00000000";
constant C_SEMAPHORE_B : std_logic_vector(31 downto 0) := X"00000001";
type t_state is ( STATE_WAIT_A,
STATE_POST_B);
signal state : t_state;
begin
state_proc: process( clk, reset )
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_WAIT_A;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_WAIT_A =>
reconos_sem_wait(o_osif,i_osif,C_SEMAPHORE_A);
state <= STATE_POST_B;
when STATE_POST_B =>
reconos_sem_post(o_osif,i_osif,C_SEMAPHORE_B);
state <= STATE_WAIT_A;
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
1cde4bb966c5c8a285a1ef1c8af316b7
| 0.653011 | 2.816434 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_textio_read.vhd
| 2 | 2,939 |
-- Copyright (c) 2015-2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test reading files using std.textio library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity vhdl_textio_read is
port(
clk, active : in std_logic;
line_counter : out integer;
ok : out std_logic
);
end vhdl_textio_read;
architecture test of vhdl_textio_read is
begin
read_data: process(clk, active)
file data_file : text;
variable data_line : line;
variable data_string : string(6 downto 1);
variable data_int, data_hex : integer;
variable data_bool : boolean;
variable data_real : real;
variable data_time : time;
variable data_logic : std_logic_vector(5 downto 0);
begin
if rising_edge(active) then
file_open(data_file, "vhdl_textio.tmp", read_mode);
line_counter := 0;
elsif falling_edge(active) then
file_close(data_file);
end if;
if rising_edge(clk) and active = '1' then
readline(data_file, data_line);
line_counter := line_counter + 1;
case line_counter is
-- Test reading different variable types
when 1 => read(data_line, data_int);
when 2 => read(data_line, data_bool);
when 3 => read(data_line, data_time);
when 4 => hread(data_line, data_hex);
when 5 => read(data_line, data_real);
when 6 => read(data_line, data_string);
when 7 =>
read(data_line, data_logic);
-- Verify the read data
if data_int = 123
and data_bool = true
and data_time = 100 s
and data_hex = x"f3"
and data_real = 12.21
and data_string = "string"
and data_logic = "1100XZ" then
ok <= '1';
end if;
end case;
end if;
end process;
end test;
|
gpl-2.0
|
2a864a090439ac0a2839301be0015f62
| 0.56754 | 4.18661 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/bfm_monitor_wrapper.vhd
| 1 | 14,867 |
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_monitor_bfm_v1_00_a;
use plb_monitor_bfm_v1_00_a.All;
entity bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_compress : in std_logic_vector(0 to 1);
M_guarded : in std_logic_vector(0 to 1);
M_ordered : in std_logic_vector(0 to 1);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MErr : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_MErr : in std_logic_vector(0 to 3);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 63);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMErr : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end bfm_monitor_wrapper;
architecture STRUCTURE of bfm_monitor_wrapper is
component plb_monitor_bfm is
generic (
PLB_MONITOR_NUM : std_logic_vector(0 to 3);
PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31);
C_PLB_AWIDTH : integer;
C_PLB_DWIDTH : integer;
C_PLB_NUM_MASTERS : integer;
C_PLB_NUM_SLAVES : integer;
C_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to ((2*C_PLB_NUM_MASTERS)-1));
M_buslock : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_RNW : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_BE : in std_logic_vector(0 to ((C_PLB_NUM_MASTERS*C_PLB_DWIDTH/8)-1));
M_msize : in std_logic_vector(0 to ((2*C_PLB_NUM_MASTERS)-1));
M_size : in std_logic_vector(0 to ((4*C_PLB_NUM_MASTERS)-1));
M_type : in std_logic_vector(0 to ((3*C_PLB_NUM_MASTERS)-1));
M_compress : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_guarded : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_ordered : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_ABus : in std_logic_vector(0 to ((C_PLB_AWIDTH*C_PLB_NUM_MASTERS)-1));
M_wrDBus : in std_logic_vector(0 to ((C_PLB_DWIDTH*C_PLB_NUM_MASTERS)-1));
M_wrBurst : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_rdBurst : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MAddrAck : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRearbitrate : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MBusy : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MErr : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MWrDAck : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRdDBus : in std_logic_vector(0 to ((C_PLB_DWIDTH*C_PLB_NUM_MASTERS)-1));
PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_PLB_NUM_MASTERS)-1));
PLB_MRdDAck : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_Mssize : in std_logic_vector(0 to ((2*C_PLB_NUM_MASTERS)-1));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_MasterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wait : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to ((C_PLB_DWIDTH*C_PLB_NUM_SLAVES)-1));
Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_PLB_NUM_SLAVES)-1));
Sl_rdDAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdBTerm : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_MBusy : in std_logic_vector(0 to ((C_PLB_NUM_MASTERS*C_PLB_NUM_SLAVES)-1));
Sl_MErr : in std_logic_vector(0 to ((C_PLB_NUM_MASTERS*C_PLB_NUM_SLAVES)-1));
Sl_ssize : in std_logic_vector(0 to ((2*C_PLB_NUM_SLAVES)-1));
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_SMErr : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
begin
bfm_monitor : plb_monitor_bfm
generic map (
PLB_MONITOR_NUM => "0000",
PLB_SLAVE0_ADDR_LO_0 => X"00000000",
PLB_SLAVE0_ADDR_HI_0 => X"00000000",
PLB_SLAVE1_ADDR_LO_0 => X"00000000",
PLB_SLAVE1_ADDR_HI_0 => X"00000000",
PLB_SLAVE2_ADDR_LO_0 => X"00000000",
PLB_SLAVE2_ADDR_HI_0 => X"00000000",
PLB_SLAVE3_ADDR_LO_0 => X"00000000",
PLB_SLAVE3_ADDR_HI_0 => X"00000000",
PLB_SLAVE4_ADDR_LO_0 => X"00000000",
PLB_SLAVE4_ADDR_HI_0 => X"00000000",
PLB_SLAVE5_ADDR_LO_0 => X"00000000",
PLB_SLAVE5_ADDR_HI_0 => X"00000000",
PLB_SLAVE6_ADDR_LO_0 => X"00000000",
PLB_SLAVE6_ADDR_HI_0 => X"00000000",
PLB_SLAVE7_ADDR_LO_0 => X"00000000",
PLB_SLAVE7_ADDR_HI_0 => X"00000000",
PLB_SLAVE0_ADDR_LO_1 => X"00000000",
PLB_SLAVE0_ADDR_HI_1 => X"00000000",
PLB_SLAVE1_ADDR_LO_1 => X"00000000",
PLB_SLAVE1_ADDR_HI_1 => X"00000000",
PLB_SLAVE2_ADDR_LO_1 => X"00000000",
PLB_SLAVE2_ADDR_HI_1 => X"00000000",
PLB_SLAVE3_ADDR_LO_1 => X"00000000",
PLB_SLAVE3_ADDR_HI_1 => X"00000000",
PLB_SLAVE4_ADDR_LO_1 => X"00000000",
PLB_SLAVE4_ADDR_HI_1 => X"00000000",
PLB_SLAVE5_ADDR_LO_1 => X"00000000",
PLB_SLAVE5_ADDR_HI_1 => X"00000000",
PLB_SLAVE6_ADDR_LO_1 => X"00000000",
PLB_SLAVE6_ADDR_HI_1 => X"00000000",
PLB_SLAVE7_ADDR_LO_1 => X"00000000",
PLB_SLAVE7_ADDR_HI_1 => X"00000000",
C_PLB_AWIDTH => 32,
C_PLB_DWIDTH => 64,
C_PLB_NUM_MASTERS => 2,
C_PLB_NUM_SLAVES => 2,
C_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_compress => M_compress,
M_guarded => M_guarded,
M_ordered => M_ordered,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_Mssize => PLB_Mssize,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_MasterID => PLB_MasterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_ordered => PLB_ordered,
PLB_lockErr => PLB_lockErr,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_pendReq => PLB_pendReq,
PLB_pendPri => PLB_pendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
Sl_ssize => Sl_ssize,
PLB_SaddrAck => PLB_SaddrAck,
PLB_Swait => PLB_Swait,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_SwrDAck => PLB_SwrDAck,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SMBusy => PLB_SMBusy,
PLB_SMErr => PLB_SMErr,
PLB_Sssize => PLB_Sssize
);
end architecture STRUCTURE;
|
gpl-3.0
|
de6ebe489b00db53af3d84b2a14d8c52
| 0.601265 | 2.934083 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/Vga.vhd
| 2 | 62,950 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas adapted from Alec Wyen and Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 13:01:51 02/15/2013
-- Design Name:
-- Module Name: Vga - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the Vga controller that creates the HSYNC and VSYNC signals
-- for the VGA screen and formats the 4-bit R, G and B signals to display various items
-- on the screen:
-- - A moving colorbar in the background
-- - A Digilent - Analog Devices logo for the Nexys4 board, the RGB data is provided
-- by the LogoDisplay component. The logo bitmap is stored in the BRAM_1 Block RAM in .ngc format.
-- - The FPGA temperature on a 0..80C scale. Temperature data is taken from the XADC
-- component in the Artix-7 FPGA, provided by the upper level FPGAMonitor component and the RGB data is
-- provided by the Inst_XadcTempDisplay instance of the TempDisplay component.
-- - The Nexys4 Onboard ADT7420 Temperature Sensor temperature on a 0..80C scale.
-- Temperature data is provided by the upper level TempSensorCtl component and the RGB data is
-- provided by the Inst_Adt7420TempDisplay instance of the TempDisplay component.
-- - The Nexys4 Onboard ADXL362 Accelerometer Temperature Sensor temperature on a 0..80C scale.
-- Temperature data is provided by the upper level AccelerometerCtl component and the RGB data is
-- provided by the Inst_Adxl362TempDisplay instance of the TempDisplay component.
-- - The R, G and B data which is also sent to the Nexys4 onboard RGB Leds LD16 and LD17. The
-- incomming RGB Led data is taken from the upper level RgbLed component and the formatted RGB data is provided
-- by the RGBLedDisplay component.
-- - The audio signal coming from the Nexys4 Onboard ADMP421 Omnidirectional Microphone. The formatted
-- RGB data is provided by the MicDisplay component.
-- - The X and Y acceleration in a form of a moving box and the acceleration magnitude determined by
-- the SQRT (X^2 + Y^2 + Z^2) formula. The acceleration and magnitude data is provided by the upper level
-- AccelerometerCtl component and the formatted RGB data is provided by the AccelDisplay component.
-- - The mouse cursor on the top on all of the items. The USB mouse should be connected to the Nexys4 board before
-- the FPGA is configured. The mouse cursor data is provided by the upper level MouseCtl component and the
-- formatted RGB data for the mouse cursor shape is provided by the MouseDisplay component.
-- - An overlay that displayed the frames and text for the displayed items described above. The overlay data is
-- stored in the overlay_bram Block RAM in the .ngc format and the data is provided by the OverlayCtl component.
-- The Vga controller holds the synchronization signal generation, the moving colorbar generation and the main
-- multiplexers for the outgoing R, G and B signals. Also the 108 MHz pixel clock (pxl_clk) generator is instantiated
-- inside the Vga controller.
-- The current resolution is 1280X1024 pixels, however, other resolutions can also be selected by
-- commenting/uncommenting the corresponding VGA resolution constants. In the case when a different resolution
-- is selected, the pixel clock generator output frequency also has to be updated accordingly.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Vga is
Port ( CLK_I : in STD_LOGIC;
-- VGA Output Signals
VGA_HS_O : out STD_LOGIC; -- HSYNC OUT
VGA_VS_O : out STD_LOGIC; -- VSYNC OUT
VGA_RED_O : out STD_LOGIC_VECTOR (3 downto 0); -- Red signal going to the VGA interface
VGA_GREEN_O : out STD_LOGIC_VECTOR (3 downto 0); -- Green signal going to the VGA interface
VGA_BLUE_O : out STD_LOGIC_VECTOR (3 downto 0); -- Blue signal going to the VGA interface
-- Input Signals
-- RGB LED
RGB_LED_RED : in STD_LOGIC_VECTOR (7 downto 0);
RGB_LED_GREEN : in STD_LOGIC_VECTOR (7 downto 0);
RGB_LED_BLUE : in STD_LOGIC_VECTOR (7 downto 0);
-- Accelerometer
ACCEL_RADIUS : in STD_LOGIC_VECTOR (11 downto 0); -- Size of the box moving when the board is tilted
LEVEL_THRESH : in STD_LOGIC_VECTOR (11 downto 0); -- Size of the internal box in which the moving box is green
ACL_X_IN : in STD_LOGIC_VECTOR (8 downto 0); -- X Acceleration Data
ACL_Y_IN : in STD_LOGIC_VECTOR (8 downto 0); -- Y Acceleration Data
ACL_MAG_IN : in STD_LOGIC_VECTOR (11 downto 0); -- Acceleration Magnitude
-- Microphone
MIC_M_DATA_I : IN STD_LOGIC; -- Input microphone data
MIC_M_CLK_RISING : IN STD_LOGIC; -- Active when the data from the microphone is read
-- Mouse signals
MOUSE_X_POS : in std_logic_vector (11 downto 0); -- X position from the mouse
MOUSE_Y_POS : in std_logic_vector (11 downto 0); -- Y position from the mouse
-- Temperature data signals
XADC_TEMP_VALUE_I : in std_logic_vector (11 downto 0); -- FPGA Temperature data from the XADC
ADT7420_TEMP_VALUE_I : in std_logic_vector (12 downto 0); -- Temperature data from the Onboard Temperature Sensor
ADXL362_TEMP_VALUE_I : in std_logic_vector (11 downto 0) -- Temperature Data from the Accelerometer
);
end Vga;
architecture Behavioral of Vga is
-------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------
-- To generate the 108 MHz Pixel Clock
-- needed for a resolution of 1280*1024 pixels
COMPONENT PxlClkGen
PORT
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
END COMPONENT;
-- Display the Digilent Nexys 4 and Analog Devices Logo
COMPONENT LogoDisplay
GENERIC(
X_START : integer range 2 to (Integer'high) := 40; -- Logo Starting Horizontal Location
Y_START : integer := 512 -- Logo Starting Vertical Location
);
PORT(
CLK_I : IN std_logic;
H_COUNT_I : IN std_logic_vector(11 downto 0);
V_COUNT_I : IN std_logic_vector(11 downto 0);
-- Logo Red, Green and Blue signals
RED_O : OUT std_logic_vector(3 downto 0);
BLUE_O : OUT std_logic_vector(3 downto 0);
GREEN_O : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
-- Display the overlay
COMPONENT OverlayCtl
PORT(
CLK_I : IN std_logic;
VSYNC_I : IN std_logic;
ACTIVE_I : IN std_logic;
OVERLAY_O : OUT std_logic
);
END COMPONENT;
-- Display the LD16 and LD17 RGB LED data
COMPONENT RgbLedDisplay
GENERIC(
X_RGB_COL_WIDTH : natural := 50; -- SZ_RGB_WIDTH - width of one RGB column
Y_RGB_COL_HEIGHT : natural := 150; -- SZ_RGB_HEIGHT - height of one RGB column
X_RGB_R_LOC : natural := 1050; -- FRM_RGB_R_H_LOC
X_RGB_G_LOC : natural := 1125; -- FRM_RGB_G_H_LOC
X_RGB_B_LOC : natural := 1200; -- FRM_RGB_B_H_LOC
Y_RGB_1_LOC : natural := 675; -- FRM_RGB_1_V_LOC
Y_RGB_2_LOC : natural := 840 -- FRM_RGB_1_V_LOC + SZ_RGB_HEIGHT + 15
);
PORT (
pxl_clk : in std_logic;
RGB_LED_RED : in STD_LOGIC_VECTOR (4 downto 0);
RGB_LED_GREEN : in STD_LOGIC_VECTOR (4 downto 0);
RGB_LED_BLUE : in STD_LOGIC_VECTOR (4 downto 0);
H_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
-- Red Columns RGB LED Data
RGB_LED_R_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_R_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_R_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0);
-- Green Columns RGB LED Data
RGB_LED_G_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_G_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_G_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0);
-- Blue Columns RGB LED Data
RGB_LED_B_RED_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_B_GREEN_COL : out STD_LOGIC_VECTOR (3 downto 0);
RGB_LED_B_BLUE_COL : out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
-- Display the FPGA, Temp Sensor and Accelerometer Temperature
COMPONENT TempDisplay
GENERIC(
X_TMP_COL_WIDTH : natural := 50; -- = SZ_TH_WIDTH - width of a TMP column
Y_TMP_COL_HEIGHT : natural := 472; -- = SZ_TH_HEIGHT - height of a TMP column
X_TMP_H_LOC : natural := 1050; -- X Location of the TMP Column
Y_TMP_V_LOC : natural := 80; -- Y Location of the TMP Column
INPUT_DATA_WIDTH : natural := 13; -- Data width is 13 for XADC and 12 for Temperature Sensor and
-- Accelerometer Temperature Sensor
TMP_TYPE : string := "XADC"
);
PORT ( CLK_I : in STD_LOGIC;
TEMP_IN : in STD_LOGIC_VECTOR (INPUT_DATA_WIDTH - 1 downto 0); -- Input Temperature Data
H_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
-- Temperature Red, Green and Blue signals
TEMP_R_OUT : out STD_LOGIC_VECTOR (3 downto 0);
TEMP_G_OUT : out STD_LOGIC_VECTOR (3 downto 0);
TEMP_B_OUT : out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
-- Display signal from the Onboard Microphone
COMPONENT MicDisplay
GENERIC(
X_WIDTH : integer := 1000;
Y_HEIGHT : integer := 400;
X_START : integer range 2 to (Integer'high) := 40;
Y_START : integer := 512;
PXLCLK_FREQ_HZ : integer := 108000000;
H_MAX : integer := 1688;
SAMPLE_RATE_DIV : integer := 4096;
BG_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"FFF";
ACTIVE_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"008" -- Light blue
);
PORT(
CLK_I : IN std_logic;
SYSCLK : IN std_logic;
H_COUNT_I : IN std_logic_vector(11 downto 0);
V_COUNT_I : IN std_logic_vector(11 downto 0);
MIC_M_DATA_I : IN std_logic;
MIC_M_CLK_RISING : IN STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR (3 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (3 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
-- Display the moving box and acceleration magnitude according to accelerometer data
COMPONENT AccelDisplay
GENERIC
(
X_XY_WIDTH : natural := 511; -- Width of the Accelerometer frame X-Y region
X_MAG_WIDTH : natural := 50; -- Width of the Accelerometer frame Magnitude region
Y_HEIGHT : natural := 511; -- Height of the Accelerometer frame
X_START : natural := 385; -- Accelerometer frame X-Y region starting horizontal location
Y_START : natural := 80; -- Accelerometer frame starting vertical location
BG_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"FFF"; -- Background color - white
ACTIVE_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"0F0"; -- Green when inside the threshold box
WARNING_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"F00" -- Red when outside the threshold box
);
PORT
(
CLK_I : IN std_logic;
H_COUNT_I : IN std_logic_vector(11 downto 0);
V_COUNT_I : IN std_logic_vector(11 downto 0);
ACCEL_X_I : IN std_logic_vector(8 downto 0); -- X acceleration input data
ACCEL_Y_I : IN std_logic_vector(8 downto 0); -- Y acceleration input data
ACCEL_MAG_I : IN std_logic_vector(8 downto 0); -- Acceleration magnitude input data
ACCEL_RADIUS : IN STD_LOGIC_VECTOR (11 downto 0); -- Size of the box moving according to acceleration data
LEVEL_THRESH : IN STD_LOGIC_VECTOR (11 downto 0); -- Size of the threshold box
-- Acceleerometer Red, Green and Blue signals
RED_O : OUT std_logic_vector(3 downto 0);
BLUE_O : OUT std_logic_vector(3 downto 0);
GREEN_O : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
-- Display the Mouse cursor
COMPONENT MouseDisplay
PORT (
pixel_clk: in std_logic;
xpos : in std_logic_vector(11 downto 0); -- Mouse cursor X position
ypos : in std_logic_vector(11 downto 0); -- Mouse cursor Y position
hcount : in std_logic_vector(11 downto 0);
vcount : in std_logic_vector(11 downto 0);
--blank : in std_logic; -- blank the screen in overlay mode, here is not used
enable_mouse_display_out : out std_logic; -- When active, the mouse cursor signal is sent to the VGA display
--red_in : in std_logic_vector(3 downto 0); -- Red, Green and Blue input signal in overlay mode, here are not used
--green_in : in std_logic_vector(3 downto 0);
--blue_in : in std_logic_vector(3 downto 0);
-- Output Red, blue and Green Signals
red_out : out std_logic_vector(3 downto 0);
green_out: out std_logic_vector(3 downto 0);
blue_out : out std_logic_vector(3 downto 0)
);
END COMPONENT;
-------------------------------------------------------------
-- Constants for various VGA Resolutions
-------------------------------------------------------------
--***640x480@60Hz***--
--constant FRAME_WIDTH : natural := 640;
--constant FRAME_HEIGHT : natural := 480;
--constant H_FP : natural := 16; --H front porch width (pixels)
--constant H_PW : natural := 96; --H sync pulse width (pixels)
--constant H_MAX : natural := 800; --H total period (pixels)
--
--constant V_FP : natural := 10; --V front porch width (lines)
--constant V_PW : natural := 2; --V sync pulse width (lines)
--constant V_MAX : natural := 525; --V total period (lines)
--constant H_POL : std_logic := '0';
--constant V_POL : std_logic := '0';
--***800x600@60Hz***--
--constant FRAME_WIDTH : natural := 800;
--constant FRAME_HEIGHT : natural := 600;
--
--constant H_FP : natural := 40; --H front porch width (pixels)
--constant H_PW : natural := 128; --H sync pulse width (pixels)
--constant H_MAX : natural := 1056; --H total period (pixels)
--
--constant V_FP : natural := 1; --V front porch width (lines)
--constant V_PW : natural := 4; --V sync pulse width (lines)
--constant V_MAX : natural := 628; --V total period (lines)
--
--constant H_POL : std_logic := '1';
--constant V_POL : std_logic := '1';
--***1280x1024@60Hz***--
constant FRAME_WIDTH : natural := 1280;
constant FRAME_HEIGHT : natural := 1024;
constant H_FP : natural := 48; --H front porch width (pixels)
constant H_PW : natural := 112; --H sync pulse width (pixels)
constant H_MAX : natural := 1688; --H total period (pixels)
constant V_FP : natural := 1; --V front porch width (lines)
constant V_PW : natural := 3; --V sync pulse width (lines)
constant V_MAX : natural := 1066; --V total period (lines)
constant H_POL : std_logic := '1';
constant V_POL : std_logic := '1';
--***1920x1080@60Hz***--
--constant FRAME_WIDTH : natural := 1920;
--constant FRAME_HEIGHT : natural := 1080;
--
--constant H_FP : natural := 88; --H front porch width (pixels)
--constant H_PW : natural := 44; --H sync pulse width (pixels)
--constant H_MAX : natural := 2200; --H total period (pixels)
--
--constant V_FP : natural := 4; --V front porch width (lines)
--constant V_PW : natural := 5; --V sync pulse width (lines)
--constant V_MAX : natural := 1125; --V total period (lines)
--
--constant H_POL : std_logic := '1';
--constant V_POL : std_logic := '1';
------------------------------------------------------------------
-- Constants for setting the displayed logo size and coordinates
------------------------------------------------------------------
constant SZ_LOGO_WIDTH : natural := 335; -- Width of the logo frame
constant SZ_LOGO_HEIGHT : natural := 280; -- Height of the logo frame
constant FRM_LOGO_H_LOC : natural := 25; -- Starting horizontal location of the logo frame
constant FRM_LOGO_V_LOC : natural := 176; -- Starting vertical location of the logo frame
-- Logo frame limits
constant LOGO_LEFT : natural := FRM_LOGO_H_LOC - 1;
constant LOGO_RIGHT : natural := FRM_LOGO_H_LOC + SZ_LOGO_WIDTH + 1;
constant LOGO_TOP : natural := FRM_LOGO_V_LOC - 1;
constant LOGO_BOTTOM : natural := FRM_LOGO_V_LOC + SZ_LOGO_HEIGHT + 1;
------------------------------------------------------------------------------
-- Constants for setting the temperature display columns size and coordinates
-------------------------------------------------------------------------------
constant SZ_TEMP_WIDTH : natural := 50; -- Width of a Temp Column
constant SZ_TEMP_HEIGHT : natural := 472; -- Height of a Temp column
-- Starting Horizontal and Vertical locations of the three temperature columns
-- FPGA Temperature
constant FRM_XADC_TEMP_H_LOC : natural := 1050;
constant FRM_XADC_TEMP_V_LOC : natural := 80;
-- ADT7420 Temperature Sensor
constant FRM_ADT7420_TEMP_H_LOC : natural := 1125;
constant FRM_ADT7420_TEMP_V_LOC : natural := 80;
-- ADXL362 Accelerometer temperature
constant FRM_ADXL362_TEMP_H_LOC : natural := 1200;
constant FRM_ADXL362_TEMP_V_LOC : natural := 80;
-- Limits of the Temperature Column Frames
-- FPGA
constant XADC_TEMP_RIGHT : natural := FRM_XADC_TEMP_H_LOC + SZ_TEMP_WIDTH + 1;
constant XADC_TEMP_LEFT : natural := FRM_XADC_TEMP_H_LOC - 1;
constant XADC_TEMP_TOP : natural := FRM_XADC_TEMP_V_LOC - 1;
constant XADC_TEMP_BOTTOM : natural := FRM_XADC_TEMP_V_LOC + SZ_TEMP_HEIGHT + 1;
-- ADT7420
constant ADT7420_TEMP_RIGHT : natural := FRM_ADT7420_TEMP_H_LOC + SZ_TEMP_WIDTH + 1;
constant ADT7420_TEMP_LEFT : natural := FRM_ADT7420_TEMP_H_LOC - 1;
constant ADT7420_TEMP_TOP : natural := FRM_ADT7420_TEMP_V_LOC - 1;
constant ADT7420_TEMP_BOTTOM : natural := FRM_ADT7420_TEMP_V_LOC + SZ_TEMP_HEIGHT + 1;
--ADXL362
constant ADXL362_TEMP_RIGHT : natural := FRM_ADXL362_TEMP_H_LOC + SZ_TEMP_WIDTH + 1;
constant ADXL362_TEMP_LEFT : natural := FRM_ADXL362_TEMP_H_LOC - 1;
constant ADXL362_TEMP_TOP : natural := FRM_ADXL362_TEMP_V_LOC - 1;
constant ADXL362_TEMP_BOTTOM : natural := FRM_ADXL362_TEMP_V_LOC + SZ_TEMP_HEIGHT + 1;
----------------------------------------------------------------------------------------------------
-- Constants for setting size and location for TBOX - the white box holding the temperature columns
-----------------------------------------------------------------------------------------------------
constant SZ_TBOX_WIDTH : natural := 278; -- TBOX width
constant SZ_TBOX_HEIGHT : natural := 553; -- TBOX height
constant FRM_TBOX_H_LOC : natural := 985; -- TBOX starting horizontal location
constant FRM_TBOX_V_LOC : natural := 40; -- TBOX starting vertical location
-- TBOX frame limits
constant TBOX_LEFT : natural := FRM_TBOX_H_LOC - 1;
constant TBOX_RIGHT : natural := FRM_TBOX_H_LOC + SZ_TBOX_WIDTH + 1;
constant TBOX_TOP : natural := FRM_TBOX_V_LOC - 1;
constant TBOX_BOTTOM : natural := FRM_TBOX_V_LOC + SZ_TBOX_HEIGHT + 1;
---------------------------------------------------------------------
-- Constants for setting size and locations for RGB LED data display
-- Three columns: R, G and B are displayed for both LD16 and LD17
---------------------------------------------------------------------
constant SZ_RGB_WIDTH : natural := 50; -- width of one RGB column
constant SZ_RGB_HEIGHT : natural := 150; -- height of one RGB column
-- For one RGB LED for which RGB data is displayed, the R, G and B columns are horizontally aligned
-- The R, G and B columns are vertically aligned between the two LEDs
constant FRM_RGB_1_V_LOC : natural := 675; -- Starting V Location of the RGB LED LD16 Column
constant FRM_RGB_2_V_LOC : natural := FRM_RGB_1_V_LOC + SZ_RGB_HEIGHT + 15; -- Starting V Location of the RGB LED LD17 Column
constant FRM_RGB_R_H_LOC : natural := 1050; -- Starting H Location of the RGB LED RED Column
constant FRM_RGB_G_H_LOC : natural := 1125; -- Starting H Location of the RGB LED GREEN Column
constant FRM_RGB_B_H_LOC : natural := 1200; -- Starting H Location of the RGB LED BLUE Column
-- LD16 R, G, B Columns Top and Bottom limits
constant RGB1_COL_TOP : natural := FRM_RGB_1_V_LOC - 1;
constant RGB1_COL_BOTTOM : natural := FRM_RGB_1_V_LOC + SZ_RGB_HEIGHT + 1;
-- LD17 R, G, B Columns Top and Bottom limits
constant RGB2_COL_TOP : natural := FRM_RGB_2_V_LOC - 1;
constant RGB2_COL_BOTTOM : natural := FRM_RGB_2_V_LOC + SZ_RGB_HEIGHT + 1;
-- R columns Left and Right Location limits
constant RGB_R_COL_LEFT : natural := FRM_RGB_R_H_LOC - 1;
constant RGB_R_COL_RIGHT : natural := FRM_RGB_R_H_LOC + SZ_RGB_WIDTH + 1;
-- G columns Left and Right Location limits
constant RGB_G_COL_LEFT : natural := FRM_RGB_G_H_LOC - 1;
constant RGB_G_COL_RIGHT : natural := FRM_RGB_G_H_LOC + SZ_RGB_WIDTH + 1;
-- B columns Left and Right Location limits
constant RGB_B_COL_LEFT : natural := FRM_RGB_B_H_LOC - 1;
constant RGB_B_COL_RIGHT : natural := FRM_RGB_B_H_LOC + SZ_RGB_WIDTH + 1;
--------------------------------------------------------------------------------------------
-- Constants for setting size and location for LBOX - box for displaying the RGB LEDs color
--------------------------------------------------------------------------------------------
constant SZ_LBOX_WIDTH : natural := 278; -- LBOX width
constant SZ_LBOX_HEIGHT : natural := 375; -- LBOX Height
constant FRM_LBOX_H_LOC : natural := 985; -- LBOX starting horizontal location
constant FRM_LBOX_V_LOC : natural := 615; -- LBOX starting vertical location
-- LBOX frame limits
constant LBOX_LEFT : natural := FRM_LBOX_H_LOC - 1;
constant LBOX_RIGHT : natural := FRM_LBOX_H_LOC + SZ_LBOX_WIDTH + 1;
constant LBOX_TOP : natural := FRM_LBOX_V_LOC - 1;
constant LBOX_BOTTOM : natural := FRM_LBOX_V_LOC + SZ_LBOX_HEIGHT + 1;
-----------------------------------------------------------------------------
-- Constants for setting size and location for the Microphone signal display
-----------------------------------------------------------------------------
constant SZ_MIC_WIDTH : natural := 915; -- Width of the Microphone frame
constant SZ_MIC_HEIGHT : natural := 375; -- Height of the Microphone frame
constant FRM_MIC_H_LOC : natural := 25; -- Microphone frame starting horizontal location
constant FRM_MIC_V_LOC : natural := 615; -- Microphone frame starting vertical location
-- Microphone display frame limits
constant MIC_LEFT : natural := FRM_MIC_H_LOC - 1;
constant MIC_RIGHT : natural := FRM_MIC_H_LOC + SZ_MIC_WIDTH + 1;
constant MIC_TOP : natural := FRM_MIC_V_LOC - 1;
constant MIC_BOTTOM : natural := FRM_MIC_V_LOC + SZ_MIC_HEIGHT + 1;
-------------------------------------------------------------------------
-- Constants for setting size and location for the Accelerometer display
--------------------------------------------------------------------------
-- Accelerometer X and Y data is scaled to 0-511 pixels, such as 0: -1g, 255: 0g, 511: +1g
constant SZ_ACL_XY_WIDTH : natural := 511; -- Width of the Accelerometer frame X-Y Region
constant SZ_ACL_MAG_WIDTH : natural := 45; -- Width of the Accelerometer frame Magnitude Region
constant SZ_ACL_WIDTH : natural := SZ_ACL_XY_WIDTH + SZ_ACL_MAG_WIDTH; -- Width of the entire Accelerometer frame
constant SZ_ACL_HEIGHT : natural := 511; -- Height of the Accelerometer frame
constant FRM_ACL_H_LOC : natural := 385; -- Accelerometer frame X-Y region starting horizontal location
constant FRM_ACL_MAG_LOC : natural := FRM_ACL_H_LOC + SZ_ACL_MAG_WIDTH; -- Accelerometer frame Magnitude Region starting horizontal location
constant FRM_ACL_V_LOC : natural := 80; -- Accelerometer frame starting vertical location
-- Accelerometer Display frame limits
constant ACL_LEFT : natural := FRM_ACL_H_LOC - 1;
constant ACL_RIGHT : natural := FRM_ACL_H_LOC + SZ_ACL_WIDTH + 1;
constant ACL_TOP : natural := FRM_ACL_V_LOC - 1;
constant ACL_BOTTOM : natural := FRM_ACL_V_LOC + SZ_ACL_HEIGHT + 1;
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- VGA Controller specific signals: Counters, Sync, R, G, B
-------------------------------------------------------------------------
-- Pixel clock, in this case 108 MHz
signal pxl_clk : std_logic;
-- The active signal is used to signal the active region of the screen (when not blank)
signal active : std_logic;
-- Horizontal and Vertical counters
signal h_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
signal v_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
-- Pipe Horizontal and Vertical Counters
signal h_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0');
signal v_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0');
-- Horizontal and Vertical Sync
signal h_sync_reg : std_logic := not(H_POL);
signal v_sync_reg : std_logic := not(V_POL);
-- Pipe Horizontal and Vertical Sync
signal h_sync_reg_dly : std_logic := not(H_POL);
signal v_sync_reg_dly : std_logic := not(V_POL);
-- VGA R, G and B signals coming from the main multiplexers
signal vga_red_cmb : std_logic_vector(3 downto 0);
signal vga_green_cmb : std_logic_vector(3 downto 0);
signal vga_blue_cmb : std_logic_vector(3 downto 0);
--The main VGA R, G and B signals, validated by active
signal vga_red : std_logic_vector(3 downto 0);
signal vga_green : std_logic_vector(3 downto 0);
signal vga_blue : std_logic_vector(3 downto 0);
-- Register VGA R, G and B signals
signal vga_red_reg : std_logic_vector(3 downto 0) := (others =>'0');
signal vga_green_reg : std_logic_vector(3 downto 0) := (others =>'0');
signal vga_blue_reg : std_logic_vector(3 downto 0) := (others =>'0');
-------------------------------------------------------------------------
-- Signals for registering the inputs
-------------------------------------------------------------------------
signal RGB_LED_RED_REG : std_logic_vector (4 downto 0);
signal RGB_LED_BLUE_REG : std_logic_vector (4 downto 0);
signal RGB_LED_GREEN_REG : std_logic_vector (4 downto 0);
signal XADC_TEMP_VALUE_I_REG : std_logic_vector (11 downto 0);
signal ADT7420_TEMP_VALUE_I_REG : std_logic_vector (12 downto 0);
signal ADXL362_TEMP_VALUE_I_REG : std_logic_vector (11 downto 0);
signal ACCEL_RADIUS_REG : STD_LOGIC_VECTOR (11 downto 0);
signal LEVEL_THRESH_REG : STD_LOGIC_VECTOR (11 downto 0);
signal ACL_X_IN_REG : STD_LOGIC_VECTOR (8 downto 0);
signal ACL_Y_IN_REG : STD_LOGIC_VECTOR (8 downto 0);
signal ACL_MAG_IN_REG : STD_LOGIC_VECTOR (11 downto 0);
signal MIC_M_DATA_I_REG : STD_LOGIC;
signal MOUSE_X_POS_REG : std_logic_vector (11 downto 0);
signal MOUSE_Y_POS_REG : std_logic_vector (11 downto 0);
signal MOUSE_LEFT_BUTTON_REG : std_logic;
-----------------------------------------------------------
-- Signals for generating the background (moving colorbar)
-----------------------------------------------------------
signal cntDyn : integer range 0 to 2**28-1; -- counter for generating the colorbar
signal intHcnt : integer range 0 to H_MAX - 1;
signal intVcnt : integer range 0 to V_MAX - 1;
-- Colorbar red, greeen and blue signals
signal bg_red : std_logic_vector(3 downto 0);
signal bg_blue : std_logic_vector(3 downto 0);
signal bg_green : std_logic_vector(3 downto 0);
-- Pipe the colorbar red, green and blue signals
signal bg_red_dly : std_logic_vector(3 downto 0) := (others => '0');
signal bg_green_dly : std_logic_vector(3 downto 0) := (others => '0');
signal bg_blue_dly : std_logic_vector(3 downto 0) := (others => '0');
-------------------------------------------------------------------------
-- Interconnection signals for the displaying components
-------------------------------------------------------------------------
-- Digilent and Analog Devices logo display signals
signal logo_red : std_logic_vector(3 downto 0);
signal logo_blue : std_logic_vector(3 downto 0);
signal logo_green : std_logic_vector(3 downto 0);
-- FPGA Temperature Display Signals
signal xadc_temp_red : std_logic_vector (3 downto 0);
signal xadc_temp_green : std_logic_vector (3 downto 0);
signal xadc_temp_blue : std_logic_vector (3 downto 0);
-- ADT740 Temperature Sensor Display Signals
signal adt7420_temp_red : std_logic_vector (3 downto 0);
signal adt7420_temp_green : std_logic_vector (3 downto 0);
signal adt7420_temp_blue : std_logic_vector (3 downto 0);
-- ADXL362 Accelerometer Temperature Sensor Display Signals
signal adxl362_temp_red : std_logic_vector (3 downto 0);
signal adxl362_temp_green : std_logic_vector (3 downto 0);
signal adxl362_temp_blue : std_logic_vector (3 downto 0);
-- TBOX (frame holding the temperature columns) display signals
signal tbox_red : std_logic_vector(3 downto 0);
signal tbox_blue : std_logic_vector(3 downto 0);
signal tbox_green : std_logic_vector(3 downto 0);
-- Microphone data display signals
signal mic_red : std_logic_vector(3 downto 0);
signal mic_blue : std_logic_vector(3 downto 0);
signal mic_green : std_logic_vector(3 downto 0);
-- RGB LED Red, Green and Blue Display signals for the three columns
signal rgb_r_red_col : std_logic_vector(3 downto 0); -- Red signal for the Red column
signal rgb_g_red_col : std_logic_vector(3 downto 0); -- Green signal for the Red column
signal rgb_b_red_col : std_logic_vector(3 downto 0); -- Blue signal for the Red column
signal rgb_r_green_col : std_logic_vector(3 downto 0); -- Red signal for the Green column
signal rgb_g_green_col : std_logic_vector(3 downto 0); -- Green signal for the Green column
signal rgb_b_green_col : std_logic_vector(3 downto 0); -- Blue signal for the Green column
signal rgb_r_blue_col : std_logic_vector(3 downto 0); -- Red signal for the Blue column
signal rgb_g_blue_col : std_logic_vector(3 downto 0); -- Green signal for the Blue column
signal rgb_b_blue_col : std_logic_vector(3 downto 0); -- Blue signal for the Blue column
--Lbox - frame holding the RGB LED columns display signals
signal lbox_red : std_logic_vector (3 downto 0);
signal lbox_green : std_logic_vector (3 downto 0);
signal lbox_blue : std_logic_vector (3 downto 0);
-- Accelerometer display dignals
signal acl_red : std_logic_vector(3 downto 0);
signal acl_blue : std_logic_vector(3 downto 0);
signal acl_green : std_logic_vector(3 downto 0);
-- Mouse cursor display signals
signal mouse_cursor_red : std_logic_vector (3 downto 0) := (others => '0');
signal mouse_cursor_blue : std_logic_vector (3 downto 0) := (others => '0');
signal mouse_cursor_green : std_logic_vector (3 downto 0) := (others => '0');
-- Mouse cursor enable display signals
signal enable_mouse_display: std_logic;
-- Overlay display signal
signal overlay_en : std_logic;
---------------------------------------------------------------------------------
-- Pipe all of the interconnection signals coming from the displaying components
---------------------------------------------------------------------------------
-- Registered Digilent and Analog Devices logo display signals
signal logo_red_dly : std_logic_vector(3 downto 0);
signal logo_blue_dly : std_logic_vector(3 downto 0);
signal logo_green_dly : std_logic_vector(3 downto 0);
-- Registered FPGA Temperature Display Signals
signal xadc_temp_red_dly : std_logic_vector (3 downto 0);
signal xadc_temp_green_dly : std_logic_vector (3 downto 0);
signal xadc_temp_blue_dly : std_logic_vector (3 downto 0);
-- Registered ADT740 Temperature Sensor Display Signals
signal adt7420_temp_red_dly : std_logic_vector (3 downto 0);
signal adt7420_temp_green_dly : std_logic_vector (3 downto 0);
signal adt7420_temp_blue_dly : std_logic_vector (3 downto 0);
-- Registered ADXL362 Accelerometer Temperature Sensor Display Signals
signal adxl362_temp_red_dly : std_logic_vector (3 downto 0);
signal adxl362_temp_green_dly : std_logic_vector (3 downto 0);
signal adxl362_temp_blue_dly : std_logic_vector (3 downto 0);
-- TBOX (frame holding the temperature columns) color is white,
-- therefore TBOX signals will not be registered again
-- Registered Microphone data display signals
signal mic_red_dly : std_logic_vector(3 downto 0);
signal mic_blue_dly : std_logic_vector(3 downto 0);
signal mic_green_dly : std_logic_vector(3 downto 0);
-- Registered RGB LED Red, Green and Blue Display signals for the three columns
signal rgb_r_red_col_dly : std_logic_vector(3 downto 0); -- Red signal for the Red column
signal rgb_g_red_col_dly : std_logic_vector(3 downto 0); -- Green signal for the Red column
signal rgb_b_red_col_dly : std_logic_vector(3 downto 0); -- Blue signal for the Red column
signal rgb_r_green_col_dly : std_logic_vector(3 downto 0); -- Red signal for the Green column
signal rgb_g_green_col_dly : std_logic_vector(3 downto 0); -- Green signal for the Green column
signal rgb_b_green_col_dly : std_logic_vector(3 downto 0); -- Blue signal for the Green column
signal rgb_r_blue_col_dly : std_logic_vector(3 downto 0); -- Red signal for the Blue column
signal rgb_g_blue_col_dly : std_logic_vector(3 downto 0); -- Green signal for the Blue column
signal rgb_b_blue_col_dly : std_logic_vector(3 downto 0); -- Blue signal for the Blue column
-- Lbox (frame holding the RGB LED columns) signals will be in fact
-- the incoming RGB LED signals, therefore will not be registered again
-- Registered Accelerometer display dignals
signal acl_red_dly : std_logic_vector(3 downto 0);
signal acl_blue_dly : std_logic_vector(3 downto 0);
signal acl_green_dly : std_logic_vector(3 downto 0);
-- Registered Mouse cursor display signals
signal mouse_cursor_red_dly : std_logic_vector (3 downto 0) := (others => '0');
signal mouse_cursor_blue_dly : std_logic_vector (3 downto 0) := (others => '0');
signal mouse_cursor_green_dly : std_logic_vector (3 downto 0) := (others => '0');
-- Registered Mouse cursor enable display signals
signal enable_mouse_display_dly : std_logic;
-- Registered Overlay display signal
signal overlay_en_dly : std_logic;
begin
------------------------------------
-- Generate the 108 MHz pixel clock
------------------------------------
Inst_PxlClkGen: PxlClkGen
port map
(-- Clock in ports
CLK_IN1 => CLK_I,
-- Clock out ports
CLK_OUT1 => pxl_clk,
-- Status and control signals
LOCKED => open
);
---------------------------------------------------------------
-- Generate Horizontal, Vertical counters and the Sync signals
---------------------------------------------------------------
-- Horizontal counter
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_cntr_reg = (H_MAX - 1)) then
h_cntr_reg <= (others =>'0');
else
h_cntr_reg <= h_cntr_reg + 1;
end if;
end if;
end process;
-- Vertical counter
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if ((h_cntr_reg = (H_MAX - 1)) and (v_cntr_reg = (V_MAX - 1))) then
v_cntr_reg <= (others =>'0');
elsif (h_cntr_reg = (H_MAX - 1)) then
v_cntr_reg <= v_cntr_reg + 1;
end if;
end if;
end process;
-- Horizontal sync
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_cntr_reg >= (H_FP + FRAME_WIDTH - 1)) and (h_cntr_reg < (H_FP + FRAME_WIDTH + H_PW - 1)) then
h_sync_reg <= H_POL;
else
h_sync_reg <= not(H_POL);
end if;
end if;
end process;
-- Vertical sync
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (v_cntr_reg >= (V_FP + FRAME_HEIGHT - 1)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT + V_PW - 1)) then
v_sync_reg <= V_POL;
else
v_sync_reg <= not(V_POL);
end if;
end if;
end process;
--------------------
-- The active
--------------------
-- active signal
active <= '1' when h_cntr_reg_dly < FRAME_WIDTH and v_cntr_reg_dly < FRAME_HEIGHT
else '0';
--------------------
-- Register Inputs
--------------------
register_inputs: process (pxl_clk, v_sync_reg)
begin
if (rising_edge(pxl_clk)) then
if v_sync_reg = V_POL then -- All of the signals, except the incoming microphone data
-- have lover frequencies than the vertical refresh rate,
-- therefore will be registered in the blanking area
RGB_LED_RED_REG <= RGB_LED_RED (4 downto 0); -- The RGB LEDs are turned on at a lower than maximum intensity,
RGB_LED_GREEN_REG <= RGB_LED_GREEN (4 downto 0); -- therefore the five least significant bits are used only
RGB_LED_BLUE_REG <= RGB_LED_BLUE (4 downto 0);
XADC_TEMP_VALUE_I_REG <= XADC_TEMP_VALUE_I;
ADT7420_TEMP_VALUE_I_REG <= ADT7420_TEMP_VALUE_I;
ADXL362_TEMP_VALUE_I_REG <= ADXL362_TEMP_VALUE_I;
ACCEL_RADIUS_REG <= ACCEL_RADIUS;
LEVEL_THRESH_REG <= LEVEL_THRESH;
ACL_X_IN_REG <= ACL_X_IN;
ACL_Y_IN_REG <= ACL_Y_IN;
ACL_MAG_IN_REG <= ACL_MAG_IN;
MOUSE_X_POS_REG <= MOUSE_X_POS;
MOUSE_Y_POS_REG <= MOUSE_Y_POS;
MOUSE_LEFT_BUTTON_REG <= MOUSE_LEFT_BUTTON_REG;
end if;
-- Incoming Microphone data rate is faster than VSYNC, therefore is registered on the pixel clock
MIC_M_DATA_I_REG <= MIC_M_DATA_I;
end if;
end process register_inputs;
--------------------------
-- Logo display instance
--------------------------
Inst_LogoDisplay: LogoDisplay
GENERIC MAP(
X_START => FRM_LOGO_H_LOC,
Y_START => FRM_LOGO_V_LOC
)
PORT MAP(
CLK_I => pxl_clk,
H_COUNT_I => h_cntr_reg,
V_COUNT_I => v_cntr_reg,
RED_O => logo_red,
BLUE_O => logo_blue,
GREEN_O => logo_green
);
--------------------------------
-- Temperature display instances
---------------------------------
----------------------------------------------------
-- FPGA Temperature - from the XADC temperature data
-----------------------------------------------------
Inst_XadcTempDisplay: TempDisplay
GENERIC MAP(
X_TMP_COL_WIDTH => SZ_TEMP_WIDTH, -- width of the TEMP column
Y_TMP_COL_HEIGHT => SZ_TEMP_HEIGHT,-- height of the TEMP column
X_TMP_H_LOC => FRM_XADC_TEMP_H_LOC, -- X Location of the FPGA TEMP Column
Y_TMP_V_LOC => FRM_XADC_TEMP_V_LOC, -- Y Location of the FPGA TEMP Column
INPUT_DATA_WIDTH => 12,
TMP_TYPE => "XADC"
)
PORT MAP (
CLK_I => pxl_clk,
TEMP_IN => XADC_TEMP_VALUE_I_REG,
H_COUNT_I => h_cntr_reg,
V_COUNT_I => v_cntr_reg,
-- Temperature Red, Green and Blue signals
TEMP_R_OUT => xadc_temp_red,
TEMP_G_OUT => xadc_temp_green,
TEMP_B_OUT => xadc_temp_blue
);
-------------------------------------------------
-- ADT740 onboard temperature sensor temperature
-------------------------------------------------
Inst_Adt7420TempDisplay: TempDisplay
GENERIC MAP (
X_TMP_COL_WIDTH => SZ_TEMP_WIDTH, -- width of the TEMP column
Y_TMP_COL_HEIGHT => SZ_TEMP_HEIGHT,-- height of the TEMP column
X_TMP_H_LOC => FRM_ADT7420_TEMP_H_LOC, -- X Location of the Temp Sensor Column
Y_TMP_V_LOC => FRM_ADT7420_TEMP_V_LOC, -- Y Location of the Temp Sensor Column
INPUT_DATA_WIDTH => 13,
TMP_TYPE => "TEMP_ACC"
)
PORT MAP (
CLK_I => pxl_clk,
TEMP_IN => ADT7420_TEMP_VALUE_I_REG,
H_COUNT_I => h_cntr_reg,
V_COUNT_I => v_cntr_reg,
-- Temperature Red, Green and Blue signals
TEMP_R_OUT => adt7420_temp_red,
TEMP_G_OUT => adt7420_temp_green,
TEMP_B_OUT => adt7420_temp_blue
);
----------------------------------------------------
-- ADXL362 onboard accelerometer temperature sensor
----------------------------------------------------
Inst_Adxl362TempDisplay: TempDisplay
GENERIC MAP(
X_TMP_COL_WIDTH => SZ_TEMP_WIDTH, -- width of the TEMP column
Y_TMP_COL_HEIGHT => SZ_TEMP_HEIGHT,-- height of the TEMP column
X_TMP_H_LOC => FRM_ADXL362_TEMP_H_LOC, -- X Location of the ACC Temp Column
Y_TMP_V_LOC => FRM_ADXL362_TEMP_V_LOC, -- Y Location of the Acc Temp Column
INPUT_DATA_WIDTH => 12,
TMP_TYPE => "TEMP_ACC"
)
PORT MAP (
CLK_I => pxl_clk,
TEMP_IN => ADXL362_TEMP_VALUE_I_REG,
H_COUNT_I => h_cntr_reg,
V_COUNT_I => v_cntr_reg,
-- Temperature Red, Green and Blue signals
TEMP_R_OUT => adxl362_temp_red,
TEMP_G_OUT => adxl362_temp_green,
TEMP_B_OUT => adxl362_temp_blue
);
-----------------------------
-- RGB LED display instance
-----------------------------
Inst_RGBLedDisplay: RgbLedDisplay
GENERIC MAP(
X_RGB_COL_WIDTH => SZ_RGB_WIDTH, -- width of one RGB column
Y_RGB_COL_HEIGHT => SZ_RGB_HEIGHT,-- height of one RGB column
X_RGB_R_LOC => FRM_RGB_R_H_LOC, -- X Location of the RGB LED RED Column
X_RGB_G_LOC => FRM_RGB_G_H_LOC, -- X Location of the RGB LED GREEN Column
X_RGB_B_LOC => FRM_RGB_B_H_LOC, -- X Location of the RGB LED BLUE Column
Y_RGB_1_LOC => FRM_RGB_1_V_LOC, -- Y Location of the RGB LED LD16 Column
Y_RGB_2_LOC => FRM_RGB_2_V_LOC -- Y Location of the RGB LED LD17 Column
)
PORT MAP(
pxl_clk => pxl_clk,
RGB_LED_RED => RGB_LED_RED_REG,
RGB_LED_GREEN => RGB_LED_GREEN_REG,
RGB_LED_BLUE => RGB_LED_BLUE_REG,
H_COUNT_I => h_cntr_reg,
V_COUNT_I => v_cntr_reg,
-- RGB LED RED signal Data for the three columns
RGB_LED_R_RED_COL => rgb_r_red_col,
RGB_LED_R_GREEN_COL => rgb_r_green_col,
RGB_LED_R_BLUE_COL => rgb_r_blue_col,
-- RGB LED GREEN signal Data for the three columns
RGB_LED_G_RED_COL => rgb_g_red_col,
RGB_LED_G_GREEN_COL => rgb_g_green_col,
RGB_LED_G_BLUE_COL => rgb_g_blue_col,
-- RGB LED BLUE signal Data for the three columns
RGB_LED_B_RED_COL => rgb_b_red_col,
RGB_LED_B_GREEN_COL => rgb_b_green_col,
RGB_LED_B_BLUE_COL => rgb_b_blue_col
);
--------------------------------------
-- Microphone signal display instance
--------------------------------------
Inst_MicDisplay: MicDisplay
GENERIC MAP(
X_WIDTH => SZ_MIC_WIDTH,
Y_HEIGHT => SZ_MIC_HEIGHT,
X_START => FRM_MIC_H_LOC,
Y_START => FRM_MIC_V_LOC,
PXLCLK_FREQ_HZ => 108000000,
H_MAX => H_MAX,
SAMPLE_RATE_DIV => 4096,
BG_COLOR => x"FFF",
ACTIVE_COLOR => x"008"
)
PORT MAP(
CLK_I => pxl_clk,
SYSCLK => CLK_I,
MIC_M_DATA_I => MIC_M_DATA_I_REG,
MIC_M_CLK_RISING => MIC_M_CLK_RISING,
H_COUNT_I => h_cntr_reg,
V_COUNT_I => v_cntr_reg,
RED_O => mic_red,
GREEN_O => mic_green,
BLUE_O => mic_blue
);
----------------------------------
-- Accelerometer display instance
----------------------------------
Inst_AccelDisplay: AccelDisplay
GENERIC MAP
(
X_XY_WIDTH => SZ_ACL_XY_WIDTH, -- Width of the Accelerometer frame X-Y region
X_MAG_WIDTH => SZ_ACL_MAG_WIDTH, -- Width of the Accelerometer frame Magnitude region
Y_HEIGHT => SZ_ACL_HEIGHT, -- Height of the Accelerometer frame
X_START => FRM_ACL_H_LOC, -- Accelerometer frame X-Y region starting horizontal location
Y_START => FRM_ACL_V_LOC, -- Accelerometer frame starting vertical location
BG_COLOR => x"FFF", -- White
ACTIVE_COLOR => x"0F0", -- Green
WARNING_COLOR => x"F00" -- Red
)
PORT MAP
(
CLK_I => pxl_clk,
ACCEL_X_I => ACL_X_IN_REG,
ACCEL_Y_I => ACL_Y_IN_REG,
ACCEL_MAG_I => ACL_MAG_IN_REG(8 DOWNTO 0), -- only 9 bits are taken into account, data is scaled between 0-500
H_COUNT_I => h_cntr_reg,
V_COUNT_I => v_cntr_reg,
ACCEL_RADIUS => ACCEL_RADIUS_REG,
LEVEL_THRESH => LEVEL_THRESH_REG,
RED_O => acl_red,
BLUE_O => acl_blue,
GREEN_O => acl_green
);
----------------------------------
-- Mouse Cursor display instance
----------------------------------
Inst_MouseDisplay: MouseDisplay
PORT MAP
(
pixel_clk => pxl_clk,
xpos => MOUSE_X_POS_REG,
ypos => MOUSE_Y_POS_REG,
hcount => h_cntr_reg,
vcount => v_cntr_reg,
enable_mouse_display_out => enable_mouse_display,
red_out => mouse_cursor_red,
green_out => mouse_cursor_green,
blue_out => mouse_cursor_blue
);
----------------------------------
-- Overlay display instance
----------------------------------
Inst_OverlayCtrl: OverlayCtl
PORT MAP
(
CLK_I => pxl_clk,
VSYNC_I => v_sync_reg,
ACTIVE_I => active,
OVERLAY_O => overlay_en
);
---------------------------------------
-- Generate moving colorbar background
---------------------------------------
process(pxl_clk)
begin
if(rising_edge(pxl_clk)) then
cntdyn <= cntdyn + 1;
end if;
end process;
intHcnt <= conv_integer(h_cntr_reg);
intVcnt <= conv_integer(v_cntr_reg);
bg_red <= conv_std_logic_vector((-intvcnt - inthcnt - cntDyn/2**20),8)(7 downto 4);
bg_green <= conv_std_logic_vector((inthcnt - cntDyn/2**20),8)(7 downto 4);
bg_blue <= conv_std_logic_vector((intvcnt - cntDyn/2**20),8)(7 downto 4);
---------------------------------------------------------------------------
-- Generate LBOX (the frame that holds the RGB LED column) signals
-- LBOX signals are, in fact, the MSB of the incoming RBG LED data signals
---------------------------------------------------------------------------
lbox_red <= RGB_LED_RED_REG(4 downto 1);
lbox_green <= RGB_LED_GREEN_REG(4 downto 1);
lbox_blue <= RGB_LED_BLUE_REG(4 downto 1);
----------------------------------------------------------------------
-- TBOX (the frame that holds the temperature columns) color is white
----------------------------------------------------------------------
tbox_red <= X"F";
tbox_blue <= X"F";
tbox_green <= X"F";
---------------------------------------------------------------------------------------------------
-- Register Outputs coming from the displaying components and the horizontal and vertical counters
---------------------------------------------------------------------------------------------------
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
logo_red_dly <= logo_red;
logo_green_dly <= logo_green;
logo_blue_dly <= logo_blue;
xadc_temp_red_dly <= xadc_temp_red;
xadc_temp_green_dly <= xadc_temp_green;
xadc_temp_blue_dly <= xadc_temp_blue;
adt7420_temp_red_dly <= adt7420_temp_red;
adt7420_temp_green_dly <= adt7420_temp_green;
adt7420_temp_blue_dly <= adt7420_temp_blue;
adxl362_temp_red_dly <= adxl362_temp_red;
adxl362_temp_green_dly <= adxl362_temp_green;
adxl362_temp_blue_dly <= adxl362_temp_blue;
rgb_r_red_col_dly <= rgb_r_red_col;
rgb_g_red_col_dly <= rgb_g_red_col;
rgb_b_red_col_dly <= rgb_b_red_col;
rgb_r_green_col_dly <= rgb_r_green_col;
rgb_g_green_col_dly <= rgb_g_green_col;
rgb_b_green_col_dly <= rgb_b_green_col;
rgb_r_blue_col_dly <= rgb_r_blue_col;
rgb_g_blue_col_dly <= rgb_g_blue_col;
rgb_b_blue_col_dly <= rgb_b_blue_col;
mic_red_dly <= mic_red;
mic_green_dly <= mic_green;
mic_blue_dly <= mic_blue;
acl_red_dly <= acl_red;
acl_green_dly <= acl_green;
acl_blue_dly <= acl_blue;
bg_red_dly <= bg_red;
bg_green_dly <= bg_green;
bg_blue_dly <= bg_blue;
mouse_cursor_red_dly <= mouse_cursor_red;
mouse_cursor_blue_dly <= mouse_cursor_blue;
mouse_cursor_green_dly <= mouse_cursor_green;
enable_mouse_display_dly <= enable_mouse_display;
overlay_en_dly <= overlay_en;
h_cntr_reg_dly <= h_cntr_reg;
v_cntr_reg_dly <= v_cntr_reg;
end if;
end process;
-------------------------------------------------------------
-- Main Multiplexers for the VGA Red, Green and Blue signals
-------------------------------------------------------------
----------
-- Red
----------
vga_red <= -- Mouse_cursor_display is on the top of others
mouse_cursor_red_dly when enable_mouse_display_dly = '1'
else
-- Overlay display is black
x"0" when overlay_en_dly = '1'
else
-- logo display
logo_red_dly when h_cntr_reg_dly > LOGO_LEFT and h_cntr_reg_dly < LOGO_RIGHT
and v_cntr_reg_dly < LOGO_BOTTOM and v_cntr_reg_dly > LOGO_TOP
else
-- Temperature display
xadc_temp_red_dly when h_cntr_reg_dly > XADC_TEMP_LEFT and h_cntr_reg_dly < XADC_TEMP_RIGHT
and v_cntr_reg_dly > XADC_TEMP_TOP and v_cntr_reg_dly < XADC_TEMP_BOTTOM
else
adt7420_temp_red_dly when h_cntr_reg_dly > ADT7420_TEMP_LEFT and h_cntr_reg_dly < ADT7420_TEMP_RIGHT
and v_cntr_reg_dly > ADT7420_TEMP_TOP and v_cntr_reg_dly < ADT7420_TEMP_BOTTOM
else
adxl362_temp_red_dly when h_cntr_reg_dly > ADXL362_TEMP_LEFT and h_cntr_reg_dly < ADXL362_TEMP_RIGHT
and v_cntr_reg_dly > ADXL362_TEMP_TOP and v_cntr_reg_dly < ADXL362_TEMP_BOTTOM
else
-- TBOX display
tbox_red when h_cntr_reg_dly > TBOX_LEFT and h_cntr_reg_dly < TBOX_RIGHT
and v_cntr_reg_dly < TBOX_BOTTOM and v_cntr_reg_dly > TBOX_TOP
else
-- RGB Led display
rgb_r_red_col_dly when (h_cntr_reg_dly > RGB_R_COL_LEFT and h_cntr_reg_dly < RGB_R_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
rgb_r_green_col_dly when (h_cntr_reg_dly > RGB_G_COL_LEFT and h_cntr_reg_dly < RGB_G_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP - 1 and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
rgb_r_blue_col_dly when (h_cntr_reg_dly > RGB_B_COL_LEFT and h_cntr_reg_dly < RGB_B_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
-- LBOX display
lbox_red when h_cntr_reg_dly > LBOX_LEFT and h_cntr_reg_dly < LBOX_RIGHT
and v_cntr_reg_dly < LBOX_BOTTOM and v_cntr_reg_dly > LBOX_TOP
else
-- Microphone data display
mic_red_dly when h_cntr_reg_dly > MIC_LEFT and h_cntr_reg_dly < MIC_RIGHT
and v_cntr_reg_dly > MIC_TOP and v_cntr_reg_dly < MIC_BOTTOM
else
-- Accelerometer display
acl_red_dly when h_cntr_reg_dly > ACL_LEFT and h_cntr_reg_dly < ACL_RIGHT
and v_cntr_reg_dly > ACL_TOP and v_cntr_reg_dly < ACL_BOTTOM
else
-- Colorbar will be on the backround
bg_red_dly;
-----------
-- Green
-----------
vga_green <= -- Mouse_cursor_display is on the top of others
mouse_cursor_green_dly when enable_mouse_display_dly = '1'
else
-- Overlay display is black
x"0" when overlay_en_dly = '1'
else
-- logo display
logo_green_dly when h_cntr_reg_dly > LOGO_LEFT and h_cntr_reg_dly < LOGO_RIGHT
and v_cntr_reg_dly < LOGO_BOTTOM and v_cntr_reg_dly > LOGO_TOP
else
-- Temperature display
xadc_temp_green_dly when h_cntr_reg_dly > XADC_TEMP_LEFT and h_cntr_reg_dly < XADC_TEMP_RIGHT
and v_cntr_reg_dly > XADC_TEMP_TOP and v_cntr_reg_dly < XADC_TEMP_BOTTOM
else
adt7420_temp_green_dly when h_cntr_reg_dly > ADT7420_TEMP_LEFT and h_cntr_reg_dly < ADT7420_TEMP_RIGHT
and v_cntr_reg_dly > ADT7420_TEMP_TOP and v_cntr_reg_dly < ADT7420_TEMP_BOTTOM
else
adxl362_temp_green_dly when h_cntr_reg_dly > ADXL362_TEMP_LEFT and h_cntr_reg_dly < ADXL362_TEMP_RIGHT
and v_cntr_reg_dly > ADXL362_TEMP_TOP and v_cntr_reg_dly < ADXL362_TEMP_BOTTOM
else
-- TBOX display
tbox_green when h_cntr_reg_dly > TBOX_LEFT and h_cntr_reg_dly < TBOX_RIGHT
and v_cntr_reg_dly < TBOX_BOTTOM and v_cntr_reg_dly > TBOX_TOP
else
-- RGB Led display
rgb_g_red_col_dly when (h_cntr_reg_dly > RGB_R_COL_LEFT and h_cntr_reg_dly < RGB_R_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
rgb_g_green_col_dly when (h_cntr_reg_dly > RGB_G_COL_LEFT and h_cntr_reg_dly < RGB_G_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP - 1 and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
rgb_g_blue_col_dly when (h_cntr_reg_dly > RGB_B_COL_LEFT and h_cntr_reg_dly < RGB_B_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
-- LBOX display
lbox_green when h_cntr_reg_dly > LBOX_LEFT and h_cntr_reg_dly < LBOX_RIGHT
and v_cntr_reg_dly < LBOX_BOTTOM and v_cntr_reg_dly > LBOX_TOP
else
-- Microphone data display
mic_green_dly when h_cntr_reg_dly > MIC_LEFT and h_cntr_reg_dly < MIC_RIGHT
and v_cntr_reg_dly > MIC_TOP and v_cntr_reg_dly < MIC_BOTTOM
else
-- Accelerometer display
acl_green_dly when h_cntr_reg_dly > ACL_LEFT and h_cntr_reg_dly < ACL_RIGHT
and v_cntr_reg_dly > ACL_TOP and v_cntr_reg_dly < ACL_BOTTOM
else
-- Colorbar will be on the backround
bg_green_dly;
-----------
-- Blue
-----------
vga_blue <= -- Mouse_cursor_display is on the top of others
mouse_cursor_blue_dly when enable_mouse_display_dly = '1'
else
-- Overlay display is black
x"0" when overlay_en_dly = '1'
else
-- logo display
logo_blue_dly when h_cntr_reg_dly > LOGO_LEFT and h_cntr_reg_dly < LOGO_RIGHT
and v_cntr_reg_dly < LOGO_BOTTOM and v_cntr_reg_dly > LOGO_TOP
else
-- Temperature display
xadc_temp_blue_dly when h_cntr_reg_dly > XADC_TEMP_LEFT and h_cntr_reg_dly < XADC_TEMP_RIGHT
and v_cntr_reg_dly > XADC_TEMP_TOP and v_cntr_reg_dly < XADC_TEMP_BOTTOM
else
adt7420_temp_blue_dly when h_cntr_reg_dly > ADT7420_TEMP_LEFT and h_cntr_reg_dly < ADT7420_TEMP_RIGHT
and v_cntr_reg_dly > ADT7420_TEMP_TOP and v_cntr_reg_dly < ADT7420_TEMP_BOTTOM
else
adxl362_temp_blue_dly when h_cntr_reg_dly > ADXL362_TEMP_LEFT and h_cntr_reg_dly < ADXL362_TEMP_RIGHT
and v_cntr_reg_dly > ADXL362_TEMP_TOP and v_cntr_reg_dly < ADXL362_TEMP_BOTTOM
else
-- TBOX display
tbox_blue when h_cntr_reg_dly > TBOX_LEFT and h_cntr_reg_dly < TBOX_RIGHT
and v_cntr_reg_dly < TBOX_BOTTOM and v_cntr_reg_dly > TBOX_TOP
else
-- RGB Led display
rgb_b_red_col_dly when (h_cntr_reg_dly > RGB_R_COL_LEFT and h_cntr_reg_dly < RGB_R_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
rgb_b_green_col_dly when (h_cntr_reg_dly > RGB_G_COL_LEFT and h_cntr_reg_dly < RGB_G_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP - 1 and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
rgb_b_blue_col_dly when (h_cntr_reg_dly > RGB_B_COL_LEFT and h_cntr_reg_dly < RGB_B_COL_RIGHT)
and
(
(v_cntr_reg_dly > RGB1_COL_TOP and v_cntr_reg_dly < RGB1_COL_BOTTOM)
or
(v_cntr_reg_dly > RGB2_COL_TOP and v_cntr_reg_dly < RGB2_COL_BOTTOM)
)
else
-- LBOX display
lbox_blue when h_cntr_reg_dly > LBOX_LEFT and h_cntr_reg_dly < LBOX_RIGHT
and v_cntr_reg_dly < LBOX_BOTTOM and v_cntr_reg_dly > LBOX_TOP
else
-- Microphone data display
mic_blue_dly when h_cntr_reg_dly > MIC_LEFT and h_cntr_reg_dly < MIC_RIGHT
and v_cntr_reg_dly > MIC_TOP and v_cntr_reg_dly < MIC_BOTTOM
else
-- Accelerometer display
acl_blue_dly when h_cntr_reg_dly > ACL_LEFT and h_cntr_reg_dly < ACL_RIGHT
and v_cntr_reg_dly > ACL_TOP and v_cntr_reg_dly < ACL_BOTTOM
else
-- Colorbar will be on the backround
bg_blue_dly;
------------------------------------------------------------
-- Turn Off VGA RBG Signals if outside of the active screen
-- Make a 4-bit AND logic with the R, G and B signals
------------------------------------------------------------
vga_red_cmb <= (active & active & active & active) and vga_red;
vga_green_cmb <= (active & active & active & active) and vga_green;
vga_blue_cmb <= (active & active & active & active) and vga_blue;
-- Register Outputs
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
v_sync_reg_dly <= v_sync_reg;
h_sync_reg_dly <= h_sync_reg;
vga_red_reg <= vga_red_cmb;
vga_green_reg <= vga_green_cmb;
vga_blue_reg <= vga_blue_cmb;
end if;
end process;
-- Assign outputs
VGA_HS_O <= h_sync_reg_dly;
VGA_VS_O <= v_sync_reg_dly;
VGA_RED_O <= vga_red_reg;
VGA_GREEN_O <= vga_green_reg;
VGA_BLUE_O <= vga_blue_reg;
end Behavioral;
|
gpl-3.0
|
18c43acfbbfd65bb8dc577ca29e902d6
| 0.555949 | 3.690351 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/genram_pkg.vhd
| 1 | 9,017 |
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2013-10-30
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
function f_zeros (size : integer) return std_logic_vector;
type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "none";
g_addr_conflict_resolution : string := "dont_care") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0):= f_gen_dummy_vec('1', (g_data_width+7)/8);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_simple_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width -1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
qb_o : out std_logic_vector(g_data_width -1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic := '0';
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
web_i : in std_logic := '0';
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_shiftreg_fifo
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
full_o : out std_logic;
almost_full_o : out std_logic;
q_valid_o : out std_logic
);
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector is
variable tmp : std_logic_vector(size-1 downto 0);
begin
for i in 0 to size-1 loop
tmp(i) := val;
end loop; -- i
return tmp;
end f_gen_dummy_vec;
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
end genram_pkg;
|
lgpl-3.0
|
1cebf23ffc921e14d5f54c15d13559a0
| 0.51658 | 3.38985 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/dff_reg.vhd
| 3 | 874 |
-- D-Flip-Flop register component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff_reg IS
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END dff_reg;
ARCHITECTURE behavioural OF dff_reg IS
BEGIN
gen_rising_edge: IF triggering_edge='1' GENERATE
reg_proc_rising: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF rising_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
gen_falling_edge: IF triggering_edge='0' GENERATE
reg_proc_falling: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF falling_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
END behavioural;
|
bsd-3-clause
|
8854cf2267215f7c754f44f2c25aa3bb
| 0.659039 | 3.427451 | false | false | false | false |
bzero/freezing-spice
|
src/encode_pkg.vhd
| 2 | 10,314 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.decode_pkg.all;
package encode_pkg is
subtype register_t is integer range 0 to 31;
-- functions to encode the different types of instructions, organized by format
function encode_r_type (insn_type : r_insn_t;
rs1, rs2, rd : register_t)
return word;
function encode_i_type (insn_type : i_insn_t;
imm : std_logic_vector(11 downto 0);
rs1, rd : register_t)
return word;
function encode_s_type (insn_type : s_insn_t;
imm : std_logic_vector(11 downto 0);
rs1, rs2 : register_t)
return word;
function encode_sb_type (insn_type : sb_insn_t;
imm : std_logic_vector(12 downto 1);
rs1, rs2 : register_t)
return word;
function encode_u_type (insn_type : u_insn_t;
imm_31_12 : std_logic_vector(31 downto 12);
rd : register_t)
return word;
function encode_uj_type (insn_type : uj_insn_t;
imm : std_logic_vector(20 downto 1);
rd : register_t)
return word;
function encode_i_shift (i_insn : i_insn_t;
shamt : std_logic_vector(4 downto 0);
rs1, rd : register_t)
return word;
end package encode_pkg;
package body encode_pkg is
-- purpose: encode a U-type instruction
function encode_u_type (insn_type : u_insn_t;
imm_31_12 : std_logic_vector(31 downto 12);
rd : register_t) return word is
variable result : word;
begin -- function encode_lui
result(31 downto 12) := imm_31_12;
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
case insn_type is
when U_LUI => result(6 downto 0) := c_op_lui;
when U_AUIPC => result(6 downto 0) := c_op_auipc;
end case;
return result;
end function encode_u_type;
-- purpose: encode an R-type instruction
function encode_r_type (insn_type : r_insn_t;
rs1, rs2, rd : register_t)
return word is
variable result : word;
begin -- function encode_r_type
result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5));
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
result(6 downto 0) := c_op_reg;
case insn_type is
when R_ADD =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "000";
when R_SUB =>
result(31 downto 25) := "0100000";
result(14 downto 12) := "000";
when R_SLL =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "001";
when R_SLT =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "010";
when R_SLTU =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "011";
when R_XOR =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "100";
when R_SRL =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "101";
when R_SRA =>
result(31 downto 25) := "0100000";
result(14 downto 12) := "101";
when R_OR =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "110";
when R_AND =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "111";
end case;
return result;
end function encode_r_type;
-- purpose: encode a UJ-type instruction
function encode_uj_type (
insn_type : uj_insn_t;
imm : std_logic_vector(20 downto 1);
rd : register_t)
return word is
variable result : word;
begin -- function encode_uj_type
result(31) := imm(20);
result(30 downto 21) := imm(10 downto 1);
result(20) := imm(11);
result(19 downto 12) := imm(19 downto 12);
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
case insn_type is
when UJ_JAL => result(6 downto 0) := c_op_jal;
end case;
return result;
end function encode_uj_type;
-- purpose: encode an I-type instruction (for shifts only)
function encode_i_shift (
i_insn : i_insn_t;
shamt : std_logic_vector(4 downto 0);
rs1, rd : register_t)
return word is
variable result : word;
begin -- function encode_i_shift
result(24 downto 20) := shamt;
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
result(6 downto 0) := c_op_imm;
case (i_insn) is
when I_SLLI =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "001";
when I_SRLI =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "101";
when I_SRAI =>
result(31 downto 25) := "0100000";
result(14 downto 12) := "101";
when others =>
assert false report "Not an immediate shift instruction" severity error;
end case;
return result;
end function encode_i_shift;
-- purpose: encode an I-type instruction
function encode_i_type (insn_type : i_insn_t;
imm : std_logic_vector(11 downto 0);
rs1, rd : register_t)
return word is
variable result : word;
begin
result(31 downto 20) := imm;
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
case insn_type is
when I_JALR =>
result(14 downto 12) := "000";
result(6 downto 0) := c_op_jalr;
when I_LB =>
result(14 downto 12) := "000";
result(6 downto 0) := c_op_load;
when I_LH =>
result(14 downto 12) := "001";
result(6 downto 0) := c_op_load;
when I_LW =>
result(14 downto 12) := "010";
result(6 downto 0) := c_op_load;
when I_LBU =>
result(14 downto 12) := "100";
result(6 downto 0) := c_op_load;
when I_LHU =>
result(14 downto 12) := "101";
result(6 downto 0) := c_op_load;
when I_ADDI =>
result(14 downto 12) := "000";
result(6 downto 0) := c_op_imm;
when I_SLTI =>
result(14 downto 12) := "010";
result(6 downto 0) := c_op_imm;
when I_SLTIU =>
result(14 downto 12) := "011";
result(6 downto 0) := c_op_imm;
when I_XORI =>
result(14 downto 12) := "100";
result(6 downto 0) := c_op_imm;
when I_ORI =>
result(14 downto 12) := "110";
result(6 downto 0) := c_op_imm;
when I_ANDI =>
result(14 downto 12) := "111";
result(6 downto 0) := c_op_imm;
when others =>
assert false report "Use encode_i_shift" severity error;
end case;
return result;
end function encode_i_type;
-- purpose: encode an S-type instruction
function encode_s_type (insn_type : s_insn_t;
imm : std_logic_vector(11 downto 0);
rs1, rs2 : register_t)
return word is
variable result : word;
begin -- function encode_s_type
result(31 downto 25) := imm(11 downto 5);
result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5));
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 7) := imm(4 downto 0);
result(6 downto 0) := c_op_store;
case insn_type is
when S_SB => result(14 downto 12) := "000";
when S_SH => result(14 downto 12) := "001";
when S_SW => result(14 downto 12) := "010";
end case;
return result;
end function encode_s_type;
-- encode an SB-type instruction
function encode_sb_type (insn_type : sb_insn_t;
imm : std_logic_vector(12 downto 1);
rs1, rs2 : register_t)
return word is
variable result : word;
begin
result(31) := imm(12);
result(30 downto 25) := imm(10 downto 5);
result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5));
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 8) := imm(4 downto 1);
result(7) := imm(11);
result(6 downto 0) := c_op_branch;
case insn_type is
when SB_BEQ => result(14 downto 12) := "000";
when SB_BNE => result(14 downto 12) := "001";
when SB_BLT => result(14 downto 12) := "100";
when SB_BGE => result(14 downto 12) := "101";
when SB_BLTU => result(14 downto 12) := "110";
when SB_BGEU => result(14 downto 12) := "111";
end case;
return result;
end function encode_sb_type;
end package body encode_pkg;
|
bsd-3-clause
|
434f4af89f9e84e676fdb1cbcb73194b
| 0.473822 | 3.986857 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_core_v2_03_a/hdl/vhdl/dcr_slave_regs.vhd
| 1 | 14,117 |
--!
--! \file dcr_slave_regs.vhd
--!
--! DCR bus slave logic for ReconOS OSIF (user_logic)
--!
--! Contains the bus access logic for the two register sets of the OSIF:
--!
--! bus2osif registers (writeable by the bus, readable by OSIF logic):
--! o_bus2osif_command command register C_DCR_BASEADDR + 0x00
--! o_bus2osif_data data register C_DCR_BASEADDR + 0x01
--! o_bus2osif_done s/w-access handshake reg C_DCR_BASEADDR + 0x02
--! UNUSED C_DCR_BASEADDR + 0x03
--!
--! osif2bus registers (readable by the bus, writeable by OSIF logic):
--! i_osif2bus_command command register C_DCR_BASEADDR + 0x00
--! i_osif2bus_data data register C_DCR_BASEADDR + 0x01
--! i_osif2bus_datax extended data register C_DCR_BASEADDR + 0x02
--! i_osif2bus_signature hardware thread signature C_DCR_BASEADDR + 0x03
--!
--!
--! The i_post signal is set on a OS request which needs to be handled in
--! software.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 07.08.2006
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- Copyright (c) 2008, Computer Engineering Group, University of
-- Paderborn.
--
-- For details regarding licensing and redistribution, see COPYING. If
-- you did not receive a COPYING file as part of the distribution package
-- containing this file, you can get it at http://www.reconos.de/COPYING.
--
-- This software is provided "as is" without express or implied warranty,
-- and with no claim as to its suitability for any particular purpose.
-- The copyright owner or the contributors shall not be liable for any
-- damages arising out of the use of this software.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 07.08.2006 Enno Luebbers File created
-- 25.09.2007 Enno Luebbers added i_osif2bus_datax
-- 23.11.2007 Enno Luebbers moved to DCR interface
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity dcr_slave_regs is
generic (
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_NUM_REGS : integer := 8;
C_ENABLE_MMU : boolean := true;
C_INCLUDE_ILA : integer := 0 -- 0: no ILA, 1: ILA
);
port (
clk : in std_logic;
reset : in std_logic; -- high active synchronous
-- DCR interface
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0);
-- mmu diagnosis registers
i_tlb_miss_count : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_tlb_hit_count : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_page_fault_count : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
-- user registers
i_osif2bus_command : in std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
i_osif2bus_flags : in std_logic_vector(0 to C_OSIF_FLAGS_WIDTH-1);
i_osif2bus_saved_state_enc : in std_logic_vector(0 to C_OSIF_STATE_ENC_WIDTH-1);
i_osif2bus_saved_step_enc : in std_logic_vector(0 to C_OSIF_STEP_ENC_WIDTH-1);
i_osif2bus_data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
i_osif2bus_datax : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
i_osif2bus_signature : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
o_bus2osif_command : out std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
o_bus2osif_data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
o_bus2osif_done : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- additional user interface
o_newcmd : out std_logic;
i_post : in std_logic;
o_busy : out std_logic
--o_interrupt : out std_logic
);
end dcr_slave_regs;
architecture behavioral of dcr_slave_regs is
-- chipscope DCR ILA component
component dcr_ila
port (
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(76 downto 0);
trig0 : in std_logic_vector(2 downto 0)
);
end component;
constant C_OSIF_DCR_AWIDTH : natural := 3;
type reg_select_t is (
C_SELECT_NONE,
C_SELECT_COMMAND,
C_SELECT_DATA,
C_SELECT_DONE,
C_SELECT_SIGNATURE,
C_SELECT_TLB_MISS,
C_SELECT_TLB_HIT,
C_SELECT_PGFAULT
);
-- Bus signalling helper signals
signal dcrAddrHit : std_logic;
signal dcrAck : std_logic;
-- Bus signalling helper signals
signal ip2bus_data : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal reg_write_select : reg_select_t;
signal reg_read_select : reg_select_t;
-- Actual bus2osif registers
signal bus2osif_command_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
signal bus2osif_data_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
signal bus2osif_done_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
-- new command arrived
signal newcmd : std_logic;
-- signals indicating unread data in bus-readable registers
signal osif2bus_reg_dirty : std_logic_vector(0 to 2) := "000";
-- DCR debug ILA signals
signal ila_data : std_logic_vector(76 downto 0);
signal ila_trig0 : std_logic_vector(2 downto 0);
begin
---------------------------------------------------
-- CHIPSCOPE
gen_dcr_ila : if C_INCLUDE_ILA = 1 generate
dcr_ila_inst : dcr_ila
port map (
control => i_dcrICON,
clk => clk,
data => ila_data,
trig0 => ila_trig0
);
-- bits 76 75 74-65 64-33 32 31-0
--ila_data <= i_dcrRead & i_dcrWrite & i_dcrABus & i_dcrDBus & dcrAck & ip2bus_data;
ila_data <= i_dcrRead & i_dcrWrite & i_dcrABus & i_dcrDBus & newcmd & ip2bus_data;
ila_trig0 <= i_dcrRead & i_dcrWrite & dcrAck;
end generate;
---------------------------------------------------
----------------------------------------------------------------------------------------------------------
-- DCR "IPIF"
----------------------------------------------------------------------------------------------------------
-- 4 registers = 2 LSBs FIXME: hardcoded. Use log2 instead!
--dcrAddrHit <= '1' when i_dcrABus(0 to C_DCR_AWIDTH-C_OSIF_DCR_AWIDTH) = C_DCR_BASEADDR(0 to C_DCR_AWIDTH-C_OSIF_DCR_AWIDTH)
-- else '0';
--regAddr <= i_dcrABus(C_DCR_AWIDTH-C_OSIF_DCR_AWIDTH+1 to C_DCR_AWIDTH-1);
--
-- decode read and write accesses into chip enable signals
-- ASYNCHRONOUS
--
ce_gen : process(dcrAddrHit, i_dcrRead, i_dcrWrite, i_dcrABus)
variable tmp : reg_select_t;
begin
-- decode register address and set
-- corresponding chip enable signal
dcrAddrHit <= '1';
if i_dcrABus = C_DCR_BASEADDR + 0 then tmp := C_SELECT_COMMAND;
elsif i_dcrABus = C_DCR_BASEADDR + 1 then tmp := C_SELECT_DATA;
elsif i_dcrABus = C_DCR_BASEADDR + 2 then tmp := C_SELECT_DONE;
elsif i_dcrABus = C_DCR_BASEADDR + 3 then tmp := C_SELECT_SIGNATURE;
elsif C_ENABLE_MMU and i_dcrABus = C_DCR_BASEADDR + 4 then tmp := C_SELECT_TLB_MISS;
elsif C_ENABLE_MMU and i_dcrABus = C_DCR_BASEADDR + 5 then tmp := C_SELECT_TLB_HIT;
elsif C_ENABLE_MMU and i_dcrABus = C_DCR_BASEADDR + 6 then tmp := C_SELECT_PGFAULT;
else
tmp := C_SELECT_NONE;
dcrAddrHit <= '0';
end if;
if i_dcrRead = '1' then
reg_read_select <= tmp;
reg_write_select <= C_SELECT_NONE;
elsif i_dcrWrite = '1' then
reg_read_select <= C_SELECT_NONE;
reg_write_select <= tmp;
else
reg_read_select <= C_SELECT_NONE;
reg_write_select <= C_SELECT_NONE;
end if;
end process;
--
-- generate DCR slave acknowledge signal
-- SYNCHRONOUS
--
gen_ack_proc : process(clk, reset)
begin
if reset = '1' then
dcrAck <= '0';
elsif rising_edge(clk) then
dcrAck <= ( i_dcrRead or i_dcrWrite ) and dcrAddrHit;
end if;
end process;
o_dcrAck <= dcrAck;
-- connect registers to outputs
o_bus2osif_command <= bus2osif_command_reg(0 to C_OSIF_CMD_WIDTH-1);
o_bus2osif_data <= bus2osif_data_reg;
o_bus2osif_done <= bus2osif_done_reg;
-- new command from OS if write_reg2 is all ones. FIXME: 0000_0001 sufficient?
-- this is here to prevent incomplete command transmission if CPU uses byte accesses
-- will be cleared on cycle after assertion (see slave_reg_write_proc)
newcmd <= '1' when bus2osif_done_reg = X"FFFF_FFFF" else '0';
o_newcmd <= newcmd;
-- we are busy as long as a pending request has not been retrieved by the CPU
o_busy <= osif2bus_reg_dirty(0) or osif2bus_reg_dirty(1) or osif2bus_reg_dirty(2) or i_post;
-- posting generates an interrupt
-- o_interrupt <= i_post;
-- drive IP to DCR Bus signals
o_dcrDBus <= ip2bus_data;
-- connect bus signalling
--reg_write_select <= writeCE;
--reg_read_select <= readCE;
-------------------------------------------------------------
-- slave_reg_write_proc: implement bus write access to slave
-- registers
-------------------------------------------------------------
slave_reg_write_proc : process(clk) is
begin
if clk'event and clk = '1' then
if reset = '1' then
bus2osif_command_reg <= (others => '0');
bus2osif_data_reg <= (others => '0');
bus2osif_done_reg <= (others => '0');
else
if dcrAck = '0' then -- register values only ONCE per write select
case reg_write_select is
when C_SELECT_COMMAND =>
bus2osif_command_reg <= i_dcrDBus;
when C_SELECT_DATA =>
bus2osif_data_reg <= i_dcrDBus;
when C_SELECT_DONE =>
bus2osif_done_reg <= i_dcrDBus;
--when C_SELECT_SIGNATURE => null;
when others => null;
end case;
end if;
if newcmd = '1' then
bus2osif_done_reg <= (others => '0');
end if;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-------------------------------------------------------------
-- slave_reg_read_proc: implement bus read access to slave
-- registers
-------------------------------------------------------------
slave_reg_read_proc : process(reg_read_select, i_osif2bus_command, i_osif2bus_data, i_osif2bus_datax, i_dcrDBus,
i_osif2bus_flags, i_osif2bus_saved_state_enc, i_osif2bus_saved_step_enc, i_osif2bus_signature, i_tlb_miss_count, i_tlb_hit_count, i_page_fault_count) is
begin
ip2bus_data <= i_dcrDBus;
case reg_read_select is
when C_SELECT_COMMAND => ip2bus_data <= i_osif2bus_command & i_osif2bus_flags & i_osif2bus_saved_state_enc & i_osif2bus_saved_step_enc & "000000";
when C_SELECT_DATA => ip2bus_data <= i_osif2bus_data;
when C_SELECT_DONE => ip2bus_data <= i_osif2bus_datax;
when C_SELECT_SIGNATURE => ip2bus_data <= i_osif2bus_signature;
when C_SELECT_TLB_MISS => ip2bus_data <= i_tlb_miss_count;
when C_SELECT_TLB_HIT => ip2bus_data <= i_tlb_hit_count;
when C_SELECT_PGFAULT => ip2bus_data <= i_page_fault_count;
when others => null;
end case;
end process SLAVE_REG_READ_PROC;
-----------------------------------------------------------------------
-- dirty_flags: sets and clears osif2bus_reg_dirty bits
--
-- This allows to block the user task in a busy state while waiting
-- for OS to fetch the new commands.
-- The signature register does not need to be read to clear the dirty
-- flags.
-- The dirty flags are (obviously) only set on software-handled requests.
-----------------------------------------------------------------------
dirty_flags : process(reset, clk) --, i_post, reg_read_select)
begin
if reset = '1' then
osif2bus_reg_dirty <= (others => '0');
-- request only pollutes the read registers, if request is to be handled by software
elsif rising_edge(clk) then
if i_post = '1' then
osif2bus_reg_dirty <= (others => '1');
else
if reg_read_select = C_SELECT_COMMAND then osif2bus_reg_dirty(0) <= '0'; end if;
if reg_read_select = C_SELECT_DATA then osif2bus_reg_dirty(1) <= '0'; end if;
if reg_read_select = C_SELECT_DONE then osif2bus_reg_dirty(2) <= '0'; end if;
end if;
end if;
end process;
end behavioral;
|
gpl-3.0
|
9e617f6a9c4b14b8b315433d9611e92f
| 0.540696 | 3.710118 | false | false | false | false |
whitef0x0/EECE353-Lab5
|
lab5_new.vhd
| 1 | 14,970 |
--David Baldwin: 10832137
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab5_new is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
-- LEDG : out std_logic_vector(7 downto 0);
colour_out : out std_logic_vector(2 downto 0);
x_out : out std_logic_vector(7 downto 0);
y_out : out std_logic_vector(6 downto 0);
plot_out : out std_logic
-- VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller
-- VGA_HS : out std_logic;
-- VGA_VS : out std_logic;
-- VGA_BLANK : out std_logic;
-- VGA_SYNC : out std_logic;
-- VGA_CLK : out std_logic
);
end lab5_new;
architecture RTL of lab5_new is
-- component vga_adapter
-- generic(RESOLUTION : string);
-- port(
-- resetn : in std_logic;
-- clock : in std_logic;
-- colour : in std_logic_vector(2 downto 0);
-- x : in std_logic_vector(7 downto 0);
-- y : in std_logic_vector(6 downto 0);
-- plot : in std_logic;
-- VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
-- VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic);
-- end component;
signal x : std_logic_vector(7 downto 0) := "00000000";
signal y : std_logic_vector(6 downto 0) := "0000000";
signal colour : std_logic_vector(2 downto 0) := "000";
signal plot : std_logic := '0';
begin
-- vga_u0 : vga_adapter
-- generic map(RESOLUTION => "160x120")
-- port map(resetn => KEY(3),
-- clock => CLOCK_50,
-- colour => colour,
-- x => x,
-- y => y,
-- plot => plot,
-- VGA_R => VGA_R,
-- VGA_G => VGA_G,
-- VGA_B => VGA_B,
-- VGA_HS => VGA_HS,
-- VGA_VS => VGA_VS,
-- VGA_BLANK => VGA_BLANK,
-- VGA_SYNC => VGA_SYNC,
-- VGA_CLK => VGA_CLK);
x_out <= x;
y_out <= y;
plot_out <= plot;
colour_out <= colour;
process(CLOCK_50, KEY(3))
type state_types is (sr, sb, sginit, sg1g, sg1f, sg2g, sg2f, sgp1, sgp2, sgpause, sgdone);
variable state : state_types := sr;
variable clk : unsigned(21 downto 0) := "0000000000000000000000";
variable max_clk : unsigned(21 downto 0) := "1111111111111111111111";
variable x_tmp : unsigned(7 downto 0) := "00000000";
variable y_tmp : unsigned(6 downto 0) := "0000000";
variable t1g, t1f, t2g, t2f : unsigned(6 downto 0);
variable puckx : unsigned(7 downto 0) := "01010000";
variable pucky : unsigned(6 downto 0) := "0111100";
variable velx : std_logic := '0';
variable vely : std_logic := '0';
begin
if (KEY(3) = '0') then
state := sr;
elsif (rising_edge(CLOCK_50)) then
case state is
when sr =>
colour <= "000";
plot <= '0';
x_tmp := "00000000";
y_tmp := "0000000";
puckx := "01010000";
pucky := "0111100";
--THIS ISN'T CORRECT WAY TO INITIALIZE OUR VELOCITY
velx := sw(17) xor sw(0);
vely := sw(16) xor sw(1);
max_clk := (others => '1');
state := sb;
when sb =>
plot <= '1';
colour <= "000";
y <= std_logic_vector(y_tmp);
x <= std_logic_vector(x_tmp);
x_tmp := x_tmp + 1;
if (x_tmp = 160) then
x_tmp := "00000000";
y_tmp := y_tmp + 1;
if (y_tmp = 120) then
x_tmp := "00000101"; -- 5
y_tmp := "0000101"; -- 5
state := sginit;
end if;
end if;
when sginit =>
plot <= '1';
colour <= "111";
y <= std_logic_vector(y_tmp);
x <= std_logic_vector(x_tmp);
x_tmp := x_tmp + 1;
if (x_tmp = 155) then
x_tmp := "00000101";
if (y_tmp = 115) then
t1g := "0110110";
t1f := "0110110";
t2g := "0110110";
t2f := "0110110";
y_tmp := "0000101";
state := sg1g;
else
y_tmp := "1110011"; -- 120 - 5 = 115
end if;
end if;
when sg1g =>
plot <= '1';
x_tmp := "00000101";
y_tmp := y_tmp + 1;
if (y_tmp >= t1g and y_tmp <= t1g + 12 and y_tmp < 115) then
colour <= "001";
elsif (y_tmp >= 115) then
if (sw(17) = '1') then
if (t1g > 6) then
t1g := t1g - 1;
end if;
else
if (t1g < 102) then
t1g := t1g + 1;
end if;
end if;
y_tmp := "0000101";
colour <= "111";
state := sg1f;
else
colour <= "000";
end if;
y <= std_logic_vector(y_tmp);
x <= std_logic_vector(x_tmp);
when sg1f =>
plot <= '1';
x_tmp := "01000011";
y_tmp := y_tmp + 1;
if (y_tmp >= t1f and y_tmp <= t1f + 12 and y_tmp < 115) then
colour <= "001";
elsif (y_tmp >= 115) then
if (sw(16) = '1') then
if (t1f > 6) then
t1f := t1f - 1;
end if;
else
if (t1f < 102) then
t1f := t1f + 1;
end if;
end if;
y_tmp := "0000101";
colour <= "111";
state := sg2g;
else
colour <= "000";
end if;
y <= std_logic_vector(y_tmp);
x <= std_logic_vector(x_tmp);
when sg2g =>
plot <= '1';
x_tmp := "10011010";
y_tmp := y_tmp + 1;
if (y_tmp >= t2g and y_tmp <= t2g + 12 and y_tmp < 115) then
colour <= "100";
elsif (y_tmp >= 115) then
if (sw(0) = '1') then
if (t2g > 6) then
t2g := t2g - 1;
end if;
else
if (t2g < 102) then
t2g := t2g + 1;
end if;
end if;
y_tmp := "0000101";
colour <= "111";
state := sg2f;
else
colour <= "000";
end if;
y <= std_logic_vector(y_tmp);
x <= std_logic_vector(x_tmp);
when sg2f =>
plot <= '1';
x_tmp := "01011101";
y_tmp := y_tmp + 1;
if (y_tmp >= t2f and y_tmp <= t2f + 12 and y_tmp < 115) then
colour <= "100";
elsif (y_tmp >= 115) then
if (sw(1) = '1') then
if (t2f > 6) then
t2f := t2f - 1;
end if;
else
if (t2f < 102) then
t2f := t2f + 1;
end if;
end if;
colour <= "111";
state := sgp1;
else
colour <= "000";
end if;
y <= std_logic_vector(y_tmp);
x <= std_logic_vector(x_tmp);
when sgp1 =>
plot <= '1';
colour <= "000";
y <= std_logic_vector(pucky);
x <= std_logic_vector(puckx);
state := sgp2;
when sgp2 =>
--collision detection with walls
--DOESN'T SEEM TO INVERT X VELOCITY
--ONLY REFRESHES WHEN BALL COLLIDES WITH LEFT OR RIGHT WALL
--Checks collision with LEFT wall
if (puckx <= 4) then
state := sr;
--velx: '1';
--Checks collision with RIGHT wall
elsif (puckx >= 156) then
state := sr;
--velx: '1';
else
--Checks collision with TOP wall
if (pucky <= 6) then
vely := '1';
--Checks collision with BOTTOM wall
elsif (pucky >= 114) then
vely := '0';
end if;
if (velx = '0') then
puckx := puckx - 1;
else
puckx := puckx + 1;
end if;
if (vely = '0') then
pucky := pucky - 1;
else
pucky := pucky + 1;
end if;
--collision detection with paddles
--ONLY INVERTS X VELOCITY, NOT THE Y VELOCITY when hitting
if (puckx = "00000101" and pucky >= t1g and pucky <= t1g+12) then
velx := not velx;
if (velx = '0') then
--Why is it going by increments of '2' and not of '1'?
puckx := puckx - 2;
else
puckx := puckx + 2;
end if;
elsif (puckx = "01000011" and pucky >= t1f and pucky <= t1f+12) then
velx := not velx;
if (velx = '0') then
puckx := puckx - 2;
else
puckx := puckx + 2;
end if;
elsif (puckx = "10011010" and pucky >= t2g and pucky <= t2g+12) then
velx := not velx;
if (velx = '0') then
puckx := puckx - 2;
else
puckx := puckx + 2;
end if;
elsif (puckx = "01011101" and pucky >= t2f and pucky <= t2f+12) then
velx := not velx;
if (velx = '0') then
puckx := puckx - 2;
else
puckx := puckx + 2;
end if;
end if;
plot <= '1';
colour <= "111";
y <= std_logic_vector(pucky);
x <= std_logic_vector(puckx);
--Go to pause state
state := sgpause;
end if;
--Handles updating all game sprites
when sgpause =>
plot <= '0';
clk := clk + 1;
--initial max_clk is 4194303
--Slow down the clock with a counter (from 50MHz)
--Refresh screen every 12Hz, 25Hz, 55Hz or 71Hz
--First refresh will be 12Hz
--Every other refresh (until initialization) will decrease by 2ms until it reaches 71Hz
if (clk = max_clk) then
--reset clk counter to 0
clk := "0000000000000000000000";
if (max_clk >= 4000000) then
max_clk := max_clk - 100000;
elsif (max_clk >= 2000000) then
max_clk := max_clk - 10000;
elsif (max_clk >= 900000) then
max_clk := max_clk - 1000;
elsif (max_clk >= 700000) then
max_clk := max_clk - 100;
end if;
-- ledg <= std_logic_vector(max_clk(21 downto 14));
--Redraw paddles
y_tmp := "0000101"; --set y to 5
colour <= "111";
state := sg1g;
end if;
when others =>
state := sb;
end case;
end if;
end process;
end RTL;
|
mit
|
8b04b54daea02f1477430e1fde36a7af
| 0.315898 | 4.94876 | false | false | false | false |
luebbers/reconos
|
demos/sort_demo_inv_pr/hw/sort8kinv/sort8kinv.vhd
| 1 | 6,191 |
--
-- sort8k.vhd
-- eCos hardware thread using the bubble_sort module and mailboxes to
-- sort 8k-sized blocks of data in main memory. The incoming messages
-- on C_MB_START contain the addresses of the blocks, and an arbitrary
-- message sent to C_MB_DONE signals completion of the sorting process.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sort8kinv is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end sort8kinv;
architecture Behavioral of sort8kinv is
component bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (STATE_GET, STATE_READ, STATE_SORT, STATE_WAIT, STATE_WRITE, STATE_PUT);
signal state : t_state := STATE_GET;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- handshaking signals
signal sort_start : std_logic := '0';
signal sort_done : std_logic;
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => 2048,
G_AWIDTH => C_BURST_AWIDTH,
G_DWIDTH => C_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
o_RAMAddr => RAMAddr,
o_RAMData => o_RAMData,
i_RAMData => i_RAMData,
o_RAMWE => o_RAMWE,
start => sort_start,
done => sort_done
);
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
sort_start <= '0';
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- wait for/get data address. No error checking is done here.
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, address);
if done then
burst_counter := 0;
state <= STATE_READ;
end if;
-- read data from main memory into local burst RAM.
when STATE_READ =>
reconos_read_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_SORT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- start sorting module
when STATE_SORT =>
sort_start <= '1';
state <= STATE_WAIT;
-- wait for sort completion
when STATE_WAIT =>
sort_start <= '0';
if sort_done = '1' then
burst_counter := 0;
state <= STATE_WRITE;
end if;
-- write sorted data back to main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_PUT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- write message to DONE mailbox
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, address);
if done then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
95fcf1a1c202d61d5b3013740a9acb88
| 0.545146 | 3.903531 | false | false | false | false |
oetr/FPGA-I2C-Slave
|
I2C_minion_TB_002_noisy_scl.vhd
| 1 | 18,358 |
-----------------------------------------------------------------------------
-- Title : I2C_minion Testbench: noisy scl
-----------------------------------------------------------------------------
-- File : I2C_minion_TB_002_noisy_scl.vhd
-- Author : Peter Samarin <[email protected]>
-----------------------------------------------------------------------------
-- Copyright (c) 2019 Peter Samarin
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use ieee.math_real.all; -- using uniform(seed1,seed2,rand)
------------------------------------------------------------------------
entity I2C_minion_TB_002_noisy_scl is
end I2C_minion_TB_002_noisy_scl;
------------------------------------------------------------------------
architecture Testbench of I2C_minion_TB_002_noisy_scl is
constant T : time := 20 ns; -- clk period
constant T_spike : time := 1 ns;
constant TH_I2C : time := 100 ns; -- i2c clk quarter period(kbis)
constant T_MUL : integer := 2; -- i2c clk quarter period(kbis)
constant T_HALF : integer := (TH_I2C*T_MUL*2) / T; -- i2c halfclk period
constant T_QUARTER : integer := (TH_I2C*T_MUL) / T; -- i2c quarterclk period
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal scl : std_logic := 'Z';
signal sda : std_logic := 'Z';
signal scl_pre_spike : std_logic := 'Z';
signal sda_pre_spike : std_logic := 'Z';
signal state_dbg : integer := 0;
signal received_data : std_logic_vector(7 downto 0) := (others => '0');
signal ack : std_logic := '0';
signal read_req : std_logic := '0';
signal data_to_master : std_logic_vector(7 downto 0) := (others => '0');
signal data_valid : std_logic := '0';
signal data_from_master : std_logic_vector(7 downto 0) := (others => '0');
signal data_from_master_reg : std_logic_vector(7 downto 0) := (others => '0');
-- random spike generation
constant MAX_SPIKE_DURATION : real := 17.0; -- 17ns
constant MAX_TIMEOUT_AFTER_SPIKE : real := 1.0; -- 1ns
constant P_SPIKE : real := 0.01;
shared variable seed1 : positive := 1000;
shared variable seed2 : positive := 2000;
shared variable rand_scl, rand_sda : real; -- random real-number value in range 0 to 1.0
shared variable scl_spike_duration : integer := 0;
shared variable timeout_after_scl_spike : integer := 0;
shared variable scl_spike_should_happen : real := 0.0;
shared variable sda_spike_duration : integer := 0;
shared variable timeout_after_sda_spike : integer := 0;
shared variable sda_spike_should_happen : real := 0.0;
-- one I2C minion for ideal scl/sda signal
-- simulation control
shared variable SCL_noise_on : boolean := false;
shared variable SDA_noise_on : boolean := false;
shared variable ENDSIM : boolean := false;
begin
---- Design Under Verification -----------------------------------------
DUV : entity work.I2C_minion
generic map (
MINION_ADDR => "0000011",
USE_INPUT_DEBOUNCING => true,
DEBOUNCING_WAIT_CYCLES => 5)
port map (
-- I2C
scl => scl,
sda => sda,
-- default signals
clk => clk,
rst => rst,
-- user interface
read_req => read_req,
data_to_master => data_to_master,
data_valid => data_valid,
data_from_master => data_from_master);
---- DUT clock running forever ----------------------------
process
begin
if ENDSIM = false then
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
else
wait;
end if;
end process;
---- Reset asserted for T/2 ------------------------------
rst <= '1', '0' after T/2;
---- SCL spike generator -------------------------
process
begin
if ENDSIM = false then
uniform(seed1, seed2, rand_scl); -- generate random number
scl_spike_should_happen := rand_scl;
uniform(seed1, seed2, rand_scl); -- generate random number
scl_spike_duration := integer(rand_scl*MAX_SPIKE_DURATION);
uniform(seed1, seed2, rand_scl); -- generate random number
timeout_after_scl_spike := integer(rand_scl*MAX_TIMEOUT_AFTER_SPIKE);
if SCL_noise_on then
if scl_spike_should_happen < P_SPIKE then
if scl = '0' then
scl <= 'Z';
else
scl <= '0';
end if;
else
scl <= scl_pre_spike;
end if;
end if;
wait for scl_spike_duration * 1 ns;
scl <= scl_pre_spike;
wait for timeout_after_scl_spike * 1 ns;
else
wait;
end if;
end process;
---- SDA spike generator -------------------------
process
begin
if ENDSIM = false then
uniform(seed1, seed2, rand_sda); -- generate random number
sda_spike_should_happen := rand_sda;
uniform(seed1, seed2, rand_sda); -- generate random number
sda_spike_duration := integer(rand_sda*MAX_SPIKE_DURATION);
uniform(seed1, seed2, rand_sda); -- generate random number
timeout_after_sda_spike := integer(rand_sda*MAX_TIMEOUT_AFTER_SPIKE);
if SDA_noise_on then
if sda_spike_should_happen < P_SPIKE then
if sda_pre_spike = '0' then
sda <= 'Z';
else
sda <= '0';
end if;
else
sda <= sda_pre_spike;
end if;
end if;
wait for sda_spike_duration * 1 ns;
sda <= sda_pre_spike;
wait for timeout_after_sda_spike * 1 ns;
else
wait;
end if;
end process;
----------------------------------------------------------
-- Save data received from the master in a register
----------------------------------------------------------
process (clk) is
begin
if rising_edge(clk) then
if data_valid = '1' then
data_from_master_reg <= data_from_master;
end if;
end if;
end process;
----- Test vector generation -------------------------------------------
TESTS : process is
-- half clock
procedure i2c_wait_half_clock is
begin
for i in 0 to T_HALF loop
wait until rising_edge(clk);
end loop;
end procedure i2c_wait_half_clock;
-- quarter clock
procedure i2c_wait_quarter_clock is
begin
for i in 0 to T_QUARTER loop
wait until rising_edge(clk);
end loop;
end procedure i2c_wait_quarter_clock;
-- Write Bit
procedure i2c_send_bit (
constant a_bit : in std_logic) is
begin
scl_pre_spike <= '0';
if a_bit = '0' then
sda_pre_spike <= '0';
else
sda_pre_spike <= 'Z';
end if;
i2c_wait_quarter_clock;
scl_pre_spike <= 'Z';
i2c_wait_half_clock;
scl_pre_spike <= '0';
i2c_wait_quarter_clock;
end procedure i2c_send_bit;
-- Read Bit
procedure i2c_receive_bit (
variable a_bit : out std_logic) is
begin
scl_pre_spike <= '0';
sda_pre_spike <= 'Z';
i2c_wait_quarter_clock;
scl_pre_spike <= 'Z';
i2c_wait_quarter_clock;
if sda = '0' then
a_bit := '0';
else
a_bit := '1';
end if;
i2c_wait_quarter_clock;
scl_pre_spike <= '0';
i2c_wait_quarter_clock;
end procedure i2c_receive_bit;
-- Write Byte
procedure i2c_send_byte (
constant a_byte : in std_logic_vector(7 downto 0)) is
begin
for i in 7 downto 0 loop
i2c_send_bit(a_byte(i));
end loop;
end procedure i2c_send_byte;
-- Address
procedure i2c_send_address (
constant address : in std_logic_vector(6 downto 0)) is
begin
for i in 6 downto 0 loop
i2c_send_bit(address(i));
end loop;
end procedure i2c_send_address;
-- Read Byte
procedure i2c_receive_byte (
signal a_byte : out std_logic_vector(7 downto 0)) is
variable a_bit : std_logic;
variable accu : std_logic_vector(7 downto 0) := (others => '0');
begin
for i in 7 downto 0 loop
i2c_receive_bit(a_bit);
accu(i) := a_bit;
end loop;
a_byte <= accu;
end procedure i2c_receive_byte;
-- START
procedure i2c_start is
begin
scl_pre_spike <= 'Z';
sda_pre_spike <= '0';
i2c_wait_half_clock;
scl_pre_spike <= 'Z';
i2c_wait_quarter_clock;
scl_pre_spike <= '0';
i2c_wait_quarter_clock;
end procedure i2c_start;
-- STOP
procedure i2c_stop is
begin
scl_pre_spike <= '0';
sda_pre_spike <= '0';
i2c_wait_quarter_clock;
scl_pre_spike <= 'Z';
i2c_wait_quarter_clock;
sda_pre_spike <= 'Z';
i2c_wait_half_clock;
i2c_wait_half_clock;
end procedure i2c_stop;
-- send write
procedure i2c_set_write is
begin
i2c_send_bit('0');
end procedure i2c_set_write;
-- send read
procedure i2c_set_read is
begin
i2c_send_bit('1');
end procedure i2c_set_read;
-- read ACK
procedure i2c_read_ack (signal ack : out std_logic) is
begin
scl_pre_spike <= '0';
sda_pre_spike <= 'Z';
i2c_wait_quarter_clock;
scl_pre_spike <= 'Z';
if sda = '0' then
ack <= '1';
else
ack <= '0';
assert false report "No ACK received: expected '0'" severity note;
end if;
i2c_wait_half_clock;
scl_pre_spike <= '0';
i2c_wait_quarter_clock;
end procedure i2c_read_ack;
-- write NACK
procedure i2c_write_nack is
begin
scl_pre_spike <= '0';
sda_pre_spike <= 'Z';
i2c_wait_quarter_clock;
scl_pre_spike <= 'Z';
i2c_wait_half_clock;
scl_pre_spike <= '0';
i2c_wait_quarter_clock;
end procedure i2c_write_nack;
-- write ACK
procedure i2c_write_ack is
begin
scl_pre_spike <= '0';
sda_pre_spike <= '0';
i2c_wait_quarter_clock;
scl_pre_spike <= 'Z';
i2c_wait_half_clock;
scl_pre_spike <= '0';
i2c_wait_quarter_clock;
end procedure i2c_write_ack;
-- write to I2C bus
procedure i2c_write (
constant address : in std_logic_vector(6 downto 0);
constant data : in std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_write;
state_dbg <= 3;
-- dummy read ACK--don't care, because we are testing
-- I2C minion
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
ack <= '0';
return;
end if;
state_dbg <= 4;
i2c_send_byte(data);
state_dbg <= 5;
i2c_read_ack(ack);
state_dbg <= 6;
i2c_stop;
end procedure i2c_write;
-- write to I2C bus
procedure i2c_quick_write (
constant address : in std_logic_vector(6 downto 0);
constant data : in std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_write;
state_dbg <= 3;
-- dummy read ACK--don't care, because we are testing
-- I2C minion
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
ack <= '0';
return;
end if;
state_dbg <= 4;
i2c_send_byte(data);
state_dbg <= 5;
i2c_read_ack(ack);
scl_pre_spike <= '0';
sda_pre_spike <= '0';
i2c_wait_quarter_clock;
scl_pre_spike <= 'Z';
sda_pre_spike <= 'Z';
i2c_wait_quarter_clock;
end procedure i2c_quick_write;
-- read I2C bus
procedure i2c_write_bytes (
constant address : in std_logic_vector(6 downto 0);
constant nof_bytes : in integer range 0 to 1023) is
variable data : std_logic_vector(7 downto 0) := (others => '0');
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_write;
state_dbg <= 3;
i2c_read_ack(ack);
if ack = '0' then
i2c_stop;
return;
end if;
ack <= '0';
for i in 0 to nof_bytes-1 loop
state_dbg <= 4;
i2c_send_byte(std_logic_vector(to_unsigned(i, 8)));
state_dbg <= 5;
i2c_read_ack(ack);
if ack = '0' then
i2c_stop;
return;
end if;
ack <= '0';
end loop;
state_dbg <= 6;
i2c_stop;
end procedure i2c_write_bytes;
-- read from I2C bus
procedure i2c_read (
constant address : in std_logic_vector(6 downto 0);
signal data : out std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_read;
state_dbg <= 3;
-- dummy read ACK--don't care, because we are testing
-- I2C minion
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
return;
end if;
ack <= '0';
state_dbg <= 4;
i2c_receive_byte(data);
state_dbg <= 5;
i2c_write_nack;
state_dbg <= 6;
i2c_stop;
end procedure i2c_read;
-- read from I2C bus
procedure i2c_quick_read (
constant address : in std_logic_vector(6 downto 0);
signal data : out std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_read;
state_dbg <= 3;
-- dummy read ACK--don't care, because we are testing
-- I2C minion
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
return;
end if;
ack <= '0';
state_dbg <= 4;
i2c_receive_byte(data);
state_dbg <= 5;
i2c_write_nack;
scl_pre_spike <= '0';
sda_pre_spike <= '0';
i2c_wait_quarter_clock;
scl_pre_spike <= 'Z';
sda_pre_spike <= 'Z';
i2c_wait_quarter_clock;
end procedure i2c_quick_read;
-- read I2C bus
procedure i2c_read_bytes (
constant address : in std_logic_vector(6 downto 0);
constant nof_bytes : in integer range 0 to 1023;
signal data : out std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_read;
state_dbg <= 3;
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
return;
end if;
for i in 0 to nof_bytes-1 loop
-- dummy read ACK--don't care, because we are testing
-- I2C minion
state_dbg <= 4;
i2c_receive_byte(data);
state_dbg <= 5;
if i < nof_bytes-1 then
i2c_write_ack;
else
i2c_write_nack;
end if;
end loop;
state_dbg <= 6;
i2c_stop;
end procedure i2c_read_bytes;
begin
--------------------------------------------------------
-- Turn on noise on SCL
--------------------------------------------------------
SCL_noise_on := true;
SDA_noise_on := false;
print("");
print("------------------------------------------------------------");
print("----------------- I2C_minion_TB_001_noisy_scl --------------");
print("------------------------------------------------------------");
scl_pre_spike <= 'Z';
sda_pre_spike <= 'Z';
print("----------------- Testing a single write ------------------");
i2c_write("0000011", "11111111");
assert data_from_master_reg = "11111111"
report "test: 0 not passed "
severity warning;
print("----------------- Testing a single write ------------------");
i2c_write("0000011", "11111010");
assert data_from_master_reg = "11111010"
report "test: 0 not passed "
severity warning;
print("----------------- Testing repeated writes -----------------");
wait until rising_edge(clk);
for i in 0 to 127 loop
i2c_write("0000011", std_logic_vector(to_unsigned(i, 8)));
assert i = to_integer(unsigned(data_from_master_reg))
report "writing test: " & integer'image(i) & " not passed "
severity warning;
end loop;
print("----------------- Testing repeated reads ------------------");
for i in 0 to 127 loop
data_to_master <= std_logic_vector(to_unsigned(i, 8));
i2c_read("0000011", received_data);
assert i = to_integer(unsigned(received_data))
report "reading test: " & integer'image(i) & " not passed "
severity warning;
end loop;
--------------------------------------------------------
-- Quick read/write
--------------------------------------------------------
print("----------------- Testing quick write --------------------");
i2c_quick_write("0000011", "10101010");
i2c_quick_write("0000011", "10101011");
i2c_quick_write("0000011", "10101111");
data_to_master <= std_logic_vector(to_unsigned(255, 8));
i2c_quick_read("0000011", received_data);
state_dbg <= 6;
i2c_stop;
--------------------------------------------------------
-- Reads, writes from wrong minion addresses
-- this should cause some assertion notes (needs manual
-- confirmation)
--------------------------------------------------------
print("----------------- Testing wrong addresses -----------------");
print("-> The following 3 tests should all fail");
print("[0] ---------------");
i2c_write_bytes("1000011", 100);
print("[1] ---------------");
i2c_read ("0101101", received_data);
print("[2] ---------------");
i2c_read_bytes ("0000010", 300, received_data);
wait until rising_edge(clk);
ENDSIM := true;
print("Simulation end...");
print("");
wait;
end process;
end Testbench;
|
mit
|
d2c703b95c920cca66e0aa5bc4cd114c
| 0.506428 | 3.590456 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_rtoi.vhd
| 3 | 1,181 |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test real to integer conversion
library ieee;
use ieee.numeric_std.all;
entity vhdl_rtoi is
end;
architecture test of vhdl_rtoi is
signal a, b, c, d : integer;
begin
-- test rounding
a <= integer(2.3); -- should be 2
b <= integer(3.7); -- should be 4
c <= integer(4.5); -- should be 5
d <= integer(8.1 * 2.1); -- ==17.01, should be 17
end test;
|
gpl-2.0
|
8b927dceba92e6ef63088673aeaab03c
| 0.709568 | 3.690625 | false | true | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/ll_fifo_pkg.vhd
| 1 | 9,769 |
-------------------------------------------------------------------------------
--
-- Module : ll_fifo_pkg.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Top Level Package File for LocalLink FIFO
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ll_fifo_pkg is
component ll_fifo is
generic (
MEM_TYPE : integer := 0; -- 0 choose BRAM,
-- 1 choose DRAM
BRAM_MACRO_NUM : integer := 2; -- For BRAM only
DRAM_DEPTH : integer := 16; -- For DRAM only
WR_DWIDTH : integer := 32; -- FIFO write data
-- width, allowable
-- values are
-- 8, 16, 32, 64, 128.
RD_DWIDTH : integer := 32; -- FIFO read data
-- width, allowable
-- values are
-- 8, 16, 32, 64, 128.
RD_REM_WIDTH : integer := 2; -- Width of remaining
-- data to receiving
WR_REM_WIDTH : integer := 2; -- Width of remaining
-- data to transmitting
USE_LENGTH : boolean := true; -- length fifo option
glbtm : time := 1 ns); -- global timing delay for simulation
port (
-- Reset
areset_in: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
-- Interface to downstream user application
data_out: out std_logic_vector(0 to RD_DWIDTH-1);
rem_out: out std_logic_vector(0 to RD_REM_WIDTH-1);
sof_out_n: out std_logic;
eof_out_n: out std_logic;
src_rdy_out_n: out std_logic;
dst_rdy_in_n: in std_logic;
-- Interface to upstream user application
data_in: in std_logic_vector(0 to WR_DWIDTH-1);
rem_in: in std_logic_vector(0 to WR_REM_WIDTH-1);
sof_in_n: in std_logic;
eof_in_n: in std_logic;
src_rdy_in_n: in std_logic;
dst_rdy_out_n: out std_logic;
-- FIFO status signals
fifostatus_out: out std_logic_vector(0 to 3);
-- Length Status
len_rdy_out: out std_logic;
len_out: out std_logic_vector(0 to 15);
len_err_out: out std_logic);
end component;
component ll_fifo_BRAM is
generic (
BRAM_MACRO_NUM : integer:=1; --Number of BRAMs. Values Allowed: 1, 2, 4, 8, 16
WR_DWIDTH : integer:= 8; --FIFO write data width, allowable values are
--8, 16, 32, 64, 128.
RD_DWIDTH : integer:= 8; --FIFO read data width, allowable values are
--8, 16, 32, 64, 128.
WR_REM_WIDTH : integer:= 1; --Width of remaining data to transmitting side
RD_REM_WIDTH : integer:= 1; --Width of remaining data to receiving side
USE_LENGTH: boolean :=true;
glbtm : time:= 1 ns);
port (
-- Reset
reset: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
-- interface to upstream user application
data_in: in std_logic_vector(WR_DWIDTH-1 downto 0);
rem_in: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
sof_in_n: in std_logic;
eof_in_n: in std_logic;
src_rdy_in_n: in std_logic;
dst_rdy_out_n: out std_logic;
-- interface to downstream user application
data_out: out std_logic_vector(RD_DWIDTH-1 downto 0);
rem_out: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
sof_out_n: out std_logic;
eof_out_n: out std_logic;
src_rdy_out_n: out std_logic;
dst_rdy_in_n: in std_logic;
-- FIFO status signals
fifostatus_out: out std_logic_vector(3 downto 0);
-- Length Status
len_rdy_out: out std_logic;
len_out: out std_logic_vector(15 downto 0);
len_err_out: out std_logic);
end component;
component ll_fifo_DRAM is
generic (
DRAM_DEPTH : integer:= 16; --FIFO depth, default is
--16,allowable values are
--16, 32, 64, 128.
WR_DWIDTH : integer:= 8; --FIFO write data width,
--allowable values are
--8, 16, 32, 64, 128.
RD_DWIDTH : integer:= 8; --FIFO read data width,
--allowable values are
--8, 16, 32, 64, 128.
RD_REM_WIDTH : integer:= 1; --Width of remaining data
--to receiving side
WR_REM_WIDTH : integer:= 1; --Width of remaining data
--to transmitting side
USE_LENGTH : boolean := true;
glbtm : time:= 1 ns );
port (
-- Reset
reset: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
-- interface to upstream user application
data_in: in std_logic_vector(WR_DWIDTH-1 downto 0);
rem_in: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
sof_in_n: in std_logic;
eof_in_n: in std_logic;
src_rdy_in_n: in std_logic;
dst_rdy_out_n: out std_logic;
-- interface to downstream user application
data_out: out std_logic_vector(RD_DWIDTH-1 downto 0);
rem_out: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
sof_out_n: out std_logic;
eof_out_n: out std_logic;
src_rdy_out_n: out std_logic;
dst_rdy_in_n: in std_logic;
-- FIFO status signals
fifostatus_out: out std_logic_vector(3 downto 0);
-- Length Status
len_rdy_out: out std_logic;
len_out: out std_logic_vector(15 downto 0);
len_err_out: out std_logic);
end component;
end ll_fifo_pkg;
|
gpl-3.0
|
d95eb75525335878459a57036ad6c7a4
| 0.395332 | 5.012314 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_fifo.vhd
| 1 | 44,151 |
-------------------------------------------------------------------------------
--
-- Module : BRAM_fifo.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Asynchronous FIFO implemented in Block SelectRAM.
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fifo_u.all;
use work.BRAM_fifo_pkg.all;
entity BRAM_fifo is
generic (
BRAM_MACRO_NUM : integer := 1; --Number of BRAM Blocks.
--Allowed: 1, 2, 4, 8, 16
WR_DWIDTH : integer := 32; --FIFO write data width.
--Allowed: 8, 16, 32, 64
RD_DWIDTH : integer := 32; --FIFO read data width.
--Allowed: 8, 16, 32, 64
WR_REM_WIDTH : integer := 2; --log2(WR_DWIDTH/8)
RD_REM_WIDTH : integer := 2; --log2(RD_DWIDTH/8)
USE_LENGTH : boolean := true;
glbtm : time := 1 ns
);
port (
-- Reset
fifo_gsr_in: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
read_data_out: out std_logic_vector(RD_DWIDTH-1 downto 0);
read_rem_out: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
read_sof_out_n: out std_logic;
read_eof_out_n: out std_logic;
read_enable_in: in std_logic;
write_data_in: in std_logic_vector(WR_DWIDTH-1 downto 0);
write_rem_in: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
write_sof_in_n: in std_logic;
write_eof_in_n: in std_logic;
write_enable_in: in std_logic;
-- FifO status signals
fifostatus_out: out std_logic_vector(3 downto 0);
full_out: out std_logic;
empty_out: out std_logic;
data_valid_out: out std_logic;
-- Length Control
len_out: out std_logic_vector(15 downto 0);
len_rdy_out: out std_logic;
len_err_out: out std_logic);
end BRAM_fifo;
architecture BRAM_fifo_hdl of BRAM_fifo is
constant MEM_IDX : integer := SQUARE2(BRAM_MACRO_NUM);
constant RD_ADDR_WIDTH : integer := GET_ADDR_MAJOR_WIDTH(
RD_DWIDTH,WR_DWIDTH,0) +MEM_IDX;
constant WR_ADDR_WIDTH : integer := GET_ADDR_MAJOR_WIDTH(
RD_DWIDTH,WR_DWIDTH,1) +MEM_IDX;
constant ADDR_MINOR_WIDTH : integer := GET_ADDR_MINOR_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant RD_ADDR_FULL_WIDTH : integer := GET_ADDR_FULL_B(RD_DWIDTH,
WR_DWIDTH, 0) + MEM_IDX;
constant WR_ADDR_FULL_WIDTH : integer := GET_ADDR_FULL_B(RD_DWIDTH,
WR_DWIDTH, 1) + MEM_IDX;
constant RD_REM_WIDTH_P : integer := GET_REM_WIDTH(RD_REM_WIDTH);
constant WR_REM_WIDTH_P : integer := GET_REM_WIDTH(WR_REM_WIDTH);
constant WR_PAR_WIDTH : integer := GET_PAR_WIDTH(WR_DWIDTH);
constant RD_PAR_WIDTH : integer := GET_PAR_WIDTH(RD_DWIDTH);
constant RD_MINOR_HIGH: integer := POWER2(ADDR_MINOR_WIDTH);
constant REM_SEL_HIGH_VALUE : integer := GET_HIGH_VALUE(
RD_REM_WIDTH,WR_REM_WIDTH);
constant REM_SEL_HIGH1 : integer := POWER2(REM_SEL_HIGH_VALUE);
constant WR_SOF_EOF_WIDTH : integer := GET_WR_SOF_EOF_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant RD_SOF_EOF_WIDTH : integer := GET_RD_SOF_EOF_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant WR_CTRL_REM_WIDTH : integer := GET_WR_CTRL_REM_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant RD_CTRL_REM_WIDTH : integer := GET_RD_CTRL_REM_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant C_WR_ADDR_WIDTH : integer := GET_C_WR_ADDR_WIDTH(RD_DWIDTH,
WR_DWIDTH, BRAM_MACRO_NUM);
constant C_RD_ADDR_WIDTH : integer := GET_C_RD_ADDR_WIDTH(RD_DWIDTH,
WR_DWIDTH, BRAM_MACRO_NUM);
constant ratio1 : integer := GET_RATIO(RD_DWIDTH, WR_DWIDTH,
WR_SOF_EOF_WIDTH);
constant WR_PAD_WIDTH : integer := GET_WR_PAD_WIDTH(RD_DWIDTH, WR_DWIDTH,
C_WR_ADDR_WIDTH,
WR_ADDR_FULL_WIDTH, WR_ADDR_WIDTH);
constant RD_PAD_WIDTH : integer := GET_RD_PAD_WIDTH(C_RD_ADDR_WIDTH,
RD_ADDR_FULL_WIDTH);
constant C_RD_TEMP_WIDTH : integer := GET_C_RD_TEMP_WIDTH(RD_DWIDTH, WR_DWIDTH);
constant C_WR_TEMP_WIDTH : integer := GET_C_WR_TEMP_WIDTH(RD_DWIDTH, WR_DWIDTH);
constant NUM_DIV : integer := GET_NUM_DIV(RD_DWIDTH, WR_DWIDTH);
constant WR_EN_FACTOR : integer := GET_WR_EN_FACTOR(NUM_DIV, BRAM_MACRO_NUM);
constant RDDWdivWRDW : integer := GET_RDDWdivWRDW(RD_DWIDTH, WR_DWIDTH);
constant LEN_BYTE_RATIO : integer := WR_DWIDTH/8; --number of bytes in the write word
constant LEN_IFACE_SIZE : integer := 16;
constant LEN_COUNT_SIZE : integer := 14;
type rd_data_vec_type is array(0 to BRAM_MACRO_NUM-1) of
std_logic_vector(RD_DWIDTH-1 downto 0);
type rd_sof_eof_vec_type is array(0 to BRAM_MACRO_NUM-1) of
std_logic_vector(RD_SOF_EOF_WIDTH-1 downto 0);
type rd_ctrl_rem_vec_type is array(0 to BRAM_MACRO_NUM-1) of
std_logic_vector(RD_CTRL_REM_WIDTH-1 downto 0);
type rd_ctrl_vec_type is array(0 to BRAM_MACRO_NUM-1) of
std_logic_vector(C_RD_TEMP_WIDTH-1 downto 0);
signal rd_clk: std_logic;
signal wr_clk: std_logic;
signal rd_en: std_logic;
signal wr_en: std_logic;
signal fifo_gsr: std_logic;
signal rd_data: std_logic_vector(RD_DWIDTH-1 downto 0);
signal wr_data: std_logic_vector(WR_DWIDTH-1 downto 0);
signal wr_rem: std_logic_vector(WR_REM_WIDTH_P-1 downto 0);
signal wr_rem_plus_one: std_logic_vector(WR_REM_WIDTH_P downto 0);
signal wr_sof_n: std_logic;
signal wr_eof_n: std_logic;
signal rd_rem: std_logic_vector(RD_REM_WIDTH_P-1 downto 0);
signal rd_sof_n: std_logic;
signal rd_eof_n: std_logic;
signal min_addr1: integer := 0;
signal min_addr2: integer := 0;
signal rem_sel1: integer := 0;
signal rem_sel2: integer := 0;
signal full: std_logic;
signal empty: std_logic;
signal rd_addr_full: std_logic_vector(RD_PAD_WIDTH+RD_ADDR_FULL_WIDTH-1 downto 0);
signal rd_addr: std_logic_vector(RD_PAD_WIDTH + RD_ADDR_WIDTH -1 downto 0);
signal rd_addr_minor: std_logic_vector(ADDR_MINOR_WIDTH-1 downto 0);
signal read_addrgray: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal read_nextgray: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal read_lastgray: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal wr_addr: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal wr_addr_full: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_FULL_WIDTH-1 downto 0);
signal wr_addr_minor: std_logic_vector(ADDR_MINOR_WIDTH-1 downto 0);
signal wr_addrgray: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal write_nextgray: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal fifostatus: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal rd_allow: std_logic;
signal rd_allow_minor: std_logic;
signal wr_allow: std_logic;
signal wr_allow_minor: std_logic;
signal full_allow: std_logic;
signal empty_allow: std_logic;
signal emptyg: std_logic;
signal fullg: std_logic;
signal ecomp: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal fcomp: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal emuxcyo: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal fmuxcyo: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal read_truegray: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal rag_writesync: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal ra_writesync: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal wr_addrr: std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
signal data_valid: std_logic;
-- Length Control FIFO --
signal wr_len: std_logic_vector(LEN_IFACE_SIZE-1 downto 0);
signal wr_len_p: std_logic_vector(LEN_IFACE_SIZE-1 downto 0);
signal wr_len_r: std_logic_vector(LEN_IFACE_SIZE-1 downto 0);
signal len_byte_cnt: std_logic_vector(LEN_COUNT_SIZE+3 downto 0);
signal len_byte_cnt_plus_rem: std_logic_vector(LEN_COUNT_SIZE+3 downto 0);
signal rd_len: std_logic_vector(LEN_IFACE_SIZE-1 downto 0);
signal len_word_cnt: std_logic_vector(LEN_COUNT_SIZE-1 downto 0);
signal len_byte_cnt_plus_rem_with_carry: std_logic_vector(LEN_COUNT_SIZE+4 downto 0);
signal total_len_byte_cnt_with_carry: std_logic_vector(LEN_COUNT_SIZE+4 downto 0);
signal len_word_cnt_with_carry: std_logic_vector(LEN_COUNT_SIZE downto 0);
signal len_byte_cnt_with_carry: std_logic_vector(LEN_COUNT_SIZE+4 downto 0);
signal carry1, carry2, carry3, carry4 : std_logic;
signal len_counter_overflow: std_logic;
signal rd_len_rdy_2: std_logic_vector(1 downto 0);
signal rd_len_rdy: std_logic;
signal rd_len_rdy_p: std_logic;
signal rd_len_rdy_p_p: std_logic;
-- we only use wr_len_rdy(0).
signal wr_len_rdy: std_logic_vector(1 downto 0);
signal wr_len_rdy_r: std_logic_vector(1 downto 0);
signal wr_len_rdy_p: std_logic_vector(1 downto 0);
signal len_wr_allow: std_logic;
signal len_wr_allow_r: std_logic;
signal len_wr_allow_p: std_logic;
signal len_rd_allow: std_logic;
signal len_rd_allow_temp: std_logic;
signal len_wr_addr: std_logic_vector(9 downto 0);
signal len_rd_addr: std_logic_vector(9 downto 0);
signal len_err: std_logic;
-- Inframe signals
signal inframe: std_logic;
signal inframe_i: std_logic;
signal fifo_gsr_n: std_logic;
signal gnd_bus: std_logic_vector(128 downto 0);
signal gnd: std_logic;
signal pwr: std_logic;
component MUXCY_L
port (
DI: in std_logic;
CI: in std_logic;
S: in std_logic;
LO: out std_logic);
end component;
begin
---------------------------------------------------------------------------
-- FIFO clk and enable signals --
---------------------------------------------------------------------------
rd_clk <= read_clock_in;
wr_clk <= write_clock_in;
fifo_gsr <= fifo_gsr_in;
wr_en <= write_enable_in;
rd_en <= read_enable_in;
wr_rem <= write_rem_in;
wr_sof_n <= write_sof_in_n;
wr_eof_n <= write_eof_in_n;
read_rem_out <= rd_rem;
read_sof_out_n <= rd_sof_n;
read_eof_out_n <= rd_eof_n;
data_valid_out <= data_valid;
wr_data <= revByteOrder(write_data_in);
read_data_out <= revByteOrder(rd_data);
min_addr1 <= slv2int(rd_addr_minor);
---------------------------------------------------------------------------
-- FIFO Status signals --
---------------------------------------------------------------------------
empty_out <= empty;
full_out <= full;
fifostatus_out <= fifostatus(WR_ADDR_WIDTH-1 downto WR_ADDR_WIDTH-4);
---------------------------------------------------------------------------
-- Misellainous --
---------------------------------------------------------------------------
gnd <= '0';
gnd_bus <= (others => '0');
pwr <= '1';
---------------------------------------------------------------------------
--------------------------INFRAME signal generation------------------------
-- This signal is used as a flag to indicate whether the incoming data --
-- are part of a frame. Since LL_FIFO is a packet FIFO so it will only --
-- store packets, not random data without frame delimiter. If the data --
-- is not part of the frame, it will be dropped. The inframe_i signal --
-- will be assert the cycle after the sof_n asserts. If the frame is --
-- only a cycle long then inframe_i signal won't be asserted for that --
-- particular frame to prevent misleading information. However, the --
-- inframe signal will include wr_sof_n to give the accurate status of --
-- the frame, and which will be used for wr_allow. --
---------------------------------------------------------------------------
inframe_i_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
inframe_i <= '0';
elsif (wr_clk'EVENT and wr_clk = '1') then
if WR_DWIDTH >= RD_DWIDTH then
if inframe_i = '0' then
inframe_i <= wr_allow and not wr_sof_n and wr_eof_n after glbtm;
elsif (inframe_i = '1' and wr_allow = '1' and wr_eof_n = '0') then
inframe_i <= '0' after glbtm;
end if;
else
if inframe_i = '0' then
inframe_i <= wr_allow_minor and not wr_sof_n and wr_eof_n after glbtm;
elsif (inframe_i = '1' and wr_allow_minor = '1' and wr_eof_n = '0') then
inframe_i <= '0' after glbtm;
end if;
end if;
end if;
end process inframe_i_proc;
inframe <= not wr_sof_n or inframe_i;
-------------------------------------------------------------------------------
---------------------------ALLOW SIGNALS GENERATION----------------------------
-- Allow flags determine whether FifO control logic can operate. If rd_en --
-- is driven high, and the FifO is not empty, then Reads are allowed. --
-- Similarly, if the wr_en signal is high, and the FifO is not full_out, --
-- then Writes are allowed. We need to extend the enable signals of reading --
-- for one clock cycle, so that we won't miss the last data. --
-- The data_valid Signal is used to indicate whether the data coming up --
-- with valid. It's used to accomodate different data width problem and --
-- also used for src_ready signal. --
-------------------------------------------------------------------------------
GEN1: if RD_DWIDTH < WR_DWIDTH generate
---------------------------------------------------------------------------
-- Address and enable for RAM assignment (GEN1) --
---------------------------------------------------------------------------
rd_addr_full <= rd_addr & rd_addr_minor;
wr_addr_full <= wr_addr;
rd_allow_minor <= (rd_en and not empty);
rd_allow <= rd_allow_minor and (boolean_to_std_logic(allOnes(rd_addr_minor)));
wr_allow <= (wr_en and not full) and inframe;
full_allow <= (full or wr_en);
empty_allow <= rd_allow or empty;
---------------------------------------------------------------------------
-- Data Valid Signal generation (GEN1) --
---------------------------------------------------------------------------
data_valid_proc1: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
data_valid <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow_minor = '1') then
if (min_addr1 /= 0 and rd_eof_n = '0') then
data_valid <= '0' after glbtm;
else
if data_valid = '0' and min_addr1 /= 0 then
data_valid <= '0' after glbtm;
else
data_valid <= '1' after glbtm;
end if;
end if;
--should extend data_valid when user halts read, do this when FIFO still contains data
elsif data_valid = '1' and (empty = '0' or rd_eof_n = '0') then
data_valid <= '1' after glbtm;
else
data_valid <= '0' after glbtm;
end if;
end if;
end process data_valid_proc1;
end generate GEN1;
GEN2: if RD_DWIDTH > WR_DWIDTH generate
---------------------------------------------------------------------------
-- Address and enable for RAM assignment (GEN2) --
---------------------------------------------------------------------------
wr_addr_full <= wr_addr & wr_addr_minor;
rd_addr_full <= rd_addr;
wr_allow_minor <= (wr_en and not full) and inframe;
wr_allow <= wr_allow_minor and (boolean_to_std_logic(allOnes(wr_addr_minor)) or not wr_eof_n);
rd_allow <= (rd_en and not empty);
empty_allow <= (empty or rd_en);
full_allow <= wr_allow or full;
---------------------------------------------------------------------------
-- Data Valid Signal generation (GEN2) --
---------------------------------------------------------------------------
data_valid_proc2: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
data_valid <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
if rd_en = '0' and data_valid = '1' then --should extend data_valid
--when user halts read,
--so data won't get lost.
data_valid <= '1' after glbtm;
else
data_valid <= rd_allow after glbtm;
end if;
end if;
end process data_valid_proc2;
end generate GEN2;
GEN3: if RD_DWIDTH = WR_DWIDTH generate
---------------------------------------------------------------------------
-- Address and enable for RAM assignment (GEN3) --
---------------------------------------------------------------------------
wr_allow <= (wr_en and not full) and inframe;
rd_allow <= (rd_en and not empty);
empty_allow <= (empty or rd_en);
full_allow <= wr_en or full;
---------------------------------------------------------------------------
-- Data Valid Signal generation (GEN3) --
---------------------------------------------------------------------------
data_valid_proc3: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
data_valid <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
if rd_en = '0' and data_valid = '1' then
data_valid <= '1' after glbtm;
else
data_valid <= rd_allow after glbtm;
end if;
end if;
end process data_valid_proc3;
end generate GEN3;
--------------------------------------------------------------------------
-- Data and Control FIFO (BRAM Macros)
--------------------------------------------------------------------------
BRAM_macro_inst: BRAM_macro
generic map (
BRAM_MACRO_NUM => BRAM_MACRO_NUM,
WR_DWIDTH => WR_DWIDTH,
RD_DWIDTH => RD_DWIDTH,
WR_REM_WIDTH => WR_REM_WIDTH,
RD_REM_WIDTH => RD_REM_WIDTH,
RD_PAD_WIDTH => RD_PAD_WIDTH,
RD_ADDR_FULL_WIDTH => RD_ADDR_FULL_WIDTH,
RD_ADDR_WIDTH => RD_ADDR_WIDTH,
ADDR_MINOR_WIDTH => ADDR_MINOR_WIDTH,
WR_PAD_WIDTH => WR_PAD_WIDTH,
WR_ADDR_FULL_WIDTH => WR_ADDR_FULL_WIDTH,
WR_ADDR_WIDTH => WR_ADDR_WIDTH,
glbtm => glbtm )
port map (
fifo_gsr => fifo_gsr,
wr_clk => wr_clk,
rd_clk => rd_clk,
rd_allow => rd_allow,
rd_allow_minor => rd_allow_minor,
rd_addr_full => rd_addr_full,
rd_addr_minor => rd_addr_minor,
rd_addr => rd_addr,
rd_data => rd_data,
rd_rem => rd_rem,
rd_sof_n => rd_sof_n,
rd_eof_n => rd_eof_n,
wr_allow => wr_allow,
wr_allow_minor => wr_allow_minor,
wr_addr => wr_addr,
wr_addr_minor => wr_addr_minor,
wr_addr_full => wr_addr_full,
wr_data => wr_data,
wr_rem => wr_rem,
wr_sof_n => wr_sof_n,
wr_eof_n => wr_eof_n);
--------------------------------------------------------------------------
-- Length FIFO --
--------------------------------------------------------------------------
use_length_gen1: if USE_LENGTH = false generate
---------------------------------------------------------------------------
-- When the user does not want to use the Length FIFO, the output of --
-- the length count will always be zero and the len_rdy signal will --
-- always be asserted. --
---------------------------------------------------------------------------
len_out <= (others => '0');
len_rdy_out <= '0';
len_err_out <= '0';
end generate use_length_gen1;
fifo_gsr_n <= not fifo_gsr;
use_length_gen2: if USE_LENGTH = true generate
---------------------------------------------------------------------------
-- The BlockRAM that is used to store length information of the data --
-- Note that the read side of the BRAM is clocked but is always enabled.--
-- This is because the length ready signal (rd_len_rdy) and the --
-- corresponding length information must be seen as soon as the wr_eof_n--
-- enables the wr_len_rdy signal.
-- To save space, the length FIFO only used 14 bits to store the number --
-- of bytes. This is sufficient enough even for the largest frame --
-- (Jumbo Frame) possible.
---------------------------------------------------------------------------
len_bram: RAMB16_S18_S18
port map (
ADDRA => len_rd_addr, ADDRB => len_wr_addr,
DIA => gnd_bus(17 downto 2), DIPA => gnd_bus(1 downto 0),
DIB => wr_len_r, DIPB => wr_len_rdy_r,
WEA => rd_len_rdy, WEB => len_wr_allow_r, CLKA => rd_clk,
CLKB => wr_clk, SSRA => fifo_gsr, SSRB => fifo_gsr,
ENA => pwr, ENB => fifo_gsr_n,
DOA => rd_len, DOPA => rd_len_rdy_2);
---------------------------------------------------------------------------
-- Read length section of the Length FIFO --
---------------------------------------------------------------------------
len_out <= gnd & gnd & rd_len(13 downto 0);
len_rdy_out <= rd_len_rdy;
len_err_out <= len_err;
len_err_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_err <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
-- if (len_rd_addr = len_wr_addr) and (len_rd_flag = '1' or len_wr_flag = '1') then
if (len_rd_addr -1 = len_wr_addr) then
len_err <= '1' after glbtm;
end if;
end if;
end process len_err_proc;
---------------------------------------------------------------------------
-- The rd_len_rdy signal is pipelined for two cycles to allow clearing --
-- of the rd_len_rdy signal in the FIFO after it is being read so in the--
-- next wrap around, there will not be any residue value that sends the --
-- wrong rd_len_rdy signal. --
---------------------------------------------------------------------------
rd_len_rdy <= not rd_len_rdy_p_p and (rd_len_rdy_p);
len_rdy_pipeline_proc1: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rd_len_rdy_p <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
if rd_len_rdy_2(0) = '1' then
rd_len_rdy_p <= '1' after glbtm;
else
rd_len_rdy_p <= '0' after glbtm;
end if;
end if;
end process len_rdy_pipeline_proc1;
len_rdy_pipeline_proc2: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rd_len_rdy_p_p <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
rd_len_rdy_p_p <= rd_len_rdy_p after glbtm;
end if;
end process len_rdy_pipeline_proc2;
---------------------------------------------------------------------------
-- The enable signals for Length FIFO. The len_rd_allow signal is --
-- independent from the enable signals for reading data (read_enable) --
-- because user may need to read the len_rdy signal before assertes --
-- the data read enables. However, the write side of the length FIFO --
-- will need to depend on the write enable signal to ensure the validity--
-- of the data being written. --
---------------------------------------------------------------------------
len_allow_gen1: if (WR_DWIDTH >= RD_DWIDTH) generate
len_rd_allow <= rd_len_rdy;
len_wr_allow <= (not wr_eof_n) and wr_allow;
end generate len_allow_gen1;
len_allow_gen2: if (WR_DWIDTH < RD_DWIDTH) generate
len_rd_allow <= rd_len_rdy;
len_wr_allow <= (not wr_eof_n) and wr_allow_minor;
end generate len_allow_gen2;
---------------------------------------------------------------------------
-- Calculating the number of bytes being written into the FIFO (wr_len) --
-- the length counter (len_count) is incremented every cycle when a --
-- valid data is received and when it's not the end of the frame, that --
-- is, wr_eof_n is not equal to '0'. However, since the length count --
-- is always a cycle late and we are writing the length into the length --
-- FIFO at the same cycle as when wr_eof_n asserts. So the --
-- combinatorial logic that finalize the counting of byte length will --
-- add one more word to the calculation to make up for it. --
---------------------------------------------------------------------------
-- calculate data bytes in the remainder
wr_rem_plus_one <= '0' & wr_rem + '1';
-- add remainder into the length byte count
len_byte_cnt_plus_rem_with_carry <= '0' & len_byte_cnt + wr_rem_plus_one;
len_byte_cnt_plus_rem <= len_byte_cnt_plus_rem_with_carry(LEN_COUNT_SIZE+3 downto 0);
carry2 <= len_byte_cnt_plus_rem_with_carry(LEN_COUNT_SIZE+4);
-- calculate the total length byte count by adding one more data beat
-- to count for SOF under certain condition
total_len_byte_cnt_with_carry <= '0' & len_byte_cnt_plus_rem when wr_sof_n = '0' and len_wr_allow = '1' else
'0' & len_byte_cnt_plus_rem + conv_std_logic_vector(LEN_BYTE_RATIO, 5)
when wr_sof_n = '1' and len_wr_allow = '1' else
(others => '0');
wr_len <= total_len_byte_cnt_with_carry(LEN_IFACE_SIZE-1 downto 0);
carry1 <= not boolean_to_std_logic(allZeroes(total_len_byte_cnt_with_carry(LEN_COUNT_SIZE+4 downto LEN_IFACE_SIZE)));
wr_len_rdy <= gnd & (not wr_eof_n);
---------------------------------------------------------------------------
-- Pipeline the wr_len and wr_len_rdy, and detect counter overflow
---------------------------------------------------------------------------
len_pipeline_proc: process(wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_counter_overflow <= '0' after glbtm;
len_wr_allow_r <= '0' after glbtm;
wr_len_rdy_r <= "00" after glbtm;
wr_len_r <= (others => '0') after glbtm;
elsif (wr_clk'EVENT and wr_clk = '1') then
len_wr_allow_r <= len_wr_allow_p after glbtm;
wr_len_r <= bit_duplicate(len_counter_overflow ,LEN_IFACE_SIZE) or wr_len_p after glbtm;
wr_len_rdy_r <= wr_len_rdy_p after glbtm;
if (wr_sof_n = '0') then
len_counter_overflow <= '0' after glbtm;
elsif (carry1 = '1' or carry2 = '1' or carry3 = '1' or carry4 = '1') then
len_counter_overflow <= '1' after glbtm;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Need to pipeline the stage so it can align with the counter overflow --
-- signal. --
---------------------------------------------------------------------------
wr_len_pipline_proc: process(wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_len_p <= (others => '0');
wr_len_rdy_p <= "00";
len_wr_allow_p <= '0';
elsif (wr_clk'EVENT and wr_clk = '1') then
wr_len_p <= wr_len after glbtm;
wr_len_rdy_p <= wr_len_rdy after glbtm;
len_wr_allow_p <= len_wr_allow after glbtm;
end if;
end process wr_len_pipline_proc;
---------------------------------------------------------------------------
len_word_cnt <= len_word_cnt_with_carry(LEN_COUNT_SIZE-1 downto 0);
carry4 <= len_word_cnt_with_carry(LEN_COUNT_SIZE);
len_byte_cnt <= len_byte_cnt_with_carry(LEN_COUNT_SIZE+3 downto 0);
carry3 <= len_byte_cnt_with_carry(LEN_COUNT_SIZE+4);
-- only count data beats between SOF and EOF
len_counter_proc: process(wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_word_cnt_with_carry <= (others => '0'); -- unit is words
len_byte_cnt_with_carry <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (WR_DWIDTH >= RD_DWIDTH) then
if (wr_allow = '1') then
if (wr_sof_n = '0' or wr_eof_n = '0') then
len_word_cnt_with_carry <= (others => '0') after glbtm;
len_byte_cnt_with_carry <= (others => '0') after glbtm;
else
len_word_cnt_with_carry <= '0' & len_word_cnt + '1' after glbtm;
len_byte_cnt_with_carry <= conv_std_logic_vector
(slv2int(len_word_cnt)*LEN_BYTE_RATIO, LEN_COUNT_SIZE + 5 ) +
conv_std_logic_vector(LEN_BYTE_RATIO, 5)
after glbtm;
end if;
end if;
elsif (WR_DWIDTH < RD_DWIDTH) then
if (wr_allow_minor = '1') then
if (wr_sof_n = '0' or wr_eof_n = '0') then
len_word_cnt_with_carry <= (others => '0') after glbtm;
len_byte_cnt_with_carry <= (others => '0') after glbtm;
else
len_word_cnt_with_carry <= '0' & len_word_cnt + '1' after glbtm;
len_byte_cnt_with_carry <= conv_std_logic_vector
(slv2int(len_word_cnt)* LEN_BYTE_RATIO, LEN_COUNT_SIZE + 5 ) +
conv_std_logic_vector(LEN_BYTE_RATIO, 5)
after glbtm;
end if;
end if;
end if;
end if;
end process len_counter_proc;
---------------------------------------------------------------------------
inc_len_wr_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_wr_addr <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (len_wr_allow_r = '1') then
len_wr_addr <= len_wr_addr + '1' after glbtm;
end if;
end if;
end process inc_len_wr_proc;
---------------------------------------------------------------------------
inc_len_rd_addr_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_rd_addr <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (len_rd_allow = '1') then
len_rd_addr <= len_rd_addr + '1' after glbtm;
end if;
end if;
end process inc_len_rd_addr_proc;
end generate use_length_gen2;
-------------------------------------------------------------------------------
empty_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
empty <= '1';
elsif (rd_clk'EVENT and rd_clk = '1') then
if (empty_allow = '1') then
empty <= emptyg after glbtm;
end if;
end if;
end process empty_proc;
full_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
full <= '0';
elsif (wr_clk'EVENT and wr_clk = '1') then
if (full_allow = '1') then
full <= fullg after glbtm;
end if;
end if;
end process full_proc;
-------------------------------------------------------------------------------
inc_rd_addr_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rd_addr <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow = '1') then
rd_addr <= rd_addr + '1' after glbtm;
end if;
end if;
end process inc_rd_addr_proc;
-------------------------------------------------------------------------------
gray_conv_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
read_nextgray(RD_ADDR_WIDTH-1) <= '1';
read_nextgray(RD_ADDR_WIDTH-2 downto 0) <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow = '1') then
read_nextgray(RD_ADDR_WIDTH-1) <= rd_addr(RD_ADDR_WIDTH-1) after glbtm;
for i in RD_ADDR_WIDTH-2 downto 0 loop
read_nextgray(i) <= rd_addr(i+1) xor rd_addr(i) after glbtm;
end loop;
end if;
end if;
end process gray_conv_proc;
pip_proc1: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
read_addrgray(RD_ADDR_WIDTH-1) <= '1';
read_addrgray(0) <= '1';
read_addrgray(RD_ADDR_WIDTH-2 downto 1) <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow = '1') then
read_addrgray <= read_nextgray after glbtm;
end if;
end if;
end process pip_proc1;
pip_proc2: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
read_lastgray(RD_ADDR_WIDTH-1) <= '1';
read_lastgray(0) <= '1';
read_lastgray(1) <= '1';
read_lastgray(RD_ADDR_WIDTH-2 downto 2) <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow = '1') then
read_lastgray <= read_addrgray after glbtm;
end if;
end if;
end process pip_proc2;
-------------------------------------------------------------------------------
inc_wr_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_addr <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (wr_allow = '1') then
wr_addr <= wr_addr + '1' after glbtm;
end if;
end if;
end process inc_wr_proc;
wr_nextgray_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
write_nextgray(WR_ADDR_WIDTH-1) <= '1';
write_nextgray(WR_ADDR_WIDTH-2 downto 0) <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (wr_allow = '1') then
write_nextgray(WR_ADDR_WIDTH-1) <= wr_addr(WR_ADDR_WIDTH-1) after glbtm;
for i in WR_ADDR_WIDTH-2 downto 0 loop
write_nextgray(i) <= wr_addr(i+1) xor wr_addr(i) after glbtm;
end loop;
end if;
end if;
end process wr_nextgray_proc;
wr_addrgray_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_addrgray(WR_ADDR_WIDTH-1) <= '1';
wr_addrgray(0) <= '1';
wr_addrgray(WR_ADDR_WIDTH-2 downto 1) <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (wr_allow = '1') then
wr_addrgray <= write_nextgray after glbtm;
end if;
end if;
end process wr_addrgray_proc;
------------------------------------------------------------------------------
rd_minor_proc: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rd_addr_minor <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (WR_DWIDTH > RD_DWIDTH) then
if (rd_allow_minor = '1') then
rd_addr_minor <= rd_addr_minor + '1' after glbtm;
end if;
end if;
end if;
end process rd_minor_proc;
wr_minor_proc: process(wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_addr_minor <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (WR_DWIDTH > RD_DWIDTH) then
if (wr_allow_minor = '1') then
wr_addr_minor <= wr_addr_minor + '1' after glbtm;
end if;
end if;
if (WR_DWIDTH < RD_DWIDTH) then
if (wr_allow_minor = '1') then
if (wr_eof_n = '0') then
wr_addr_minor <= (others => '0') after glbtm;
else
wr_addr_minor <= wr_addr_minor + '1' after glbtm;
end if;
end if;
end if;
end if;
end process wr_minor_proc;
------------------------------------------------------------------------------
truegray_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
read_truegray <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
read_truegray(RD_ADDR_WIDTH-1) <= rd_addr(RD_ADDR_WIDTH-1);
for i in RD_ADDR_WIDTH-2 downto 0 loop
read_truegray(i) <= rd_addr(i+1) xor rd_addr(i) after glbtm;
end loop;
end if;
end process truegray_proc;
rag_wr_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rag_writesync <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
rag_writesync <= read_truegray after glbtm;
end if;
end process rag_wr_proc;
----------------------------------------------------------
-- --
-- Gray to binary Conversion. --
-- --
----------------------------------------------------------
ra_writesync <= gray_to_bin(rag_writesync);
----------------------------------------------------------
wr_addrr_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_addrr <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
wr_addrr <= wr_addr after glbtm;
end if;
end process wr_addrr_proc;
----------------------------------------------------------
status_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
fifostatus <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (full = '0') then
fifostatus <= (wr_addrr - ra_writesync) after glbtm;
end if;
end if;
end process status_proc;
--------------------------------------------------------------------------------------------------------
ecompgen: for i in 0 to WR_ADDR_WIDTH-1 generate
begin
ecomp(i) <= (not (wr_addrgray(i) xor read_addrgray(i)) and empty) or
(not (wr_addrgray(i) xor read_nextgray(i)) and not empty);
end generate ecompgen;
----------------------------------------------------------------------------------------------------------
emuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr,S=>ecomp(0),LO=>emuxcyo(0));
emuxcygen1: for i in 1 to WR_ADDR_WIDTH-2 generate
emuxcyx: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(i-1),S=>ecomp(i),LO=>emuxcyo(i));
end generate emuxcygen1;
emuxcylast: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(WR_ADDR_WIDTH-2),S=>ecomp(WR_ADDR_WIDTH-1),LO=>emptyg);
----------------------------------------------------------------------------------------------------------
fcompgen: for j in 0 to WR_ADDR_WIDTH-1 generate
begin
fcomp(j) <= (not (read_lastgray(j) xor wr_addrgray(j)) and full) or
(not (read_lastgray(j) xor write_nextgray(j)) and not full);
end generate fcompgen;
----------------------------------------------------------------------------------------------------
fmuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr, S=>fcomp(0),LO=>fmuxcyo(0));
fmuxcygen2: for i in 1 to WR_ADDR_WIDTH-2 generate
fmuxcyx: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(i-1),S=>fcomp(i),LO=>fmuxcyo(i));
end generate fmuxcygen2;
fmuxcylast: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(WR_ADDR_WIDTH-2),S=>fcomp(WR_ADDR_WIDTH-1),LO=>fullg);
end BRAM_fifo_hdl;
|
gpl-3.0
|
39364183262cf057b0303d6505feb5df
| 0.4688 | 3.895447 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/framework/sampling.vhd
| 1 | 27,850 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity sampling is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end sampling;
architecture Behavioral of sampling is
component uf_prediction is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the prediction user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- size of one particle
particle_size : in integer;
-- if every particle is sampled, this signal has to be set to '1'
finished : out std_logic);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (STATE_INIT, STATE_READ_PARTICLES_ADDRESS, STATE_READ_N,
STATE_READ_PARTICLE_SIZE, STATE_READ_MAX_NUMBER_OF_PARTICLES, STATE_READ_BLOCK_SIZE,
STATE_READ_PARAMETER_ADDRESS, STATE_READ_PARAMETER ,STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_PARTICLES_1, STATE_CALCULATE_REMAINING_PARTICLES_2,
STATE_CALCULATE_REMAINING_PARTICLES_3, STATE_CALCULATE_REMAINING_PARTICLES_4,
STATE_NEEDED_BURSTS_1, STATE_NEEDED_BURSTS_2, STATE_NEEDED_BURSTS_3,
STATE_NEEDED_BURSTS_4, STATE_COPY_PARTICLE_BURST_DECISION, STATE_COPY_PARTICLE_BURST,
--STATE_COPY_PARTICLE_BURST_2, STATE_COPY_PARTICLE_BURST_3, STATE_COPY_PARTICLE_BURST_4,
STATE_PREDICTION, STATE_PREDICTION_DONE,
STATE_WRITE_BURST_DECISION, STATE_WRITE_BURST,
STATE_CALCULATE_WRITES_1, STATE_CALCULATE_WRITES_2, STATE_CALCULATE_WRITES_3,
STATE_CALCULATE_WRITES_4, STATE_WRITE_DECISION, STATE_READ, STATE_WRITE,
STATE_SEND_MESSAGE, STATE_SEND_MEASUREMENT_1, STATE_SEND_MEASUREMENT_2);
-- current state
signal state : t_state := STATE_INIT;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal current_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter array address
signal parameter_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM write_address
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like N, particle size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 4;
-- number of particles still to resample
signal remaining_particles : integer := 4;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered (for writing back)
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 48;
-- temp variable
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal offset : integer := 0;
-- start particle index
signal start_particle_index : integer := 0;
-- maximum number of particles, which fit into the local RAM (minus 128 byte)
signal max_number_of_particles : integer := 168;
-- number of bytes, which are not written with valid particle data
signal diff : integer := 0;
-- number of writes
signal number_of_writes : integer := 0;
-- local ram address for interface
signal local_ram_address_if_read : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_address_if_write : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- message (received from message box). The number in the message says,
-- which particle block has to be sampled
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- block size, is the number of particles in a particle block
signal block_size : integer := 10;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
signal particle_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for prediction user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the resampling user process
signal particles_loaded : std_logic := '0';
-- number of particles in local RAM
signal number_of_particles : integer := 4;
-- size of one particle
signal particle_size_2 : integer := 0;
-- if every particle is resampled, this signal has to be set to '1'
signal finished : std_logic := '0';
-- corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrPrediction : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrSampling : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEPrediction : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWESampling : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataPrediction : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataSampling : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_prediction
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrPrediction, o_RAMData=>o_RAMDataPrediction,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWEPrediction, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, particles_loaded=>particles_loaded,
number_of_particles=>number_of_particles,
particle_size=>particle_size_2, finished=>finished);
-- burst ram interface
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrPrediction(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrPrediction(C_TASK_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrSampling(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrSampling(C_TASK_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEPrediction when enable = '1' else o_RAMWESampling;
-- switch 3: output ram data
o_RAMData <= o_RAMDataPrediction when enable = '1' else o_RAMDataSampling;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Sampling:
--
-- 1) The Parameter are copied to the first 128 bytes of the local RAM
-- Other information are set
--
--
-- 2) Waiting for Message m (Start of a Sampling run)
-- Message m: sample particles of m-th particle block
--
--
-- 3) The number of needed bursts is calculated to fill the local RAM
-- The number only differs from 63, if it is for the last particles,
-- which fit into the local ram.
--
--
-- 4) The particles are copied into the local RAM by burst reads
--
--
-- 5) The user prediction process is run
--
--
-- 6) After prediction the particles are written back to Main Memory.
-- Since there can be several sampling threads, there has to be
-- special treatment for the last 128 byte, which are written
-- in 4 byte blocks and not in a 128 byte burst.
--
--
-- 7) If the user process is finished and more particle need to be
-- sampled, then go to step 3 else to step 8
--
--
-- 8) Send message m (Stop of a Sampling run)
-- Particles of m-th particle block are sampled
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and max number of particles which fit in the local RAM
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable max_number_of_particles_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
--! init state, receive particle array address
-- TODO: C H A N G E !!! (1 of 3)
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
enable <= '0';
local_ram_address <= (others => '0');
local_ram_start_address <= (others => '0');
init <= '1';
particles_loaded <= '0';
if done then
-- TODO: C H A N G E !!! (2 of 3)
state <= STATE_READ_PARTICLES_ADDRESS;
--state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_READ_PARTICLES_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_N;
end if;
when STATE_READ_N =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_MAX_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_MAX_NUMBER_OF_PARTICLES =>
--! read max number of particles, which fit into 63 bursts (128 bytes per burst)
reconos_read (done, o_osif, i_osif, information_struct+12, max_number_of_particles_var);
if done then
particle_size_2 <= particle_size / 4;
max_number_of_particles <= TO_INTEGER(SIGNED(max_number_of_particles_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read bock size, this is the size of how many particles are in one block.
-- A message sends the block number
reconos_read (done, o_osif, i_osif, information_struct+16, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
--state <= STATE_WAIT_FOR_MESSAGE;
-- CHANGE BACK !!! (1 of 2)
state <= STATE_READ_PARAMETER_ADDRESS;
end if;
when STATE_READ_PARAMETER_ADDRESS =>
--! read parameter array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, parameter_array_address);
if done then
state <= STATE_READ_PARAMETER;
end if;
when STATE_READ_PARAMETER =>
--! copy all parameter in one burst
reconos_read_burst(done, o_osif, i_osif, local_ram_start_address, parameter_array_address);
if done then
state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for message, that starts Sampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
particles_loaded <= '0';
enable <= '0';
init <= '1';
time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= STATE_CALCULATE_REMAINING_PARTICLES_1;
end if;
when STATE_CALCULATE_REMAINING_PARTICLES_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
state <= STATE_CALCULATE_REMAINING_PARTICLES_2;
when STATE_CALCULATE_REMAINING_PARTICLES_2 =>
--! calculates particle array address and number of particles to sample
remaining_particles <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_PARTICLES_3;
when STATE_CALCULATE_REMAINING_PARTICLES_3 =>
--! calculates particle array address and number of particles to sample
remaining_particles <= N - remaining_particles;
particle_array_address <= particle_array_start_address;
state <= STATE_CALCULATE_REMAINING_PARTICLES_4;
when STATE_CALCULATE_REMAINING_PARTICLES_4 =>
--! calculates particle array address and number of particles to sample
if (remaining_particles > block_size) then
remaining_particles <= block_size;
end if;
current_particle_array_address <= particle_array_start_address;
state <= STATE_NEEDED_BURSTS_1;
when STATE_NEEDED_BURSTS_1 =>
--! decision how many bursts are needed
local_ram_address <= local_ram_start_address + 128;
local_ram_address_if_read <= local_ram_start_address_if + 32;
particles_loaded <= '0';
enable <= '0';
init <= '1';
--start_particle_index <= N - remaining_particles;
start_particle_index <= message2 * block_size;
if (remaining_particles <= 0) then
state <= STATE_SEND_MESSAGE;
time_stop <= TO_INTEGER(SIGNED(i_timeBase));
else
temp <= remaining_particles * particle_size;
state <= STATE_NEEDED_BURSTS_2;
end if;
when STATE_NEEDED_BURSTS_2 =>
--! decision how many bursts are needed
offset <= start_particle_index * particle_size;
state <= STATE_NEEDED_BURSTS_3;
when STATE_NEEDED_BURSTS_3 =>
--! decision how many bursts are needed
current_particle_array_address <= particle_array_start_address + offset;
particle_array_address <= particle_array_start_address + offset;
if (temp >= 8064) then --8064 = 63*128
--copy as much particles as possible
number_of_bursts <= 63;
number_of_bursts_remember <= 63;
number_of_particles <= max_number_of_particles;
state <= STATE_COPY_PARTICLE_BURST_DECISION;
else
-- copy only remaining particles
number_of_bursts <= temp / 128;
number_of_bursts_remember <= temp / 128;
number_of_particles <= remaining_particles;
state <= STATE_NEEDED_BURSTS_4;
end if;
when STATE_NEEDED_BURSTS_4 =>
--! decision how many bursts are needed
number_of_bursts <= number_of_bursts + 1;
number_of_bursts_remember <= number_of_bursts_remember + 1;
state <= STATE_COPY_PARTICLE_BURST_DECISION;
when STATE_COPY_PARTICLE_BURST_DECISION =>
--! check if another burst is needed
if (number_of_bursts > 63) then
number_of_bursts <= 63;
elsif (number_of_bursts > 0) then
number_of_bursts <= number_of_bursts - 1;
state <= STATE_COPY_PARTICLE_BURST;
elsif (remaining_particles <= 0) then
-- check it
state <= STATE_SEND_MESSAGE;
time_stop <= TO_INTEGER(SIGNED(i_timeBase));
else
remaining_particles <= remaining_particles - number_of_particles;
state <= STATE_PREDICTION;
enable <= '1';
particles_loaded <= '1';
init <= '0';
end if;
when STATE_COPY_PARTICLE_BURST =>
--! read another burst
-- NO MORE BURSTS
--temp3 <= 32;
--state <= STATE_COPY_PARTICLE_BURST_2;
reconos_read_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
if done then
state <= STATE_COPY_PARTICLE_BURST_DECISION;
--if (local_ram_address < 8064) then
local_ram_address <= local_ram_address + 128;
--end if;
current_particle_array_address <= current_particle_array_address + 128;
end if;
-- when STATE_COPY_PARTICLE_BURST_2 =>
-- --! read another burst
-- -- NO MORE BURSTS
-- enable <= '0';
-- o_RAMWESampling<= '0';
-- if (temp3 > 0) then
--
-- state <= STATE_COPY_PARTICLE_BURST_3;
-- temp3 <= temp3 - 1;
-- else
--
-- state <= STATE_COPY_PARTICLE_BURST_DECISION;
-- end if;
--
--
-- when STATE_COPY_PARTICLE_BURST_3 =>
-- --! read another burst
-- -- NO MORE BURSTS
-- --! load data to local ram
-- reconos_read_s (done, o_osif, i_osif, particle_array_address, particle_data);
-- if done then
-- state <= STATE_COPY_PARTICLE_BURST_4;
-- particle_array_address <= particle_array_address + 4;
-- end if;
--
--
-- when STATE_COPY_PARTICLE_BURST_4 =>
-- --! write particle data to local ram
-- o_RAMWESampling<= '1';
-- o_RAMAddrSampling <= local_ram_address_if_read;
-- o_RAMDataSampling <= particle_data;
-- local_ram_address_if_read <= local_ram_address_if_read + 1;
-- state <= STATE_COPY_PARTICLE_BURST_2;
when STATE_PREDICTION =>
--! start prediction user process and wait until prediction is finished
init <= '0';
enable <= '1';
particles_loaded <= '0';
if (finished = '1') then
state <= STATE_PREDICTION_DONE;
end if;
when STATE_PREDICTION_DONE =>
--! start prediction user process and wait until it is finished
init <= '1';
enable <= '0';
particles_loaded <= '0';
current_particle_array_address <= particle_array_address;
local_ram_address <= local_ram_start_address + 128;
local_ram_address_if_write <= local_ram_start_address_if + 32;
number_of_bursts <= number_of_bursts_remember;
state <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_BURST_DECISION =>
--! if write burst is demanded by user process, it will be done
if (number_of_bursts > 63) then
number_of_bursts <= 63;
--else
-- NO MORE BURSTS
elsif (number_of_bursts > 1) then
state <= STATE_WRITE_BURST;
elsif (number_of_bursts <= 1) then
number_of_bursts <= 0;
state <= STATE_CALCULATE_WRITES_1;
diff <= (number_of_bursts_remember * 128);
end if;
when STATE_WRITE_BURST =>
--! write bursts from local ram into index array
reconos_write_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
if done then
local_ram_address <= local_ram_address + 128;
local_ram_address_if_write <= local_ram_address_if_write + 32;
current_particle_array_address <= current_particle_array_address + 128;
number_of_bursts <= number_of_bursts - 1;
state <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_CALCULATE_WRITES_1 =>
--! calculates number of writes (1/4)
temp2 <= number_of_particles * particle_size;
--state <= STATE_CALCULATE_WRITES_4;
-- NO MORE BURSTS
state <= STATE_CALCULATE_WRITES_2;
when STATE_CALCULATE_WRITES_2 =>
--! calculates number of writes (2/4)
diff <= diff - temp2;
state <= STATE_CALCULATE_WRITES_3;
when STATE_CALCULATE_WRITES_3 =>
--! calculates number of writes (3/4)
number_of_writes <= 128 - diff;
state <= STATE_CALCULATE_WRITES_4;
when STATE_CALCULATE_WRITES_4 =>
--! calculates number of writes (4/4)
-- NO MORE BURSTS
number_of_writes <= number_of_writes / 4;
--number_of_writes <= temp2 / 4;
state <= STATE_WRITE_DECISION;
when STATE_WRITE_DECISION =>
--! decide if a reconos write is needed
if (number_of_writes <= 0) then
state <= STATE_NEEDED_BURSTS_1;
else
-- read local ram data
state <= STATE_READ;
o_RAMAddrSampling <= local_ram_address_if_write;
end if;
when STATE_READ =>
--! read 4 byte from local RAM
number_of_writes <= number_of_writes - 1;
--local_ram_address_if <= local_ram_address_if + 1;
o_RAMAddrSampling <= local_ram_address_if_write;
state <= STATE_WRITE;
when STATE_WRITE =>
--! write 4 byte to particle array in main memory
reconos_write(done, o_osif, i_osif, current_particle_array_address, i_RAMData);
if done then
local_ram_address_if_write <= local_ram_address_if_write + 1;
current_particle_array_address <= current_particle_array_address + 4;
if (number_of_writes <= 0) then
state <= STATE_NEEDED_BURSTS_1;
else
o_RAMAddrSampling <= local_ram_address_if_write;
state <= STATE_READ;
end if;
end if;
when STATE_SEND_MESSAGE =>
--! send message i (sampling is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
particles_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
-- when STATE_SEND_MEASUREMENT_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
--
-- state <= STATE_WAIT_FOR_MESSAGE;
-- end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
7de7b977b95a3a1d3597607ea552880a
| 0.554039 | 4.006041 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/dec2to4.vhd
| 4 | 625 |
library ieee;
use ieee.std_logic_1164.all;
entity dec2to4 is
port (sel: in std_logic_vector (1 downto 0);
en: in std_logic;
y: out std_logic_vector (0 to 3) );
end dec2to4;
architecture dec2to4_rtl of dec2to4 is
begin
process (sel, en)
begin
if (en = '1') then
case sel is
when "00" => y <= "1000";
when "01" => y <= "0100";
when "10" => y <= "0010";
when "11" => y <= "0001";
when others => y <= "0000";
end case;
else
y <= "0000";
end if;
end process;
end dec2to4_rtl;
|
gpl-2.0
|
05236cbe21586cd6f16dde888900bbc1
| 0.4784 | 3.272251 | false | false | false | false |
BenBoZ/realtimestagram
|
src/test_bench_driver.vhd
| 2 | 7,720 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
--! use standard library
library ieee;
--! use std_logic_vector
use ieee.std_logic_1164.all;
--! needed for colorscheme calculations
use ieee.numeric_std.all;
--! used for writing and reading images
use std.textio.all;
--! used only for calculation of constants
use ieee.math_real.all;
use work.image_io_pkg.all;
use work.config_const_pkg.all;
entity test_bench_driver is
generic (
wordsize: integer; --! size of input pixel value in bits
input_file: string;
output_file: string;
clk_period_ns: time := 2 ns;
rst_after: time := 10 ns;
rst_duration: time := 10 ns;
--! Number of clk pulses of delay of a Device Under Test between input and output
dut_delay: integer := 1;
h_count_size: integer := integer(ceil(log2(real(const_imagewidth))));
v_count_size: integer := integer(ceil(log2(real(const_imageheight))))
);
port (
clk: out std_logic; --! completely clocked process
rst: out std_logic; --! asynchronous reset
enable: out std_logic;
h_count: out std_logic_vector(h_count_size-1 downto 0) := (others => '0');
v_count: out std_logic_vector(v_count_size-1 downto 0) := (others => '0');
pixel_from_file: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_to_file: in std_logic_vector((wordsize-1) downto 0) --! the output pixel
);
end entity;
architecture behavioural of test_bench_driver is
--===================signal declaration===================--
signal tb_clk: std_logic := '0';
signal tb_rst: std_logic := '0';
signal tb_enable: std_logic := '0';
signal tb_done: std_logic := '0';
signal dut_data_valid: std_logic := '0';
signal end_of_file: std_logic := '0';
signal pixel_tmp: std_logic_vector(wordsize-1 downto 0) := (others => '0');
--===================file declaration===================--
--! File containing pixels for input of the testbench
file file_input_pixel: text open read_mode is input_file;
--! File used as output for the tesbench
file file_output_pixel: text open write_mode is output_file;
begin
--===================rst===================--
tb_rst <= '0', '1' after rst_after, '0' after rst_after+rst_duration when tb_done = '0';
rst <= tb_rst;
--===================clock===================--
tb_clk <= not tb_clk after clk_period_ns when tb_done = '0';
clk <= tb_clk;
--=================== enable ===============--
enable <= tb_enable;
--=================== release ===============--
--! \vhdlflow [Release process]
release_process: process(tb_clk, tb_rst, end_of_file)
variable pre_delay_count : integer := dut_delay;
variable post_delay_count : integer := dut_delay - 1;
begin
if rising_edge(tb_clk) then
if tb_rst = '1' then
tb_enable <= '1'; -- enable tb
end if;
if tb_enable = '1' and tb_rst = '0' then
if pre_delay_count > 0 then
pre_delay_count := pre_delay_count - 1;
else
dut_data_valid <= '1';
end if;
end if;
if end_of_file = '1' or post_delay_count < dut_delay-1 then
if post_delay_count > 0 then
post_delay_count := post_delay_count - 1;
else
tb_enable <= '0';
tb_done <= '1';
end if;
end if;
end if;
end process;
--===================process for reading input_pixels ===============--
reading_input_pixels: process(tb_clk)
constant pgm_width : integer := const_imagewidth;
constant pgm_height : integer := const_imageheight;
constant max_pixel_value : integer := 2**wordsize-1;
variable readheader: std_logic := '1';
begin
pixel_from_file <= pixel_tmp;
if rising_edge(tb_clk) then
if readheader = '1' then
read_pbmplus_header( pgm_width, pgm_height, max_pixel_value, pgm, file_input_pixel );
readheader := '0';
end if;
if tb_rst = '0' then
if tb_enable = '1' and end_of_file = '0' then
read_pixel(file_input_pixel, pixel_tmp, end_of_file);
end if;
end if;
end if;
end process;
--===================process for writing output ===================================--
writing_output_file: process( tb_clk )
constant pgm_width : integer := const_imagewidth;
constant pgm_height : integer := const_imageheight;
constant max_pixel_value : integer := 2**wordsize-1;
variable writeheader: std_logic := '1';
variable val: integer := 0;
begin
if rising_edge(tb_clk) then
if writeheader = '1' then
write_pbmplus_header( pgm_width, pgm_height, max_pixel_value, pgm, file_output_pixel );
writeheader := '0';
end if;
if tb_enable = '1' and tb_rst = '0' and tb_done = '0' then
-- write output image
val := to_integer(unsigned(pixel_to_file));
--report integer'image(val);
write_pixel( val, file_output_pixel);
end if;
end if;
end process;
--=================== process for pixel counts ===================================--
h_and_v_counters: process( tb_clk )
constant pgm_width : integer := const_imagewidth;
constant pgm_height : integer := const_imageheight;
variable h_count_var : integer range 0 to const_imagewidth := 0;
variable v_count_var : integer range 0 to const_imageheight := 0;
begin
if rising_edge(tb_clk) then
if tb_enable = '1' and tb_rst = '0' then
if h_count_var < const_imagewidth-1 then
h_count_var := h_count_var + 1;
else
h_count_var := 0;
if v_count_var < const_imageheight-1 then
v_count_var := v_count_var + 1;
else
v_count_var := 0;
end if;
end if;
h_count <= std_logic_vector(to_unsigned(h_count_var, h_count_size));
v_count <= std_logic_vector(to_unsigned(v_count_var, v_count_size));
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
ec9be7751fe7dbd569b0a4e1ad365f0f
| 0.509067 | 4.179751 | false | false | false | false |
luebbers/reconos
|
support/pcores/v4_mgt_protector_v1_00_a/hdl/vhdl/v4_mgt_protector.vhd
| 1 | 2,580 |
library IEEE;
use IEEE.std_logic_1164.all;
entity v4_mgt_protector is
generic (
G_NUM_MGTS : natural := 10 -- for v4fx100
);
port
(
clk : in std_logic;
rx1n : in std_logic_vector(2*G_NUM_MGTS-1 downto 0);
rx1p : in std_logic_vector(2*G_NUM_MGTS-1 downto 0);
tx1n : out std_logic_vector(2*G_NUM_MGTS-1 downto 0);
tx1p : out std_logic_vector(2*G_NUM_MGTS-1 downto 0)
);
end v4_mgt_protector;
architecture structure of v4_mgt_protector is
-------------------------------------------------------------------
--
-- NULL_PAIR core component declaration
--
-------------------------------------------------------------------
COMPONENT NULL_PAIR
PORT (
GREFCLK_IN : IN std_logic;
RX1N_IN : IN std_logic_vector(1 DOWNTO 0);
RX1P_IN : IN std_logic_vector(1 DOWNTO 0);
TX1N_OUT : OUT std_logic_vector(1 DOWNTO 0);
TX1P_OUT : OUT std_logic_vector(1 DOWNTO 0));
END COMPONENT;
attribute box_type: string;
attribute box_type of NULL_PAIR: component is "user_black_box";
COMPONENT BUFG
PORT (
I : IN std_logic;
O : OUT std_logic);
END COMPONENT;
-------------------------------------------------------------------
--
-- NULL_PAIR core signal declarations
--
-------------------------------------------------------------------
signal global_sig : std_logic;
begin
-------------------------------------------------------------------
--
-- GREFCLK_IN port needs to be driven with any global signal
-- (any BUFG output, even a BUFG with ground for input will work).
--
-------------------------------------------------------------------
global_bufg_inst : BUFG
port map
(
I => clk,
O => global_sig
);
-------------------------------------------------------------------
--
-- NULL_PAIR core instances
--
-------------------------------------------------------------------
mgt: for i in 0 to G_NUM_MGTS-1 generate
null_pair_inst: NULL_PAIR
port map
(
GREFCLK_IN => global_sig,
RX1N_IN => rx1n(2*i+1 downto 2*i),
RX1P_IN => rx1p(2*i+1 downto 2*i),
TX1N_OUT => tx1n(2*i+1 downto 2*i),
TX1P_OUT => tx1p(2*i+1 downto 2*i)
);
end generate;
end structure;
|
gpl-3.0
|
1c9d82af5408e712f8feb4ccfda683f0
| 0.402713 | 4.128 | false | false | false | false |
denis4net/hw_design
|
2/altera-project/src/file_tb.vhd
| 1 | 2,840 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
library std;
use std.env.all;
entity testbench_file is
generic(
constant period: time:= 20 ps
);
end entity;
architecture arch of testbench_file is
component COUNTER8
port (
DATA: in std_logic_vector(7 downto 0);
NCCLR, NCCKEN, CCK, NCLOAD, RCK: in std_logic;
NRCO: out std_logic;
QDATA: out std_logic_vector(7 downto 0)
);
end component;
signal TEST_DATA: std_logic_vector(7 downto 0) := b"00000000";
signal NRCO: std_logic;
signal NCCLR: std_logic := '0';
signal RCK: std_logic := '0';
signal NCLOAD: std_logic := '1';
signal NCCKEN: std_Logic := '0';
signal CCK: std_logic := '0';
signal NRCO_FILE: std_logic := '0';
signal QDATA: std_logic_vector(7 downto 0) := b"00000000";
begin
COUNTER80: COUNTER8 port map(DATA=>TEST_DATA, NRCO=>NRCO, NCCKEN=>NCCKEN, CCK=>CCK, NCLOAD=>NCLOAD, RCK=>RCK, NCCLR=>NCCLR, QDATA=>QDATA);
CCK <= not CCK after period / 2;
--genereate data test file
create_data_file : process
file file_pointer : text;
variable file_status : file_open_status;
variable current_line : line;
-- prefix 'f' mean data readed from file
variable fDATA: std_logic_vector(7 downto 0);
variable fNCCLR, fNCCKEN, fCCK, fNCLOAD, fRCK: std_logic;
variable fNRCO: std_logic;
variable timestamp: time;
variable fQDATA: std_logic_vector(7 downto 0);
begin
-- create file
file_open(file_status, file_pointer, "test.data", READ_MODE);
-- check file open ok
assert(file_status = OPEN_OK)
report "ERROR: open file WRITE_MODE "
severity failure;
wait for period;
readloop:
while not endfile(file_pointer)
loop
-- DATA: in std_logic_vector(7 downto 0);
-- NCCLR, NCCKEN, CCK, NCLOAD, RCK: in std_logic;
-- NRCO: out std_logic
readline(file_pointer, current_line);
read(current_line, timestamp);
readline(file_pointer, current_line);
read(current_line, fDATA);
readline(file_pointer, current_line);
read(current_line, fNCCLR);
readline(file_pointer, current_line);
read(current_line, fNCCKEN);
readline(file_pointer, current_line);
read(current_line, fNCLOAD);
readline(file_pointer, current_line);
read(current_line, fRCK);
readline(file_pointer, current_line);
read(current_line, fNRCO);
readline(file_pointer, current_line);
read(current_line, fQDATA);
TEST_DATA <= fDATA;
NCCLR <= fNCCLR;
NCCKEN <= fNCCKEN;
NCLOAD <= fNCLOAD;
NRCO_FILE <= fNRCO;
RCK <= fRCK;
wait for period / 2;
assert(NRCO = NRCO_FILE) report ("Test failed on test.data");
assert(QDATA = fQDATA) report ("Test (2) failed");
end loop;
file_close(file_pointer);
stop(2);
end process;
end architecture;
|
mit
|
6760fd761c47474c68eb38447b2449e0
| 0.677113 | 2.961418 | false | true | false | false |
bzero/freezing-spice
|
src/common.vhd
| 2 | 5,916 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package common is
-- definition for a machine word
subtype word is std_logic_vector(31 downto 0);
subtype imm_type_t is std_logic_vector(2 downto 0);
subtype alu_func_t is std_logic_vector(3 downto 0);
constant ALU_NONE : alu_func_t := "0000";
constant ALU_ADD : alu_func_t := "0001";
constant ALU_ADDU : alu_func_t := "0010";
constant ALU_SUB : alu_func_t := "0011";
constant ALU_SUBU : alu_func_t := "0100";
constant ALU_SLT : alu_func_t := "0101";
constant ALU_SLTU : alu_func_t := "0110";
constant ALU_AND : alu_func_t := "0111";
constant ALU_OR : alu_func_t := "1000";
constant ALU_XOR : alu_func_t := "1001";
constant ALU_SLL : alu_func_t := "1010";
constant ALU_SRA : alu_func_t := "1011";
constant ALU_SRL : alu_func_t := "1100";
subtype insn_type_t is std_logic_vector(3 downto 0);
constant OP_ILLEGAL : insn_type_t := "0000";
constant OP_LUI : insn_type_t := "0001";
constant OP_AUIPC : insn_type_t := "0010";
constant OP_JAL : insn_type_t := "0011";
constant OP_JALR : insn_type_t := "0100";
constant OP_BRANCH : insn_type_t := "0101";
constant OP_LOAD : insn_type_t := "0110";
constant OP_STORE : insn_type_t := "0111";
constant OP_ALU : insn_type_t := "1000";
subtype branch_type_t is std_logic_vector(2 downto 0);
constant BRANCH_NONE : branch_type_t := "000";
constant BEQ : branch_type_t := "001";
constant BNE : branch_type_t := "010";
constant BLT : branch_type_t := "011";
constant BGE : branch_type_t := "100";
constant BLTU : branch_type_t := "101";
constant BGEU : branch_type_t := "110";
subtype load_type_t is std_logic_vector(2 downto 0);
constant LOAD_NONE : load_type_t := "000";
constant LB : load_type_t := "001";
constant LH : load_type_t := "010";
constant LW : load_type_t := "011";
constant LBU : load_type_t := "100";
constant LHU : load_type_t := "101";
subtype store_type_t is std_logic_vector(1 downto 0);
constant STORE_NONE : store_type_t := "00";
constant SB : store_type_t := "01";
constant SH : store_type_t := "10";
constant SW : store_type_t := "11";
-- print a string with a newline
procedure println (str : in string);
procedure print (slv : in std_logic_vector);
procedure write(l : inout line; slv : in std_logic_vector);
function hstr(slv : std_logic_vector) return string;
-- instruction formats
type r_insn_t is (R_ADD, R_SLT, R_SLTU, R_AND, R_OR, R_XOR, R_SLL, R_SRL, R_SUB, R_SRA);
type i_insn_t is (I_JALR, I_LB, I_LH, I_LW, I_LBU, I_LHU, I_ADDI, I_SLTI, I_SLTIU, I_XORI, I_ORI, I_ANDI, I_SLLI, I_SRLI, I_SRAI);
type s_insn_t is (S_SB, S_SH, S_SW);
type sb_insn_t is (SB_BEQ, SB_BNE, SB_BLT, SB_BGE, SB_BLTU, SB_BGEU);
type u_insn_t is (U_LUI, U_AUIPC);
type uj_insn_t is (UJ_JAL);
-- ADDI r0, r0, r0
constant NOP : word := "00000000000000000000000000010011";
end package common;
package body common is
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- print a string with a newline
procedure println (str : in string) is
variable l : line;
begin -- procedure println
write(l, str);
writeline(output, l);
end procedure println;
procedure write(l : inout line; slv : in std_logic_vector) is
begin
for i in slv'range loop
if slv(i) = '0' then
write(l, string'("0"));
elsif slv(i) = '1' then
write(l, string'("1"));
elsif slv(i) = 'X' then
write(l, string'("X"));
elsif slv(i) = 'U' then
write(l, string'("U"));
end if;
end loop; -- i
end procedure write;
procedure print (slv : in std_logic_vector) is
variable l : line;
begin -- procedure print
write(l, slv);
writeline(output, l);
end procedure print;
end package body common;
|
bsd-3-clause
|
8c1a92d13bfab80ae5322dec99cf3fe1
| 0.524172 | 3.331081 | false | false | false | false |
luebbers/reconos
|
tests/simulation/plb/mutex/test_mutex.vhd
| 1 | 3,092 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_mutex is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_mutex;
architecture Behavioral of test_mutex is
constant C_MY_MUTEX : std_logic_vector(0 to 31) := X"00000000";
type t_state is (STATE_INIT, STATE_HALLO, STATE_LOCK, STATE_READ, STATE_WRITE, STATE_UNLOCK);
signal state : t_state := STATE_INIT;
signal in_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal out_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
out_value <= in_value + 1;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_get_init_data_s (done, o_osif, i_osif, init_data);
if done then
state <= STATE_HALLO;
end if;
when STATE_HALLO =>
reconos_write(done, o_osif, i_osif, X"10000002", X"AFFEDEAD");
if done then
state <= STATE_LOCK;
end if;
when STATE_LOCK =>
reconos_mutex_lock (done, success, o_osif, i_osif, C_MY_MUTEX);
if done and success then
state <= STATE_READ;
end if;
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, init_data, in_value);
if done then
state <= STATE_WRITE;
end if;
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, init_data, out_value);
if done then
state <= STATE_UNLOCK;
end if;
when STATE_UNLOCK =>
reconos_mutex_unlock (o_osif, i_osif, C_MY_MUTEX);
state <= STATE_LOCK;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
d8cb2f63595d74a18f14bb3d302211d9
| 0.569211 | 3.412804 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/SPI_If.vhd
| 1 | 9,496 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 17:55:33 02/17/2014
-- Design Name:
-- Module Name: SPI_If - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents an SPI controller. The controller transfers 8 bits of data, MSB first.
-- Data is read on the positive edge of SCLK and also stable on the positive edge of SCLK.
-- When there is no data transfer, SCLK = 0, therefore CPOL = 0, CPHA = 0.
-- Data transfer starts by activating the "Start" signal, and, when data transfer is done, the
-- "Done" signal is activated for one SYSCLK period.
--
-- The module is also capable to transfer multiple bytes, if the "HOLD_SS" signal is active.
-- In this case SS is not raised between byte transfers and a new transfer can begin
-- if the "Start" signal is activated. This feature is used in conjunction with the ADXL 362 accelerometer
-- or any device which needs multiple-byte transfers for sending commands and/or reading data
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SPI_If is
generic
(
SYSCLK_FREQUENCY_HZ : integer:= 100000000;
SCLK_FREQUENCY_HZ : integer:= 1000000
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (7 downto 0); -- Data to be transmitted
Dout : out STD_LOGIC_VECTOR (7 downto 0); -- Data received;
Start : in STD_LOGIC; -- used to start the transmission
Done : out STD_LOGIC; -- Signaling that transmission ended
HOLD_SS : in STD_LOGIC; -- Signal that forces SS low in the case of multiple byte
-- transmit/receive mode
--SPI Interface Signals
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC
);
end SPI_If;
architecture Behavioral of SPI_If is
-- Determine the division rate in order to create the 2X SCLK tick
constant DIV_RATE : integer := ((SYSCLK_FREQUENCY_HZ / ( 2 * SCLK_FREQUENCY_HZ)) - 1);
-- To generate the 2X SCLK tick, then SCLK
signal SCLK_2X_DIV : integer range 0 to DIV_RATE := 0;
signal SCLK_2X_TICK : STD_LOGIC := '0';
-- Internal SCLK signal
signal SCLK_INT : STD_LOGIC := '0';
-- Enable Output Signals
signal EN_SCLK : STD_LOGIC := '0';
signal EN_SS : STD_LOGIC := '0';
-- Control Signals
signal EN_SHIFT : STD_LOGIC := '0'; -- Enable shifting the MOSI_REG and MISO_REG registers
signal EN_LOAD_DOUT : STD_LOGIC :='0'; -- Enable loading the Dout register
-- from the shift register for MISO
signal EN_LOAD_DIN : STD_LOGIC := '0'; -- Load the MOSI shift register
signal SHIFT_TICK_IN : STD_LOGIC; -- the moment at which the shifting is made,
signal SHIFT_TICK_OUT : STD_LOGIC; -- i.e. at the SCLK frequency
-- State machine internal condition signals
signal Start_Shifting : STD_LOGIC := '0';
signal Shifting_Done : STD_LOGIC := '0';
--Counter for number of bits sent/received
signal CntBits: integer range 0 to 7 := 0;
signal Reset_Counters: STD_LOGIC; -- to reset all the counters, when in the Idle State
-- Shift In and Shift Out Registers
signal MOSI_REG : STD_LOGIC_VECTOR (7 downto 0) := X"00";
signal MISO_REG : STD_LOGIC_VECTOR (7 downto 0) := X"00";
-- Pipe Done signal to ensure that data is stable at the output
signal DONE_1 : STD_LOGIC := '0';
-- Define Control Signals and States. From MSB: 7:EN_LOAD_DIN, 6:EN_SHIFT, 5:Reset_Counters,
-- 4:EN_SCLK, 3:EN_SS, 2:EN_LOAD_DOUT, 1:STC(1), 0:STC(0)
constant stIdle : STD_LOGIC_VECTOR (7 downto 0) := "10100000";
constant stPrepare : STD_LOGIC_VECTOR (7 downto 0) := "00001001";
constant stShift : STD_LOGIC_VECTOR (7 downto 0) := "01011011";
constant stDone : STD_LOGIC_VECTOR (7 downto 0) := "00001110";
--State Machine Signal Definitions
signal StC, StN : STD_LOGIC_VECTOR (7 downto 0) := stIdle;
--Force User Encoding for the State Machine
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of StC: signal is "USER";
begin
-- Assign the control signals first
EN_LOAD_DIN <= StC(7);
EN_SHIFT <= StC(6);
Reset_Counters <= StC(5);
EN_SCLK <= StC(4);
EN_SS <= StC(3);
EN_LOAD_DOUT <= StC(2);
-- Assign the outputs
SS <= '0' when RESET = '0' and (HOLD_SS = '1' or EN_SS = '1') else '1';
MOSI <= MOSI_REG(7);
SCLK <= SCLK_INT when EN_SCLK = '1' else '0';
--Assign the outputs: Register Dout
Load_Output: process (SYSCLK, EN_LOAD_DOUT, MISO_REG)
begin
if RISING_EDGE (SYSCLK) then
if EN_LOAD_DOUT = '1' then
Dout <= MISO_REG;
end if;
end if;
end process Load_Output;
-- Set the Done signal, delayed with one clock period
-- after data is assigned
Set_Done: process (SYSCLK, EN_LOAD_DOUT, DONE_1)
begin
if RISING_EDGE (SYSCLK) then
DONE_1 <= EN_LOAD_DOUT;
Done <= DONE_1;
end if;
end process Set_Done;
-- Divider to generate the 2X SCLK tick
Div_2X_SCLK: process (SYSCLK, Reset_Counters, SCLK_2X_DIV)
begin
if RISING_EDGE (SYSCLK) then
if Reset_Counters = '1'
or SCLK_2X_DIV = DIV_RATE then
SCLK_2X_DIV <= 0;
else
SCLK_2X_DIV <= SCLK_2X_DIV + 1;
end if;
end if;
end process Div_2X_SCLK;
-- SCLK_2X_TICK will be active at both the rising and falling edges
-- of SCLK_INT
SCLK_2X_TICK <= '1' when SCLK_2X_DIV = DIV_RATE else '0';
--Generate SCLK_INT;
Gen_SCLK_INT: process (SYSCLK, Reset_Counters, SCLK_2X_TICK, SCLK_INT)
begin
if RISING_EDGE (SYSCLK) then
if Reset_Counters = '1' then
SCLK_INT <= '0';
elsif SCLK_2X_TICK = '1' then
SCLK_INT <= not SCLK_INT;
end if;
end if;
end process Gen_SCLK_INT;
-- SHIFT_TICK_IN will be active at the rising edge of SCLK
-- At that moment MOSI will be read
SHIFT_TICK_IN <= '1' when EN_SHIFT = '1' and SCLK_INT = '0' and SCLK_2X_TICK = '1' else '0';
-- SHIFT_TICK_OUT will be active at the falling edge of SCLK
-- At that moment the next bit will be shifted out
SHIFT_TICK_OUT <= '1' when EN_SHIFT = '1' and SCLK_INT = '1' and SCLK_2X_TICK = '1' else '0';
-- Create the shift in register, MSB First, so shift left
SHIFT_IN: process (SYSCLK, SHIFT_TICK_IN, MISO_REG)
begin
if RISING_EDGE (SYSCLK) then
if SHIFT_TICK_IN = '1' then
MISO_REG (7 downto 0) <= MISO_REG (6 downto 0) & MISO;
end if;
end if;
end process SHIFT_IN;
-- Create the shift out register, MSB out first, so shift left
-- MOSI_REG is constantly loaded with Din when in idle state;
SHIFT_OUT: process (SYSCLK, EN_LOAD_DIN, Din, SHIFT_TICK_OUT, MOSI_REG)
begin
if RISING_EDGE (SYSCLK) then
if EN_LOAD_DIN = '1' then
MOSI_REG <= Din;
elsif SHIFT_TICK_OUT = '1' then
MOSI_REG (7 downto 0) <= MOSI_REG (6 downto 0) & '0';
end if;
end if;
end process SHIFT_OUT;
-- CntBits will be incremented at the falling edge of SCLK
-- i.e. when SHIFT_TICK_OUT is active
Count_Bits: process (SYSCLK, Reset_Counters, SHIFT_TICK_OUT, CntBits)
begin
if RISING_EDGE (SYSCLK) then
if Reset_Counters = '1' then
CntBits <= 0;
elsif SHIFT_TICK_OUT = '1' then
if CntBits = 7 then
CntBits <= 0;
else
CntBits <= CntBits + 1;
end if;
end if;
end if;
end process Count_Bits;
-- Assign the State machine internal condition signals
-- Start Shifting in the stPrepare state, after
-- either a falling edge of SCLK_INT comes in a single byte transfer mode
-- or immediately after a Start command received, in multiple byte transfer mode
Start_Shifting <= '1' when StC = stPrepare and (HOLD_SS = '1' or (SCLK_INT = '1' and SCLK_2X_TICK = '1'))
else '0';
-- Shifting ends when 8 bits has been transferred,
-- at the falling edge of SCLK_INT
Shifting_Done <= '1' when StC = stShift and CntBits = 7 and SCLK_INT = '1' and SCLK_2X_TICK = '1' else '0';
-- State machine register process
Reg_Statem: process (SYSCLK, RESET, StN)
begin
if RISING_EDGE (SYSCLK) then
if RESET = '1' then
StC <= stIdle;
else
StC <= StN;
end if;
end if;
end process Reg_Statem;
-- State machine transition process
Cmb_Statem: process (StC, Start, Start_Shifting, Shifting_Done)
begin
StN <= StC; -- default: stay in the current state if no other
-- condition for transition occurs
case StC is
when stIdle => if Start = '1' then StN <= stPrepare; end if;
when stPrepare => if Start_Shifting = '1' then StN <= stShift; end if;
when stShift => if Shifting_Done = '1' then StN <= stDone; end if;
when stDone => StN <= stIdle;
when others => StN <= stIdle;
end case;
end process Cmb_Statem;
end Behavioral;
|
gpl-3.0
|
10e5ace9b69a0ea019cd605172b2a116
| 0.625737 | 3.541962 | false | false | false | false |
luebbers/reconos
|
support/pcores/message_manager_v1_00_a/hdl/vhdl/mm_tb.vhd
| 1 | 8,342 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:23:53 10/16/2007
-- Design Name: message_manager
-- Module Name: /users/jagron/message_manager/src//mm_tb.vhd
-- Project Name: my_ise_proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: message_manager
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY mm_tb_vhd IS
END mm_tb_vhd;
ARCHITECTURE behavior OF mm_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT message_manager
PORT(
clk : IN std_logic;
reset : IN std_logic;
i_request : IN std_logic;
i_user_opcode : IN std_logic_vector(0 to 7);
i_user_data : IN std_logic_vector(0 to 31);
i_user_channel : IN std_logic_vector(0 to 7);
i_user_sender : IN std_logic_vector(0 to 7);
i_packet_data : IN std_logic_vector(0 to 31);
i_packet_channel : IN std_logic_vector(0 to 7);
i_packet_sender : IN std_logic_vector(0 to 7);
i_packet_valid : IN std_logic;
i_token : IN std_logic;
o_user_data : OUT std_logic_vector(0 to 31);
o_user_channel : OUT std_logic_vector(0 to 7);
o_user_sender : OUT std_logic_vector(0 to 7);
o_busy : OUT std_logic;
o_send_ready : out std_logic;
o_recv_ready : out std_logic;
o_token : OUT std_logic;
o_packet_data : OUT std_logic_vector(0 to 31);
o_packet_channel : OUT std_logic_vector(0 to 7);
o_packet_sender : OUT std_logic_vector(0 to 7);
o_packet_valid : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL i_request : std_logic := '0';
SIGNAL i_packet_valid : std_logic := '0';
SIGNAL i_token : std_logic := '0';
SIGNAL i_user_opcode : std_logic_vector(0 to 7) := (others=>'0');
SIGNAL i_user_data : std_logic_vector(0 to 31) := (others=>'0');
SIGNAL i_user_channel : std_logic_vector(0 to 7) := (others=>'0');
SIGNAL i_user_sender : std_logic_vector(0 to 7) := (others=>'0');
SIGNAL i_packet_data : std_logic_vector(0 to 31) := (others=>'0');
SIGNAL i_packet_channel : std_logic_vector(0 to 7) := (others=>'0');
SIGNAL i_packet_sender : std_logic_vector(0 to 7) := (others=>'0');
--Outputs
SIGNAL o_user_data : std_logic_vector(0 to 31);
SIGNAL o_user_channel : std_logic_vector(0 to 7);
SIGNAL o_user_sender : std_logic_vector(0 to 7);
SIGNAL o_busy : std_logic;
signal o_send_ready : std_logic;
signal o_recv_ready : std_logic;
SIGNAL o_token : std_logic;
SIGNAL o_packet_data : std_logic_vector(0 to 31);
SIGNAL o_packet_channel : std_logic_vector(0 to 7);
SIGNAL o_packet_sender : std_logic_vector(0 to 7);
SIGNAL o_packet_valid : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: message_manager PORT MAP(
clk => clk,
reset => reset,
i_request => i_request,
i_user_opcode => i_user_opcode,
i_user_data => i_user_data,
i_user_channel => i_user_channel,
i_user_sender => i_user_sender,
o_user_data => o_user_data,
o_user_channel => o_user_channel,
o_user_sender => o_user_sender,
o_busy => o_busy,
o_send_ready => o_send_ready,
o_recv_ready => o_recv_ready,
i_packet_data => i_packet_data,
i_packet_channel => i_packet_channel,
i_packet_sender => i_packet_sender,
i_packet_valid => i_packet_valid,
i_token => i_token,
o_token => o_token,
o_packet_data => o_packet_data,
o_packet_channel => o_packet_channel,
o_packet_sender => o_packet_sender,
o_packet_valid => o_packet_valid
);
tb : PROCESS
procedure send_packet(channel: in std_logic_vector(0 to 7); sender : in std_logic_vector(0 to 7); data : in std_logic_vector(0 to 31)) is
begin
-- Send a packet
wait until clk = '0' and o_send_ready = '1';
i_user_sender <= sender;
i_user_channel <= channel;
i_user_data <= data;
i_user_opcode <= x"04";
i_request <= '1';
wait until o_busy = '1' and clk = '1';
i_request <= '0';
wait until clk = '0';
i_user_sender <= (others => '0');
i_user_channel <= (others => '0');
i_user_data <= (others => '0');
i_user_opcode <= (others => '0');
wait until clk = '1';
end procedure send_packet;
procedure recv_packet is
begin
-- Receive a packet
wait until clk = '0' and o_recv_ready = '1';
i_user_sender <= (others => '0');
i_user_channel <= (others => '0');
i_user_data <= (others => '0');
i_user_opcode <= x"05";
i_request <= '1';
wait until o_busy = '1' and clk = '1';
i_request <= '0';
wait until clk = '0';
i_user_sender <= (others => '0');
i_user_channel <= (others => '0');
i_user_data <= (others => '0');
i_user_opcode <= (others => '0');
wait until clk = '1';
end procedure recv_packet;
procedure register_sender(sender: in std_logic_vector(0 to 7)) is
begin
-- Register sender
wait until clk = '0' and o_busy = '0';
i_user_sender <= sender;
i_user_opcode <= x"06";
i_request <= '1';
wait until o_busy = '1' and clk = '1';
i_request <= '0';
wait until clk = '0';
i_user_sender <= (others => '0');
i_user_opcode <= (others => '0');
wait until clk = '1';
end procedure register_sender;
procedure register_channel(channel: in std_logic_vector(0 to 7)) is
begin
-- Register channel
wait until clk = '0' and o_busy = '0';
i_user_channel <= channel;
i_user_opcode <= x"03";
i_request <= '1';
wait until o_busy = '1' and clk = '1';
i_request <= '0';
wait until clk = '0';
i_user_channel <= (others => '0');
i_user_opcode <= (others => '0');
wait until clk = '1';
end procedure register_channel;
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Reset the MM
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for 100 ns;
wait for 100 ns;
-- Register a channel
register_sender(x"AD");
wait for 50 ns;
register_channel(x"0A");
wait for 50 ns;
-- Send Packets
send_packet(x"11",x"BB",x"DEADBEEF");
wait for 50 ns;
send_packet(x"22",x"EE",x"CAFEBABE");
wait for 50 ns;
send_packet(x"33",x"11",x"22222222");
-- Receive token
i_token <= '1';
wait for 20 ns;
i_token <= '0';
-- Send Packets
wait for 20 ns;
send_packet(x"44",x"44",x"22222222");
-- Send Packets (This one should arrive after the send queue has emptied, and we have released the token, so it shouldn't be sent)
wait for 400 ns;
send_packet(x"55",x"BB",x"33333333");
-- Receive Packets from outside world
i_packet_data <= x"AAAAAAAA"; -- Wrong channel, shouldn't receive, but should forward
i_packet_sender <= x"01";
i_packet_channel <= x"0B";
i_packet_valid <= '1';
wait for 20 ns;
i_packet_valid <= '0';
wait for 100 ns;
i_packet_data <= x"91919191"; -- Right channel, should receive, and should forward
i_packet_sender <= x"01";
i_packet_channel <= x"0A";
i_packet_valid <= '1';
wait for 100 ns;
i_packet_valid <= '0';
wait for 100 ns;
i_packet_data <= x"23232323"; -- Right channel, should receive, and should forward
i_packet_sender <= x"01";
i_packet_channel <= x"0A";
i_packet_valid <= '1';
wait for 100 ns;
i_packet_valid <= '0';
wait for 100 ns;
i_packet_data <= x"85858585"; -- Sent by me, shouldn't receive or forward
i_packet_sender <= x"AD";
i_packet_channel <= x"0A";
i_packet_valid <= '1';
wait for 20 ns;
i_packet_valid <= '0';
wait for 20 ns;
-- Receive token again
i_token <= '1';
wait for 20 ns;
i_token <= '0';
wait for 100 ns;
-- Now the last remaining packet should be sent out
-- Ask the system for a packet (the one that was received earlier)
recv_packet;
recv_packet;
wait; -- will wait forever
END PROCESS;
clk_proc : process (clk)
begin
clk <= (not clk) after 10 ns;
end process clk_proc;
END;
|
gpl-3.0
|
0df20f3862b8e7bf3f3f82adc3bc3da7
| 0.617957 | 2.766833 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S16_S144.vhd
| 1 | 8,299 |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S16_S144.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (16 and 128) --
-- made for LL_FIFO. --
-- --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S16_S144 is
port (ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end entity BRAM_S16_S144;
architecture BRAM_S16_S144_arch of BRAM_S16_S144 is
component BRAM_S8_S72
port (
ADDRA: in std_logic_vector(11 downto 0);
ADDRB: in std_logic_vector(8 downto 0);
DIA: in std_logic_vector(7 downto 0);
DIB: in std_logic_vector(63 downto 0);
DIPB: in std_logic_vector(7 downto 0);
WEA: in std_logic;
WEB: in std_logic;
CLKA: in std_logic;
CLKB: in std_logic;
SSRA: in std_logic;
SSRB: in std_logic;
ENA: in std_logic;
ENB: in std_logic;
DOA: out std_logic_vector(7 downto 0);
DOB: out std_logic_vector(63 downto 0);
DOPB: out std_logic_vector(7 downto 0));
END component;
signal doa1 : std_logic_vector (7 downto 0);
signal dob1 : std_logic_vector (63 downto 0);
signal doa2 : std_logic_vector (7 downto 0);
signal dob2 : std_logic_vector (63 downto 0);
signal dia1 : std_logic_vector (7 downto 0);
signal dib1 : std_logic_vector (63 downto 0);
signal dia2 : std_logic_vector (7 downto 0);
signal dib2 : std_logic_vector (63 downto 0);
signal dipb1: std_logic_vector(7 downto 0);
signal dipb2: std_logic_vector(7 downto 0);
signal dopb1: std_logic_vector(7 downto 0);
signal dopb2: std_logic_vector(7 downto 0);
begin
dia1 <= DIA(7 downto 0);
dia2 <= DIA(15 downto 8);
DOA(7 downto 0) <= doa1;
DOA(15 downto 8) <= doa2;
dib1(7 downto 0) <= DIB(7 downto 0);
dib2(7 downto 0) <= DIB(15 downto 8);
dib1(15 downto 8) <= DIB(23 downto 16);
dib2(15 downto 8) <= DIB(31 downto 24);
dib1(23 downto 16) <= DIB(39 downto 32);
dib2(23 downto 16) <= DIB(47 downto 40);
dib1(31 downto 24) <= DIB(55 downto 48);
dib2(31 downto 24) <= DIB(63 downto 56);
dib1(39 downto 32) <= DIB(71 downto 64);
dib2(39 downto 32) <= DIB(79 downto 72);
dib1(47 downto 40) <= DIB(87 downto 80);
dib2(47 downto 40) <= DIB(95 downto 88);
dib1(55 downto 48) <= DIB(103 downto 96);
dib2(55 downto 48) <= DIB(111 downto 104);
dib1(63 downto 56) <= DIB(119 downto 112);
dib2(63 downto 56) <= DIB(127 downto 120);
DOB(7 downto 0) <= dob1(7 downto 0);
DOB(15 downto 8) <= dob2(7 downto 0);
DOB(23 downto 16) <= dob1(15 downto 8);
DOB(31 downto 24) <= dob2(15 downto 8);
DOB(39 downto 32) <= dob1(23 downto 16);
DOB(47 downto 40) <= dob2(23 downto 16);
DOB(55 downto 48) <= dob1(31 downto 24);
DOB(63 downto 56) <= dob2(31 downto 24);
DOB(71 downto 64) <= dob1(39 downto 32);
DOB(79 downto 72) <= dob2(39 downto 32);
DOB(87 downto 80) <= dob1(47 downto 40);
DOB(95 downto 88) <= dob2(47 downto 40);
DOB(103 downto 96) <= dob1(55 downto 48);
DOB(111 downto 104) <= dob2(55 downto 48);
DOB(119 downto 112) <= dob1(63 downto 56);
DOB(127 downto 120) <= dob2(63 downto 56);
dipb1(0 downto 0) <= DIPB(0 downto 0);
dipb2(0 downto 0) <= DIPB(1 downto 1);
dipb1(1 downto 1) <= DIPB(2 downto 2);
dipb2(1 downto 1) <= DIPB(3 downto 3);
dipb1(2 downto 2) <= DIPB(4 downto 4);
dipb2(2 downto 2) <= DIPB(5 downto 5);
dipb1(3 downto 3) <= DIPB(6 downto 6);
dipb2(3 downto 3) <= DIPB(7 downto 7);
dipb1(4 downto 4) <= DIPB(8 downto 8);
dipb2(4 downto 4) <= DIPB(9 downto 9);
dipb1(5 downto 5) <= DIPB(10 downto 10);
dipb2(5 downto 5) <= DIPB(11 downto 11);
dipb1(6 downto 6) <= DIPB(12 downto 12);
dipb2(6 downto 6) <= DIPB(13 downto 13);
dipb1(7 downto 7) <= DIPB(14 downto 14);
dipb2(7 downto 7) <= DIPB(15 downto 15);
DOPB(0 downto 0) <= dopb1(0 downto 0);
DOPB(1 downto 1) <= dopb2(0 downto 0);
DOPB(2 downto 2) <= dopb1(1 downto 1);
DOPB(3 downto 3) <= dopb2(1 downto 1);
DOPB(4 downto 4) <= dopb1(2 downto 2);
DOPB(5 downto 5) <= dopb2(2 downto 2);
DOPB(6 downto 6) <= dopb1(3 downto 3);
DOPB(7 downto 7) <= dopb2(3 downto 3);
DOPB(8 downto 8) <= dopb1(4 downto 4);
DOPB(9 downto 9) <= dopb2(4 downto 4);
DOPB(10 downto 10)<= dopb1(5 downto 5);
DOPB(11 downto 11)<= dopb2(5 downto 5);
DOPB(12 downto 12)<= dopb1(6 downto 6);
DOPB(13 downto 13)<= dopb2(6 downto 6);
DOPB(14 downto 14)<= dopb1(7 downto 7);
DOPB(15 downto 15)<= dopb2(7 downto 7);
bram1: BRAM_S8_S72
port map (
ADDRA => addra(11 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOB => dob1,
DOPB => dopb1);
bram2: BRAM_S8_S72
port map (
ADDRA => addra(11 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S16_S144_arch;
|
gpl-3.0
|
d59c8ab00f92ca2356703bb6f0605bc0
| 0.464273 | 3.817387 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/framework/importance.vhd
| 1 | 25,659 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity importance is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end importance;
architecture Behavioral of importance is
component uf_likelihood is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
init : in std_logic;
enable : in std_logic;
observation_loaded : in std_logic;
ref_data_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
observation_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
observation_size : in integer;
finished : out std_logic;
likelihood_value : out integer
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (STATE_INIT, STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES, STATE_READ_PARTICLE_SIZE, STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE, STATE_NEEDED_BURSTS, STATE_NEEDED_BURSTS_2,
STATE_NEEDED_READS_1, STATE_NEEDED_READS_2, STATE_READ_OBSERVATION_ADDRESS,
STATE_READ_REF_DATA_ADDRESS, STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1, STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3, STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5, STATE_LOAD_OBSERVATION,
STATE_LOAD_BURST_DECISION, STATE_LOAD_BURST, STATE_LOAD_READ_DECISION,
STATE_LOAD_READ, STATE_WRITE_TO_RAM,
STATE_LOAD_OBSERVATION_DATA_DECISION, STATE_LOAD_OBSERVATION_DATA_DECISION_2,
STATE_LOAD_OBSERVATION_DATA_DECISION_3,
STATE_LIKELIHOOD, STATE_LIKELIHOOD_DONE, STATE_WRITE_LIKELIHOOD,
STATE_SEND_MESSAGE, STATE_SEND_MEASUREMENT_1, STATE_SEND_MEASUREMENT_2 );
-- current state
signal state : t_state := STATE_INIT;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- reference data
signal reference_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles / observations (set by message box, default = 100)
signal N : integer := 10;
-- number of observations
signal remaining_observations : integer := 10;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 4;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal offset : integer := 0;
-- start observation index
--signal start_observation_index : integer := 0;
-- number of reads
signal number_of_reads : integer := 0;
-- number of needed reads to be remembered
signal number_of_reads_remember : integer := 0;
-- set to '1', if after the first run the reference data + the first observation is loaded
signal second_run : std_logic := '0';
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 10;
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- number of observations, where importance has to be calculated (max = block size)
signal number_of_calculations : integer := 10;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the likelihood user process
signal observation_loaded : std_logic := '0';
-- size of one observation
signal observation_size_2 : integer := 0;
-- reference data address
signal ref_data_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- observation data address
signal observation_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- if the likelihood value is calculated, this signal is set to '1'
signal finished : std_logic := '0';
-- likelihood value
signal likelihood_value : integer := 128;
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrLikelihood : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrImportance : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWELikelihood : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEImportance : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataLikelihood : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataImportance : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_likelihood
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrLikelihood, o_RAMData=>o_RAMDataLikelihood,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWELikelihood, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, observation_loaded=>observation_loaded,
ref_data_address=>ref_data_address, observation_address=>observation_address,
observation_size=>observation_size_2, finished=>finished, likelihood_value=>likelihood_value);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrLikelihood(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrLikelihood(C_TASK_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrImportance(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrImportance(C_TASK_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWELikelihood when enable = '1' else o_RAMWEImportance;
-- switch 3: output ram data
o_RAMData <= o_RAMDataLikelihood when enable = '1' else o_RAMDataImportance;
observation_size_2 <= observation_size / 4;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Importance:
--
-- 1) Information are set (like particle array address and
-- particle and observation size)
--
--
-- 2) Waiting for Message m (Start of a Importance run)
-- Calculate likelihood values for particles of m-th particle block
-- i = 0
--
--
-- 3) Calculate if block size particles should be calculated
-- or less (iff last particle block)
--
--
-- 4) The Reference Histogram ist copied to the local ram
--
--
-- 5) If there is still a observation left (i < counter) then
-- go to step 6;
-- else
-- go to step 9;
-- end if
--
--
-- 6) The observation is copied into the local ram
--
--
-- 7) Start and run likelihood user process
-- i++;
--
--
-- 8) After likelihood user process is finished,
-- write back the weight to particle array
-- go to step 5;
--
--
-- 9) Send Message m (Stop of a Importance run)
-- Likelihood values for particles of m-th particle block calculated
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK (1 of 6) !!!
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
if done then
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
observation_loaded <= '0';
state <= STATE_READ_PARTICLE_ADDRESS;
-- CHANGE BACK (2 of 6) !!!
--state <= STATE_NEEDED_BURSTS;
end if;
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
temp4 <= observation_size / 4;
state <= STATE_NEEDED_BURSTS_2;
when STATE_NEEDED_BURSTS_2 =>
--! calculate needed bursts
observation_address <= local_ram_address_if + temp4;
state <= STATE_NEEDED_READS_1;
when STATE_NEEDED_READS_1 =>
--! calculate number of reads (1 of 2)
-- change this back
-- old
--number_of_reads_remember <= observation_size mod 128;
-- changed (new) [2 lines]
number_of_reads_remember <= observation_size;
number_of_bursts_remember <= 0;
state <= STATE_NEEDED_READS_2;
when STATE_NEEDED_READS_2 =>
--! calculate number of reads (2 of 2)
number_of_reads_remember <= number_of_reads_remember / 4;
state <= STATE_READ_OBSERVATION_ADDRESS;
when STATE_READ_OBSERVATION_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_REF_DATA_ADDRESS;
end if;
-- -- CHANGE BACK (3 of 6) !!!
-- observation_array_start_address <= "00100000000000000000000000000000";
-- state <= STATE_READ_REF_DATA_ADDRESS;
when STATE_READ_REF_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, information_struct+24, reference_data_address);
if done then
state <= STATE_WAIT_FOR_MESSAGE;
end if;
-- -- CHANGE BACK (4 of 6) !!!
-- -- ref data address = 10000040
-- reference_data_address <= "00010000000000000000000001000000";
-- state <= STATE_WAIT_FOR_MESSAGE;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
observation_loaded <= '0';
enable <= '0';
init <= '1';
second_run <= '0';
time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
temp <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
number_of_calculations <= block_size;
else
number_of_calculations <= remaining_observations;
end if;
state <= STATE_LOAD_OBSERVATION;
when STATE_LOAD_OBSERVATION =>
--! prepare to load an observation to local ram
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
load_address <= reference_data_address;
state <= STATE_LOAD_BURST_DECISION;
when STATE_LOAD_BURST_DECISION =>
--! decision if a burst is needed
if (number_of_bursts > 0) then
state <= STATE_LOAD_BURST;
number_of_bursts <= number_of_bursts - 1;
else
state <= STATE_LOAD_READ_DECISION;
end if;
when STATE_LOAD_BURST =>
--! load bursts of observation
reconos_read_burst(done, o_osif, i_osif, local_ram_address, load_address);
if done then
local_ram_address <= local_ram_address + 128;
load_address <= load_address + 128;
local_ram_address_if <= local_ram_address_if + 32;
state <= STATE_LOAD_BURST_DECISION;
end if;
when STATE_LOAD_READ_DECISION =>
--! decision if a read into local ram is needed
if (number_of_reads > 0) then
state <= STATE_LOAD_READ;
number_of_reads <= number_of_reads - 1;
elsif (second_run = '1') then
state <= STATE_LIKELIHOOD;
else
second_run <= '1';
state <= STATE_LOAD_OBSERVATION_DATA_DECISION;
end if;
when STATE_LOAD_READ =>
--! load reads of observation
reconos_read_s(done, o_osif, i_osif, load_address, ram_data);
if done then
load_address <= load_address + 4;
state <= STATE_WRITE_TO_RAM;
end if;
when STATE_WRITE_TO_RAM =>
--! write value to ram
o_RAMWEImportance<= '1';
o_RAMAddrImportance <= local_ram_address_if;
o_RAMDataImportance <= ram_data;
local_ram_address_if <= local_ram_address_if + 1;
state <= STATE_LOAD_READ_DECISION;
when STATE_LOAD_OBSERVATION_DATA_DECISION =>
--! first step of calculation of observation address
observation_offset <= number_of_calculations - remaining_observations;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION_2;
when STATE_LOAD_OBSERVATION_DATA_DECISION_2 =>
--! decide, if there is another observation to be handled, else post semaphore
o_RAMWEImportance <= '0';
local_ram_address <= local_ram_start_address + observation_size;
local_ram_address_if <= observation_address;
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
offset <= observation_offset * observation_size ;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION_3;
when STATE_LOAD_OBSERVATION_DATA_DECISION_3 =>
--! decide, if there is another observation to be handled, else post semaphore
load_address <= observation_array_address + offset;
if (remaining_observations > 0) then
state <= STATE_LOAD_BURST_DECISION;
else
time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
when STATE_LIKELIHOOD =>
--! start and run likelihood user process
init <= '0';
enable <= '1';
observation_loaded <= '1';
state <= STATE_LIKELIHOOD_DONE;
when STATE_LIKELIHOOD_DONE =>
--! wait until the likelihood user process is finished
observation_loaded <= '0';
if (finished = '1') then
enable <= '0';
init <= '1';
state <= STATE_WRITE_LIKELIHOOD;
remaining_observations <= remaining_observations - 1;
end if;
when STATE_WRITE_LIKELIHOOD =>
--! write likelihood value into the particle array
reconos_write(done, o_osif, i_osif, particle_array_address, STD_LOGIC_VECTOR(TO_SIGNED(likelihood_value, C_OSIF_DATA_WIDTH)));
if done and success then
particle_array_address <= particle_array_address + particle_size;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION;
end if;
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
observation_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
-- when STATE_SEND_MEASUREMENT_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
--
-- state <= STATE_WAIT_FOR_MESSAGE;
-- end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
b58a61502146ee37fff95e70fe6a95d6
| 0.563194 | 4.098882 | false | false | false | false |
williammacdowell/gcm
|
src/fpga/shift_rows_ea.vhd
| 1 | 3,298 |
-------------------------------------------------------------------------------
-- Title : Shift Rows
-- Project : AES-GCM
-------------------------------------------------------------------------------
-- File : shift_rows_ea.vhd
-- Author : Bill MacDowell <bill@bill-macdowell-laptop>
-- Company :
-- Created : 2017-03-20
-- Last update: 2017-03-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Implementation of the shift-rows portion of the AES cipher as
-- described in the FIPS 197 AES Spec. This module takes a 128-bit input block,
-- and shifts the rows of the matrix as depicted below.
--
-- Input Matrix: Output Matrix:
-- | 0 4 8 12 | | 0 4 8 12 | no shift
-- | 1 5 9 13 | -> | 5 9 13 1 | 1 shift left
-- | 2 6 10 14 | | 10 14 2 6 | 2 shifts left
-- | 3 7 11 15 | | 15 3 7 11 | 3 shifts left
-- * where the numbers in the matrix indicate byte indicies of the 128-bit block
--
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-03-20 1.0 bill Created
-------------------------------------------------------------------------------
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.gcm_pkg.all;
entity shift_rows is
port (
clk : in std_logic;
rst : in std_logic;
block_in : in std_logic_vector(127 downto 0);
block_out : out std_logic_vector(127 downto 0));
end entity shift_rows;
architecture rtl of shift_rows is
-- These are for converting the 128-bit vectors to 4x4 byte matricies
signal matrix_in : t_matrix;
signal matrix_out : t_matrix;
begin
-- Convert between 128-bit vector and 4x4 byte matrix here. No added logic,
-- just some type conversions to make VHDL happy
v2m : process (block_in) is
begin
matrix_in <= vector_to_matrix(block_in);
end process v2m;
m2v : process (matrix_out) is
begin
block_out <= matrix_to_vector(matrix_out);
end process m2v;
-- This process shifts the rows of the matrix as shown in the header comment
shift_rows_proc : process (clk) is
begin
if clk'event and clk = '1' then
-- row 0 - 0 shift
matrix_out(0) <= matrix_in(0);
matrix_out(4) <= matrix_in(4);
matrix_out(8) <= matrix_in(8);
matrix_out(12) <= matrix_in(12);
-- row 1 - 1 shift left
matrix_out(1) <= matrix_in(5);
matrix_out(5) <= matrix_in(9);
matrix_out(9) <= matrix_in(13);
matrix_out(13) <= matrix_in(1);
-- row 2 - 2 shifts left
matrix_out(2) <= matrix_in(10);
matrix_out(6) <= matrix_in(14);
matrix_out(10) <= matrix_in(2);
matrix_out(14) <= matrix_in(6);
-- row 3 - 3 shifts left
matrix_out(3) <= matrix_in(15);
matrix_out(7) <= matrix_in(3);
matrix_out(11) <= matrix_in(7);
matrix_out(15) <= matrix_in(11);
if rst = '1' then
matrix_out <= (others => (others => '0'));
end if;
end if;
end process shift_rows_proc;
end rtl;
|
gpl-3.0
|
061f6e61f9a9a4c76061b90f9d0b909a
| 0.512129 | 3.557713 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/framework/resampling.vhd
| 1 | 24,604 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity resampling is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end resampling;
architecture Behavioral of resampling is
component uf_resampling
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
Port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the resampling user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- number of particles in total
number_of_particles_in_total : in integer;
-- index of first particles (the particles are sorted increasingly)
start_particle_index : in integer;
-- resampling function init
U_init : in integer;
-- address of the last 128 byte burst in local RAM
write_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- information if a write burst has been handled by the Framework
write_burst_done : in std_logic;
-- this signal has to be set to '1', if the Framework should write
-- the last burst from local RAM into Maim Memory
write_burst : out std_logic;
-- write burst done acknowledgement
write_burst_done_ack : out std_logic;
-- number of currently written particles
written_values : out integer;
-- if every particle is resampled, this signal has to be set to '1'
finished : out std_logic);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (STATE_INIT, STATE_READ_PARTICLES_ADDRESS, STATE_READ_INDEXES_ADDRESS,
STATE_READ_N, STATE_READ_PARTICLE_SIZE, STATE_READ_MAX_NUMBER_OF_PARTICLES,
STATE_READ_BLOCK_SIZE, STATE_READ_U_FUNCTION,
STATE_WAIT_FOR_MESSAGE, STATE_CALCULATE_REMAINING_PARTICLES_1,
STATE_CALCULATE_REMAINING_PARTICLES_2, STATE_CALCULATE_REMAINING_PARTICLES_3,
STATE_CALCULATE_REMAINING_PARTICLES_4, STATE_CALCULATE_REMAINING_PARTICLES_5,
STATE_LOAD_U_INIT, STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1,
STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_2, STATE_WRITE_TO_RAM,
STATE_WRITE_BURST_DECISION, STATE_WRITE_BURST_DECISION_2, STATE_WRITE_BURST,
STATE_WRITE_DECISION, STATE_READ, STATE_WRITE,
STATE_WRITE_BURST_DONE_ACK, STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1, STATE_SEND_MEASUREMENT_2 );
-- current state
signal state : t_state := STATE_INIT;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- index array
signal index_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"10000000";
signal index_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- resampling function U array
signal U_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"10000000";
signal U_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_if_write : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_address_if_read : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- local RAM write_address
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like N, particle size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- message (received from message box). The number in the message says,
-- which particle block has to be sampled
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- block size, is the number of particles in a particle block
signal block_size : integer := 10;
-- local RAM data (particle weight)
signal weight_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 18;
-- number of particles still to resample
signal remaining_particles : integer := 0;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- size of a particle
signal particle_size : integer := 8;
-- temp variable
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
-- number of particles to resample
signal number_of_particles_to_resample : integer := 9;
-- write counter
signal write_counter : integer := 0;
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- start index
signal start_index : integer := 3;
-- temporary variables
signal offset : integer := 1;
signal offset2 : integer := 1;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for resampling user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the resampling user process
signal particles_loaded : std_logic := '0';
-- number of particles in local RAM
signal number_of_particles : integer := 18;
-- number of particles in total
signal number_of_particles_in_total : integer := 18;
-- index of first particles (the particles are sorted increasingly)
signal start_particle_index : integer := 0;
-- resampling function init
signal U_init : integer := 2000;
-- address of the last 128 byte burst in local RAM
signal write_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- information if a write burst has been handled by the Framework
signal write_burst_done : std_logic := '0';
-- the last burst from local RAM into Maim Memory
signal write_burst : std_logic := '0';
-- number of currently written index values
signal written_values : integer := 0;
-- if every particle is resampled, this signal has to be set to '1'
signal finished : std_logic := '0';
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrUserProcess : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrResampling : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEUserProcess : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEResampling : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataUserProcess : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataResampling : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- write burst done acknowledgement
signal write_burst_done_ack : std_logic := '0';
begin
-- entity of user process
user_process : uf_resampling
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrUserProcess, o_RAMData=>o_RAMDataUserProcess,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWEUserProcess, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, particles_loaded=>particles_loaded,
number_of_particles=>number_of_particles,
number_of_particles_in_total => number_of_particles_in_total,
start_particle_index=>start_particle_index,
U_init=>U_init, write_address=>write_address,
write_burst_done=>write_burst_done, write_burst=>write_burst,
write_burst_done_ack=>write_burst_done_ack, written_values=>written_values,
finished=>finished);
-- burst ram interface
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrUserProcess(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrUserProcess(C_TASK_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrResampling(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrResampling(C_TASK_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEUserProcess when enable = '1' else o_RAMWEResampling;
-- switch 3: output ram data
o_RAMData <= o_RAMDataUserProcess when enable = '1' else o_RAMDataResampling;
number_of_particles_in_total <= N;
write_address <= "11111100000";
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Resampling:
--
-- 1) The index array adress, the number of particles (N) and
-- the particle size is received by message boxes
--
--
-- 2) Waiting for Message m (Start of a Resampling run)
-- Resample particles of m-th block
--
--
-- 3) calcualte the number of particles, which have to be resampled
--
--
-- 4) Copy the weight of the particles to the local RAM
--
--
-- 5) The user resampling process is started
--
--
-- 6) Every time the user process demands to make a write burst into
-- the index array, it is done by the Framework
--
--
-- 7) If the user process is finished go to step 8
--
--
-- 8) Send Message m (Stop of a Resampling run)
-- Particles of m-th block are resampled
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and max number of particles which fit in the local RAM
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable U_init_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
--! init state, receive particle array address
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK !!! (1 of 3)
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_address);
enable <= '0';
init <= '1';
if done then
state <= STATE_READ_PARTICLES_ADDRESS;
-- CHANGE BACK !!! (2 of 3)
--state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_READ_PARTICLES_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_INDEXES_ADDRESS;
end if;
when STATE_READ_INDEXES_ADDRESS =>
--! read index array address
reconos_read_s (done, o_osif, i_osif, information_struct+4, index_array_start_address);
if done then
state <= STATE_READ_N;
end if;
when STATE_READ_N =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+8, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read number of particles to resample
reconos_read (done, o_osif, i_osif, information_struct+16, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_U_FUNCTION;
end if;
when STATE_READ_U_FUNCTION =>
--! read start index of first particle to resample
reconos_read_s (done, o_osif, i_osif, information_struct+20, U_array_start_address);
if done then
state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for Message, that starts resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
--remaining_particles <= number_of_particles_to_resample;
--index_array_address <= index_array_address;
--particle_array_address <= particle_array_address;
local_ram_address <= (others=>'0');
local_ram_address_if_read <= (others=>'0');
local_ram_address_if_write <= (others=>'0');
init <= '1';
enable <= '0';
particles_loaded <= '0';
state <= STATE_CALCULATE_REMAINING_PARTICLES_1;
time_start <= TO_INTEGER(SIGNED(i_timebase));
-- CHANGE BACK !!! (3 of 3)
--state <= STATE_NEEDED_BURSTS_1;
end if;
when STATE_CALCULATE_REMAINING_PARTICLES_1 =>
--! calcualte remaining particles
message2 <= message - 1;
state <= STATE_CALCULATE_REMAINING_PARTICLES_2;
when STATE_CALCULATE_REMAINING_PARTICLES_2 =>
--! calcualte remaining particles
offset <= message2 * block_size;
temp2 <= message2 * 4;
state <= STATE_CALCULATE_REMAINING_PARTICLES_3;
when STATE_CALCULATE_REMAINING_PARTICLES_3 =>
--! calcualte remaining particles
temp3 <= offset * 8;
state <= STATE_CALCULATE_REMAINING_PARTICLES_4;
when STATE_CALCULATE_REMAINING_PARTICLES_4 =>
--! calcualte remaining particles
remaining_particles <= N - offset;
index_array_address <= index_array_start_address + temp3;
start_index <= offset;
start_particle_index <= offset;
temp4 <= offset * particle_size;
U_array_address <= U_array_start_address + temp2;
state <= STATE_CALCULATE_REMAINING_PARTICLES_5;
when STATE_CALCULATE_REMAINING_PARTICLES_5 =>
--! calcualte remaining particles
if (remaining_particles > block_size) then
number_of_particles_to_resample <= block_size;
remaining_particles <= block_size;
else
number_of_particles_to_resample <= remaining_particles;
end if;
particle_array_address <= particle_array_start_address + temp4;
state <= STATE_LOAD_U_INIT;
when STATE_LOAD_U_INIT =>
--! load U_init
reconos_read (done, o_osif, i_osif, U_array_address, U_init_var);
if done then
U_init <= TO_INTEGER(SIGNED(U_init_var));
state <= STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1;
number_of_particles <= remaining_particles;
end if;
when STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1 =>
--! load weights to local ram, if this is done start the resampling
o_RAMWEResampling<= '0';
if (remaining_particles > 0) then
remaining_particles <= remaining_particles - 1;
state <= STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_2;
else
enable <= '1';
particles_loaded <= '1';
init <= '0';
state <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_2 =>
--! load weights to local ram
reconos_read_s (done, o_osif, i_osif, particle_array_address, weight_data);
if done then
state <= STATE_WRITE_TO_RAM;
particle_array_address <= particle_array_address + particle_size;
end if;
when STATE_WRITE_TO_RAM =>
--! write value to ram
o_RAMWEResampling<= '1';
o_RAMAddrResampling <= local_ram_address_if_read;
o_RAMDataResampling <= weight_data;
local_ram_address_if_read <= local_ram_address_if_read + 1;
state <= STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1;
when STATE_WRITE_BURST_DECISION =>
--! if write burst is demanded by user process, it will be done
write_burst_done <= '0';
if (finished = '1') then
-- everything is finished
state <= STATE_SEND_MESSAGE;
enable <= '0';
particles_loaded <= '0';
time_stop <= TO_INTEGER(SIGNED(i_timebase));
--init <= '1';
elsif (write_burst = '1') then
--state <= STATE_WRITE_BURST;
state <= STATE_WRITE_BURST_DECISION_2;
end if;
when STATE_WRITE_BURST_DECISION_2 =>
--! decides if there will be a burst or there will be several writes
-- NO MORE BURSTS
--if (written_values = 16) then
-- write only burst, if the burst is full
-- state <= STATE_WRITE_BURST;
--else
local_ram_address_if_write <= write_address;
write_counter <= 2 * written_values;
enable <= '0';
state <= STATE_WRITE_DECISION;
--end if;
when STATE_WRITE_BURST =>
--! write bursts from local ram into index array
reconos_write_burst(done, o_osif, i_osif, (local_ram_start_address + 8064), index_array_address);
if done then
write_burst_done <= '1';
index_array_address <= index_array_address + 128;
state <= STATE_WRITE_BURST_DONE_ACK;
end if;
when STATE_WRITE_DECISION =>
-- decides if there is still something to write
if (write_counter > 0) then
o_RAMAddrResampling <= local_ram_address_if_write;
state <= STATE_READ;
else
write_burst_done <= '1';
enable <= '1';
state <= STATE_WRITE_BURST_DONE_ACK;
end if;
when STATE_READ =>
--! read index values
state <= STATE_WRITE;
when STATE_WRITE =>
--! write data to index array
reconos_write(done, o_osif, i_osif, index_array_address, i_RAMData);
if done then
index_array_address <= index_array_address + 4;
local_ram_address_if_write <= local_ram_address_if_write + 1;
write_counter <= write_counter - 1;
state <= STATE_WRITE_DECISION;
end if;
when STATE_WRITE_BURST_DONE_ACK =>
--! write bursts from local ram into index array
if (write_burst_done_ack = '1') then
write_burst_done <= '0';
state <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_SEND_MESSAGE =>
--! send Message (resampling is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
particles_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
--when STATE_SEND_MEASUREMENT_2 =>
--! sends time measurement to message box
-- send message
--reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
-- state <= STATE_WAIT_FOR_MESSAGE;
--end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
b5a8f3cc98e7882699665e3698c12f84
| 0.558893 | 3.972231 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_test4.vhd
| 2 | 492 |
--
-- Author: Pawel Szostek ([email protected])
-- Date: 27.07.2011
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(7 downto 0);
o2: out std_logic_vector(7 downto 0);
o3: out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
o1 <= (others => '0');
o2 <= (3 => '1', others => '0');
o3 <= (7=>'1', 6|5|4|3|2|1|0 => '0', others => '1'); --tricky
end;
|
gpl-2.0
|
0cf640797db49b3abc80324258d2865e
| 0.579268 | 2.703297 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_core.vhd
| 7 | 24,894 |
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vhd
--
-- Description: Provides a simple synchronous interface to a
-- AC97 codec. This was designed for the National
-- LM4549A and only supports slots 0-4.
-- This interface does not have any data buffering.
--
-- The interface to the AC97 is straightforward.
-- To transfer playback data, this interface will
-- sample the playback data and control signals
-- when the PCM_Playback_X_Accept signals are asserted.
-- This sample will
-- be sent to the codec during the next frame. The Record (
-- input) data is provided as an ouptput and is valid when
-- new_frame is asserted.
--
-- This core supports the full 20-bit PCM sample size. The
-- actual size of the PCM can be modified to a lower value for
-- easier interfacing using the C_PCM_DATA_WIDTH generic. This
-- core will stuff the remaining lsb bits with '0' if a value
-- lower than 20 is used.
--
-- This core is synchronous to the AC97_Bit_Clk and all
-- signals interfacing to this core should be synchronized to
-- this clock.
--
-- AC97 Register Interface
--
-- This core provides a simple interface to the AC97 codec registers. To write
-- a new value to the register, drive the AC97_Reg_Addr and
-- AC97_Reg_Write_Data input signals and assert the AC97_Reg_Write_Strobe
-- signal. To read a register value, drive the AC97_Reg_Addr and assert
-- the AC97_Reg_Read_Strobe signal. Once either strobe has been asserted, the
-- register interface state machine will process the request to the CODEC and
-- assert the AC97_Reg_Busy signal. The strobe control signals will be ignored
-- while the state machine is busy (the AC97 only supports one read or write
-- transaction at a time).
--
-- When the transaction is complete, the state machine will respond as
-- follows: first, the AC97_Reg_Busy signal will be deasserted indicating that
-- the transaction is complete and that the interface is ready to handle
-- another interface. If there was an error with the response (i.e. the AC97
-- codec did not respond properly to the request), the AC97_Reg_Error signal
-- will be asserted. This signal will remain asserted until a new register
-- transfer has been initiated.
--
-- On the successful completion of a register read operation, the
-- AC97_Reg_Read_Data_Valid signal will be asserted to validate the data
-- read from the AC97 controller. This signal will remain asserted until a new
-- register transaction is initiated.
--
--
-- This core will produce valid data on the AC97_SData_Out signal
-- during the following slots:
--
-- Slot 0: Tag Phase (indicates valid slots in packet)
-- Slot 1: Read/Write, Control Address
-- Slot 2: Command Data
-- Slot 3: PCM Left
-- Slot 4: PCM Right
--
-- This core will recognize valid data on the AC97_SData_In signal
-- during the following slots:
--
-- Slot 0: Codec/Slot Status Bits
-- Slot 1: Status Address / Slot Request
-- Slot 2: Status Data
-- Slot 3: PCM Record Left
-- Slot 4: PCM Record Righ
--
-- To Do:
-- - signal to validate recorded data
-- - signal to "request" playback data
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- - ac97_core
-- - ac97_timing
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.TextIO.all;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-------------------------------------------------------------------------------
--
-- Genearics Summary
-- C_PLAYBACK: Enable playback logic. Disable to simplify circuit
-- C_RECORD: Enable record logic. Disable to simplify circuit
-- C_PCM_DATA_WIDTH:
-- AC97 specifies a 20-bit data word. HOwever, many codecs don't
-- support the full resolution (The LM4549 only supports 18). This
-- value indicates the number of data bits that will be sent/received
-- from the CODEC. Zeros will be inserted for least-significant digits.
--
-- Signal Summary
--
-- AC97_Bit_Clk:
-- Input clock generated by the AC97 Codec
-- AC97_Sync:
-- Frame synchronization signal. Generated by ac97_timing module.
-- AC97_SData_Out:
-- Serial data out. Transitions on the rising edge of bit_clk. Is
-- sampled by the CODEC on the falling edge
-- AC97_SData_In:
-- Serial data in. Transitions on the rising edge of bit_clk. Is
-- sampled by the this module on the falling edge.
-- AC97_SData_In:
-- CODEC_RDY:
-- This signal is generated by each frame from the AC97
-- Codec. It arrives each frame as the first bit of Slot 1.
-------------------------------------------------------------------------------
entity ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
--
CODEC_RDY : out std_logic
);
end entity ac97_core;
library unisim;
use unisim.all;
architecture IMP of ac97_core is
component ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end component ac97_timing;
signal last_frame_cycle : std_logic;
signal sync_i : std_logic;
signal slot_end : std_logic;
signal slot_No : natural range 0 to 12;
--signal bit_No : natural range 0 to 19;
-- register IF signals
type reg_if_states is (IDLE, WAIT_FOR_NEW_FRAME, SEND_REQUEST_FRAME,
RESPONSE_SLOT0, RESPONSE_SLOT1, RESPONSE_SLOT2,
END_STATE);
signal reg_if_state : reg_if_states := IDLE;
signal register_addr : std_logic_vector(0 to 6) := (others => '0');
signal register_data : std_logic_vector(0 to 15) := (others => '0');
signal register_write_cmd : std_logic := '0';
signal ac97_reg_error_i, ac97_reg_busy_i : std_logic := '0';
signal valid_Frame : std_logic;
signal valid_Control_Addr : std_logic;
-- Slot 0 in signals
signal record_pcm_left_valid : std_logic;
signal record_pcm_right_valid : std_logic;
--signal return_status_address_valid : std_logic;
--signal return_status_data_valid : std_logic;
signal accept_pcm_left : std_logic;
signal accept_pcm_right : std_logic;
signal new_data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_in : std_logic_vector(19 downto 0);
signal slot0 : std_logic_vector(15 downto 0);
signal slot1 : std_logic_vector(19 downto 0);
signal slot2 : std_logic_vector(19 downto 0);
signal slot3 : std_logic_vector(19 downto 0) := (others => '0');
signal slot4 : std_logic_vector(19 downto 0) := (others => '0');
signal codec_rdy_i : std_logic := '0';
signal PCM_Record_Left_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
signal PCM_Record_Right_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- AC97 Timing Module & Interface signals
-----------------------------------------------------------------------------
ac97_timing_I_1 : ac97_timing
port map (
Bit_Clk => AC97_Bit_Clk,
Reset => Reset,
Sync => sync_i,
Bit_Num => open,
Slot_Num => slot_No,
Slot_End => slot_end,
Frame_End => last_frame_cycle
);
AC97_Sync <= sync_i;
-----------------------------------------------------------------------------
-- AC97 Register Interface
-----------------------------------------------------------------------------
-- Register state machine
register_if_PROCESS : process (AC97_Bit_Clk) is
begin
if RESET = '1' then
reg_if_state <= IDLE;
ac97_reg_busy_i <= '0';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
case reg_if_state is
-- Wait for a register transfer strobe to occur.
when IDLE =>
if (AC97_Reg_Read_Strobe = '1' or AC97_Reg_Write_Strobe = '1')
and codec_rdy_i = '1' then
reg_if_state <= WAIT_FOR_NEW_FRAME;
ac97_reg_busy_i <= '1';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
register_addr <= AC97_Reg_Addr;
if AC97_Reg_Write_Strobe = '1' then
register_data <= AC97_Reg_Write_Data;
register_write_cmd <= '1';
else
register_write_cmd <= '0';
end if;
end if;
-- Wait for the end of the current frame. During the last cycle of
-- this state (last_frame_cycle = 1), all the signals are
-- latched into slot 0 and a valid request is on its way out.
when WAIT_FOR_NEW_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= SEND_REQUEST_FRAME;
end if;
-- Wait for the request to be completely sent to the codec.
when SEND_REQUEST_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= RESPONSE_SLOT0;
end if;
-- Wait for the response in slot 0 and make sure the
-- appropriate response bits are set
when RESPONSE_SLOT0 =>
if slot_No = 0 and slot_end = '1' then
if register_write_cmd = '0' then
if (data_in(14) /= '1' or data_in(13) /= '1') then
-- Bit 14 of Slot 0 indicates a valid slot 1 data
-- (echo the requested address). If this is not a
-- '1' then there is was an error. Bit 13 of Slot 0
-- indicates a valid data response. If the transaction
-- was a read and it is not true, an error.
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
reg_if_state <= RESPONSE_SLOT1;
end if;
else
-- Nothing else to do for writes
reg_if_state <= END_STATE;
end if;
end if;
-- Check the data in slot 1 and make sure it matches
-- the address sent
when RESPONSE_SLOT1 =>
if slot_No = 1 and slot_end = '1' then
if data_in(18 downto 12) /= register_addr then
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
-- we need to get the data for read commands
reg_if_state <= RESPONSE_SLOT2;
end if;
end if;
when RESPONSE_SLOT2 =>
if slot_No = 2 and slot_end = '1' then
AC97_Reg_Read_Data <= data_in(19 downto 4);
AC97_Reg_Read_Data_Valid <= '1';
reg_if_state <= END_STATE;
end if;
when END_STATE =>
ac97_reg_busy_i <= '0';
reg_if_state <= IDLE;
when others => NULL;
end case;
end if;
end process register_if_PROCESS;
AC97_Reg_Busy <= ac97_reg_busy_i;
AC97_Reg_Error <= ac97_reg_error_i;
with reg_if_state select
debug(0 to 2) <= "000" when IDLE,
"001" when WAIT_FOR_NEW_FRAME,
"010" when SEND_REQUEST_FRAME,
"011" when RESPONSE_SLOT0,
"100" when RESPONSE_SLOT1,
"101" when RESPONSE_SLOT2,
"110" when END_STATE,
"000" when others;
debug(3 to 15) <= (others => '0');
-- This signal indicates that we are sending a request command
-- and that the address send to the codec is valid
valid_Control_Addr <= '1' when reg_if_state = WAIT_FOR_NEW_FRAME
else '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Setup slot0 data at start of frame
--
-- Slot 0 is the TAG slot. The bits of this slot are defined as
-- follows:
-- bit 15: Valid frame
-- bit 14: valid control address (slot 1)
-- bit 13: valid control data (slot 2)
-- bit 12: valid PCM playback data Left (slot 3)
-- bit 11: valid PCM playback data Right (slot 4)
-- bot 10-2: ignored - fill with zeros
-- bit 1-0: 2-bit codec ID (assigned to '00' for primary)
--
-- The slot 0 signals are created directly from the inputs
-- of the module rather than using the "registered" versions
-- (i.e. ac97_reg_write instead of ac97_reag_write_i). The
-- slot0 signal is latched on the clock edge following
-- the frame signal into the shift register signal "data_out".
--
-----------------------------------------------------------------------------
-- temporary
valid_Frame <= valid_Control_Addr or
pcm_playback_left_valid or
pcm_playback_right_valid;
slot0(15) <= valid_Frame;
slot0(14) <= valid_Control_Addr;
slot0(13) <= register_write_cmd; -- valid data only during write
slot0(12) <= PCM_Playback_Left_Valid;
slot0(11) <= PCM_Playback_Right_Valid;
slot0(10 downto 2) <= "000000000";
slot0(1 downto 0) <= "00";
-----------------------------------------------------------------------------
-- Slot 1
--
-- Slot 1 is the Command Address:
-- Bit 19: Read/Write (1=read,0=write)
-- Bit 18-12: Control register index/address
-- Bit 11:0 reserved (stuff with 0)
-----------------------------------------------------------------------------
slot1(19) <= not register_write_cmd;
slot1(18 downto 12) <= register_addr;
slot1(11 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Slot 2
--
-- Slot 2 is the Command Data Port:
-- Bit 19-4: Control register write data
-- Bit 3-0: reserved (stuff with 0)
-----------------------------------------------------------------------------
slot2(19 downto 4) <= register_data;
slot2( 3 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Setup slot3 data (PCM play left)
-----------------------------------------------------------------------------
process (PCM_Playback_Left) is
begin
slot3((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot3(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Left;
end process;
-----------------------------------------------------------------------------
-- Setup slot4 data (PCM play right)
-----------------------------------------------------------------------------
process (PCM_Playback_Right) is
begin
slot4((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot4(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Right;
end process;
-----------------------------------------------------------------------------
-- Output data multiplexer for AC97_SData_Out signal
--
-- Choose the appropriate data to send out the shift register
-- (new_data_out)
-----------------------------------------------------------------------------
process (last_frame_cycle, slot_end, slot_No, slot0,
slot1, slot2, slot3, slot4) is
begin -- process
new_data_out <= (others => '0');
if (last_frame_cycle = '1') then
new_data_out(19 downto 4) <= slot0;
elsif (slot_end = '1') then
case slot_No is
when 0 => new_data_out(slot1'range) <= slot1;
when 1 => new_data_out(slot2'range) <= slot2;
when 2 => new_data_out <= slot3;
when 3 => new_data_out <= slot4;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 data out shift register
-----------------------------------------------------------------------------
Data_Out_Handle : process (AC97_Bit_Clk) is
begin -- process Data_Out_Handle
if reset = '1' then
data_out <= (others => '0');
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (last_frame_cycle = '1') or (slot_end = '1') then
data_out <= New_Data_Out;
else
data_out(19 downto 0) <= data_out(18 downto 0) & '0';
end if;
end if;
end process Data_Out_Handle;
AC97_SData_Out <= data_out(19);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Input Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- AC97 data in shift register
-----------------------------------------------------------------------------
Shifting_Data_Coming_Back : process (AC97_Bit_Clk) is
begin -- process Shifting_Data_Coming_Back
if AC97_Bit_Clk'event and AC97_Bit_Clk = '0' then -- falling clock edge
data_in(19 downto 0) <= data_in(18 downto 0) & AC97_SData_In;
end if;
end process Shifting_Data_Coming_Back;
-----------------------------------------------------------------------------
-- Get slot 0 data (TAG - which slots are valid)
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_no = 0 and slot_end = '1') then
codec_rdy_i <= data_in(15);
-- data_in(14) and data(13) are used directly in the reg_if
-- state machine
--return_status_address_valid <= data_in(14);
-- return_status_data_valid <= data_in(13);
record_pcm_left_valid <= data_in(12);
record_pcm_right_valid <= data_in(11);
end if;
end if;
end process;
PCM_Record_Left_Valid <= record_pcm_left_valid and last_frame_cycle;
PCM_Record_Right_Valid <= record_pcm_right_valid and last_frame_cycle;
codec_rdy <= codec_rdy_i;
-----------------------------------------------------------------------------
-- Get slot 1 PCM request bit
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
if (slot_end = '1' and slot_No = 1 ) then
accept_pcm_left <= not data_in(11);
accept_pcm_right <= not data_in(10);
end if;
end if;
end process;
PCM_Playback_Left_Accept <= accept_pcm_left and last_frame_cycle;
PCM_Playback_Right_Accept <= accept_pcm_right and last_frame_cycle;
-----------------------------------------------------------------------------
-- Get slot 3 and 4 data
-----------------------------------------------------------------------------
Get_Record_Data : process (AC97_Bit_Clk) is
-- synthesis translate_off
variable my_line : LINE;
-- synthesis translate_on
begin -- process Get_Record_Data
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_end = '1' and slot_No = 3 ) then
PCM_Record_Left_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Left Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Left_i) ));
writeline(output, my_line);
-- synthesis translate_on
elsif (slot_end = '1' and slot_No = 4 ) then
PCM_Record_Right_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Right Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Right_i) ));
writeline(output, my_line);
-- synthesis translate_on
end if;
end if;
end process Get_Record_Data;
PCM_Record_Left <= PCM_Record_Left_i;
PCM_Record_Right <= PCM_Record_Right_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
|
gpl-3.0
|
20a367339b919390b440be325c95d9e1
| 0.480076 | 4.180353 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_const_record.vhd
| 3 | 2,871 |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for accessing constant records & arrays of records in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vhdl_const_record is
port(sel : in integer range 0 to 3;
hex : out std_logic_vector(7 downto 0);
aval : out std_logic_vector(7 downto 0));
end entity vhdl_const_record;
architecture test of vhdl_const_record is
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_4, var_5, var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
type t_var_record is record
var : t_var; -- 32 bits
a : t_byte_array (3 downto 0); -- 4*8 bits
hexvalue : std_logic_vector (7 downto 0); -- 8 bits
end record; -- total 72 bits
type t_var_array is array (natural range <>) of t_var_record;
constant c_vars_array : t_var_array(0 to 3) := (
0 => (var => var_presence,
hexvalue => x"14",
a => (0 => x"aa", 1 => x"ab", 2 => x"ac", 3 => x"ad")),
1 => (var => var_identif,
hexvalue => x"24",
a => (0 => x"ba", 1 => x"bb", 2 => x"bc", 3 => x"bd")),
2 => (var => var_1,
hexvalue => x"34",
a => (0 => x"ca", 1 => x"cb", 2 => x"cc", 3 => x"cd")),
3 => (var => var_2,
hexvalue => x"56",
a => (0 => x"da", 1 => x"db", 2 => x"dc", 3 => x"dd"))
);
constant c_record : t_var_record := (
var => var_4,
hexvalue => x"66",
a => (0 => x"00", 1 => x"11", 2 => x"22", 3 => x"33")
);
signal sig : std_logic_vector(7 downto 0);
signal sig2 : std_logic_vector(7 downto 0);
begin
sig <= c_record.hexvalue;
process(sel)
begin
sig2 <= c_record.a(sel);
hex <= c_vars_array(sel).hexvalue;
aval <= c_vars_array(sel).a(sel);
end process;
end architecture test;
|
gpl-2.0
|
2d4072b22414a6d9e70dbfc70f6bbcdf
| 0.557297 | 3.401659 | false | false | false | false |
luebbers/reconos
|
core/pcores/burst_ram_v2_01_a/hdl/vhdl/ram_single.vhd
| 1 | 11,415 |
--
-- \file ram_single.vhd
--
-- Single-Port parametrizable local RAM block
--
-- Port A is thread-side, port b is osif-side.
--
-- Possible combinations of generics:
--
-- G_PORTA_DWIDTH = 32 (fixed)
-- G_PORTB_DWIDTH = 64 (fixed)
--
-- G_PORTA_AWIDTH | G_PORTB_AWIDTH | size
-- ----------------+----------------+-----
-- 10 | 9 | 4kB
-- 11 | 10 | 8kB
-- 12 | 11 | 16kB
-- 13 | 12 | 32kB
-- 14 | 13 | 64kB
--
-- To enable the use of byte enable signals from Port B, symmetric BRAM
-- blocks must be used, which are then multiplexed on the read port of
-- Port A to realize the lower data bus width:
--
-- _____ ____
-- _______| |________ sel | |
-- | 8 |_____| 8 | ------| FF |<--- addra(0)
-- | | | |____|
-- | ... |------- |
-- | _____ | 32 | |
-- |_______| |________| | |\
-- | 8 |_____| 8 | | \
-- 64 | ---|0|
-- -------| | |-------------> douta
-- | _____ ---|1|
-- |_______| |________ | | /
-- | 8 |_____| 8 | | |/
-- | | |
-- | ... |-------
-- | _____ | 32
-- |_______| |________|
-- 8 |_____| 8
--
-- Note that the sel signal for the read multiplexer must be delayed to match
-- the read delay of the synchronous BRAMs.
--
-- \author Enno Luebbers <[email protected]>
-- \date 11.05.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library reconos_v1_02_a;
--use reconos_v1_02_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ram_single is
generic (
-- address and data widths, THREAD-side and OSIF-side
G_PORTA_AWIDTH : integer := 10;
G_PORTA_DWIDTH : integer := 32; -- this is fixed!
G_PORTB_AWIDTH : integer := 10;
G_PORTB_DWIDTH : integer := 64; -- this is fixed!
G_PORTB_USE_BE : integer := 0 -- use BEs on port B
);
port (
-- A is thread-side, AX is secondary thread-side, B is OSIF-side
addra : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
addrb : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
clka : in std_logic;
clkb : in std_logic;
dina : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0); -- these widths are fixed
dinb : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
douta : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
doutb : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
wea : in std_logic;
web : in std_logic;
ena : in std_logic;
enb : in std_logic;
beb : in std_logic_vector(G_PORTB_DWIDTH/8-1 downto 0)
);
end ram_single;
architecture Behavioral of ram_single is
--== DERIVED CONSTANTS ==--
-- RAM size derived from Port A
constant C_PORTA_SIZE_BYTES : natural := 2**G_PORTA_AWIDTH * (G_PORTA_DWIDTH/8);
-- RAM size derived from Port B
constant C_PORTB_SIZE_BYTES : natural := 2**G_PORTB_AWIDTH * (G_PORTB_DWIDTH/8);
constant C_RAM_SIZE_KB : natural := C_PORTA_SIZE_BYTES / 1024;
-- number of BRAM blocks
constant C_NUM_BRAMS : natural := C_RAM_SIZE_KB / 2;
-- thread-side data width of a single BRAM block
constant C_PORTA_BRAM_DWIDTH : natural := G_PORTA_DWIDTH / C_NUM_BRAMS;
constant C_PORTB_BRAM_DWIDTH : natural := G_PORTB_DWIDTH / C_NUM_BRAMS;
-- ratio of data widths
constant C_BRAM_DWIDTH_RATIO : natural := C_PORTB_BRAM_DWIDTH / C_PORTA_BRAM_DWIDTH; -- always 2
-- BRAM wrapper component
component bram_wrapper is
generic (
G_PORTA_DWIDTH : natural := 8;
G_PORTB_DWIDTH : natural := 16;
G_PORTA_AWIDTH : natural := 11;
G_PORTB_AWIDTH : natural := 10
);
port (
DOA : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
DOB : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
ADDRA : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
ADDRB : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
DIB : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic;
WEB : in std_logic
);
end component;
subtype bram_vec_array_t is std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
-- helper signals for BRAM connection
signal dina_tmp : bram_vec_array_t;
signal douta_tmp : bram_vec_array_t;
signal ena_tmp : std_logic_vector(C_NUM_BRAMS-1 downto 0);
signal wea_tmp : std_logic_vector(C_NUM_BRAMS-1 downto 0);
signal enb_tmp : std_logic_vector(C_NUM_BRAMS-1 downto 0);
signal web_tmp : std_logic_vector(C_NUM_BRAMS-1 downto 0);
signal sel : std_logic; -- selector for PORTA BRAM multiplexer
begin
-- check generics for feasibility
assert G_PORTA_DWIDTH = 32
report "thread-side (PORTA) data width must be 32"
severity failure;
assert G_PORTB_DWIDTH = 64
report "OSIF-side (PORTB) data width must be 64"
severity failure;
-- this will not catch two-port/14 bit, which is not supported)
assert (G_PORTA_AWIDTH >= 10) and (G_PORTA_AWIDTH <= 14)
report "PORTA must have address width between 10 and 14 bits"
severity failure;
-- this will not catch two-port/9 bit, which is not supported)
assert (G_PORTB_AWIDTH >= 9) and (G_PORTA_AWIDTH <= 13)
report "PORTB must have address width between 9 and 13 bits"
severity failure;
assert (G_PORTB_AWIDTH = G_PORTA_AWIDTH-1)
report "PORTB must have an address width one greater than that of PORTA"
severity failure;
assert C_PORTA_SIZE_BYTES = C_PORTB_SIZE_BYTES
report "combination of data and address widths impossible"
severity failure;
assert (G_PORTB_USE_BE = 0) or (C_PORTB_BRAM_DWIDTH <= 8)
report "port B byte enables cannot be used with this memory size"
severity failure;
-- generate enable signals from byte enables for PORTB
WITH_BE: if G_PORTB_USE_BE /= 0 generate
PORTB: for i in C_NUM_BRAMS-1 downto 0 generate
enb_tmp(i) <= beb(i/(8/C_PORTB_BRAM_DWIDTH)) and ENB;
web_tmp(i) <= beb(i/(8/C_PORTB_BRAM_DWIDTH)) and WEB;
end generate;
end generate;
WITHOUT_BE: if G_PORTB_USE_BE = 0 generate
PORTB: for i in C_NUM_BRAMS-1 downto 0 generate
enb_tmp(i) <= ENB;
web_tmp(i) <= WEB;
end generate;
end generate;
-- generate enable/write enable signals for PORTA
TOP_HALF : for i in C_NUM_BRAMS-1 downto C_NUM_BRAMS/2 generate
ena_tmp(i) <= ENA and addra(0);
wea_tmp(i) <= WEA and addra(0);
end generate;
BOTTOM_HALF : for i in (C_NUM_BRAMS/2)-1 downto 0 generate
ena_tmp(i) <= ENA and not addra(0);
wea_tmp(i) <= WEA and not addra(0);
end generate;
-- delay multiplexer select signal for one cycle to match BRAM delay
sel_delay_proc: process(clka)
begin
if rising_edge(clka) then
sel <= addra(0);
end if;
end process;
-- multiplex PORTA RAM output
douta <= douta_tmp((G_PORTA_DWIDTH*2)-1 downto G_PORTA_DWIDTH) when sel = '1' else
douta_tmp( G_PORTA_DWIDTH -1 downto 0);
dina_tmp((G_PORTA_DWIDTH*2)-1 downto G_PORTA_DWIDTH) <= dina;
dina_tmp( G_PORTA_DWIDTH -1 downto 0) <= dina;
-- instantiate RAMs
rams: for i in C_NUM_BRAMS-1 downto 0 generate
bram_inst : bram_wrapper
generic map (
G_PORTA_DWIDTH => C_PORTB_BRAM_DWIDTH,
G_PORTA_AWIDTH => G_PORTB_AWIDTH,
G_PORTB_DWIDTH => C_PORTB_BRAM_DWIDTH,
G_PORTB_AWIDTH => G_PORTB_AWIDTH
)
port map (
DOA => douta_tmp((i+1)*C_PORTB_BRAM_DWIDTH-1 downto i*C_PORTB_BRAM_DWIDTH),
-- douta((i+1)*C_PORTA_BRAM_DWIDTH-1 downto i*C_PORTA_BRAM_DWIDTH),
DOB => doutb((i+1)*C_PORTB_BRAM_DWIDTH-1 downto i*C_PORTB_BRAM_DWIDTH),
ADDRA => addra(G_PORTA_AWIDTH-1 downto 1),
ADDRB => addrb,
CLKA => clka,
CLKB => clkb,
DIA => dina_tmp((i+1)*C_PORTB_BRAM_DWIDTH-1 downto i*C_PORTB_BRAM_DWIDTH),
-- dina((i+1)*C_PORTA_BRAM_DWIDTH-1 downto i*C_PORTA_BRAM_DWIDTH),
DIB => dinb((i+1)*C_PORTB_BRAM_DWIDTH-1 downto i*C_PORTB_BRAM_DWIDTH),
ENA => ena_tmp(i),
ENB => enb_tmp(i),
SSRA => '0',
SSRB => '0',
WEA => wea_tmp(i),
WEB => web_tmp(i)
);
end generate; -- rams
end Behavioral;
|
gpl-3.0
|
84f610cd30eafb07e54743b4733e050f
| 0.496715 | 3.937565 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S144_S144.vhd
| 1 | 6,438 |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S144_S144.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (128 and 128) --
-- made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S144_S144 is
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (127 downto 0);
DIPA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (127 downto 0);
DOPA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end entity BRAM_S144_S144;
architecture BRAM_S144_S144_arch of BRAM_S144_S144 is
component BRAM_S72_S72
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
END component;
signal doa1 : std_logic_vector (63 downto 0);
signal dob1 : std_logic_vector (63 downto 0);
signal doa2 : std_logic_vector (63 downto 0);
signal dob2 : std_logic_vector (63 downto 0);
signal dia1 : std_logic_vector (63 downto 0);
signal dib1 : std_logic_vector (63 downto 0);
signal dia2 : std_logic_vector (63 downto 0);
signal dib2 : std_logic_vector (63 downto 0);
signal dipa1: std_logic_vector(7 downto 0);
signal dipa2: std_logic_vector(7 downto 0);
signal dipb1: std_logic_vector(7 downto 0);
signal dipb2: std_logic_vector(7 downto 0);
signal dopa1: std_logic_vector(7 downto 0);
signal dopa2: std_logic_vector(7 downto 0);
signal dopb1: std_logic_vector(7 downto 0);
signal dopb2: std_logic_vector(7 downto 0);
begin
dia1(31 downto 0) <= DIA(31 downto 0);
dia2(31 downto 0) <= DIA(63 downto 32);
dia1(63 downto 32) <= DIA(95 downto 64);
dia2(63 downto 32) <= DIA(127 downto 96);
dib1 <= DIB(63 downto 0);
dib2 <= DIB(127 downto 64);
DOA(63 downto 0) <= doa1;
DOA(127 downto 64) <= doa2;
DOB(63 downto 0) <= dob1;
DOB(127 downto 64) <= dob2;
dipa1 <= dipa(7 downto 0);
dipa2 <= dipa(15 downto 8);
dopa(7 downto 0) <= dopa1;
dopa(15 downto 8) <= dopa2;
dipb1 <= dipb(7 downto 0);
dipb2 <= dipb(15 downto 8);
dopb(7 downto 0) <= dopb1;
dopb(15 downto 8) <= dopb2;
bram1: BRAM_S72_S72
port map (
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: BRAM_S72_S72
port map (
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S144_S144_arch;
|
gpl-3.0
|
307e3da97c94cc066018d3da3edf0570
| 0.427617 | 4.292 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/physical/v6_gtxwizard_gtx.vhd
| 1 | 35,802 |
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.5
-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
-- / / Filename : v6_gtxwizard_gtx.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module V6_GTXWIZARD_GTX (a GTX Wrapper)
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity V6_GTXWIZARD_GTX is
generic
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE : string := "TXPLL";
-- Save power parameter
GTX_POWER_SAVE : bit_vector := "0000010000"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
RXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA_OUT : out std_logic;
RXCHARISK_OUT : out std_logic;
RXDISPERR_OUT : out std_logic;
RXNOTINTABLE_OUT : out std_logic;
RXRUNDISP_OUT : out std_logic;
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN_IN : in std_logic;
RXENPCOMMAALIGN_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT : out std_logic_vector(7 downto 0);
RXRECCLK_OUT : out std_logic;
RXRESET_IN : in std_logic;
RXUSRCLK2_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXELECIDLE_OUT : out std_logic;
RXN_IN : in std_logic;
RXP_IN : in std_logic;
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET_IN : in std_logic;
RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN : in std_logic;
MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
PLLRXRESET_IN : in std_logic;
RXPLLLKDET_OUT : out std_logic;
RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARDISPMODE_IN : in std_logic;
TXCHARDISPVAL_IN : in std_logic;
TXCHARISK_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(7 downto 0);
TXOUTCLK_OUT : out std_logic;
TXRESET_IN : in std_logic;
TXUSRCLK2_IN : in std_logic;
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN : in std_logic;
MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
PLLTXRESET_IN : in std_logic;
TXPLLLKDET_OUT : out std_logic;
TXRESETDONE_OUT : out std_logic
);
end V6_GTXWIZARD_GTX;
architecture RTL of V6_GTXWIZARD_GTX is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
-- RX Datapath signals
signal rxdata_i : std_logic_vector(31 downto 0);
signal rxchariscomma_float_i : std_logic_vector(2 downto 0);
signal rxcharisk_float_i : std_logic_vector(2 downto 0);
signal rxdisperr_float_i : std_logic_vector(2 downto 0);
signal rxnotintable_float_i : std_logic_vector(2 downto 0);
signal rxrundisp_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata_i : std_logic_vector(31 downto 0);
signal txkerr_float_i : std_logic_vector(2 downto 0);
signal txrundisp_float_i : std_logic_vector(2 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
------------------- GTX Datapath byte mapping -----------------
RXDATA_OUT <= rxdata_i(7 downto 0);
txdata_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA_IN);
----------------------------- GTX Instance --------------------------
gtxe1_i :GTXE1
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_GTXRESET_SPEEDUP => (GTX_SIM_GTXRESET_SPEEDUP),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_TXREFCLK_SOURCE => ("000"),
SIM_RXREFCLK_SOURCE => ("000"),
----------------------------TX PLL----------------------------
TX_CLK_SOURCE => (GTX_TX_CLK_SOURCE),
TX_OVERSAMPLE_MODE => (FALSE),
TXPLL_COM_CFG => (x"21680a"),
TXPLL_CP_CFG => (x"0D"),
TXPLL_DIVSEL_FB => (2),
TXPLL_DIVSEL_OUT => (2),
TXPLL_DIVSEL_REF => (1),
TXPLL_DIVSEL45_FB => (5),
TXPLL_LKDET_CFG => ("111"),
TX_CLK25_DIVIDER => (5),
TXPLL_SATA => ("00"),
TX_TDCC_CFG => ("00"),
PMA_CAS_CLK_EN => (FALSE),
POWER_SAVE => (GTX_POWER_SAVE),
-------------------------TX Interface-------------------------
GEN_TXUSRCLK => (TRUE),
TX_DATA_WIDTH => (10),
TX_USRCLK_CFG => (x"00"),
TXOUTCLK_CTRL => ("TXPLLREFCLK_DIV1"),
TXOUTCLK_DLY => ("0000000000"),
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT => ('0'),
PMA_TX_CFG => (x"80082"),
TX_BUFFER_USE => (TRUE),
TX_BYTECLK_CFG => (x"00"),
TX_EN_RATE_RESET_BUF => (TRUE),
TX_XCLK_SEL => ("TXOUT"),
TX_DLYALIGN_CTRINC => ("0100"),
TX_DLYALIGN_LPFINC => ("0110"),
TX_DLYALIGN_MONSEL => ("000"),
TX_DLYALIGN_OVRDSETTING => ("10000000"),
-------------------------TX Gearbox---------------------------
GEARBOX_ENDEC => ("000"),
TXGEARBOX_USE => (FALSE),
----------------TX Driver and OOB Signalling------------------
TX_DRIVE_MODE => ("DIRECT"),
TX_IDLE_ASSERT_DELAY => ("101"),
TX_IDLE_DEASSERT_DELAY => ("011"),
TXDRIVE_LOOPBACK_HIZ => (FALSE),
TXDRIVE_LOOPBACK_PD => (FALSE),
--------------TX Pipe Control for PCI Express/SATA------------
COM_BURST_VAL => ("1111"),
------------------TX Attributes for PCI Express---------------
TX_DEEMPH_0 => ("11010"),
TX_DEEMPH_1 => ("10000"),
TX_MARGIN_FULL_0 => ("1001110"),
TX_MARGIN_FULL_1 => ("1001001"),
TX_MARGIN_FULL_2 => ("1000101"),
TX_MARGIN_FULL_3 => ("1000010"),
TX_MARGIN_FULL_4 => ("1000000"),
TX_MARGIN_LOW_0 => ("1000110"),
TX_MARGIN_LOW_1 => ("1000100"),
TX_MARGIN_LOW_2 => ("1000010"),
TX_MARGIN_LOW_3 => ("1000000"),
TX_MARGIN_LOW_4 => ("1000000"),
----------------------------RX PLL----------------------------
RX_OVERSAMPLE_MODE => (FALSE),
RXPLL_COM_CFG => (x"21680a"),
RXPLL_CP_CFG => (x"0D"),
RXPLL_DIVSEL_FB => (2),
RXPLL_DIVSEL_OUT => (2),
RXPLL_DIVSEL_REF => (1),
RXPLL_DIVSEL45_FB => (5),
RXPLL_LKDET_CFG => ("111"),
RX_CLK25_DIVIDER => (5),
-------------------------RX Interface-------------------------
GEN_RXUSRCLK => (TRUE),
RX_DATA_WIDTH => (10),
RXRECCLK_CTRL => ("RXRECCLKPMA_DIV1"),
RXRECCLK_DLY => ("0000000000"),
RXUSRCLK_DLY => (x"0000"),
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS => (TRUE),
CDR_PH_ADJ_TIME => ("10100"),
OOBDETECT_THRESHOLD => ("011"),
PMA_CDR_SCAN => (x"640404C"),
PMA_RX_CFG => (x"05ce048"),
RCV_TERM_GND => (FALSE),
RCV_TERM_VTTRX => (FALSE),
RX_EN_IDLE_HOLD_CDR => (FALSE),
RX_EN_IDLE_RESET_FR => (TRUE),
RX_EN_IDLE_RESET_PH => (TRUE),
TX_DETECT_RX_CFG => (x"1832"),
TERMINATION_CTRL => ("00000"),
TERMINATION_OVRD => (FALSE),
CM_TRIM => ("01"),
PMA_RXSYNC_CFG => (x"00"),
PMA_CFG => (x"0040000040000000003"),
BGTEST_CFG => ("00"),
BIAS_CFG => (x"00000"),
--------------RX Decision Feedback Equalizer(DFE)-------------
DFE_CAL_TIME => ("01100"),
DFE_CFG => ("00011011"),
RX_EN_IDLE_HOLD_DFE => (TRUE),
RX_EYE_OFFSET => (x"4C"),
RX_EYE_SCANMODE => ("00"),
-------------------------PRBS Detection-----------------------
RXPRBSERR_LOOPBACK => ('0'),
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD => (1),
COMMA_10B_ENABLE => ("0001111111"),
COMMA_DOUBLE => (FALSE),
DEC_MCOMMA_DETECT => (TRUE),
DEC_PCOMMA_DETECT => (TRUE),
DEC_VALID_COMMA_ONLY => (FALSE),
MCOMMA_10B_VALUE => ("1010000011"),
MCOMMA_DETECT => (TRUE),
PCOMMA_10B_VALUE => ("0101111100"),
PCOMMA_DETECT => (TRUE),
RX_DECODE_SEQ_MATCH => (TRUE),
RX_SLIDE_AUTO_WAIT => (5),
RX_SLIDE_MODE => ("OFF"),
SHOW_REALIGN_COMMA => (FALSE),
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR => (1),
RX_LOS_THRESHOLD => (4),
RX_LOSS_OF_SYNC_FSM => (FALSE),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE => (FALSE),
-------------RX Elastic Buffer and Phase alignment------------
RX_BUFFER_USE => (TRUE),
RX_EN_IDLE_RESET_BUF => (TRUE),
RX_EN_MODE_RESET_BUF => (TRUE),
RX_EN_RATE_RESET_BUF => (TRUE),
RX_EN_REALIGN_RESET_BUF => (FALSE),
RX_EN_REALIGN_RESET_BUF2 => (FALSE),
RX_FIFO_ADDR_MODE => ("FULL"),
RX_IDLE_HI_CNT => ("1000"),
RX_IDLE_LO_CNT => ("0000"),
RX_XCLK_SEL => ("RXREC"),
RX_DLYALIGN_CTRINC => ("0100"),
RX_DLYALIGN_EDGESET => ("00010"),
RX_DLYALIGN_LPFINC => ("0110"),
RX_DLYALIGN_MONSEL => ("000"),
RX_DLYALIGN_OVRDSETTING => ("10000000"),
------------------------Clock Correction----------------------
CLK_COR_ADJ_LEN => (2),
CLK_COR_DET_LEN => (2),
CLK_COR_INSERT_IDLE_FLAG => (FALSE),
CLK_COR_KEEP_IDLE => (FALSE),
CLK_COR_MAX_LAT => (18),
CLK_COR_MIN_LAT => (14),
CLK_COR_PRECEDENCE => (TRUE),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_1_1 => ("0110111100"),
CLK_COR_SEQ_1_2 => ("0001010000"),
CLK_COR_SEQ_1_3 => ("0000000000"),
CLK_COR_SEQ_1_4 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0110111100"),
CLK_COR_SEQ_2_2 => ("0010110101"),
CLK_COR_SEQ_2_3 => ("0000000000"),
CLK_COR_SEQ_2_4 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_USE => (TRUE),
CLK_CORRECT_USE => (TRUE),
------------------------Channel Bonding----------------------
CHAN_BOND_1_MAX_SKEW => (1),
CHAN_BOND_2_MAX_SKEW => (1),
CHAN_BOND_KEEP_ALIGN => (FALSE),
CHAN_BOND_SEQ_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2 => ("0000000000"),
CHAN_BOND_SEQ_1_3 => ("0000000000"),
CHAN_BOND_SEQ_1_4 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2 => ("0000000000"),
CHAN_BOND_SEQ_2_3 => ("0000000000"),
CHAN_BOND_SEQ_2_4 => ("0000000000"),
CHAN_BOND_SEQ_2_CFG => ("00000"),
CHAN_BOND_SEQ_2_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_USE => (FALSE),
CHAN_BOND_SEQ_LEN => (1),
PCI_EXPRESS_MODE => (FALSE),
-------------RX Attributes for PCI Express/SATA/SAS----------
SAS_MAX_COMSAS => (52),
SAS_MIN_COMSAS => (40),
SATA_BURST_VAL => ("100"),
SATA_IDLE_VAL => ("100"),
SATA_MAX_BURST => (9),
SATA_MAX_INIT => (27),
SATA_MAX_WAKE => (9),
SATA_MIN_BURST => (5),
SATA_MIN_INIT => (15),
SATA_MIN_WAKE => (5),
TRANS_TIME_FROM_P2 => (x"03c"),
TRANS_TIME_NON_P2 => (x"19"),
TRANS_TIME_RATE => (x"ff"),
TRANS_TIME_TO_P2 => (x"064")
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK => LOOPBACK_IN,
RXPOWERDOWN => RXPOWERDOWN_IN,
TXPOWERDOWN => TXPOWERDOWN_IN,
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID => open,
RXGEARBOXSLIP => tied_to_ground_i,
RXHEADER => open,
RXHEADERVALID => open,
RXSTARTOFSEQ => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA(3 downto 1) => rxchariscomma_float_i,
RXCHARISCOMMA(0) => RXCHARISCOMMA_OUT,
RXCHARISK(3 downto 1) => rxcharisk_float_i,
RXCHARISK(0) => RXCHARISK_OUT,
RXDEC8B10BUSE => tied_to_vcc_i,
RXDISPERR(3 downto 1) => rxdisperr_float_i,
RXDISPERR(0) => RXDISPERR_OUT,
RXNOTINTABLE(3 downto 1) => rxnotintable_float_i,
RXNOTINTABLE(0) => RXNOTINTABLE_OUT,
RXRUNDISP(3 downto 1) => rxrundisp_float_i,
RXRUNDISP(0) => RXRUNDISP_OUT,
USRCODEERR => tied_to_ground_i,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ => open,
RXCHBONDI => tied_to_ground_vec_i(3 downto 0),
RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE => tied_to_ground_i,
RXENCHANSYNC => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => RXCLKCORCNT_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED => open,
RXBYTEREALIGN => open,
RXCOMMADET => open,
RXCOMMADETUSE => tied_to_vcc_i,
RXENMCOMMAALIGN => RXENMCOMMAALIGN_IN,
RXENPCOMMAALIGN => RXENPCOMMAALIGN_IN,
RXSLIDE => tied_to_ground_i,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET => tied_to_ground_i,
RXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA => rxdata_i,
RXRECCLK => RXRECCLK_OUT,
RXRECCLKPCS => open,
RXRESET => RXRESET_IN,
RXUSRCLK => tied_to_ground_i,
RXUSRCLK2 => RXUSRCLK2_IN,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJMON => open,
DFEDLYOVRD => tied_to_vcc_i,
DFEEYEDACMON => open,
DFESENSCAL => open,
DFETAP1 => tied_to_ground_vec_i(4 downto 0),
DFETAP1MONITOR => open,
DFETAP2 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR => open,
DFETAP3 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR => open,
DFETAP4 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR => open,
DFETAPOVRD => tied_to_vcc_i,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE => tied_to_ground_i,
IGNORESIGDET => tied_to_ground_i,
RXCDRRESET => tied_to_ground_i,
RXELECIDLE => RXELECIDLE_OUT,
RXEQMIX => "0000000111",
RXN => RXN_IN,
RXP => RXP_IN,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET => RXBUFRESET_IN,
RXBUFSTATUS => RXBUFSTATUS_OUT,
RXCHANISALIGNED => open,
RXCHANREALIGN => open,
RXDLYALIGNDISABLE => tied_to_ground_i,
RXDLYALIGNMONENB => tied_to_ground_i,
RXDLYALIGNMONITOR => open,
RXDLYALIGNOVERRIDE => tied_to_ground_i,
RXDLYALIGNRESET => tied_to_ground_i,
RXDLYALIGNSWPPRECURB => tied_to_vcc_i,
RXDLYALIGNUPDSW => tied_to_ground_i,
RXENPMAPHASEALIGN => tied_to_ground_i,
RXPMASETPHASE => tied_to_ground_i,
RXSTATUS => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN => tied_to_ground_i,
RXOVERSAMPLEERR => open,
------------------------ Receive Ports - RX PLL Ports ----------------------
GREFCLKRX => tied_to_ground_i,
GTXRXRESET => GTXRXRESET_IN,
MGTREFCLKRX => MGTREFCLKRX_IN,
NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
PERFCLKRX => tied_to_ground_i,
PLLRXRESET => PLLRXRESET_IN,
RXPLLLKDET => RXPLLLKDET_OUT,
RXPLLLKDETEN => tied_to_vcc_i,
RXPLLPOWERDOWN => tied_to_ground_i,
RXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
RXRATE => tied_to_ground_vec_i(1 downto 0),
RXRATEDONE => open,
RXRESETDONE => RXRESETDONE_OUT,
SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS => open,
RXVALID => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => tied_to_ground_i,
--------------------- Receive Ports - RX Ports for SATA --------------------
COMINITDET => open,
COMSASDET => open,
COMWAKEDET => open,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPMODE(0) => TXCHARDISPMODE_IN,
TXCHARDISPVAL(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPVAL(0) => TXCHARDISPVAL_IN,
TXCHARISK(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK(0) => TXCHARISK_IN,
TXENC8B10BUSE => tied_to_vcc_i,
TXKERR => open,
TXRUNDISP => open,
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST => "1000000000000",
MGTREFCLKFAB => open,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN => "11111111111111111111",
TSTOUT => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA => txdata_i,
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKPCS => open,
TXRESET => TXRESET_IN,
TXUSRCLK => tied_to_ground_i,
TXUSRCLK2 => TXUSRCLK2_IN,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXBUFDIFFCTRL => "100",
TXDIFFCTRL => "0000",
TXINHIBIT => tied_to_ground_i,
TXN => TXN_OUT,
TXP => TXP_OUT,
TXPOSTEMPHASIS => "00000",
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXPREEMPHASIS => "0000",
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS => TXBUFSTATUS_OUT,
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE => tied_to_vcc_i,
TXDLYALIGNMONENB => tied_to_ground_i,
TXDLYALIGNMONITOR => open,
TXDLYALIGNOVERRIDE => tied_to_ground_i,
TXDLYALIGNRESET => tied_to_ground_i,
TXDLYALIGNUPDSW => tied_to_vcc_i,
TXENPMAPHASEALIGN => tied_to_ground_i,
TXPMASETPHASE => tied_to_ground_i,
----------------------- Transmit Ports - TX PLL Ports ----------------------
GREFCLKTX => tied_to_ground_i,
GTXTXRESET => GTXTXRESET_IN,
MGTREFCLKTX => MGTREFCLKTX_IN,
NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
PERFCLKTX => tied_to_ground_i,
PLLTXRESET => PLLTXRESET_IN,
SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
TXPLLLKDET => TXPLLLKDET_OUT,
TXPLLLKDETEN => tied_to_vcc_i,
TXPLLPOWERDOWN => tied_to_ground_i,
TXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
TXRATE => tied_to_ground_vec_i(1 downto 0),
TXRATEDONE => open,
TXRESETDONE => TXRESETDONE_OUT,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDEEMPH => tied_to_ground_i,
TXDETECTRX => tied_to_ground_i,
TXELECIDLE => tied_to_ground_i,
TXMARGIN => tied_to_ground_vec_i(2 downto 0),
TXPDOWNASYNCH => tied_to_ground_i,
TXSWING => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
COMFINISH => open,
TXCOMINIT => tied_to_ground_i,
TXCOMSAS => tied_to_ground_i,
TXCOMWAKE => tied_to_ground_i
);
end RTL;
|
gpl-3.0
|
ee024d29c9f009e19578a15ccfe68007
| 0.369951 | 5.063216 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/thermal_monitor_v1_03_a/hdl/vhdl/inv_comp.vhd
| 1 | 1,335 |
----------------------------------------------------------------------------------
-- Company: University of Paderborn
-- Engineer: Markus Happe
--
-- Create Date: 16:04:47 02/09/2011
-- Design Name:
-- Module Name: inv_comp - Behavioral
-- Module Name: delay_comp - Behavioral
-- Project Name: Thermal Sensor Net
-- Target Devices: Virtex 6 ML605
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity inv_comp is
port ( rst : in std_logic;
x_in : in std_logic;
x_out : out std_logic);
end inv_comp;
architecture Behavioral of inv_comp is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
signal x : std_logic;
attribute KEEP : string;
attribute KEEP of x : signal is "true";
attribute INIT : string;
attribute INIT of invert_lut : label is "B";
begin
x_out <= x;
invert_lut: LUT2
--synthesies translate_off
generic map (INIT => X"B")
--synthesies translate_on
port map( I0 => rst,
I1 => x_in,
O => x
);
end Behavioral;
|
gpl-3.0
|
9f491236f4c64eb1420e19a4428f8296
| 0.553558 | 3.869565 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.ip_user_files/ipstatic/axi_uartlite_v2_0_10/hdl/src/vhdl/uartlite_tx.vhd
| 1 | 22,881 |
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0_2;
-- dynshreg_i_f refered from proc_common_v4_0_20_a
library axi_uartlite_v2_0_10;
-- uartlite_core refered from axi_uartlite_v2_0_10
use axi_uartlite_v2_0_10.all;
-- srl_fifo_f refered from proc_common_v4_0_20_a
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0_10.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
|
mit
|
2819bf5025a08c116db44bba3c0384b3
| 0.401687 | 4.867262 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/opb_ac97.vhd
| 4 | 10,264 |
-------------------------------------------------------------------------------
-- $Id: opb_ac97.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------------------------------
-- opb_ac97.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ac97
--
-- Description: Provides an OPB interface to the ac97 fifo controller
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_fifo
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity opb_ac97 is
generic (
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_8000";
C_HIGHADDR : std_logic_vector := X"FFFF_80FF";
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
-- C_GPOUT_DWIDTH : integer := 1;
-- value of 0,1,2,3,4
-- 0 = No Interrupt
-- 1 = empty
-- 2 = halfempty
-- 3 = halffull
-- 4 = full
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
-- GPIO signals (Beep, reset, etc.)
-- AC97_GPOUT : out std_logic_vector(0 to C_GPOUT_DWIDTH-1);
-- Interrupt signals
Interrupt : out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_BASEADDR : constant is "0x100";
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_ac97;
-- library proc_common_v1_00_b;
-- use proc_common_v1_00_b.proc_common_pkg.all;
-- library ipif_common_v1_00_c;
-- use ipif_common_v1_00_c.ipif_pkg.all;
-- library opb_ipif_v3_00_a;
-- use opb_ipif_v3_00_a.all;
library Common_v1_00_a;
use Common_v1_00_a.pselect;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
library unisim;
use unisim.all;
architecture IMP of opb_ac97 is
component ac97_fifo is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLAYBACK : integer := 1;
C_RECORD : integer := 0;
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
-- IP Interface
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Interrupt: out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
end component ac97_fifo;
component FDR is
port (Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component pselect is
generic (
C_AB : integer;
C_AW : integer;
C_BAR : std_logic_vector);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
ps : out std_logic);
end component pselect;
function Addr_Bits (x, y : std_logic_vector(0 to C_OPB_AWIDTH-1)) return integer is
variable addr_nor : std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_OPB_AWIDTH-1 loop
if addr_nor(i) = '1' then return i;
end if;
end loop;
return(C_OPB_AWIDTH);
end function Addr_Bits;
constant C_AB : integer := Addr_Bits(C_HIGHADDR, C_BASEADDR);
signal ac97_CS : std_logic;
signal ac97_CS_1 : std_logic; -- Active as long as AC97_CS is active
signal ac97_CS_2 : std_logic; -- Active only 1 clock cycle during an
signal ac97_CS_3 : std_logic; -- Active only 1 clock cycle during an
signal xfer_Ack : std_logic;
signal opb_RNW_1 : std_logic;
signal opb_rdce : std_logic;
signal opb_wrce : std_logic;
signal iSln_DBus : std_logic_vector(0 to 31);
signal interrupt_i : std_logic;
begin
Interrupt <= interrupt_i;
-- Do the OPB address decoding
pselect_I : pselect
generic map (
C_AB => C_AB, -- [integer]
C_AW => C_OPB_AWIDTH, -- [integer]
C_BAR => C_BASEADDR) -- [std_logic_vector]
port map (
A => OPB_ABus, -- [in std_logic_vector(0 to C_AW-1)]
AValid => OPB_select, -- [in std_logic]
ps => ac97_CS); -- [out std_logic]
ac97_CS_1_DFF : FDR
port map (
Q => ac97_CS_1, -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
D => ac97_CS, -- [in std_logic]
R => xfer_Ack); -- [in std_logic]
ac97_CS_2_DFF: process (OPB_Clk, OPB_Rst) is
begin -- process uart_CS_2_DFF
if OPB_Rst = '1' then -- asynchronous reset (active high)
ac97_CS_2 <= '0';
ac97_CS_3 <= '0';
opb_RNW_1 <= '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
ac97_CS_2 <= ac97_CS_1 and not ac97_CS_2 and not ac97_CS_3;
ac97_CS_3 <= ac97_CS_2;
opb_RNW_1 <= OPB_RNW;
end if;
end process ac97_CS_2_DFF;
opb_rdce <= ac97_CS_2 and OPB_RNW_1;
opb_wrce <= ac97_CS_2 and (not OPB_RNW_1);
XFER_Control : process (OPB_Clk, OPB_Rst) is
begin -- process XFER_Control
if OPB_Rst = '1' then -- asynchronous reset (active high)
xfer_Ack <= '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
xfer_Ack <= ac97_CS_2;
end if;
end process XFER_Control;
Sln_errAck <= '0';
Sln_retry <= '0';
Sln_toutSup <= '0';
sln_xferAck <= xfer_Ack;
OPB_rdDBus_DFF : for I in iSln_DBus'range generate
OPB_rdBus_FDRE : FDRE
port map (
Q => Sln_DBus(I), -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
CE => ac97_CS_2, -- [in std_logic]
D => iSln_Dbus(I), -- [in std_logic]
R => xfer_Ack); -- [in std_logic]
end generate OPB_rdDBus_DFF;
AC97_FIFO_I : ac97_fifo
generic map (
C_PLAYBACK => C_PLAYBACK,
C_RECORD => C_RECORD,
C_INTR_LEVEL => C_INTR_LEVEL,
C_USE_BRAM => C_USE_BRAM
)
port map (
-- IP Interface
Bus2IP_Clk => OPB_Clk,
Bus2IP_Reset => OPB_Rst,
Bus2IP_Addr => OPB_ABus,
Bus2IP_Data => OPB_Dbus,
Bus2IP_BE => OPB_BE,
Bus2IP_RdCE => opb_rdce,
Bus2IP_WrCE => opb_wrce,
IP2Bus_Data => iSln_DBus,
Interrupt => interrupt_i,
-- CODEC signals
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In,
AC97Reset_n => AC97Reset_n
);
end architecture IMP;
|
gpl-3.0
|
aed31b009e429d21afcc0b4d3f2e13a2
| 0.454988 | 3.522306 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/framework/sampling.vhd
| 1 | 26,333 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity sampling is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end sampling;
architecture Behavioral of sampling is
component uf_prediction is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the prediction user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- size of one particle
particle_size : in integer;
-- if every particle is sampled, this signal has to be set to '1'
finished : out std_logic);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (initialize, read_particle_address, read_N,
read_particle_size, read_max_number_of_particles, read_block_size,
read_parameter_address, read_parameter, wait_for_message,
calculate_remaining_particles_1, calculate_remaining_particles_2,
calculate_remaining_particles_3, calculate_remaining_particles_4,
needed_bursts_1, needed_bursts_2, needed_bursts_3,
needed_bursts_4, copy_particle_burst_decision, copy_particle_burst,
--copy_particle_burst_2, copy_particle_burst_3, copy_particle_burst_4,
prediction, prediction_done,
write_burst_decision, write_burst,
calculate_writes_1, calculate_writes_2, calculate_writes_3,
calculate_writes_4, --write_decision, read, write,
write_last_burst,
send_message, send_measurement_1, send_measurement_2);
-- current state
signal state : t_state := initialize;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal current_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter array address
signal parameter_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM write_address
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like N, particle size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 4;
-- number of particles still to resample
signal remaining_particles : integer := 4;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered (for writing back)
signal number_of_bursts_remember : integer := 0;
-- length of last burst
signal last_burst_length : integer := 0;
-- size of a particle
signal particle_size : integer := 48;
-- temp variable
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal offset : integer := 0;
-- start particle index
signal start_particle_index : integer := 0;
-- maximum number of particles, which fit into the local RAM (minus 128 byte)
signal max_number_of_particles : integer := 168;
-- number of bytes, which are not written with valid particle data
signal diff : integer := 0;
-- number of writes
signal number_of_writes : integer := 0;
-- local ram address for interface
signal local_ram_address_if_read : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_address_if_write : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- message (received from message box). The number in the message says,
-- which particle block has to be sampled
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- block size, is the number of particles in a particle block
signal block_size : integer := 10;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
signal particle_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for prediction user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the resampling user process
signal particles_loaded : std_logic := '0';
-- number of particles in local RAM
signal number_of_particles : integer := 4;
-- size of one particle
signal particle_size_2 : integer := 0;
-- if every particle is resampled, this signal has to be set to '1'
signal finished : std_logic := '0';
-- corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
-- for switch 1: corrected local ram address.
-- the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrPrediction : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
--signal o_RAMAddrSampling : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEPrediction : std_logic := '0';
-- for switch 2: Write enable, importance
--signal o_RAMWESampling : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataPrediction : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
--signal o_RAMDataSampling : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_prediction
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrPrediction, o_RAMData=>o_RAMDataPrediction,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWEPrediction, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, particles_loaded=>particles_loaded,
number_of_particles=>number_of_particles,
particle_size=>particle_size_2, finished=>finished);
-- burst ram interface
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrPrediction(0 to C_BURST_AWIDTH-2) & not o_RAMAddrPrediction(C_BURST_AWIDTH-1);
--when enable = '1' else o_RAMAddrSampling(0 to C_BURST_AWIDTH-2) & not o_RAMAddrSampling(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEPrediction when enable = '1' else '0'; -- o_RAMWESampling;
-- switch 3: output ram data
o_RAMData <= o_RAMDataPrediction when enable = '1' else (others=>'0'); -- else o_RAMDataSampling;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Sampling:
--
-- (1) The Parameter are copied to the first 128 bytes of the local RAM
-- Other information are set
--
--
-- (2) Waiting for Message m (Start of a Sampling run)
-- Message m: sample particles of m-th particle block
--
--
-- (3) The number of needed bursts is calculated to fill the local RAM
-- The number only differs from 63, if it is for the last particles,
-- which fit into the local ram.
--
--
-- (4) The particles are copied into the local RAM by burst reads
--
--
-- (5) The user prediction process is run
--
--
-- (6) After prediction the particles are written back to Main Memory.
-- Since there can be several sampling threads, there has to be
-- special treatment for the last 128 byte, which are written
-- in 4 byte blocks and not in a 128 byte burst.
--
--
-- (7) If the user process is finished and more particle need to be
-- sampled, then go to step 3 else to step 8
--
--
-- (8) Send message m (Stop of a Sampling run)
-- Particles of m-th particle block are sampled
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and max number of particles which fit in the local RAM
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable max_number_of_particles_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= initialize;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when initialize =>
--! init state, receive particle array address
-- TODO: C H A N G E !!! (1 of 3)
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
enable <= '0';
local_ram_address <= (others => '0');
local_ram_start_address <= (others => '0');
init <= '1';
particles_loaded <= '0';
if done then
-- TODO: C H A N G E !!! (2 of 3)
state <= read_particle_address;
--state <= wait_for_message;
end if;
when read_particle_address =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= read_N;
end if;
when read_N =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= read_particle_size;
end if;
when read_particle_size =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= read_max_number_of_particles;
end if;
when read_max_number_of_particles =>
--! read max number of particles, which fit into 63 bursts (128 bytes per burst)
reconos_read (done, o_osif, i_osif, information_struct+12, max_number_of_particles_var);
if done then
particle_size_2 <= particle_size / 4;
max_number_of_particles <= TO_INTEGER(SIGNED(max_number_of_particles_var));
state <= read_block_size;
end if;
when read_block_size =>
--! read bock size, this is the size of how many particles are in one block.
-- A message sends the block number
reconos_read (done, o_osif, i_osif, information_struct+16, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
--state <= wait_for_message;
-- CHANGE BACK !!! (1 of 2)
state <= read_parameter_address;
end if;
when read_parameter_address =>
--! read parameter array address
reconos_read_s (done,o_osif,i_osif,information_struct+20,parameter_array_address);
if done then
state <= read_parameter;
end if;
when read_parameter =>
--! copy all parameter in one burst
reconos_read_burst(done,o_osif,i_osif,local_ram_start_address,parameter_array_address);
if done then
state <= wait_for_message;
end if;
when wait_for_message =>
--! wait for message, that starts Sampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
particles_loaded <= '0';
enable <= '0';
init <= '1';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= calculate_remaining_particles_1;
end if;
when calculate_remaining_particles_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
--particle_size <= 32; -- TODO: ONLY FOR SIMULATION
--particle_size_2 <= 8; -- TODO: ONLY FOR SIMULATION
--block_size <= 2; -- TODO: ONLY FOR SIMULATION
--particle_array_start_address <= X"10000000"; -- TODO: ONLY FOR SIMULATION
--N <=100; -- TODO: ONLY FOR SIMULATION
state <= calculate_remaining_particles_2;
when calculate_remaining_particles_2 =>
--! calculates particle array address and number of particles to sample
remaining_particles <= message2 * block_size;
state <= calculate_remaining_particles_3;
when calculate_remaining_particles_3 =>
--! calculates particle array address and number of particles to sample
remaining_particles <= N - remaining_particles;
particle_array_address <= particle_array_start_address;
state <= calculate_remaining_particles_4;
when calculate_remaining_particles_4 =>
--! calculates particle array address and number of particles to sample
if (remaining_particles > block_size) then
remaining_particles <= block_size;
end if;
current_particle_array_address <= particle_array_start_address;
state <= needed_bursts_1;
when needed_bursts_1 =>
--! decision how many bursts are needed
local_ram_address <= local_ram_start_address + 128;
local_ram_address_if_read <= local_ram_start_address_if + 32;
particles_loaded <= '0';
enable <= '0';
init <= '1';
--start_particle_index <= N - remaining_particles;
start_particle_index <= message2 * block_size;
if (remaining_particles <= 0) then
state <= send_message;
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
else
temp <= remaining_particles * particle_size;
state <= needed_bursts_2;
end if;
when needed_bursts_2 =>
--! decision how many bursts are needed
offset <= start_particle_index * particle_size;
state <= needed_bursts_3;
when needed_bursts_3 =>
--! decision how many bursts are needed
current_particle_array_address <= particle_array_start_address + offset;
particle_array_address <= particle_array_start_address + offset;
if (temp >= 8064) then --8064 = 63*128
--copy as much particles as possible
number_of_bursts <= 63;
number_of_bursts_remember <= 63;
number_of_particles <= max_number_of_particles;
state <= copy_particle_burst_decision;
else
-- copy only remaining particles
number_of_bursts <= temp / 128;
number_of_bursts_remember <= temp / 128;
number_of_particles <= remaining_particles;
state <= needed_bursts_4;
end if;
when needed_bursts_4 =>
--! decision how many bursts are needed
number_of_bursts <= number_of_bursts + 1;
number_of_bursts_remember <= number_of_bursts_remember + 1;
state <= copy_particle_burst_decision;
when copy_particle_burst_decision =>
--! check if another burst is needed
if (number_of_bursts > 63) then
number_of_bursts <= 63;
elsif (number_of_bursts > 0) then
number_of_bursts <= number_of_bursts - 1;
state <= copy_particle_burst;
elsif (remaining_particles <= 0) then
-- check it
state <= send_message;
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
else
remaining_particles <= remaining_particles - number_of_particles;
state <= prediction;
enable <= '1';
particles_loaded <= '1';
init <= '0';
end if;
when copy_particle_burst =>
--! read another burst
-- NO MORE BURSTS
--temp3 <= 32;
--state <= copy_particle_burst_2;
reconos_read_burst(done,o_osif,i_osif,local_ram_address,current_particle_array_address);
if done then
state <= copy_particle_burst_decision;
--if (local_ram_address < 8064) then
local_ram_address <= local_ram_address + 128;
--end if;
current_particle_array_address <= current_particle_array_address + 128;
end if;
-- when copy_particle_burst_2 =>
-- --! read another burst
-- -- NO MORE BURSTS
-- enable <= '0';
-- o_RAMWESampling<= '0';
-- if (temp3 > 0) then
-- state <= copy_particle_burst_3;
-- temp3 <= temp3 - 1;
-- else
-- state <= copy_particle_burst_decision;
-- end if;
--
--
-- when copy_particle_burst_3 =>
-- --! read another burst
-- -- NO MORE BURSTS
-- --! load data to local ram
-- reconos_read_s (done, o_osif, i_osif, particle_array_address, particle_data);
-- if done then
-- state <= copy_particle_burst_4;
-- particle_array_address <= particle_array_address + 4;
-- end if;
--
--
-- when copy_particle_burst_4 =>
-- --! write particle data to local ram
-- o_RAMWESampling<= '1';
-- o_RAMAddrSampling <= local_ram_address_if_read;
-- o_RAMDataSampling <= particle_data;
-- local_ram_address_if_read <= local_ram_address_if_read + 1;
-- state <= copy_particle_burst_2;
when prediction =>
--!start prediction user process and wait until prediction is finished
init <= '0';
enable <= '1';
particles_loaded <= '0';
if (finished = '1') then
state <= prediction_done;
end if;
when prediction_done =>
--! prediction finished
init <= '1';
enable <= '0';
particles_loaded <= '0';
current_particle_array_address <= particle_array_address;
local_ram_address <= local_ram_start_address + 128;
local_ram_address_if_write <= local_ram_start_address_if + 32;
number_of_bursts <= number_of_bursts_remember;
state <= write_burst_decision;
when write_burst_decision =>
--! if write burst is demanded by user process, it will be done
if (number_of_bursts > 63) then
number_of_bursts <= 63;
-- NO MORE BURSTS
elsif (number_of_bursts > 1) then
state <= write_burst;
elsif (number_of_bursts <= 1) then
number_of_bursts <= 0;
state <= calculate_writes_1;
diff <= (number_of_bursts_remember * 128);
end if;
when write_burst =>
--! write bursts from local ram into index array
reconos_write_burst(done,o_osif,i_osif,local_ram_address,current_particle_array_address);
if done then
local_ram_address <= local_ram_address + 128;
local_ram_address_if_write <= local_ram_address_if_write + 32;
current_particle_array_address <= current_particle_array_address + 128;
number_of_bursts <= number_of_bursts - 1;
state <= write_burst_decision;
end if;
when calculate_writes_1 =>
--! calculates number of writes (1/4)
temp2 <= number_of_particles * particle_size;
--state <= calculate_writes_4;
-- NO MORE BURSTS
state <= calculate_writes_2;
when calculate_writes_2 =>
--! calculates number of writes (2/4)
diff <= diff - temp2;
state <= calculate_writes_3;
when calculate_writes_3 =>
--! calculates number of writes (3/4)
number_of_writes <= 128 - diff;
state <= calculate_writes_4;
when calculate_writes_4 =>
--! calculates number of writes (4/4)
-- NO MORE BURSTS
--number_of_writes <= number_of_writes / 4;
--number_of_writes <= temp2 / 4;
last_burst_length <= number_of_writes / 8;
--state <= write_decision;
state <= write_last_burst;
when write_last_burst =>
--! write last burst from local ram into index array
reconos_write_burst_l(done,o_osif,i_osif,local_ram_address,
current_particle_array_address,last_burst_length);
if done then
current_particle_array_address <= current_particle_array_address + number_of_writes;
state <= needed_bursts_1;
end if;
--
-- when write_decision =>
-- --! decide if a reconos write is needed
-- if (number_of_writes <= 0) then
-- state <= needed_bursts_1;
-- else
-- -- read local ram data
-- state <= read;
-- o_RAMAddrSampling <= local_ram_address_if_write;
-- end if;
--
--
-- when read =>
-- --! read 4 byte from local RAM
-- number_of_writes <= number_of_writes - 1;
-- --local_ram_address_if <= local_ram_address_if + 1;
-- o_RAMAddrSampling <= local_ram_address_if_write;
-- state <= write;
--
--
-- when write =>
-- --! write 4 byte to particle array in main memory
-- reconos_write(done, o_osif, i_osif, current_particle_array_address, i_RAMData);
-- if done then
-- local_ram_address_if_write <= local_ram_address_if_write + 1;
-- current_particle_array_address <= current_particle_array_address + 4;
-- if (number_of_writes <= 0) then
-- state <= needed_bursts_1;
-- else
-- o_RAMAddrSampling <= local_ram_address_if_write;
-- state <= read;
-- end if;
-- end if;
when send_message =>
--! send message i (sampling is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE,
STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
particles_loaded <= '0';
state <= wait_for_message;
--state <= send_measurement_1;
end if;
-- when send_measurement_1 =>
-- --! sends time measurement to message box
-- -- send only, if time start < time stop. Else ignore this measurement
-- if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= send_measurement_2;
-- else
-- state <= wait_for_message;
-- end if;
-- when send_measurement_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
-- state <= wait_for_message;
-- end if;
when others =>
state <= wait_for_message;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
6ac6e6c5ec850472774a87fa4d7fd668
| 0.580185 | 3.561401 | false | false | false | false |
twlostow/dsi-shield
|
hdl/top/rev2/reset_gen.vhd
| 1 | 1,565 |
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity reset_gen is
port (
clk_sys_i : in std_logic;
spi_cs_n_rst_i: in std_logic;
mask_reset_i : in std_logic;
rst_sys_n_o : out std_logic
);
end reset_gen;
architecture behavioral of reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal unmask_cnt : unsigned(7 downto 0) := x"00";
signal synced_n : std_logic;
signal powerup_n : std_logic := '0';
signal rst_n_a : std_logic;
signal unmask_wait : std_logic;
begin -- behavioral
rst_n_a <= spi_cs_n_rst_i and not mask_reset_i;
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_n_a,
ppulse_o => synced_n);
p_unmask: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
unmask_wait <= '0';
elsif mask_reset_i = '1' then
unmask_wait <= '1';
unmask_cnt <= (others => '0');
elsif (unmask_cnt = x"ff") then
unmask_wait <= '0';
else
unmask_cnt <= unmask_cnt + 1;
end if;
end if;
end process;
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_sys_n_o <= ( powerup_n and (not synced_n) ) or unmask_wait;
end behavioral;
|
lgpl-3.0
|
117702f08240df35d373e63f24234378
| 0.560383 | 2.947269 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/ip/ddr/ddr/user_design/rtl/ddr_mig_sim.vhd
| 1 | 76,865 |
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 2.3
-- \ \ Application : MIG
-- / / Filename : ddr_mig.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module can be instantiated in the
-- system and interconnect as shown in user design wrapper file (user top module).
-- In addition to the memory controller, the module instantiates:
-- 1. Clock generation/distribution, reset logic
-- 2. IDELAY control block
-- 3. Debug logic
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr_mig is
generic (
RST_ACT_LOW : integer := 1;
-- =1 for active low reset,
-- =0 for active high.
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 5;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
ECC_TEST : string := "OFF";
PAYLOAD_WIDTH : integer := 16;
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 16;
-- VCO output divisor for PLL output clock (CLKOUT3)
MMCM_VCO : integer := 1200;
-- Max Freq (MHz) of MMCM VCO
MMCM_MULT_F : integer := 15;
-- write MMCM VCO multiplier
MMCM_DIVCLK_DIVIDE : integer := 1;
-- write MMCM VCO divisor
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP0 : string := "DDR_IODELAY_MIG0";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (200MHz).
IODELAY_GRP1 : string := "DDR_IODELAY_MIG1";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (300MHz/400MHz).
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
FPGA_SPEED_GRADE : integer := 1;
-- FPGA speed grade
REF_CLK_MMCM_IODELAY_CTRL : string := "FALSE";
CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 4;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "EXTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH/8)-1 downto 0) ;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
-- The 12 MSB bits of the temperature sensor transfer
-- function need to be connected to this port. This port
-- will be synchronized w.r.t. to fabric clock internally.
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity ddr_mig;
architecture arch_ddr_mig of ddr_mig is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;
constant DATA_WIDTH : integer := 16;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant TAPSPERKCLK : integer := 56;
function TEMP_MON return string is
begin
if(SIMULATION = "TRUE") then
return "ON";
else
return "OFF";
end if;
end function;
constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
constant ECC_WIDTH : integer := ECCWIDTH;
constant DATA_BUF_OFFSET_WIDTH : integer := 1;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
constant TEMP_MON_EN : string := TEMP_MON;
-- Enable or disable the temp monitor module
constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
component mig_7series_v2_3_iodelay_ctrl is
generic(
TCQ : integer;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
REFCLK_TYPE : string;
SYSCLK_TYPE : string;
SYS_RST_PORT : string;
RST_ACT_LOW : integer;
DIFF_TERM_REFCLK : string;
FPGA_SPEED_GRADE : integer;
REF_CLK_MMCM_IODELAY_CTRL : string
);
port (
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
clk_ref_i : in std_logic;
sys_rst : in std_logic;
clk_ref : out std_logic_vector(1 downto 0);
sys_rst_o : out std_logic;
iodelay_ctrl_rdy : out std_logic_vector(1 downto 0)
);
end component mig_7series_v2_3_iodelay_ctrl;
component mig_7series_v2_3_clk_ibuf is
generic (
SYSCLK_TYPE : string;
DIFF_TERM_SYSCLK : string
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk_i : in std_logic;
mmcm_clk : out std_logic
);
end component mig_7series_v2_3_clk_ibuf;
component mig_7series_v2_3_infrastructure is
generic (
SIMULATION : string := "TRUE";
TCQ : integer;
CLKIN_PERIOD : integer;
nCK_PER_CLK : integer;
SYSCLK_TYPE : string;
UI_EXTRA_CLOCKS : string := "FALSE";
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
MMCM_VCO : integer;
MMCM_MULT_F : integer;
MMCM_DIVCLK_DIVIDE : integer;
MMCM_CLKOUT0_EN : string := "FALSE";
MMCM_CLKOUT1_EN : string := "FALSE";
MMCM_CLKOUT2_EN : string := "FALSE";
MMCM_CLKOUT3_EN : string := "FALSE";
MMCM_CLKOUT4_EN : string := "FALSE";
MMCM_CLKOUT0_DIVIDE : integer := 1;
MMCM_CLKOUT1_DIVIDE : integer := 1;
MMCM_CLKOUT2_DIVIDE : integer := 1;
MMCM_CLKOUT3_DIVIDE : integer := 1;
MMCM_CLKOUT4_DIVIDE : integer := 1;
RST_ACT_LOW : integer;
tCK : integer;
MEM_TYPE : string
);
port (
mmcm_clk : in std_logic;
sys_rst : in std_logic;
iodelay_ctrl_rdy : in std_logic_vector(1 downto 0);
psen : in std_logic;
psincdec : in std_logic;
clk : out std_logic;
mem_refclk : out std_logic;
freq_refclk : out std_logic;
sync_pulse : out std_logic;
mmcm_ps_clk : out std_logic;
poc_sample_pd : out std_logic;
iddr_rst : out std_logic;
psdone : out std_logic;
auxout_clk : out std_logic;
ui_addn_clk_0 : out std_logic;
ui_addn_clk_1 : out std_logic;
ui_addn_clk_2 : out std_logic;
ui_addn_clk_3 : out std_logic;
ui_addn_clk_4 : out std_logic;
pll_locked : out std_logic;
mmcm_locked : out std_logic;
rstdiv0 : out std_logic;
rst_phaser_ref : out std_logic;
ref_dll_lock : in std_logic
);
end component mig_7series_v2_3_infrastructure;
component mig_7series_v2_3_tempmon is
generic (
TCQ : integer;
TEMP_MON_CONTROL : string;
XADC_CLK_PERIOD : integer;
tTEMPSAMPLE : integer
);
port (
clk : in std_logic;
xadc_clk : in std_logic;
rst : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
device_temp : out std_logic_vector(11 downto 0)
);
end component mig_7series_v2_3_tempmon;
component mig_7series_v2_3_memc_ui_top_std is
generic (
TCQ : integer;
DDR3_VDD_OP_VOLT : string := "135";
PAYLOAD_WIDTH : integer;
ADDR_CMD_MODE : string;
AL : string;
BANK_WIDTH : integer;
BM_CNT_WIDTH : integer;
BURST_MODE : string;
BURST_TYPE : string;
CA_MIRROR : string := "FALSE";
CK_WIDTH : integer;
CL : integer;
COL_WIDTH : integer;
CMD_PIPE_PLUS1 : string;
CS_WIDTH : integer;
CKE_WIDTH : integer;
CWL : integer := 5;
DATA_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DDR2_DQSN_ENABLE : string := "YES";
DM_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
DRAM_WIDTH : integer;
ECC : string;
ECC_WIDTH : integer;
ECC_TEST : string;
MC_ERR_ADDR_WIDTH : integer;
MASTER_PHY_CTL : integer;
nAL : integer;
nBANK_MACHS : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
ORDERING : string;
IBUF_LPWR_MODE : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN : string;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
FPGA_SPEED_GRADE : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string := "120";
STARVE_LIMIT : integer;
tCK : integer;
tCKE : integer;
tFAW : integer;
tPRDI : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
USER_REFRESH : string;
TEMP_MON_EN : string;
WRLVL : string;
DEBUG_PORT : string;
CAL_WIDTH : string;
RANK_WIDTH : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
APP_MASK_WIDTH : integer;
APP_DATA_WIDTH : integer;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
SIM_BYPASS_INIT_CAL : string;
REFCLK_FREQ : real;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IDELAY_ADJ : string;
FINE_PER_BIT : string;
CENTER_COMP_MODE : string;
PI_VAL_ADJ : string;
TAPSPERKCLK : integer := 56
);
port (
clk : in std_logic;
clk_ref : in std_logic_vector(1 downto 0);
mem_refclk : in std_logic;
freq_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
rst : in std_logic;
rst_phaser_ref : in std_logic;
ref_dll_lock : out std_logic;
iddr_rst : in std_logic;
mmcm_ps_clk : in std_logic;
poc_sample_pd : in std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_hi_pri : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1 downto 0);
app_wdf_wren : in std_logic;
app_correct_en_i : in std_logic;
app_raw_not_ecc : in std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_multiple_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
device_temp : in std_logic_vector(11 downto 0);
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_final_po_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
dbg_prbs_final_dqs_tap_cnt_r : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
init_calib_complete : out std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_cpt_tap_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
dbg_rd_data_offset : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_calib_rd_data_offset_1 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_rd_data_offset_2 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_data_offset : out std_logic_vector(5 downto 0);
dbg_data_offset_1 : out std_logic_vector(5 downto 0);
dbg_data_offset_2 : out std_logic_vector(5 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector((DRAM_WIDTH*16)-1 downto 0)
);
end component mig_7series_v2_3_memc_ui_top_std;
-- Signal declarations
signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
signal clk : std_logic;
signal clk_ref : std_logic_vector(1 downto 0);
signal iodelay_ctrl_rdy : std_logic_vector(1 downto 0);
signal clk_ref_in : std_logic;
signal sys_rst_o : std_logic;
signal freq_refclk : std_logic;
signal mem_refclk : std_logic;
signal pll_locked : std_logic;
signal sync_pulse : std_logic;
signal mmcm_ps_clk : std_logic;
signal poc_sample_pd : std_logic;
signal psen : std_logic;
signal psincdec : std_logic;
signal psdone : std_logic;
signal iddr_rst : std_logic;
signal ref_dll_lock : std_logic;
signal rst_phaser_ref : std_logic;
signal rst : std_logic;
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal ddr2_reset_n : std_logic;
signal ddr2_parity : std_logic;
signal init_calib_complete_i : std_logic;
signal sys_clk_p : std_logic;
signal sys_clk_n : std_logic;
signal mmcm_clk : std_logic;
signal clk_ref_p : std_logic;
signal clk_ref_n : std_logic;
signal clk_ref_i : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
-- Debug port signals
signal dbg_idel_down_all : std_logic;
signal dbg_idel_down_cpt : std_logic;
signal dbg_idel_up_all : std_logic;
signal dbg_idel_up_cpt : std_logic;
signal dbg_sel_all_idel_cpt : std_logic;
signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal dbg_pi_f_inc : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_po_f_dec : std_logic;
signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps : std_logic_vector(11 downto 0);
signal dbg_cpt_tap_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_dq_idelay_tap_cnt : std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_calib_top : std_logic_vector(255 downto 0);
signal dbg_cpt_first_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_cpt_second_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_rd_data_offset : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
signal dbg_final_po_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_final_po_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
signal dbg_phy_init : std_logic_vector(255 downto 0);
signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
signal dbg_pi_phaselock_start : std_logic;
signal dbg_pi_phaselocked_done : std_logic;
signal dbg_pi_phaselock_err : std_logic;
signal dbg_pi_dqsfound_start : std_logic;
signal dbg_pi_dqsfound_done : std_logic;
signal dbg_pi_dqsfound_err : std_logic;
signal dbg_wrcal_start : std_logic;
signal dbg_wrcal_done : std_logic;
signal dbg_wrcal_err : std_logic;
signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_oclkdelay_calib_start : std_logic;
signal dbg_oclkdelay_calib_done : std_logic;
signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
signal dbg_oclkdelay_rd_data : std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dbg_rddata : std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
signal dbg_rddata_valid : std_logic;
signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
signal dbg_wrlvl_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
signal dbg_wl_edge_detect_valid : std_logic;
signal dbg_wrlvl_done : std_logic;
signal dbg_wrlvl_err : std_logic;
signal dbg_wrlvl_start : std_logic;
signal dbg_rddata_r : std_logic_vector(63 downto 0);
signal dbg_rddata_valid_r : std_logic;
signal ocal_tap_cnt : std_logic_vector(53 downto 0);
signal dbg_dqs : std_logic_vector(4 downto 0);
signal dbg_bit : std_logic_vector(8 downto 0);
signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
signal dbg_calib_rd_data_offset_1 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_calib_rd_data_offset_2 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_data_offset : std_logic_vector(5 downto 0);
signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
signal all_zeros : std_logic_vector((2*nCK_PER_CLK)-1 downto 0) := (others => '0');
signal ddr2_ila_basic_int : std_logic_vector(119 downto 0);
signal ddr2_ila_wrpath_int : std_logic_vector(390 downto 0);
signal ddr2_ila_rdpath_int : std_logic_vector(1023 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r_int : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps_int : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps_int : std_logic_vector(11 downto 0);
begin
--***************************************************************************
ui_clk <= clk;
ui_clk_sync_rst <= rst;
sys_clk_p <= '0';
sys_clk_n <= '0';
clk_ref_i <= '0';
init_calib_complete <= init_calib_complete_i;
clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
clk_ref_in <= mmcm_clk;
end generate;
clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
clk_ref_in <= clk_ref_i;
end generate;
u_iodelay_ctrl : mig_7series_v2_3_iodelay_ctrl
generic map
(
TCQ => TCQ,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
REFCLK_TYPE => REFCLK_TYPE,
SYSCLK_TYPE => SYSCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
RST_ACT_LOW => RST_ACT_LOW,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REF_CLK_MMCM_IODELAY_CTRL => REF_CLK_MMCM_IODELAY_CTRL
)
port map
(
-- Outputs
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
sys_rst_o => sys_rst_o,
clk_ref => clk_ref,
-- Inputs
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
clk_ref_i => clk_ref_in,
sys_rst => sys_rst
);
u_ddr2_clk_ibuf : mig_7series_v2_3_clk_ibuf
generic map
(
SYSCLK_TYPE => SYSCLK_TYPE,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
)
port map
(
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_clk_i => sys_clk_i,
mmcm_clk => mmcm_clk
);
-- Temperature monitoring logic
temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
u_tempmon : mig_7series_v2_3_tempmon
generic map
(
TCQ => TCQ,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
XADC_CLK_PERIOD => XADC_CLK_PERIOD,
tTEMPSAMPLE => tTEMPSAMPLE
)
port map
(
clk => clk,
xadc_clk => clk_ref(0),
rst => rst,
device_temp_i => device_temp_i,
device_temp => device_temp
);
end generate;
temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
device_temp <= (others => '0');
end generate;
u_ddr2_infrastructure : mig_7series_v2_3_infrastructure
generic map
(
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLKIN_PERIOD => CLKIN_PERIOD,
SYSCLK_TYPE => SYSCLK_TYPE,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
MMCM_VCO => MMCM_VCO,
MMCM_MULT_F => MMCM_MULT_F,
MMCM_DIVCLK_DIVIDE => MMCM_DIVCLK_DIVIDE,
RST_ACT_LOW => RST_ACT_LOW,
tCK => tCK,
MEM_TYPE => DRAM_TYPE
)
port map
(
-- Outputs
rstdiv0 => rst,
clk => clk,
mem_refclk => mem_refclk,
freq_refclk => freq_refclk,
sync_pulse => sync_pulse,
psen => psen,
psincdec => psincdec,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
iddr_rst => iddr_rst,
psdone => psdone,
auxout_clk => open,
ui_addn_clk_0 => open,
ui_addn_clk_1 => open,
ui_addn_clk_2 => open,
ui_addn_clk_3 => open,
ui_addn_clk_4 => open,
pll_locked => pll_locked,
mmcm_locked => open,
rst_phaser_ref => rst_phaser_ref,
-- Inputs
mmcm_clk => mmcm_clk,
sys_rst => sys_rst_o,
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
ref_dll_lock => ref_dll_lock
);
u_memc_ui_top_std : mig_7series_v2_3_memc_ui_top_std
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DM_WIDTH => DM_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
REFCLK_FREQ => REFCLK_FREQ,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
nCK_PER_CLK => nCK_PER_CLK,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCK => tCK,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
TEMP_MON_EN => TEMP_MON_EN,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
CAL_WIDTH => CAL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
STARVE_LIMIT => STARVE_LIMIT,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IDELAY_ADJ => "OFF",
FINE_PER_BIT => "OFF",
CENTER_COMP_MODE => "OFF",
PI_VAL_ADJ => "OFF",
MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK,
TAPSPERKCLK => TAPSPERKCLK
)
port map (
clk => clk,
clk_ref => clk_ref,
mem_refclk => mem_refclk, --memory clock
freq_refclk => freq_refclk,
pll_lock => pll_locked,
sync_pulse => sync_pulse,
rst => rst,
rst_phaser_ref => rst_phaser_ref,
ref_dll_lock => ref_dll_lock,
iddr_rst => iddr_rst,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
-- Memory interface ports
ddr_dq => ddr2_dq,
ddr_dqs_n => ddr2_dqs_n,
ddr_dqs => ddr2_dqs_p,
ddr_addr => ddr2_addr,
ddr_ba => ddr2_ba,
ddr_cas_n => ddr2_cas_n,
ddr_ck_n => ddr2_ck_n,
ddr_ck => ddr2_ck_p,
ddr_cke => ddr2_cke,
ddr_cs_n => ddr2_cs_n,
ddr_dm => ddr2_dm,
ddr_odt => ddr2_odt,
ddr_ras_n => ddr2_ras_n,
ddr_reset_n => ddr2_reset_n,
ddr_parity => ddr2_parity,
ddr_we_n => ddr2_we_n,
bank_mach_next => bank_mach_next,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_hi_pri => '0',
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_ecc_multiple_err => app_ecc_multiple_err,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_sr_active => app_sr_active,
app_ref_req => app_ref_req,
app_ref_ack => app_ref_ack,
app_zq_req => app_zq_req,
app_zq_ack => app_zq_ack,
app_raw_not_ecc => all_zeros,
app_correct_en_i => '1',
psen => psen,
psincdec => psincdec,
psdone => psdone,
device_temp => device_temp,
-- Debug logic ports
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_calib_top => dbg_calib_top,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_rd_data_offset => dbg_rd_data_offset,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_rddata => dbg_rddata,
dbg_rddata_valid => dbg_rddata_valid,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_pi_counter_read_val => dbg_pi_counter_read_val,
dbg_po_counter_read_val => dbg_po_counter_read_val,
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_phaselocked_done => dbg_pi_phaselocked_done,
dbg_pi_phaselock_err => dbg_pi_phaselock_err,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
dbg_data_offset => dbg_data_offset,
dbg_data_offset_1 => dbg_data_offset_1,
dbg_data_offset_2 => dbg_data_offset_2,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrcal_err => dbg_wrcal_err,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
dbg_prbs_final_dqs_tap_cnt_r => dbg_prbs_final_dqs_tap_cnt_r_int,
dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps_int,
dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps_int,
init_calib_complete => init_calib_complete_i
);
--*********************************************************************
-- Resetting all RTL debug inputs as the debug ports are not enabled
--*********************************************************************
dbg_idel_down_all <= '0';
dbg_idel_down_cpt <= '0';
dbg_idel_up_all <= '0';
dbg_idel_up_cpt <= '0';
dbg_sel_all_idel_cpt <= '0';
dbg_sel_idel_cpt <= (others => '0');
dbg_byte_sel <= (others => '0');
dbg_sel_pi_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
dbg_sel_po_incdec <= '0';
end architecture arch_ddr_mig;
|
gpl-3.0
|
27f3cb82f1b2d0251940f42666bb3328
| 0.449658 | 4.205099 | false | false | false | false |
whitef0x0/EECE353-Lab5
|
lab5_new_tb.vhd
| 1 | 16,266 |
-- lab5_new Testbench. A test bench is a file that describes the commands that should
-- be used when simulating the design. The test bench does not describe any hardware,
-- but is only used during simulation. In Lab 2, you can use this test bench directly,
-- and do *not need to modify it* (in later labs, you will have to write test benches).
-- Therefore, you do not need to worry about the details in this file (but you might find
-- it interesting to look through anyway).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
-- Testbenches don't have input and output ports. We'll talk about that in class
-- later in the course.
entity lab5_new_tb is
end lab5_new_tb;
architecture stimulus of lab5_new_tb is
--Declare the device under test (DUT)
component lab5_new is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
--LEDG : out std_logic_vector(7 downto 0);
colour_out : out std_logic_vector(2 downto 0);
x_out : out std_logic_vector(7 downto 0);
y_out : out std_logic_vector(6 downto 0);
plot_out : out std_logic);
end component;
--Signals that connect to the ports of the DUT. The inputs would be
--driven inside the testbench according to different test cases, and
--the output would be monitored in the waveform viewer.
--Input/Output mapping signals
signal clk: std_logic := '0';
signal key : std_logic_vector(3 downto 0);
signal sw : std_logic_vector(17 downto 0);
-- signal led_out : std_logic_vector(7 downto 0);
signal colour_out : std_logic_vector(2 downto 0);
signal x_out : std_logic_vector(7 downto 0);
signal y_out : std_logic_vector(6 downto 0);
signal plot_out : std_logic;
--Component Signals
--KEY Signals
signal resetb : std_logic := '1';
--SW Signals
signal p1_goalie : std_logic := '0';
signal p1_fwd : std_logic := '0';
signal p2_goalie : std_logic := '0';
signal p2_fwd : std_logic := '0';
--Records/Arrays for testing
--type record_name is
-- output_record
-- colour : std_logic_vector(2 downto 0);
-- x_out : std_logic_vector(7 downto 0);
-- y_out : std_logic_vector(6 downto 0);
-- plot : std_logic;
-- end record;
--type record_name is
-- input_record
-- key : in std_logic_vector(3 downto 0);
-- sw : in std_logic_vector(17 downto 0);
-- end record;
--type input_record_array is array (0 to 10) of input_record;
--type output_record_array is array (0 to 10) of output_record;
--signal s_input_sequence : input_record_array;
--signal s_output_sequence : output_record_array;
--Declare a constant of type 'time'. This would be used to cause delay
-- between clock edges
--Period of 50MHz Clock
--constant HALF_PERIOD : Time := 10ns;
constant HALF_PERIOD : Time := 1ps;
--Colour constants
constant WALL_COLOUR : std_logic_vector(2 downto 0) := "111";
constant BACKGROUND_COLOUR : std_logic_vector(2 downto 0) := "000";
constant P1_COLOUR : std_logic_vector(2 downto 0) := "001";
constant P2_COLOUR : std_logic_vector(2 downto 0) := "100";
--Position constants
constant INIT_X_PUCK : unsigned(7 downto 0) := "01010000"; --80
constant INIT_Y_PUCK : unsigned(6 downto 0) := "0111100"; --60
--constant INIT_X_DRAW : std_logic_vector(7 downto 0) := "00000101"; --5
--constant INIT_Y_DRAW : std_logic_vector(7 downto 0) := "0000101"; --5
begin
key <= resetb & "000";
sw <= p2_fwd & p2_goalie & "00000000000000" & p2_fwd & p2_goalie;
DUT: lab5_new
port map (
CLOCK_50 => clk,
key => key,
sw => sw,
-- ledg => out_led,
colour_out => colour_out,
x_out => x_out,
y_out => y_out,
plot_out => plot_out
);
-- CLOCK STIMULI
clock_process: process is
begin
CLK <= not clk after HALF_PERIOD;
wait for 2*HALF_PERIOD;
end process;
test: process is
variable t1g, t1f, t2g, t2f: unsigned(6 downto 0);
variable puckx : unsigned(7 downto 0) := INIT_X_PUCK; -- 80
variable pucky : unsigned(6 downto 0) := INIT_Y_PUCK; -- 60
variable velx : std_logic := '0';
variable vely : std_logic := '0';
variable tmp_i_y : integer := 0;
variable tmp_i_x : integer := 0;
-- procedure test_sequence(
-- input_sequence: input_record_array;
-- expected_output_sequence: output_record_array
-- ) is begin
-- for i in input_sequence'range loop
-- x_out <= input_sequence(i);
-- wait until rising_edge(clk);
-- assert colour_out = expected_output_sequence(i).colour;
-- --assert x_out = expected_output_sequence(i).x_out;
-- --assert y_out = expected_output_sequence(i).y_out;
-- assert plot_out = expected_output_sequence(i).plot;
-- end loop;
-- end;
procedure clear_screen is
begin
wait until rising_edge(clk);
assert x_out = "00000000" report "x not initialized to 0" severity failure;
assert y_out = "0000000" report "y not initialized to 0run" severity failure;
assert plot_out = '0' report "plot != 0 " severity failure;
assert colour_out = BACKGROUND_COLOUR report "color not 000 " severity failure;
wait until rising_edge(clk);
wait until rising_edge(clk);
for i_y in 0 to 119 loop
for i_x in 1 to 160 loop
tmp_i_x := i_x;
tmp_i_y := i_y;
--report "plot_out is "& std_logic'image( plot_out );
assert plot_out = '1' report "plot not 1 CLRSCRN. plot_out:"& std_logic'image( plot_out) &" i_x:"&integer'image( i_x)& " i_y:"& integer'image( i_y) severity failure;
-- assert x_out = std_logic_vector(i_x);
-- assert y_out = std_logic_vector(i_y);
assert colour_out = BACKGROUND_COLOUR report "color not 000 CLRSCRN" severity failure;
wait until rising_edge(clk);
end loop;
end loop;
--report "END CLR SCRN\n";
--report "plot_out:"& std_logic'image( plot_out) &" i_x:"&integer'image( tmp_i_x)& " i_y:"& integer'image( tmp_i_y);
--report "colour_out:"& integer'image( conv_integer(colour_out) ) &" x_out:"&integer'image( conv_integer(x_out) )& " y_out:"& integer'image( conv_integer(y_out) );
end clear_screen;
procedure draw_walls is
begin
--wait until rising_edge(clk);
--Check we are starting in correct state
--assert plot_out = '1' ;
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure; -- make sure colour of walls is white
-- make sure we start at (5,5)
--report "x_out is "& integer'image( conv_integer(x_out) );
assert x_out = "00000101" report "x_out not 5" severity failure;
assert y_out = "0000101" report "y_out not 5" severity failure;
wait until rising_edge(clk);
--Draw top wall
for i in 6 to 154 loop
--report "plot_out is "& std_logic'image( plot_out );
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
-- assert x_out = std_logic_vector(i);
-- assert y_out = "0000101";
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
wait until rising_edge(clk);
end loop;
--report "colour_out:"& integer'image( conv_integer(colour_out) ) &" x_out:"&integer'image( conv_integer(x_out) )& " y_out:"& integer'image( conv_integer(y_out) );
-- make sure we start at (5,155)
assert x_out = "00000101" report "x_out not 5" severity failure;
assert y_out = "1110011" report "x_out not 115" severity failure;
wait until rising_edge(clk);
--report "colour_out:"& integer'image( conv_integer(colour_out) ) &" x_out:"&integer'image( conv_integer(x_out) )& " y_out:"& integer'image( conv_integer(y_out) );
--Draw bottom wall
for i in 6 to 154 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
assert x_out = conv_std_logic_vector(i,x_out'length) report "x_out not i. x_out:"&integer'image(conv_integer(x_out))&" i:"&integer'image(i) severity failure;
assert y_out = "1110011" report "x_out not 115" severity failure;
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
wait until rising_edge(clk);
end loop;
end draw_walls;
procedure draw_paddles is
begin
--STEP #1
--test s1g state (DRAW PLYR1 GOALIE)
--Start drawing from (5,6)
assert x_out = "00000101" report "x_out not 5" severity failure; -- 5
assert y_out = "0000110" report "x_out not 5" severity failure; -- 6
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
wait until rising_edge(clk);
--run s1g state (DRAW PLYR2 GOALIE)
for i in 7 to 115 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
if((i >= 54) and (i <= 66)) then
assert colour_out = P1_COLOUR report "colour_out not P1_COLOUR" severity failure;
elsif(i = 115) then
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
else
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
end if;
wait until rising_edge(clk);
end loop;
t1g := t1g + 1;
--STEP #2
--test s1f state (DRAW PLYR1 FWD)
assert x_out = "01000011"; -- 67
assert y_out = "0000110" report "x_out not 5" severity failure; -- 6
assert colour_out = BACKGROUND_COLOUR report "BACKGROUND_COLOUR" severity failure;
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
wait until rising_edge(clk);
--run s1f state (DRAW PLYR1 FWD)
for i in 7 to 115 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
if(i >= 54 and i <= 66) then
assert colour_out = P1_COLOUR report "colour_out not P2_COLOUR" severity failure;
elsif(i = 115) then
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
else
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
end if;
wait until rising_edge(clk);
end loop;
t1f := t1f + 1;
--STEP #3
--test s2g state (DRAW PLYR2 GOALIE)
assert x_out = "10011010"; -- 154
assert y_out = "0000110" report "x_out not 5" severity failure; -- 6
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
wait until rising_edge(clk);
--run s2g state (DRAW PLYR2 GOALIE)
for i in 7 to 115 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
if(i >= 54 and i <= 66) then
assert colour_out = P2_COLOUR report "colour_out not P2_COLOUR" severity failure;
elsif(i = 115) then
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
else
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
end if;
wait until rising_edge(clk);
end loop;
t2g := t2g + 1;
--STEP #4
--test s2f state (DRAW PLYR2 FWD)
assert x_out = "01011101"; -- 93
assert y_out = "0000110" report "x_out not 5" severity failure; -- 6
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
wait until rising_edge(clk);
--run s2g state (DRAW PLYR2 GOALIE)
for i in 7 to 115 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
if(i >= 54 and i <= 66) then
assert colour_out = P2_COLOUR report "colour_out not P2_COLOUR" severity failure;
elsif(i = 115) then
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
else
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
end if;
wait until rising_edge(clk);
end loop;
t2f := t2f + 1;
--STEP #5
--test sgp1 state (INIT PUCK)
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
assert colour_out = BACKGROUND_COLOUR report "colour not BACKGROUND_COLOUR" severity failure;
assert x_out = std_logic_vector(INIT_X_PUCK) report "x_out not INIT_X_PUCK (80)" severity failure; -- 80
assert y_out = std_logic_vector(INIT_Y_PUCK) report"y_out not INIT_Y_PUCK (60)" severity failure; -- 60
wait until rising_edge(clk);
end draw_paddles;
begin
--Test #1: Move All Paddles DOWN
--Initialize inputs
p2_fwd <= '0';
p2_goalie <= '0';
p1_fwd <= '0';
p2_goalie <= '0';
--Initialization Procedure
t1g := "0110110";
t1f := "0110110";
t2g := "0110110";
t2f := "0110110";
velx := p2_fwd xor p1_fwd;
velx := p2_goalie xor p1_goalie;
--Press Reset
resetb <= '0';
wait until rising_edge(clk);
--Clear Screen Initial State
resetb <= '1';
clear_screen;
draw_walls;
draw_paddles;
--wait until rising_edge(clk);
--Test 1 | STEP #1
--test sgp2 state (PUCK COLLISION and PUCK DRAW)
-- PUCK will move on UPWARD-LEFT trajectory till (26, 6)
for i in 0 to 53 loop
--Draw ball
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
--report "colour_out:"& integer'image( conv_integer(colour_out) ) &" x_out:"&integer'image( conv_integer(x_out) )& " y_out:"& integer'image( conv_integer(y_out) );
--report " i:"&integer'image( i );
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
puckx := puckx - 1;
pucky := pucky - 1;
assert x_out = std_logic_vector(puckx);
assert y_out = std_logic_vector(pucky);
wait until rising_edge(clk);
--Wait until paddle have been updated
assert plot_out = '0' report "plot!=1 " severity failure;
wait until plot_out = '1';
--Wait until paddles have been fully drawn
for b in 0 to 441 loop
assert plot_out = '1' report "plot != 1 " severity failure;
wait until rising_edge(clk);
end loop;
end loop;
-- PUCK hits TOP wall and bounces off DOWNWARD-LEFT after (26, 6)
assert y_out = "0000101" report "ynot != 5" severity failure; -- 5
assert x_out = "00011011" report "xnot != 25" severity failure; -- 25
puckx := puckx - 1;
pucky := pucky + 1;
vely := '1';
wait until rising_edge(clk);
-- PUCK will move on a DOWNWARD-LEFT trajectory till (4, 28)
for i in 0 to 21 loop
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
puckx := puckx - 1;
pucky := pucky + 1;
wait until rising_edge(clk);
--Wait until paddle have been updated
assert plot_out = '0' report "plot != 0" severity failure;
wait until plot_out = '1';
--Wait until paddles have been fully drawn
for b in 0 to 440 loop
assert plot_out = '1' report "plot != 1" severity failure;
wait until rising_edge(clk);
end loop;
end loop;
-- PUCK hit RIGHT WALL and bounces off DOWNWARD-RIGHT after (4, 28)
-- Player2 scores a point and game resets
assert y_out = "0000101" report "y_out != 5" severity failure; -- 5
assert x_out = "00011011" report "x_out != 25" severity failure; -- 25
puckx := puckx + 1;
pucky := pucky + 1;
vely := '1';
wait until rising_edge(clk);
-- PUCK will be reset to (80,60)
clear_screen;
draw_walls;
draw_paddles;
assert x_out = std_logic_vector(INIT_X_PUCK) report "x_out != 80" severity failure; -- 80
assert y_out = std_logic_vector(INIT_Y_PUCK) report "y_out != 60" severity failure; -- 60
wait until rising_edge(clk);
report "FINISHED TEST#1";
std.env.finish;
end process;
end architecture;
|
mit
|
9eee71008975aa1283336c7d586e842d
| 0.632731 | 3.286061 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/Stack/Stack_sim_netlist.vhdl
| 1 | 71,227 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Wed Apr 27 15:28:05 2016
-- Host : Dries007Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Github/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/Stack/Stack_sim_netlist.vhdl
-- Design : Stack
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Stack_spram is
port (
spo : out STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
we : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Stack_spram : entity is "spram";
end Stack_spram;
architecture STRUCTURE of Stack_spram is
signal qspo_int : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of qspo_int : signal is "true";
signal ram_reg_0_255_0_0_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_0_0_n_0 : STD_LOGIC;
signal ram_reg_0_255_10_10_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_10_10_n_0 : STD_LOGIC;
signal ram_reg_0_255_11_11_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_11_11_n_0 : STD_LOGIC;
signal ram_reg_0_255_12_12_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_12_12_n_0 : STD_LOGIC;
signal ram_reg_0_255_13_13_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_13_13_n_0 : STD_LOGIC;
signal ram_reg_0_255_14_14_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_14_14_n_0 : STD_LOGIC;
signal ram_reg_0_255_15_15_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_15_15_n_0 : STD_LOGIC;
signal ram_reg_0_255_1_1_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_1_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_2_2_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_2_2_n_0 : STD_LOGIC;
signal ram_reg_0_255_3_3_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_3_3_n_0 : STD_LOGIC;
signal ram_reg_0_255_4_4_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_4_4_n_0 : STD_LOGIC;
signal ram_reg_0_255_5_5_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_5_5_n_0 : STD_LOGIC;
signal ram_reg_0_255_6_6_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_6_6_n_0 : STD_LOGIC;
signal ram_reg_0_255_7_7_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_7_7_n_0 : STD_LOGIC;
signal ram_reg_0_255_8_8_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_8_8_n_0 : STD_LOGIC;
signal ram_reg_0_255_9_9_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_9_9_n_0 : STD_LOGIC;
signal ram_reg_256_511_0_0_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_0_0_n_0 : STD_LOGIC;
signal ram_reg_256_511_10_10_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_10_10_n_0 : STD_LOGIC;
signal ram_reg_256_511_11_11_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_11_11_n_0 : STD_LOGIC;
signal ram_reg_256_511_12_12_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_12_12_n_0 : STD_LOGIC;
signal ram_reg_256_511_13_13_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_13_13_n_0 : STD_LOGIC;
signal ram_reg_256_511_14_14_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_14_14_n_0 : STD_LOGIC;
signal ram_reg_256_511_15_15_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_15_15_n_0 : STD_LOGIC;
signal ram_reg_256_511_1_1_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_1_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_2_2_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_2_2_n_0 : STD_LOGIC;
signal ram_reg_256_511_3_3_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_3_3_n_0 : STD_LOGIC;
signal ram_reg_256_511_4_4_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_4_4_n_0 : STD_LOGIC;
signal ram_reg_256_511_5_5_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_5_5_n_0 : STD_LOGIC;
signal ram_reg_256_511_6_6_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_6_6_n_0 : STD_LOGIC;
signal ram_reg_256_511_7_7_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_7_7_n_0 : STD_LOGIC;
signal ram_reg_256_511_8_8_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_8_8_n_0 : STD_LOGIC;
signal ram_reg_256_511_9_9_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_9_9_n_0 : STD_LOGIC;
signal ram_reg_512_767_0_0_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_0_0_n_0 : STD_LOGIC;
signal ram_reg_512_767_10_10_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_10_10_n_0 : STD_LOGIC;
signal ram_reg_512_767_11_11_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_11_11_n_0 : STD_LOGIC;
signal ram_reg_512_767_12_12_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_12_12_n_0 : STD_LOGIC;
signal ram_reg_512_767_13_13_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_13_13_n_0 : STD_LOGIC;
signal ram_reg_512_767_14_14_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_14_14_n_0 : STD_LOGIC;
signal ram_reg_512_767_15_15_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_15_15_n_0 : STD_LOGIC;
signal ram_reg_512_767_1_1_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_1_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_2_2_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_2_2_n_0 : STD_LOGIC;
signal ram_reg_512_767_3_3_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_3_3_n_0 : STD_LOGIC;
signal ram_reg_512_767_4_4_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_4_4_n_0 : STD_LOGIC;
signal ram_reg_512_767_5_5_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_5_5_n_0 : STD_LOGIC;
signal ram_reg_512_767_6_6_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_6_6_n_0 : STD_LOGIC;
signal ram_reg_512_767_7_7_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_7_7_n_0 : STD_LOGIC;
signal ram_reg_512_767_8_8_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_8_8_n_0 : STD_LOGIC;
signal ram_reg_512_767_9_9_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_9_9_n_0 : STD_LOGIC;
signal ram_reg_768_1023_0_0_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_0_0_n_0 : STD_LOGIC;
signal ram_reg_768_1023_10_10_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_10_10_n_0 : STD_LOGIC;
signal ram_reg_768_1023_11_11_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_11_11_n_0 : STD_LOGIC;
signal ram_reg_768_1023_12_12_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_12_12_n_0 : STD_LOGIC;
signal ram_reg_768_1023_13_13_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_13_13_n_0 : STD_LOGIC;
signal ram_reg_768_1023_14_14_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_14_14_n_0 : STD_LOGIC;
signal ram_reg_768_1023_15_15_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_15_15_n_0 : STD_LOGIC;
signal ram_reg_768_1023_1_1_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_1_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_2_2_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_2_2_n_0 : STD_LOGIC;
signal ram_reg_768_1023_3_3_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_3_3_n_0 : STD_LOGIC;
signal ram_reg_768_1023_4_4_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_4_4_n_0 : STD_LOGIC;
signal ram_reg_768_1023_5_5_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_5_5_n_0 : STD_LOGIC;
signal ram_reg_768_1023_6_6_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_6_6_n_0 : STD_LOGIC;
signal ram_reg_768_1023_7_7_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_7_7_n_0 : STD_LOGIC;
signal ram_reg_768_1023_8_8_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_8_8_n_0 : STD_LOGIC;
signal ram_reg_768_1023_9_9_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_9_9_n_0 : STD_LOGIC;
signal \^spo\ : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute KEEP : string;
attribute KEEP of \qspo_int_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \qspo_int_reg[0]\ : label is "no";
attribute KEEP of \qspo_int_reg[10]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[10]\ : label is "no";
attribute KEEP of \qspo_int_reg[11]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[11]\ : label is "no";
attribute KEEP of \qspo_int_reg[12]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[12]\ : label is "no";
attribute KEEP of \qspo_int_reg[13]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[13]\ : label is "no";
attribute KEEP of \qspo_int_reg[14]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[14]\ : label is "no";
attribute KEEP of \qspo_int_reg[15]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[15]\ : label is "no";
attribute KEEP of \qspo_int_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[1]\ : label is "no";
attribute KEEP of \qspo_int_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[2]\ : label is "no";
attribute KEEP of \qspo_int_reg[3]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[3]\ : label is "no";
attribute KEEP of \qspo_int_reg[4]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[4]\ : label is "no";
attribute KEEP of \qspo_int_reg[5]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[5]\ : label is "no";
attribute KEEP of \qspo_int_reg[6]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[6]\ : label is "no";
attribute KEEP of \qspo_int_reg[7]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[7]\ : label is "no";
attribute KEEP of \qspo_int_reg[8]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[8]\ : label is "no";
attribute KEEP of \qspo_int_reg[9]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[9]\ : label is "no";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_0_0 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_10_10 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_11_11 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_12_12 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_13_13 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_14_14 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_15_15 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_1_1 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_2_2 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_3_3 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_4_4 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_5_5 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_6_6 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_7_7 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_8_8 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_9_9 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_0_0 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_10_10 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_11_11 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_12_12 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_13_13 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_14_14 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_15_15 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_1_1 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_2_2 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_3_3 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_4_4 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_5_5 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_6_6 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_7_7 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_8_8 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_9_9 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_0_0 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_10_10 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_11_11 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_12_12 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_13_13 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_14_14 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_15_15 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_1_1 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_2_2 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_3_3 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_4_4 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_5_5 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_6_6 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_7_7 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_8_8 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_9_9 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_0_0 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_10_10 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_11_11 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_12_12 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_13_13 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_14_14 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_15_15 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_1_1 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_2_2 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_3_3 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_4_4 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_5_5 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_6_6 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_7_7 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_8_8 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_9_9 : label is "{SYNTH-5 {cell *THIS*}}";
begin
spo(15 downto 0) <= \^spo\(15 downto 0);
\qspo_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(0),
Q => qspo_int(0),
R => '0'
);
\qspo_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(10),
Q => qspo_int(10),
R => '0'
);
\qspo_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(11),
Q => qspo_int(11),
R => '0'
);
\qspo_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(12),
Q => qspo_int(12),
R => '0'
);
\qspo_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(13),
Q => qspo_int(13),
R => '0'
);
\qspo_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(14),
Q => qspo_int(14),
R => '0'
);
\qspo_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(15),
Q => qspo_int(15),
R => '0'
);
\qspo_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(1),
Q => qspo_int(1),
R => '0'
);
\qspo_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(2),
Q => qspo_int(2),
R => '0'
);
\qspo_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(3),
Q => qspo_int(3),
R => '0'
);
\qspo_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(4),
Q => qspo_int(4),
R => '0'
);
\qspo_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(5),
Q => qspo_int(5),
R => '0'
);
\qspo_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(6),
Q => qspo_int(6),
R => '0'
);
\qspo_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(7),
Q => qspo_int(7),
R => '0'
);
\qspo_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(8),
Q => qspo_int(8),
R => '0'
);
\qspo_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(9),
Q => qspo_int(9),
R => '0'
);
ram_reg_0_255_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(0),
O => ram_reg_0_255_0_0_n_0,
WCLK => clk,
WE => ram_reg_0_255_0_0_i_1_n_0
);
ram_reg_0_255_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_0_0_i_1_n_0
);
ram_reg_0_255_10_10: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(10),
O => ram_reg_0_255_10_10_n_0,
WCLK => clk,
WE => ram_reg_0_255_10_10_i_1_n_0
);
ram_reg_0_255_10_10_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_10_10_i_1_n_0
);
ram_reg_0_255_11_11: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(11),
O => ram_reg_0_255_11_11_n_0,
WCLK => clk,
WE => ram_reg_0_255_11_11_i_1_n_0
);
ram_reg_0_255_11_11_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_11_11_i_1_n_0
);
ram_reg_0_255_12_12: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(12),
O => ram_reg_0_255_12_12_n_0,
WCLK => clk,
WE => ram_reg_0_255_12_12_i_1_n_0
);
ram_reg_0_255_12_12_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_12_12_i_1_n_0
);
ram_reg_0_255_13_13: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(13),
O => ram_reg_0_255_13_13_n_0,
WCLK => clk,
WE => ram_reg_0_255_13_13_i_1_n_0
);
ram_reg_0_255_13_13_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_13_13_i_1_n_0
);
ram_reg_0_255_14_14: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(14),
O => ram_reg_0_255_14_14_n_0,
WCLK => clk,
WE => ram_reg_0_255_14_14_i_1_n_0
);
ram_reg_0_255_14_14_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_14_14_i_1_n_0
);
ram_reg_0_255_15_15: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(15),
O => ram_reg_0_255_15_15_n_0,
WCLK => clk,
WE => ram_reg_0_255_15_15_i_1_n_0
);
ram_reg_0_255_15_15_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_15_15_i_1_n_0
);
ram_reg_0_255_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(1),
O => ram_reg_0_255_1_1_n_0,
WCLK => clk,
WE => ram_reg_0_255_1_1_i_1_n_0
);
ram_reg_0_255_1_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_1_1_i_1_n_0
);
ram_reg_0_255_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(2),
O => ram_reg_0_255_2_2_n_0,
WCLK => clk,
WE => ram_reg_0_255_2_2_i_1_n_0
);
ram_reg_0_255_2_2_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_2_2_i_1_n_0
);
ram_reg_0_255_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(3),
O => ram_reg_0_255_3_3_n_0,
WCLK => clk,
WE => ram_reg_0_255_3_3_i_1_n_0
);
ram_reg_0_255_3_3_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_3_3_i_1_n_0
);
ram_reg_0_255_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(4),
O => ram_reg_0_255_4_4_n_0,
WCLK => clk,
WE => ram_reg_0_255_4_4_i_1_n_0
);
ram_reg_0_255_4_4_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_4_4_i_1_n_0
);
ram_reg_0_255_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(5),
O => ram_reg_0_255_5_5_n_0,
WCLK => clk,
WE => ram_reg_0_255_5_5_i_1_n_0
);
ram_reg_0_255_5_5_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_5_5_i_1_n_0
);
ram_reg_0_255_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(6),
O => ram_reg_0_255_6_6_n_0,
WCLK => clk,
WE => ram_reg_0_255_6_6_i_1_n_0
);
ram_reg_0_255_6_6_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_6_6_i_1_n_0
);
ram_reg_0_255_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(7),
O => ram_reg_0_255_7_7_n_0,
WCLK => clk,
WE => ram_reg_0_255_7_7_i_1_n_0
);
ram_reg_0_255_7_7_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_7_7_i_1_n_0
);
ram_reg_0_255_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(8),
O => ram_reg_0_255_8_8_n_0,
WCLK => clk,
WE => ram_reg_0_255_8_8_i_1_n_0
);
ram_reg_0_255_8_8_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_8_8_i_1_n_0
);
ram_reg_0_255_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(9),
O => ram_reg_0_255_9_9_n_0,
WCLK => clk,
WE => ram_reg_0_255_9_9_i_1_n_0
);
ram_reg_0_255_9_9_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_9_9_i_1_n_0
);
ram_reg_256_511_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(0),
O => ram_reg_256_511_0_0_n_0,
WCLK => clk,
WE => ram_reg_256_511_0_0_i_1_n_0
);
ram_reg_256_511_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_0_0_i_1_n_0
);
ram_reg_256_511_10_10: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(10),
O => ram_reg_256_511_10_10_n_0,
WCLK => clk,
WE => ram_reg_256_511_10_10_i_1_n_0
);
ram_reg_256_511_10_10_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_10_10_i_1_n_0
);
ram_reg_256_511_11_11: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(11),
O => ram_reg_256_511_11_11_n_0,
WCLK => clk,
WE => ram_reg_256_511_11_11_i_1_n_0
);
ram_reg_256_511_11_11_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_11_11_i_1_n_0
);
ram_reg_256_511_12_12: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(12),
O => ram_reg_256_511_12_12_n_0,
WCLK => clk,
WE => ram_reg_256_511_12_12_i_1_n_0
);
ram_reg_256_511_12_12_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_12_12_i_1_n_0
);
ram_reg_256_511_13_13: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(13),
O => ram_reg_256_511_13_13_n_0,
WCLK => clk,
WE => ram_reg_256_511_13_13_i_1_n_0
);
ram_reg_256_511_13_13_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_13_13_i_1_n_0
);
ram_reg_256_511_14_14: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(14),
O => ram_reg_256_511_14_14_n_0,
WCLK => clk,
WE => ram_reg_256_511_14_14_i_1_n_0
);
ram_reg_256_511_14_14_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_14_14_i_1_n_0
);
ram_reg_256_511_15_15: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(15),
O => ram_reg_256_511_15_15_n_0,
WCLK => clk,
WE => ram_reg_256_511_15_15_i_1_n_0
);
ram_reg_256_511_15_15_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_15_15_i_1_n_0
);
ram_reg_256_511_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(1),
O => ram_reg_256_511_1_1_n_0,
WCLK => clk,
WE => ram_reg_256_511_1_1_i_1_n_0
);
ram_reg_256_511_1_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_1_1_i_1_n_0
);
ram_reg_256_511_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(2),
O => ram_reg_256_511_2_2_n_0,
WCLK => clk,
WE => ram_reg_256_511_2_2_i_1_n_0
);
ram_reg_256_511_2_2_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_2_2_i_1_n_0
);
ram_reg_256_511_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(3),
O => ram_reg_256_511_3_3_n_0,
WCLK => clk,
WE => ram_reg_256_511_3_3_i_1_n_0
);
ram_reg_256_511_3_3_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_3_3_i_1_n_0
);
ram_reg_256_511_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(4),
O => ram_reg_256_511_4_4_n_0,
WCLK => clk,
WE => ram_reg_256_511_4_4_i_1_n_0
);
ram_reg_256_511_4_4_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_4_4_i_1_n_0
);
ram_reg_256_511_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(5),
O => ram_reg_256_511_5_5_n_0,
WCLK => clk,
WE => ram_reg_256_511_5_5_i_1_n_0
);
ram_reg_256_511_5_5_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_5_5_i_1_n_0
);
ram_reg_256_511_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(6),
O => ram_reg_256_511_6_6_n_0,
WCLK => clk,
WE => ram_reg_256_511_6_6_i_1_n_0
);
ram_reg_256_511_6_6_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_6_6_i_1_n_0
);
ram_reg_256_511_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(7),
O => ram_reg_256_511_7_7_n_0,
WCLK => clk,
WE => ram_reg_256_511_7_7_i_1_n_0
);
ram_reg_256_511_7_7_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_7_7_i_1_n_0
);
ram_reg_256_511_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(8),
O => ram_reg_256_511_8_8_n_0,
WCLK => clk,
WE => ram_reg_256_511_8_8_i_1_n_0
);
ram_reg_256_511_8_8_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_8_8_i_1_n_0
);
ram_reg_256_511_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(9),
O => ram_reg_256_511_9_9_n_0,
WCLK => clk,
WE => ram_reg_256_511_9_9_i_1_n_0
);
ram_reg_256_511_9_9_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_9_9_i_1_n_0
);
ram_reg_512_767_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(0),
O => ram_reg_512_767_0_0_n_0,
WCLK => clk,
WE => ram_reg_512_767_0_0_i_1_n_0
);
ram_reg_512_767_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_0_0_i_1_n_0
);
ram_reg_512_767_10_10: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(10),
O => ram_reg_512_767_10_10_n_0,
WCLK => clk,
WE => ram_reg_512_767_10_10_i_1_n_0
);
ram_reg_512_767_10_10_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_10_10_i_1_n_0
);
ram_reg_512_767_11_11: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(11),
O => ram_reg_512_767_11_11_n_0,
WCLK => clk,
WE => ram_reg_512_767_11_11_i_1_n_0
);
ram_reg_512_767_11_11_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_11_11_i_1_n_0
);
ram_reg_512_767_12_12: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(12),
O => ram_reg_512_767_12_12_n_0,
WCLK => clk,
WE => ram_reg_512_767_12_12_i_1_n_0
);
ram_reg_512_767_12_12_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_12_12_i_1_n_0
);
ram_reg_512_767_13_13: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(13),
O => ram_reg_512_767_13_13_n_0,
WCLK => clk,
WE => ram_reg_512_767_13_13_i_1_n_0
);
ram_reg_512_767_13_13_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_13_13_i_1_n_0
);
ram_reg_512_767_14_14: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(14),
O => ram_reg_512_767_14_14_n_0,
WCLK => clk,
WE => ram_reg_512_767_14_14_i_1_n_0
);
ram_reg_512_767_14_14_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_14_14_i_1_n_0
);
ram_reg_512_767_15_15: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(15),
O => ram_reg_512_767_15_15_n_0,
WCLK => clk,
WE => ram_reg_512_767_15_15_i_1_n_0
);
ram_reg_512_767_15_15_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_15_15_i_1_n_0
);
ram_reg_512_767_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(1),
O => ram_reg_512_767_1_1_n_0,
WCLK => clk,
WE => ram_reg_512_767_1_1_i_1_n_0
);
ram_reg_512_767_1_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_1_1_i_1_n_0
);
ram_reg_512_767_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(2),
O => ram_reg_512_767_2_2_n_0,
WCLK => clk,
WE => ram_reg_512_767_2_2_i_1_n_0
);
ram_reg_512_767_2_2_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_2_2_i_1_n_0
);
ram_reg_512_767_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(3),
O => ram_reg_512_767_3_3_n_0,
WCLK => clk,
WE => ram_reg_512_767_3_3_i_1_n_0
);
ram_reg_512_767_3_3_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_3_3_i_1_n_0
);
ram_reg_512_767_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(4),
O => ram_reg_512_767_4_4_n_0,
WCLK => clk,
WE => ram_reg_512_767_4_4_i_1_n_0
);
ram_reg_512_767_4_4_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_4_4_i_1_n_0
);
ram_reg_512_767_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(5),
O => ram_reg_512_767_5_5_n_0,
WCLK => clk,
WE => ram_reg_512_767_5_5_i_1_n_0
);
ram_reg_512_767_5_5_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_5_5_i_1_n_0
);
ram_reg_512_767_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(6),
O => ram_reg_512_767_6_6_n_0,
WCLK => clk,
WE => ram_reg_512_767_6_6_i_1_n_0
);
ram_reg_512_767_6_6_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_6_6_i_1_n_0
);
ram_reg_512_767_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(7),
O => ram_reg_512_767_7_7_n_0,
WCLK => clk,
WE => ram_reg_512_767_7_7_i_1_n_0
);
ram_reg_512_767_7_7_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_7_7_i_1_n_0
);
ram_reg_512_767_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(8),
O => ram_reg_512_767_8_8_n_0,
WCLK => clk,
WE => ram_reg_512_767_8_8_i_1_n_0
);
ram_reg_512_767_8_8_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_8_8_i_1_n_0
);
ram_reg_512_767_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(9),
O => ram_reg_512_767_9_9_n_0,
WCLK => clk,
WE => ram_reg_512_767_9_9_i_1_n_0
);
ram_reg_512_767_9_9_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_9_9_i_1_n_0
);
ram_reg_768_1023_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(0),
O => ram_reg_768_1023_0_0_n_0,
WCLK => clk,
WE => ram_reg_768_1023_0_0_i_1_n_0
);
ram_reg_768_1023_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_0_0_i_1_n_0
);
ram_reg_768_1023_10_10: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(10),
O => ram_reg_768_1023_10_10_n_0,
WCLK => clk,
WE => ram_reg_768_1023_10_10_i_1_n_0
);
ram_reg_768_1023_10_10_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_10_10_i_1_n_0
);
ram_reg_768_1023_11_11: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(11),
O => ram_reg_768_1023_11_11_n_0,
WCLK => clk,
WE => ram_reg_768_1023_11_11_i_1_n_0
);
ram_reg_768_1023_11_11_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_11_11_i_1_n_0
);
ram_reg_768_1023_12_12: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(12),
O => ram_reg_768_1023_12_12_n_0,
WCLK => clk,
WE => ram_reg_768_1023_12_12_i_1_n_0
);
ram_reg_768_1023_12_12_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_12_12_i_1_n_0
);
ram_reg_768_1023_13_13: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(13),
O => ram_reg_768_1023_13_13_n_0,
WCLK => clk,
WE => ram_reg_768_1023_13_13_i_1_n_0
);
ram_reg_768_1023_13_13_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_13_13_i_1_n_0
);
ram_reg_768_1023_14_14: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(14),
O => ram_reg_768_1023_14_14_n_0,
WCLK => clk,
WE => ram_reg_768_1023_14_14_i_1_n_0
);
ram_reg_768_1023_14_14_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_14_14_i_1_n_0
);
ram_reg_768_1023_15_15: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(15),
O => ram_reg_768_1023_15_15_n_0,
WCLK => clk,
WE => ram_reg_768_1023_15_15_i_1_n_0
);
ram_reg_768_1023_15_15_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_15_15_i_1_n_0
);
ram_reg_768_1023_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(1),
O => ram_reg_768_1023_1_1_n_0,
WCLK => clk,
WE => ram_reg_768_1023_1_1_i_1_n_0
);
ram_reg_768_1023_1_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_1_1_i_1_n_0
);
ram_reg_768_1023_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(2),
O => ram_reg_768_1023_2_2_n_0,
WCLK => clk,
WE => ram_reg_768_1023_2_2_i_1_n_0
);
ram_reg_768_1023_2_2_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_2_2_i_1_n_0
);
ram_reg_768_1023_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(3),
O => ram_reg_768_1023_3_3_n_0,
WCLK => clk,
WE => ram_reg_768_1023_3_3_i_1_n_0
);
ram_reg_768_1023_3_3_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_3_3_i_1_n_0
);
ram_reg_768_1023_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(4),
O => ram_reg_768_1023_4_4_n_0,
WCLK => clk,
WE => ram_reg_768_1023_4_4_i_1_n_0
);
ram_reg_768_1023_4_4_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_4_4_i_1_n_0
);
ram_reg_768_1023_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(5),
O => ram_reg_768_1023_5_5_n_0,
WCLK => clk,
WE => ram_reg_768_1023_5_5_i_1_n_0
);
ram_reg_768_1023_5_5_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_5_5_i_1_n_0
);
ram_reg_768_1023_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(6),
O => ram_reg_768_1023_6_6_n_0,
WCLK => clk,
WE => ram_reg_768_1023_6_6_i_1_n_0
);
ram_reg_768_1023_6_6_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_6_6_i_1_n_0
);
ram_reg_768_1023_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(7),
O => ram_reg_768_1023_7_7_n_0,
WCLK => clk,
WE => ram_reg_768_1023_7_7_i_1_n_0
);
ram_reg_768_1023_7_7_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_7_7_i_1_n_0
);
ram_reg_768_1023_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(8),
O => ram_reg_768_1023_8_8_n_0,
WCLK => clk,
WE => ram_reg_768_1023_8_8_i_1_n_0
);
ram_reg_768_1023_8_8_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_8_8_i_1_n_0
);
ram_reg_768_1023_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(9),
O => ram_reg_768_1023_9_9_n_0,
WCLK => clk,
WE => ram_reg_768_1023_9_9_i_1_n_0
);
ram_reg_768_1023_9_9_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_9_9_i_1_n_0
);
\spo[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_0_0_n_0,
I1 => ram_reg_512_767_0_0_n_0,
I2 => a(9),
I3 => ram_reg_256_511_0_0_n_0,
I4 => a(8),
I5 => ram_reg_0_255_0_0_n_0,
O => \^spo\(0)
);
\spo[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_10_10_n_0,
I1 => ram_reg_512_767_10_10_n_0,
I2 => a(9),
I3 => ram_reg_256_511_10_10_n_0,
I4 => a(8),
I5 => ram_reg_0_255_10_10_n_0,
O => \^spo\(10)
);
\spo[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_11_11_n_0,
I1 => ram_reg_512_767_11_11_n_0,
I2 => a(9),
I3 => ram_reg_256_511_11_11_n_0,
I4 => a(8),
I5 => ram_reg_0_255_11_11_n_0,
O => \^spo\(11)
);
\spo[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_12_12_n_0,
I1 => ram_reg_512_767_12_12_n_0,
I2 => a(9),
I3 => ram_reg_256_511_12_12_n_0,
I4 => a(8),
I5 => ram_reg_0_255_12_12_n_0,
O => \^spo\(12)
);
\spo[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_13_13_n_0,
I1 => ram_reg_512_767_13_13_n_0,
I2 => a(9),
I3 => ram_reg_256_511_13_13_n_0,
I4 => a(8),
I5 => ram_reg_0_255_13_13_n_0,
O => \^spo\(13)
);
\spo[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_14_14_n_0,
I1 => ram_reg_512_767_14_14_n_0,
I2 => a(9),
I3 => ram_reg_256_511_14_14_n_0,
I4 => a(8),
I5 => ram_reg_0_255_14_14_n_0,
O => \^spo\(14)
);
\spo[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_15_15_n_0,
I1 => ram_reg_512_767_15_15_n_0,
I2 => a(9),
I3 => ram_reg_256_511_15_15_n_0,
I4 => a(8),
I5 => ram_reg_0_255_15_15_n_0,
O => \^spo\(15)
);
\spo[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_1_1_n_0,
I1 => ram_reg_512_767_1_1_n_0,
I2 => a(9),
I3 => ram_reg_256_511_1_1_n_0,
I4 => a(8),
I5 => ram_reg_0_255_1_1_n_0,
O => \^spo\(1)
);
\spo[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_2_2_n_0,
I1 => ram_reg_512_767_2_2_n_0,
I2 => a(9),
I3 => ram_reg_256_511_2_2_n_0,
I4 => a(8),
I5 => ram_reg_0_255_2_2_n_0,
O => \^spo\(2)
);
\spo[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_3_3_n_0,
I1 => ram_reg_512_767_3_3_n_0,
I2 => a(9),
I3 => ram_reg_256_511_3_3_n_0,
I4 => a(8),
I5 => ram_reg_0_255_3_3_n_0,
O => \^spo\(3)
);
\spo[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_4_4_n_0,
I1 => ram_reg_512_767_4_4_n_0,
I2 => a(9),
I3 => ram_reg_256_511_4_4_n_0,
I4 => a(8),
I5 => ram_reg_0_255_4_4_n_0,
O => \^spo\(4)
);
\spo[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_5_5_n_0,
I1 => ram_reg_512_767_5_5_n_0,
I2 => a(9),
I3 => ram_reg_256_511_5_5_n_0,
I4 => a(8),
I5 => ram_reg_0_255_5_5_n_0,
O => \^spo\(5)
);
\spo[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_6_6_n_0,
I1 => ram_reg_512_767_6_6_n_0,
I2 => a(9),
I3 => ram_reg_256_511_6_6_n_0,
I4 => a(8),
I5 => ram_reg_0_255_6_6_n_0,
O => \^spo\(6)
);
\spo[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_7_7_n_0,
I1 => ram_reg_512_767_7_7_n_0,
I2 => a(9),
I3 => ram_reg_256_511_7_7_n_0,
I4 => a(8),
I5 => ram_reg_0_255_7_7_n_0,
O => \^spo\(7)
);
\spo[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_8_8_n_0,
I1 => ram_reg_512_767_8_8_n_0,
I2 => a(9),
I3 => ram_reg_256_511_8_8_n_0,
I4 => a(8),
I5 => ram_reg_0_255_8_8_n_0,
O => \^spo\(8)
);
\spo[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_9_9_n_0,
I1 => ram_reg_512_767_9_9_n_0,
I2 => a(9),
I3 => ram_reg_256_511_9_9_n_0,
I4 => a(8),
I5 => ram_reg_0_255_9_9_n_0,
O => \^spo\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Stack_dist_mem_gen_v8_0_9_synth is
port (
spo : out STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
we : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Stack_dist_mem_gen_v8_0_9_synth : entity is "dist_mem_gen_v8_0_9_synth";
end Stack_dist_mem_gen_v8_0_9_synth;
architecture STRUCTURE of Stack_dist_mem_gen_v8_0_9_synth is
begin
\gen_sp_ram.spram_inst\: entity work.Stack_spram
port map (
a(9 downto 0) => a(9 downto 0),
clk => clk,
d(15 downto 0) => d(15 downto 0),
spo(15 downto 0) => spo(15 downto 0),
we => we
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Stack_dist_mem_gen_v8_0_9 is
port (
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
dpra : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
we : in STD_LOGIC;
i_ce : in STD_LOGIC;
qspo_ce : in STD_LOGIC;
qdpo_ce : in STD_LOGIC;
qdpo_clk : in STD_LOGIC;
qspo_rst : in STD_LOGIC;
qdpo_rst : in STD_LOGIC;
qspo_srst : in STD_LOGIC;
qdpo_srst : in STD_LOGIC;
spo : out STD_LOGIC_VECTOR ( 15 downto 0 );
dpo : out STD_LOGIC_VECTOR ( 15 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 15 downto 0 );
qdpo : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute C_ADDR_WIDTH : integer;
attribute C_ADDR_WIDTH of Stack_dist_mem_gen_v8_0_9 : entity is 10;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of Stack_dist_mem_gen_v8_0_9 : entity is "0";
attribute C_DEPTH : integer;
attribute C_DEPTH of Stack_dist_mem_gen_v8_0_9 : entity is 1024;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of Stack_dist_mem_gen_v8_0_9 : entity is "./";
attribute C_FAMILY : string;
attribute C_FAMILY of Stack_dist_mem_gen_v8_0_9 : entity is "artix7";
attribute C_HAS_CLK : integer;
attribute C_HAS_CLK of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_HAS_D : integer;
attribute C_HAS_D of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_HAS_DPO : integer;
attribute C_HAS_DPO of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_DPRA : integer;
attribute C_HAS_DPRA of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_I_CE : integer;
attribute C_HAS_I_CE of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO : integer;
attribute C_HAS_QDPO of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_CE : integer;
attribute C_HAS_QDPO_CE of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_CLK : integer;
attribute C_HAS_QDPO_CLK of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_RST : integer;
attribute C_HAS_QDPO_RST of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_SRST : integer;
attribute C_HAS_QDPO_SRST of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO : integer;
attribute C_HAS_QSPO of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_CE : integer;
attribute C_HAS_QSPO_CE of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_RST : integer;
attribute C_HAS_QSPO_RST of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_SRST : integer;
attribute C_HAS_QSPO_SRST of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_SPO : integer;
attribute C_HAS_SPO of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_HAS_WE : integer;
attribute C_HAS_WE of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_MEM_INIT_FILE : string;
attribute C_MEM_INIT_FILE of Stack_dist_mem_gen_v8_0_9 : entity is "no_coe_file_loaded";
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_PARSER_TYPE : integer;
attribute C_PARSER_TYPE of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_PIPELINE_STAGES : integer;
attribute C_PIPELINE_STAGES of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_QCE_JOINED : integer;
attribute C_QCE_JOINED of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_QUALIFY_WE : integer;
attribute C_QUALIFY_WE of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_READ_MIF : integer;
attribute C_READ_MIF of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_REG_A_D_INPUTS : integer;
attribute C_REG_A_D_INPUTS of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_REG_DPRA_INPUT : integer;
attribute C_REG_DPRA_INPUT of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_SYNC_ENABLE : integer;
attribute C_SYNC_ENABLE of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_WIDTH : integer;
attribute C_WIDTH of Stack_dist_mem_gen_v8_0_9 : entity is 16;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Stack_dist_mem_gen_v8_0_9 : entity is "dist_mem_gen_v8_0_9";
end Stack_dist_mem_gen_v8_0_9;
architecture STRUCTURE of Stack_dist_mem_gen_v8_0_9 is
signal \<const0>\ : STD_LOGIC;
begin
dpo(15) <= \<const0>\;
dpo(14) <= \<const0>\;
dpo(13) <= \<const0>\;
dpo(12) <= \<const0>\;
dpo(11) <= \<const0>\;
dpo(10) <= \<const0>\;
dpo(9) <= \<const0>\;
dpo(8) <= \<const0>\;
dpo(7) <= \<const0>\;
dpo(6) <= \<const0>\;
dpo(5) <= \<const0>\;
dpo(4) <= \<const0>\;
dpo(3) <= \<const0>\;
dpo(2) <= \<const0>\;
dpo(1) <= \<const0>\;
dpo(0) <= \<const0>\;
qdpo(15) <= \<const0>\;
qdpo(14) <= \<const0>\;
qdpo(13) <= \<const0>\;
qdpo(12) <= \<const0>\;
qdpo(11) <= \<const0>\;
qdpo(10) <= \<const0>\;
qdpo(9) <= \<const0>\;
qdpo(8) <= \<const0>\;
qdpo(7) <= \<const0>\;
qdpo(6) <= \<const0>\;
qdpo(5) <= \<const0>\;
qdpo(4) <= \<const0>\;
qdpo(3) <= \<const0>\;
qdpo(2) <= \<const0>\;
qdpo(1) <= \<const0>\;
qdpo(0) <= \<const0>\;
qspo(15) <= \<const0>\;
qspo(14) <= \<const0>\;
qspo(13) <= \<const0>\;
qspo(12) <= \<const0>\;
qspo(11) <= \<const0>\;
qspo(10) <= \<const0>\;
qspo(9) <= \<const0>\;
qspo(8) <= \<const0>\;
qspo(7) <= \<const0>\;
qspo(6) <= \<const0>\;
qspo(5) <= \<const0>\;
qspo(4) <= \<const0>\;
qspo(3) <= \<const0>\;
qspo(2) <= \<const0>\;
qspo(1) <= \<const0>\;
qspo(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\synth_options.dist_mem_inst\: entity work.Stack_dist_mem_gen_v8_0_9_synth
port map (
a(9 downto 0) => a(9 downto 0),
clk => clk,
d(15 downto 0) => d(15 downto 0),
spo(15 downto 0) => spo(15 downto 0),
we => we
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Stack is
port (
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
we : in STD_LOGIC;
spo : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of Stack : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of Stack : entity is "Stack,dist_mem_gen_v8_0_9,{}";
attribute core_generation_info : string;
attribute core_generation_info of Stack : entity is "Stack,dist_mem_gen_v8_0_9,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=10,C_DEFAULT_DATA=0,C_DEPTH=1024,C_HAS_CLK=1,C_HAS_D=1,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=1,C_MEM_INIT_FILE=no_coe_file_loaded,C_ELABORATION_DIR=./,C_MEM_TYPE=1,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=0,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=16,C_PARSER_TYPE=1}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of Stack : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of Stack : entity is "dist_mem_gen_v8_0_9,Vivado 2015.4";
end Stack;
architecture STRUCTURE of Stack is
signal NLW_U0_dpo_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_qdpo_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_qspo_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_CLK : integer;
attribute C_HAS_CLK of U0 : label is 1;
attribute C_HAS_D : integer;
attribute C_HAS_D of U0 : label is 1;
attribute C_HAS_DPO : integer;
attribute C_HAS_DPO of U0 : label is 0;
attribute C_HAS_DPRA : integer;
attribute C_HAS_DPRA of U0 : label is 0;
attribute C_HAS_QDPO : integer;
attribute C_HAS_QDPO of U0 : label is 0;
attribute C_HAS_QDPO_CE : integer;
attribute C_HAS_QDPO_CE of U0 : label is 0;
attribute C_HAS_QDPO_CLK : integer;
attribute C_HAS_QDPO_CLK of U0 : label is 0;
attribute C_HAS_QDPO_RST : integer;
attribute C_HAS_QDPO_RST of U0 : label is 0;
attribute C_HAS_QDPO_SRST : integer;
attribute C_HAS_QDPO_SRST of U0 : label is 0;
attribute C_HAS_WE : integer;
attribute C_HAS_WE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_QCE_JOINED : integer;
attribute C_QCE_JOINED of U0 : label is 0;
attribute C_REG_DPRA_INPUT : integer;
attribute C_REG_DPRA_INPUT of U0 : label is 0;
attribute c_addr_width : integer;
attribute c_addr_width of U0 : label is 10;
attribute c_default_data : string;
attribute c_default_data of U0 : label is "0";
attribute c_depth : integer;
attribute c_depth of U0 : label is 1024;
attribute c_elaboration_dir : string;
attribute c_elaboration_dir of U0 : label is "./";
attribute c_has_i_ce : integer;
attribute c_has_i_ce of U0 : label is 0;
attribute c_has_qspo : integer;
attribute c_has_qspo of U0 : label is 0;
attribute c_has_qspo_ce : integer;
attribute c_has_qspo_ce of U0 : label is 0;
attribute c_has_qspo_rst : integer;
attribute c_has_qspo_rst of U0 : label is 0;
attribute c_has_qspo_srst : integer;
attribute c_has_qspo_srst of U0 : label is 0;
attribute c_has_spo : integer;
attribute c_has_spo of U0 : label is 1;
attribute c_mem_init_file : string;
attribute c_mem_init_file of U0 : label is "no_coe_file_loaded";
attribute c_parser_type : integer;
attribute c_parser_type of U0 : label is 1;
attribute c_pipeline_stages : integer;
attribute c_pipeline_stages of U0 : label is 0;
attribute c_qualify_we : integer;
attribute c_qualify_we of U0 : label is 0;
attribute c_read_mif : integer;
attribute c_read_mif of U0 : label is 0;
attribute c_reg_a_d_inputs : integer;
attribute c_reg_a_d_inputs of U0 : label is 0;
attribute c_sync_enable : integer;
attribute c_sync_enable of U0 : label is 1;
attribute c_width : integer;
attribute c_width of U0 : label is 16;
begin
U0: entity work.Stack_dist_mem_gen_v8_0_9
port map (
a(9 downto 0) => a(9 downto 0),
clk => clk,
d(15 downto 0) => d(15 downto 0),
dpo(15 downto 0) => NLW_U0_dpo_UNCONNECTED(15 downto 0),
dpra(9 downto 0) => B"0000000000",
i_ce => '1',
qdpo(15 downto 0) => NLW_U0_qdpo_UNCONNECTED(15 downto 0),
qdpo_ce => '1',
qdpo_clk => '0',
qdpo_rst => '0',
qdpo_srst => '0',
qspo(15 downto 0) => NLW_U0_qspo_UNCONNECTED(15 downto 0),
qspo_ce => '1',
qspo_rst => '0',
qspo_srst => '0',
spo(15 downto 0) => spo(15 downto 0),
we => we
);
end STRUCTURE;
|
mit
|
5a22f58beda0bbc4bb25d6d636c271c8
| 0.567678 | 2.723682 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/imports/Downloads/ps2_keyboard_to_ascii.vhd
| 2 | 16,293 |
--------------------------------------------------------------------------------
--
-- filename: ps2_keyboard_to_ascii.vhd
-- dependencies: ps2_keyboard.vhd, debounce.vhd
-- design software: quartus ii 32-bit version 12.1 build 177 sj full version
--
-- hdl code is provided "as is." digi-key expressly disclaims any
-- warranty of any kind, whether express or implied, including but not
-- limited to, the implied warranties of merchantability, fitness for a
-- particular purpose, or non-infringement. in no event shall digi-key
-- be liable for any incidental, special, indirect or consequential
-- damages, lost profits or lost data, harm to your equipment, cost of
-- procurement of substitute goods, technology or services, any claims
-- by third parties (including but not limited to any defense thereof),
-- any claims for indemnity or contribution, or other similar costs.
--
-- version history
-- version 1.0 11/29/2013 scott larson
-- initial public release
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ps2_keyboard_to_ascii is
generic
(
clk_freq : integer := 100_000_000 --system clock frequency in hz
);
port
(
clk : in std_logic; --system clock input
ps2_clk : in std_logic; --clock signal from ps2 keyboard
ps2_data : in std_logic; --data signal from ps2 keyboard
ascii_new : out std_logic; --output flag indicating new ascii value
ascii_code : out std_logic_vector(6 downto 0) --ascii value
);
end ps2_keyboard_to_ascii;
architecture behavior of ps2_keyboard_to_ascii is
type machine is(ready, new_code, translate, output); --needed states
signal state : machine; --state machine
signal ps2_code_new : std_logic; --new ps2 code flag from ps2_keyboard component
signal ps2_code : std_logic_vector(7 downto 0); --ps2 code input form ps2_keyboard component
signal prev_ps2_code_new : std_logic := '1'; --value of ps2_code_new flag on previous clock
signal break : std_logic := '0'; --'1' for break code, '0' for make code
signal e0_code : std_logic := '0'; --'1' for multi-code commands, '0' for single code commands
signal caps_lock : std_logic := '0'; --'1' if caps lock is active, '0' if caps lock is inactive
signal control_r : std_logic := '0'; --'1' if right control key is held down, else '0'
signal control_l : std_logic := '0'; --'1' if left control key is held down, else '0'
signal shift_r : std_logic := '0'; --'1' if right shift is held down, else '0'
signal shift_l : std_logic := '0'; --'1' if left shift is held down, else '0'
signal ascii : std_logic_vector(7 downto 0) := x"ff"; --internal value of ascii translation
--declare ps2 keyboard interface component
component ps2_keyboard is
generic(
clk_freq : integer --system clock frequency in hz
);
port(
clk : in std_logic; --system clock
ps2_clk : in std_logic; --clock signal from ps2 keyboard
ps2_data : in std_logic; --data signal from ps2 keyboard
ps2_code_new : out std_logic; --flag that new ps/2 code is available on ps2_code bus
ps2_code : out std_logic_vector(7 downto 0)); --code received from ps/2
end component;
begin
--instantiate ps2 keyboard interface logic
ps2_keyboard_0: ps2_keyboard
generic map(clk_freq => clk_freq)
port map(clk => clk, ps2_clk => ps2_clk, ps2_data => ps2_data, ps2_code_new => ps2_code_new, ps2_code => ps2_code);
process(clk)
begin
if(clk'event and clk = '1') then
prev_ps2_code_new <= ps2_code_new; --keep track of previous ps2_code_new values to determine low-to-high transitions
case state is
--ready state: wait for a new ps2 code to be received
when ready =>
ascii_new <= '0';
if(prev_ps2_code_new = '0' and ps2_code_new = '1') then --new ps2 code received
--reset new ascii code indicator
state <= new_code; --proceed to new_code state
else --no new ps2 code received yet
state <= ready; --remain in ready state
end if;
--new_code state: determine what to do with the new ps2 code
when new_code =>
ascii_new <= '0';
if(ps2_code = x"f0") then --code indicates that next command is break
break <= '1'; --set break flag
state <= ready; --return to ready state to await next ps2 code
elsif(ps2_code = x"e0") then --code indicates multi-key command
e0_code <= '1'; --set multi-code command flag
state <= ready; --return to ready state to await next ps2 code
else --code is the last ps2 code in the make/break code
ascii(7) <= '1'; --set internal ascii value to unsupported code (for verification)
state <= translate; --proceed to translate state
end if;
--translate state: translate ps2 code to ascii value
when translate =>
ascii_new <= '0';
break <= '0'; --reset break flag
e0_code <= '0'; --reset multi-code command flag
--handle codes for control, shift, and caps lock
case ps2_code is
when x"58" => --caps lock code
if(break = '0') then --if make command
caps_lock <= not caps_lock; --toggle caps lock
end if;
when x"14" => --code for the control keys
if(e0_code = '1') then --code for right control
control_r <= not break; --update right control flag
else --code for left control
control_l <= not break; --update left control flag
end if;
when x"12" => --left shift code
shift_l <= not break; --update left shift flag
when x"59" => --right shift code
shift_r <= not break; --update right shift flag
when others => null;
end case;
if(control_l = '0' and control_r = '0') then
--translate characters that do not depend on shift, or caps lock
if(e0_code = '1') then
-- Multi keys
case ps2_code is
when x"71" => ascii <= x"7f"; --delete
when x"75" => ascii <= x"01"; --up
when x"72" => ascii <= x"02"; --down
when x"6b" => ascii <= x"03"; --left
when x"74" => ascii <= x"04"; --right
-- Keypad controls
when x"a4" => ascii <= x"2f"; --/
when x"5a" => ascii <= x"0d"; --enter
when others => null;
end case;
else
-- Single characters
case ps2_code is
when x"7e" => ascii <= x"00"; --null character, for scroll lock
when x"29" => ascii <= x"20"; --space
when x"66" => ascii <= x"08"; --backspace (bs control code)
when x"0d" => ascii <= x"09"; --tab (ht control code)
when x"5a" => ascii <= x"0d"; --enter (cr control code)
when x"76" => ascii <= x"1b"; --escape (esc control code)
when x"05" => ascii <= x"0e"; --F1
when x"06" => ascii <= x"0f"; --F2
when x"04" => ascii <= x"10"; --F3
when x"0c" => ascii <= x"11"; --F4
when x"03" => ascii <= x"12"; --F5
when x"0b" => ascii <= x"13"; --F6
when x"83" => ascii <= x"14"; --F7
when x"0a" => ascii <= x"15"; --F8
when x"01" => ascii <= x"16"; --F9
when x"09" => ascii <= x"17"; --F10
when x"78" => ascii <= x"18"; --F11
when x"07" => ascii <= x"19"; --F12
-- Keypad controls
when x"70" => ascii <= x"30"; --0
when x"69" => ascii <= x"31"; --1
when x"72" => ascii <= x"32"; --2
when x"7a" => ascii <= x"33"; --3
when x"6b" => ascii <= x"34"; --4
when x"73" => ascii <= x"35"; --5
when x"74" => ascii <= x"36"; --6
when x"6c" => ascii <= x"37"; --7
when x"75" => ascii <= x"38"; --8
when x"7d" => ascii <= x"39"; --9
when x"7c" => ascii <= x"2a"; --*
when x"7b" => ascii <= x"2d"; ---
when x"79" => ascii <= x"2b"; --+
when others => null;
end case;
end if;
--translate letters (these depend on both shift and caps lock)
if ((shift_r = '0' and shift_l = '0' and caps_lock = '0') or ((shift_r = '1' or shift_l = '1') and caps_lock = '1')) then
--letter is lowercase
case ps2_code is
when x"1c" => ascii <= x"61"; --a
when x"32" => ascii <= x"62"; --b
when x"21" => ascii <= x"63"; --c
when x"23" => ascii <= x"64"; --d
when x"24" => ascii <= x"65"; --e
when x"2b" => ascii <= x"66"; --f
when x"34" => ascii <= x"67"; --g
when x"33" => ascii <= x"68"; --h
when x"43" => ascii <= x"69"; --i
when x"3b" => ascii <= x"6a"; --j
when x"42" => ascii <= x"6b"; --k
when x"4b" => ascii <= x"6c"; --l
when x"3a" => ascii <= x"6d"; --m
when x"31" => ascii <= x"6e"; --n
when x"44" => ascii <= x"6f"; --o
when x"4d" => ascii <= x"70"; --p
when x"15" => ascii <= x"71"; --q
when x"2d" => ascii <= x"72"; --r
when x"1b" => ascii <= x"73"; --s
when x"2c" => ascii <= x"74"; --t
when x"3c" => ascii <= x"75"; --u
when x"2a" => ascii <= x"76"; --v
when x"1d" => ascii <= x"77"; --w
when x"22" => ascii <= x"78"; --x
when x"35" => ascii <= x"79"; --y
when x"1a" => ascii <= x"7a"; --z
when x"45" => ascii <= x"30"; --0
when x"16" => ascii <= x"31"; --1
when x"1e" => ascii <= x"32"; --2
when x"26" => ascii <= x"33"; --3
when x"25" => ascii <= x"34"; --4
when x"2e" => ascii <= x"35"; --5
when x"36" => ascii <= x"36"; --6
when x"3d" => ascii <= x"37"; --7
when x"3e" => ascii <= x"38"; --8
when x"46" => ascii <= x"39"; --9
when x"52" => ascii <= x"27"; --'
when x"41" => ascii <= x"2c"; --,
when x"4e" => ascii <= x"2d"; ---
when x"49" => ascii <= x"2e"; --.
when x"4a" => ascii <= x"2f"; --/
when x"4c" => ascii <= x"3b"; --;
when x"55" => ascii <= x"3d"; --=
when x"54" => ascii <= x"5b"; --[
when x"5d" => ascii <= x"5c"; --\
when x"5b" => ascii <= x"5d"; --]
when x"0e" => ascii <= x"60"; --`
when others => null;
end case;
else
--letter is uppercase
case ps2_code is
when x"1c" => ascii <= x"41"; --a
when x"32" => ascii <= x"42"; --b
when x"21" => ascii <= x"43"; --c
when x"23" => ascii <= x"44"; --d
when x"24" => ascii <= x"45"; --e
when x"2b" => ascii <= x"46"; --f
when x"34" => ascii <= x"47"; --g
when x"33" => ascii <= x"48"; --h
when x"43" => ascii <= x"49"; --i
when x"3b" => ascii <= x"4a"; --j
when x"42" => ascii <= x"4b"; --k
when x"4b" => ascii <= x"4c"; --l
when x"3a" => ascii <= x"4d"; --m
when x"31" => ascii <= x"4e"; --n
when x"44" => ascii <= x"4f"; --o
when x"4d" => ascii <= x"50"; --p
when x"15" => ascii <= x"51"; --q
when x"2d" => ascii <= x"52"; --r
when x"1b" => ascii <= x"53"; --s
when x"2c" => ascii <= x"54"; --t
when x"3c" => ascii <= x"55"; --u
when x"2a" => ascii <= x"56"; --v
when x"1d" => ascii <= x"57"; --w
when x"22" => ascii <= x"58"; --x
when x"35" => ascii <= x"59"; --y
when x"1a" => ascii <= x"5a"; --z
when x"16" => ascii <= x"21"; --!
when x"52" => ascii <= x"22"; --"
when x"26" => ascii <= x"23"; --#
when x"25" => ascii <= x"24"; --$
when x"2e" => ascii <= x"25"; --%
when x"3d" => ascii <= x"26"; --&
when x"46" => ascii <= x"28"; --(
when x"45" => ascii <= x"29"; --)
when x"3e" => ascii <= x"2a"; --*
when x"55" => ascii <= x"2b"; --+
when x"4c" => ascii <= x"3a"; --:
when x"41" => ascii <= x"3c"; --<
when x"49" => ascii <= x"3e"; -->
when x"4a" => ascii <= x"3f"; --?
when x"1e" => ascii <= x"40"; --@
when x"36" => ascii <= x"5e"; --^
when x"4e" => ascii <= x"5f"; --_
when x"54" => ascii <= x"7b"; --{
when x"5d" => ascii <= x"7c"; --|
when x"5b" => ascii <= x"7d"; --}
when x"0e" => ascii <= x"7e"; --~
when others => null;
end case;
end if;
end if;
if (break = '0') then --the code is a make
state <= output; --proceed to output state
else --code is a break
state <= ready; --return to ready state to await next ps2 code
end if;
--output state: verify the code is valid and output the ascii value
when output =>
if ascii(7) = '0' then --the ps2 code has an ascii output
ascii_new <= '1'; --set flag indicating new ascii output
ascii_code <= ascii(6 downto 0); --output the ascii value
else
ascii_new <= '0';
end if;
state <= ready; --return to ready state to await next ps2 code
end case;
end if;
end process;
end behavior;
|
mit
|
1a755e09da010a0d24187bcbc98e7343
| 0.412079 | 3.959417 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/uart_async_tx.vhd
| 1 | 3,887 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_async_tx is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baud_tick_i: in std_logic;
txd_o : out std_logic;
tx_start_p_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_busy_o : out std_logic
);
end uart_async_tx;
architecture behavioral of uart_async_tx is
signal BaudTick : std_logic;
signal TxD_busy : std_logic;
signal TxD_ready : std_logic;
signal state : std_logic_vector(3 downto 0);
signal TxD_dataReg : std_logic_vector(7 downto 0);
signal TxD_dataD : std_logic_vector(7 downto 0);
signal muxbit : std_logic;
signal TxD : std_logic;
begin -- behavioral
TxD_ready <= '1' when state = "0000" else '0';
TxD_busy <= not TxD_ready;
BaudTick <= baud_tick_i;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
TxD_dataReg <= (others => '0');
elsif TxD_ready = '1' and tx_start_p_i = '1' then
TxD_dataReg <= tx_data_i;
end if;
end if;
end process;
TxD_dataD <= TxD_dataReg;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= "0000";
else
case state is
when "0000" =>
if (tx_start_p_i = '1') then
state <= "0001";
end if;
when "0001" =>
if (BaudTick = '1') then
state <= "0100";
end if;
when "0100" =>
if (BaudTick = '1') then
state <= "1000";
end if;
when "1000" =>
if (BaudTick = '1') then
state <= "1001";
end if;
when "1001" =>
if (BaudTick = '1') then
state <= "1010";
end if;
when "1010" =>
if (BaudTick = '1') then
state <= "1011";
end if;
when "1011" =>
if (BaudTick = '1') then
state <= "1100";
end if;
when "1100" =>
if (BaudTick = '1') then
state <= "1101";
end if;
when "1101" =>
if (BaudTick = '1') then
state <= "1110";
end if;
when "1110" =>
if (BaudTick = '1') then
state <= "1111";
end if;
when "1111" =>
if (BaudTick = '1') then
state <= "0010";
end if;
when "0010" =>
if (BaudTick = '1') then
state <= "0011";
end if;
when "0011" =>
if (BaudTick = '1') then
state <= "0000";
end if;
when others =>
state <= "0000";
end case;
end if;
end if;
end process;
process(TxD_dataD, state)
begin
case state(2 downto 0) is
when "000" => muxbit <= TxD_dataD(0);
when "001" => muxbit <= TxD_dataD(1);
when "010" => muxbit <= TxD_dataD(2);
when "011" => muxbit <= TxD_dataD(3);
when "100" => muxbit <= TxD_dataD(4);
when "101" => muxbit <= TxD_dataD(5);
when "110" => muxbit <= TxD_dataD(6);
when "111" => muxbit <= TxD_dataD(7);
when others => null;
end case;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
TxD <= '0';
else
if(unsigned(state) < to_unsigned(4, state'length) or (state(3) = '1' and muxbit = '1')) then
TxD <= '1';
else
TxD <= '0';
end if;
end if;
end if;
end process;
txd_o <= TxD;
tx_busy_o <= TxD_busy;
end behavioral;
|
lgpl-3.0
|
0e6690f7bbe31c1843c41ade8539665b
| 0.455107 | 3.501802 | false | false | false | false |
luebbers/reconos
|
core/pcores/burst_ram_v2_01_a/hdl/vhdl/burst_ram.vhd
| 1 | 11,188 |
--
-- \file burst_ram.vhd
--
-- Highly parametrizable local RAM block for hardware threads
--
-- Port A is thread-side, port AX is optional thread-side, port b is osif-side.
-- If configured for two thread-side ports, each port will access one half of
-- the total burst RAM.
--
-- Possible combinations of generics:
--
-- G_PORTA_DWIDTH = 32 (fixed)
-- G_PORTB_DWIDTH = 64 (fixed)
--
-- G_PORTA_PORTS | G_PORTA_AWIDTH | G_PORTB_AWIDTH | size
-- ---------------+----------------+----------------+-----
-- 1 | 10 | 9 | 4kB
-- 1 | 11 | 10 | 8kB
-- 1 | 12 | 11 | 16kB
-- 1 | 13 | 12 | 32kB
-- 1 | 14 | 13 | 64kB
-- 2 | 10 | 10 | 8kB
-- 2 | 11 | 11 | 16kB
-- 2 | 12 | 12 | 32kB
-- 2 | 13 | 13 | 64kB
--
-- \author Enno Luebbers <[email protected]>
-- \date 08.05.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library reconos_v1_02_a;
--use reconos_v1_02_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity burst_ram is
generic (
-- address and data widths, THREAD-side and OSIF-side
G_PORTA_AWIDTH : integer := 10;
G_PORTA_DWIDTH : integer := 32; -- this is fixed!
G_PORTA_PORTS : integer := 2;
G_PORTB_AWIDTH : integer := 10;
G_PORTB_DWIDTH : integer := 64; -- this is fixed!
G_PORTB_USE_BE : integer := 0 -- use byte-enable on Port B
);
port (
-- A is thread-side, AX is secondary thread-side, B is OSIF-side
addra : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
addrax: in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
addrb : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
clka : in std_logic;
clkax : in std_logic;
clkb : in std_logic;
dina : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0); -- these widths are fixed
dinax : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
dinb : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
douta : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
doutax: out std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
doutb : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
wea : in std_logic;
weax : in std_logic;
web : in std_logic;
ena : in std_logic;
enax : in std_logic;
enb : in std_logic;
beb : in std_logic_vector(G_PORTB_DWIDTH/8-1 downto 0)
);
end burst_ram;
architecture Behavioral of burst_ram is
--== DERIVED CONSTANTS ==--
-- RAM size derived from Port A
constant C_PORTA_SIZE_BYTES : natural := 2**G_PORTA_AWIDTH * (G_PORTA_DWIDTH/8) * G_PORTA_PORTS;
-- RAM size derived from Port B
constant C_PORTB_SIZE_BYTES : natural := 2**G_PORTB_AWIDTH * (G_PORTB_DWIDTH/8);
constant C_RAM_SIZE_KB : natural := C_PORTA_SIZE_BYTES / 1024;
-- constant C_OSIF_AWIDTH : natural := log2(C_RAM_SIZE_BYTES);
-- constant C_THREAD_AWIDTH : natural := C_OSIF_AWIDTH - 2 - log2(G_THREAD_PORTS);
-- number of BRAM blocks
constant C_NUM_BRAMS : natural := C_RAM_SIZE_KB / 2;
-- thread-side data width of a single BRAM block
constant C_PORTA_BRAM_DWIDTH : natural := G_PORTA_DWIDTH * G_PORTA_PORTS / C_NUM_BRAMS;
constant C_PORTB_BRAM_DWIDTH : natural := C_PORTA_BRAM_DWIDTH * 2;
-- ratio of data widths
constant C_BRAM_DWIDTH_RATIO : natural := C_PORTB_BRAM_DWIDTH / C_PORTA_BRAM_DWIDTH; -- always 2
-- RAM primitive component declaration
component ram_single is
generic (
-- address and data widths, THREAD-side and OSIF-side
G_PORTA_AWIDTH : integer := 10;
G_PORTA_DWIDTH : integer := 32; -- this is fixed!
G_PORTB_AWIDTH : integer := 10;
G_PORTB_DWIDTH : integer := 64; -- this is fixed!
G_PORTB_USE_BE : integer := 0 -- use byte-enable on Port B
);
port (
-- A is thread-side, AX is secondary thread-side, B is OSIF-side
addra : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
addrb : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
clka : in std_logic;
clkb : in std_logic;
dina : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0); -- these widths are fixed
dinb : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
douta : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
doutb : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
wea : in std_logic;
web : in std_logic;
ena : in std_logic;
enb : in std_logic;
beb : in std_logic_vector(G_PORTB_DWIDTH/8-1 downto 0)
);
end component;
type mux_vec_array_t is array (G_PORTA_PORTS-1 downto 0) of std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
-- helper signals for PORTB multiplexer
signal sel : std_logic;
signal doutb_tmp : mux_vec_array_t;
signal web_tmp : std_logic_vector(G_PORTA_PORTS-1 downto 0); -- 1 is upper RAM (lower addresses)
-- 0 is lower RAM (higher addresses)
begin
-- check generics for feasibility
assert G_PORTA_DWIDTH = 32
report "thread-side (PORTA) data width must be 32"
severity failure;
assert G_PORTB_DWIDTH = 64
report "OSIF-side (PORTB) data width must be 64"
severity failure;
-- this will not catch two-port/14 bit, which is not supported)
assert (G_PORTA_AWIDTH >= 10) and (G_PORTA_AWIDTH <= 14)
report "PORTA must have address width between 10 and 14 bits"
severity failure;
-- this will not catch two-port/9 bit, which is not supported)
assert (G_PORTB_AWIDTH >= 9) and (G_PORTA_AWIDTH <= 13)
report "PORTB must have address width between 9 and 13 bits"
severity failure;
assert (G_PORTA_PORTS <= 2) and (G_PORTA_PORTS > 0)
report "only one or two thread-side (PORTA) ports supported"
severity failure;
assert C_PORTA_SIZE_BYTES = C_PORTB_SIZE_BYTES
report "combination of data and address widths impossible"
severity failure;
assert (G_PORTB_USE_BE = 0) or (C_PORTB_BRAM_DWIDTH <= 8)
report "port B byte enables cannot be used with this memory size"
severity failure;
------------------------ SINGLE PORT ---------------------------------------------
single_port: if G_PORTA_PORTS = 1 generate -- one thread-side port => no multiplexers
ram_inst: ram_single
generic map (
G_PORTA_AWIDTH => G_PORTA_AWIDTH,
G_PORTA_DWIDTH => G_PORTA_DWIDTH,
G_PORTB_AWIDTH => G_PORTB_AWIDTH,
G_PORTB_DWIDTH => G_PORTB_DWIDTH,
G_PORTB_USE_BE => G_PORTB_USE_BE
)
port map (
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
doutb => doutb,
wea => wea,
web => web,
ena => ena,
enb => enb,
beb => beb
);
doutax <= (others => '0');
end generate; -- single_port
------------------------ MULTI PORT ---------------------------------------------
multi_ports: if G_PORTA_PORTS = 2 generate
-- assert false report "multiple ports not yet implemented!" severity failure;
-- PORTA RAM
ram_porta: ram_single
generic map (
G_PORTA_AWIDTH => G_PORTA_AWIDTH,
G_PORTA_DWIDTH => G_PORTA_DWIDTH,
G_PORTB_AWIDTH => G_PORTB_AWIDTH-1,
G_PORTB_DWIDTH => G_PORTB_DWIDTH,
G_PORTB_USE_BE => G_PORTB_USE_BE
)
port map (
addra => addra,
addrb => addrb(G_PORTB_AWIDTH-2 downto 0),
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
doutb => doutb_tmp(1),
wea => wea,
web => web_tmp(1),
ena => ena,
enb => enb,
beb => beb
);
-- PORTAX RAM
ram_portax: ram_single
generic map (
G_PORTA_AWIDTH => G_PORTA_AWIDTH,
G_PORTA_DWIDTH => G_PORTA_DWIDTH,
G_PORTB_AWIDTH => G_PORTB_AWIDTH-1,
G_PORTB_DWIDTH => G_PORTB_DWIDTH,
G_PORTB_USE_BE => G_PORTB_USE_BE
)
port map (
addra => addrax,
addrb => addrb(G_PORTB_AWIDTH-2 downto 0),
clka => clkax,
clkb => clkb,
dina => dinax,
dinb => dinb,
douta => doutax,
doutb => doutb_tmp(0),
wea => weax,
web => web_tmp(0),
ena => enax,
enb => enb,
beb => beb
);
-- multiplexer
sel <= addrb(G_PORTB_AWIDTH-1);
doutb <= doutb_tmp(1) when sel = '0' else doutb_tmp(0);
web_tmp(1 downto 0) <= (web and not sel) & (web and sel);
end generate;
end Behavioral;
|
gpl-3.0
|
048e812db7de1eefff7d9cf7814f797f
| 0.506167 | 3.886072 | false | false | false | false |
BenBoZ/realtimestagram
|
src/lomo_tb.vhd
| 2 | 6,699 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity lomo_tb is
generic (
input_file: string := "tst/input/amersfoort.pnm"; --! Input file of test
output_file: string := "tst/output/lomo_output.pnm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight --! Height of input image
);
end entity;
--======================================================================================--
architecture structural of lomo_tb is
--===================component declaration===================--
component test_bench_driver_color is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 4
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
red_pixel_from_file: out std_logic_vector;
green_pixel_from_file: out std_logic_vector;
blue_pixel_from_file: out std_logic_vector;
red_pixel_to_file: in std_logic_vector;
green_pixel_to_file: in std_logic_vector;
blue_pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component lomo is
generic (
wordsize: integer := wordsize; --! input image wordsize in bits
image_width: integer := image_width; --! width of input image
image_height: integer := image_height --! height of input image
);
port (
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
--! x-coordinate of input pixel
h_count: in std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0);
--! y-coordinate of input pixel
v_count: in std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0);
pixel_red_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_red_o: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_o: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_o: out std_logic_vector((wordsize-1) downto 0) --! the input pixel
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal red_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal red_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver_color
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
red_pixel_from_file => red_pixel_from_file,
green_pixel_from_file => green_pixel_from_file,
blue_pixel_from_file => blue_pixel_from_file,
red_pixel_to_file => red_pixel_to_file,
green_pixel_to_file => green_pixel_to_file,
blue_pixel_to_file => blue_pixel_to_file
);
device_under_test: lomo
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
pixel_red_i => red_pixel_from_file,
pixel_green_i => green_pixel_from_file,
pixel_blue_i => blue_pixel_from_file,
pixel_red_o => red_pixel_to_file,
pixel_green_o => green_pixel_to_file,
pixel_blue_o => blue_pixel_to_file
);
end architecture;
|
gpl-2.0
|
931e68fa49c473d3d9b740efcc660d1e
| 0.503956 | 4.179039 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/generic_dpram_sameclock.vhd
| 1 | 7,159 |
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram_sameclock.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-09
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram_sameclock is
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clk_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram_sameclock;
architecture syn of generic_dpram_sameclock is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
function f_memarray_to_ramtype(arr : t_meminit_array) return t_ram_type is
variable tmp : t_ram_type;
variable n, pos : integer;
begin
pos := 0;
while(pos < g_size)loop
n := 0;
-- avoid ISE loop iteration limit
while (pos < g_size and n < 4096) loop
for i in 0 to g_data_width-1 loop
tmp(pos)(i) := arr(pos, i);
end loop; -- i
n := n+1;
pos := pos + 1;
end loop;
end loop;
return tmp;
end f_memarray_to_ramtype;
function f_file_contents return t_meminit_array is
begin
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
function f_check_bounds(x : integer; minx : integer; maxx : integer) return integer is
begin
if(x < minx) then
return minx;
elsif(x > maxx) then
return maxx;
else
return x;
end if;
end f_check_bounds;
begin
wea_rep <= (others => wea_i);
web_rep <= (others => web_i);
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process (clk_i)
begin
if rising_edge(clk_i) then
qa_o <= ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
qb_o <= ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
for i in 0 to c_num_bytes-1 loop
if s_we_a(i) = '1' then
ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
end if;
if(s_we_b(i) = '1') then
ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clk_i)
begin
if rising_edge(clk_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
qb_o <= ram(to_integer(unsigned(ab_i)));
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
end if;
end if;
end process;
end generate gen_without_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
qa_o <= da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
qb_o <= db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_nochange;
end syn;
|
lgpl-3.0
|
7ea741d394be5424c131018fbda56999
| 0.541277 | 3.323584 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/dcr_v29_v9_00_a/hdl/vhdl/dcr_v29.vhd
| 7 | 12,890 |
-------------------------------------------------------------------------------
-- $Id: dcr_v29.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- dcr_v29.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dcr_v29.vhd
-- Version: v1.00b
-- Description: IBM DCR (Device Control Register) Bus implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- dcr_v29.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 4-18-02 First Version
-- ALS 4-29-02
-- ALS 4-01-03 Put in work-around for 1 DCR Slave problem with
-- NGDBUILD
-- GAB 10-05-09 Removed reference to proc_common_v1_00_b and pulled
-- or_gate and or_muxcy into this dcr library.
-- Updated copyright header
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- Removed 10/5/09
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.all;
library dcr_v29_v9_00_a;
use dcr_v29_v9_00_a.all;
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DCR_NUM_SLAVES -- number of DCR slaves
-- C_DCR_DWIDTH -- width of DCR data bus
-- C_DCR_AWIDTH -- width of DCR address bus
-- C_USE_LUT_OR -- use LUTs to implement BUS ORs instead
-- -- of carry-chain implementation
--
-- Definition of Ports:
-- -- Master interface
-- M_dcrABus -- master dcr address bus output
-- M_dcrDBus -- master dcr data bus output
-- M_dcrRead -- master dcr read output
-- M_dcrWrite -- master dcr write output
-- DCR_M_DBus -- master dcr data bus input
-- DCR_Ack -- master dcr ack input
--
-- -- Slave interface
-- -- Note: All slave signals are concatenated together to form a
-- -- single bus. A particular slave's connection must be indexed
-- -- into the bus
-- DCR_ABus -- slave address bus input
-- DCR_Sl_DBus -- slave data bus input
-- DCR_Read -- slave dcr read input
-- DCR_Write -- slave dcr write input
-- Sl_dcrDBus -- slave data bus output
-- Sl_dcrAck -- slave dcr ack output
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity dcr_v29 is
generic (
C_DCR_NUM_SLAVES : integer := 4;
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_USE_LUT_OR : integer := 1
);
port (
-- Master outputs
M_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
M_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
M_dcrRead : in std_logic;
M_dcrWrite : in std_logic;
-- Master inputs
DCR_M_DBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Ack : out std_logic;
-- Slave inputs
DCR_ABus : out std_logic_vector(0 to C_DCR_AWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Sl_DBus : out std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Read : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
DCR_Write : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
-- slave outputs
Sl_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
Sl_dcrAck : in std_logic_vector(0 to C_DCR_NUM_SLAVES-1)
);
end entity dcr_v29;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of dcr_v29 is
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
-- internal version of DCR_Ack
signal m_dcrack_i : std_logic_vector(0 to 0);
-- dummy signal for NGDBUILD workaround which requires at least one component
-- in the NGC file when C_DCR_NUM_SLAVES=1
signal dummy : std_logic;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- Replaced with direct instantiation 10/5/09
--component or_gate is
-- generic (
-- C_OR_WIDTH : natural range 1 to 32;
-- C_BUS_WIDTH : natural range 1 to 64;
-- C_USE_LUT_OR : boolean := TRUE
-- );
-- port (
-- A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
-- Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
-- );
--end component or_gate;
-- dummy buffer for NGDBUILD workaround
component BUF
port (
O : out std_logic;
I : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin -- architecture imp
-----------------------------------------------------------------------------
-- Instantiation of Dummy buffer to get through NGDBUILD
-----------------------------------------------------------------------------
DUMMY_BUF_I: BUF
port map (O => dummy,
I => '1'
);
-----------------------------------------------------------------------------
-- Send the Master's Address bus and read/write signals to the slaves
-----------------------------------------------------------------------------
ABUS_RW_GEN: for i in 0 to C_DCR_NUM_SLAVES-1 generate
DCR_Read(i) <= M_dcrRead;
DCR_Write(i) <= M_dcrWrite;
DCR_ABus(i*C_DCR_AWIDTH to i*C_DCR_AWIDTH+C_DCR_AWIDTH-1) <= M_dcrABus;
end generate ABUS_RW_GEN;
-----------------------------------------------------------------------------
-- Daisy chain the DCR Data bus from the Master to Slave 0, then Slave 1, etc.
-- and then back to the Master
-----------------------------------------------------------------------------
DCR_Sl_DBus(0 to C_DCR_DWIDTH-1) <= M_dcrDBus;
DBUS_DCHAIN: for i in 1 to C_DCR_NUM_SLAVES-1 generate
DCR_Sl_DBus(i*C_DCR_DWIDTH to i*C_DCR_DWIDTH+C_DCR_DWIDTH-1)
<= Sl_dcrDBus((i-1)*C_DCR_DWIDTH to (i-1)*C_DCR_DWIDTH+C_DCR_DWIDTH-1);
end generate;
DCR_M_DBus <= Sl_dcrDBus((C_DCR_NUM_SLAVES-1)*C_DCR_DWIDTH to
(C_DCR_NUM_SLAVES-1)*C_DCR_DWIDTH+C_DCR_DWIDTH-1);
-----------------------------------------------------------------------------
-- OR the slave's dcrAck signals to generate the Master's dcrAck input
-----------------------------------------------------------------------------
M_DCRACK_OR_I: entity dcr_v29_v9_00_a.or_gate
generic map ( C_OR_WIDTH => C_DCR_NUM_SLAVES,
C_BUS_WIDTH => 1,
C_USE_LUT_OR => C_USE_LUT_OR /= 0
)
port map (
A => Sl_dcrAck,
Y => m_dcrack_i
);
DCR_Ack <= m_dcrack_i(0);
end imp;
|
gpl-3.0
|
ef015d16b7a0331e03726272f73fca12
| 0.416524 | 4.847687 | false | false | false | false |
zebarnabe/music-keyboard-vhdl
|
src/main/keyboardDriver.vhd
| 1 | 2,429 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:36:39 06/30/2015
-- Design Name:
-- Module Name: keyboardDriver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keyboardDriver is
Port ( clk : in STD_LOGIC;
--btn : in STD_LOGIC_VECTOR (3 downto 0);
KEYBO : in STD_LOGIC_VECTOR (7 downto 0);
KEYBI : out STD_LOGIC_VECTOR (3 downto 0);
keyBank1 : out STD_LOGIC_VECTOR (7 downto 0);
keyBank2 : out STD_LOGIC_VECTOR (7 downto 0);
keyBank3 : out STD_LOGIC_VECTOR (7 downto 0);
keyBank4 : out STD_LOGIC_VECTOR (7 downto 0));
end keyboardDriver;
architecture Behavioral of keyboardDriver is
subtype keybuffer is STD_LOGIC_VECTOR(7 downto 0);
signal keybuffer1 : keybuffer := (others => '0');
signal keybuffer2 : keybuffer := (others => '0');
signal keybuffer3 : keybuffer := (others => '0');
signal keybuffer4 : keybuffer := (others => '0');
signal clkDiv : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
begin
process (clk, KEYBO)
begin
if (rising_edge(clk)) then
clkDiv <= clkDiv+1;
case clkDiv(11 downto 9) is
when "000" =>
KEYBI <= "1000";
when "001" =>
keybuffer1 <= KEYBO;
when "010" =>
KEYBI <= "0100";
when "011" =>
keybuffer2 <= KEYBO;
when "100" =>
KEYBI <= "0010";
when "101" =>
keybuffer3 <= KEYBO;
when "110" =>
KEYBI <= "0001";
when "111" =>
keybuffer4 <= KEYBO;
when others => null;
end case;
end if;
end process;
-- keyBus <= keybuffer1 & keybuffer2 & keybuffer3 & keybuffer4;
keyBank1 <= keybuffer1;
keyBank2 <= keybuffer2;
keyBank3 <= keybuffer3;
keyBank4 <= keybuffer4;
end Behavioral;
|
gpl-2.0
|
f6a2fe35209f84c4d8cadafb742b1727
| 0.568135 | 3.898876 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/irq_gen_v1_1/f141c1dc/hdl/vhdl/ipif_pkg.vhd
| 2 | 53,580 |
-------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the user?s sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
use work.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
|
gpl-2.0
|
1e07462dcbfa91e03a5aa4fb8f238122
| 0.489735 | 4.858982 | false | false | false | false |
luebbers/reconos
|
core/pcores/burst_ram_v2_01_a/hdl/vhdl/burst_ram_tb.vhd
| 1 | 9,325 |
--
-- \file burst_ram_tb.vhd
--
-- Test bench for ReconOS hardware thread burst RAMs
--
-- \author Enno Luebbers <[email protected]>
-- \date 10.10.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity burst_ram_tb is
generic (
G_PORTA_AWIDTH : integer := 12;
G_PORTA_DWIDTH : integer := 32; -- this is fixed!
G_PORTA_PORTS : integer := 1;
G_PORTB_AWIDTH : integer := 11;
G_PORTB_DWIDTH : integer := 64; -- this is fixed!
G_PORTB_USE_BE : integer := 1
);
end burst_ram_tb;
architecture Behavioral of burst_ram_tb is
constant CLK_T : time := 10 ns;
component burst_ram is
generic (
-- address and data widths, THREAD-side and OSIF-side
G_PORTA_AWIDTH : integer := 12;
G_PORTA_DWIDTH : integer := 32; -- this is fixed!
G_PORTA_PORTS : integer := 1;
G_PORTB_AWIDTH : integer := 11;
G_PORTB_DWIDTH : integer := 64; -- this is fixed!
G_PORTB_USE_BE : integer := 1
);
port (
-- A is thread-side, AX is secondary thread-side, B is OSIF-side
addra : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
addrax: in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
addrb : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
clka : in std_logic;
clkax : in std_logic;
clkb : in std_logic;
dina : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0); -- these widths are fixed
dinax : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
dinb : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
douta : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
doutax: out std_logic_vector(G_PORTA_DWIDTH-1 downto 0); --
doutb : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0); --
wea : in std_logic;
weax : in std_logic;
web : in std_logic;
ena : in std_logic;
enax : in std_logic;
enb : in std_logic;
beb : in std_logic_vector(G_PORTB_DWIDTH/8-1 downto 0)
);
end component;
signal addra : std_logic_vector(G_PORTA_AWIDTH-1 downto 0) := (others => '0');
signal addrax: std_logic_vector(G_PORTA_AWIDTH-1 downto 0) := (others => '0');
signal addrb : std_logic_vector(G_PORTB_AWIDTH-1 downto 0) := (others => '0');
signal clka : std_logic := '0';
signal clkax : std_logic := '0';
signal clkb : std_logic := '0';
signal dina : std_logic_vector(G_PORTA_DWIDTH-1 downto 0) := (others => '0');
signal dinax : std_logic_vector(G_PORTA_DWIDTH-1 downto 0) := (others => '0');
signal dinb : std_logic_vector(G_PORTB_DWIDTH-1 downto 0) := (others => '0');
signal douta : std_logic_vector(G_PORTA_DWIDTH-1 downto 0) := (others => '0');
signal doutax: std_logic_vector(G_PORTA_DWIDTH-1 downto 0) := (others => '0');
signal doutb : std_logic_vector(G_PORTB_DWIDTH-1 downto 0) := (others => '0');
signal wea : std_logic := '0';
signal weax : std_logic := '0';
signal web : std_logic := '0';
signal ena : std_logic := '0';
signal enax : std_logic := '0';
signal enb : std_logic := '0';
signal beb : std_logic_vector(7 downto 0) := (others => '1');
signal expecteda : std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
signal expectedax : std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
signal expectedb : std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
begin
dut : burst_ram
generic map (
G_PORTA_AWIDTH => G_PORTA_AWIDTH,
G_PORTA_DWIDTH => G_PORTA_DWIDTH,
G_PORTA_PORTS => G_PORTA_PORTS,
G_PORTB_AWIDTH => G_PORTB_AWIDTH,
G_PORTB_DWIDTH => G_PORTB_DWIDTH
)
port map (
addra => addra,
addrax => addrax,
addrb => addrb,
clka => clka,
clkax => clkax,
clkb => clkb,
dina => dina,
dinax => dinax,
dinb => dinb,
douta => douta,
doutax => doutax,
doutb => doutb,
wea => wea,
weax => weax,
web => web,
ena => ena,
enax => enax,
enb => enb,
beb => beb
);
clock_gen : process
begin
wait for CLK_T/2;
clka <= not clka;
end process;
clkax <= clka;
clkb <= clka;
test_proc : process
variable checka : std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
variable checkax : std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
variable checkb : std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
begin
-- write each 8-bitmemory cell on PORTA(X) with it's address
for i in 0 to 2**G_PORTA_AWIDTH-1 loop
wait until rising_edge(clka);
addra <= std_logic_vector(to_unsigned(i, G_PORTA_AWIDTH));
for j in 0 to G_PORTA_DWIDTH/8-1 loop
dina((j+1)*8-1 downto j*8) <= std_logic_vector(to_unsigned((i*G_PORTA_DWIDTH/8+j) mod 256, 8));
end loop;
ena <= '1';
wea <= '1';
if G_PORTA_PORTS = 2 then
addrax <= std_logic_vector(to_unsigned(i, G_PORTA_AWIDTH));
for j in 0 to G_PORTA_DWIDTH/8-1 loop
dinax((j+1)*8-1 downto j*8) <= std_logic_vector(to_unsigned((i*G_PORTA_DWIDTH/8+j+2**G_PORTA_AWIDTH) mod 256, 8));
end loop;
enax <= '1';
weax <= '1';
end if;
end loop;
wait until rising_edge(clka);
wea <= '0';
weax <= '0';
ena <= '0';
enax <= '0';
-- read each 8-bit memory cell on PORTB and check it for correctness
for i in 0 to 2**G_PORTB_AWIDTH-1 loop
wait until rising_edge(clkb);
addrb <= std_logic_vector(to_unsigned(i, G_PORTB_AWIDTH));
enb <= '1';
for j in 0 to G_PORTB_DWIDTH/8-1 loop
checkb((j+1)*8-1 downto j*8) := std_logic_vector(to_unsigned((i*G_PORTB_DWIDTH/8+j) mod 256, 8));
expectedb <= checkb;
end loop;
wait until rising_edge(clkb);
wait until rising_edge(clkb);
assert checkb = doutb report "Read data mismatch on port B" severity WARNING;
end loop;
wait until rising_edge(clka);
enb <= '0';
-- write each 8-bit memory cell on PORTB with it's address (inverted)
-- check each 8-bit memory cell on PORTA(X) with it's address (inverted)
for i in 0 to 2**G_PORTA_AWIDTH-1 loop
wait until rising_edge(clka);
addra <= std_logic_vector(to_unsigned(i, G_PORTA_AWIDTH));
ena <= '1';
for j in 0 to G_PORTA_DWIDTH/8-1 loop
checka((j+1)*8-1 downto j*8) := std_logic_vector(to_unsigned((i*G_PORTA_DWIDTH/8+j) mod 256, 8));
expecteda <= checka;
end loop;
wait until rising_edge(clka);
wait until rising_edge(clka);
assert checka = douta report "Read data mismatch on port A" severity WARNING;
if G_PORTA_PORTS = 2 then
addrax <= std_logic_vector(to_unsigned(i, G_PORTA_AWIDTH));
enax <= '1';
for j in 0 to G_PORTA_DWIDTH/8-1 loop
checkax((j+1)*8-1 downto j*8) := std_logic_vector(to_unsigned((i*G_PORTA_DWIDTH/8+j+2**G_PORTA_AWIDTH) mod 256, 8));
expectedax <= checkax;
end loop;
wait until rising_edge(clka);
wait until rising_edge(clka);
assert checka = douta report "Read data mismatch on port AX" severity WARNING;
end if;
end loop;
wait until rising_edge(clka);
ena <= '0';
enax <= '0';
end process;
end Behavioral;
|
gpl-3.0
|
1bc27fe38df85fd41fe9299fa3317503
| 0.537587 | 3.690146 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a/pcores/xps_osif_tb_v2_01_a/simhdl/vhdl/xps_osif_tb.vhd
| 1 | 27,110 |
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- xps_osif_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: xps_osif_tb.vhd
-- Version: 2.01.a
-- Description: IP testbench
-- Date: Thu Jul 23 14:47:35 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library xps_osif_v2_01_a;
library burst_ram_v2_01_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity xps_osif_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
C_FIFO_DWIDTH : natural := 32;
C_DCR_BASEADDR : std_logic_vector := "0000000000";
C_DCR_HIGHADDR : std_logic_vector := "0000000011";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_REGISTER_OSIF_PORTS : integer := 1; -- route OSIF ports through registers
C_DCR_ILA : integer := 0; -- 0: no debug ILA, 1: include debug chipscope ILA for DCR debugging
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 64;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity xps_osif_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of xps_osif_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Signal to hook up master detected error and synch bus
------------------------------------------
signal sig_dev_mderr : std_logic;
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant MST_ERROR : integer := 30;
constant INTERRUPT : integer := 31;
signal PLB_Clk : std_logic;
signal PLB_Rst : std_logic;
signal busy_local : std_logic;
signal task_interrupt : std_logic;
signal task_busy : std_logic;
signal task_blocking : std_logic;
signal task_clk : std_logic;
signal task_reset : std_logic;
signal task_os2task_vec : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal task_os2task_vec_i : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal task_task2os_vec : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal task_os2task : osif_os2task_t;
signal task_task2os : osif_task2os_t;
signal burstAddr : std_logic_vector(0 to 13);
signal burstWrData : std_logic_vector(0 to 63);
signal burstRdData : std_logic_vector(0 to 63);
signal burstWE : std_logic;
signal burstBE : std_logic_vector(0 to 7);
signal task2burst_Addr : std_logic_vector(0 to 11);
signal task2burst_Data : std_logic_vector(0 to 31);
signal burst2task_Data : std_logic_vector(0 to 31);
signal task2burst_WE : std_logic;
signal VDEC_YCrCb : std_logic_vector(9 downto 2);
signal VDEC_LLC : std_logic;
signal VDEC_Rst : std_logic;
signal VDEC_OE : std_logic;
signal VDEC_PwrDn : std_logic;
---------
-- FIFO control and data lines
---------
signal fifo_clk : std_logic;
signal fifo_reset : std_logic;
signal fifo_read_remove : std_logic;
signal fifo_read_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_read_ready : std_logic;
signal fifo_write_add : std_logic;
signal fifo_write_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_write_ready : std_logic;
-- for simulation
signal fifo_read_add : std_logic;
signal fifo_read_datain : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_read_empty : std_logic;
signal fifo_read_full : std_logic;
signal fifo_read_valid : std_logic;
signal fifo_write_remove : std_logic;
signal fifo_write_dataout : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_write_empty : std_logic;
signal fifo_write_full : std_logic;
signal fifo_write_valid : std_logic;
---------
-- DCR stimuli
---------
signal dcrAck : std_logic;
signal dcrDBus_in : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal dcrABus : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal dcrDBus_out : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal dcrRead : std_logic;
signal dcrWrite : std_logic;
signal dcrICON : std_logic_vector(35 downto 0); -- chipscope
constant C_GND_TASK_DATA : std_logic_vector(0 to 31) := (others => '0');
constant C_GND_TASK_ADDR : std_logic_vector(0 to 11) := (others => '0');
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity xps_osif_v2_01_a.xps_osif
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_BURST_AWIDTH => 14,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_FAMILY => C_FAMILY,
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_DCR_ILA => C_DCR_ILA,
C_MPLB_AWIDTH =>C_MPLB_AWIDTH,
C_MPLB_DWIDTH =>C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH =>C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P =>C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE =>C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS =>C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
interrupt => task_interrupt,
busy => task_busy,
blocking => task_blocking,
-- task interface
task_clk => task_clk,
task_reset => task_reset,
osif_os2task_vec => task_os2task_vec,
osif_task2os_vec => task_task2os_vec,
-- burst mem interface
burstAddr => burstAddr,
burstWrData => burstWrData,
burstRdData => burstRdData,
burstWE => burstWE,
burstBE => burstBE,
-- "real" FIFO access signals
fifo_clk => fifo_clk,
fifo_reset => fifo_reset,
fifo_read_en => fifo_read_remove,
fifo_read_data => fifo_read_data,
fifo_read_ready => fifo_read_ready,
fifo_write_en => fifo_write_add,
fifo_write_data => fifo_write_data,
fifo_write_ready => fifo_write_ready,
-- MAP USER PORTS ABOVE THIS LINE ------------------
o_dcrAck => dcrAck,
o_dcrDBus => dcrDBus_in,
i_dcrABus => dcrABus,
i_dcrDBus => dcrDBus_out,
i_dcrRead => dcrRead,
i_dcrWrite => dcrWrite,
i_dcrICON => dcrICON,
-- sys_clk => PLB_Clk,
-- sys_reset => PLB_Rst,
-- SPLB_Clk => SPLB_Clk,
-- SPLB_Rst => SPLB_Rst ,
-- PLB_ABus => PLB_ABus,
-- PLB_UABus => PLB_UABus,
-- PLB_PAValid => PLB_PAValid,
-- PLB_SAValid => PLB_SAValid,
-- PLB_rdPrim => PLB_rdPrim,
-- PLB_wrPrim => PLB_wrPrim,
-- PLB_masterID => PLB_masterID,
-- PLB_abort => PLB_abort,
-- PLB_busLock => PLB_busLock,
-- PLB_RNW => PLB_RNW,
-- PLB_BE => PLB_BE,
-- PLB_MSize => PLB_MSize,
-- PLB_size => PLB_size ,
-- PLB_type => PLB_type,
-- PLB_lockErr => PLB_lockErr,
-- PLB_wrDBus => PLB_wrDBus,
-- PLB_wrBurst => PLB_wrBurst,
-- PLB_rdBurst => PLB_rdBurst,
-- PLB_wrPendReq => PLB_wrPendReq,
-- PLB_rdPendReq => PLB_rdPendReq,
-- PLB_wrPendPri => PLB_wrPendPri,
-- PLB_rdPendPri => PLB_rdPendPri,
-- PLB_reqPri => PLB_reqPri,
-- PLB_TAttribute => PLB_TAttribute,
-- Sl_addrAck => Sl_addrAck,
-- Sl_SSize => Sl_SSize,
-- Sl_wait => Sl_wait,
-- Sl_rearbitrate => Sl_rearbitrate,
-- Sl_wrDAck => Sl_wrDAck,
-- Sl_wrComp => Sl_wrComp,
-- Sl_wrBTerm => Sl_wrBTerm,
-- Sl_rdDBus => Sl_rdDBus,
-- Sl_rdWdAddr => Sl_rdWdAddr,
-- Sl_rdDAck => Sl_rdDAck,
-- Sl_rdComp => Sl_rdComp,
-- Sl_rdBTerm => Sl_rdBTerm ,
-- Sl_MBusy => Sl_MBusy,
-- Sl_MWrErr => Sl_MWrErr,
-- Sl_MRdErr => Sl_MRdErr,
-- Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock ,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst =>M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
PLB_Clk <= MPLB_Clk;
PLB_Rst <= MPLB_Rst;
------------------------------------------
-- user task
------------------------------------------
dont_register_osif_ports : if C_REGISTER_OSIF_PORTS = 0 generate
task_os2task_vec_i <= task_os2task_vec;
task_task2os_vec <= to_std_logic_vector(task_task2os);
end generate;
register_osif_ports : if C_REGISTER_OSIF_PORTS /= 0 generate
register_osif_ports_proc: process(task_clk)
begin
if rising_edge(task_clk) then
task_os2task_vec_i <= task_os2task_vec;
task_task2os_vec <= to_std_logic_vector(task_task2os);
end if;
end process;
end generate;
task_os2task <= to_osif_os2task_t(task_os2task_vec_i or (X"0000000000" & busy_local & "000000"));
-- task_inst: User task instatiation
-- %%%USER_TASK%%%
------------------------------------------
-- Hook up UUT MD_error to synch_out bit for Master Detected Error status monitor
------------------------------------------
SYNCH_OUT(MST_ERROR) <= sig_dev_mderr;
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic IP Master
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
-- assert FALSE report "*** Start User Logic IP Master Read Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master read ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
-- assert FALSE report "*** User Logic is doing master read transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
-- assert FALSE report "*** Continue User Logic IP Master Write Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master write ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
-- assert FALSE report "*** User Logic is doing master write transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
-- assert FALSE report "*** Continue the rest of User Logic IP Master Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
-- assert FALSE report "*** User Logic IP Master Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
dcr_sim : process is
procedure OSIF_WRITE( where : in std_logic_vector(0 to 1);
what : in std_logic_vector(0 to C_DCR_DWIDTH-1) ) is
begin
dcrABus(C_DCR_AWIDTH-2 to C_DCR_AWIDTH-1) <= where;
dcrDBus_out <= what;
wait until rising_edge(PLB_Clk);
dcrWrite <= '1';
wait until rising_edge(PLB_Clk) and dcrAck = '1';
dcrWrite <= '0';
end procedure;
procedure OSIF_READ( where : in std_logic_vector(0 to 1);
variable what : out std_logic_vector(0 to C_DCR_DWIDTH-1) ) is
begin
dcrABus(C_DCR_AWIDTH-2 to C_DCR_AWIDTH-1) <= where;
wait until rising_edge(PLB_Clk);
dcrRead <= '1';
wait until rising_edge(PLB_Clk) and dcrAck = '1';
what := dcrDBus_in;
dcrRead <= '0';
end procedure;
constant OSIF_REG_COMMAND : std_logic_vector(0 to 1) := "00";
constant OSIF_REG_DATA : std_logic_vector(0 to 1) := "01";
constant OSIF_REG_DONE : std_logic_vector(0 to 1) := "10";
constant OSIF_REG_DATAX : std_logic_vector(0 to 1) := "10";
constant OSIF_REG_SIGNATURE : std_logic_vector(0 to 1) := "11";
constant OSIF_CMDNEW : std_logic_vector(0 to C_DCR_DWIDTH-1) := X"FFFFFFFF";
variable dummy : std_logic_vector(0 to C_DCR_DWIDTH-1);
begin
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (PLB_Rst'EVENT and PLB_Rst = '0');
dcrABus <= C_DCR_BASEADDR;
dcrDBus_out <= (others => '0');
dcrICON <= (others => '0');
dcrRead <= '0';
dcrWrite <= '0';
-- sst-generated code starts here
-- %%%SST_TESTBENCH_START%%%
-- %%%SST_TESTBENCH_END%%%
-- end of sst-generated code
wait for 1 us;
wait;
end process;
-- simulate RAM
burst_ram_i : entity burst_ram_v2_01_a.burst_ram
generic map (
G_PORTA_AWIDTH => 12,
G_PORTA_DWIDTH => 32,
G_PORTA_PORTS => 1,
G_PORTB_AWIDTH => 11,
G_PORTB_DWIDTH => 64,
G_PORTB_USE_BE => 1
)
port map (
addra => task2burst_Addr,
addrax => C_GND_TASK_ADDR,
addrb => burstAddr(0 to 10), -- RAM is addressing 64Bit values
clka => task_clk,
clkax => '0',
clkb => task_clk,
dina => task2burst_Data,
dinax => C_GND_TASK_DATA,
dinb => burstWrData,
douta => burst2task_Data,
doutax => open,
doutb => burstRdData,
wea => task2burst_WE,
weax => '0',
web => burstWE,
ena => '1',
enax => '0',
enb => '1',
beb => burstBE
);
-- simulate FIFOs
fifo_left : entity work.fifo
port map (
clk => fifo_clk,
din => fifo_read_datain,
rd_en => fifo_read_remove,
rst => fifo_reset,
wr_en => fifo_read_add,
dout => fifo_read_data,
empty => fifo_read_empty,
full => fifo_read_full,
valid => fifo_read_valid);
fifo_read_ready <= (not fifo_read_empty) or fifo_read_valid ;
fifo_right : entity work.fifo
port map (
clk => fifo_clk,
din => fifo_write_data,
rd_en => fifo_write_remove,
rst => fifo_reset,
wr_en => fifo_write_add,
dout => fifo_write_dataout,
empty => fifo_write_empty,
full => fifo_write_full,
valid => fifo_write_valid);
fifo_write_ready <= not(fifo_write_full);
fifo_fill : process(fifo_clk, fifo_reset)
variable counter : std_logic_vector(0 to C_FIFO_DWIDTH-1);
begin
if fifo_reset = '1' then
counter := (others => '0');
fifo_read_add <= '0';
fifo_read_datain <= (others => '0');
elsif rising_edge(fifo_clk) then
fifo_read_add <= '0';
-- only write on every second clock
if fifo_read_full = '0' and fifo_read_add = '0' and counter < 16 then
fifo_read_datain <= counter;
counter := counter + 1;
fifo_read_add <= '1';
end if;
end if;
end process;
-- infer latch for local busy signal
-- needed for asynchronous communication between thread and OSIF
busy_local_gen : process(task_reset, task_task2os.request, task_os2task.ack)
begin
if task_reset = '1' then
busy_local <= '0';
elsif task_task2os.request = '1' then
busy_local <= '1';
elsif task_os2task.ack = '1' then
busy_local <= '0';
end if;
end process;
end architecture testbench;
|
gpl-3.0
|
30a6ef21c3ef173961658b49a298641c
| 0.473073 | 4.104466 | false | false | false | false |
five-elephants/hw-neural-sampling
|
lfsr.vhdl
| 1 | 1,456 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.xor_reduce;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity lfsr is
generic (
width : integer := 8
);
port (
clk, reset : in std_ulogic;
seed, poly : in std_logic_vector(width-1 downto 0);
rand_out : out std_logic_vector(width-1 downto 0)
);
end lfsr;
architecture rtl of lfsr is
subtype state_t is std_logic_vector(width-1 downto 0);
signal state : state_t;
begin
rand_out <= state;
process ( clk, reset )
variable taps : state_t;
variable b : std_logic;
begin
if reset = '1' then
state <= seed;
elsif rising_edge(clk) then
taps := state and poly;
b := xor_reduce(taps);
state <= state(state'left-1 downto state'right) & b;
end if;
end process;
end rtl;
architecture behave of lfsr is
subtype state_t is std_logic_vector(width-1 downto 0);
signal state : state_t;
begin
rand_out <= state;
process ( clk, reset )
variable seed1, seed2 : positive;
variable rand : real;
variable int_rand : integer;
begin
if reset = '1' then
state <= seed;
seed1 := to_integer(unsigned(seed));
seed2 := 1234;
elsif rising_edge(clk) then
uniform(seed1, seed2, rand);
int_rand := integer(rand * (2.0**width-1.0));
state <= std_logic_vector(
to_unsigned(int_rand, state'length)
);
end if;
end process;
end behave;
|
apache-2.0
|
cb6e41e5fd6cab9b5c9f81a747c1af68
| 0.620192 | 3.301587 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/xwb_simple_uart.vhd
| 1 | 3,692 |
------------------------------------------------------------------------------
-- Title : Simple Wishbone UART
-- Project : General Cores Collection (gencores) library
------------------------------------------------------------------------------
-- File : xwb_simple_uart.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2011-11-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple UART controller, providing two modes of operation
-- (both can be used simultenously):
-- - physical UART (encoding fixed to 8 data bits, no parity and one stop bit)
-- - virtual UART: TXed data is passed via a FIFO to the Wishbone host (and
-- vice versa).
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-- 2011-10-04 1.1 twlostow xwb module
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
entity xwb_simple_uart is
generic(
g_with_virtual_uart : boolean := true;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
uart_rxd_i: in std_logic;
uart_txd_o: out std_logic
);
end xwb_simple_uart;
architecture rtl of xwb_simple_uart is
component wb_simple_uart
generic (
g_with_virtual_uart : boolean;
g_with_physical_uart : boolean;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_vuart_fifo_size : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic);
end component;
begin -- rtl
U_Wrapped_UART: wb_simple_uart
generic map (
g_with_virtual_uart => g_with_virtual_uart,
g_with_physical_uart => g_with_physical_uart,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_vuart_fifo_size => g_vuart_fifo_size)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_adr_i => slave_i.adr(4 downto 0),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o);
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <='0';
end rtl;
|
lgpl-3.0
|
ea94e7f6dbce78f6ce3690c5affa6718
| 0.514355 | 3.44082 | false | false | false | false |
five-elephants/hw-neural-sampling
|
sampling_network.vhdl
| 1 | 4,151 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.ceil;
use ieee.math_real.log2;
use work.sampling.all;
entity sampling_network is
generic (
num_samplers : integer := 1;
tau : positive := 20
);
port (
clk, reset : in std_ulogic;
clock_tick : out std_ulogic;
systime : out systime_t;
state : out state_array_t(1 to num_samplers);
membranes : out membrane_array_t(1 to num_samplers);
fires : out std_ulogic_vector(1 to num_samplers);
seeds : in lfsr_state_array_t(1 to num_samplers);
biases : in weight_array_t(1 to num_samplers);
weights : in weight_array2_t(1 to num_samplers, 1 to num_samplers)
);
end sampling_network;
architecture rtl of sampling_network is
subtype sum_in_t is
signed(sum_in_size(num_samplers)-1 downto 0);
signal phase : phase_t;
signal do_prop_count : std_ulogic;
signal prop_ctr : integer range 0 to lfsr_width-1;
signal state_i : state_array_t(1 to num_samplers);
signal systime_i : systime_t;
begin
state <= state_i;
systime <= systime_i;
------------------------------------------------------------
gen_samplers: for sampler_i in 1 to num_samplers generate
signal sum_in : sum_in_t;
signal weight_row : weight_array_t(1 to num_samplers);
begin
process ( weights )
begin
for i in 1 to num_samplers loop
weight_row(i) <= weights(sampler_i, i);
end loop;
end process;
summation: entity work.input_sum
generic map (
num_samplers => num_samplers
)
port map (
clk => clk,
reset => reset,
phase => phase,
state => state_i,
weights => weight_row,
sum => sum_in
);
sampler: entity work.sampler(rtl)
generic map (
num_samplers => num_samplers,
lfsr_polynomial => lfsr_polynomial,
tau => tau
)
port map (
clk => clk,
reset => reset,
phase => phase,
bias => biases(sampler_i),
sum_in => sum_in,
state => state_i(sampler_i),
membrane => membranes(sampler_i),
fire => fires(sampler_i),
seed => seeds(sampler_i)
);
end generate gen_samplers;
------------------------------------------------------------
------------------------------------------------------------
count_propagation: process ( clk, reset )
begin
if reset = '1' then
prop_ctr <= 0;
elsif rising_edge(clk) then
if do_prop_count = '1' then
if prop_ctr < lfsr_width-1 then
prop_ctr <= prop_ctr + 1;
else
prop_ctr <= 0;
end if;
end if;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
phase_fsm_transitions: process ( clk, reset )
begin
if reset = '1' then
phase <= idle;
elsif rising_edge(clk) then
case phase is
when idle =>
phase <= propagate;
when propagate =>
if prop_ctr = lfsr_width-2 then
phase <= tick;
end if;
when tick =>
phase <= evaluate;
when evaluate =>
phase <= propagate;
end case;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
phase_fsm_output: process (phase)
begin
--default assignments
do_prop_count <= '0';
clock_tick <= '0';
case phase is
when propagate =>
do_prop_count <= '1';
when tick =>
clock_tick <= '1';
when others =>
end case;
end process;
------------------------------------------------------------
------------------------------------------------------------
systime_counter: process ( clk, reset )
begin
if reset = '1' then
systime_i <= to_unsigned(0, systime_i'length);
elsif rising_edge(clk) then
if phase = tick then
systime_i <= systime_i + to_unsigned(1, systime_i'length);
end if;
end if;
end process;
------------------------------------------------------------
end rtl;
|
apache-2.0
|
011c63f8ba8cdfceac75e79d2e0b06b9
| 0.494098 | 4.126243 | false | false | false | false |
luebbers/reconos
|
support/templates/coregen/burst_ram/burst_ram.vhd
| 1 | 5,406 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2005 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file burst_ram.vhd when simulating
-- the core, burst_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY burst_ram IS
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic);
END burst_ram;
ARCHITECTURE burst_ram_a OF burst_ram IS
-- synopsys translate_off
component wrapped_burst_ram
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_burst_ram use entity XilinxCoreLib.blkmemdp_v6_2(behavioral)
generic map(
c_reg_inputsb => 0,
c_reg_inputsa => 0,
c_has_ndb => 0,
c_has_nda => 0,
c_ytop_addr => "1024",
c_has_rfdb => 0,
c_has_rfda => 0,
c_ywea_is_high => 1,
c_yena_is_high => 1,
c_yclka_is_rising => 1,
c_yhierarchy => "hierarchy1",
c_ysinita_is_high => 1,
c_ybottom_addr => "0",
c_width_b => 64,
c_width_a => 32,
c_sinita_value => "0",
c_sinitb_value => "0",
c_limit_data_pitch => 18,
c_write_modeb => 0,
c_write_modea => 0,
c_has_rdyb => 0,
c_yuse_single_primitive => 0,
c_has_rdya => 0,
c_addra_width => 11,
c_addrb_width => 10,
c_has_limit_data_pitch => 0,
c_default_data => "0",
c_pipe_stages_b => 0,
c_yweb_is_high => 1,
c_yenb_is_high => 1,
c_pipe_stages_a => 0,
c_yclkb_is_rising => 1,
c_yydisable_warnings => 1,
c_enable_rlocs => 0,
c_ysinitb_is_high => 1,
c_has_default_data => 1,
c_has_web => 1,
c_has_sinitb => 0,
c_has_wea => 1,
c_has_sinita => 0,
c_has_dinb => 1,
c_has_dina => 1,
c_ymake_bmm => 0,
c_sim_collision_check => "NONE",
c_has_enb => 0,
c_has_ena => 0,
c_depth_b => 1024,
c_mem_init_file => "mif_file_16_1",
c_depth_a => 2048,
c_has_doutb => 1,
c_has_douta => 1,
c_yprimitive_type => "16kx1");
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_burst_ram
port map (
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
doutb => doutb,
wea => wea,
web => web);
-- synopsys translate_on
END burst_ram_a;
|
gpl-3.0
|
f53b862ff809e2e40d302c62860e7a03
| 0.559563 | 3.570674 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/IcapCTRL_v1_00_d/hdl/vhdl/icapCTRL.vhd
| 1 | 17,851 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:05 07/20/2006
-- Design Name:
-- Module Name: icapCTRL - icapCTRL_rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity icapCTRL is
generic (
C_FAMILY : string := "virtex5";
C_ICAP_DWIDTH : integer:= 32;
C_BURST_SIZE : natural := 16; -- Number of DWords
C_NUM_WIDTH : integer := 5;
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := b"10_0000_0000"; --DCR_BaseAddr
C_DCR_HIGHADDR : std_logic_vector(9 downto 0) := b"00_0000_0011"; --DCR_HighAddr, not used
C_COUNT_ADDR : std_logic_vector(31 downto 0) := X"00000010"
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic_vector(1 downto 0);
M_rdAddr_o : out std_logic_vector(31 downto 0);
M_rdReq_o : out std_logic;
M_rdNum_o : out std_logic_vector(C_NUM_WIDTH - 1 downto 0);
M_rdAccept_i : in std_logic;
M_rdData_i : in std_logic_vector(63 downto 0);
M_rdAck_i : in std_logic;
M_rdComp_i : in std_logic;
M_wrAddr_o : out std_logic_vector(31 downto 0);
M_wrReq_o : out std_logic;
M_wrNum_o : out std_logic_vector(C_NUM_WIDTH - 1 downto 0);
M_wrAccept_i : in std_logic;
M_wrData_o : out std_logic_vector(63 downto 0);
M_wrRdy_i : in std_logic;
M_wrAck_i : in std_logic;
M_wrComp_i : in std_logic;
BUSY : out std_ulogic;
O : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
CE : out std_ulogic;
I : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
WRITE : out std_ulogic;
Fifo_empty_o : out std_logic;
Fifo_full_o : out std_logic;
--- Interrupt
done_int : out std_logic;
--- DCR signals
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
---
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
DCR_ABus_o : out std_logic_vector(9 downto 0);
DCR_Write_o : out std_logic;
DCR_Din_o : out std_logic_vector(31 downto 0);
state_CS : out std_logic_vector(2 downto 0);
burst_counter_CS : out std_logic_vector(2 downto 0)
);
end icapCTRL;
architecture icapCTRL_rtl of icapCTRL is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then
return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
component ICAP_VIRTEX2
port (
BUSY : out std_ulogic;
O : out std_logic_vector(7 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(7 downto 0);
WRITE : in std_ulogic
);
end component;
component ICAP_VIRTEX4
generic (
ICAP_WIDTH : string := "X32" -- "X8" or "X32"
);
port (
BUSY : out std_ulogic;
O : out std_logic_vector(31 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_ulogic
);
end component;
component ICAP_VIRTEX5
generic (
ICAP_WIDTH : string := "X32" -- "X8" or "X32"
);
port (
BUSY : out std_ulogic;
O : out std_logic_vector(31 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_ulogic
);
end component;
component icapFIFO
generic (
C_FIFO_DEPTH : integer := 64;
C_DIN_WIDTH : integer := 64;
C_DOUT_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
wEn_i : in std_logic;
wData_i : in std_logic_vector(C_DIN_WIDTH-1 downto 0);
rEn_i : in std_logic;
rData_o : out std_logic_vector(C_DOUT_WIDTH-1 downto 0);
full_o : out std_logic;
empty_o : out std_logic
);
end component;
-- component DCR_control
-- generic(
-- ICAP_DCR_ADDR_L : std_logic_vector(9 downto 0) := b"10_0000_0000";
-- ICAP_DCR_ADDR_H : std_logic_vector(9 downto 0) := b"10_0000_0011"
-- );
-- port(
-- dcr_addr : in std_logic_vector(9 downto 0);
-- dcr_mrd : in std_logic;
-- dcr_mwr : in std_logic;
-- dcr_din : in std_logic_vector(31 downto 0);
-- ---
-- dcr_ack : out std_logic;
-- dcr_dout : out std_logic_vector(31 downto 0);
-- ---
-- start_w : out std_logic;
-- start_r : out std_logic;
-- addr : out std_logic_vector(31 downto 0);
-- ---
-- clk : in std_logic
-- );
-- end component;
type state_type is (IDLE, INIT, ACTIVE, BURSTING, WRITE_COUNT, DONE);
signal state : state_type;
--signal addr : std_logic_vector(14 downto 0);
--signal addr : std_logic_vector(13 downto 0);
signal addr : std_logic_vector(18-(log2(C_BURST_SIZE)) downto 0);
signal addr_tail : std_logic_vector(2+(log2(C_BURST_SIZE)) downto 0);
signal base_addr : std_logic_vector(31 downto 22);
signal base_lngth : std_logic_vector(15 downto 0);
signal icap_busy : std_logic;
signal icap_dout : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din_r : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_en_l : std_logic;
signal icap_rnw : std_logic;
signal fifo_rEn : std_logic;
signal fifo_wEn : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal count : std_logic_vector(31 downto 0);
signal debounce : std_logic_vector(1 downto 0);
signal dcr_reg : std_logic_vector(31 downto 0);
signal dcr_start_w : std_logic;
signal dcr_start_w_n : std_logic;
signal dcr_start_r : std_logic;
signal dcr_addr : std_logic_vector(31 downto 0);
signal ctrl_reg : std_logic_vector(31 downto 0);
signal Sl_dcrAck_sig : std_logic;
signal done_int_i : std_logic;
signal state_sig : std_logic_vector(2 downto 0);
signal burst_counter : std_logic_vector(2 downto 0); -- range from 0 to 7, MPMC can acknowledge not more than 4 transfers at the same time
begin
-- ICAP_4 : ICAP_VIRTEX5
-- generic map (
-- ICAP_WIDTH => "X32") -- "X8" or "X32"
-- port map (
-- BUSY => icap_busy, -- Busy output
-- O => icap_dout, -- 8-bit data output
-- CE => icap_en_l, -- Clock enable input
-- CLK => clk, -- Clock input
-- I => icap_din_r, -- 8-bit data input
-- WRITE => icap_rnw -- Write input
-- );
--
-- SWAP_BITS: process (icap_din) is
-- begin -- process Swap_bit_Order
-- for byte_i in 0 to 3 loop
-- for bit_i in 0 to 7 loop
-- icap_din_r(byte_i*8 + (7-bit_i)) <= icap_din(byte_i*8 + bit_i);
-- end loop; -- Bit
-- end loop; -- Byte
-- end process SWAP_BITS;
state_CS <= state_sig;
addr_tail <= (others => '0');
-- Make icap signals available to chipscope at output
BUSY <= icap_busy; -- Busy output
O <= icap_dout; -- 8-bit data output
CE <= icap_en_l; -- Clock enable input
I <= icap_din; -- 8-bit data input
WRITE <= icap_rnw; -- Write input
-- dcr interface instantiation
dcr_control: entity work.dcr_if
generic map (
C_DCR_BASEADDR => C_DCR_BASEADDR)
port map (
clk => clk,
rst => reset,
DCR_ABus => DCR_ABus,
DCR_Sl_DBus => DCR_Sl_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
Sl_dcrAck => Sl_dcrAck_sig,
Sl_dcrDBus => Sl_dcrDBus,
ctrl_reg => ctrl_reg);
dcr_start_w <= Sl_dcrAck_sig and DCR_Write;
Sl_dcrAck <= Sl_dcrAck_sig;
-- Make DCR signals available to chipscope at output
DCR_ABus_o <= DCR_ABus;
DCR_Write_o <= DCR_Write;
DCR_Din_o <= ctrl_reg;
burst_counter_CS <= burst_counter;
Fifo_empty_o <= fifo_empty;
Fifo_full_o <= fifo_full;
-- -- WARNING!!!
-- -- The ICAP's data signals are reversed!
-- process(icap_din) begin
-- for i in 0 to 7 loop
-- icap_din_r(7-i) <= icap_din(i);
-- end loop;
-- end process;
-- if virtex2P or Virtex2 use ICAP_Virtex2 and invert input bits
V2_GEN : if (C_FAMILY = "virtex2p" or C_FAMILY = "virtex2") generate
V2_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_0 : ICAP_VIRTEX2
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
-- WARNING!!!
-- The ICAP's data signals are reversed in V2P!
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V2_GEN_8;
end generate V2_GEN;
V4_GEN : if (C_FAMILY = "virtex4") generate
V4_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_1 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X8") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V4_GEN_8;
V4_GEN_32 : if (C_ICAP_DWIDTH = 32) generate
ICAP_2 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X32") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
icap_din_r <= icap_din;
end generate V4_GEN_32;
end generate V4_GEN;
V5_GEN : if (C_FAMILY = "virtex5") generate
V5_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_3 : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => "X8") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V5_GEN_8;
V5_GEN_32 : if (C_ICAP_DWIDTH = 32) generate
ICAP_4 : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => "X32") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
SWAP_BITS: process (icap_din) is
begin -- process Swap_bit_Order
for byte_i in 0 to 3 loop
for bit_i in 0 to 7 loop
icap_din_r(byte_i*8 + (7-bit_i)) <= icap_din(byte_i*8 + bit_i);
end loop; -- Bit
end loop; -- Byte
end process SWAP_BITS;
end generate V5_GEN_32;
end generate V5_GEN;
-- fifo_empty is active high. If Fifo is not empty (fifo_empty = '0') rnw and ce gow low!
icap_rnw <= fifo_empty;
icap_en_l <= fifo_empty;
fifo_rEn <= not icap_busy;
fifo_wEn <= M_rdAck_i when(state=BURSTING) else '0';
icapFIFO_0 : icapFIFO
generic map (
C_FIFO_DEPTH => 64,
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => C_ICAP_DWIDTH
)
port map (
clk => clk,
reset => reset,
wEn_i => fifo_wEn,
wData_i => M_rdData_i,
rEn_i => fifo_rEn,
rData_o => icap_din,
full_o => fifo_full,
empty_o => fifo_empty
);
-- process(state, debounce, addr, base_addr) begin
-- M_rdAddr_o <= base_addr & addr & b"0000000";
-- if(state=IDLE) then
-- if(debounce(0)='0') then
-- M_rdAddr_o <= C_CONFIG_ADDR_0;
-- else
-- M_rdAddr_o <= C_CONFIG_ADDR_1;
-- end if;
-- end if;
-- end process;
-- Generate the read address
--M_rdAddr_o <= base_addr & addr & b"0000000";
--M_rdAddr_o <= base_addr & addr & b"00000000";
M_rdAddr_o <= base_addr & addr & addr_tail;
done_int <= done_int_i;
-- delay start signal by one cycle
process(clk) begin
if(clk='1' and clk'event) then
dcr_start_w_n <= dcr_start_w;
end if;
end process;
--By Rehan -- modified to Generics by Florian, 01.07.2009
M_rdNum_o <= CONV_STD_LOGIC_VECTOR(C_BURST_SIZE,C_NUM_WIDTH);
process(state, fifo_full, fifo_empty, addr) begin
-- don't request data
M_rdReq_o <= '0';
M_wrReq_o <= '0';
-- if(state=IDLE) then
-- -- debounce is active low, when one of the switches is pressed debounce goes low.
-- --M_rdReq_o <= not debounce(0) or not debounce(1); -- is one of the switches pressed?
-- M_rdReq_o <= dcr_start_w;
-- M_rdNum_o <= "00001"; -- request one 64 bit word
-- els
--if(state=ACTIVE) then
if ((state=ACTIVE or state=BURSTING) and (addr /= base_lngth)) then
M_rdReq_o <= not fifo_full;
elsif(state=WRITE_COUNT) then
M_wrReq_o <= fifo_empty;
end if;
end process;
M_wrAddr_o <= C_COUNT_ADDR;
M_wrNum_o <= CONV_STD_LOGIC_VECTOR(1,C_NUM_WIDTH);
M_wrData_o(63 downto 32) <= (others=>'0');
M_wrData_o(31 downto 0) <= count;
process(clk) begin
if(clk='1' and clk'event) then
if(state=IDLE) then
count <= (others=>'0');
else
if(fifo_empty='0') then -- if Fifo is not empty increase counter
count <= count+1;
end if;
end if;
end if;
end process;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
state <= IDLE;
addr <= (others=>'0');
base_addr <= (others=>'0');
base_lngth <= (others=>'0');
dcr_reg <= (others => '0');
done_int_i <= '0';
state_sig <= (others=>'0');
burst_counter <= (others=>'0');
else
--collect all M_rdAccepts
if(M_rdAccept_i='1') then
addr <= addr + 1;
burst_counter <= burst_counter+1;
end if;
done_int_i <= '0';
case(state) is
when IDLE =>
state_sig <= "000";
burst_counter <= (others=>'0');
addr <= (others=>'0');
-- initialize base addr and base_lngth with the data from DCR bus once!
base_addr <= ctrl_reg(31 downto 22);
base_lngth <= ctrl_reg(15 downto 0);
if(dcr_start_w_n='1') then
state <= ACTIVE;
end if;
when ACTIVE =>
state_sig <= "001";
if(burst_counter>=1) then
state <= BURSTING;
end if;
when BURSTING =>
state_sig <= "010";
-- 15.07.09 mod. Florian, the burst_counter value is decreased after completion of the current
-- burst which is indicated by the assertion of M_rdComp. This means, that the final burst
-- is completed but the burst_counter value still remains 1 until the next clock cycle occurs.
if(M_rdComp_i='1') then
if(addr=base_lngth and burst_counter=1) then
burst_counter <= burst_counter-1;
state <= WRITE_COUNT;
else
burst_counter <= burst_counter-1;
state <= ACTIVE;
end if;
end if;
when WRITE_COUNT =>
state_sig <= "011";
--if(M_wrAccept_i='1') then
state <= DONE;
--end if;
when DONE =>
state_sig <= "100";
if(fifo_empty = '1' and dcr_start_w_n = '0') then
done_int_i <= '1';
state <= IDLE;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
end icapCTRL_rtl;
|
gpl-3.0
|
1eaf9155db66781d6fd5ce13a46df5ef
| 0.51661 | 3.229781 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_record_elab.vhd
| 3 | 2,069 |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests initialization of records with aggregate expressions.
-- (based on the vhdl_struct_array test)
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_record_elab is
port (
i_low0: in std_logic_vector (3 downto 0);
i_high0: in std_logic_vector (3 downto 0);
i_low1: in std_logic_vector (3 downto 0);
i_high1: in std_logic_vector (3 downto 0);
o_low0: out std_logic_vector (3 downto 0);
o_high0: out std_logic_vector (3 downto 0);
o_low1: out std_logic_vector (3 downto 0);
o_high1: out std_logic_vector (3 downto 0)
);
end vhdl_record_elab;
architecture test of vhdl_record_elab is
type word is record
high: std_logic_vector (3 downto 0);
low: std_logic_vector (3 downto 0);
end record;
type dword is array (1 downto 0) of word;
signal my_dword : dword;
signal dword_a : dword;
begin
-- inputs
my_dword(0) <= (low => i_low0, high => i_high0);
-- test if you can assign values in any order
my_dword(1) <= (high => i_high1, low => i_low1);
dword_a <= (0 => (low => "0110", high => "1001"),
1 => (high => "1100", low => "0011"));
-- outputs
o_low0 <= my_dword(0).low;
o_high0 <= my_dword(0).high;
o_low1 <= my_dword(1).low;
o_high1 <= my_dword(1).high;
end test;
|
gpl-2.0
|
ed78c527c5bcb191a03fe9bd3053548c
| 0.675689 | 3.289348 | false | true | false | false |
luebbers/reconos
|
demos/resume_demo/hw/hwthreads/just_wait/just_wait.vhd
| 1 | 3,907 |
--!
--! \file just_wait.vhd
--!
--! Benchmark for cooperative multithreading
--!
--! \author Enno Luebbers <[email protected]>
--! \date 13.03.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 13.03.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity just_wait is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end just_wait;
architecture Behavioral of just_wait is
-- OS synchronization state machine states
type state_t is (STATE_INIT,
STATE_WAIT,
STATE_EXIT);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"03");
constant decode : decode_t := (STATE_INIT,
STATE_WAIT,
STATE_EXIT);
signal state : state_t := STATE_INIT;
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : state_t := STATE_INIT;
variable wait_time : std_logic_vector(0 to C_OSIF_DATA_WIDTH/2-2); -- possible values: 0..32767 (x 6553 us)
variable counter : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
next_state := STATE_INIT;
done := false;
success := false;
wait_time := (others => '0');
counter := (others => '0');
init_data := (others => '0');
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, init_data);
wait_time := init_data(17 to 31);
counter := wait_time & "0" & X"0000"; -- x 1.31 ms
next_state := STATE_WAIT;
when STATE_WAIT =>
if counter = X"00000000" then
next_state := STATE_EXIT;
else
counter := counter - 1;
end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
next_state := STATE_EXIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
38e5fe11e54cdceb21af492379d2ae6b
| 0.517021 | 3.7245 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_core_v2_01_a/hdl/vhdl/dcr_slave_regs.vhd
| 1 | 15,626 |
--!
--! \file dcr_slave_regs.vhd
--!
--! DCR bus slave logic for ReconOS OSIF (user_logic)
--!
--! Contains the bus access logic for the two register sets of the OSIF:
--!
--! bus2osif registers (writeable by the bus, readable by OSIF logic):
--! slv_bus2osif_command command register C_DCR_BASEADDR + 0x00
--! slv_bus2osif_data data register C_DCR_BASEADDR + 0x01
--! slv_bus2osif_done s/w-access handshake reg C_DCR_BASEADDR + 0x02
--! UNUSED C_DCR_BASEADDR + 0x03
--!
--! osif2bus registers (readable by the bus, writeable by OSIF logic):
--! slv_osif2bus_command command register C_DCR_BASEADDR + 0x00
--! slv_osif2bus_data data register C_DCR_BASEADDR + 0x01
--! slv_osif2bus_datax extended data register C_DCR_BASEADDR + 0x02
--! slv_osif2bus_signature hardware thread signature C_DCR_BASEADDR + 0x03
--!
--!
--! The i_post signal is set on a OS request which needs to be handled in
--! software.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 07.08.2006
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 07.08.2006 Enno Luebbers File created
-- 25.09.2007 Enno Luebbers added slv_osif2bus_datax
-- 23.11.2007 Enno Luebbers moved to DCR interface
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
--use IEEE.STD_LOGIC_ARITH.all;
--use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity dcr_slave_regs is
generic (
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_NUM_REGS : integer := 4;
C_INCLUDE_ILA : integer := 0 -- 0: no ILA, 1: ILA
-- for DCR debug
);
port (
clk : in std_logic;
reset : in std_logic; -- high active synchronous
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0);
-- user registers
slv_osif2bus_command : in std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
slv_osif2bus_flags : in std_logic_vector(0 to C_OSIF_FLAGS_WIDTH-1);
slv_osif2bus_saved_state_enc : in std_logic_vector(0 to C_OSIF_STATE_ENC_WIDTH-1);
slv_osif2bus_saved_step_enc : in std_logic_vector(0 to C_OSIF_STEP_ENC_WIDTH-1);
slv_osif2bus_data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
slv_osif2bus_datax : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
slv_osif2bus_signature : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
slv_bus2osif_command : out std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
slv_bus2osif_data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
slv_bus2osif_done : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- additional user interface
o_newcmd : out std_logic;
i_post : in std_logic;
o_busy : out std_logic;
o_interrupt : out std_logic
);
end dcr_slave_regs;
architecture behavioral of dcr_slave_regs is
-- chipscope DCR ILA component
component dcr_ila
port
(
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(76 downto 0);
trig0 : in std_logic_vector(2 downto 0)
);
end component;
-- Bus signalling helper signals
signal dcrAddrHit : std_logic;
signal dcrAck : std_logic;
signal regAddr : std_logic_vector(0 to 1); -- FIXME: hardcoded
signal readCE : std_logic_vector(0 to C_NUM_REGS-1);
signal writeCE : std_logic_vector(0 to C_NUM_REGS-1);
-- Bus signalling helper signals
signal slv_ip2bus_data : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to C_NUM_REGS-1);
signal slv_reg_read_select : std_logic_vector(0 to C_NUM_REGS-1);
-- Actual bus2osif registers
signal slv_bus2osif_command_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
signal slv_bus2osif_data_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
signal slv_bus2osif_done_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
-- new command arrived
signal newcmd : std_logic;
-- signals indicating unread data in bus-readable registers
signal osif2bus_reg_dirty : std_logic_vector(0 to 2) := "000";
-- DCR debug ILA signals
signal ila_data : std_logic_vector(76 downto 0);
signal ila_trig0 : std_logic_vector(2 downto 0);
begin
---------------------------------------------------
-- CHIPSCOPE
gen_dcr_ila : if C_INCLUDE_ILA = 1 generate
dcr_ila_inst : dcr_ila
port map
(
control => i_dcrICON,
clk => clk,
data => ila_data,
trig0 => ila_trig0
);
-- bits 76 75 74-65 64-33 32 31-0
--ila_data <= i_dcrRead & i_dcrWrite & i_dcrABus & i_dcrDBus & dcrAck & slv_ip2bus_data;
ila_data <= i_dcrRead & i_dcrWrite & i_dcrABus & i_dcrDBus & newcmd & slv_ip2bus_data;
ila_trig0 <= i_dcrRead & i_dcrWrite & dcrAck;
end generate;
---------------------------------------------------
----------------------------------------------------------------------------------------------------------
-- DCR "IPIF"
----------------------------------------------------------------------------------------------------------
-- 4 registers = 2 LSBs FIXME: hardcoded. Use log2 instead!
dcrAddrHit <= '1' when i_dcrABus(0 to C_DCR_AWIDTH-3) = C_DCR_BASEADDR(0 to C_DCR_AWIDTH-3)
else '0';
regAddr <= i_dcrABus(C_DCR_AWIDTH-2 to C_DCR_AWIDTH-1);
--
-- decode read and write accesses into chip enable signals
-- ASYNCHRONOUS
--
ce_gen : process(dcrAddrHit, i_dcrRead, i_dcrWrite,
regAddr)
begin
-- clear all chip enables by default
for i in 0 to C_NUM_REGS-1 loop
readCE(i) <= '0';
writeCE(i) <= '0';
end loop;
-- decode register address and set
-- corresponding chip enable signal
if dcrAddrHit = '1' then
if i_dcrRead = '1' then
readCE(TO_INTEGER(unsigned(regAddr))) <= '1';
elsif i_dcrWrite = '1' then
writeCE(TO_INTEGER(unsigned(regAddr))) <= '1';
end if;
end if;
end process;
--
-- generate DCR slave acknowledge signal
-- SYNCHRONOUS
--
gen_ack_proc : process(clk, reset)
begin
if reset = '1' then
dcrAck <= '0';
elsif rising_edge(clk) then
dcrAck <= ( i_dcrRead or i_dcrWrite ) and
dcrAddrHit;
end if;
end process;
o_dcrAck <= dcrAck;
-- --
-- -- update slave registers on write access
-- -- SYNCHRONOUS
-- --
-- reg_write_proc: process(i_clk, i_reset)
-- begin
-- if i_reset = '1' then
-- slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
-- slv_reg2 <= (others => '0');
-- slv_reg3 <= (others => '0');
-- elsif rising_edge(i_clk) then
-- case writeCE is
-- when "0001" =>
-- slv_reg0 <= i_dcrDBus;
-- when "0010" =>
-- slv_reg1 <= i_dcrDBus;
-- when "0100" =>
-- slv_reg2 <= i_dcrDBus;
-- when "1000" =>
-- slv_reg3 <= i_dcrDBus;
-- when others => null;
-- end case;
-- end if;
-- end process;
-- --
-- -- output slave registers on data bus on read access
-- -- ASYNCHRONOUS
-- --
-- reg_read_proc: process(readCE, slv_reg0, slv_reg1, slv_reg2,
-- slv_reg3, i_dcrDBus)
-- begin
-- o_dcrDBus <= i_dcrDBus;
-- case readCE is
-- when "0001" =>
-- o_dcrDBus <= slv_reg0;
-- when "0010" =>
-- o_dcrDBus <= slv_reg1;
-- when "0100" =>
-- o_dcrDBus <= slv_reg2;
-- when "1000" =>
-- o_dcrDBus <= slv_reg3;
-- when others =>
-- o_dcrDBus <= i_dcrDBus;
-- end case;
-- end process;
----------------------------------------------------------------------------------------------------------
-- DCR "IPIF" END
----------------------------------------------------------------------------------------------------------
-- ######################### CONCURRENT ASSIGNMENTS #######################
-- connect registers to outputs
slv_bus2osif_command <= slv_bus2osif_command_reg(0 to C_OSIF_CMD_WIDTH-1);
slv_bus2osif_data <= slv_bus2osif_data_reg;
slv_bus2osif_done <= slv_bus2osif_done_reg;
-- slv_bus2osif_shm <= slv_bus2osif_shm_reg;
-- new command from OS if write_reg2 is all ones. FIXME: 0000_0001 sufficient?
-- this is here to prevent incomplete command transmission if CPU uses byte accesses
-- will be cleared on cycle after assertion (see slave_reg_write_proc)
newcmd <= '1' when slv_bus2osif_done_reg = X"FFFF_FFFF" else '0';
o_newcmd <= newcmd;
-- we are busy as long as a pending request has not been retrieved by the CPU
o_busy <= osif2bus_reg_dirty(0) or osif2bus_reg_dirty(1) or osif2bus_reg_dirty(2) or i_post;
-- posting generates an interrupt
o_interrupt <= i_post;
-- drive IP to DCR Bus signals
o_dcrDBus <= slv_ip2bus_data;
-- connect bus signalling
slv_reg_write_select <= writeCE;
slv_reg_read_select <= readCE;
-- ############################### PROCESSES ############################
-------------------------------------------------------------
-- slave_reg_write_proc: implement bus write access to slave
-- registers
-------------------------------------------------------------
slave_reg_write_proc : process(clk) is
begin
if clk'event and clk = '1' then
if reset = '1' then
slv_bus2osif_command_reg <= (others => '0');
slv_bus2osif_data_reg <= (others => '0');
slv_bus2osif_done_reg <= (others => '0');
else
if dcrAck = '0' then -- register values only ONCE per write select
case slv_reg_write_select(0 to 3) is
when "1000" =>
slv_bus2osif_command_reg <= i_dcrDBus;
when "0100" =>
slv_bus2osif_data_reg <= i_dcrDBus;
when "0010" =>
slv_bus2osif_done_reg <= i_dcrDBus;
when "0001" => null;
when others => null;
end case;
end if;
if newcmd = '1' then
slv_bus2osif_done_reg <= (others => '0');
end if;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-------------------------------------------------------------
-- slave_reg_read_proc: implement bus read access to slave
-- registers
-------------------------------------------------------------
slave_reg_read_proc : process(slv_reg_read_select, slv_osif2bus_command, slv_osif2bus_data, slv_osif2bus_datax, i_dcrDBus) is
begin
slv_ip2bus_data <= i_dcrDBus;
case slv_reg_read_select(0 to 3) is
when "1000" => slv_ip2bus_data <= slv_osif2bus_command & slv_osif2bus_flags & slv_osif2bus_saved_state_enc & slv_osif2bus_saved_step_enc & "000000";
when "0100" => slv_ip2bus_data <= slv_osif2bus_data;
when "0010" => slv_ip2bus_data <= slv_osif2bus_datax;
when "0001" => slv_ip2bus_data <= slv_osif2bus_signature;
-- when others => slv_ip2bus_data <= (others => '0');
when others => null;
end case;
end process SLAVE_REG_READ_PROC;
-----------------------------------------------------------------------
-- dirty_flags: sets and clears osif2bus_reg_dirty bits
--
-- This allows to block the user task in a busy state while waiting
-- for OS to fetch the new commands.
-- The signature register does not need to be read to clear the dirty
-- flags.
-- The dirty flags are (obviously) only set on software-handled requests.
-----------------------------------------------------------------------
dirty_flags : process(reset, clk) --, i_post, slv_reg_read_select)
begin
if reset = '1' then
osif2bus_reg_dirty <= "000";
-- request only pollutes the read registers, if request is to be handled by software
elsif rising_edge(clk) then
if i_post = '1' then
osif2bus_reg_dirty <= "111";
else
case slv_reg_read_select(0 to 3) is
when "1000" =>
osif2bus_reg_dirty(0) <= '0';
when "0100" =>
osif2bus_reg_dirty(1) <= '0';
when "0010" =>
osif2bus_reg_dirty(2) <= '0';
when others => null;
end case;
end if;
end if;
end process;
end behavioral;
|
gpl-3.0
|
beca1339c626f35b1324904b31f6a76e
| 0.487393 | 3.990296 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.ip_user_files/ipstatic/axi_uartlite_v2_0_10/hdl/src/vhdl/uartlite_rx.vhd
| 1 | 24,736 |
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
-- dynshreg_i_f refered from proc_common_v4_0_2
-- srl_fifo_f refered from proc_common_v4_0_2
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_uartlite_v2_0_10;
-- uartlite_core refered from axi_uartlite_v2_0_10
use axi_uartlite_v2_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity axi_uartlite_v2_0_10.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
|
mit
|
5dc353c5a764047b726b3d3e20a89308
| 0.395901 | 4.922587 | false | false | false | false |
luebbers/reconos
|
support/pcores/message_manager_v1_00_a/hdl/vhdl/queue.vhd
| 1 | 8,266 |
-- *************************************************************************
-- File: queue.vhd
-- Purpose: Implements a queue (FIFO) usiing inferred BRAM.
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity queue is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
clk : in std_logic;
rst : in std_logic;
add : in std_logic;
remove : in std_logic;
entryToAdd : in std_logic_vector(0 to DATA_BITS-1);
head : out std_logic_vector(0 to DATA_BITS-1);
headValid : out std_logic;
full : out std_logic;
empty : out std_logic
);
end entity queue;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of queue is
-- Declare the component for the inferred BRAM
component infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_bram_dual_port;
-- Internal signals to hook up to output ports
signal empty_int, full_int, headValid_int : std_logic;
-- Signals to hook up to the inferred BRAM
signal ena, enb, wea : std_logic;
signal addra, addrb : std_logic_vector(0 to ADDRESS_BITS-1);
signal dia, doa, dob : std_logic_vector(0 to DATA_BITS-1);
-- ENQ FSM registers
signal tailPtr, tailPtr_next, nextFreePtr, nextFreePtr_next : std_logic_vector(0 to ADDRESS_BITS-1);
signal enqEntry, enqEntry_next : std_logic_vector(0 to DATA_BITS-1);
-- DEQ FSM registers
signal headPtr, headPtr_next : std_logic_vector(0 to ADDRESS_BITS-1);
signal busy, busy_next : std_logic;
-- Enqueue state enumeration
type enq_state_type is
(
reset,
idle,
beginAdd,
finishAdd
);
signal currentEnqState, nextEnqState : enq_state_type := idle;
-- Dequeue state enumeration
type deq_state_type is
(
reset,
idle,
beginRemove,
finishRemove
);
signal currentDeqState, nextDeqState : deq_state_type := idle;
-- *********************************************************
-- *********************************************************
-- *********************************************************
begin
-- Connect up status signals to output ports
empty <= empty_int;
full <= full_int;
headValid <= headValid_int;
-- Instantiation of the BRAM block to hold the queue data structure
queue_BRAM : infer_bram_dual_port
generic map (
ADDRESS_BITS => ADDRESS_BITS,
DATA_BITS => DATA_BITS
)
port map (
CLKA => clk,
ENA => ena,
WEA => wea,
ADDRA => addra,
DIA => dia,
DOA => doa,
CLKB => clk,
ENB => enb,
ADDRB => addrb,
DOB => dob
);
-- Connect head output to data output B of RAM
head <= dob;
-- Status Process
-- Calculate FULL/EMPTY status
STATUS : process
(clk, rst, tailPtr, headPtr, nextFreePtr, busy) is
begin
if (clk'event and clk = '1') then
if (rst = '1') then
full_int <= '0';
empty_int <= '1';
else
-- Check "full" condition
if (nextFreePtr = headPtr) then
full_int <= '1';
else
full_int <= '0';
end if;
-- Check "empty" condition
-- * headValid = (not empty) and (not busy)
if (tailPtr = headPtr) then
empty_int <= '1';
headValid_int <= '0' and (not busy);
else
empty_int <= '0';
headValid_int <= '1' and (not busy);
end if;
end if;
end if;
end process STATUS;
-- Syncrhonous ENQ FSM Process
-- Control state transitions of ENQ FSM
SYNCH_ENQ : process
(clk, rst, nextEnqState) is
begin
if (clk'event and clk = '1') then
if (rst = '1') then
-- Reset state
currentEnqState <= reset;
tailPtr <= (others => '0');
-- nextFreePtr <= (others => '0');
nextFreePtr <= conv_std_logic_vector(1,ADDRESS_BITS);
enqEntry <= (others => '0');
else
-- Transition state
currentEnqState <= nextEnqState;
tailPtr <= tailPtr_next;
nextFreePtr <= nextFreePtr_next;
enqEntry <= enqEntry_next;
end if;
end if;
end process SYNCH_ENQ;
-- Combinational ENQ FSM Process
-- State machine logic for ENQ FSM
COMB_ENQ : process
(currentEnqState, add, entryToAdd, tailPtr, enqEntry, full_int) is
begin
-- Setup default values for FSM signals
nextEnqState <= currentEnqState;
tailPtr_next <= tailPtr;
nextFreePtr_next <= tailPtr + 1;
enqEntry_next <= enqEntry;
addra <= (others => '0');
wea <= '0';
ena <= '0';
dia <= (others => '0');
-- FSM case statement
case (currentEnqState) is
when reset =>
-- Reset state
tailPtr_next <= (others => '0');
--nextFreePtr <= (others => '0');
nextFreePtr_next <= conv_std_logic_vector(1,ADDRESS_BITS);
-- Move to idle state
nextEnqState <= idle;
when idle =>
-- If request to add and queue isn't full
if (add = '1' and full_int ='0') then
-- Store entry to add and begin addition
enqEntry_next <= entryToAdd;
nextEnqState <= beginAdd;
-- Otherwise, stay in the idle state
else
nextEnqState <= idle;
end if;
when beginAdd =>
-- Write entry to BRAM
addra <= tailPtr;
wea <= '1';
ena <= '1';
dia <= enqEntry;
-- Increment tailPtr
tailPtr_next <= tailPtr + 1;
nextEnqState <= finishAdd;
when finishAdd =>
-- Used for delay
nextEnqState <= idle;
when others =>
nextEnqState <= reset;
end case;
end process COMB_ENQ;
-- Syncrhonous DEQ FSM Process
-- Control state transitions of DEQ FSM
SYNCH_DEQ : process
(clk, rst, nextDeqState) is
begin
if (clk'event and clk = '1') then
if (rst = '1') then
-- Reset state
currentDeqState <= reset;
headPtr <= (others => '0');
busy <= '0';
else
-- Transition state
currentDeqState <= nextDeqState;
headPtr <= headPtr_next;
busy <= busy_next;
end if;
end if;
end process SYNCH_DEQ;
-- Combinational DEQ FSM Process
-- State machine logic for DEQ FSM
COMB_DEQ : process
(currentDeqState, remove, headPtr, headValid_int, empty_int) is
begin
-- Setup default values for FSM signals
nextDeqState <= currentDeqState;
headPtr_next <= headPtr;
busy_next <= '0';
addrb <= headPtr;
enb <= '1';
-- FSM case statement
case (currentDeqState) is
when reset =>
-- Reset state
headPtr_next <= (others => '0');
busy_next <= '0';
-- Move to idle state
nextDeqState <= idle;
when idle =>
-- If request to remove and queue isn't empty
if (remove = '1' and empty_int = '0') then
busy_next <= '1';
headPtr_next <= headPtr + 1;
nextDeqState <= beginRemove;
-- Otherwise stay in idle state
else
busy_next <= '0';
nextDeqState <= idle;
end if;
when beginRemove =>
-- Used for delay
busy_next <= '1';
nextDeqState <= finishRemove;
when finishRemove =>
-- Used for delay
busy_next <= '0';
nextDeqState <= idle;
when others =>
nextDeqState <= reset;
end case;
end process COMB_DEQ;
end architecture implementation;
|
gpl-3.0
|
74e09e394261d672e15c8029dfa1442d
| 0.555287 | 3.465828 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/generic_dpram_dualclock.vhd
| 1 | 7,382 |
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-28
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram_dualclock is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram_dualclock;
architecture syn of generic_dpram_dualclock is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
function f_memarray_to_ramtype(arr : t_meminit_array) return t_ram_type is
variable tmp : t_ram_type;
variable n, pos : integer;
begin
pos := 0;
while(pos < g_size)loop
n := 0;
-- avoid ISE loop iteration limit
while (pos < g_size and n < 4096) loop
for i in 0 to g_data_width-1 loop
tmp(pos)(i) := arr(pos, i);
end loop; -- i
n := n+1;
pos := pos + 1;
end loop;
end loop;
return tmp;
end f_memarray_to_ramtype;
function f_file_contents return t_meminit_array is
begin
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
signal clka_int : std_logic;
signal clkb_int : std_logic;
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
begin
wea_rep <= (others => wea_i);
web_rep <= (others => web_i);
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process (clka_i)
begin
if rising_edge(clka_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_a(i) = '1' then
ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
process (clkb_i)
begin
if rising_edge(clkb_i) then
qb_o <= ram(to_integer(unsigned(ab_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_b(i) = '1' then
ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8)
:= db_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clka_i)
begin
if rising_edge(clka_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
qb_o <= ram(to_integer(unsigned(ab_i)));
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
end if;
end if;
end process;
end generate gen_without_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clka_i)
begin
if rising_edge(clka_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
qa_o <= da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
qb_o <= db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
process(clka_i)
begin
if rising_edge(clka_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_nochange;
end syn;
|
lgpl-3.0
|
c81328ae41a39ef9da8d8dda21b45768
| 0.537795 | 3.366165 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_macro.vhd
| 1 | 85,552 |
-------------------------------------------------------------------------------
--
-- Module : BRAM_macro.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Block SelectRAM macros and Control Mappings
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fifo_u.all;
use work.BRAM_fifo_pkg.all;
entity BRAM_macro is
generic (
BRAM_MACRO_NUM : integer := 1; --Number of BRAM Blocks.
--Allowed: 1, 2, 4, 8, 16
WR_DWIDTH : integer := 32; --FIFO write data width.
--Allowed: 8, 16, 32, 64
RD_DWIDTH : integer := 32; --FIFO read data width.
--Allowed: 8, 16, 32, 64
WR_REM_WIDTH : integer := 2; --log2(WR_DWIDTH/8)
RD_REM_WIDTH : integer := 2; --log2(RD_DWIDTH/8)
RD_PAD_WIDTH : integer := 1;
RD_ADDR_FULL_WIDTH: integer := 10;
RD_ADDR_WIDTH : integer := 9;
ADDR_MINOR_WIDTH: integer := 1;
WR_PAD_WIDTH : integer := 1;
WR_ADDR_FULL_WIDTH: integer := 10;
WR_ADDR_WIDTH : integer := 9;
glbtm : time := 1 ns );
port (
-- Reset
fifo_gsr: in std_logic;
-- clocks
wr_clk: in std_logic;
rd_clk: in std_logic;
rd_allow: in std_logic;
rd_allow_minor: in std_logic;
rd_addr_full: in std_logic_vector(RD_PAD_WIDTH+RD_ADDR_FULL_WIDTH-1 downto 0);
rd_addr_minor: in std_logic_vector(ADDR_MINOR_WIDTH-1 downto 0);
rd_addr: in std_logic_vector(RD_PAD_WIDTH + RD_ADDR_WIDTH -1 downto 0);
rd_data: out std_logic_vector(RD_DWIDTH -1 downto 0);
rd_rem: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
rd_sof_n: out std_logic;
rd_eof_n: out std_logic;
wr_allow: in std_logic;
wr_allow_minor: in std_logic;
wr_addr: in std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
wr_addr_minor: in std_logic_vector(ADDR_MINOR_WIDTH-1 downto 0);
wr_addr_full: in std_logic_vector(WR_PAD_WIDTH + WR_ADDR_FULL_WIDTH-1 downto 0);
wr_data: in std_logic_vector(WR_DWIDTH-1 downto 0);
wr_rem: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
wr_sof_n: in std_logic;
wr_eof_n: in std_logic
);
end BRAM_macro;
architecture BRAM_macro_hdl of BRAM_macro is
constant MEM_IDX : integer := SQUARE2(BRAM_MACRO_NUM);
constant WR_PAR_WIDTH : integer := GET_PAR_WIDTH(WR_DWIDTH);
constant RD_PAR_WIDTH : integer := GET_PAR_WIDTH(RD_DWIDTH);
constant RD_MINOR_HIGH: integer := POWER2(ADDR_MINOR_WIDTH);
constant REM_SEL_HIGH_VALUE : integer := GET_HIGH_VALUE(
RD_REM_WIDTH,WR_REM_WIDTH);
constant REM_SEL_HIGH1 : integer := POWER2(REM_SEL_HIGH_VALUE);
constant WR_SOF_EOF_WIDTH : integer := GET_WR_SOF_EOF_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant RD_SOF_EOF_WIDTH : integer := GET_RD_SOF_EOF_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant WR_CTRL_REM_WIDTH : integer := GET_WR_CTRL_REM_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant RD_CTRL_REM_WIDTH : integer := GET_RD_CTRL_REM_WIDTH(
RD_DWIDTH, WR_DWIDTH);
constant C_WR_ADDR_WIDTH : integer := GET_C_WR_ADDR_WIDTH(RD_DWIDTH,
WR_DWIDTH, BRAM_MACRO_NUM);
constant C_RD_ADDR_WIDTH : integer := GET_C_RD_ADDR_WIDTH(RD_DWIDTH,
WR_DWIDTH, BRAM_MACRO_NUM);
constant ratio1 : integer := GET_RATIO(RD_DWIDTH, WR_DWIDTH,
WR_SOF_EOF_WIDTH);
constant C_RD_TEMP_WIDTH : integer := GET_C_RD_TEMP_WIDTH(RD_DWIDTH, WR_DWIDTH);
constant C_WR_TEMP_WIDTH : integer := GET_C_WR_TEMP_WIDTH(RD_DWIDTH, WR_DWIDTH);
constant NUM_DIV : integer := GET_NUM_DIV(RD_DWIDTH, WR_DWIDTH);
constant WR_EN_FACTOR : integer := GET_WR_EN_FACTOR(NUM_DIV, BRAM_MACRO_NUM);
constant RDDWdivWRDW : integer := GET_RDDWdivWRDW(RD_DWIDTH, WR_DWIDTH);
type rd_data_vec_type is array(0 to BRAM_MACRO_NUM-1) of
std_logic_vector(RD_DWIDTH-1 downto 0);
type rd_sof_eof_vec_type is array(0 to BRAM_MACRO_NUM-1) of
std_logic_vector(RD_SOF_EOF_WIDTH-1 downto 0);
type rd_ctrl_rem_vec_type is array(0 to BRAM_MACRO_NUM-1) of
std_logic_vector(RD_CTRL_REM_WIDTH-1 downto 0);
type rd_ctrl_vec_type is array(0 to BRAM_MACRO_NUM-1) of
std_logic_vector(C_RD_TEMP_WIDTH-1 downto 0);
signal rd_data_grp: std_logic_vector((RD_DWIDTH * BRAM_MACRO_NUM) -1 downto 0);
signal rd_data_p: rd_data_vec_type := (others=>(others=>'0'));
signal rd_ctrl_rem_p: rd_ctrl_rem_vec_type := (others=>(others=>'0'));
signal rd_sof_eof_p: rd_sof_eof_vec_type := (others=>(others=>'0'));
signal rd_ctrl_p: rd_ctrl_vec_type := (others=>(others=>'0'));
signal wr_rem_plus_one: std_logic_vector(WR_REM_WIDTH downto 0);
signal wr_ctrl_rem: std_logic_vector(WR_CTRL_REM_WIDTH-1 downto 0);
signal rd_ctrl_rem: std_logic_vector(RD_CTRL_REM_WIDTH-1 downto 0);
signal min_addr1: integer := 0;
signal min_addr2: integer := 0;
signal rem_sel1: integer := 0;
signal rem_sel2: integer := 0;
signal gnd_bus: std_logic_vector(128 downto 0);
signal gnd: std_logic;
signal pwr: std_logic;
signal wr_sof_eof: std_logic_vector(WR_SOF_EOF_WIDTH-1 downto 0);
signal rd_sof_eof: std_logic_vector(RD_SOF_EOF_WIDTH-1 downto 0);
signal wr_sof_temp_n: std_logic_vector(RDDWdivWRDW -1 downto 0);
signal c_rd_temp: std_logic_vector(C_RD_TEMP_WIDTH-1 downto 0);
signal c_wr_temp: std_logic_vector(C_WR_TEMP_WIDTH-1 downto 0);
signal c_wr_en: std_logic_vector(WR_EN_FACTOR-1 downto 0);
----------------------------------------------------------------------------
-- ram enable signals
-- each ram has two enables for two ports
----------------------------------------------------------------------------
signal ram_wr_en: std_logic_vector(BRAM_MACRO_NUM -1 downto 0);
----------------------------------------------------------------------------
-- ram select signal, for read and write
-- each bit in this signal will select one bram
----------------------------------------------------------------------------
signal bram_rd_sel: std_logic_vector (MEM_IDX downto 0);
signal bram_wr_sel: std_logic_vector (MEM_IDX downto 0);
signal rd_sof_eof_grp: std_logic_vector((RD_SOF_EOF_WIDTH * BRAM_MACRO_NUM)-1 downto 0);
signal rd_ctrl_rem_grp: std_logic_vector((RD_CTRL_REM_WIDTH * BRAM_MACRO_NUM)-1 downto 0);
signal c_rd_ctrl_grp: std_logic_vector((C_RD_TEMP_WIDTH * BRAM_MACRO_NUM)-1 downto 0);
signal c_rd_allow1: std_logic;
signal c_wr_allow1: std_logic;
signal c_rd_allow2: std_logic;
signal c_wr_allow2: std_logic;
signal c_rd_ctrl_rem1: std_logic_vector(RD_CTRL_REM_WIDTH-1 downto 0);
signal c_rd_ctrl_rem2: std_logic_vector(RD_CTRL_REM_WIDTH-1 downto 0);
signal rd_addr_full_r: std_logic_vector(RD_PAD_WIDTH+RD_ADDR_FULL_WIDTH-1 downto 0);
begin
---------------------------------------------------------------------------
-- Misellainous --
---------------------------------------------------------------------------
gnd <= '0';
gnd_bus <= (others => '0');
pwr <= '1';
---------------------------------------------------------------------------
-- Pipeline
process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_allow = '1' then
rd_addr_full_r <= rd_addr_full after glbtm;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- -- Convert minor address to integer to use as select signals for data --
-- -- and control outputs --
------------------------------------------------------------------------------
min_addr1 <= slv2int(rd_addr_minor);
min_addr2 <= slv2int(wr_addr_minor);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
---------------------------- Multiplexer on Read Port -------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
readmuxgen1: if BRAM_MACRO_NUM > 1 generate
rdma: for i in 0 to BRAM_MACRO_NUM - 1 generate -- for data
rd_data_p(i) <= rd_data_grp (RD_DWIDTH* (i+1) -1 downto RD_DWIDTH * i);
end generate rdma;
rdmuxgen1a: if WR_DWIDTH > RD_DWIDTH generate
rd_data <= rd_data_p(conv_integer(bram_rd_sel));
end generate rdmuxgen1a;
rdmuxgen1b: if WR_DWIDTH <= RD_DWIDTH generate
rd_data <= rd_data_p(conv_integer(bram_rd_sel));
end generate rdmuxgen1b;
rdma_1: if WR_DWIDTH + RD_DWIDTH = 160 generate
rdma_1a: for i in 0 to BRAM_MACRO_NUM - 1 generate
rd_ctrl_rem_p(i) <= rd_ctrl_rem_grp(RD_CTRL_REM_WIDTH * (i+1) -1
downto RD_CTRL_REM_WIDTH*i);
end generate rdma_1a;
rd_ctrl_rem <= rd_ctrl_rem_p(conv_integer(bram_rd_sel));
end generate rdma_1;
end generate readmuxgen1;
readmuxgen2: if BRAM_MACRO_NUM = 1 generate
rdmuxgen1a: if WR_DWIDTH > RD_DWIDTH generate
rd_data <= rd_data_grp (RD_DWIDTH -1 downto 0);
end generate rdmuxgen1a;
rdmuxgen1b: if WR_DWIDTH <= RD_DWIDTH generate
rd_data <= rd_data_grp (RD_DWIDTH -1 downto 0);
end generate rdmuxgen1b;
rdma_2: if WR_DWIDTH + RD_DWIDTH = 160 generate
rd_ctrl_rem <= rd_ctrl_rem_grp(RD_CTRL_REM_WIDTH -1 downto 0);
end generate rdma_2;
end generate readmuxgen2;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------- Generate Select Signal on Multiple BRAMs --------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
bramselgen: if BRAM_MACRO_NUM > 1 generate
bramsel_gen1: if RD_DWIDTH /= WR_DWIDTH generate
bramsel_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
bram_rd_sel <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow_minor = '1' or rd_allow = '1') then
bram_rd_sel <= '0' & rd_addr_full(RD_ADDR_FULL_WIDTH-1
downto RD_ADDR_FULL_WIDTH-MEM_IDX);
end if;
end if;
end process bramsel_proc;
bram_wr_sel <= '0' & wr_addr_full(WR_ADDR_FULL_WIDTH-1 downto
WR_ADDR_FULL_WIDTH-MEM_IDX);
end generate bramsel_gen1;
bramsel_gen2: if RD_DWIDTH = WR_DWIDTH generate
bramsel_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
bram_rd_sel <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow_minor = '1' or rd_allow = '1') then
bram_rd_sel <= '0' & rd_addr(RD_ADDR_WIDTH-1
downto RD_ADDR_WIDTH-MEM_IDX);
end if;
end if;
end process bramsel_proc;
bram_wr_sel <= '0' & wr_addr(WR_ADDR_FULL_WIDTH-1 downto
WR_ADDR_FULL_WIDTH-MEM_IDX);
end generate bramsel_gen2;
end generate bramselgen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
---------------------------- SOF/EOF/REM Mappings -------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Width is smaller
-------------------------------------------------------------------------------
GEN1: if RD_DWIDTH < WR_DWIDTH generate -- If rd width is smaller
---------------------------------------------------------------------------
-- Ram enable signal for each ram unit (GEN1) --
-- each bit of this signal will select one unit of ram --
---------------------------------------------------------------------------
ram_en_gen1a: if BRAM_MACRO_NUM > 1 generate
ram_wr_en <= conv_std_logic_vector(POWER2(conv_integer(bram_wr_sel)),
BRAM_MACRO_NUM)
when wr_allow = '1' else (others=>'0');
end generate ram_en_gen1a;
ram_en_gen1b: if BRAM_MACRO_NUM = 1 generate
ram_wr_en <= "1" when wr_allow = '1' else (others=>'0');
end generate ram_en_gen1b;
GEN1_wr_map_1: if RD_DWIDTH > 8 generate -- rd width is greater than 8
rem_sel1 <= slv2int(wr_rem(WR_REM_WIDTH-1 downto RD_REM_WIDTH));
-- SOF mapping
wr_sof_eof(0) <= wr_sof_n;
GEN1_wr_map_2: for k in 1 to REM_SEL_HIGH1-1 generate
wr_sof_eof(k*ratio1) <= '1';
end generate GEN1_wr_map_2;
-- EOF mapping
GEN1_wr_map_3: for j in 0 to REM_SEL_HIGH1-1 generate
wr_sof_eof(j*ratio1 + 1) <= wr_eof_n when rem_sel1 = j else '1';
end generate GEN1_wr_map_3;
-- REM mapping
GEN1_wr_map_4: if RD_DWIDTH > 16 generate
GEN1_wr_map_5: if WR_DWIDTH + RD_DWIDTH = 96 generate
-- For this case, the rem and sof and eof are all group together
-- to become wr_sof_eof.
GEN1_wr_map_6: for i in 0 to REM_SEL_HIGH1-1 generate
wr_sof_eof(i*ratio1+RD_REM_WIDTH+1 downto i*ratio1+2) <=
wr_rem(RD_REM_WIDTH-1 downto 0)
when rem_sel1 = i else (others => '0');
end generate GEN1_wr_map_6;
end generate GEN1_wr_map_5;
GEN1_wr_map_7: if WR_DWIDTH + RD_DWIDTH = 160 generate
GEN1_wr_map_8: for i in 0 to REM_SEL_HIGH1-1 generate
wr_ctrl_rem(i*4+WR_REM_WIDTH-1 downto i*4) <= gnd & gnd &
wr_rem(RD_REM_WIDTH-1 downto 0)
when rem_sel1 = i else (others => '0');
end generate GEN1_wr_map_8;
end generate GEN1_wr_map_7;
GEN1_wr_map_9: if WR_DWIDTH + RD_DWIDTH = 192 generate
GEN1_wr_map_10: for i in 0 to REM_SEL_HIGH1-1 generate
wr_sof_eof(i*ratio1+RD_REM_WIDTH+1 downto i*ratio1+2) <=
wr_rem(RD_REM_WIDTH-1 downto 0)
when rem_sel1 = i else (others => '0');
end generate GEN1_wr_map_10;
end generate GEN1_wr_map_9;
end generate GEN1_wr_map_4;
GEN1_wr_map_11: if RD_DWIDTH = 16 generate
GEN1_wr_map_12: if WR_DWIDTH /= 128 generate
GEN1_wr_map_13: for i in 0 to REM_SEL_HIGH1-1 generate
wr_ctrl_rem(i) <= wr_rem(0) when rem_sel1 = i else '0';
end generate GEN1_wr_map_13;
end generate GEN1_wr_map_12;
GEN1_wr_map_14: if WR_DWIDTH = 128 generate
GEN1_wr_map_15: for i in 0 to REM_SEL_HIGH1-1 generate
wr_sof_eof(i*ratio1+2)<=wr_rem(0) when rem_sel1=i else '0';
end generate GEN1_wr_map_15;
end generate GEN1_wr_map_14;
end generate GEN1_wr_map_11;
end generate GEN1_wr_map_1;
---------------------------------------------------------------------------
-- The following generate statments Covers cases: 128:8, 64:8, 32:8, 16:8--
-- There is no need to find rem, so we only need two bit wide to store --
-- sof and eof. (GEN1) --
---------------------------------------------------------------------------
GEN1_wr_map_16: if RD_DWIDTH = 8 generate -- rd width is 8
rem_sel2 <= slv2int(wr_rem(WR_REM_WIDTH-1 downto 0));
-- SOF Mapping
wr_sof_eof(0) <= wr_sof_n;
GEN1_wr_map_17: if WR_DWIDTH /= 16 generate
GEN1_wr_map_18: if WR_DWIDTH /= 128 generate
GEN1_wr_map_19: for k in 1 to REM_SEL_HIGH1*2-1 generate
wr_sof_eof(k*ratio1) <= '1';
end generate GEN1_wr_map_19;
-- EOF mapping
GEN1_wr_map_20: for p in 0 to REM_SEL_HIGH1*2-1 generate
wr_sof_eof(p*ratio1 + 1)<=wr_eof_n when rem_sel2=p else '1';
end generate GEN1_wr_map_20;
end generate GEN1_wr_map_18;
GEN1_wr_map_21: if WR_DWIDTH = 128 generate
GEN1_wr_map_22: for k in 1 to REM_SEL_HIGH1*2-1 generate
wr_sof_eof(k*ratio1) <= '1';
end generate GEN1_wr_map_22;
-- EOF mapping
GEN1_wr_map_23: for p in 0 to REM_SEL_HIGH1*2-1 generate
wr_sof_eof(p*ratio1 + 1)<=wr_eof_n when rem_sel2=p else '1';
end generate GEN1_wr_map_23;
end generate GEN1_wr_map_21;
end generate GEN1_wr_map_17;
GEN1_wr_map_24: if WR_DWIDTH = 16 generate
GEN1_wr_map_25: for k in 1 to REM_SEL_HIGH1-1 generate
wr_sof_eof(k*ratio1) <= '1';
end generate GEN1_wr_map_25;
-- EOF mapping
GEN1_wr_map_26: for p in 0 to REM_SEL_HIGH1-1 generate
wr_sof_eof(p*ratio1 + 1) <= wr_eof_n when rem_sel2=p else '1';
end generate GEN1_wr_map_26;
end generate GEN1_wr_map_24;
end generate GEN1_wr_map_16;
---------------------------------------------------------------------------
-- Reading SOF, EOF, REM with mapping (GEN1) --
---------------------------------------------------------------------------
rd_sof_n <= rd_sof_eof(0) when min_addr1 = 1 else '1';
rd_eof_n <= rd_sof_eof(1);
GEN1_rd_map_0: if RD_DWIDTH = 8 generate
rd_rem <= (others => '0');
end generate;
GEN1_rd_map_1: if RD_DWIDTH > 8 generate
GEN1_rd_map_2: if RD_DWIDTH = 16 generate
rd_rem <= rd_ctrl_rem when rd_sof_eof(1) = '0' else (others => '0');
end generate GEN1_rd_map_2;
GEN1_rd_map_3: if RD_DWIDTH = 64 generate
rd_rem <= rd_ctrl_rem(RD_REM_WIDTH-1 downto 0);
end generate GEN1_rd_map_3;
GEN1_rd_map_4: if RD_DWIDTH = 32 generate
GEN1_rd_map_5: if WR_DWIDTH = 64 generate
rd_rem <= rd_sof_eof(RD_REM_WIDTH+1 downto 2);
end generate GEN1_rd_map_5;
GEN1_rd_map_6: if WR_DWIDTH = 128 generate
rd_rem <= rd_ctrl_rem(RD_REM_WIDTH-1 downto 0);
end generate GEN1_rd_map_6;
end generate GEN1_rd_map_4;
end generate GEN1_rd_map_1;
end generate GEN1;
-------------------------------------------------------------------------------
-- Write Width is smaller
-------------------------------------------------------------------------------
GEN2: if RD_DWIDTH > WR_DWIDTH generate
---------------------------------------------------------------------------
-- Ram enable signal for each ram unit (GEN2) --
-- each bit of this signal will select one unit of ram --
---------------------------------------------------------------------------
ram_en_gen2a: if BRAM_MACRO_NUM > 1 generate
ram_wr_en <= conv_std_logic_vector( POWER2(conv_integer(bram_wr_sel)),
BRAM_MACRO_NUM)
when wr_allow_minor = '1' else (others=>'0');
end generate ram_en_gen2a;
ram_en_gen2b: if BRAM_MACRO_NUM = 1 generate
ram_wr_en <= "1" when wr_allow_minor = '1' else (others=>'0');
end generate ram_en_gen2b;
---------------------------------------------------------------------------
-- Writing SOF, EOF, REM with mapping (GEN2) --
-- The process below is used to pipeline wr_sof_n in a register to avoid --
-- latches. --
---------------------------------------------------------------------------
wr_sw_gen2a2_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_sof_temp_n <= (others => '0');
elsif wr_clk'EVENT and wr_clk = '1' then
if wr_allow_minor = '1' then
wr_sof_temp_n(min_addr2) <= wr_sof_n after glbtm;
end if;
end if;
end process wr_sw_gen2a2_proc;
GEN2_wr_map_1: if WR_DWIDTH = 32 generate
GEN2_wr_map_2: if RD_DWIDTH = 64 generate
wr_sof_eof(0) <= wr_sof_n when (min_addr2 = 0) else wr_sof_temp_n(0);
wr_sof_eof(1) <= wr_eof_n;
wr_ctrl_rem(RD_REM_WIDTH-1 downto 0) <= wr_addr_minor & wr_rem
when wr_eof_n = '0' else (others => '0');
end generate GEN2_wr_map_2;
GEN2_wr_map_3: if RD_DWIDTH = 128 generate
wr_sof_eof(0) <= wr_sof_n when min_addr2 = 0 else wr_sof_temp_n(0);
wr_sof_eof(1) <= wr_eof_n;
wr_ctrl_rem(RD_REM_WIDTH-1 downto 0) <= wr_addr_minor & wr_rem
when wr_eof_n = '0' else (others => '0');
end generate GEN2_wr_map_3;
end generate GEN2_wr_map_1;
GEN2_wr_map_4: if WR_DWIDTH = 16 generate
GEN2_wr_map_5: if RD_DWIDTH /=128 generate
wr_sof_eof(0) <= wr_sof_n when min_addr2 = 0 else wr_sof_temp_n(0);
wr_sof_eof(1) <= wr_eof_n;
wr_ctrl_rem(RD_REM_WIDTH-1 downto 0) <= wr_addr_minor & wr_rem
when wr_eof_n = '0' else (others => '0');
end generate GEN2_wr_map_5;
GEN2_wr_map_6: if RD_DWIDTH = 128 generate
wr_sof_eof(0) <= wr_sof_n when (min_addr2 = 0 and wr_eof_n = '0')
else wr_sof_temp_n(0);
wr_sof_eof(1) <= wr_eof_n;
wr_ctrl_rem(RD_REM_WIDTH-1 downto 0) <= wr_addr_minor & wr_rem
when wr_eof_n = '0' else (others => '0');
end generate GEN2_wr_map_6;
end generate GEN2_wr_map_4;
GEN2_wr_map_7: if WR_DWIDTH = 8 generate
wr_sof_eof(0) <= wr_sof_n when (min_addr2 = 0 and wr_eof_n = '0')
else wr_sof_temp_n(0);
wr_sof_eof(1) <= wr_eof_n after glbtm;
GEN2_wr_map_8: if RD_DWIDTH > 32 generate
wr_ctrl_rem(RD_REM_WIDTH-1 downto 0) <= wr_addr_minor when
wr_eof_n = '0' else (others => '0');
end generate GEN2_wr_map_8;
GEN2_wr_map_9: if RD_DWIDTH <= 32 generate
wr_ctrl_rem(0) <= '1' when wr_eof_n = '0' else '0';
end generate GEN2_wr_map_9;
end generate GEN2_wr_map_7;
GEN2_wr_map_10: if WR_DWIDTH = 64 generate
wr_sof_eof(0) <= wr_sof_n when min_addr2 = 0 else wr_sof_temp_n(0);
wr_sof_eof(1) <= wr_eof_n;
wr_sof_eof(RD_REM_WIDTH+1 downto 2) <= wr_addr_minor & wr_rem when
wr_eof_n = '0' else (others => '0');
wr_sof_eof(7 downto RD_REM_WIDTH+2) <= (others => '0');
end generate GEN2_wr_map_10;
---------------------------------------------------------------------------
-- Reading SOF, EOF, REM with mapping (GEN2) --
---------------------------------------------------------------------------
GEN2_rd_map_1: if WR_DWIDTH = 32 generate
rd_sof_n <= rd_sof_eof(0);
GEN2_rd_map_2: if RD_DWIDTH = 64 generate
rd_eof_n <= rd_sof_eof(1) when rd_sof_eof(1) = '0' else rd_sof_eof(5);
rd_rem <= rd_ctrl_rem(2 downto 0);
end generate GEN2_rd_map_2;
GEN2_rd_map_3: if RD_DWIDTH = 128 generate
rd_eof_n <= rd_sof_eof(1) when rd_sof_eof(1) = '0'
else rd_sof_eof(3) when rd_sof_eof(3) = '0'
else rd_sof_eof(5) when rd_sof_eof(5) = '0'
else rd_sof_eof(7);
rd_rem <= rd_ctrl_rem(3 downto 0) when rd_sof_eof(1) = '0'
else rd_ctrl_rem(7 downto 4)
when rd_ctrl_rem(7 downto 6) = "01" and rd_sof_eof(3) = '0'
else rd_ctrl_rem(11 downto 8)
when rd_ctrl_rem(11 downto 10) = "10" and rd_sof_eof(5) = '0'
else rd_ctrl_rem(15 downto 12)
when rd_ctrl_rem(15 downto 14) = "11" and rd_sof_eof(7) = '0'
else (others => '0');
end generate GEN2_rd_map_3;
end generate GEN2_rd_map_1;
GEN2_rd_map_4: if WR_DWIDTH = 16 generate
GEN2_rd_map_5: if RD_DWIDTH = 64 generate
rd_sof_n <= rd_sof_eof(0);
rd_eof_n <= rd_sof_eof(1) when rd_sof_eof(1) = '0'
else rd_sof_eof(3) when rd_sof_eof(3) = '0'
else rd_sof_eof(5) when rd_sof_eof(5) = '0'
else rd_sof_eof(7);
rd_rem <= rd_ctrl_rem(RD_REM_WIDTH-1 downto 0);
end generate GEN2_rd_map_5;
GEN2_rd_map_6: if RD_DWIDTH = 32 generate
rd_sof_n <= rd_sof_eof(0);
rd_eof_n <= rd_sof_eof(1) when rd_sof_eof(1) = '0'
else rd_sof_eof(3);
rd_rem <= rd_ctrl_rem(RD_REM_WIDTH-1 downto 0);
end generate GEN2_rd_map_6;
GEN2_rd_map_7: if RD_DWIDTH = 128 generate
rd_sof_n <= rd_sof_eof(0);
rd_eof_n <= rd_sof_eof(1);
rd_rem <= rd_ctrl_rem(RD_REM_WIDTH-1 downto 0);
end generate GEN2_rd_map_7;
end generate GEN2_rd_map_4;
GEN2_rd_map_8: if WR_DWIDTH = 8 generate
rd_sof_n <= rd_sof_eof(0);
rd_eof_n <= rd_sof_eof(1);
GEN2_rd_map_9: if RD_DWIDTH > 32 generate
rd_rem <= rd_ctrl_rem(RD_REM_WIDTH-1 downto 0);
end generate GEN2_rd_map_9;
GEN2_rd_map_10: if RD_DWIDTH = 32 generate
rd_rem <= "00" when rd_ctrl_rem(0) = '1'
else "01" when rd_ctrl_rem(1) = '1'
else "10" when rd_ctrl_rem(2) = '1'
else "11" when rd_ctrl_rem(3) = '1'
else "00";
end generate GEN2_rd_map_10;
GEN2_rd_map_11: if RD_DWIDTH = 16 generate
rd_rem(0) <= '0' when rd_ctrl_rem(0) = '1'
else '1' when rd_ctrl_rem(1) = '1'
else '0';
end generate GEN2_rd_map_11;
end generate GEN2_rd_map_8;
GEN2_rd_map_12: if WR_DWIDTH = 64 generate
rd_sof_n <= rd_sof_eof(0);
rd_eof_n <= rd_sof_eof(1) when rd_sof_eof(1) = '0' else rd_sof_eof(9);
rd_rem <= rd_sof_eof(RD_REM_WIDTH+1 downto 2) when rd_sof_eof(1) = '0'
else rd_sof_eof(RD_REM_WIDTH+9 downto 10);
end generate GEN2_rd_map_12;
end generate GEN2;
-------------------------------------------------------------------------------
-- Read Width and write width are the same
-------------------------------------------------------------------------------
GEN3: if RD_DWIDTH = WR_DWIDTH generate
---------------------------------------------------------------------------
-- Ram enable signal for each ram unit (GEN3) --
-- each bit of this signal will select one unit of ram --
---------------------------------------------------------------------------
ram_en_gen3a: if BRAM_MACRO_NUM > 1 generate
ram_wr_en <= conv_std_logic_vector( POWER2(conv_integer(bram_wr_sel)),
BRAM_MACRO_NUM)
when wr_allow = '1' else (others=>'0');
end generate ram_en_gen3a;
ram_en_gen3b: if BRAM_MACRO_NUM = 1 generate
ram_wr_en <= "1" when wr_allow = '1' else (others=>'0');
end generate ram_en_gen3b;
---------------------------------------------------------------------------
-- Reading SOF, EOF, REM with mapping (GEN3) --
-- In the case when WR_DWIDTH and RD_DWIDTH are larger than 16 bit wide, --
-- all control signals(including sof and eof) are group together for --
-- mapping. This group name is different when the data width are --
-- different for easier implementations. --
---------------------------------------------------------------------------
wr_sof_eof(0) <= wr_sof_n;
wr_sof_eof(1) <= wr_eof_n;
rd_sof_n <= rd_sof_eof(0);
rd_eof_n <= rd_sof_eof(1);
rd_ctrl_gen3a: if WR_DWIDTH + RD_DWIDTH > 32 generate -- 32, 64, 128
wr_sof_eof(WR_REM_WIDTH+1 downto 2) <= wr_rem;
rd_rem <= rd_sof_eof(RD_REM_WIDTH+1 downto 2);
end generate rd_ctrl_gen3a;
rd_ctrl_gen3b: if WR_DWIDTH + RD_DWIDTH < 32 generate -- 16
rd_rem <= (others => '0');
end generate rd_ctrl_gen3b;
rd_ctrl_gen3c: if WR_DWIDTH + RD_DWIDTH /= 16 generate -- 16, 32, 64, 128
rd_ctrl_gen3c1: for i in 0 to BRAM_MACRO_NUM - 1 generate
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH * (i+1) -1
downto RD_SOF_EOF_WIDTH*i);
end generate rd_ctrl_gen3c1;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel));
end generate rd_ctrl_gen3c;
end generate GEN3;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--------------------------- Data and Control BRAMs ----------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Same Data Width --
-------------------------------------------------------------------------------
BRAM_gen_1: if WR_DWIDTH + RD_DWIDTH = 16 generate -- rd and wr are 8-bit wide
-- Data BRAM
BRAM_gen_1aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram1a: RAMB16_S9_S9 port map (ADDRA => rd_addr(10 downto 0),
ADDRB => wr_addr(10 downto 0),
DIA => gnd_bus(8 downto 1), DIPA => gnd_bus(0 downto 0),
DIB => wr_data, DIPB(0) => gnd,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
end generate BRAM_gen_1aa;
-- Control BRAM
BRAM_gen_1ab: if BRAM_MACRO_NUM < 16 generate -- if DATA BRAM is small, all
-- control data can fit into one BRAM
bram1b: RAMB16_S2_S2 port map (ADDRA => rd_addr(12 downto 0),
ADDRB => wr_addr(12 downto 0),
DIA => gnd_bus(1 downto 0), DIB => wr_sof_eof,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow, ENB => wr_allow,
DOA => rd_sof_eof);
end generate BRAM_gen_1ab;
BRAM_gen_1ac: if BRAM_MACRO_NUM >= 16 generate -- If DATA BRAM is large,
-- multiple control BRAMs are used
BRAM_gen_1ac1: for i in 0 to BRAM_MACRO_NUM/4-1 generate
bram1c: RAMB16_S2_S2 port map (ADDRA => rd_addr(12 downto 0),
ADDRB => wr_addr(12 downto 0),
DIA => gnd_bus(1 downto 0), DIB => wr_sof_eof,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow, ENB => c_wr_en(i),
DOA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
c_wr_en(i) <= ram_wr_en(i*4) or ram_wr_en(i*4+1) or
ram_wr_en(i*4+2) or ram_wr_en(i*4+3) ;
end generate BRAM_gen_1ac1;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel)/4);
end generate BRAM_gen_1ac;
end generate BRAM_gen_1;
-------------------------------------------------------------------------------
BRAM_gen_2: if WR_DWIDTH + RD_DWIDTH = 32 generate -- rd and wr are 16-bit wide
-- Data and Control BRAM
BRAM_gen_2aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram2a: RAMB16_S18_S18 port map (ADDRA => rd_addr(9 downto 0),
ADDRB => wr_addr(9 downto 0),
DIA => gnd_bus(17 downto 2), DIPA => gnd_bus(1 downto 0),
DIB => wr_data, DIPB => wr_sof_eof(1 downto 0),
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
end generate BRAM_gen_2aa;
-- Additional Control BRAM
bram2b: RAMB16_S1_S1 port map (ADDRA => rd_addr(13 downto 0),
ADDRB => wr_addr(13 downto 0),
DIA(0) => gnd, DIB(0) => wr_rem(0),
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow, ENB => wr_allow,
DOA(0) => rd_rem(0));
end generate BRAM_gen_2;
-------------------------------------------------------------------------------
BRAM_gen_3: if WR_DWIDTH + RD_DWIDTH = 64 generate -- rd and wr are 32-bit wide
-- Data and Control BRAM
BRAM_gen_3aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram3a: RAMB16_S36_S36 port map (ADDRA => rd_addr(8 downto 0),
ADDRB => wr_addr(8 downto 0),
DIA => gnd_bus(35 downto 4), DIPA => gnd_bus(3 downto 0),
DIB => wr_data, DIPB => wr_sof_eof,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i) );
end generate BRAM_gen_3aa;
end generate BRAM_gen_3;
-------------------------------------------------------------------------------
BRAM_gen_3a: if WR_DWIDTH + RD_DWIDTH = 128 generate -- rd and wr are 64-bit wide
-- Data and Control BRAM
BRAM_gen_3bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram3b: BRAM_S72_S72 port map (ADDRA => rd_addr(8 downto 0),
ADDRB => wr_addr(8 downto 0),
DIA => gnd_bus(71 downto 8), DIPA => gnd_bus(7 downto 0),
DIB => wr_data, DIPB => wr_sof_eof,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
end generate BRAM_gen_3bb;
end generate BRAM_gen_3a;
-------------------------------------------------------------------------------
BRAM_gen_3b: if WR_DWIDTH + RD_DWIDTH = 256 generate -- rd and wr are 128-bit wide
BRAM_gen_3cc: for i in 0 to BRAM_MACRO_NUM-1 generate
bram3c: BRAM_S144_S144 port map (ADDRA => rd_addr(8 downto 0),
ADDRB => wr_addr(8 downto 0),
DIA => gnd_bus(127 downto 0), DIPA => gnd_bus(15 downto 0),
DIB => wr_data, DIPB => wr_sof_eof,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
end generate BRAM_gen_3cc;
end generate BRAM_gen_3b;
-------------------------------------------------------------------------------
-- Different Data Width --
-------------------------------------------------------------------------------
BRAM_gen_4: if WR_DWIDTH + RD_DWIDTH = 24 generate
BRAM_gen_4a: if RD_DWIDTH = 8 generate -- rd is 8-bit, wr is 16-bit wide
-- Data BRAM
BRAM_gen_4aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram4a: RAMB16_S9_S18 port map (ADDRA => rd_addr_full(10 downto 0),
ADDRB => wr_addr_full(9 downto 0),
DIA => gnd_bus(7 downto 0), DIPA => gnd_bus(0 downto 0),
DIB => wr_data, DIPB => gnd_bus(1 downto 0),
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
end generate BRAM_gen_4aa;
-- Control BRAM
BRAM_gen_4ab: if BRAM_MACRO_NUM < 8 generate
bram4b: RAMB16_S2_S4 port map (ADDRA => rd_addr_full(12 downto 0),
ADDRB => wr_addr_full(11 downto 0),
DIA => gnd_bus(1 downto 0), DIB => wr_sof_eof,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => wr_allow,
DOA => rd_sof_eof);
end generate BRAM_gen_4ab;
BRAM_gen_4ac: if BRAM_MACRO_NUM >= 8 generate
BRAM_gen_4ac1: for i in 0 to BRAM_MACRO_NUM/4-1 generate
bram4c: RAMB16_S2_S4 port map (ADDRA =>rd_addr_full(12 downto 0),
ADDRB => wr_addr_full(11 downto 0),
DIA => gnd_bus(1 downto 0), DIB => wr_sof_eof,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => c_wr_en(i),
DOA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
c_wr_en(i) <= ram_wr_en(i*4) or ram_wr_en(i*4+1)
or ram_wr_en(i*4+2)
or ram_wr_en(i*4+3);
end generate BRAM_gen_4ac1;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel)/4);
end generate BRAM_gen_4ac;
end generate BRAM_gen_4a;
-------------------------------------------------------------------------------
BRAM_gen_4b: if RD_DWIDTH = 16 generate -- rd is 16-bit, wr is 8-bit wide
-- Data and Control BRAM
BRAM_gen_4bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram4d: RAMB16_S9_S18 port map ( ADDRB => rd_addr_full(9 downto 0),
ADDRA => wr_addr_full(10 downto 0),
DIB => gnd_bus(17 downto 2), DIPB => gnd_bus(1 downto 0),
DIA => wr_data, DIPA(0) => wr_ctrl_rem(0),
WEA => pwr, WEB => gnd, CLKA => wr_clk,
CLKB => rd_clk, SSRA => gnd, SSRB => gnd,
ENA => ram_wr_en(i), ENB => rd_allow,
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPB => rd_ctrl_rem_grp(RD_CTRL_REM_WIDTH*(i+1)-1
downto RD_CTRL_REM_WIDTH*i));
rd_ctrl_rem_p(i) <= rd_ctrl_rem_grp(RD_CTRL_REM_WIDTH*(i+1)-1
downto RD_CTRL_REM_WIDTH*i);
end generate BRAM_gen_4bb;
rd_ctrl_rem <= rd_ctrl_rem_p(conv_integer(bram_rd_sel));
-- Additional Control BRAM
BRAM_gen_4cc: if BRAM_MACRO_NUM < 16 generate
bram4e: RAMB16_S2_S2 port map (ADDRB => rd_addr_full(12 downto 0),
ADDRA=> wr_addr(12 downto 0),
DIA => wr_sof_eof, DIB => gnd_bus(1 downto 0) ,
WEA => pwr, WEB => gnd, CLKA => wr_clk,
CLKB => rd_clk, SSRA => gnd, SSRB => gnd,
ENA => wr_allow, ENB => rd_allow,
DOB => rd_sof_eof);
end generate BRAM_gen_4cc;
BRAM_gen_4dd: if BRAM_MACRO_NUM >= 16 generate
BRAM_gen_4dda: for i in 0 to BRAM_MACRO_NUM/8 -1 generate
bram4f: RAMB16_S2_S2 port map (ADDRB => rd_addr_full(12 downto 0),
ADDRA=> wr_addr(12 downto 0),
DIA => wr_sof_eof, DIB => gnd_bus(1 downto 0) ,
WEA => pwr, WEB => gnd, CLKA => wr_clk,
CLKB => rd_clk, SSRA => gnd, SSRB => gnd,
ENA => c_wr_en(i), ENB => rd_allow,
DOB => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
c_wr_en(i) <= ram_wr_en(i*8) or ram_wr_en(i*8+1)
or ram_wr_en(i*8+2)
or ram_wr_en(i*8+3) or ram_wr_en(i*8+4)
or ram_wr_en(i*8+5) or ram_wr_en(i*8+6)
or ram_wr_en(i*8+7);
end generate BRAM_gen_4dda;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel)/8);
end generate BRAM_gen_4dd;
end generate BRAM_gen_4b;
end generate BRAM_gen_4;
-----------------------------------------------------------------------------
BRAM_gen_5: if WR_DWIDTH + RD_DWIDTH = 40 generate
BRAM_gen_5a: if RD_DWIDTH = 8 generate -- rd is 8-bit, wr is 32-bit wide
BRAM_gen_5aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram5a: RAMB16_S9_S36 port map (ADDRA => rd_addr_full(10 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(8 downto 1), DIPA => gnd_bus(0 downto 0),
DIB => wr_data, DIPB => gnd_bus(4 downto 1),
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
end generate BRAM_gen_5aa;
BRAM_gen_5ab: if BRAM_MACRO_NUM < 8 generate
bram5b: RAMB16_S2_S9 port map (ADDRA => rd_addr_full(12 downto 0),
ADDRB => wr_addr_full(10 downto 0),
DIA => gnd_bus(10 downto 9), DIB => wr_sof_eof,
DIPB => gnd_bus(0 downto 0),
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => wr_allow,
DOA => rd_sof_eof);
end generate BRAM_gen_5ab;
BRAM_gen_5ac: if BRAM_MACRO_NUM >= 8 generate
BRAM_gen_5ac1: for i in 0 to BRAM_MACRO_NUM/4-1 generate
bram5c: RAMB16_S2_S9 port map (ADDRA => rd_addr_full(12 downto 0),
ADDRB => wr_addr_full(10 downto 0),
DIA => gnd_bus(10 downto 9), DIB => wr_sof_eof,
DIPB => gnd_bus(0 downto 0),
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => c_wr_en(i) ,
DOA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
c_wr_en(i) <= ram_wr_en(i*4) or ram_wr_en(i*4+1)
or ram_wr_en(i*4+2)
or ram_wr_en(i*4+3);
end generate BRAM_gen_5ac1;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel)/4);
end generate BRAM_gen_5ac;
end generate BRAM_gen_5a;
-------------------------------------------------------------------------------
BRAM_gen_5b: if RD_DWIDTH = 32 generate -- rd is 32-bit, wr is 8-bit wide
BRAM_gen_5bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram5d: RAMB16_S9_S36 port map (ADDRB => rd_addr_full(8 downto 0),
ADDRA => wr_addr_full(10 downto 0),
DIB => gnd_bus(35 downto 4), DIPB => gnd_bus(3 downto 0),
DIA => wr_data, DIPA => wr_ctrl_rem,
WEB => gnd, WEA => pwr, CLKB => rd_clk,
CLKA => wr_clk, SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPB => rd_ctrl_rem_grp(RD_CTRL_REM_WIDTH*(i+1)-1
downto RD_CTRL_REM_WIDTH*i));
rd_ctrl_rem_p(i) <= rd_ctrl_rem_grp(RD_CTRL_REM_WIDTH*(i+1)-1
downto RD_CTRL_REM_WIDTH*i);
end generate BRAM_gen_5bb;
rd_ctrl_rem <= rd_ctrl_rem_p(conv_integer(bram_rd_sel));
bram5e: RAMB16_S2_S2 port map (ADDRB => rd_addr_full(12 downto 0),
ADDRA=> wr_addr(12 downto 0),
DIA => wr_sof_eof, DIB => gnd_bus(1 downto 0),
WEA => pwr, WEB => gnd, CLKA => wr_clk,
CLKB => rd_clk, SSRA => gnd, SSRB => gnd,
ENA => wr_allow, ENB => rd_allow,
DOB => rd_sof_eof);
end generate BRAM_gen_5b;
end generate BRAM_gen_5;
-------------------------------------------------------------------------------
BRAM_gen_6: if WR_DWIDTH + RD_DWIDTH = 48 generate
BRAM_gen_6a: if RD_DWIDTH = 16 generate -- rd is 16-bit, wr is 32-bit wide
BRAM_gen_6aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram6a: RAMB16_S18_S36 port map (ADDRA => rd_addr_full(9 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(17 downto 2), DIPA => gnd_bus(1 downto 0),
DIB => wr_data, DIPB => wr_sof_eof,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
end generate BRAM_gen_6aa;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel));
bram6b: RAMB16_S1_S2 port map (ADDRA => rd_addr_full(13 downto 0),
ADDRB => wr_addr_full(12 downto 0),
DIA(0) => gnd, DIB => wr_ctrl_rem,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => wr_allow,
DOA => rd_ctrl_rem);
end generate BRAM_gen_6a;
-------------------------------------------------------------------------------
BRAM_gen_6b: if RD_DWIDTH = 32 generate -- rd is 32-bit, wr is 16-bit wide
BRAM_gen_6bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram6c: RAMB16_S18_S36 port map (ADDRB => rd_addr_full(8 downto 0),
ADDRA => wr_addr_full(9 downto 0),
DIB => gnd_bus(35 downto 4), DIPB => gnd_bus(3 downto 0),
DIA=> wr_data, DIPA => wr_sof_eof,
WEB => gnd, WEA => pwr, CLKB => rd_clk,
CLKA => wr_clk, SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPB => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
end generate BRAM_gen_6bb;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel));
bram6d: RAMB16_S2_S2 port map (ADDRB => rd_addr_full(12 downto 0),
ADDRA => wr_addr(12 downto 0),
DIB => gnd_bus(1 downto 0), DIA=> wr_ctrl_rem,
WEB => gnd, WEA => pwr, CLKB => rd_clk,
CLKA => wr_clk, SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => wr_allow,
DOB => rd_ctrl_rem);
end generate BRAM_gen_6b;
end generate BRAM_gen_6;
-------------------------------------------------------------------------------
BRAM_gen_7: if WR_DWIDTH + RD_DWIDTH = 72 generate
BRAM_gen_7a: if RD_DWIDTH = 8 generate -- rd is 8-bit, wr is 64-bit wide
BRAM_gen_7aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram7a: BRAM_S8_S72 port map (ADDRA => rd_addr_full(11 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(7 downto 0), DIB => wr_data,
DIPB => gnd_bus(15 downto 8),
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
end generate BRAM_gen_7aa;
BRAM_gen_7ab: if BRAM_MACRO_NUM < 4 generate
bram7b: RAMB16_S2_S18 port map (ADDRA => rd_addr_full(12 downto 0),
ADDRB => wr_addr_full(9 downto 0),
DIA => gnd_bus(1 downto 0),
DIB => wr_sof_eof, DIPB => gnd_bus(3 downto 2),
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => wr_allow,
DOA => rd_sof_eof);
end generate BRAM_gen_7ab;
BRAM_gen_7ac: if BRAM_MACRO_NUM >= 4 generate
BRAM_gen_7ac1: for i in 0 to BRAM_MACRO_NUM/2-1 generate
bram7c: RAMB16_S2_S18 port map (ADDRA => rd_addr_full(12 downto 0),
ADDRB => wr_addr_full(9 downto 0),
DIA => gnd_bus(1 downto 0),
DIB => wr_sof_eof, DIPB => gnd_bus(3 downto 2),
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => c_wr_en(i),
DOA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
c_wr_en(i) <= ram_wr_en(i*2) or ram_wr_en(i*2+1);
end generate BRAM_gen_7ac1;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel)/2);
end generate BRAM_gen_7ac;
end generate BRAM_gen_7a;
-------------------------------------------------------------------------------
BRAM_gen_7b: if RD_DWIDTH = 64 generate -- rd is 64-bit, wr is 8-bit wide
BRAM_gen_7bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram7d: BRAM_S8_S72 port map (ADDRB => rd_addr_full(8 downto 0),
ADDRA => wr_addr_full(11 downto 0),
DIB => gnd_bus(63 downto 0), DIA => wr_data,
DIPB => gnd_bus(71 downto 64),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
end generate BRAM_gen_7bb;
c_wr_temp <= "000" & wr_ctrl_rem & wr_sof_eof;
rd_sof_eof <= c_rd_temp(1 downto 0);
rd_ctrl_rem <= c_rd_temp(4 downto 2);
BRAM_gen_7cc: if BRAM_MACRO_NUM <= 4 generate
bram7e: RAMB16_S9_S9 port map (ADDRB => rd_addr_full(10 downto 0),
ADDRA => wr_addr(10 downto 0),
DIB => gnd_bus(7 downto 0), DIA => c_wr_temp,
DIPA => gnd_bus(0 downto 0), DIPB => gnd_bus(0 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => wr_allow,
DOB => c_rd_temp);
end generate BRAM_gen_7cc;
BRAM_gen_7dd: if BRAM_MACRO_NUM > 4 generate
BRAM_gen_7dda: for i in 0 to BRAM_MACRO_NUM/2 -1 generate
bram7f: RAMB16_S9_S9 port map (ADDRB => rd_addr_full(10 downto 0),
ADDRA => wr_addr(10 downto 0),
DIB => gnd_bus(7 downto 0), DIA => c_wr_temp,
DIPA => gnd_bus(0 downto 0), DIPB => gnd_bus(0 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => c_wr_en(i),
DOB => c_rd_ctrl_grp(8*(i+1)-1 downto 8*i));
c_wr_en(i) <= ram_wr_en(i*2) or ram_wr_en(i*2+1);
rd_ctrl_p(i) <= c_rd_ctrl_grp(8*(i+1) -1 downto 8*i);
end generate BRAM_gen_7dda;
c_rd_temp <= rd_ctrl_p(conv_integer(bram_rd_sel)/2);
end generate BRAM_gen_7dd;
end generate BRAM_gen_7b;
end generate BRAM_gen_7;
--------------------------------------------------------------------------------
BRAM_gen_9: if WR_DWIDTH + RD_DWIDTH = 80 generate
BRAM_gen_9a: if RD_DWIDTH = 16 generate -- rd is 16-bit, wr is 64-bit wide
BRAM_gen_9aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram9a: BRAM_S18_S72 port map (ADDRA => rd_addr_full(10 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(15 downto 0),DIPA => gnd_bus(17 downto 16),
DIB => wr_data, DIPB => wr_sof_eof ,
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
end generate BRAM_gen_9aa;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel));
BRAM_gen_9ab: if BRAM_MACRO_NUM < 16 generate
bram9b: RAMB16_S1_S4 port map (ADDRA => rd_addr_full(13 downto 0),
ADDRB => wr_addr_full(11 downto 0),
DIA => gnd_bus(0 downto 0), DIB => wr_ctrl_rem,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => wr_allow,
DOA => rd_ctrl_rem);
end generate BRAM_gen_9ab;
BRAM_gen_9ac: if BRAM_MACRO_NUM >= 16 generate
c_rd_allow1 <= rd_allow_minor and rd_addr_full(14);
c_rd_allow2 <= rd_allow_minor and not c_rd_allow1 ;
c_wr_allow1 <= wr_allow and wr_addr_full(12);
c_wr_allow2 <= wr_allow and not c_wr_allow1;
rd_ctrl_rem <= c_rd_ctrl_rem1 when rd_addr_full_r(14) = '1' else c_rd_ctrl_rem2;
bram9c: RAMB16_S1_S4 port map (ADDRA => rd_addr_full(13 downto 0),
ADDRB => wr_addr_full(11 downto 0),
DIA => gnd_bus(0 downto 0), DIB => wr_ctrl_rem,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => c_rd_allow1, ENB => c_wr_allow1,
DOA => c_rd_ctrl_rem1);
bram9d: RAMB16_S1_S4 port map (ADDRA => rd_addr_full(13 downto 0),
ADDRB => wr_addr_full(11 downto 0),
DIA => gnd_bus(0 downto 0), DIB => wr_ctrl_rem,
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => c_rd_allow2, ENB => c_wr_allow2,
DOA => c_rd_ctrl_rem2);
end generate BRAM_gen_9ac;
end generate BRAM_gen_9a;
-------------------------------------------------------------------------------
BRAM_gen_9b: if RD_DWIDTH = 64 generate -- rd is 64-bit, wr is 16-bit wide
BRAM_gen_9bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram9e: BRAM_S18_S72 port map (ADDRB => rd_addr_full(8 downto 0),
ADDRA => wr_addr_full(10 downto 0),
DIA => wr_data, DIPA => wr_sof_eof,
DIB => gnd_bus(63 downto 0), DIPB => gnd_bus(71 downto 64),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPB => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
end generate BRAM_gen_9bb;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel));
BRAM_gen_9cc: if BRAM_MACRO_NUM <= 8 generate
bram9f: RAMB16_S4_S4 port map (ADDRB => rd_addr_full(11 downto 0),
ADDRA => wr_addr(11 downto 0),
DIB => gnd_bus(3 downto 0), DIA => wr_ctrl_rem,
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => wr_allow,
DOB => rd_ctrl_rem);
end generate BRAM_gen_9cc;
BRAM_gen_9dd: if BRAM_MACRO_NUM > 8 generate
c_rd_allow1 <= rd_allow and rd_addr_full(12);
c_rd_allow2 <= rd_allow and not c_rd_allow1;
c_wr_allow1 <= wr_allow and wr_addr(12);
c_wr_allow2 <= wr_allow and not c_wr_allow1;
rd_ctrl_rem <= c_rd_ctrl_rem1 when rd_addr_full_r(12) = '1' else c_rd_ctrl_rem2;
bram9g: RAMB16_S4_S4 port map (ADDRB => rd_addr_full(11 downto 0),
ADDRA => wr_addr(11 downto 0),
DIA => wr_ctrl_rem, DIB => gnd_bus(3 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => c_rd_allow1, ENA => c_wr_allow1,
DOB => c_rd_ctrl_rem1);
bram9h: RAMB16_S4_S4 port map (ADDRB => rd_addr_full(11 downto 0),
ADDRA => wr_addr(11 downto 0),
DIA => wr_ctrl_rem, DIB => gnd_bus(3 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => c_rd_allow2, ENA => c_wr_allow2,
DOB => c_rd_ctrl_rem2);
end generate BRAM_gen_9dd;
end generate BRAM_gen_9b;
end generate BRAM_gen_9;
-------------------------------------------------------------------------------
BRAM_gen_8: if WR_DWIDTH + RD_DWIDTH = 96 generate
BRAM_gen_8a: if RD_DWIDTH = 32 generate -- rd is 32-bit, wr is 64-bit wide
BRAM_gen_8aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram8a: BRAM_S36_S72 port map (ADDRA => rd_addr_full(9 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(31 downto 0),DIPA => gnd_bus(35 downto 32),
DIB => wr_data, DIPB => wr_sof_eof ,
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
end generate BRAM_gen_8aa;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel));
end generate BRAM_gen_8a;
-------------------------------------------------------------------------------
BRAM_gen_8b: if RD_DWIDTH = 64 generate -- rd is 64-bit, wr is 32-bit wide
BRAM_gen_8bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram8b: BRAM_S36_S72 port map (ADDRB => rd_addr_full(8 downto 0),
ADDRA => wr_addr_full(9 downto 0),
DIA => wr_data, DIPA => wr_sof_eof,
DIB => gnd_bus(63 downto 0), DIPB => gnd_bus(71 downto 64),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPB => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
end generate BRAM_gen_8bb;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel));
BRAM_gen_8cc: if BRAM_MACRO_NUM <= 8 generate
bram8c: RAMB16_S4_S4 port map (ADDRB => rd_addr_full(11 downto 0),
ADDRA => wr_addr(11 downto 0),
DIA => wr_ctrl_rem, DIB => gnd_bus(3 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => wr_allow,
DOB => rd_ctrl_rem);
end generate BRAM_gen_8cc;
BRAM_gen_8dd: if BRAM_MACRO_NUM > 8 generate
c_rd_allow1 <= rd_allow and rd_addr_full(12);
c_rd_allow2 <= rd_allow and not c_rd_allow1;
rd_ctrl_rem <= c_rd_ctrl_rem1 when rd_addr_full_r(12) = '1' else c_rd_ctrl_rem2;
c_wr_allow1 <= wr_allow and wr_addr(12);
c_wr_allow2 <= wr_allow and not c_wr_allow1;
bram8d: RAMB16_S4_S4 port map (ADDRB => rd_addr_full(11 downto 0),
ADDRA => wr_addr(11 downto 0),
DIA => wr_ctrl_rem, DIB => gnd_bus(3 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => c_rd_allow1, ENA => c_wr_allow1,
DOB => c_rd_ctrl_rem1);
bram8e: RAMB16_S4_S4 port map (ADDRB => rd_addr_full(11 downto 0),
ADDRA => wr_addr(11 downto 0),
DIA => wr_ctrl_rem, DIB => gnd_bus(3 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => c_rd_allow2, ENA => c_wr_allow2,
DOB => c_rd_ctrl_rem2);
end generate BRAM_gen_8dd;
end generate BRAM_gen_8b;
end generate BRAM_gen_8;
-------------------------------------------------------------------------------
BRAM_gen_10: if WR_DWIDTH + RD_DWIDTH = 136 generate
BRAM_gen_10a: if RD_DWIDTH = 8 generate -- rd is 8-bit, wr is 128-bit wide
BRAM_gen_10aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram10a: BRAM_S8_S144 port map (ADDRA => rd_addr_full(12 downto 0), -- Data FIFO
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(7 downto 0), DIB => wr_data,
DIPB => gnd_bus(15 downto 0),
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
bram10b: RAMB16_S2_S36 port map (ADDRA => rd_addr_full(12 downto 0), -- Control FIFO
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(1 downto 0),
DIB => wr_sof_eof, DIPB => gnd_bus(3 downto 0),
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1 downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
end generate BRAM_gen_10aa;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel));
end generate BRAM_gen_10a;
-------------------------------------------------------------------------------
BRAM_gen_10b: if RD_DWIDTH = 128 generate -- rd is 128-bit, wr is 8-bit wide
BRAM_gen_10bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram10c: BRAM_S8_S144 port map (ADDRB => rd_addr_full(8 downto 0), -- Data FIFO
ADDRA => wr_addr_full(12 downto 0),
DIB => gnd_bus(127 downto 0), DIA => wr_data,
DIPB => gnd_bus(15 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
end generate BRAM_gen_10bb;
c_wr_temp <= "00" & wr_ctrl_rem & wr_sof_eof;
rd_sof_eof <= c_rd_temp(1 downto 0);
rd_ctrl_rem <= c_rd_temp(5 downto 2);
BRAM_gen_10cc: if BRAM_MACRO_NUM < 8 generate
bram10d: RAMB16_S9_S9 port map (ADDRB => rd_addr_full(10 downto 0), -- Control FIFO
ADDRA => wr_addr(10 downto 0),
DIB => gnd_bus(7 downto 0), DIA => c_wr_temp,
DIPA => gnd_bus(0 downto 0), DIPB => gnd_bus(0 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => wr_allow,
DOB => c_rd_temp);
end generate BRAM_gen_10cc;
BRAM_gen_10dd: if BRAM_MACRO_NUM >= 8 generate
BRAM_gen_10dda: for i in 0 to BRAM_MACRO_NUM/4 -1 generate
bram10e: RAMB16_S9_S9 port map (ADDRB => rd_addr_full(10 downto 0), -- Control FIFO
ADDRA => wr_addr(10 downto 0),
DIB => gnd_bus(7 downto 0), DIA => c_wr_temp,
DIPA => gnd_bus(0 downto 0), DIPB => gnd_bus(0 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => c_wr_en(i),
DOB => c_rd_ctrl_grp(8*(i+1)-1 downto 8*i));
c_wr_en(i) <= ram_wr_en(i*4) or ram_wr_en(i*4+1)
or ram_wr_en(i*4+2) or ram_wr_en(i*4+3) ;
rd_ctrl_p(i) <= c_rd_ctrl_grp(8*(i+1) -1 downto 8*i);
end generate BRAM_gen_10dda;
c_rd_temp <= rd_ctrl_p(conv_integer(bram_rd_sel)/4);
end generate BRAM_gen_10dd;
end generate BRAM_gen_10b;
end generate BRAM_gen_10;
-----------------------------------------------------------------------------
BRAM_gen_11: if WR_DWIDTH + RD_DWIDTH = 144 generate -- rd is 16-bit, wr is 128-bit wide
BRAM_gen_11a: if RD_DWIDTH = 16 generate
BRAM_gen_11aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram11a: BRAM_S16_S144 port map (ADDRA => rd_addr_full(11 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(15 downto 0),
DIB => wr_data, DIPB => gnd_bus(15 downto 0) ,
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
-- ENA => pwr, ENB => ram_wr_en(i),
ENA => rd_allow_minor, ENB => ram_wr_en(i), -- DH: fixed read enable to handle dst_rdy
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
bram11b: RAMB16_S4_S36 port map (ADDRA => rd_addr_full(11 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(3 downto 0),
DIB => wr_sof_eof, DIPB => gnd_bus(3 downto 0),
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
-- ENA => pwr, ENB => ram_wr_en(i),
ENA => rd_allow_minor, ENB => ram_wr_en(i), -- DH: fixed read enable to handle dst_rdy
DOA => c_rd_ctrl_grp(4*(i+1)-1 downto 4*i));
rd_ctrl_p(i) <= c_rd_ctrl_grp(4*(i+1) -1 downto 4*i);
end generate BRAM_gen_11aa;
c_rd_temp <= rd_ctrl_p(conv_integer(bram_rd_sel));
rd_sof_eof <= c_rd_temp(1 downto 0);
rd_ctrl_rem <= c_rd_temp(2 downto 2);
end generate BRAM_gen_11a;
-------------------------------------------------------------------------------
BRAM_gen_11b: if RD_DWIDTH = 128 generate -- rd is 128-bit, wr is 16-bit wide
BRAM_gen_11bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram11c: BRAM_S16_S144 port map (ADDRB => rd_addr_full(8 downto 0),
ADDRA => wr_addr_full(11 downto 0),
DIB => gnd_bus(127 downto 0), DIA => wr_data, DIPB => gnd_bus(15 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i));
end generate BRAM_gen_11bb;
c_wr_temp <= "00" & wr_ctrl_rem & wr_sof_eof;
rd_sof_eof <= c_rd_temp(1 downto 0);
rd_ctrl_rem <= c_rd_temp(5 downto 2);
BRAM_gen_11cc: if BRAM_MACRO_NUM < 8 generate
bram11d: RAMB16_S9_S9 port map (ADDRB => rd_addr_full(10 downto 0),
ADDRA => wr_addr(10 downto 0),
DIB => gnd_bus(7 downto 0), DIA => c_wr_temp,
DIPA => gnd_bus(0 downto 0), DIPB => gnd_bus(0 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => wr_allow,
DOB => c_rd_temp);
end generate BRAM_gen_11cc;
BRAM_gen_11dd: if BRAM_MACRO_NUM >= 8 generate
BRAM_gen_11dda: for i in 0 to BRAM_MACRO_NUM/4 -1 generate
bram11e: RAMB16_S9_S9 port map (ADDRB => rd_addr_full(10 downto 0),
ADDRA => wr_addr(10 downto 0),
DIB => gnd_bus(7 downto 0), DIA => c_wr_temp,
DIPA => gnd_bus(0 downto 0), DIPB => gnd_bus(0 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => c_wr_en(i),
DOB => c_rd_ctrl_grp(8*(i+1)-1 downto 8*i));
c_wr_en(i) <= ram_wr_en(i*4) or ram_wr_en(i*4+1)
or ram_wr_en(i*4+2) or ram_wr_en(i*4+3) ;
rd_ctrl_p(i) <= c_rd_ctrl_grp(8*(i+1) -1 downto 8*i);
end generate BRAM_gen_11dda;
c_rd_temp <= rd_ctrl_p(conv_integer(bram_rd_sel)/4);
end generate BRAM_gen_11dd;
end generate BRAM_gen_11b;
end generate BRAM_gen_11;
-----------------------------------------------------------------------------
BRAM_gen_12: if WR_DWIDTH + RD_DWIDTH = 160 generate
BRAM_gen_12a: if RD_DWIDTH = 32 generate -- rd is 32-bit, wr is 128-bit wide
BRAM_gen_12aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram12a: BRAM_S36_S144 port map (ADDRA => rd_addr_full(10 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(31 downto 0),DIPA => gnd_bus(35 downto 32),
DIB => wr_data, DIPB => wr_ctrl_rem ,
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => rd_ctrl_rem_grp(RD_CTRL_REM_WIDTH * (i+1) -1 downto RD_CTRL_REM_WIDTH*i));
end generate BRAM_gen_12aa;
BRAM_gen_12ab: if BRAM_MACRO_NUM < 8 generate
bram12b: RAMB16_S2_S9 port map (ADDRA => rd_addr_full(12 downto 0),
ADDRB => wr_addr_full(10 downto 0),
DIA => gnd_bus(10 downto 9), DIB => wr_sof_eof, DIPB => gnd_bus(0 downto 0),
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => wr_allow,
DOA => rd_sof_eof);
end generate BRAM_gen_12ab;
BRAM_gen_12ac: if BRAM_MACRO_NUM >= 8 generate
BRAM_gen_12ac1: for i in 0 to BRAM_MACRO_NUM/4-1 generate
bram12c: RAMB16_S2_S9 port map (ADDRA => rd_addr_full(12 downto 0),
ADDRB => wr_addr_full(10 downto 0),
DIA => gnd_bus(10 downto 9), DIB => wr_sof_eof,
DIPB => gnd_bus(0 downto 0),
WEA => gnd, WEB => pwr, CLKA => rd_clk,
CLKB => wr_clk, SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => c_wr_en(i),
DOA => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
c_wr_en(i) <= ram_wr_en(i*4) or ram_wr_en(i*4+1) or ram_wr_en(i*4+2) or ram_wr_en(i*4+3) ;
end generate BRAM_gen_12ac1;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel)/4);
end generate BRAM_gen_12ac;
end generate BRAM_gen_12a;
-------------------------------------------------------------------------------
BRAM_gen_12b: if RD_DWIDTH = 128 generate -- rd is 128-bit, wr is 32-bit wide
BRAM_gen_12ba: for i in 0 to BRAM_MACRO_NUM-1 generate
bram12d: BRAM_S36_S144 port map (ADDRB => rd_addr_full(8 downto 0),
ADDRA => wr_addr_full(10 downto 0),
DIA => wr_data, DIPA => wr_ctrl_rem,
DIB => gnd_bus(127 downto 0), DIPB => gnd_bus(15 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPB => rd_ctrl_rem_grp(RD_CTRL_REM_WIDTH * (i+1) -1 downto RD_CTRL_REM_WIDTH*i));
end generate BRAM_gen_12ba;
BRAM_gen_12bb: if BRAM_MACRO_NUM < 8 generate
bram12e: RAMB16_S2_S9 port map (ADDRB => rd_addr_full(10 downto 0),
ADDRA => wr_addr_full(12 downto 0),
DIA => wr_sof_eof, DIB => gnd_bus(7 downto 0),
DIPB => gnd_bus(0 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => wr_allow_minor,
DOB => rd_sof_eof);
end generate BRAM_gen_12bb;
BRAM_gen_12bc: if BRAM_MACRO_NUM >= 8 generate
BRAM_gen_12bc1: for i in 0 to BRAM_MACRO_NUM/4-1 generate
bram12e: RAMB16_S2_S9 port map (ADDRB => rd_addr_full(10 downto 0),
ADDRA => wr_addr_full(12 downto 0),
DIA => wr_sof_eof, DIB => gnd_bus(7 downto 0),
DIPB => gnd_bus(0 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => c_wr_en(i),
DOB => rd_sof_eof_grp(RD_SOF_EOF_WIDTH*(i+1)-1
downto RD_SOF_EOF_WIDTH*i));
rd_sof_eof_p(i) <= rd_sof_eof_grp(RD_SOF_EOF_WIDTH *(i+1)-1
downto RD_SOF_EOF_WIDTH*i);
c_wr_en(i) <= ram_wr_en(i*4) or ram_wr_en(i*4+1) or ram_wr_en(i*4+2) or ram_wr_en(i*4+3) ;
end generate BRAM_gen_12bc1;
rd_sof_eof <= rd_sof_eof_p(conv_integer(bram_rd_sel)/4);
end generate BRAM_gen_12bc;
end generate BRAM_gen_12b;
end generate BRAM_gen_12;
-------------------------------------------------------------------------------
BRAM_gen_13: if WR_DWIDTH + RD_DWIDTH = 192 generate
BRAM_gen_13a: if RD_DWIDTH = 64 generate -- rd is 64-bit, wr is 128-bit wide
BRAM_gen_13aa: for i in 0 to BRAM_MACRO_NUM-1 generate
bram13a: BRAM_S72_S144 port map (
ADDRA => rd_addr_full(9 downto 0),
ADDRB => wr_addr_full(8 downto 0),
DIA => gnd_bus(63 downto 0),DIPA => gnd_bus(7 downto 0),
DIB => wr_data,
DIPB => wr_sof_eof(15 downto 0) ,
WEA => gnd, WEB => pwr,
CLKA => rd_clk, CLKB => wr_clk,
SSRA => gnd, SSRB => gnd,
ENA => rd_allow_minor, ENB => ram_wr_en(i),
DOA => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPA => c_rd_ctrl_grp(8*(i+1)-1 downto 8*i));
rd_ctrl_p(i) <= c_rd_ctrl_grp(8*(i+1) -1 downto 8*i);
end generate BRAM_gen_13aa;
c_rd_temp <= rd_ctrl_p(conv_integer(bram_rd_sel));
rd_sof_eof <= c_rd_temp(1 downto 0);
rd_ctrl_rem <= c_rd_temp(4 downto 2);
end generate BRAM_gen_13a;
-------------------------------------------------------------------------------
BRAM_gen_13b: if RD_DWIDTH = 128 generate -- rd is 128-bit, wr is 64-bit wide
BRAM_gen_13bb: for i in 0 to BRAM_MACRO_NUM-1 generate
bram13b: BRAM_S72_S144 port map (ADDRB => rd_addr_full(8 downto 0),
ADDRA => wr_addr_full(9 downto 0),
DIA => wr_data, DIPA => wr_sof_eof,
DIB => gnd_bus(127 downto 0), DIPB => gnd_bus(15 downto 0),
WEB => gnd, WEA => pwr,
CLKB => rd_clk, CLKA => wr_clk,
SSRA => gnd, SSRB => gnd,
ENB => rd_allow, ENA => ram_wr_en(i),
DOB => rd_data_grp(RD_DWIDTH*(i+1)-1 downto RD_DWIDTH*i),
DOPB => c_rd_ctrl_grp(16*(i+1)-1 downto 16*i));
rd_ctrl_p(i) <= c_rd_ctrl_grp(16*(i+1) -1 downto 16*i);
end generate BRAM_gen_13bb;
rd_sof_eof <= rd_ctrl_p(conv_integer(bram_rd_sel));
end generate BRAM_gen_13b;
end generate BRAM_gen_13;
end BRAM_macro_hdl;
|
gpl-3.0
|
69ad151c108a97309af3338dfafba42b
| 0.445893 | 3.613143 | false | false | false | false |
zebarnabe/music-keyboard-vhdl
|
src/main/periodMap.vhd
| 1 | 3,773 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:37:35 10/24/2015
-- Design Name:
-- Module Name: periodMap - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity periodMap is
Port ( clk : in STD_LOGIC;
key : in STD_LOGIC_VECTOR (31 downto 0);
sig : out STD_LOGIC_VECTOR (7 downto 0));
end periodMap;
architecture Behavioral of periodMap is
component voiceSynth
port ( clk : in STD_LOGIC;
enable : in STD_LOGIC;
period : in unsigned (15 downto 0);
sig : out STD_LOGIC_VECTOR (7 downto 0));
end component;
type vectorPeriod is array (natural range <>) of unsigned(15 downto 0);
constant keyPeriodMap : vectorPeriod(0 to 31) := (
to_unsigned(17896, 16),
to_unsigned(16892, 16),
to_unsigned(15944, 16),
to_unsigned(15049, 16),
to_unsigned(14204, 16),
to_unsigned(13407, 16),
to_unsigned(12654, 16),
to_unsigned(11944, 16),
to_unsigned(11274, 16),
to_unsigned(10641, 16),
to_unsigned(10044, 16),
to_unsigned(9480, 16),
to_unsigned(8948, 16),
to_unsigned(8446, 16),
to_unsigned(7972, 16),
to_unsigned(7524, 16),
to_unsigned(7102, 16),
to_unsigned(6703, 16),
to_unsigned(6327, 16),
to_unsigned(5972, 16),
to_unsigned(5637, 16),
to_unsigned(5320, 16),
to_unsigned(5022, 16),
to_unsigned(4740, 16),
to_unsigned(4474, 16),
to_unsigned(4223, 16),
to_unsigned(3986, 16),
to_unsigned(3762, 16),
to_unsigned(3551, 16),
to_unsigned(3351, 16),
to_unsigned(3163, 16),
to_unsigned(2986, 16)
);
type vectorSignal is array (natural range <>) of std_logic_vector(7 downto 0);
signal signalMap : vectorSignal(31 downto 0);
signal sigOut : std_logic_vector(12 downto 0);
begin
GEN_REG:
for I in 0 to 31 generate
voiceSynthInstance: voiceSynth port map (
clk => clk,
enable => key(I),
period => keyPeriodMap(I),
sig => signalMap(I)
);
end generate GEN_REG;
sigOut <= std_logic_vector(
resize(unsigned(signalMap(0)),13)+
resize(unsigned(signalMap(1)),13)+
resize(unsigned(signalMap(2)),13)+
resize(unsigned(signalMap(3)),13)+
resize(unsigned(signalMap(4)),13)+
resize(unsigned(signalMap(5)),13)+
resize(unsigned(signalMap(6)),13)+
resize(unsigned(signalMap(7)),13)+
resize(unsigned(signalMap(8)),13)+
resize(unsigned(signalMap(9)),13)+
resize(unsigned(signalMap(10)),13)+
resize(unsigned(signalMap(11)),13)+
resize(unsigned(signalMap(12)),13)+
resize(unsigned(signalMap(13)),13)+
resize(unsigned(signalMap(14)),13)+
resize(unsigned(signalMap(15)),13)+
resize(unsigned(signalMap(16)),13)+
resize(unsigned(signalMap(17)),13)+
resize(unsigned(signalMap(18)),13)+
resize(unsigned(signalMap(19)),13)+
resize(unsigned(signalMap(20)),13)+
resize(unsigned(signalMap(21)),13)+
resize(unsigned(signalMap(22)),13)+
resize(unsigned(signalMap(23)),13)+
resize(unsigned(signalMap(24)),13)+
resize(unsigned(signalMap(25)),13)+
resize(unsigned(signalMap(26)),13)+
resize(unsigned(signalMap(27)),13)+
resize(unsigned(signalMap(28)),13)+
resize(unsigned(signalMap(29)),13)+
resize(unsigned(signalMap(30)),13)+
resize(unsigned(signalMap(31)),13));
sig <= sigOut(12 downto 5);
end Behavioral;
|
gpl-2.0
|
7279cc94727cac772cb8632059fbebe7
| 0.657567 | 3.344858 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/user_processes/uf_prediction.vhd
| 1 | 10,004 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : P R E D I C T I O N
--
--
-- The particles are loaded into the local RAM by the Framework.
-- The 16kb local RAM is filled with as many particles as possible.
-- There will not be any space between the particles.
--
-- The user of the framework knows how a particle is defined and
-- he defines here, how the next state is going to be predicted.
-- In the end the user has to overwrite every particle with the
-- sampled particle.
--
-- If this has be done for every particle, the finshed signal
-- has to be set to '1'. A new run of the prediction will be
-- started if new particles are loaded to the local RAM and
-- the signal particles_loaded is equal to '1'.
--
-- Because this function depends on parameter, additional
-- parameter can be given to the framework, which copies
-- them into the first 128 byte of the local RAM.
--
------------------------------------------------------------------------------------
entity uf_prediction is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
init : in std_logic;
enable : in std_logic;
-- start signal for the prediction user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- size of one particle
particle_size : in integer;
-- if every particle is sampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_prediction;
architecture Behavioral of uf_prediction is
component pseudo_random is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
load : in STD_LOGIC;
seed : in STD_LOGIC_VECTOR(31 downto 0);
pseudoR : out STD_LOGIC_VECTOR(31 downto 0));
end component;
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- handshake signals for processes
--signal load_parameter_en : std_logic := '0';
--signal load_parameter_done : std_logic := '0';
signal sample_en : std_logic := '0';
signal sample_done : std_logic := '0';
-- burst ram interface access for processes
signal o_RAMAddr_sample : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
--signal o_RAMAddr_load_param : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMWE_sample : std_logic := '0';
-- states
type t_state is (
initialize,
--load_parameter,
sample,
finish
);
-- current state
signal state : t_state := initialize;
-- needed for pseudo random entity
signal enable_pseudo : std_logic := '0';
signal load : std_logic := '0';
signal seed : std_logic_vector(31 downto 0) := (others => '0');
signal pseudoR : std_logic_vector(31 downto 0) := (others => '0');
-- signals needed for beat tracking
signal interval_min : std_logic_vector(0 to 31) := (others => '0');
signal initial_phase : std_logic_vector(0 to 31) := (others => '0');
signal next_beat : std_logic_vector(0 to 31) := (others => '0');
signal last_beat : std_logic_vector(0 to 31) := (others => '0');
signal tempo : std_logic_vector(0 to 31) := (others => '0');
signal noise1 : std_logic_vector(0 to 3) := (others => '0');
signal noise2 : std_logic_vector(0 to 5) := (others => '0');
signal the_step : integer := 0;
begin
pseudo_r : pseudo_random
port map (reset=>reset, clk=>clk, enable=>enable_pseudo, load=>load, seed=>seed, pseudoR=>pseudoR);
-- burst ram interface
o_RAMClk <= clk;
o_RAMWE <= o_RAMWE_sample when sample_en = '1' else '0';
o_RAMAddr <= o_RAMAddr_sample when sample_en = '1' else (others=>'0');
---- loads parameter needed by sampling process
--load_parameter_proc : process(clk, reset, load_parameter_en)
-- variable step : natural range 0 to 3;
--begin
--
-- if reset = '1' or load_parameter_en = '0' then
-- load_parameter_done <= '0';
-- step := 0;
-- elsif rising_edge(clk) then
-- case step is
--
-- when 0 =>
-- --! load parameter values
-- o_RAMAddr_load_param <= (others=>'0');
-- step := step + 1;
--
-- when 1 =>
-- --! wait one cycle
-- step := step + 1;
--
-- when 2 =>
-- --! load interval min (first 32 bits)
-- interval_min_addr(0 to 31) <= i_RAMData(0 to 31);
-- step := step + 1;
--
-- when 3 =>
-- load_parameter_done <= '1';
-- end case;
-- end if;
--end process;
-- samples particles
sample_proc : process(clk, reset, sample_en)
variable step : natural range 0 to 17;
variable num : integer;
variable particle_address : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
if reset = '1' or sample_en = '0' then
sample_done <= '0';
o_RAMWE_sample <= '0';
o_RAMAddr_sample <= (others=>'0');
o_RAMData <= (others=>'0');
step := 0;
the_step <= 0;
elsif rising_edge(clk) then
the_step <= step;
case step is
when 0 =>
--! how many particles need to be read?
num := number_of_particles;
particle_address := (others=>'0');
step := step + 1;
when 1 =>
--! calcualte 1st particle address
particle_address := particle_address + 32; -- 32*4 bytes for parameter
step := step + 1;
when 2 =>
--! no more particles to process?
if (num <= 0) then
-- finished sampling
step := 17;
else
-- more particles to process
num := num - 1;
step := step + 1;
end if;
when 3 =>
--! read particle data
o_RAMAddr_sample <= particle_address + 2;
step := step + 1;
when 4 =>
--! wait one cycle
o_RAMAddr_sample <= particle_address + 4;
step := step + 1;
when 5 =>
--! read next beat position
o_RAMAddr_sample <= particle_address + 5;
next_beat <= i_RAMData;
step := step + 1;
when 6 =>
--! read tempo
o_RAMAddr_sample <= particle_address + 6;
tempo <= i_RAMData;
step := step + 1;
when 7 =>
--! read interval_min
initial_phase <= i_RAMData;
step := step + 1;
when 8 =>
--! read interval_min
interval_min <= i_RAMData;
if (initial_phase > 0) then
-- no samplig
step := 17;
else
step := step + 1;
end if;
when 9 =>
--! sampling needed (only if interval_min > next beat position)
if (interval_min > next_beat) then
-- sampling needed
step := step + 1;
else
-- no (more) sampling needed
step := step + 4; -- write value
end if;
when 10 =>
--! update last beat
last_beat(0 to 31) <= next_beat(0 to 31);
noise1 (0 to 3) <= pseudoR(3)&pseudoR(2)&pseudoR(1)&pseudoR(0);
step := step + 1;
when 11 =>
--! sample next beat
next_beat(0 to 31) <= std_logic_vector(unsigned(next_beat) + unsigned(tempo));
if (pseudoR(4)='1') then
tempo(0 to 31) <= std_logic_vector(unsigned(tempo) + unsigned(noise1));
else
tempo(0 to 31) <= std_logic_vector(unsigned(tempo) - unsigned(noise1));
end if;
noise2 (0 to 5) <= pseudoR(5)&pseudoR(4)&pseudoR(3)&pseudoR(2)&pseudoR(1)&pseudoR(0);
step := step + 1;
when 12 =>
--! add some noise
if (pseudoR(6)='1') then
next_beat(0 to 31) <= std_logic_vector(unsigned(next_beat) + unsigned(noise2));
else
next_beat(0 to 31) <= std_logic_vector(unsigned(next_beat) - unsigned(noise2));
end if;
step := step - 3;
when 13 =>
--! write sampled values: next beat
o_RAMWE_sample <= '1';
o_RAMAddr_sample <= particle_address + 2;
o_RAMData <= next_beat;
step := step + 1;
when 14 =>
--! write sampled values: last beat
o_RAMWE_sample <= '1';
o_RAMAddr_sample <= particle_address + 3;
o_RAMData <= last_beat;
step := step + 1;
when 15 =>
--! write sampled values: tempo
o_RAMWE_sample <= '1';
o_RAMAddr_sample <= particle_address + 4;
o_RAMData <= tempo;
step := step + 1;
when 16 =>
--! finished writing
o_RAMWE_sample <= '0';
particle_address := particle_address + particle_size;
step := 2;
when 17 =>
o_RAMWE_sample <= '0';
sample_done <= '1';
end case;
end if;
end process;
main_proc : process(clk, reset)
begin
if (reset = '1') then
seed <= X"7A3E0426";
load <= '1';
enable_pseudo <= '1';
sample_en <= '0';
--load_parameter_en <= '0';
finished <= '0';
state <= initialize;
elsif rising_edge(clk) then
enable_pseudo <= enable;
load <= '0';
if (init = '1') then
finished <= '0';
sample_en <= '0';
--load_parameter_en <= '0';
state <= initialize;
elsif enable = '1' then
case state is
--! (1) initialize
when initialize =>
finished <= '0';
sample_en <= '0';
if (particles_loaded = '1') then
--load_parameter_en <= '1';
--state <= load_parameter;
sample_en <= '1';
state <= sample;
end if;
-- --! (2) load parameter
-- when load_parameter =>
-- if (load_parameter_done = '1') then
-- load_parameter_en <= '0';
-- sample_en <= '1';
-- state <= sample;
-- end if;
--! (3) sample data
when sample =>
finished <= '0';
if (sample_done = '1') then
sample_en <= '0';
state <= finish;
end if;
--! (4) sampling finished
when finish =>
finished <= '1';
if (particles_loaded = '1') then
sample_en <= '1';
state <= sample;
end if;
when others =>
state <= initialize;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
6a45d0e79bb40300fe6d15648e628342
| 0.57547 | 3.131142 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/sim/FrameBuffer.vhd
| 1 | 13,039 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY FrameBuffer IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FrameBuffer;
ARCHITECTURE FrameBuffer_arch OF FrameBuffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FrameBuffer_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "FrameBuffer.mif",
C_INIT_FILE => "FrameBuffer.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 10240,
C_READ_DEPTH_A => 10240,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 10240,
C_READ_DEPTH_B => 10240,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.61856 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END FrameBuffer_arch;
|
mit
|
33dddcf2b4022562b79ab2ed83034b32
| 0.613467 | 3.241114 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/framework/importance.vhd
| 1 | 29,395 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity importance is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end importance;
architecture Behavioral of importance is
component uf_likelihood is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
init : in std_logic;
enable : in std_logic;
observation_loaded : in std_logic;
ref_data_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
observation_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
observation_size : in integer;
finished : out std_logic;
likelihood_value : out integer
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type state_t is ( STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_NEEDED_READS_1,
STATE_NEEDED_READS_2,
STATE_READ_OBSERVATION_ADDRESS,
STATE_READ_REF_DATA_ADDRESS,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_LOAD_OBSERVATION,
STATE_LOAD_BURST_DECISION,
STATE_LOAD_BURST,
STATE_LOAD_READ_DECISION,
STATE_LOAD_READ,
STATE_WRITE_TO_RAM,
STATE_LOAD_OBSERVATION_DATA_DECISION,
STATE_LOAD_OBSERVATION_DATA_DECISION_2,
STATE_LOAD_OBSERVATION_DATA_DECISION_3,
STATE_LIKELIHOOD,
STATE_LIKELIHOOD_DONE,
STATE_WRITE_LIKELIHOOD,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2
);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07",
X"08",
X"09",
X"0A",
X"0B",
X"0C",
X"0D",
X"0E",
X"0F",
X"10",
X"11",
X"12",
X"13",
X"14",
X"15",
X"16",
X"17",
X"18",
X"19",
X"1A",
X"1B",
X"1C",
X"1D",
X"1E",
X"1F",
X"20",
X"21"
);
constant decode : decode_t := (STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_NEEDED_READS_1,
STATE_NEEDED_READS_2,
STATE_READ_OBSERVATION_ADDRESS,
STATE_READ_REF_DATA_ADDRESS,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_LOAD_OBSERVATION,
STATE_LOAD_BURST_DECISION,
STATE_LOAD_BURST,
STATE_LOAD_READ_DECISION,
STATE_LOAD_READ,
STATE_WRITE_TO_RAM,
STATE_LOAD_OBSERVATION_DATA_DECISION,
STATE_LOAD_OBSERVATION_DATA_DECISION_2,
STATE_LOAD_OBSERVATION_DATA_DECISION_3,
STATE_LIKELIHOOD,
STATE_LIKELIHOOD_DONE,
STATE_WRITE_LIKELIHOOD,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2
);
-- current state
signal state : state_t := STATE_CHECK;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- reference data
signal reference_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles / observations (set by message box, default = 100)
signal N : integer := 10;
-- number of observations
signal remaining_observations : integer := 10;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 4;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal offset : integer := 0;
-- start observation index
--signal start_observation_index : integer := 0;
-- number of reads
signal number_of_reads : integer := 0;
-- number of needed reads to be remembered
signal number_of_reads_remember : integer := 0;
-- set to '1', if after the first run the reference data + the first observation is loaded
signal second_run : std_logic := '0';
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 10;
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- number of observations, where importance has to be calculated (max = block size)
signal number_of_calculations : integer := 10;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
--signal time_start : integer := 0;
--signal time_stop : integer := 0;
--signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the likelihood user process
signal observation_loaded : std_logic := '0';
-- size of one observation
signal observation_size_2 : integer := 0;
-- reference data address
signal ref_data_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- observation data address
signal observation_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- if the likelihood value is calculated, this signal is set to '1'
signal finished : std_logic := '0';
-- likelihood value
signal likelihood_value : integer := 128;
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrLikelihood : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrImportance : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWELikelihood : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEImportance : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataLikelihood : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataImportance : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_likelihood
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrLikelihood, o_RAMData=>o_RAMDataLikelihood,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWELikelihood, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, observation_loaded=>observation_loaded,
ref_data_address=>ref_data_address, observation_address=>observation_address,
observation_size=>observation_size_2, finished=>finished, likelihood_value=>likelihood_value);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrLikelihood(0 to C_BURST_AWIDTH-2) & not o_RAMAddrLikelihood(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrImportance(0 to C_BURST_AWIDTH-2) & not o_RAMAddrImportance(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWELikelihood when enable = '1' else o_RAMWEImportance;
-- switch 3: output ram data
o_RAMData <= o_RAMDataLikelihood when enable = '1' else o_RAMDataImportance;
observation_size_2 <= observation_size / 4;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Importance:
--
-- 1) Information are set (like particle array address and
-- particle and observation size)
--
--
-- 2) Waiting for Message m (Start of a Importance run)
-- Calculate likelihood values for particles of m-th particle block
-- i = 0
--
--
-- 3) Calculate if block size particles should be calculated
-- or less (iff last particle block)
--
--
-- 4) The Reference Histogram ist copied to the local ram
--
--
-- 5) If there is still a observation left (i < counter) then
-- go to step 6;
-- else
-- go to step 9;
-- end if
--
--
-- 6) The observation is copied into the local ram
--
--
-- 7) Start and run likelihood user process
-- i++;
--
--
-- 8) After likelihood user process is finished,
-- write back the weight to particle array
-- go to step 5;
--
--
-- 9) Send Message m (Stop of a Importance run)
-- Likelihood values for particles of m-th particle block calculated
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable resume_state_enc : reconos_state_enc_t := (others => '0');
variable preempted : boolean;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"11111111");
resume_state_enc := (others => '0');
preempted := false;
done := false;
success := false;
state <= STATE_CHECK;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
-- set flag, that thread was preempted
preempted := true;
state <= decode(to_integer(unsigned(resume_state_enc)));
else
state <= STATE_INIT;
end if;
end if;
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK (1 of 6) !!!
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
if done then
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
observation_loaded <= '0';
state <= STATE_READ_PARTICLE_ADDRESS;
-- CHANGE BACK (2 of 6) !!!
--state <= STATE_NEEDED_BURSTS;
end if;
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
temp4 <= observation_size / 4;
state <= STATE_NEEDED_BURSTS_2;
when STATE_NEEDED_BURSTS_2 =>
--! calculate needed bursts
observation_address <= local_ram_address_if + temp4;
state <= STATE_NEEDED_READS_1;
when STATE_NEEDED_READS_1 =>
--! calculate number of reads (1 of 2)
-- change this back
-- old
--number_of_reads_remember <= observation_size mod 128;
-- changed (new) [2 lines]
number_of_reads_remember <= observation_size;
number_of_bursts_remember <= 0;
state <= STATE_NEEDED_READS_2;
when STATE_NEEDED_READS_2 =>
--! calculate number of reads (2 of 2)
number_of_reads_remember <= number_of_reads_remember / 4;
state <= STATE_READ_OBSERVATION_ADDRESS;
when STATE_READ_OBSERVATION_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_REF_DATA_ADDRESS;
end if;
-- -- CHANGE BACK (3 of 6) !!!
-- observation_array_start_address <= "00100000000000000000000000000000";
-- state <= STATE_READ_REF_DATA_ADDRESS;
when STATE_READ_REF_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, information_struct+24, reference_data_address);
if done then
if preempted then
preempted := false;
enable <= '0';
init <= '1';
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
-- -- CHANGE BACK (4 of 6) !!!
-- -- ref data address = 10000040
-- reference_data_address <= "00010000000000000000000001000000";
-- state <= STATE_WAIT_FOR_MESSAGE;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
reconos_flag_yield(o_osif, i_osif, encode(STATE_WAIT_FOR_MESSAGE));
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
observation_loaded <= '0';
enable <= '0';
init <= '1';
second_run <= '0';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
if preempted then
state <= STATE_INIT;
else
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
temp <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
number_of_calculations <= block_size;
else
number_of_calculations <= remaining_observations;
end if;
state <= STATE_LOAD_OBSERVATION;
when STATE_LOAD_OBSERVATION =>
--! prepare to load an observation to local ram
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
load_address <= reference_data_address;
state <= STATE_LOAD_BURST_DECISION;
when STATE_LOAD_BURST_DECISION =>
--! decision if a burst is needed
if (number_of_bursts > 0) then
state <= STATE_LOAD_BURST;
number_of_bursts <= number_of_bursts - 1;
else
state <= STATE_LOAD_READ_DECISION;
end if;
when STATE_LOAD_BURST =>
--! load bursts of observation
reconos_read_burst(done, o_osif, i_osif, local_ram_address, load_address);
if done then
local_ram_address <= local_ram_address + 128;
load_address <= load_address + 128;
local_ram_address_if <= local_ram_address_if + 32;
state <= STATE_LOAD_BURST_DECISION;
end if;
when STATE_LOAD_READ_DECISION =>
--! decision if a read into local ram is needed
if (number_of_reads > 0) then
state <= STATE_LOAD_READ;
number_of_reads <= number_of_reads - 1;
elsif (second_run = '1') then
state <= STATE_LIKELIHOOD;
else
second_run <= '1';
state <= STATE_LOAD_OBSERVATION_DATA_DECISION;
end if;
when STATE_LOAD_READ =>
--! load reads of observation
reconos_read_s(done, o_osif, i_osif, load_address, ram_data);
if done then
load_address <= load_address + 4;
state <= STATE_WRITE_TO_RAM;
end if;
when STATE_WRITE_TO_RAM =>
--! write value to ram
o_RAMWEImportance<= '1';
o_RAMAddrImportance <= local_ram_address_if;
o_RAMDataImportance <= ram_data;
local_ram_address_if <= local_ram_address_if + 1;
state <= STATE_LOAD_READ_DECISION;
when STATE_LOAD_OBSERVATION_DATA_DECISION =>
--! first step of calculation of observation address
observation_offset <= number_of_calculations - remaining_observations;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION_2;
when STATE_LOAD_OBSERVATION_DATA_DECISION_2 =>
--! decide, if there is another observation to be handled, else post semaphore
o_RAMWEImportance <= '0';
local_ram_address <= local_ram_start_address + observation_size;
local_ram_address_if <= observation_address;
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
offset <= observation_offset * observation_size ;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION_3;
when STATE_LOAD_OBSERVATION_DATA_DECISION_3 =>
--! decide, if there is another observation to be handled, else post semaphore
load_address <= observation_array_address + offset;
if (remaining_observations > 0) then
state <= STATE_LOAD_BURST_DECISION;
else
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
when STATE_LIKELIHOOD =>
--! start and run likelihood user process
init <= '0';
enable <= '1';
observation_loaded <= '1';
state <= STATE_LIKELIHOOD_DONE;
when STATE_LIKELIHOOD_DONE =>
--! wait until the likelihood user process is finished
observation_loaded <= '0';
if (finished = '1') then
enable <= '0';
init <= '1';
state <= STATE_WRITE_LIKELIHOOD;
remaining_observations <= remaining_observations - 1;
end if;
when STATE_WRITE_LIKELIHOOD =>
--! write likelihood value into the particle array
reconos_write(done, o_osif, i_osif, particle_array_address, STD_LOGIC_VECTOR(TO_SIGNED(likelihood_value, C_OSIF_DATA_WIDTH)));
if done and success then
particle_array_address <= particle_array_address + particle_size;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION;
end if;
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
observation_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
-- when STATE_SEND_MEASUREMENT_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
--
-- state <= STATE_WAIT_FOR_MESSAGE;
-- end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
653eef021b3bb8c15c182f9ad9c39290
| 0.540704 | 4.133736 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/rteasy_functions.vhd
| 3 | 2,227 |
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector;
END rteasy_functions;
PACKAGE BODY rteasy_functions IS
-- signed relative comparison functions
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean IS
BEGIN
IF a(sign_index) = b(sign_index) THEN
RETURN a < b;
ELSE
RETURN a(sign_index) = '1';
END IF;
END bool_signed_lt;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_lt;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_le;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_gt;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ge;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_eq;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ne;
END rteasy_functions;
|
bsd-3-clause
|
16a5d097c8eaa9d8a88284ca49bf6a35
| 0.66053 | 3.190544 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/imports/Downloads/ps2_keyboard.vhd
| 2 | 4,180 |
--------------------------------------------------------------------------------
--
-- filename: ps2_keyboard.vhd
-- dependencies: debounce.vhd
-- design software: quartus ii 32-bit version 12.1 build 177 sj full version
--
-- hdl code is provided "as is." digi-key expressly disclaims any
-- warranty of any kind, whether express or implied, including but not
-- limited to, the implied warranties of merchantability, fitness for a
-- particular purpose, or non-infringement. in no event shall digi-key
-- be liable for any incidental, special, indirect or consequential
-- damages, lost profits or lost data, harm to your equipment, cost of
-- procurement of substitute goods, technology or services, any claims
-- by third parties (including but not limited to any defense thereof),
-- any claims for indemnity or contribution, or other similar costs.
--
-- version history
-- version 1.0 11/25/2013 scott larson
-- initial public release
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ps2_keyboard is
generic
(
clk_freq : integer := 100_000_000 --system clock frequency in hz
);
port(
clk : in std_logic; --system clock
ps2_clk : in std_logic; --clock signal from ps/2 keyboard
ps2_data : in std_logic; --data signal from ps/2 keyboard
ps2_code_new : out std_logic; --flag that new ps/2 code is available on ps2_code bus
ps2_code : out std_logic_vector(7 downto 0)); --code received from ps/2
end ps2_keyboard;
architecture logic of ps2_keyboard is
signal ps2_clk_int : std_logic; --debounced clock signal from ps/2 keyboard
signal ps2_data_int : std_logic; --debounced data signal from ps/2 keyboard
signal ps2_word : std_logic_vector(10 downto 0); --stores the ps2 data word
signal error : std_logic; --validate parity, start, and stop bits
signal count_idle : integer range 0 to clk_freq/18_000; --counter to determine ps/2 is idle
begin
--synchronizer flip-flops
process(clk)
begin
if(clk'event and clk = '1') then --rising edge of system clock
ps2_clk_int <= ps2_clk; --synchronize ps/2 clock signal
ps2_data_int <= ps2_data; --synchronize ps/2 data signal
end if;
end process;
--input ps2 data
process(ps2_clk_int)
begin
if(ps2_clk_int'event and ps2_clk_int = '0') then --falling edge of ps2 clock
ps2_word <= ps2_data_int & ps2_word(10 downto 1); --shift in ps2 data bit
end if;
end process;
--verify that parity, start, and stop bits are all correct
error <= not (not ps2_word(0) and ps2_word(10) and (ps2_word(9) xor ps2_word(8) xor
ps2_word(7) xor ps2_word(6) xor ps2_word(5) xor ps2_word(4) xor ps2_word(3) xor
ps2_word(2) xor ps2_word(1)));
--determine if ps2 port is idle (i.e. last transaction is finished) and output result
process(clk)
begin
if(clk'event and clk = '1') then --rising edge of system clock
if(ps2_clk_int = '0') then --low ps2 clock, ps/2 is active
count_idle <= 0; --reset idle counter
elsif(count_idle /= clk_freq/18_000) then --ps2 clock has been high less than a half clock period (<55us)
count_idle <= count_idle + 1; --continue counting
end if;
if(count_idle = clk_freq/18_000 and error = '0') then --idle threshold reached and no errors detected
ps2_code_new <= '1'; --set flag that new ps/2 code is available
ps2_code <= ps2_word(8 downto 1); --output new ps/2 code
else --ps/2 port active or error detected
ps2_code_new <= '0'; --set flag that ps/2 transaction is in progress
end if;
end if;
end process;
end logic;
|
mit
|
01bfeeb85c38ecde940389a391d2daf6
| 0.574163 | 3.859649 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_sync_ffs.vhd
| 1 | 3,928 |
-------------------------------------------------------------------------------
-- Title : Synchronizer chain
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : gc_sync_ffs.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-06-14
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Synchronizer chain and edge detector.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-14 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end gc_sync_ffs;
architecture behavioral of gc_sync_ffs is
signal sync0, sync1, sync2 : std_logic;
attribute shreg_extract : string;
attribute shreg_extract of sync0 : signal is "no";
attribute shreg_extract of sync1 : signal is "no";
attribute shreg_extract of sync2 : signal is "no";
attribute keep : string;
attribute keep of sync0 : signal is "true";
attribute keep of sync1 : signal is "true";
begin
sync_posedge : if (g_sync_edge = "positive") generate
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
sync0 <= '0';
sync1 <= '0';
sync2 <= '0';
synced_o <= '0';
npulse_o <= '0';
ppulse_o <= '0';
elsif rising_edge(clk_i) then
sync0 <= data_i;
sync1 <= sync0;
sync2 <= sync1;
synced_o <= sync1;
npulse_o <= sync2 and not sync1;
ppulse_o <= not sync2 and sync1;
end if;
end process;
end generate sync_posedge;
sync_negedge : if(g_sync_edge = "negative") generate
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
sync0 <= '0';
sync1 <= '0';
sync2 <= '0';
synced_o <= '0';
npulse_o <= '0';
ppulse_o <= '0';
elsif falling_edge(clk_i) then
sync0 <= data_i;
sync1 <= sync0;
sync2 <= sync1;
synced_o <= sync1;
npulse_o <= sync2 and not sync1;
ppulse_o <= not sync2 and sync1;
end if;
end process;
end generate sync_negedge;
end behavioral;
|
lgpl-3.0
|
ecd78fec2204facf32f2d3f6edeb5744
| 0.505346 | 4.045314 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_tlb_v2_01_a/hdl/vhdl/match_encoder.vhd
| 1 | 2,614 |
------------------------------------------------------------------------------
-- priority encoder with mask input and match output
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity match_encoder is
port
(
i_multi_match : in std_logic_vector(31 downto 0);
i_mask : in std_logic_vector(31 downto 0);
o_match : out std_logic;
o_match_addr : out std_logic_vector(4 downto 0)
);
-- force priority encoder macro extraction:
--
-- attribute priority_extract: string;
-- attribute priority_extract of match_encoder: entity is "force";
end entity;
architecture imp of match_encoder is
signal m : std_logic_vector(31 downto 0);
begin
m <= i_multi_match and i_mask;
o_match <= '0' when m = X"00000000" else '1';
o_match_addr <= "00000" when m( 0) = '1' else
"00001" when m( 1) = '1' else
"00010" when m( 2) = '1' else
"00011" when m( 3) = '1' else
"00100" when m( 4) = '1' else
"00101" when m( 5) = '1' else
"00110" when m( 6) = '1' else
"00111" when m( 7) = '1' else
"01000" when m( 8) = '1' else
"01001" when m( 9) = '1' else
"01010" when m(10) = '1' else
"01011" when m(11) = '1' else
"01100" when m(12) = '1' else
"01101" when m(13) = '1' else
"01110" when m(14) = '1' else
"01111" when m(15) = '1' else
"10000" when m(16) = '1' else
"10001" when m(17) = '1' else
"10010" when m(18) = '1' else
"10011" when m(19) = '1' else
"10100" when m(20) = '1' else
"10101" when m(21) = '1' else
"10110" when m(22) = '1' else
"10111" when m(23) = '1' else
"11000" when m(24) = '1' else
"11001" when m(25) = '1' else
"11010" when m(26) = '1' else
"11011" when m(27) = '1' else
"11100" when m(28) = '1' else
"11101" when m(29) = '1' else
"11110" when m(30) = '1' else
"11111" when m(31) = '1' else
"-----";
end architecture;
|
gpl-3.0
|
9f1196d602cbc4e96e6661af531425e3
| 0.413925 | 3.69209 | false | false | false | false |
luebbers/reconos
|
demos/mbox_demo/hw/src/threadB.vhd
| 1 | 7,992 |
--
-- threadB.vhd
-- demo thread
-- Waiting on its local read FIFO, this thread will transfer 8 kB of data
-- from the FIFO to its burst RAM, and then burst that to a main memory
-- address determined by its init data.
-- Both transactions are timed, and sent to C_MBOX_GETTIME,
-- C_MBOX_WRITETIME respectively.
--
-- NOTE: These measurements may not be entirely accurate due to the bus load
-- incurred by the OS commands.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 15.10.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity threadB is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
i_timeBase : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
);
end threadB;
architecture Behavioral of threadB is
-- timer address (FIXME: hardcoded!)
constant TIMER_ADDR : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"50004000";
-- ReconOS resources used by this thread
constant C_MB_TRANSFER : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_GETTIME : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_WRITETIME : std_logic_vector(0 to 31) := X"00000002";
-- OS synchronization state machine states (TODO: measurements!)
type t_state is (
STATE_INIT,
STATE_GETTIME_START,
STATE_TRANSFER,
STATE_GETTIME_STOP,
STATE_WRITE,
STATE_WRITETIME_STOP,
STATE_POST_GETTIME_1,
STATE_POST_GETTIME_2,
STATE_POST_WRITETIME_1,
STATE_POST_WRITETIME_2,
STATE_ERROR
);
signal state : t_state := STATE_INIT;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- timing values
signal gettime : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
signal writetime : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
signal RAMAddr_d1 : std_logic_vector(0 to C_BURST_AWIDTH-1); -- delay by one
begin
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr_d1(0 to C_BURST_AWIDTH-2) & not RAMAddr_d1(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- delay RAM address
delay_proc : process(clk)
begin
if rising_edge(clk) then
RAMAddr_d1 <= RAMAddr;
end if;
end process;
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1; -- transfer 128 bytes at once
variable trans_counter : natural range 0 to 8192/4 - 1; -- transfer 4 bytes at once
-- timing values
variable writetime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable writetime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable gettime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
variable gettime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
address <= (others => '0');
state <= STATE_INIT;
o_RAMWE <= '0';
o_RAMData <= (others => '0');
burst_counter := 0;
trans_counter := 0;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read init data
when STATE_INIT =>
reconos_get_init_data_s(done, o_osif, i_osif, address);
if done then
trans_counter := 0;
RAMAddr <= (others => '0');
state <= STATE_GETTIME_START;
end if;
-- get start time of FIFO transfer
when STATE_GETTIME_START =>
gettime_1 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, gettime_1);
-- if done then
state <= STATE_TRANSFER;
-- end if;
-- transfer data across mailbox
-- this state also hides the RAM access timing, since this is a multi-cycle
-- command, and the "data" parameter is only transferred in the second cycle.
when STATE_TRANSFER =>
o_RAMWE <= '0';
if trans_counter = 0 then
gettime_1 := i_timeBase;
end if;
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_TRANSFER, o_RAMData);
if done then
if success then
o_RAMWE <= '1';
if trans_counter = 8192/4 - 1 then
burst_counter := 0;
state <= STATE_GETTIME_STOP;
else
RAMAddr <= RAMAddr + 1; -- note that this is delayed by one clock cycle
trans_counter := trans_counter + 1;
end if;
else -- no success
state <= STATE_ERROR;
end if;
end if;
-- get stop time of FIFO transfer
when STATE_GETTIME_STOP =>
o_RAMWE <= '0';
gettime_2 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, gettime_2);
-- if done then
writetime_1 := gettime_2;
state <= STATE_WRITE;
-- end if;
-- write data from local burst RAM into main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_WRITETIME_STOP;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- get stop time of burst transfer
when STATE_WRITETIME_STOP =>
writetime_2 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, writetime_2);
-- if done then
state <= STATE_POST_GETTIME_1;
-- end if;
-- write transfer time to mailbox
when STATE_POST_GETTIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_GETTIME, gettime_1);
if done and success then
state <= STATE_POST_GETTIME_2;
end if;
when STATE_POST_GETTIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_GETTIME, gettime_2);
if done and success then
state <= STATE_POST_WRITETIME_1;
end if;
-- write write time to mailbox
when STATE_POST_WRITETIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_WRITETIME, writetime_1);
if done and success then
state <= STATE_POST_WRITETIME_2;
end if;
when STATE_POST_WRITETIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_WRITETIME, writetime_2);
if done and success then
trans_counter := 0;
RAMAddr <= (others => '0');
state <= STATE_TRANSFER;
end if;
when STATE_ERROR =>
reconos_thread_exit(o_osif, i_osif, X"00000" & RAMAddr);
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
db3f13e7728bc697bca23294b2522122
| 0.606857 | 3.502191 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/work7b/timebase.vhd
| 8 | 1,393 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter (of 25 bits) is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a count of 20000000 pulses has been accumulated
entity TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (24 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
constant DIVIDER_VALUE : std_logic_vector := x"7cf"; -- 20000000 count value, 1 second
signal RunningCounter : std_logic_vector(24 downto 0); -- this is the 25 bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= '0' & x"000000";
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = DIVIDER_VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
|
gpl-2.0
|
06eeb68e81e67e8514f97f3e3886ed74
| 0.666188 | 3.901961 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S36_S72.vhd
| 1 | 6,642 |
---------------------------------------------------------------------------
-- --
-- Module : BRAM_S36_S72.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (32 and --
-- 72) made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S36_S72 is
port (ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end entity BRAM_S36_S72;
architecture BRAM_S36_S72_arch of BRAM_S36_S72 is
component RAMB16_S18_S36
port (
ADDRA: in std_logic_vector(9 downto 0);
ADDRB: in std_logic_vector(8 downto 0);
DIA: in std_logic_vector(15 downto 0);
DIPA: in std_logic_vector(1 downto 0);
DIB: in std_logic_vector(31 downto 0);
DIPB: in std_logic_vector(3 downto 0);
WEA: in std_logic;
WEB: in std_logic;
CLKA: in std_logic;
CLKB: in std_logic;
SSRA: in std_logic;
SSRB: in std_logic;
ENA: in std_logic;
ENB: in std_logic;
DOA: OUT std_logic_vector(15 downto 0);
DOPA: OUT std_logic_vector(1 downto 0);
DOB: OUT std_logic_vector(31 downto 0);
DOPB: OUT std_logic_vector(3 downto 0));
END component;
signal doa1 : std_logic_vector (15 downto 0);
signal dob1 : std_logic_vector (31 downto 0);
signal doa2 : std_logic_vector (15 downto 0);
signal dob2 : std_logic_vector (31 downto 0);
signal dia1 : std_logic_vector (15 downto 0);
signal dib1 : std_logic_vector (31 downto 0);
signal dia2 : std_logic_vector (15 downto 0);
signal dib2 : std_logic_vector (31 downto 0);
signal dipa1: std_logic_vector (1 downto 0);
signal dipa2: std_logic_vector (1 downto 0);
signal dopa1: std_logic_vector (1 downto 0);
signal dopa2: std_logic_vector (1 downto 0);
signal dipb1: std_logic_vector (3 downto 0);
signal dipb2: std_logic_vector (3 downto 0);
signal dopb1: std_logic_vector (3 downto 0);
signal dopb2: std_logic_vector (3 downto 0);
begin
dia1(15 downto 0) <= DIA(15 downto 0);
dia2(15 downto 0) <= DIA(31 downto 16);
dib1(15 downto 0) <= DIB(15 downto 0);
dib2(15 downto 0) <= DIB(31 downto 16);
dib1(31 downto 16) <= DIB(47 downto 32);
dib2(31 downto 16) <= DIB(63 downto 48);
dipa1(1 downto 0) <= DIPA(1 downto 0);
dipa2(1 downto 0) <= DIPA(3 downto 2);
dipb1(1 downto 0) <= DIPB(1 downto 0);
dipb2(1 downto 0) <= DIPB(3 downto 2);
dipb1(3 downto 2) <= DIPB(5 downto 4);
dipb2(3 downto 2) <= DIPB(7 downto 6);
DOA(15 downto 0) <= doa1;
DOA(31 downto 16) <= doa2;
DOPA(1 downto 0) <= dopa1;
DOPA(3 downto 2) <= dopa2;
DOPB(1 downto 0) <= dopb1(1 downto 0);
DOPB(3 downto 2) <= dopb2(1 downto 0);
DOPB(5 downto 4) <= dopb1(3 downto 2);
DOPB(7 downto 6) <= dopb2(3 downto 2);
DOB(15 downto 0) <= dob1(15 downto 0);
DOB(31 downto 16) <= dob2(15 downto 0);
DOB(47 downto 32) <= dob1(31 downto 16);
DOB(63 downto 48) <= dob2(31 downto 16);
bram1: RAMB16_S18_S36
port map (
ADDRA => addra(9 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: RAMB16_S18_S36
port map (
ADDRA => addra(9 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S36_S72_arch;
|
gpl-3.0
|
d97d6a7c31f985987460115346c7f777
| 0.446703 | 4.062385 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_struct_array.vhd
| 4 | 966 |
library ieee;
use ieee.std_logic_1164.all;
entity foo_entity is
port (
i_low0: in std_logic_vector (3 downto 0);
i_high0: in std_logic_vector (3 downto 0);
i_low1: in std_logic_vector (3 downto 0);
i_high1: in std_logic_vector (3 downto 0);
o_low0: out std_logic_vector (3 downto 0);
o_high0: out std_logic_vector (3 downto 0);
o_low1: out std_logic_vector (3 downto 0);
o_high1: out std_logic_vector (3 downto 0)
);
end foo_entity;
architecture beh of foo_entity is
type word is record
high: std_logic_vector (3 downto 0);
low: std_logic_vector (3 downto 0);
end record;
type dword is array (1 downto 0) of word;
signal my_dword: dword;
begin
-- inputs
my_dword(0).low <= i_low0;
my_dword(0).high <= i_high0;
my_dword(1).low <= i_low1;
my_dword(1).high <= i_high1;
-- outputs
o_low0 <= my_dword(0).low;
o_high0 <= my_dword(0).high;
o_low1 <= my_dword(1).low;
o_high1 <= my_dword(1).high;
end beh;
|
gpl-2.0
|
dc64e5245a6932898475404368a168c1
| 0.639752 | 2.653846 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/rtl/example_top.vhd
| 1 | 33,681 |
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 2.3
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
generic (
--***************************************************************************
-- Traffic Gen related parameters
--***************************************************************************
BL_WIDTH : integer := 10;
PORT_MODE : string := "BI_MODE";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
EYE_TEST : string := "FALSE";
-- set EYE_TEST = "TRUE" to probe memory
-- signals. Traffic Generator will only
-- write to one single location and no
-- read transactions will be generated.
DATA_PATTERN : string := "DGEN_ALL";
-- For small devices, choose one only.
-- For large device, choose "DGEN_ALL"
-- "DGEN_HAMMER", "DGEN_WALKING1",
-- "DGEN_WALKING0","DGEN_ADDR","
-- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
CMD_PATTERN : string := "CGEN_ALL";
-- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- "CGEN_SEQUENTIAL", "CGEN_ALL"
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC_TEST : string := "OFF";
RANKS : integer := 1;
-- # of Ranks.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
TCQ : integer := 100;
DRAM_TYPE : string := "DDR2";
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
nCK_PER_CLK : integer := 4;
-- # of memory CKs per fabric CLK
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "EXTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
-- The 12 MSB bits of the temperature sensor transfer
-- function need to be connected to this port. This port
-- will be synchronized w.r.t. to fabric clock internally.
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;function STR_TO_INT(BM : string) return integer is
begin
if(BM = "8") then
return 8;
elsif(BM = "4") then
return 4;
else
return 0;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
constant tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
constant DATA_WIDTH : integer := 16;
constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--***************************************************************************
-- Traffic Gen related parameters (derived)
--***************************************************************************
constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant MASK_SIZE : integer := DATA_WIDTH/8;
-- Start of User Design top component
component mig_7series_0
-- generic (
-- #parameters_user_design_top_component#
-- RST_ACT_LOW : integer
-- );
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
sys_rst : in std_logic
);
end component mig_7series_0;
-- End of User Design top component
component mig_7series_v2_3_traffic_gen_top
generic (
TCQ : integer;
SIMULATION : string;
FAMILY : string;
MEM_TYPE : string;
TST_MEM_INSTR_MODE : string;
--BL_WIDTH : integer;
nCK_PER_CLK : integer;
NUM_DQ_PINS : integer;
MEM_BURST_LEN : integer;
MEM_COL_WIDTH : integer;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
MASK_SIZE : integer := 8;
DATA_MODE : std_logic_vector(3 downto 0);
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
CMDS_GAP_DELAY : std_logic_vector(5 downto 0) := "000000";
SEL_VICTIM_LINE : integer := 8;
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
EYE_TEST : string;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string
);
port (
clk : in std_logic;
rst : in std_logic;
tg_only_rst : in std_logic;
manual_clear_error : in std_logic;
memc_init_done : in std_logic;
memc_cmd_full : in std_logic;
memc_cmd_en : out std_logic;
memc_cmd_instr : out std_logic_vector(2 downto 0);
memc_cmd_bl : out std_logic_vector(5 downto 0);
memc_cmd_addr : out std_logic_vector(31 downto 0);
memc_wr_en : out std_logic;
memc_wr_end : out std_logic;
memc_wr_mask : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
memc_wr_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
memc_wr_full : in std_logic;
memc_rd_en : out std_logic;
memc_rd_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
memc_rd_empty : in std_logic;
qdr_wr_cmd_o : out std_logic;
qdr_rd_cmd_o : out std_logic;
vio_pause_traffic : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(3 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_instr_mode_value : in std_logic_vector(3 downto 0);
vio_bl_mode_value : in std_logic_vector(1 downto 0);
vio_fixed_bl_value : in std_logic_vector(9 downto 0);
vio_fixed_instr_value : in std_logic_vector(2 downto 0);
vio_data_mask_gen : in std_logic;
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(31 downto 0);
simple_data0 : in std_logic_vector(31 downto 0);
simple_data1 : in std_logic_vector(31 downto 0);
simple_data2 : in std_logic_vector(31 downto 0);
simple_data3 : in std_logic_vector(31 downto 0);
simple_data4 : in std_logic_vector(31 downto 0);
simple_data5 : in std_logic_vector(31 downto 0);
simple_data6 : in std_logic_vector(31 downto 0);
simple_data7 : in std_logic_vector(31 downto 0);
wdt_en_i : in std_logic;
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
cmp_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
dq_error_bytelane_cmp : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
error : out std_logic;
error_status : out std_logic_vector((64+(2*DATA_WIDTH))-1 downto 0);
cumlative_dq_lane_error : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
cmd_wdt_err_o : out std_logic;
wr_wdt_err_o : out std_logic;
rd_wdt_err_o : out std_logic;
mem_pattern_init_done : out std_logic
);
end component mig_7series_v2_3_traffic_gen_top;
-- Signal declarations
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_addr_i : std_logic_vector(31 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_rdy : std_logic;
signal app_rdy_i : std_logic;
signal app_rd_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rd_data_valid_i : std_logic;
signal app_wdf_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(APP_MASK_WIDTH-1 downto 0);
signal app_wdf_rdy : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal app_wdf_wren : std_logic;
signal error_status : std_logic_vector((64 + (4*PAYLOAD_WIDTH*nCK_PER_CLK))-1 downto 0);
signal cumlative_dq_lane_error : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal mem_pattern_init_done : std_logic_vector(0 downto 0);
signal modify_enable_sel : std_logic;
signal data_mode_manual_sel : std_logic_vector(2 downto 0);
signal addr_mode_manual_sel : std_logic_vector(2 downto 0);
signal cmp_data : std_logic_vector((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0);
signal cmp_data_r : std_logic_vector(63 downto 0);
signal cmp_data_valid : std_logic;
signal cmp_data_valid_r : std_logic;
signal cmp_error : std_logic;
signal tg_wr_data_counts : std_logic_vector(47 downto 0);
signal tg_rd_data_counts : std_logic_vector(47 downto 0);
signal dq_error_bytelane_cmp : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal init_calib_complete_i : std_logic;
signal tg_compare_error_i : std_logic;
signal tg_rst : std_logic;
signal po_win_tg_rst : std_logic;
signal manual_clear_error : std_logic_vector(0 downto 0);
signal clk : std_logic;
signal rst : std_logic;
signal vio_modify_enable : std_logic_vector(0 downto 0);
signal vio_data_mode_value : std_logic_vector(3 downto 0);
signal vio_pause_traffic : std_logic_vector(0 downto 0);
signal vio_addr_mode_value : std_logic_vector(2 downto 0);
signal vio_instr_mode_value : std_logic_vector(3 downto 0);
signal vio_bl_mode_value : std_logic_vector(1 downto 0);
signal vio_fixed_bl_value : std_logic_vector(BL_WIDTH-1 downto 0);
signal vio_fixed_instr_value : std_logic_vector(2 downto 0);
signal vio_data_mask_gen : std_logic_vector(0 downto 0);
signal dbg_clear_error : std_logic_vector(0 downto 0);
signal vio_tg_rst : std_logic_vector(0 downto 0);
signal dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal dbg_po_f_inc : std_logic_vector(0 downto 0);
signal dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal dbg_po_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_dec : std_logic_vector(0 downto 0);
signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
signal wdt_en_w : std_logic_vector(0 downto 0);
signal cmd_wdt_err_w : std_logic;
signal wr_wdt_err_w : std_logic;
signal rd_wdt_err_w : std_logic;
begin
--***************************************************************************
init_calib_complete <= init_calib_complete_i;
tg_compare_error <= tg_compare_error_i;
app_rdy_i <= not(app_rdy);
app_wdf_rdy_i <= not(app_wdf_rdy);
app_rd_data_valid_i <= not(app_rd_data_valid);
app_addr <= app_addr_i(ADDR_WIDTH-1 downto 0);
-- Start of User Design top instance
--***************************************************************************
-- The User design is instantiated below. The memory interface ports are
-- connected to the top-level and the application interface ports are
-- connected to the traffic generator module. This provides a reference
-- for connecting the memory controller to system.
--***************************************************************************
u_mig_7series_0 : mig_7series_0
-- generic map (
-- #parameters_mapping_user_design_top_instance#
-- RST_ACT_LOW => RST_ACT_LOW
-- )
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete_i,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
device_temp_i => device_temp_i,
sys_rst => sys_rst
);
-- End of User Design top instance
--***************************************************************************
-- The traffic generation module instantiated below drives traffic (patterns)
-- on the application interface of the memory controller
--***************************************************************************
tg_rst <= vio_tg_rst(0) or po_win_tg_rst;
u_traffic_gen_top : mig_7series_v2_3_traffic_gen_top
generic map (
TCQ => TCQ,
SIMULATION => SIMULATION,
FAMILY => "VIRTEX7",
MEM_TYPE => DRAM_TYPE,
TST_MEM_INSTR_MODE => TST_MEM_INSTR_MODE,
nCK_PER_CLK => nCK_PER_CLK,
NUM_DQ_PINS => PAYLOAD_WIDTH,
MEM_BURST_LEN => BURST_LENGTH,
MEM_COL_WIDTH => COL_WIDTH,
PORT_MODE => PORT_MODE,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => TG_ADDR_WIDTH,
DATA_WIDTH => APP_DATA_WIDTH,
BEGIN_ADDRESS => BEGIN_ADDRESS,
DATA_MODE => DATA_MODE,
END_ADDRESS => END_ADDRESS,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
CMD_WDT => CMD_WDT,
RD_WDT => RD_WDT,
WR_WDT => WR_WDT,
EYE_TEST => EYE_TEST
)
port map (
clk => clk,
rst => rst,
tg_only_rst => tg_rst,
manual_clear_error => manual_clear_error(0),
memc_init_done => init_calib_complete_i,
memc_cmd_full => app_rdy_i,
memc_cmd_en => app_en,
memc_cmd_instr => app_cmd,
memc_cmd_bl => open,
memc_cmd_addr => app_addr_i,
memc_wr_en => app_wdf_wren,
memc_wr_end => app_wdf_end,
memc_wr_mask => app_wdf_mask(((PAYLOAD_WIDTH*2*nCK_PER_CLK)/8)-1 downto 0),
memc_wr_data => app_wdf_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_wr_full => app_wdf_rdy_i,
memc_rd_en => open,
memc_rd_data => app_rd_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_rd_empty => app_rd_data_valid_i,
qdr_wr_cmd_o => open,
qdr_rd_cmd_o => open,
vio_pause_traffic => vio_pause_traffic(0),
vio_modify_enable => vio_modify_enable(0),
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_instr_mode_value => vio_instr_mode_value,
vio_bl_mode_value => vio_bl_mode_value,
vio_fixed_bl_value => vio_fixed_bl_value,
vio_fixed_instr_value=> vio_fixed_instr_value,
vio_data_mask_gen => vio_data_mask_gen(0),
fixed_addr_i => all_zeros1,
fixed_data_i => all_zeros1,
simple_data0 => all_zeros1,
simple_data1 => all_zeros1,
simple_data2 => all_zeros1,
simple_data3 => all_zeros1,
simple_data4 => all_zeros1,
simple_data5 => all_zeros1,
simple_data6 => all_zeros1,
simple_data7 => all_zeros1,
wdt_en_i => wdt_en_w(0),
bram_cmd_i => all_zeros2,
bram_valid_i => '0',
bram_rdy_o => open,
cmp_data => cmp_data,
cmp_data_valid => cmp_data_valid,
cmp_error => cmp_error,
wr_data_counts => tg_wr_data_counts,
rd_data_counts => tg_rd_data_counts,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
error => tg_compare_error_i,
error_status => error_status,
cumlative_dq_lane_error => cumlative_dq_lane_error,
cmd_wdt_err_o => cmd_wdt_err_w,
wr_wdt_err_o => wr_wdt_err_w,
rd_wdt_err_o => rd_wdt_err_w,
mem_pattern_init_done => mem_pattern_init_done(0)
);
--*****************************************************************
-- Default values are assigned to the debug inputs of the traffic
-- generator
--*****************************************************************
vio_modify_enable(0) <= '0';
vio_data_mode_value <= "0010";
vio_addr_mode_value <= "011";
vio_instr_mode_value <= "0010";
vio_bl_mode_value <= "10";
vio_fixed_bl_value <= "0000010000";
vio_data_mask_gen(0) <= '0';
vio_pause_traffic(0) <= '0';
vio_fixed_instr_value <= "001";
dbg_clear_error(0) <= '0';
po_win_tg_rst <= '0';
vio_tg_rst(0) <= '0';
wdt_en_w(0) <= '1';
dbg_sel_pi_incdec(0) <= '0';
dbg_sel_po_incdec(0) <= '0';
dbg_pi_f_inc(0) <= '0';
dbg_pi_f_dec(0) <= '0';
dbg_po_f_inc(0) <= '0';
dbg_po_f_dec(0) <= '0';
dbg_po_f_stg23_sel(0) <= '0';
end architecture arch_example_top;
|
gpl-3.0
|
feadffdbfe97dc698f59a22ccf8a016c
| 0.462219 | 4.076122 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.